4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, MemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void gen_a64_set_pc_im(uint64_t val
)
156 tcg_gen_movi_i64(cpu_pc
, val
);
160 * Handle Top Byte Ignore (TBI) bits.
162 * If address tagging is enabled via the TCR TBI bits:
163 * + for EL2 and EL3 there is only one TBI bit, and if it is set
164 * then the address is zero-extended, clearing bits [63:56]
165 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
166 * and TBI1 controls addressses with bit 55 == 1.
167 * If the appropriate TBI bit is set for the address then
168 * the address is sign-extended from bit 55 into bits [63:56]
170 * Here We have concatenated TBI{1,0} into tbi.
172 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
173 TCGv_i64 src
, int tbi
)
176 /* Load unmodified address */
177 tcg_gen_mov_i64(dst
, src
);
178 } else if (s
->current_el
>= 2) {
179 /* FIXME: ARMv8.1-VHE S2 translation regime. */
180 /* Force tag byte to all zero */
181 tcg_gen_extract_i64(dst
, src
, 0, 56);
183 /* Sign-extend from bit 55. */
184 tcg_gen_sextract_i64(dst
, src
, 0, 56);
187 TCGv_i64 tcg_zero
= tcg_const_i64(0);
190 * The two TBI bits differ.
191 * If tbi0, then !tbi1: only use the extension if positive.
192 * if !tbi0, then tbi1: only use the extension if negative.
194 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
195 dst
, dst
, tcg_zero
, dst
, src
);
196 tcg_temp_free_i64(tcg_zero
);
201 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
204 * If address tagging is enabled for instructions via the TCR TBI bits,
205 * then loading an address into the PC will clear out any tag.
207 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
211 * Return a "clean" address for ADDR according to TBID.
212 * This is always a fresh temporary, as we need to be able to
213 * increment this independently of a dirty write-back address.
215 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
217 TCGv_i64 clean
= new_tmp_a64(s
);
218 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
222 typedef struct DisasCompare64
{
227 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
231 arm_test_cc(&c32
, cc
);
233 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
234 * properly. The NE/EQ comparisons are also fine with this choice. */
235 c64
->cond
= c32
.cond
;
236 c64
->value
= tcg_temp_new_i64();
237 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
242 static void a64_free_cc(DisasCompare64
*c64
)
244 tcg_temp_free_i64(c64
->value
);
247 static void gen_exception_internal(int excp
)
249 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
251 assert(excp_is_internal(excp
));
252 gen_helper_exception_internal(cpu_env
, tcg_excp
);
253 tcg_temp_free_i32(tcg_excp
);
256 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
258 gen_a64_set_pc_im(pc
);
259 gen_exception_internal(excp
);
260 s
->base
.is_jmp
= DISAS_NORETURN
;
263 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
264 uint32_t syndrome
, uint32_t target_el
)
266 gen_a64_set_pc_im(pc
);
267 gen_exception(excp
, syndrome
, target_el
);
268 s
->base
.is_jmp
= DISAS_NORETURN
;
271 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
275 gen_a64_set_pc_im(s
->pc_curr
);
276 tcg_syn
= tcg_const_i32(syndrome
);
277 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
278 tcg_temp_free_i32(tcg_syn
);
279 s
->base
.is_jmp
= DISAS_NORETURN
;
282 static void gen_step_complete_exception(DisasContext
*s
)
284 /* We just completed step of an insn. Move from Active-not-pending
285 * to Active-pending, and then also take the swstep exception.
286 * This corresponds to making the (IMPDEF) choice to prioritize
287 * swstep exceptions over asynchronous exceptions taken to an exception
288 * level where debug is disabled. This choice has the advantage that
289 * we do not need to maintain internal state corresponding to the
290 * ISV/EX syndrome bits between completion of the step and generation
291 * of the exception, and our syndrome information is always correct.
294 gen_swstep_exception(s
, 1, s
->is_ldex
);
295 s
->base
.is_jmp
= DISAS_NORETURN
;
298 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
300 /* No direct tb linking with singlestep (either QEMU's or the ARM
301 * debug architecture kind) or deterministic io
303 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
304 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
308 #ifndef CONFIG_USER_ONLY
309 /* Only link tbs from inside the same guest page */
310 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
318 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
320 TranslationBlock
*tb
;
323 if (use_goto_tb(s
, n
, dest
)) {
325 gen_a64_set_pc_im(dest
);
326 tcg_gen_exit_tb(tb
, n
);
327 s
->base
.is_jmp
= DISAS_NORETURN
;
329 gen_a64_set_pc_im(dest
);
331 gen_step_complete_exception(s
);
332 } else if (s
->base
.singlestep_enabled
) {
333 gen_exception_internal(EXCP_DEBUG
);
335 tcg_gen_lookup_and_goto_ptr();
336 s
->base
.is_jmp
= DISAS_NORETURN
;
341 static void init_tmp_a64_array(DisasContext
*s
)
343 #ifdef CONFIG_DEBUG_TCG
344 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
346 s
->tmp_a64_count
= 0;
349 static void free_tmp_a64(DisasContext
*s
)
352 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
353 tcg_temp_free_i64(s
->tmp_a64
[i
]);
355 init_tmp_a64_array(s
);
358 TCGv_i64
new_tmp_a64(DisasContext
*s
)
360 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
361 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
364 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
366 TCGv_i64 t
= new_tmp_a64(s
);
367 tcg_gen_movi_i64(t
, 0);
372 * Register access functions
374 * These functions are used for directly accessing a register in where
375 * changes to the final register value are likely to be made. If you
376 * need to use a register for temporary calculation (e.g. index type
377 * operations) use the read_* form.
379 * B1.2.1 Register mappings
381 * In instruction register encoding 31 can refer to ZR (zero register) or
382 * the SP (stack pointer) depending on context. In QEMU's case we map SP
383 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
384 * This is the point of the _sp forms.
386 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
389 return new_tmp_a64_zero(s
);
395 /* register access for when 31 == SP */
396 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
401 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
402 * representing the register contents. This TCGv is an auto-freed
403 * temporary so it need not be explicitly freed, and may be modified.
405 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
407 TCGv_i64 v
= new_tmp_a64(s
);
410 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
412 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
415 tcg_gen_movi_i64(v
, 0);
420 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
422 TCGv_i64 v
= new_tmp_a64(s
);
424 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
426 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
431 /* Return the offset into CPUARMState of a slice (from
432 * the least significant end) of FP register Qn (ie
434 * (Note that this is not the same mapping as for A32; see cpu.h)
436 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
438 return vec_reg_offset(s
, regno
, 0, size
);
441 /* Offset of the high half of the 128 bit vector Qn */
442 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
444 return vec_reg_offset(s
, regno
, 1, MO_64
);
447 /* Convenience accessors for reading and writing single and double
448 * FP registers. Writing clears the upper parts of the associated
449 * 128 bit vector register, as required by the architecture.
450 * Note that unlike the GP register accessors, the values returned
451 * by the read functions must be manually freed.
453 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
455 TCGv_i64 v
= tcg_temp_new_i64();
457 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
461 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
463 TCGv_i32 v
= tcg_temp_new_i32();
465 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
469 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
471 TCGv_i32 v
= tcg_temp_new_i32();
473 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
477 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
478 * If SVE is not enabled, then there are only 128 bits in the vector.
480 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
482 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
483 unsigned vsz
= vec_full_reg_size(s
);
486 TCGv_i64 tcg_zero
= tcg_const_i64(0);
487 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
488 tcg_temp_free_i64(tcg_zero
);
491 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
495 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
497 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
499 tcg_gen_st_i64(v
, cpu_env
, ofs
);
500 clear_vec_high(s
, false, reg
);
503 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
505 TCGv_i64 tmp
= tcg_temp_new_i64();
507 tcg_gen_extu_i32_i64(tmp
, v
);
508 write_fp_dreg(s
, reg
, tmp
);
509 tcg_temp_free_i64(tmp
);
512 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
514 TCGv_ptr statusptr
= tcg_temp_new_ptr();
517 /* In A64 all instructions (both FP and Neon) use the FPCR; there
518 * is no equivalent of the A32 Neon "standard FPSCR value".
519 * However half-precision operations operate under a different
520 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
523 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
525 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
527 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
531 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
532 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
533 GVecGen2Fn
*gvec_fn
, int vece
)
535 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
536 is_q
? 16 : 8, vec_full_reg_size(s
));
539 /* Expand a 2-operand + immediate AdvSIMD vector operation using
540 * an expander function.
542 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
543 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
545 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
546 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
549 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
550 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
551 GVecGen3Fn
*gvec_fn
, int vece
)
553 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
554 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
557 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
558 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
559 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
561 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
562 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
563 is_q
? 16 : 8, vec_full_reg_size(s
));
566 /* Expand a 2-operand + immediate AdvSIMD vector operation using
569 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
570 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
572 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
573 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
576 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
577 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
578 int rn
, int rm
, const GVecGen3
*gvec_op
)
580 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
581 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
582 vec_full_reg_size(s
), gvec_op
);
585 /* Expand a 3-operand operation using an out-of-line helper. */
586 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
587 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
589 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
590 vec_full_reg_offset(s
, rn
),
591 vec_full_reg_offset(s
, rm
),
592 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
595 /* Expand a 3-operand + env pointer operation using
596 * an out-of-line helper.
598 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
599 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
601 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
602 vec_full_reg_offset(s
, rn
),
603 vec_full_reg_offset(s
, rm
), cpu_env
,
604 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
607 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
608 * an out-of-line helper.
610 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
611 int rm
, bool is_fp16
, int data
,
612 gen_helper_gvec_3_ptr
*fn
)
614 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
615 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
616 vec_full_reg_offset(s
, rn
),
617 vec_full_reg_offset(s
, rm
), fpst
,
618 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
619 tcg_temp_free_ptr(fpst
);
622 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
623 * than the 32 bit equivalent.
625 static inline void gen_set_NZ64(TCGv_i64 result
)
627 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
628 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
631 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
632 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
635 gen_set_NZ64(result
);
637 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
638 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
640 tcg_gen_movi_i32(cpu_CF
, 0);
641 tcg_gen_movi_i32(cpu_VF
, 0);
644 /* dest = T0 + T1; compute C, N, V and Z flags */
645 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
648 TCGv_i64 result
, flag
, tmp
;
649 result
= tcg_temp_new_i64();
650 flag
= tcg_temp_new_i64();
651 tmp
= tcg_temp_new_i64();
653 tcg_gen_movi_i64(tmp
, 0);
654 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
656 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
658 gen_set_NZ64(result
);
660 tcg_gen_xor_i64(flag
, result
, t0
);
661 tcg_gen_xor_i64(tmp
, t0
, t1
);
662 tcg_gen_andc_i64(flag
, flag
, tmp
);
663 tcg_temp_free_i64(tmp
);
664 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
666 tcg_gen_mov_i64(dest
, result
);
667 tcg_temp_free_i64(result
);
668 tcg_temp_free_i64(flag
);
670 /* 32 bit arithmetic */
671 TCGv_i32 t0_32
= tcg_temp_new_i32();
672 TCGv_i32 t1_32
= tcg_temp_new_i32();
673 TCGv_i32 tmp
= tcg_temp_new_i32();
675 tcg_gen_movi_i32(tmp
, 0);
676 tcg_gen_extrl_i64_i32(t0_32
, t0
);
677 tcg_gen_extrl_i64_i32(t1_32
, t1
);
678 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
679 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
680 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
681 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
682 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
683 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
685 tcg_temp_free_i32(tmp
);
686 tcg_temp_free_i32(t0_32
);
687 tcg_temp_free_i32(t1_32
);
691 /* dest = T0 - T1; compute C, N, V and Z flags */
692 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
695 /* 64 bit arithmetic */
696 TCGv_i64 result
, flag
, tmp
;
698 result
= tcg_temp_new_i64();
699 flag
= tcg_temp_new_i64();
700 tcg_gen_sub_i64(result
, t0
, t1
);
702 gen_set_NZ64(result
);
704 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
705 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
707 tcg_gen_xor_i64(flag
, result
, t0
);
708 tmp
= tcg_temp_new_i64();
709 tcg_gen_xor_i64(tmp
, t0
, t1
);
710 tcg_gen_and_i64(flag
, flag
, tmp
);
711 tcg_temp_free_i64(tmp
);
712 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
713 tcg_gen_mov_i64(dest
, result
);
714 tcg_temp_free_i64(flag
);
715 tcg_temp_free_i64(result
);
717 /* 32 bit arithmetic */
718 TCGv_i32 t0_32
= tcg_temp_new_i32();
719 TCGv_i32 t1_32
= tcg_temp_new_i32();
722 tcg_gen_extrl_i64_i32(t0_32
, t0
);
723 tcg_gen_extrl_i64_i32(t1_32
, t1
);
724 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
725 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
726 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
727 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
728 tmp
= tcg_temp_new_i32();
729 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
730 tcg_temp_free_i32(t0_32
);
731 tcg_temp_free_i32(t1_32
);
732 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
733 tcg_temp_free_i32(tmp
);
734 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
738 /* dest = T0 + T1 + CF; do not compute flags. */
739 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
741 TCGv_i64 flag
= tcg_temp_new_i64();
742 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
743 tcg_gen_add_i64(dest
, t0
, t1
);
744 tcg_gen_add_i64(dest
, dest
, flag
);
745 tcg_temp_free_i64(flag
);
748 tcg_gen_ext32u_i64(dest
, dest
);
752 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
753 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
756 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
757 result
= tcg_temp_new_i64();
758 cf_64
= tcg_temp_new_i64();
759 vf_64
= tcg_temp_new_i64();
760 tmp
= tcg_const_i64(0);
762 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
763 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
764 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
765 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
766 gen_set_NZ64(result
);
768 tcg_gen_xor_i64(vf_64
, result
, t0
);
769 tcg_gen_xor_i64(tmp
, t0
, t1
);
770 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
771 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
773 tcg_gen_mov_i64(dest
, result
);
775 tcg_temp_free_i64(tmp
);
776 tcg_temp_free_i64(vf_64
);
777 tcg_temp_free_i64(cf_64
);
778 tcg_temp_free_i64(result
);
780 TCGv_i32 t0_32
, t1_32
, tmp
;
781 t0_32
= tcg_temp_new_i32();
782 t1_32
= tcg_temp_new_i32();
783 tmp
= tcg_const_i32(0);
785 tcg_gen_extrl_i64_i32(t0_32
, t0
);
786 tcg_gen_extrl_i64_i32(t1_32
, t1
);
787 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
788 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
790 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
791 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
792 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
793 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
794 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
796 tcg_temp_free_i32(tmp
);
797 tcg_temp_free_i32(t1_32
);
798 tcg_temp_free_i32(t0_32
);
803 * Load/Store generators
807 * Store from GPR register to memory.
809 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
810 TCGv_i64 tcg_addr
, int size
, int memidx
,
812 unsigned int iss_srt
,
813 bool iss_sf
, bool iss_ar
)
816 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
821 syn
= syn_data_abort_with_iss(0,
827 0, 0, 0, 0, 0, false);
828 disas_set_insn_syndrome(s
, syn
);
832 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
833 TCGv_i64 tcg_addr
, int size
,
835 unsigned int iss_srt
,
836 bool iss_sf
, bool iss_ar
)
838 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
839 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
843 * Load from memory to GPR register
845 static void do_gpr_ld_memidx(DisasContext
*s
,
846 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
847 int size
, bool is_signed
,
848 bool extend
, int memidx
,
849 bool iss_valid
, unsigned int iss_srt
,
850 bool iss_sf
, bool iss_ar
)
852 MemOp memop
= s
->be_data
+ size
;
860 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
862 if (extend
&& is_signed
) {
864 tcg_gen_ext32u_i64(dest
, dest
);
870 syn
= syn_data_abort_with_iss(0,
876 0, 0, 0, 0, 0, false);
877 disas_set_insn_syndrome(s
, syn
);
881 static void do_gpr_ld(DisasContext
*s
,
882 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
883 int size
, bool is_signed
, bool extend
,
884 bool iss_valid
, unsigned int iss_srt
,
885 bool iss_sf
, bool iss_ar
)
887 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
889 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
893 * Store from FP register to memory
895 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
897 /* This writes the bottom N bits of a 128 bit wide vector to memory */
898 TCGv_i64 tmp
= tcg_temp_new_i64();
899 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
901 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
904 bool be
= s
->be_data
== MO_BE
;
905 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
907 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
908 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
910 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
911 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
913 tcg_temp_free_i64(tcg_hiaddr
);
916 tcg_temp_free_i64(tmp
);
920 * Load from memory to FP register
922 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
924 /* This always zero-extends and writes to a full 128 bit wide vector */
925 TCGv_i64 tmplo
= tcg_temp_new_i64();
929 MemOp memop
= s
->be_data
+ size
;
930 tmphi
= tcg_const_i64(0);
931 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
933 bool be
= s
->be_data
== MO_BE
;
936 tmphi
= tcg_temp_new_i64();
937 tcg_hiaddr
= tcg_temp_new_i64();
939 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
940 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
942 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
944 tcg_temp_free_i64(tcg_hiaddr
);
947 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
948 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
950 tcg_temp_free_i64(tmplo
);
951 tcg_temp_free_i64(tmphi
);
953 clear_vec_high(s
, true, destidx
);
957 * Vector load/store helpers.
959 * The principal difference between this and a FP load is that we don't
960 * zero extend as we are filling a partial chunk of the vector register.
961 * These functions don't support 128 bit loads/stores, which would be
962 * normal load/store operations.
964 * The _i32 versions are useful when operating on 32 bit quantities
965 * (eg for floating point single or using Neon helper functions).
968 /* Get value of an element within a vector register */
969 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
970 int element
, MemOp memop
)
972 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
975 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
978 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
981 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
984 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
987 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
990 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
994 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
997 g_assert_not_reached();
1001 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1002 int element
, MemOp memop
)
1004 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1007 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1010 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1013 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1016 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1020 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1023 g_assert_not_reached();
1027 /* Set value of an element within a vector register */
1028 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1029 int element
, MemOp memop
)
1031 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1034 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1037 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1040 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1043 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1046 g_assert_not_reached();
1050 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1051 int destidx
, int element
, MemOp memop
)
1053 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1056 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1059 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1062 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1065 g_assert_not_reached();
1069 /* Store from vector register to memory */
1070 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1071 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1073 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1075 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1076 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1078 tcg_temp_free_i64(tcg_tmp
);
1081 /* Load from memory to vector register */
1082 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1083 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1085 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1087 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1088 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1090 tcg_temp_free_i64(tcg_tmp
);
1093 /* Check that FP/Neon access is enabled. If it is, return
1094 * true. If not, emit code to generate an appropriate exception,
1095 * and return false; the caller should not emit any code for
1096 * the instruction. Note that this check must happen after all
1097 * unallocated-encoding checks (otherwise the syndrome information
1098 * for the resulting exception will be incorrect).
1100 static inline bool fp_access_check(DisasContext
*s
)
1102 assert(!s
->fp_access_checked
);
1103 s
->fp_access_checked
= true;
1105 if (!s
->fp_excp_el
) {
1109 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1110 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1114 /* Check that SVE access is enabled. If it is, return true.
1115 * If not, emit code to generate an appropriate exception and return false.
1117 bool sve_access_check(DisasContext
*s
)
1119 if (s
->sve_excp_el
) {
1120 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1124 return fp_access_check(s
);
1128 * This utility function is for doing register extension with an
1129 * optional shift. You will likely want to pass a temporary for the
1130 * destination register. See DecodeRegExtend() in the ARM ARM.
1132 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1133 int option
, unsigned int shift
)
1135 int extsize
= extract32(option
, 0, 2);
1136 bool is_signed
= extract32(option
, 2, 1);
1141 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1144 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1147 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1150 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1156 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1159 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1162 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1165 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1171 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1175 static inline void gen_check_sp_alignment(DisasContext
*s
)
1177 /* The AArch64 architecture mandates that (if enabled via PSTATE
1178 * or SCTLR bits) there is a check that SP is 16-aligned on every
1179 * SP-relative load or store (with an exception generated if it is not).
1180 * In line with general QEMU practice regarding misaligned accesses,
1181 * we omit these checks for the sake of guest program performance.
1182 * This function is provided as a hook so we can more easily add these
1183 * checks in future (possibly as a "favour catching guest program bugs
1184 * over speed" user selectable option).
1189 * This provides a simple table based table lookup decoder. It is
1190 * intended to be used when the relevant bits for decode are too
1191 * awkwardly placed and switch/if based logic would be confusing and
1192 * deeply nested. Since it's a linear search through the table, tables
1193 * should be kept small.
1195 * It returns the first handler where insn & mask == pattern, or
1196 * NULL if there is no match.
1197 * The table is terminated by an empty mask (i.e. 0)
1199 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1202 const AArch64DecodeTable
*tptr
= table
;
1204 while (tptr
->mask
) {
1205 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1206 return tptr
->disas_fn
;
1214 * The instruction disassembly implemented here matches
1215 * the instruction encoding classifications in chapter C4
1216 * of the ARM Architecture Reference Manual (DDI0487B_a);
1217 * classification names and decode diagrams here should generally
1218 * match up with those in the manual.
1221 /* Unconditional branch (immediate)
1223 * +----+-----------+-------------------------------------+
1224 * | op | 0 0 1 0 1 | imm26 |
1225 * +----+-----------+-------------------------------------+
1227 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1229 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1231 if (insn
& (1U << 31)) {
1232 /* BL Branch with link */
1233 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1236 /* B Branch / BL Branch with link */
1238 gen_goto_tb(s
, 0, addr
);
1241 /* Compare and branch (immediate)
1242 * 31 30 25 24 23 5 4 0
1243 * +----+-------------+----+---------------------+--------+
1244 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1245 * +----+-------------+----+---------------------+--------+
1247 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1249 unsigned int sf
, op
, rt
;
1251 TCGLabel
*label_match
;
1254 sf
= extract32(insn
, 31, 1);
1255 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1256 rt
= extract32(insn
, 0, 5);
1257 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1259 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1260 label_match
= gen_new_label();
1263 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1264 tcg_cmp
, 0, label_match
);
1266 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1267 gen_set_label(label_match
);
1268 gen_goto_tb(s
, 1, addr
);
1271 /* Test and branch (immediate)
1272 * 31 30 25 24 23 19 18 5 4 0
1273 * +----+-------------+----+-------+-------------+------+
1274 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1275 * +----+-------------+----+-------+-------------+------+
1277 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1279 unsigned int bit_pos
, op
, rt
;
1281 TCGLabel
*label_match
;
1284 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1285 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1286 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1287 rt
= extract32(insn
, 0, 5);
1289 tcg_cmp
= tcg_temp_new_i64();
1290 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1291 label_match
= gen_new_label();
1294 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1295 tcg_cmp
, 0, label_match
);
1296 tcg_temp_free_i64(tcg_cmp
);
1297 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1298 gen_set_label(label_match
);
1299 gen_goto_tb(s
, 1, addr
);
1302 /* Conditional branch (immediate)
1303 * 31 25 24 23 5 4 3 0
1304 * +---------------+----+---------------------+----+------+
1305 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1306 * +---------------+----+---------------------+----+------+
1308 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1313 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1314 unallocated_encoding(s
);
1317 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1318 cond
= extract32(insn
, 0, 4);
1322 /* genuinely conditional branches */
1323 TCGLabel
*label_match
= gen_new_label();
1324 arm_gen_test_cc(cond
, label_match
);
1325 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1326 gen_set_label(label_match
);
1327 gen_goto_tb(s
, 1, addr
);
1329 /* 0xe and 0xf are both "always" conditions */
1330 gen_goto_tb(s
, 0, addr
);
1334 /* HINT instruction group, including various allocated HINTs */
1335 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1336 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1338 unsigned int selector
= crm
<< 3 | op2
;
1341 unallocated_encoding(s
);
1346 case 0b00000: /* NOP */
1348 case 0b00011: /* WFI */
1349 s
->base
.is_jmp
= DISAS_WFI
;
1351 case 0b00001: /* YIELD */
1352 /* When running in MTTCG we don't generate jumps to the yield and
1353 * WFE helpers as it won't affect the scheduling of other vCPUs.
1354 * If we wanted to more completely model WFE/SEV so we don't busy
1355 * spin unnecessarily we would need to do something more involved.
1357 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1358 s
->base
.is_jmp
= DISAS_YIELD
;
1361 case 0b00010: /* WFE */
1362 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1363 s
->base
.is_jmp
= DISAS_WFE
;
1366 case 0b00100: /* SEV */
1367 case 0b00101: /* SEVL */
1368 /* we treat all as NOP at least for now */
1370 case 0b00111: /* XPACLRI */
1371 if (s
->pauth_active
) {
1372 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1375 case 0b01000: /* PACIA1716 */
1376 if (s
->pauth_active
) {
1377 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1380 case 0b01010: /* PACIB1716 */
1381 if (s
->pauth_active
) {
1382 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1385 case 0b01100: /* AUTIA1716 */
1386 if (s
->pauth_active
) {
1387 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1390 case 0b01110: /* AUTIB1716 */
1391 if (s
->pauth_active
) {
1392 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1395 case 0b11000: /* PACIAZ */
1396 if (s
->pauth_active
) {
1397 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1398 new_tmp_a64_zero(s
));
1401 case 0b11001: /* PACIASP */
1402 if (s
->pauth_active
) {
1403 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1406 case 0b11010: /* PACIBZ */
1407 if (s
->pauth_active
) {
1408 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1409 new_tmp_a64_zero(s
));
1412 case 0b11011: /* PACIBSP */
1413 if (s
->pauth_active
) {
1414 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1417 case 0b11100: /* AUTIAZ */
1418 if (s
->pauth_active
) {
1419 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1420 new_tmp_a64_zero(s
));
1423 case 0b11101: /* AUTIASP */
1424 if (s
->pauth_active
) {
1425 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1428 case 0b11110: /* AUTIBZ */
1429 if (s
->pauth_active
) {
1430 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1431 new_tmp_a64_zero(s
));
1434 case 0b11111: /* AUTIBSP */
1435 if (s
->pauth_active
) {
1436 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1440 /* default specified as NOP equivalent */
1445 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1447 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1450 /* CLREX, DSB, DMB, ISB */
1451 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1452 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1457 unallocated_encoding(s
);
1468 case 1: /* MBReqTypes_Reads */
1469 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1471 case 2: /* MBReqTypes_Writes */
1472 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1474 default: /* MBReqTypes_All */
1475 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1481 /* We need to break the TB after this insn to execute
1482 * a self-modified code correctly and also to take
1483 * any pending interrupts immediately.
1486 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1490 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1491 goto do_unallocated
;
1494 * TODO: There is no speculation barrier opcode for TCG;
1495 * MB and end the TB instead.
1497 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1498 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1503 unallocated_encoding(s
);
1508 static void gen_xaflag(void)
1510 TCGv_i32 z
= tcg_temp_new_i32();
1512 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1521 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1522 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1525 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1526 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1528 /* (!C & Z) << 31 -> -(Z & ~C) */
1529 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1530 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1533 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1535 tcg_temp_free_i32(z
);
1538 static void gen_axflag(void)
1540 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1541 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1543 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1544 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1546 tcg_gen_movi_i32(cpu_NF
, 0);
1547 tcg_gen_movi_i32(cpu_VF
, 0);
1550 /* MSR (immediate) - move immediate to processor state field */
1551 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1552 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1555 int op
= op1
<< 3 | op2
;
1557 /* End the TB by default, chaining is ok. */
1558 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1561 case 0x00: /* CFINV */
1562 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1563 goto do_unallocated
;
1565 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1566 s
->base
.is_jmp
= DISAS_NEXT
;
1569 case 0x01: /* XAFlag */
1570 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1571 goto do_unallocated
;
1574 s
->base
.is_jmp
= DISAS_NEXT
;
1577 case 0x02: /* AXFlag */
1578 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1579 goto do_unallocated
;
1582 s
->base
.is_jmp
= DISAS_NEXT
;
1585 case 0x05: /* SPSel */
1586 if (s
->current_el
== 0) {
1587 goto do_unallocated
;
1589 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1590 gen_helper_msr_i_spsel(cpu_env
, t1
);
1591 tcg_temp_free_i32(t1
);
1594 case 0x1e: /* DAIFSet */
1595 t1
= tcg_const_i32(crm
);
1596 gen_helper_msr_i_daifset(cpu_env
, t1
);
1597 tcg_temp_free_i32(t1
);
1600 case 0x1f: /* DAIFClear */
1601 t1
= tcg_const_i32(crm
);
1602 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1603 tcg_temp_free_i32(t1
);
1604 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1605 s
->base
.is_jmp
= DISAS_UPDATE
;
1610 unallocated_encoding(s
);
1615 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1617 TCGv_i32 tmp
= tcg_temp_new_i32();
1618 TCGv_i32 nzcv
= tcg_temp_new_i32();
1620 /* build bit 31, N */
1621 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1622 /* build bit 30, Z */
1623 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1624 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1625 /* build bit 29, C */
1626 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1627 /* build bit 28, V */
1628 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1629 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1630 /* generate result */
1631 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1633 tcg_temp_free_i32(nzcv
);
1634 tcg_temp_free_i32(tmp
);
1637 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1639 TCGv_i32 nzcv
= tcg_temp_new_i32();
1641 /* take NZCV from R[t] */
1642 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1645 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1647 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1648 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1650 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1651 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1653 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1654 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1655 tcg_temp_free_i32(nzcv
);
1658 /* MRS - move from system register
1659 * MSR (register) - move to system register
1662 * These are all essentially the same insn in 'read' and 'write'
1663 * versions, with varying op0 fields.
1665 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1666 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1667 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1669 const ARMCPRegInfo
*ri
;
1672 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1673 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1674 crn
, crm
, op0
, op1
, op2
));
1677 /* Unknown register; this might be a guest error or a QEMU
1678 * unimplemented feature.
1680 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1681 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1682 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1683 unallocated_encoding(s
);
1687 /* Check access permissions */
1688 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1689 unallocated_encoding(s
);
1694 /* Emit code to perform further access permissions checks at
1695 * runtime; this may result in an exception.
1698 TCGv_i32 tcg_syn
, tcg_isread
;
1701 gen_a64_set_pc_im(s
->pc_curr
);
1702 tmpptr
= tcg_const_ptr(ri
);
1703 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1704 tcg_syn
= tcg_const_i32(syndrome
);
1705 tcg_isread
= tcg_const_i32(isread
);
1706 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1707 tcg_temp_free_ptr(tmpptr
);
1708 tcg_temp_free_i32(tcg_syn
);
1709 tcg_temp_free_i32(tcg_isread
);
1712 /* Handle special cases first */
1713 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1717 tcg_rt
= cpu_reg(s
, rt
);
1719 gen_get_nzcv(tcg_rt
);
1721 gen_set_nzcv(tcg_rt
);
1724 case ARM_CP_CURRENTEL
:
1725 /* Reads as current EL value from pstate, which is
1726 * guaranteed to be constant by the tb flags.
1728 tcg_rt
= cpu_reg(s
, rt
);
1729 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1732 /* Writes clear the aligned block of memory which rt points into. */
1733 tcg_rt
= cpu_reg(s
, rt
);
1734 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1739 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1741 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1745 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1749 tcg_rt
= cpu_reg(s
, rt
);
1752 if (ri
->type
& ARM_CP_CONST
) {
1753 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1754 } else if (ri
->readfn
) {
1756 tmpptr
= tcg_const_ptr(ri
);
1757 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1758 tcg_temp_free_ptr(tmpptr
);
1760 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1763 if (ri
->type
& ARM_CP_CONST
) {
1764 /* If not forbidden by access permissions, treat as WI */
1766 } else if (ri
->writefn
) {
1768 tmpptr
= tcg_const_ptr(ri
);
1769 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1770 tcg_temp_free_ptr(tmpptr
);
1772 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1776 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1777 /* I/O operations must end the TB here (whether read or write) */
1778 s
->base
.is_jmp
= DISAS_UPDATE
;
1779 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1780 /* We default to ending the TB on a coprocessor register write,
1781 * but allow this to be suppressed by the register definition
1782 * (usually only necessary to work around guest bugs).
1784 s
->base
.is_jmp
= DISAS_UPDATE
;
1789 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1790 * +---------------------+---+-----+-----+-------+-------+-----+------+
1791 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1792 * +---------------------+---+-----+-----+-------+-------+-----+------+
1794 static void disas_system(DisasContext
*s
, uint32_t insn
)
1796 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1797 l
= extract32(insn
, 21, 1);
1798 op0
= extract32(insn
, 19, 2);
1799 op1
= extract32(insn
, 16, 3);
1800 crn
= extract32(insn
, 12, 4);
1801 crm
= extract32(insn
, 8, 4);
1802 op2
= extract32(insn
, 5, 3);
1803 rt
= extract32(insn
, 0, 5);
1806 if (l
|| rt
!= 31) {
1807 unallocated_encoding(s
);
1811 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1812 handle_hint(s
, insn
, op1
, op2
, crm
);
1814 case 3: /* CLREX, DSB, DMB, ISB */
1815 handle_sync(s
, insn
, op1
, op2
, crm
);
1817 case 4: /* MSR (immediate) */
1818 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1821 unallocated_encoding(s
);
1826 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1829 /* Exception generation
1831 * 31 24 23 21 20 5 4 2 1 0
1832 * +-----------------+-----+------------------------+-----+----+
1833 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1834 * +-----------------------+------------------------+----------+
1836 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1838 int opc
= extract32(insn
, 21, 3);
1839 int op2_ll
= extract32(insn
, 0, 5);
1840 int imm16
= extract32(insn
, 5, 16);
1845 /* For SVC, HVC and SMC we advance the single-step state
1846 * machine before taking the exception. This is architecturally
1847 * mandated, to ensure that single-stepping a system call
1848 * instruction works properly.
1853 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1854 syn_aa64_svc(imm16
), default_exception_el(s
));
1857 if (s
->current_el
== 0) {
1858 unallocated_encoding(s
);
1861 /* The pre HVC helper handles cases when HVC gets trapped
1862 * as an undefined insn by runtime configuration.
1864 gen_a64_set_pc_im(s
->pc_curr
);
1865 gen_helper_pre_hvc(cpu_env
);
1867 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1868 syn_aa64_hvc(imm16
), 2);
1871 if (s
->current_el
== 0) {
1872 unallocated_encoding(s
);
1875 gen_a64_set_pc_im(s
->pc_curr
);
1876 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1877 gen_helper_pre_smc(cpu_env
, tmp
);
1878 tcg_temp_free_i32(tmp
);
1880 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1881 syn_aa64_smc(imm16
), 3);
1884 unallocated_encoding(s
);
1890 unallocated_encoding(s
);
1894 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1898 unallocated_encoding(s
);
1901 /* HLT. This has two purposes.
1902 * Architecturally, it is an external halting debug instruction.
1903 * Since QEMU doesn't implement external debug, we treat this as
1904 * it is required for halting debug disabled: it will UNDEF.
1905 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1907 if (semihosting_enabled() && imm16
== 0xf000) {
1908 #ifndef CONFIG_USER_ONLY
1909 /* In system mode, don't allow userspace access to semihosting,
1910 * to provide some semblance of security (and for consistency
1911 * with our 32-bit semihosting).
1913 if (s
->current_el
== 0) {
1914 unsupported_encoding(s
, insn
);
1918 gen_exception_internal_insn(s
, s
->base
.pc_next
, EXCP_SEMIHOST
);
1920 unsupported_encoding(s
, insn
);
1924 if (op2_ll
< 1 || op2_ll
> 3) {
1925 unallocated_encoding(s
);
1928 /* DCPS1, DCPS2, DCPS3 */
1929 unsupported_encoding(s
, insn
);
1932 unallocated_encoding(s
);
1937 /* Unconditional branch (register)
1938 * 31 25 24 21 20 16 15 10 9 5 4 0
1939 * +---------------+-------+-------+-------+------+-------+
1940 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1941 * +---------------+-------+-------+-------+------+-------+
1943 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1945 unsigned int opc
, op2
, op3
, rn
, op4
;
1946 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
1950 opc
= extract32(insn
, 21, 4);
1951 op2
= extract32(insn
, 16, 5);
1952 op3
= extract32(insn
, 10, 6);
1953 rn
= extract32(insn
, 5, 5);
1954 op4
= extract32(insn
, 0, 5);
1957 goto do_unallocated
;
1969 goto do_unallocated
;
1971 dst
= cpu_reg(s
, rn
);
1976 if (!dc_isar_feature(aa64_pauth
, s
)) {
1977 goto do_unallocated
;
1981 if (rn
!= 0x1f || op4
!= 0x1f) {
1982 goto do_unallocated
;
1985 modifier
= cpu_X
[31];
1987 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
1989 goto do_unallocated
;
1991 modifier
= new_tmp_a64_zero(s
);
1993 if (s
->pauth_active
) {
1994 dst
= new_tmp_a64(s
);
1996 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
1998 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2001 dst
= cpu_reg(s
, rn
);
2006 goto do_unallocated
;
2008 gen_a64_set_pc(s
, dst
);
2009 /* BLR also needs to load return address */
2011 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2017 if (!dc_isar_feature(aa64_pauth
, s
)) {
2018 goto do_unallocated
;
2020 if ((op3
& ~1) != 2) {
2021 goto do_unallocated
;
2023 btype_mod
= opc
& 1;
2024 if (s
->pauth_active
) {
2025 dst
= new_tmp_a64(s
);
2026 modifier
= cpu_reg_sp(s
, op4
);
2028 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2030 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2033 dst
= cpu_reg(s
, rn
);
2035 gen_a64_set_pc(s
, dst
);
2036 /* BLRAA also needs to load return address */
2038 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2043 if (s
->current_el
== 0) {
2044 goto do_unallocated
;
2049 goto do_unallocated
;
2051 dst
= tcg_temp_new_i64();
2052 tcg_gen_ld_i64(dst
, cpu_env
,
2053 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2056 case 2: /* ERETAA */
2057 case 3: /* ERETAB */
2058 if (!dc_isar_feature(aa64_pauth
, s
)) {
2059 goto do_unallocated
;
2061 if (rn
!= 0x1f || op4
!= 0x1f) {
2062 goto do_unallocated
;
2064 dst
= tcg_temp_new_i64();
2065 tcg_gen_ld_i64(dst
, cpu_env
,
2066 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2067 if (s
->pauth_active
) {
2068 modifier
= cpu_X
[31];
2070 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2072 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2078 goto do_unallocated
;
2080 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2084 gen_helper_exception_return(cpu_env
, dst
);
2085 tcg_temp_free_i64(dst
);
2086 /* Must exit loop to check un-masked IRQs */
2087 s
->base
.is_jmp
= DISAS_EXIT
;
2091 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2092 goto do_unallocated
;
2094 unsupported_encoding(s
, insn
);
2100 unallocated_encoding(s
);
2104 switch (btype_mod
) {
2106 if (dc_isar_feature(aa64_bti
, s
)) {
2107 /* BR to {x16,x17} or !guard -> 1, else 3. */
2108 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2113 if (dc_isar_feature(aa64_bti
, s
)) {
2114 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2119 default: /* RET or none of the above. */
2120 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2124 s
->base
.is_jmp
= DISAS_JUMP
;
2127 /* Branches, exception generating and system instructions */
2128 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2130 switch (extract32(insn
, 25, 7)) {
2131 case 0x0a: case 0x0b:
2132 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2133 disas_uncond_b_imm(s
, insn
);
2135 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2136 disas_comp_b_imm(s
, insn
);
2138 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2139 disas_test_b_imm(s
, insn
);
2141 case 0x2a: /* Conditional branch (immediate) */
2142 disas_cond_b_imm(s
, insn
);
2144 case 0x6a: /* Exception generation / System */
2145 if (insn
& (1 << 24)) {
2146 if (extract32(insn
, 22, 2) == 0) {
2147 disas_system(s
, insn
);
2149 unallocated_encoding(s
);
2155 case 0x6b: /* Unconditional branch (register) */
2156 disas_uncond_b_reg(s
, insn
);
2159 unallocated_encoding(s
);
2165 * Load/Store exclusive instructions are implemented by remembering
2166 * the value/address loaded, and seeing if these are the same
2167 * when the store is performed. This is not actually the architecturally
2168 * mandated semantics, but it works for typical guest code sequences
2169 * and avoids having to monitor regular stores.
2171 * The store exclusive uses the atomic cmpxchg primitives to avoid
2172 * races in multi-threaded linux-user and when MTTCG softmmu is
2175 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2176 TCGv_i64 addr
, int size
, bool is_pair
)
2178 int idx
= get_mem_index(s
);
2179 MemOp memop
= s
->be_data
;
2181 g_assert(size
<= 3);
2183 g_assert(size
>= 2);
2185 /* The pair must be single-copy atomic for the doubleword. */
2186 memop
|= MO_64
| MO_ALIGN
;
2187 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2188 if (s
->be_data
== MO_LE
) {
2189 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2190 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2192 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2193 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2196 /* The pair must be single-copy atomic for *each* doubleword, not
2197 the entire quadword, however it must be quadword aligned. */
2199 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2200 memop
| MO_ALIGN_16
);
2202 TCGv_i64 addr2
= tcg_temp_new_i64();
2203 tcg_gen_addi_i64(addr2
, addr
, 8);
2204 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2205 tcg_temp_free_i64(addr2
);
2207 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2208 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2211 memop
|= size
| MO_ALIGN
;
2212 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2213 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2215 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2218 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2219 TCGv_i64 addr
, int size
, int is_pair
)
2221 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2222 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2225 * [addr + datasize] = {Rt2};
2231 * env->exclusive_addr = -1;
2233 TCGLabel
*fail_label
= gen_new_label();
2234 TCGLabel
*done_label
= gen_new_label();
2237 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2239 tmp
= tcg_temp_new_i64();
2242 if (s
->be_data
== MO_LE
) {
2243 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2245 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2247 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2248 cpu_exclusive_val
, tmp
,
2250 MO_64
| MO_ALIGN
| s
->be_data
);
2251 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2252 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2253 if (!HAVE_CMPXCHG128
) {
2254 gen_helper_exit_atomic(cpu_env
);
2255 s
->base
.is_jmp
= DISAS_NORETURN
;
2256 } else if (s
->be_data
== MO_LE
) {
2257 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2262 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2267 } else if (s
->be_data
== MO_LE
) {
2268 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2269 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2271 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2272 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2275 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2276 cpu_reg(s
, rt
), get_mem_index(s
),
2277 size
| MO_ALIGN
| s
->be_data
);
2278 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2280 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2281 tcg_temp_free_i64(tmp
);
2282 tcg_gen_br(done_label
);
2284 gen_set_label(fail_label
);
2285 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2286 gen_set_label(done_label
);
2287 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2290 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2293 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2294 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2295 int memidx
= get_mem_index(s
);
2296 TCGv_i64 clean_addr
;
2299 gen_check_sp_alignment(s
);
2301 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2302 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2303 size
| MO_ALIGN
| s
->be_data
);
2306 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2309 TCGv_i64 s1
= cpu_reg(s
, rs
);
2310 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2311 TCGv_i64 t1
= cpu_reg(s
, rt
);
2312 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2313 TCGv_i64 clean_addr
;
2314 int memidx
= get_mem_index(s
);
2317 gen_check_sp_alignment(s
);
2319 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2322 TCGv_i64 cmp
= tcg_temp_new_i64();
2323 TCGv_i64 val
= tcg_temp_new_i64();
2325 if (s
->be_data
== MO_LE
) {
2326 tcg_gen_concat32_i64(val
, t1
, t2
);
2327 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2329 tcg_gen_concat32_i64(val
, t2
, t1
);
2330 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2333 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2334 MO_64
| MO_ALIGN
| s
->be_data
);
2335 tcg_temp_free_i64(val
);
2337 if (s
->be_data
== MO_LE
) {
2338 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2340 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2342 tcg_temp_free_i64(cmp
);
2343 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2344 if (HAVE_CMPXCHG128
) {
2345 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2346 if (s
->be_data
== MO_LE
) {
2347 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2348 clean_addr
, t1
, t2
);
2350 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2351 clean_addr
, t1
, t2
);
2353 tcg_temp_free_i32(tcg_rs
);
2355 gen_helper_exit_atomic(cpu_env
);
2356 s
->base
.is_jmp
= DISAS_NORETURN
;
2359 TCGv_i64 d1
= tcg_temp_new_i64();
2360 TCGv_i64 d2
= tcg_temp_new_i64();
2361 TCGv_i64 a2
= tcg_temp_new_i64();
2362 TCGv_i64 c1
= tcg_temp_new_i64();
2363 TCGv_i64 c2
= tcg_temp_new_i64();
2364 TCGv_i64 zero
= tcg_const_i64(0);
2366 /* Load the two words, in memory order. */
2367 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2368 MO_64
| MO_ALIGN_16
| s
->be_data
);
2369 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2370 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2372 /* Compare the two words, also in memory order. */
2373 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2374 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2375 tcg_gen_and_i64(c2
, c2
, c1
);
2377 /* If compare equal, write back new data, else write back old data. */
2378 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2379 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2380 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2381 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2382 tcg_temp_free_i64(a2
);
2383 tcg_temp_free_i64(c1
);
2384 tcg_temp_free_i64(c2
);
2385 tcg_temp_free_i64(zero
);
2387 /* Write back the data from memory to Rs. */
2388 tcg_gen_mov_i64(s1
, d1
);
2389 tcg_gen_mov_i64(s2
, d2
);
2390 tcg_temp_free_i64(d1
);
2391 tcg_temp_free_i64(d2
);
2395 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2396 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2398 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2400 int opc0
= extract32(opc
, 0, 1);
2404 regsize
= opc0
? 32 : 64;
2406 regsize
= size
== 3 ? 64 : 32;
2408 return regsize
== 64;
2411 /* Load/store exclusive
2413 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2414 * +-----+-------------+----+---+----+------+----+-------+------+------+
2415 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2416 * +-----+-------------+----+---+----+------+----+-------+------+------+
2418 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2419 * L: 0 -> store, 1 -> load
2420 * o2: 0 -> exclusive, 1 -> not
2421 * o1: 0 -> single register, 1 -> register pair
2422 * o0: 1 -> load-acquire/store-release, 0 -> not
2424 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2426 int rt
= extract32(insn
, 0, 5);
2427 int rn
= extract32(insn
, 5, 5);
2428 int rt2
= extract32(insn
, 10, 5);
2429 int rs
= extract32(insn
, 16, 5);
2430 int is_lasr
= extract32(insn
, 15, 1);
2431 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2432 int size
= extract32(insn
, 30, 2);
2433 TCGv_i64 clean_addr
;
2435 switch (o2_L_o1_o0
) {
2436 case 0x0: /* STXR */
2437 case 0x1: /* STLXR */
2439 gen_check_sp_alignment(s
);
2442 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2444 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2445 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2448 case 0x4: /* LDXR */
2449 case 0x5: /* LDAXR */
2451 gen_check_sp_alignment(s
);
2453 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2455 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2457 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2461 case 0x8: /* STLLR */
2462 if (!dc_isar_feature(aa64_lor
, s
)) {
2465 /* StoreLORelease is the same as Store-Release for QEMU. */
2467 case 0x9: /* STLR */
2468 /* Generate ISS for non-exclusive accesses including LASR. */
2470 gen_check_sp_alignment(s
);
2472 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2473 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2474 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2475 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2478 case 0xc: /* LDLAR */
2479 if (!dc_isar_feature(aa64_lor
, s
)) {
2482 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2484 case 0xd: /* LDAR */
2485 /* Generate ISS for non-exclusive accesses including LASR. */
2487 gen_check_sp_alignment(s
);
2489 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2490 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2491 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2492 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2495 case 0x2: case 0x3: /* CASP / STXP */
2496 if (size
& 2) { /* STXP / STLXP */
2498 gen_check_sp_alignment(s
);
2501 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2503 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2504 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2508 && ((rt
| rs
) & 1) == 0
2509 && dc_isar_feature(aa64_atomics
, s
)) {
2511 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2516 case 0x6: case 0x7: /* CASPA / LDXP */
2517 if (size
& 2) { /* LDXP / LDAXP */
2519 gen_check_sp_alignment(s
);
2521 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2523 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2525 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2530 && ((rt
| rs
) & 1) == 0
2531 && dc_isar_feature(aa64_atomics
, s
)) {
2532 /* CASPA / CASPAL */
2533 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2539 case 0xb: /* CASL */
2540 case 0xe: /* CASA */
2541 case 0xf: /* CASAL */
2542 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2543 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2548 unallocated_encoding(s
);
2552 * Load register (literal)
2554 * 31 30 29 27 26 25 24 23 5 4 0
2555 * +-----+-------+---+-----+-------------------+-------+
2556 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2557 * +-----+-------+---+-----+-------------------+-------+
2559 * V: 1 -> vector (simd/fp)
2560 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2561 * 10-> 32 bit signed, 11 -> prefetch
2562 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2564 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2566 int rt
= extract32(insn
, 0, 5);
2567 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2568 bool is_vector
= extract32(insn
, 26, 1);
2569 int opc
= extract32(insn
, 30, 2);
2570 bool is_signed
= false;
2572 TCGv_i64 tcg_rt
, clean_addr
;
2576 unallocated_encoding(s
);
2580 if (!fp_access_check(s
)) {
2585 /* PRFM (literal) : prefetch */
2588 size
= 2 + extract32(opc
, 0, 1);
2589 is_signed
= extract32(opc
, 1, 1);
2592 tcg_rt
= cpu_reg(s
, rt
);
2594 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2596 do_fp_ld(s
, rt
, clean_addr
, size
);
2598 /* Only unsigned 32bit loads target 32bit registers. */
2599 bool iss_sf
= opc
!= 0;
2601 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2602 true, rt
, iss_sf
, false);
2604 tcg_temp_free_i64(clean_addr
);
2608 * LDNP (Load Pair - non-temporal hint)
2609 * LDP (Load Pair - non vector)
2610 * LDPSW (Load Pair Signed Word - non vector)
2611 * STNP (Store Pair - non-temporal hint)
2612 * STP (Store Pair - non vector)
2613 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2614 * LDP (Load Pair of SIMD&FP)
2615 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2616 * STP (Store Pair of SIMD&FP)
2618 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2619 * +-----+-------+---+---+-------+---+-----------------------------+
2620 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2621 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2623 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2625 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2626 * V: 0 -> GPR, 1 -> Vector
2627 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2628 * 10 -> signed offset, 11 -> pre-index
2629 * L: 0 -> Store 1 -> Load
2631 * Rt, Rt2 = GPR or SIMD registers to be stored
2632 * Rn = general purpose register containing address
2633 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2635 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2637 int rt
= extract32(insn
, 0, 5);
2638 int rn
= extract32(insn
, 5, 5);
2639 int rt2
= extract32(insn
, 10, 5);
2640 uint64_t offset
= sextract64(insn
, 15, 7);
2641 int index
= extract32(insn
, 23, 2);
2642 bool is_vector
= extract32(insn
, 26, 1);
2643 bool is_load
= extract32(insn
, 22, 1);
2644 int opc
= extract32(insn
, 30, 2);
2646 bool is_signed
= false;
2647 bool postindex
= false;
2650 TCGv_i64 clean_addr
, dirty_addr
;
2655 unallocated_encoding(s
);
2662 size
= 2 + extract32(opc
, 1, 1);
2663 is_signed
= extract32(opc
, 0, 1);
2664 if (!is_load
&& is_signed
) {
2665 unallocated_encoding(s
);
2671 case 1: /* post-index */
2676 /* signed offset with "non-temporal" hint. Since we don't emulate
2677 * caches we don't care about hints to the cache system about
2678 * data access patterns, and handle this identically to plain
2682 /* There is no non-temporal-hint version of LDPSW */
2683 unallocated_encoding(s
);
2688 case 2: /* signed offset, rn not updated */
2691 case 3: /* pre-index */
2697 if (is_vector
&& !fp_access_check(s
)) {
2704 gen_check_sp_alignment(s
);
2707 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2709 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2711 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2715 do_fp_ld(s
, rt
, clean_addr
, size
);
2717 do_fp_st(s
, rt
, clean_addr
, size
);
2719 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2721 do_fp_ld(s
, rt2
, clean_addr
, size
);
2723 do_fp_st(s
, rt2
, clean_addr
, size
);
2726 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2727 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2730 TCGv_i64 tmp
= tcg_temp_new_i64();
2732 /* Do not modify tcg_rt before recognizing any exception
2733 * from the second load.
2735 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2736 false, 0, false, false);
2737 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2738 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2739 false, 0, false, false);
2741 tcg_gen_mov_i64(tcg_rt
, tmp
);
2742 tcg_temp_free_i64(tmp
);
2744 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2745 false, 0, false, false);
2746 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2747 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2748 false, 0, false, false);
2754 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2756 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2761 * Load/store (immediate post-indexed)
2762 * Load/store (immediate pre-indexed)
2763 * Load/store (unscaled immediate)
2765 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2766 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2767 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2768 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2770 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2772 * V = 0 -> non-vector
2773 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2774 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2776 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2782 int rn
= extract32(insn
, 5, 5);
2783 int imm9
= sextract32(insn
, 12, 9);
2784 int idx
= extract32(insn
, 10, 2);
2785 bool is_signed
= false;
2786 bool is_store
= false;
2787 bool is_extended
= false;
2788 bool is_unpriv
= (idx
== 2);
2789 bool iss_valid
= !is_vector
;
2793 TCGv_i64 clean_addr
, dirty_addr
;
2796 size
|= (opc
& 2) << 1;
2797 if (size
> 4 || is_unpriv
) {
2798 unallocated_encoding(s
);
2801 is_store
= ((opc
& 1) == 0);
2802 if (!fp_access_check(s
)) {
2806 if (size
== 3 && opc
== 2) {
2807 /* PRFM - prefetch */
2809 unallocated_encoding(s
);
2814 if (opc
== 3 && size
> 1) {
2815 unallocated_encoding(s
);
2818 is_store
= (opc
== 0);
2819 is_signed
= extract32(opc
, 1, 1);
2820 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2838 g_assert_not_reached();
2842 gen_check_sp_alignment(s
);
2845 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2847 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2849 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2853 do_fp_st(s
, rt
, clean_addr
, size
);
2855 do_fp_ld(s
, rt
, clean_addr
, size
);
2858 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2859 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2860 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2863 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2864 iss_valid
, rt
, iss_sf
, false);
2866 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2867 is_signed
, is_extended
, memidx
,
2868 iss_valid
, rt
, iss_sf
, false);
2873 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2875 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2877 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2882 * Load/store (register offset)
2884 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2885 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2886 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2887 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2890 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2891 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2893 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2894 * opc<0>: 0 -> store, 1 -> load
2895 * V: 1 -> vector/simd
2896 * opt: extend encoding (see DecodeRegExtend)
2897 * S: if S=1 then scale (essentially index by sizeof(size))
2898 * Rt: register to transfer into/out of
2899 * Rn: address register or SP for base
2900 * Rm: offset register or ZR for offset
2902 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2908 int rn
= extract32(insn
, 5, 5);
2909 int shift
= extract32(insn
, 12, 1);
2910 int rm
= extract32(insn
, 16, 5);
2911 int opt
= extract32(insn
, 13, 3);
2912 bool is_signed
= false;
2913 bool is_store
= false;
2914 bool is_extended
= false;
2916 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2918 if (extract32(opt
, 1, 1) == 0) {
2919 unallocated_encoding(s
);
2924 size
|= (opc
& 2) << 1;
2926 unallocated_encoding(s
);
2929 is_store
= !extract32(opc
, 0, 1);
2930 if (!fp_access_check(s
)) {
2934 if (size
== 3 && opc
== 2) {
2935 /* PRFM - prefetch */
2938 if (opc
== 3 && size
> 1) {
2939 unallocated_encoding(s
);
2942 is_store
= (opc
== 0);
2943 is_signed
= extract32(opc
, 1, 1);
2944 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2948 gen_check_sp_alignment(s
);
2950 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2952 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2953 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2955 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
2956 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2960 do_fp_st(s
, rt
, clean_addr
, size
);
2962 do_fp_ld(s
, rt
, clean_addr
, size
);
2965 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2966 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2968 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2969 true, rt
, iss_sf
, false);
2971 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
2972 is_signed
, is_extended
,
2973 true, rt
, iss_sf
, false);
2979 * Load/store (unsigned immediate)
2981 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2982 * +----+-------+---+-----+-----+------------+-------+------+
2983 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2984 * +----+-------+---+-----+-----+------------+-------+------+
2987 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2988 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2990 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2991 * opc<0>: 0 -> store, 1 -> load
2992 * Rn: base address register (inc SP)
2993 * Rt: target register
2995 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3001 int rn
= extract32(insn
, 5, 5);
3002 unsigned int imm12
= extract32(insn
, 10, 12);
3003 unsigned int offset
;
3005 TCGv_i64 clean_addr
, dirty_addr
;
3008 bool is_signed
= false;
3009 bool is_extended
= false;
3012 size
|= (opc
& 2) << 1;
3014 unallocated_encoding(s
);
3017 is_store
= !extract32(opc
, 0, 1);
3018 if (!fp_access_check(s
)) {
3022 if (size
== 3 && opc
== 2) {
3023 /* PRFM - prefetch */
3026 if (opc
== 3 && size
> 1) {
3027 unallocated_encoding(s
);
3030 is_store
= (opc
== 0);
3031 is_signed
= extract32(opc
, 1, 1);
3032 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3036 gen_check_sp_alignment(s
);
3038 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3039 offset
= imm12
<< size
;
3040 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3041 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3045 do_fp_st(s
, rt
, clean_addr
, size
);
3047 do_fp_ld(s
, rt
, clean_addr
, size
);
3050 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3051 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3053 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3054 true, rt
, iss_sf
, false);
3056 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3057 true, rt
, iss_sf
, false);
3062 /* Atomic memory operations
3064 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3065 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3066 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3067 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3069 * Rt: the result register
3070 * Rn: base address or SP
3071 * Rs: the source register for the operation
3072 * V: vector flag (always 0 as of v8.3)
3076 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3077 int size
, int rt
, bool is_vector
)
3079 int rs
= extract32(insn
, 16, 5);
3080 int rn
= extract32(insn
, 5, 5);
3081 int o3_opc
= extract32(insn
, 12, 4);
3082 TCGv_i64 tcg_rs
, clean_addr
;
3083 AtomicThreeOpFn
*fn
;
3085 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3086 unallocated_encoding(s
);
3090 case 000: /* LDADD */
3091 fn
= tcg_gen_atomic_fetch_add_i64
;
3093 case 001: /* LDCLR */
3094 fn
= tcg_gen_atomic_fetch_and_i64
;
3096 case 002: /* LDEOR */
3097 fn
= tcg_gen_atomic_fetch_xor_i64
;
3099 case 003: /* LDSET */
3100 fn
= tcg_gen_atomic_fetch_or_i64
;
3102 case 004: /* LDSMAX */
3103 fn
= tcg_gen_atomic_fetch_smax_i64
;
3105 case 005: /* LDSMIN */
3106 fn
= tcg_gen_atomic_fetch_smin_i64
;
3108 case 006: /* LDUMAX */
3109 fn
= tcg_gen_atomic_fetch_umax_i64
;
3111 case 007: /* LDUMIN */
3112 fn
= tcg_gen_atomic_fetch_umin_i64
;
3115 fn
= tcg_gen_atomic_xchg_i64
;
3118 unallocated_encoding(s
);
3123 gen_check_sp_alignment(s
);
3125 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3126 tcg_rs
= read_cpu_reg(s
, rs
, true);
3128 if (o3_opc
== 1) { /* LDCLR */
3129 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3132 /* The tcg atomic primitives are all full barriers. Therefore we
3133 * can ignore the Acquire and Release bits of this instruction.
3135 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3136 s
->be_data
| size
| MO_ALIGN
);
3140 * PAC memory operations
3142 * 31 30 27 26 24 22 21 12 11 10 5 0
3143 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3144 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3145 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3147 * Rt: the result register
3148 * Rn: base address or SP
3149 * V: vector flag (always 0 as of v8.3)
3150 * M: clear for key DA, set for key DB
3151 * W: pre-indexing flag
3154 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3155 int size
, int rt
, bool is_vector
)
3157 int rn
= extract32(insn
, 5, 5);
3158 bool is_wback
= extract32(insn
, 11, 1);
3159 bool use_key_a
= !extract32(insn
, 23, 1);
3161 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3163 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3164 unallocated_encoding(s
);
3169 gen_check_sp_alignment(s
);
3171 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3173 if (s
->pauth_active
) {
3175 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3177 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3181 /* Form the 10-bit signed, scaled offset. */
3182 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3183 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3184 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3186 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3187 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3189 tcg_rt
= cpu_reg(s
, rt
);
3190 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3191 /* extend */ false, /* iss_valid */ !is_wback
,
3192 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3195 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3199 /* Load/store register (all forms) */
3200 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3202 int rt
= extract32(insn
, 0, 5);
3203 int opc
= extract32(insn
, 22, 2);
3204 bool is_vector
= extract32(insn
, 26, 1);
3205 int size
= extract32(insn
, 30, 2);
3207 switch (extract32(insn
, 24, 2)) {
3209 if (extract32(insn
, 21, 1) == 0) {
3210 /* Load/store register (unscaled immediate)
3211 * Load/store immediate pre/post-indexed
3212 * Load/store register unprivileged
3214 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3217 switch (extract32(insn
, 10, 2)) {
3219 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3222 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3225 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3230 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3233 unallocated_encoding(s
);
3236 /* AdvSIMD load/store multiple structures
3238 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3239 * +---+---+---------------+---+-------------+--------+------+------+------+
3240 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3241 * +---+---+---------------+---+-------------+--------+------+------+------+
3243 * AdvSIMD load/store multiple structures (post-indexed)
3245 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3246 * +---+---+---------------+---+---+---------+--------+------+------+------+
3247 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3248 * +---+---+---------------+---+---+---------+--------+------+------+------+
3250 * Rt: first (or only) SIMD&FP register to be transferred
3251 * Rn: base address or SP
3252 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3254 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3256 int rt
= extract32(insn
, 0, 5);
3257 int rn
= extract32(insn
, 5, 5);
3258 int rm
= extract32(insn
, 16, 5);
3259 int size
= extract32(insn
, 10, 2);
3260 int opcode
= extract32(insn
, 12, 4);
3261 bool is_store
= !extract32(insn
, 22, 1);
3262 bool is_postidx
= extract32(insn
, 23, 1);
3263 bool is_q
= extract32(insn
, 30, 1);
3264 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3265 MemOp endian
= s
->be_data
;
3267 int ebytes
; /* bytes per element */
3268 int elements
; /* elements per vector */
3269 int rpt
; /* num iterations */
3270 int selem
; /* structure elements */
3273 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3274 unallocated_encoding(s
);
3278 if (!is_postidx
&& rm
!= 0) {
3279 unallocated_encoding(s
);
3283 /* From the shared decode logic */
3314 unallocated_encoding(s
);
3318 if (size
== 3 && !is_q
&& selem
!= 1) {
3320 unallocated_encoding(s
);
3324 if (!fp_access_check(s
)) {
3329 gen_check_sp_alignment(s
);
3332 /* For our purposes, bytes are always little-endian. */
3337 /* Consecutive little-endian elements from a single register
3338 * can be promoted to a larger little-endian operation.
3340 if (selem
== 1 && endian
== MO_LE
) {
3344 elements
= (is_q
? 16 : 8) / ebytes
;
3346 tcg_rn
= cpu_reg_sp(s
, rn
);
3347 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3348 tcg_ebytes
= tcg_const_i64(ebytes
);
3350 for (r
= 0; r
< rpt
; r
++) {
3352 for (e
= 0; e
< elements
; e
++) {
3354 for (xs
= 0; xs
< selem
; xs
++) {
3355 int tt
= (rt
+ r
+ xs
) % 32;
3357 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3359 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3361 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3365 tcg_temp_free_i64(tcg_ebytes
);
3368 /* For non-quad operations, setting a slice of the low
3369 * 64 bits of the register clears the high 64 bits (in
3370 * the ARM ARM pseudocode this is implicit in the fact
3371 * that 'rval' is a 64 bit wide variable).
3372 * For quad operations, we might still need to zero the
3375 for (r
= 0; r
< rpt
* selem
; r
++) {
3376 int tt
= (rt
+ r
) % 32;
3377 clear_vec_high(s
, is_q
, tt
);
3383 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3385 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3390 /* AdvSIMD load/store single structure
3392 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3393 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3394 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3395 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3397 * AdvSIMD load/store single structure (post-indexed)
3399 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3400 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3401 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3402 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3404 * Rt: first (or only) SIMD&FP register to be transferred
3405 * Rn: base address or SP
3406 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3407 * index = encoded in Q:S:size dependent on size
3409 * lane_size = encoded in R, opc
3410 * transfer width = encoded in opc, S, size
3412 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3414 int rt
= extract32(insn
, 0, 5);
3415 int rn
= extract32(insn
, 5, 5);
3416 int rm
= extract32(insn
, 16, 5);
3417 int size
= extract32(insn
, 10, 2);
3418 int S
= extract32(insn
, 12, 1);
3419 int opc
= extract32(insn
, 13, 3);
3420 int R
= extract32(insn
, 21, 1);
3421 int is_load
= extract32(insn
, 22, 1);
3422 int is_postidx
= extract32(insn
, 23, 1);
3423 int is_q
= extract32(insn
, 30, 1);
3425 int scale
= extract32(opc
, 1, 2);
3426 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3427 bool replicate
= false;
3428 int index
= is_q
<< 3 | S
<< 2 | size
;
3430 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3432 if (extract32(insn
, 31, 1)) {
3433 unallocated_encoding(s
);
3436 if (!is_postidx
&& rm
!= 0) {
3437 unallocated_encoding(s
);
3443 if (!is_load
|| S
) {
3444 unallocated_encoding(s
);
3453 if (extract32(size
, 0, 1)) {
3454 unallocated_encoding(s
);
3460 if (extract32(size
, 1, 1)) {
3461 unallocated_encoding(s
);
3464 if (!extract32(size
, 0, 1)) {
3468 unallocated_encoding(s
);
3476 g_assert_not_reached();
3479 if (!fp_access_check(s
)) {
3483 ebytes
= 1 << scale
;
3486 gen_check_sp_alignment(s
);
3489 tcg_rn
= cpu_reg_sp(s
, rn
);
3490 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3491 tcg_ebytes
= tcg_const_i64(ebytes
);
3493 for (xs
= 0; xs
< selem
; xs
++) {
3495 /* Load and replicate to all elements */
3496 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3498 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3499 get_mem_index(s
), s
->be_data
+ scale
);
3500 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3501 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3503 tcg_temp_free_i64(tcg_tmp
);
3505 /* Load/store one element per register */
3507 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3509 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3512 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3515 tcg_temp_free_i64(tcg_ebytes
);
3519 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3521 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3526 /* Loads and stores */
3527 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3529 switch (extract32(insn
, 24, 6)) {
3530 case 0x08: /* Load/store exclusive */
3531 disas_ldst_excl(s
, insn
);
3533 case 0x18: case 0x1c: /* Load register (literal) */
3534 disas_ld_lit(s
, insn
);
3536 case 0x28: case 0x29:
3537 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3538 disas_ldst_pair(s
, insn
);
3540 case 0x38: case 0x39:
3541 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3542 disas_ldst_reg(s
, insn
);
3544 case 0x0c: /* AdvSIMD load/store multiple structures */
3545 disas_ldst_multiple_struct(s
, insn
);
3547 case 0x0d: /* AdvSIMD load/store single structure */
3548 disas_ldst_single_struct(s
, insn
);
3551 unallocated_encoding(s
);
3556 /* PC-rel. addressing
3557 * 31 30 29 28 24 23 5 4 0
3558 * +----+-------+-----------+-------------------+------+
3559 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3560 * +----+-------+-----------+-------------------+------+
3562 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3564 unsigned int page
, rd
;
3568 page
= extract32(insn
, 31, 1);
3569 /* SignExtend(immhi:immlo) -> offset */
3570 offset
= sextract64(insn
, 5, 19);
3571 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3572 rd
= extract32(insn
, 0, 5);
3576 /* ADRP (page based) */
3581 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3585 * Add/subtract (immediate)
3587 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3588 * +--+--+--+-----------+-----+-------------+-----+-----+
3589 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3590 * +--+--+--+-----------+-----+-------------+-----+-----+
3592 * sf: 0 -> 32bit, 1 -> 64bit
3593 * op: 0 -> add , 1 -> sub
3595 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3597 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3599 int rd
= extract32(insn
, 0, 5);
3600 int rn
= extract32(insn
, 5, 5);
3601 uint64_t imm
= extract32(insn
, 10, 12);
3602 int shift
= extract32(insn
, 22, 2);
3603 bool setflags
= extract32(insn
, 29, 1);
3604 bool sub_op
= extract32(insn
, 30, 1);
3605 bool is_64bit
= extract32(insn
, 31, 1);
3607 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3608 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3609 TCGv_i64 tcg_result
;
3618 unallocated_encoding(s
);
3622 tcg_result
= tcg_temp_new_i64();
3625 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3627 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3630 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3632 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3634 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3636 tcg_temp_free_i64(tcg_imm
);
3640 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3642 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3645 tcg_temp_free_i64(tcg_result
);
3648 /* The input should be a value in the bottom e bits (with higher
3649 * bits zero); returns that value replicated into every element
3650 * of size e in a 64 bit integer.
3652 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3662 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3663 static inline uint64_t bitmask64(unsigned int length
)
3665 assert(length
> 0 && length
<= 64);
3666 return ~0ULL >> (64 - length
);
3669 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3670 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3671 * value (ie should cause a guest UNDEF exception), and true if they are
3672 * valid, in which case the decoded bit pattern is written to result.
3674 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3675 unsigned int imms
, unsigned int immr
)
3678 unsigned e
, levels
, s
, r
;
3681 assert(immn
< 2 && imms
< 64 && immr
< 64);
3683 /* The bit patterns we create here are 64 bit patterns which
3684 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3685 * 64 bits each. Each element contains the same value: a run
3686 * of between 1 and e-1 non-zero bits, rotated within the
3687 * element by between 0 and e-1 bits.
3689 * The element size and run length are encoded into immn (1 bit)
3690 * and imms (6 bits) as follows:
3691 * 64 bit elements: immn = 1, imms = <length of run - 1>
3692 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3693 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3694 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3695 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3696 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3697 * Notice that immn = 0, imms = 11111x is the only combination
3698 * not covered by one of the above options; this is reserved.
3699 * Further, <length of run - 1> all-ones is a reserved pattern.
3701 * In all cases the rotation is by immr % e (and immr is 6 bits).
3704 /* First determine the element size */
3705 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3707 /* This is the immn == 0, imms == 0x11111x case */
3717 /* <length of run - 1> mustn't be all-ones. */
3721 /* Create the value of one element: s+1 set bits rotated
3722 * by r within the element (which is e bits wide)...
3724 mask
= bitmask64(s
+ 1);
3726 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3727 mask
&= bitmask64(e
);
3729 /* ...then replicate the element over the whole 64 bit value */
3730 mask
= bitfield_replicate(mask
, e
);
3735 /* Logical (immediate)
3736 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3737 * +----+-----+-------------+---+------+------+------+------+
3738 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3739 * +----+-----+-------------+---+------+------+------+------+
3741 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3743 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3744 TCGv_i64 tcg_rd
, tcg_rn
;
3746 bool is_and
= false;
3748 sf
= extract32(insn
, 31, 1);
3749 opc
= extract32(insn
, 29, 2);
3750 is_n
= extract32(insn
, 22, 1);
3751 immr
= extract32(insn
, 16, 6);
3752 imms
= extract32(insn
, 10, 6);
3753 rn
= extract32(insn
, 5, 5);
3754 rd
= extract32(insn
, 0, 5);
3757 unallocated_encoding(s
);
3761 if (opc
== 0x3) { /* ANDS */
3762 tcg_rd
= cpu_reg(s
, rd
);
3764 tcg_rd
= cpu_reg_sp(s
, rd
);
3766 tcg_rn
= cpu_reg(s
, rn
);
3768 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3769 /* some immediate field values are reserved */
3770 unallocated_encoding(s
);
3775 wmask
&= 0xffffffff;
3779 case 0x3: /* ANDS */
3781 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3785 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3788 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3791 assert(FALSE
); /* must handle all above */
3795 if (!sf
&& !is_and
) {
3796 /* zero extend final result; we know we can skip this for AND
3797 * since the immediate had the high 32 bits clear.
3799 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3802 if (opc
== 3) { /* ANDS */
3803 gen_logic_CC(sf
, tcg_rd
);
3808 * Move wide (immediate)
3810 * 31 30 29 28 23 22 21 20 5 4 0
3811 * +--+-----+-------------+-----+----------------+------+
3812 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3813 * +--+-----+-------------+-----+----------------+------+
3815 * sf: 0 -> 32 bit, 1 -> 64 bit
3816 * opc: 00 -> N, 10 -> Z, 11 -> K
3817 * hw: shift/16 (0,16, and sf only 32, 48)
3819 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3821 int rd
= extract32(insn
, 0, 5);
3822 uint64_t imm
= extract32(insn
, 5, 16);
3823 int sf
= extract32(insn
, 31, 1);
3824 int opc
= extract32(insn
, 29, 2);
3825 int pos
= extract32(insn
, 21, 2) << 4;
3826 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3829 if (!sf
&& (pos
>= 32)) {
3830 unallocated_encoding(s
);
3844 tcg_gen_movi_i64(tcg_rd
, imm
);
3847 tcg_imm
= tcg_const_i64(imm
);
3848 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3849 tcg_temp_free_i64(tcg_imm
);
3851 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3855 unallocated_encoding(s
);
3861 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3862 * +----+-----+-------------+---+------+------+------+------+
3863 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3864 * +----+-----+-------------+---+------+------+------+------+
3866 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3868 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3869 TCGv_i64 tcg_rd
, tcg_tmp
;
3871 sf
= extract32(insn
, 31, 1);
3872 opc
= extract32(insn
, 29, 2);
3873 n
= extract32(insn
, 22, 1);
3874 ri
= extract32(insn
, 16, 6);
3875 si
= extract32(insn
, 10, 6);
3876 rn
= extract32(insn
, 5, 5);
3877 rd
= extract32(insn
, 0, 5);
3878 bitsize
= sf
? 64 : 32;
3880 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3881 unallocated_encoding(s
);
3885 tcg_rd
= cpu_reg(s
, rd
);
3887 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3888 to be smaller than bitsize, we'll never reference data outside the
3889 low 32-bits anyway. */
3890 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3892 /* Recognize simple(r) extractions. */
3894 /* Wd<s-r:0> = Wn<s:r> */
3895 len
= (si
- ri
) + 1;
3896 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3897 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3899 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3900 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3903 /* opc == 1, BFXIL fall through to deposit */
3904 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
3907 /* Handle the ri > si case with a deposit
3908 * Wd<32+s-r,32-r> = Wn<s:0>
3911 pos
= (bitsize
- ri
) & (bitsize
- 1);
3914 if (opc
== 0 && len
< ri
) {
3915 /* SBFM: sign extend the destination field from len to fill
3916 the balance of the word. Let the deposit below insert all
3917 of those sign bits. */
3918 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3922 if (opc
== 1) { /* BFM, BFXIL */
3923 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3925 /* SBFM or UBFM: We start with zero, and we haven't modified
3926 any bits outside bitsize, therefore the zero-extension
3927 below is unneeded. */
3928 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3933 if (!sf
) { /* zero extend final result */
3934 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3939 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3940 * +----+------+-------------+---+----+------+--------+------+------+
3941 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3942 * +----+------+-------------+---+----+------+--------+------+------+
3944 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3946 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3948 sf
= extract32(insn
, 31, 1);
3949 n
= extract32(insn
, 22, 1);
3950 rm
= extract32(insn
, 16, 5);
3951 imm
= extract32(insn
, 10, 6);
3952 rn
= extract32(insn
, 5, 5);
3953 rd
= extract32(insn
, 0, 5);
3954 op21
= extract32(insn
, 29, 2);
3955 op0
= extract32(insn
, 21, 1);
3956 bitsize
= sf
? 64 : 32;
3958 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3959 unallocated_encoding(s
);
3961 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3963 tcg_rd
= cpu_reg(s
, rd
);
3965 if (unlikely(imm
== 0)) {
3966 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3967 * so an extract from bit 0 is a special case.
3970 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3972 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3975 tcg_rm
= cpu_reg(s
, rm
);
3976 tcg_rn
= cpu_reg(s
, rn
);
3979 /* Specialization to ROR happens in EXTRACT2. */
3980 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
3982 TCGv_i32 t0
= tcg_temp_new_i32();
3984 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
3986 tcg_gen_rotri_i32(t0
, t0
, imm
);
3988 TCGv_i32 t1
= tcg_temp_new_i32();
3989 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
3990 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
3991 tcg_temp_free_i32(t1
);
3993 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
3994 tcg_temp_free_i32(t0
);
4000 /* Data processing - immediate */
4001 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4003 switch (extract32(insn
, 23, 6)) {
4004 case 0x20: case 0x21: /* PC-rel. addressing */
4005 disas_pc_rel_adr(s
, insn
);
4007 case 0x22: case 0x23: /* Add/subtract (immediate) */
4008 disas_add_sub_imm(s
, insn
);
4010 case 0x24: /* Logical (immediate) */
4011 disas_logic_imm(s
, insn
);
4013 case 0x25: /* Move wide (immediate) */
4014 disas_movw_imm(s
, insn
);
4016 case 0x26: /* Bitfield */
4017 disas_bitfield(s
, insn
);
4019 case 0x27: /* Extract */
4020 disas_extract(s
, insn
);
4023 unallocated_encoding(s
);
4028 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4029 * Note that it is the caller's responsibility to ensure that the
4030 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4031 * mandated semantics for out of range shifts.
4033 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4034 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4036 switch (shift_type
) {
4037 case A64_SHIFT_TYPE_LSL
:
4038 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4040 case A64_SHIFT_TYPE_LSR
:
4041 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4043 case A64_SHIFT_TYPE_ASR
:
4045 tcg_gen_ext32s_i64(dst
, src
);
4047 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4049 case A64_SHIFT_TYPE_ROR
:
4051 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4054 t0
= tcg_temp_new_i32();
4055 t1
= tcg_temp_new_i32();
4056 tcg_gen_extrl_i64_i32(t0
, src
);
4057 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4058 tcg_gen_rotr_i32(t0
, t0
, t1
);
4059 tcg_gen_extu_i32_i64(dst
, t0
);
4060 tcg_temp_free_i32(t0
);
4061 tcg_temp_free_i32(t1
);
4065 assert(FALSE
); /* all shift types should be handled */
4069 if (!sf
) { /* zero extend final result */
4070 tcg_gen_ext32u_i64(dst
, dst
);
4074 /* Shift a TCGv src by immediate, put result in dst.
4075 * The shift amount must be in range (this should always be true as the
4076 * relevant instructions will UNDEF on bad shift immediates).
4078 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4079 enum a64_shift_type shift_type
, unsigned int shift_i
)
4081 assert(shift_i
< (sf
? 64 : 32));
4084 tcg_gen_mov_i64(dst
, src
);
4086 TCGv_i64 shift_const
;
4088 shift_const
= tcg_const_i64(shift_i
);
4089 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4090 tcg_temp_free_i64(shift_const
);
4094 /* Logical (shifted register)
4095 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4096 * +----+-----+-----------+-------+---+------+--------+------+------+
4097 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4098 * +----+-----+-----------+-------+---+------+--------+------+------+
4100 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4102 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4103 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4105 sf
= extract32(insn
, 31, 1);
4106 opc
= extract32(insn
, 29, 2);
4107 shift_type
= extract32(insn
, 22, 2);
4108 invert
= extract32(insn
, 21, 1);
4109 rm
= extract32(insn
, 16, 5);
4110 shift_amount
= extract32(insn
, 10, 6);
4111 rn
= extract32(insn
, 5, 5);
4112 rd
= extract32(insn
, 0, 5);
4114 if (!sf
&& (shift_amount
& (1 << 5))) {
4115 unallocated_encoding(s
);
4119 tcg_rd
= cpu_reg(s
, rd
);
4121 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4122 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4123 * register-register MOV and MVN, so it is worth special casing.
4125 tcg_rm
= cpu_reg(s
, rm
);
4127 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4129 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4133 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4135 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4141 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4144 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4147 tcg_rn
= cpu_reg(s
, rn
);
4149 switch (opc
| (invert
<< 2)) {
4152 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4155 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4158 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4162 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4165 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4168 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4176 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4180 gen_logic_CC(sf
, tcg_rd
);
4185 * Add/subtract (extended register)
4187 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4188 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4189 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4190 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4192 * sf: 0 -> 32bit, 1 -> 64bit
4193 * op: 0 -> add , 1 -> sub
4196 * option: extension type (see DecodeRegExtend)
4197 * imm3: optional shift to Rm
4199 * Rd = Rn + LSL(extend(Rm), amount)
4201 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4203 int rd
= extract32(insn
, 0, 5);
4204 int rn
= extract32(insn
, 5, 5);
4205 int imm3
= extract32(insn
, 10, 3);
4206 int option
= extract32(insn
, 13, 3);
4207 int rm
= extract32(insn
, 16, 5);
4208 int opt
= extract32(insn
, 22, 2);
4209 bool setflags
= extract32(insn
, 29, 1);
4210 bool sub_op
= extract32(insn
, 30, 1);
4211 bool sf
= extract32(insn
, 31, 1);
4213 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4215 TCGv_i64 tcg_result
;
4217 if (imm3
> 4 || opt
!= 0) {
4218 unallocated_encoding(s
);
4222 /* non-flag setting ops may use SP */
4224 tcg_rd
= cpu_reg_sp(s
, rd
);
4226 tcg_rd
= cpu_reg(s
, rd
);
4228 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4230 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4231 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4233 tcg_result
= tcg_temp_new_i64();
4237 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4239 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4243 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4245 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4250 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4252 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4255 tcg_temp_free_i64(tcg_result
);
4259 * Add/subtract (shifted register)
4261 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4262 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4263 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4264 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4266 * sf: 0 -> 32bit, 1 -> 64bit
4267 * op: 0 -> add , 1 -> sub
4269 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4270 * imm6: Shift amount to apply to Rm before the add/sub
4272 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4274 int rd
= extract32(insn
, 0, 5);
4275 int rn
= extract32(insn
, 5, 5);
4276 int imm6
= extract32(insn
, 10, 6);
4277 int rm
= extract32(insn
, 16, 5);
4278 int shift_type
= extract32(insn
, 22, 2);
4279 bool setflags
= extract32(insn
, 29, 1);
4280 bool sub_op
= extract32(insn
, 30, 1);
4281 bool sf
= extract32(insn
, 31, 1);
4283 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4284 TCGv_i64 tcg_rn
, tcg_rm
;
4285 TCGv_i64 tcg_result
;
4287 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4288 unallocated_encoding(s
);
4292 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4293 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4295 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4297 tcg_result
= tcg_temp_new_i64();
4301 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4303 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4307 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4309 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4314 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4316 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4319 tcg_temp_free_i64(tcg_result
);
4322 /* Data-processing (3 source)
4324 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4325 * +--+------+-----------+------+------+----+------+------+------+
4326 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4327 * +--+------+-----------+------+------+----+------+------+------+
4329 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4331 int rd
= extract32(insn
, 0, 5);
4332 int rn
= extract32(insn
, 5, 5);
4333 int ra
= extract32(insn
, 10, 5);
4334 int rm
= extract32(insn
, 16, 5);
4335 int op_id
= (extract32(insn
, 29, 3) << 4) |
4336 (extract32(insn
, 21, 3) << 1) |
4337 extract32(insn
, 15, 1);
4338 bool sf
= extract32(insn
, 31, 1);
4339 bool is_sub
= extract32(op_id
, 0, 1);
4340 bool is_high
= extract32(op_id
, 2, 1);
4341 bool is_signed
= false;
4346 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4348 case 0x42: /* SMADDL */
4349 case 0x43: /* SMSUBL */
4350 case 0x44: /* SMULH */
4353 case 0x0: /* MADD (32bit) */
4354 case 0x1: /* MSUB (32bit) */
4355 case 0x40: /* MADD (64bit) */
4356 case 0x41: /* MSUB (64bit) */
4357 case 0x4a: /* UMADDL */
4358 case 0x4b: /* UMSUBL */
4359 case 0x4c: /* UMULH */
4362 unallocated_encoding(s
);
4367 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4368 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4369 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4370 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4373 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4375 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4378 tcg_temp_free_i64(low_bits
);
4382 tcg_op1
= tcg_temp_new_i64();
4383 tcg_op2
= tcg_temp_new_i64();
4384 tcg_tmp
= tcg_temp_new_i64();
4387 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4388 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4391 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4392 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4394 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4395 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4399 if (ra
== 31 && !is_sub
) {
4400 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4401 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4403 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4405 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4407 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4412 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4415 tcg_temp_free_i64(tcg_op1
);
4416 tcg_temp_free_i64(tcg_op2
);
4417 tcg_temp_free_i64(tcg_tmp
);
4420 /* Add/subtract (with carry)
4421 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4422 * +--+--+--+------------------------+------+-------------+------+-----+
4423 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4424 * +--+--+--+------------------------+------+-------------+------+-----+
4427 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4429 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4430 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4432 sf
= extract32(insn
, 31, 1);
4433 op
= extract32(insn
, 30, 1);
4434 setflags
= extract32(insn
, 29, 1);
4435 rm
= extract32(insn
, 16, 5);
4436 rn
= extract32(insn
, 5, 5);
4437 rd
= extract32(insn
, 0, 5);
4439 tcg_rd
= cpu_reg(s
, rd
);
4440 tcg_rn
= cpu_reg(s
, rn
);
4443 tcg_y
= new_tmp_a64(s
);
4444 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4446 tcg_y
= cpu_reg(s
, rm
);
4450 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4452 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4457 * Rotate right into flags
4458 * 31 30 29 21 15 10 5 4 0
4459 * +--+--+--+-----------------+--------+-----------+------+--+------+
4460 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4461 * +--+--+--+-----------------+--------+-----------+------+--+------+
4463 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4465 int mask
= extract32(insn
, 0, 4);
4466 int o2
= extract32(insn
, 4, 1);
4467 int rn
= extract32(insn
, 5, 5);
4468 int imm6
= extract32(insn
, 15, 6);
4469 int sf_op_s
= extract32(insn
, 29, 3);
4473 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4474 unallocated_encoding(s
);
4478 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4479 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4481 nzcv
= tcg_temp_new_i32();
4482 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4484 if (mask
& 8) { /* N */
4485 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4487 if (mask
& 4) { /* Z */
4488 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4489 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4491 if (mask
& 2) { /* C */
4492 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4494 if (mask
& 1) { /* V */
4495 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4498 tcg_temp_free_i32(nzcv
);
4502 * Evaluate into flags
4503 * 31 30 29 21 15 14 10 5 4 0
4504 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4505 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4506 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4508 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4510 int o3_mask
= extract32(insn
, 0, 5);
4511 int rn
= extract32(insn
, 5, 5);
4512 int o2
= extract32(insn
, 15, 6);
4513 int sz
= extract32(insn
, 14, 1);
4514 int sf_op_s
= extract32(insn
, 29, 3);
4518 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4519 !dc_isar_feature(aa64_condm_4
, s
)) {
4520 unallocated_encoding(s
);
4523 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4525 tmp
= tcg_temp_new_i32();
4526 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4527 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4528 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4529 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4530 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4531 tcg_temp_free_i32(tmp
);
4534 /* Conditional compare (immediate / register)
4535 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4536 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4537 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4538 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4541 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4543 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4544 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4545 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4548 if (!extract32(insn
, 29, 1)) {
4549 unallocated_encoding(s
);
4552 if (insn
& (1 << 10 | 1 << 4)) {
4553 unallocated_encoding(s
);
4556 sf
= extract32(insn
, 31, 1);
4557 op
= extract32(insn
, 30, 1);
4558 is_imm
= extract32(insn
, 11, 1);
4559 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4560 cond
= extract32(insn
, 12, 4);
4561 rn
= extract32(insn
, 5, 5);
4562 nzcv
= extract32(insn
, 0, 4);
4564 /* Set T0 = !COND. */
4565 tcg_t0
= tcg_temp_new_i32();
4566 arm_test_cc(&c
, cond
);
4567 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4570 /* Load the arguments for the new comparison. */
4572 tcg_y
= new_tmp_a64(s
);
4573 tcg_gen_movi_i64(tcg_y
, y
);
4575 tcg_y
= cpu_reg(s
, y
);
4577 tcg_rn
= cpu_reg(s
, rn
);
4579 /* Set the flags for the new comparison. */
4580 tcg_tmp
= tcg_temp_new_i64();
4582 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4584 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4586 tcg_temp_free_i64(tcg_tmp
);
4588 /* If COND was false, force the flags to #nzcv. Compute two masks
4589 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4590 * For tcg hosts that support ANDC, we can make do with just T1.
4591 * In either case, allow the tcg optimizer to delete any unused mask.
4593 tcg_t1
= tcg_temp_new_i32();
4594 tcg_t2
= tcg_temp_new_i32();
4595 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4596 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4598 if (nzcv
& 8) { /* N */
4599 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4601 if (TCG_TARGET_HAS_andc_i32
) {
4602 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4604 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4607 if (nzcv
& 4) { /* Z */
4608 if (TCG_TARGET_HAS_andc_i32
) {
4609 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4611 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4614 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4616 if (nzcv
& 2) { /* C */
4617 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4619 if (TCG_TARGET_HAS_andc_i32
) {
4620 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4622 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4625 if (nzcv
& 1) { /* V */
4626 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4628 if (TCG_TARGET_HAS_andc_i32
) {
4629 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4631 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4634 tcg_temp_free_i32(tcg_t0
);
4635 tcg_temp_free_i32(tcg_t1
);
4636 tcg_temp_free_i32(tcg_t2
);
4639 /* Conditional select
4640 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4641 * +----+----+---+-----------------+------+------+-----+------+------+
4642 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4643 * +----+----+---+-----------------+------+------+-----+------+------+
4645 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4647 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4648 TCGv_i64 tcg_rd
, zero
;
4651 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4652 /* S == 1 or op2<1> == 1 */
4653 unallocated_encoding(s
);
4656 sf
= extract32(insn
, 31, 1);
4657 else_inv
= extract32(insn
, 30, 1);
4658 rm
= extract32(insn
, 16, 5);
4659 cond
= extract32(insn
, 12, 4);
4660 else_inc
= extract32(insn
, 10, 1);
4661 rn
= extract32(insn
, 5, 5);
4662 rd
= extract32(insn
, 0, 5);
4664 tcg_rd
= cpu_reg(s
, rd
);
4666 a64_test_cc(&c
, cond
);
4667 zero
= tcg_const_i64(0);
4669 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4671 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4673 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4676 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4677 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4678 if (else_inv
&& else_inc
) {
4679 tcg_gen_neg_i64(t_false
, t_false
);
4680 } else if (else_inv
) {
4681 tcg_gen_not_i64(t_false
, t_false
);
4682 } else if (else_inc
) {
4683 tcg_gen_addi_i64(t_false
, t_false
, 1);
4685 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4688 tcg_temp_free_i64(zero
);
4692 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4696 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4697 unsigned int rn
, unsigned int rd
)
4699 TCGv_i64 tcg_rd
, tcg_rn
;
4700 tcg_rd
= cpu_reg(s
, rd
);
4701 tcg_rn
= cpu_reg(s
, rn
);
4704 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4706 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4707 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4708 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4709 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4710 tcg_temp_free_i32(tcg_tmp32
);
4714 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4715 unsigned int rn
, unsigned int rd
)
4717 TCGv_i64 tcg_rd
, tcg_rn
;
4718 tcg_rd
= cpu_reg(s
, rd
);
4719 tcg_rn
= cpu_reg(s
, rn
);
4722 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4724 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4725 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4726 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4727 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4728 tcg_temp_free_i32(tcg_tmp32
);
4732 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4733 unsigned int rn
, unsigned int rd
)
4735 TCGv_i64 tcg_rd
, tcg_rn
;
4736 tcg_rd
= cpu_reg(s
, rd
);
4737 tcg_rn
= cpu_reg(s
, rn
);
4740 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4742 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4743 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4744 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4745 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4746 tcg_temp_free_i32(tcg_tmp32
);
4750 /* REV with sf==1, opcode==3 ("REV64") */
4751 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4752 unsigned int rn
, unsigned int rd
)
4755 unallocated_encoding(s
);
4758 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4761 /* REV with sf==0, opcode==2
4762 * REV32 (sf==1, opcode==2)
4764 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4765 unsigned int rn
, unsigned int rd
)
4767 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4770 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4771 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4773 /* bswap32_i64 requires zero high word */
4774 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4775 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4776 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4777 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4778 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4780 tcg_temp_free_i64(tcg_tmp
);
4782 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4783 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4787 /* REV16 (opcode==1) */
4788 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4789 unsigned int rn
, unsigned int rd
)
4791 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4792 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4793 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4794 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4796 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4797 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4798 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4799 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4800 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4802 tcg_temp_free_i64(mask
);
4803 tcg_temp_free_i64(tcg_tmp
);
4806 /* Data-processing (1 source)
4807 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4808 * +----+---+---+-----------------+---------+--------+------+------+
4809 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4810 * +----+---+---+-----------------+---------+--------+------+------+
4812 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4814 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4817 if (extract32(insn
, 29, 1)) {
4818 unallocated_encoding(s
);
4822 sf
= extract32(insn
, 31, 1);
4823 opcode
= extract32(insn
, 10, 6);
4824 opcode2
= extract32(insn
, 16, 5);
4825 rn
= extract32(insn
, 5, 5);
4826 rd
= extract32(insn
, 0, 5);
4828 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4830 switch (MAP(sf
, opcode2
, opcode
)) {
4831 case MAP(0, 0x00, 0x00): /* RBIT */
4832 case MAP(1, 0x00, 0x00):
4833 handle_rbit(s
, sf
, rn
, rd
);
4835 case MAP(0, 0x00, 0x01): /* REV16 */
4836 case MAP(1, 0x00, 0x01):
4837 handle_rev16(s
, sf
, rn
, rd
);
4839 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4840 case MAP(1, 0x00, 0x02):
4841 handle_rev32(s
, sf
, rn
, rd
);
4843 case MAP(1, 0x00, 0x03): /* REV64 */
4844 handle_rev64(s
, sf
, rn
, rd
);
4846 case MAP(0, 0x00, 0x04): /* CLZ */
4847 case MAP(1, 0x00, 0x04):
4848 handle_clz(s
, sf
, rn
, rd
);
4850 case MAP(0, 0x00, 0x05): /* CLS */
4851 case MAP(1, 0x00, 0x05):
4852 handle_cls(s
, sf
, rn
, rd
);
4854 case MAP(1, 0x01, 0x00): /* PACIA */
4855 if (s
->pauth_active
) {
4856 tcg_rd
= cpu_reg(s
, rd
);
4857 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4858 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4859 goto do_unallocated
;
4862 case MAP(1, 0x01, 0x01): /* PACIB */
4863 if (s
->pauth_active
) {
4864 tcg_rd
= cpu_reg(s
, rd
);
4865 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4866 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4867 goto do_unallocated
;
4870 case MAP(1, 0x01, 0x02): /* PACDA */
4871 if (s
->pauth_active
) {
4872 tcg_rd
= cpu_reg(s
, rd
);
4873 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4874 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4875 goto do_unallocated
;
4878 case MAP(1, 0x01, 0x03): /* PACDB */
4879 if (s
->pauth_active
) {
4880 tcg_rd
= cpu_reg(s
, rd
);
4881 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4882 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4883 goto do_unallocated
;
4886 case MAP(1, 0x01, 0x04): /* AUTIA */
4887 if (s
->pauth_active
) {
4888 tcg_rd
= cpu_reg(s
, rd
);
4889 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4890 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4891 goto do_unallocated
;
4894 case MAP(1, 0x01, 0x05): /* AUTIB */
4895 if (s
->pauth_active
) {
4896 tcg_rd
= cpu_reg(s
, rd
);
4897 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4898 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4899 goto do_unallocated
;
4902 case MAP(1, 0x01, 0x06): /* AUTDA */
4903 if (s
->pauth_active
) {
4904 tcg_rd
= cpu_reg(s
, rd
);
4905 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4906 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4907 goto do_unallocated
;
4910 case MAP(1, 0x01, 0x07): /* AUTDB */
4911 if (s
->pauth_active
) {
4912 tcg_rd
= cpu_reg(s
, rd
);
4913 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4914 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4915 goto do_unallocated
;
4918 case MAP(1, 0x01, 0x08): /* PACIZA */
4919 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4920 goto do_unallocated
;
4921 } else if (s
->pauth_active
) {
4922 tcg_rd
= cpu_reg(s
, rd
);
4923 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4926 case MAP(1, 0x01, 0x09): /* PACIZB */
4927 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4928 goto do_unallocated
;
4929 } else if (s
->pauth_active
) {
4930 tcg_rd
= cpu_reg(s
, rd
);
4931 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4934 case MAP(1, 0x01, 0x0a): /* PACDZA */
4935 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4936 goto do_unallocated
;
4937 } else if (s
->pauth_active
) {
4938 tcg_rd
= cpu_reg(s
, rd
);
4939 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4942 case MAP(1, 0x01, 0x0b): /* PACDZB */
4943 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4944 goto do_unallocated
;
4945 } else if (s
->pauth_active
) {
4946 tcg_rd
= cpu_reg(s
, rd
);
4947 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4950 case MAP(1, 0x01, 0x0c): /* AUTIZA */
4951 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4952 goto do_unallocated
;
4953 } else if (s
->pauth_active
) {
4954 tcg_rd
= cpu_reg(s
, rd
);
4955 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4958 case MAP(1, 0x01, 0x0d): /* AUTIZB */
4959 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4960 goto do_unallocated
;
4961 } else if (s
->pauth_active
) {
4962 tcg_rd
= cpu_reg(s
, rd
);
4963 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4966 case MAP(1, 0x01, 0x0e): /* AUTDZA */
4967 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4968 goto do_unallocated
;
4969 } else if (s
->pauth_active
) {
4970 tcg_rd
= cpu_reg(s
, rd
);
4971 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4974 case MAP(1, 0x01, 0x0f): /* AUTDZB */
4975 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4976 goto do_unallocated
;
4977 } else if (s
->pauth_active
) {
4978 tcg_rd
= cpu_reg(s
, rd
);
4979 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4982 case MAP(1, 0x01, 0x10): /* XPACI */
4983 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4984 goto do_unallocated
;
4985 } else if (s
->pauth_active
) {
4986 tcg_rd
= cpu_reg(s
, rd
);
4987 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
4990 case MAP(1, 0x01, 0x11): /* XPACD */
4991 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4992 goto do_unallocated
;
4993 } else if (s
->pauth_active
) {
4994 tcg_rd
= cpu_reg(s
, rd
);
4995 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5000 unallocated_encoding(s
);
5007 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5008 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5010 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5011 tcg_rd
= cpu_reg(s
, rd
);
5013 if (!sf
&& is_signed
) {
5014 tcg_n
= new_tmp_a64(s
);
5015 tcg_m
= new_tmp_a64(s
);
5016 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5017 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5019 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5020 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5024 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5026 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5029 if (!sf
) { /* zero extend final result */
5030 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5034 /* LSLV, LSRV, ASRV, RORV */
5035 static void handle_shift_reg(DisasContext
*s
,
5036 enum a64_shift_type shift_type
, unsigned int sf
,
5037 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5039 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5040 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5041 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5043 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5044 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5045 tcg_temp_free_i64(tcg_shift
);
5048 /* CRC32[BHWX], CRC32C[BHWX] */
5049 static void handle_crc32(DisasContext
*s
,
5050 unsigned int sf
, unsigned int sz
, bool crc32c
,
5051 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5053 TCGv_i64 tcg_acc
, tcg_val
;
5056 if (!dc_isar_feature(aa64_crc32
, s
)
5057 || (sf
== 1 && sz
!= 3)
5058 || (sf
== 0 && sz
== 3)) {
5059 unallocated_encoding(s
);
5064 tcg_val
= cpu_reg(s
, rm
);
5078 g_assert_not_reached();
5080 tcg_val
= new_tmp_a64(s
);
5081 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5084 tcg_acc
= cpu_reg(s
, rn
);
5085 tcg_bytes
= tcg_const_i32(1 << sz
);
5088 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5090 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5093 tcg_temp_free_i32(tcg_bytes
);
5096 /* Data-processing (2 source)
5097 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5098 * +----+---+---+-----------------+------+--------+------+------+
5099 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5100 * +----+---+---+-----------------+------+--------+------+------+
5102 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5104 unsigned int sf
, rm
, opcode
, rn
, rd
;
5105 sf
= extract32(insn
, 31, 1);
5106 rm
= extract32(insn
, 16, 5);
5107 opcode
= extract32(insn
, 10, 6);
5108 rn
= extract32(insn
, 5, 5);
5109 rd
= extract32(insn
, 0, 5);
5111 if (extract32(insn
, 29, 1)) {
5112 unallocated_encoding(s
);
5118 handle_div(s
, false, sf
, rm
, rn
, rd
);
5121 handle_div(s
, true, sf
, rm
, rn
, rd
);
5124 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5127 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5130 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5133 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5135 case 12: /* PACGA */
5136 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5137 goto do_unallocated
;
5139 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5140 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5149 case 23: /* CRC32 */
5151 int sz
= extract32(opcode
, 0, 2);
5152 bool crc32c
= extract32(opcode
, 2, 1);
5153 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5158 unallocated_encoding(s
);
5164 * Data processing - register
5165 * 31 30 29 28 25 21 20 16 10 0
5166 * +--+---+--+---+-------+-----+-------+-------+---------+
5167 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5168 * +--+---+--+---+-------+-----+-------+-------+---------+
5170 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5172 int op0
= extract32(insn
, 30, 1);
5173 int op1
= extract32(insn
, 28, 1);
5174 int op2
= extract32(insn
, 21, 4);
5175 int op3
= extract32(insn
, 10, 6);
5180 /* Add/sub (extended register) */
5181 disas_add_sub_ext_reg(s
, insn
);
5183 /* Add/sub (shifted register) */
5184 disas_add_sub_reg(s
, insn
);
5187 /* Logical (shifted register) */
5188 disas_logic_reg(s
, insn
);
5196 case 0x00: /* Add/subtract (with carry) */
5197 disas_adc_sbc(s
, insn
);
5200 case 0x01: /* Rotate right into flags */
5202 disas_rotate_right_into_flags(s
, insn
);
5205 case 0x02: /* Evaluate into flags */
5209 disas_evaluate_into_flags(s
, insn
);
5213 goto do_unallocated
;
5217 case 0x2: /* Conditional compare */
5218 disas_cc(s
, insn
); /* both imm and reg forms */
5221 case 0x4: /* Conditional select */
5222 disas_cond_select(s
, insn
);
5225 case 0x6: /* Data-processing */
5226 if (op0
) { /* (1 source) */
5227 disas_data_proc_1src(s
, insn
);
5228 } else { /* (2 source) */
5229 disas_data_proc_2src(s
, insn
);
5232 case 0x8 ... 0xf: /* (3 source) */
5233 disas_data_proc_3src(s
, insn
);
5238 unallocated_encoding(s
);
5243 static void handle_fp_compare(DisasContext
*s
, int size
,
5244 unsigned int rn
, unsigned int rm
,
5245 bool cmp_with_zero
, bool signal_all_nans
)
5247 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5248 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5250 if (size
== MO_64
) {
5251 TCGv_i64 tcg_vn
, tcg_vm
;
5253 tcg_vn
= read_fp_dreg(s
, rn
);
5254 if (cmp_with_zero
) {
5255 tcg_vm
= tcg_const_i64(0);
5257 tcg_vm
= read_fp_dreg(s
, rm
);
5259 if (signal_all_nans
) {
5260 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5262 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5264 tcg_temp_free_i64(tcg_vn
);
5265 tcg_temp_free_i64(tcg_vm
);
5267 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5268 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5270 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5271 if (cmp_with_zero
) {
5272 tcg_gen_movi_i32(tcg_vm
, 0);
5274 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5279 if (signal_all_nans
) {
5280 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5282 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5286 if (signal_all_nans
) {
5287 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5289 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5293 g_assert_not_reached();
5296 tcg_temp_free_i32(tcg_vn
);
5297 tcg_temp_free_i32(tcg_vm
);
5300 tcg_temp_free_ptr(fpst
);
5302 gen_set_nzcv(tcg_flags
);
5304 tcg_temp_free_i64(tcg_flags
);
5307 /* Floating point compare
5308 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5309 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5310 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5311 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5313 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5315 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5318 mos
= extract32(insn
, 29, 3);
5319 type
= extract32(insn
, 22, 2);
5320 rm
= extract32(insn
, 16, 5);
5321 op
= extract32(insn
, 14, 2);
5322 rn
= extract32(insn
, 5, 5);
5323 opc
= extract32(insn
, 3, 2);
5324 op2r
= extract32(insn
, 0, 3);
5326 if (mos
|| op
|| op2r
) {
5327 unallocated_encoding(s
);
5340 if (dc_isar_feature(aa64_fp16
, s
)) {
5345 unallocated_encoding(s
);
5349 if (!fp_access_check(s
)) {
5353 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5356 /* Floating point conditional compare
5357 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5358 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5359 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5360 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5362 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5364 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5366 TCGLabel
*label_continue
= NULL
;
5369 mos
= extract32(insn
, 29, 3);
5370 type
= extract32(insn
, 22, 2);
5371 rm
= extract32(insn
, 16, 5);
5372 cond
= extract32(insn
, 12, 4);
5373 rn
= extract32(insn
, 5, 5);
5374 op
= extract32(insn
, 4, 1);
5375 nzcv
= extract32(insn
, 0, 4);
5378 unallocated_encoding(s
);
5391 if (dc_isar_feature(aa64_fp16
, s
)) {
5396 unallocated_encoding(s
);
5400 if (!fp_access_check(s
)) {
5404 if (cond
< 0x0e) { /* not always */
5405 TCGLabel
*label_match
= gen_new_label();
5406 label_continue
= gen_new_label();
5407 arm_gen_test_cc(cond
, label_match
);
5409 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5410 gen_set_nzcv(tcg_flags
);
5411 tcg_temp_free_i64(tcg_flags
);
5412 tcg_gen_br(label_continue
);
5413 gen_set_label(label_match
);
5416 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5419 gen_set_label(label_continue
);
5423 /* Floating point conditional select
5424 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5425 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5426 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5427 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5429 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5431 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5432 TCGv_i64 t_true
, t_false
, t_zero
;
5436 mos
= extract32(insn
, 29, 3);
5437 type
= extract32(insn
, 22, 2);
5438 rm
= extract32(insn
, 16, 5);
5439 cond
= extract32(insn
, 12, 4);
5440 rn
= extract32(insn
, 5, 5);
5441 rd
= extract32(insn
, 0, 5);
5444 unallocated_encoding(s
);
5457 if (dc_isar_feature(aa64_fp16
, s
)) {
5462 unallocated_encoding(s
);
5466 if (!fp_access_check(s
)) {
5470 /* Zero extend sreg & hreg inputs to 64 bits now. */
5471 t_true
= tcg_temp_new_i64();
5472 t_false
= tcg_temp_new_i64();
5473 read_vec_element(s
, t_true
, rn
, 0, sz
);
5474 read_vec_element(s
, t_false
, rm
, 0, sz
);
5476 a64_test_cc(&c
, cond
);
5477 t_zero
= tcg_const_i64(0);
5478 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5479 tcg_temp_free_i64(t_zero
);
5480 tcg_temp_free_i64(t_false
);
5483 /* Note that sregs & hregs write back zeros to the high bits,
5484 and we've already done the zero-extension. */
5485 write_fp_dreg(s
, rd
, t_true
);
5486 tcg_temp_free_i64(t_true
);
5489 /* Floating-point data-processing (1 source) - half precision */
5490 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5492 TCGv_ptr fpst
= NULL
;
5493 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5494 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5497 case 0x0: /* FMOV */
5498 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5500 case 0x1: /* FABS */
5501 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5503 case 0x2: /* FNEG */
5504 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5506 case 0x3: /* FSQRT */
5507 fpst
= get_fpstatus_ptr(true);
5508 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5510 case 0x8: /* FRINTN */
5511 case 0x9: /* FRINTP */
5512 case 0xa: /* FRINTM */
5513 case 0xb: /* FRINTZ */
5514 case 0xc: /* FRINTA */
5516 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5517 fpst
= get_fpstatus_ptr(true);
5519 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5520 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5522 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5523 tcg_temp_free_i32(tcg_rmode
);
5526 case 0xe: /* FRINTX */
5527 fpst
= get_fpstatus_ptr(true);
5528 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5530 case 0xf: /* FRINTI */
5531 fpst
= get_fpstatus_ptr(true);
5532 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5538 write_fp_sreg(s
, rd
, tcg_res
);
5541 tcg_temp_free_ptr(fpst
);
5543 tcg_temp_free_i32(tcg_op
);
5544 tcg_temp_free_i32(tcg_res
);
5547 /* Floating-point data-processing (1 source) - single precision */
5548 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5550 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5551 TCGv_i32 tcg_op
, tcg_res
;
5555 tcg_op
= read_fp_sreg(s
, rn
);
5556 tcg_res
= tcg_temp_new_i32();
5559 case 0x0: /* FMOV */
5560 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5562 case 0x1: /* FABS */
5563 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5565 case 0x2: /* FNEG */
5566 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5568 case 0x3: /* FSQRT */
5569 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5571 case 0x8: /* FRINTN */
5572 case 0x9: /* FRINTP */
5573 case 0xa: /* FRINTM */
5574 case 0xb: /* FRINTZ */
5575 case 0xc: /* FRINTA */
5576 rmode
= arm_rmode_to_sf(opcode
& 7);
5577 gen_fpst
= gen_helper_rints
;
5579 case 0xe: /* FRINTX */
5580 gen_fpst
= gen_helper_rints_exact
;
5582 case 0xf: /* FRINTI */
5583 gen_fpst
= gen_helper_rints
;
5585 case 0x10: /* FRINT32Z */
5586 rmode
= float_round_to_zero
;
5587 gen_fpst
= gen_helper_frint32_s
;
5589 case 0x11: /* FRINT32X */
5590 gen_fpst
= gen_helper_frint32_s
;
5592 case 0x12: /* FRINT64Z */
5593 rmode
= float_round_to_zero
;
5594 gen_fpst
= gen_helper_frint64_s
;
5596 case 0x13: /* FRINT64X */
5597 gen_fpst
= gen_helper_frint64_s
;
5600 g_assert_not_reached();
5603 fpst
= get_fpstatus_ptr(false);
5605 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5606 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5607 gen_fpst(tcg_res
, tcg_op
, fpst
);
5608 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5609 tcg_temp_free_i32(tcg_rmode
);
5611 gen_fpst(tcg_res
, tcg_op
, fpst
);
5613 tcg_temp_free_ptr(fpst
);
5616 write_fp_sreg(s
, rd
, tcg_res
);
5617 tcg_temp_free_i32(tcg_op
);
5618 tcg_temp_free_i32(tcg_res
);
5621 /* Floating-point data-processing (1 source) - double precision */
5622 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5624 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5625 TCGv_i64 tcg_op
, tcg_res
;
5630 case 0x0: /* FMOV */
5631 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5635 tcg_op
= read_fp_dreg(s
, rn
);
5636 tcg_res
= tcg_temp_new_i64();
5639 case 0x1: /* FABS */
5640 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5642 case 0x2: /* FNEG */
5643 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5645 case 0x3: /* FSQRT */
5646 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5648 case 0x8: /* FRINTN */
5649 case 0x9: /* FRINTP */
5650 case 0xa: /* FRINTM */
5651 case 0xb: /* FRINTZ */
5652 case 0xc: /* FRINTA */
5653 rmode
= arm_rmode_to_sf(opcode
& 7);
5654 gen_fpst
= gen_helper_rintd
;
5656 case 0xe: /* FRINTX */
5657 gen_fpst
= gen_helper_rintd_exact
;
5659 case 0xf: /* FRINTI */
5660 gen_fpst
= gen_helper_rintd
;
5662 case 0x10: /* FRINT32Z */
5663 rmode
= float_round_to_zero
;
5664 gen_fpst
= gen_helper_frint32_d
;
5666 case 0x11: /* FRINT32X */
5667 gen_fpst
= gen_helper_frint32_d
;
5669 case 0x12: /* FRINT64Z */
5670 rmode
= float_round_to_zero
;
5671 gen_fpst
= gen_helper_frint64_d
;
5673 case 0x13: /* FRINT64X */
5674 gen_fpst
= gen_helper_frint64_d
;
5677 g_assert_not_reached();
5680 fpst
= get_fpstatus_ptr(false);
5682 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5683 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5684 gen_fpst(tcg_res
, tcg_op
, fpst
);
5685 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5686 tcg_temp_free_i32(tcg_rmode
);
5688 gen_fpst(tcg_res
, tcg_op
, fpst
);
5690 tcg_temp_free_ptr(fpst
);
5693 write_fp_dreg(s
, rd
, tcg_res
);
5694 tcg_temp_free_i64(tcg_op
);
5695 tcg_temp_free_i64(tcg_res
);
5698 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5699 int rd
, int rn
, int dtype
, int ntype
)
5704 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5706 /* Single to double */
5707 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5708 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5709 write_fp_dreg(s
, rd
, tcg_rd
);
5710 tcg_temp_free_i64(tcg_rd
);
5712 /* Single to half */
5713 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5714 TCGv_i32 ahp
= get_ahp_flag();
5715 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5717 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5718 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5719 write_fp_sreg(s
, rd
, tcg_rd
);
5720 tcg_temp_free_i32(tcg_rd
);
5721 tcg_temp_free_i32(ahp
);
5722 tcg_temp_free_ptr(fpst
);
5724 tcg_temp_free_i32(tcg_rn
);
5729 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5730 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5732 /* Double to single */
5733 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5735 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5736 TCGv_i32 ahp
= get_ahp_flag();
5737 /* Double to half */
5738 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5739 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5740 tcg_temp_free_ptr(fpst
);
5741 tcg_temp_free_i32(ahp
);
5743 write_fp_sreg(s
, rd
, tcg_rd
);
5744 tcg_temp_free_i32(tcg_rd
);
5745 tcg_temp_free_i64(tcg_rn
);
5750 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5751 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5752 TCGv_i32 tcg_ahp
= get_ahp_flag();
5753 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5755 /* Half to single */
5756 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5757 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5758 write_fp_sreg(s
, rd
, tcg_rd
);
5759 tcg_temp_free_ptr(tcg_fpst
);
5760 tcg_temp_free_i32(tcg_ahp
);
5761 tcg_temp_free_i32(tcg_rd
);
5763 /* Half to double */
5764 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5765 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5766 write_fp_dreg(s
, rd
, tcg_rd
);
5767 tcg_temp_free_i64(tcg_rd
);
5769 tcg_temp_free_i32(tcg_rn
);
5777 /* Floating point data-processing (1 source)
5778 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5779 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5780 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5781 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5783 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5785 int mos
= extract32(insn
, 29, 3);
5786 int type
= extract32(insn
, 22, 2);
5787 int opcode
= extract32(insn
, 15, 6);
5788 int rn
= extract32(insn
, 5, 5);
5789 int rd
= extract32(insn
, 0, 5);
5792 unallocated_encoding(s
);
5797 case 0x4: case 0x5: case 0x7:
5799 /* FCVT between half, single and double precision */
5800 int dtype
= extract32(opcode
, 0, 2);
5801 if (type
== 2 || dtype
== type
) {
5802 unallocated_encoding(s
);
5805 if (!fp_access_check(s
)) {
5809 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5813 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5814 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5815 unallocated_encoding(s
);
5822 /* 32-to-32 and 64-to-64 ops */
5825 if (!fp_access_check(s
)) {
5828 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5831 if (!fp_access_check(s
)) {
5834 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5837 if (!dc_isar_feature(aa64_fp16
, s
)) {
5838 unallocated_encoding(s
);
5842 if (!fp_access_check(s
)) {
5845 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5848 unallocated_encoding(s
);
5853 unallocated_encoding(s
);
5858 /* Floating-point data-processing (2 source) - single precision */
5859 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5860 int rd
, int rn
, int rm
)
5867 tcg_res
= tcg_temp_new_i32();
5868 fpst
= get_fpstatus_ptr(false);
5869 tcg_op1
= read_fp_sreg(s
, rn
);
5870 tcg_op2
= read_fp_sreg(s
, rm
);
5873 case 0x0: /* FMUL */
5874 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5876 case 0x1: /* FDIV */
5877 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5879 case 0x2: /* FADD */
5880 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5882 case 0x3: /* FSUB */
5883 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5885 case 0x4: /* FMAX */
5886 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5888 case 0x5: /* FMIN */
5889 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5891 case 0x6: /* FMAXNM */
5892 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5894 case 0x7: /* FMINNM */
5895 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5897 case 0x8: /* FNMUL */
5898 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5899 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5903 write_fp_sreg(s
, rd
, tcg_res
);
5905 tcg_temp_free_ptr(fpst
);
5906 tcg_temp_free_i32(tcg_op1
);
5907 tcg_temp_free_i32(tcg_op2
);
5908 tcg_temp_free_i32(tcg_res
);
5911 /* Floating-point data-processing (2 source) - double precision */
5912 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5913 int rd
, int rn
, int rm
)
5920 tcg_res
= tcg_temp_new_i64();
5921 fpst
= get_fpstatus_ptr(false);
5922 tcg_op1
= read_fp_dreg(s
, rn
);
5923 tcg_op2
= read_fp_dreg(s
, rm
);
5926 case 0x0: /* FMUL */
5927 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5929 case 0x1: /* FDIV */
5930 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5932 case 0x2: /* FADD */
5933 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5935 case 0x3: /* FSUB */
5936 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5938 case 0x4: /* FMAX */
5939 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5941 case 0x5: /* FMIN */
5942 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5944 case 0x6: /* FMAXNM */
5945 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5947 case 0x7: /* FMINNM */
5948 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5950 case 0x8: /* FNMUL */
5951 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5952 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5956 write_fp_dreg(s
, rd
, tcg_res
);
5958 tcg_temp_free_ptr(fpst
);
5959 tcg_temp_free_i64(tcg_op1
);
5960 tcg_temp_free_i64(tcg_op2
);
5961 tcg_temp_free_i64(tcg_res
);
5964 /* Floating-point data-processing (2 source) - half precision */
5965 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5966 int rd
, int rn
, int rm
)
5973 tcg_res
= tcg_temp_new_i32();
5974 fpst
= get_fpstatus_ptr(true);
5975 tcg_op1
= read_fp_hreg(s
, rn
);
5976 tcg_op2
= read_fp_hreg(s
, rm
);
5979 case 0x0: /* FMUL */
5980 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5982 case 0x1: /* FDIV */
5983 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5985 case 0x2: /* FADD */
5986 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5988 case 0x3: /* FSUB */
5989 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5991 case 0x4: /* FMAX */
5992 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5994 case 0x5: /* FMIN */
5995 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5997 case 0x6: /* FMAXNM */
5998 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6000 case 0x7: /* FMINNM */
6001 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6003 case 0x8: /* FNMUL */
6004 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6005 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6008 g_assert_not_reached();
6011 write_fp_sreg(s
, rd
, tcg_res
);
6013 tcg_temp_free_ptr(fpst
);
6014 tcg_temp_free_i32(tcg_op1
);
6015 tcg_temp_free_i32(tcg_op2
);
6016 tcg_temp_free_i32(tcg_res
);
6019 /* Floating point data-processing (2 source)
6020 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6021 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6022 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6023 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6025 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6027 int mos
= extract32(insn
, 29, 3);
6028 int type
= extract32(insn
, 22, 2);
6029 int rd
= extract32(insn
, 0, 5);
6030 int rn
= extract32(insn
, 5, 5);
6031 int rm
= extract32(insn
, 16, 5);
6032 int opcode
= extract32(insn
, 12, 4);
6034 if (opcode
> 8 || mos
) {
6035 unallocated_encoding(s
);
6041 if (!fp_access_check(s
)) {
6044 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6047 if (!fp_access_check(s
)) {
6050 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6053 if (!dc_isar_feature(aa64_fp16
, s
)) {
6054 unallocated_encoding(s
);
6057 if (!fp_access_check(s
)) {
6060 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6063 unallocated_encoding(s
);
6067 /* Floating-point data-processing (3 source) - single precision */
6068 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6069 int rd
, int rn
, int rm
, int ra
)
6071 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6072 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6073 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6075 tcg_op1
= read_fp_sreg(s
, rn
);
6076 tcg_op2
= read_fp_sreg(s
, rm
);
6077 tcg_op3
= read_fp_sreg(s
, ra
);
6079 /* These are fused multiply-add, and must be done as one
6080 * floating point operation with no rounding between the
6081 * multiplication and addition steps.
6082 * NB that doing the negations here as separate steps is
6083 * correct : an input NaN should come out with its sign bit
6084 * flipped if it is a negated-input.
6087 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6091 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6094 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6096 write_fp_sreg(s
, rd
, tcg_res
);
6098 tcg_temp_free_ptr(fpst
);
6099 tcg_temp_free_i32(tcg_op1
);
6100 tcg_temp_free_i32(tcg_op2
);
6101 tcg_temp_free_i32(tcg_op3
);
6102 tcg_temp_free_i32(tcg_res
);
6105 /* Floating-point data-processing (3 source) - double precision */
6106 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6107 int rd
, int rn
, int rm
, int ra
)
6109 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6110 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6111 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6113 tcg_op1
= read_fp_dreg(s
, rn
);
6114 tcg_op2
= read_fp_dreg(s
, rm
);
6115 tcg_op3
= read_fp_dreg(s
, ra
);
6117 /* These are fused multiply-add, and must be done as one
6118 * floating point operation with no rounding between the
6119 * multiplication and addition steps.
6120 * NB that doing the negations here as separate steps is
6121 * correct : an input NaN should come out with its sign bit
6122 * flipped if it is a negated-input.
6125 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6129 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6132 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6134 write_fp_dreg(s
, rd
, tcg_res
);
6136 tcg_temp_free_ptr(fpst
);
6137 tcg_temp_free_i64(tcg_op1
);
6138 tcg_temp_free_i64(tcg_op2
);
6139 tcg_temp_free_i64(tcg_op3
);
6140 tcg_temp_free_i64(tcg_res
);
6143 /* Floating-point data-processing (3 source) - half precision */
6144 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6145 int rd
, int rn
, int rm
, int ra
)
6147 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6148 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6149 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6151 tcg_op1
= read_fp_hreg(s
, rn
);
6152 tcg_op2
= read_fp_hreg(s
, rm
);
6153 tcg_op3
= read_fp_hreg(s
, ra
);
6155 /* These are fused multiply-add, and must be done as one
6156 * floating point operation with no rounding between the
6157 * multiplication and addition steps.
6158 * NB that doing the negations here as separate steps is
6159 * correct : an input NaN should come out with its sign bit
6160 * flipped if it is a negated-input.
6163 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6167 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6170 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6172 write_fp_sreg(s
, rd
, tcg_res
);
6174 tcg_temp_free_ptr(fpst
);
6175 tcg_temp_free_i32(tcg_op1
);
6176 tcg_temp_free_i32(tcg_op2
);
6177 tcg_temp_free_i32(tcg_op3
);
6178 tcg_temp_free_i32(tcg_res
);
6181 /* Floating point data-processing (3 source)
6182 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6183 * +---+---+---+-----------+------+----+------+----+------+------+------+
6184 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6185 * +---+---+---+-----------+------+----+------+----+------+------+------+
6187 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6189 int mos
= extract32(insn
, 29, 3);
6190 int type
= extract32(insn
, 22, 2);
6191 int rd
= extract32(insn
, 0, 5);
6192 int rn
= extract32(insn
, 5, 5);
6193 int ra
= extract32(insn
, 10, 5);
6194 int rm
= extract32(insn
, 16, 5);
6195 bool o0
= extract32(insn
, 15, 1);
6196 bool o1
= extract32(insn
, 21, 1);
6199 unallocated_encoding(s
);
6205 if (!fp_access_check(s
)) {
6208 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6211 if (!fp_access_check(s
)) {
6214 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6217 if (!dc_isar_feature(aa64_fp16
, s
)) {
6218 unallocated_encoding(s
);
6221 if (!fp_access_check(s
)) {
6224 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6227 unallocated_encoding(s
);
6231 /* Floating point immediate
6232 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6233 * +---+---+---+-----------+------+---+------------+-------+------+------+
6234 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6235 * +---+---+---+-----------+------+---+------------+-------+------+------+
6237 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6239 int rd
= extract32(insn
, 0, 5);
6240 int imm5
= extract32(insn
, 5, 5);
6241 int imm8
= extract32(insn
, 13, 8);
6242 int type
= extract32(insn
, 22, 2);
6243 int mos
= extract32(insn
, 29, 3);
6249 unallocated_encoding(s
);
6262 if (dc_isar_feature(aa64_fp16
, s
)) {
6267 unallocated_encoding(s
);
6271 if (!fp_access_check(s
)) {
6275 imm
= vfp_expand_imm(sz
, imm8
);
6277 tcg_res
= tcg_const_i64(imm
);
6278 write_fp_dreg(s
, rd
, tcg_res
);
6279 tcg_temp_free_i64(tcg_res
);
6282 /* Handle floating point <=> fixed point conversions. Note that we can
6283 * also deal with fp <=> integer conversions as a special case (scale == 64)
6284 * OPTME: consider handling that special case specially or at least skipping
6285 * the call to scalbn in the helpers for zero shifts.
6287 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6288 bool itof
, int rmode
, int scale
, int sf
, int type
)
6290 bool is_signed
= !(opcode
& 1);
6291 TCGv_ptr tcg_fpstatus
;
6292 TCGv_i32 tcg_shift
, tcg_single
;
6293 TCGv_i64 tcg_double
;
6295 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6297 tcg_shift
= tcg_const_i32(64 - scale
);
6300 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6302 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6305 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6307 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6310 tcg_int
= tcg_extend
;
6314 case 1: /* float64 */
6315 tcg_double
= tcg_temp_new_i64();
6317 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6318 tcg_shift
, tcg_fpstatus
);
6320 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6321 tcg_shift
, tcg_fpstatus
);
6323 write_fp_dreg(s
, rd
, tcg_double
);
6324 tcg_temp_free_i64(tcg_double
);
6327 case 0: /* float32 */
6328 tcg_single
= tcg_temp_new_i32();
6330 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6331 tcg_shift
, tcg_fpstatus
);
6333 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6334 tcg_shift
, tcg_fpstatus
);
6336 write_fp_sreg(s
, rd
, tcg_single
);
6337 tcg_temp_free_i32(tcg_single
);
6340 case 3: /* float16 */
6341 tcg_single
= tcg_temp_new_i32();
6343 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6344 tcg_shift
, tcg_fpstatus
);
6346 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6347 tcg_shift
, tcg_fpstatus
);
6349 write_fp_sreg(s
, rd
, tcg_single
);
6350 tcg_temp_free_i32(tcg_single
);
6354 g_assert_not_reached();
6357 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6360 if (extract32(opcode
, 2, 1)) {
6361 /* There are too many rounding modes to all fit into rmode,
6362 * so FCVTA[US] is a special case.
6364 rmode
= FPROUNDING_TIEAWAY
;
6367 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6369 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6372 case 1: /* float64 */
6373 tcg_double
= read_fp_dreg(s
, rn
);
6376 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6377 tcg_shift
, tcg_fpstatus
);
6379 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6380 tcg_shift
, tcg_fpstatus
);
6384 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6385 tcg_shift
, tcg_fpstatus
);
6387 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6388 tcg_shift
, tcg_fpstatus
);
6392 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6394 tcg_temp_free_i64(tcg_double
);
6397 case 0: /* float32 */
6398 tcg_single
= read_fp_sreg(s
, rn
);
6401 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6402 tcg_shift
, tcg_fpstatus
);
6404 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6405 tcg_shift
, tcg_fpstatus
);
6408 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6410 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6411 tcg_shift
, tcg_fpstatus
);
6413 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6414 tcg_shift
, tcg_fpstatus
);
6416 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6417 tcg_temp_free_i32(tcg_dest
);
6419 tcg_temp_free_i32(tcg_single
);
6422 case 3: /* float16 */
6423 tcg_single
= read_fp_sreg(s
, rn
);
6426 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6427 tcg_shift
, tcg_fpstatus
);
6429 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6430 tcg_shift
, tcg_fpstatus
);
6433 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6435 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6436 tcg_shift
, tcg_fpstatus
);
6438 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6439 tcg_shift
, tcg_fpstatus
);
6441 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6442 tcg_temp_free_i32(tcg_dest
);
6444 tcg_temp_free_i32(tcg_single
);
6448 g_assert_not_reached();
6451 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6452 tcg_temp_free_i32(tcg_rmode
);
6455 tcg_temp_free_ptr(tcg_fpstatus
);
6456 tcg_temp_free_i32(tcg_shift
);
6459 /* Floating point <-> fixed point conversions
6460 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6461 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6462 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6463 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6465 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6467 int rd
= extract32(insn
, 0, 5);
6468 int rn
= extract32(insn
, 5, 5);
6469 int scale
= extract32(insn
, 10, 6);
6470 int opcode
= extract32(insn
, 16, 3);
6471 int rmode
= extract32(insn
, 19, 2);
6472 int type
= extract32(insn
, 22, 2);
6473 bool sbit
= extract32(insn
, 29, 1);
6474 bool sf
= extract32(insn
, 31, 1);
6477 if (sbit
|| (!sf
&& scale
< 32)) {
6478 unallocated_encoding(s
);
6483 case 0: /* float32 */
6484 case 1: /* float64 */
6486 case 3: /* float16 */
6487 if (dc_isar_feature(aa64_fp16
, s
)) {
6492 unallocated_encoding(s
);
6496 switch ((rmode
<< 3) | opcode
) {
6497 case 0x2: /* SCVTF */
6498 case 0x3: /* UCVTF */
6501 case 0x18: /* FCVTZS */
6502 case 0x19: /* FCVTZU */
6506 unallocated_encoding(s
);
6510 if (!fp_access_check(s
)) {
6514 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6517 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6519 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6520 * without conversion.
6524 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6530 tmp
= tcg_temp_new_i64();
6531 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6532 write_fp_dreg(s
, rd
, tmp
);
6533 tcg_temp_free_i64(tmp
);
6537 write_fp_dreg(s
, rd
, tcg_rn
);
6540 /* 64 bit to top half. */
6541 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6542 clear_vec_high(s
, true, rd
);
6546 tmp
= tcg_temp_new_i64();
6547 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6548 write_fp_dreg(s
, rd
, tmp
);
6549 tcg_temp_free_i64(tmp
);
6552 g_assert_not_reached();
6555 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6560 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6564 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6567 /* 64 bits from top half */
6568 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6572 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6575 g_assert_not_reached();
6580 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6582 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6583 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6585 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6587 tcg_temp_free_ptr(fpstatus
);
6589 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6590 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6591 tcg_gen_movi_i32(cpu_CF
, 0);
6592 tcg_gen_movi_i32(cpu_NF
, 0);
6593 tcg_gen_movi_i32(cpu_VF
, 0);
6595 tcg_temp_free_i64(t
);
6598 /* Floating point <-> integer conversions
6599 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6600 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6601 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6602 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6604 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6606 int rd
= extract32(insn
, 0, 5);
6607 int rn
= extract32(insn
, 5, 5);
6608 int opcode
= extract32(insn
, 16, 3);
6609 int rmode
= extract32(insn
, 19, 2);
6610 int type
= extract32(insn
, 22, 2);
6611 bool sbit
= extract32(insn
, 29, 1);
6612 bool sf
= extract32(insn
, 31, 1);
6616 goto do_unallocated
;
6624 case 4: /* FCVTAS */
6625 case 5: /* FCVTAU */
6627 goto do_unallocated
;
6630 case 0: /* FCVT[NPMZ]S */
6631 case 1: /* FCVT[NPMZ]U */
6633 case 0: /* float32 */
6634 case 1: /* float64 */
6636 case 3: /* float16 */
6637 if (!dc_isar_feature(aa64_fp16
, s
)) {
6638 goto do_unallocated
;
6642 goto do_unallocated
;
6644 if (!fp_access_check(s
)) {
6647 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6651 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6652 case 0b01100110: /* FMOV half <-> 32-bit int */
6654 case 0b11100110: /* FMOV half <-> 64-bit int */
6656 if (!dc_isar_feature(aa64_fp16
, s
)) {
6657 goto do_unallocated
;
6660 case 0b00000110: /* FMOV 32-bit */
6662 case 0b10100110: /* FMOV 64-bit */
6664 case 0b11001110: /* FMOV top half of 128-bit */
6666 if (!fp_access_check(s
)) {
6670 handle_fmov(s
, rd
, rn
, type
, itof
);
6673 case 0b00111110: /* FJCVTZS */
6674 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6675 goto do_unallocated
;
6676 } else if (fp_access_check(s
)) {
6677 handle_fjcvtzs(s
, rd
, rn
);
6683 unallocated_encoding(s
);
6690 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6691 * 31 30 29 28 25 24 0
6692 * +---+---+---+---------+-----------------------------+
6693 * | | 0 | | 1 1 1 1 | |
6694 * +---+---+---+---------+-----------------------------+
6696 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6698 if (extract32(insn
, 24, 1)) {
6699 /* Floating point data-processing (3 source) */
6700 disas_fp_3src(s
, insn
);
6701 } else if (extract32(insn
, 21, 1) == 0) {
6702 /* Floating point to fixed point conversions */
6703 disas_fp_fixed_conv(s
, insn
);
6705 switch (extract32(insn
, 10, 2)) {
6707 /* Floating point conditional compare */
6708 disas_fp_ccomp(s
, insn
);
6711 /* Floating point data-processing (2 source) */
6712 disas_fp_2src(s
, insn
);
6715 /* Floating point conditional select */
6716 disas_fp_csel(s
, insn
);
6719 switch (ctz32(extract32(insn
, 12, 4))) {
6720 case 0: /* [15:12] == xxx1 */
6721 /* Floating point immediate */
6722 disas_fp_imm(s
, insn
);
6724 case 1: /* [15:12] == xx10 */
6725 /* Floating point compare */
6726 disas_fp_compare(s
, insn
);
6728 case 2: /* [15:12] == x100 */
6729 /* Floating point data-processing (1 source) */
6730 disas_fp_1src(s
, insn
);
6732 case 3: /* [15:12] == 1000 */
6733 unallocated_encoding(s
);
6735 default: /* [15:12] == 0000 */
6736 /* Floating point <-> integer conversions */
6737 disas_fp_int_conv(s
, insn
);
6745 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6748 /* Extract 64 bits from the middle of two concatenated 64 bit
6749 * vector register slices left:right. The extracted bits start
6750 * at 'pos' bits into the right (least significant) side.
6751 * We return the result in tcg_right, and guarantee not to
6754 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6755 assert(pos
> 0 && pos
< 64);
6757 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6758 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6759 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6761 tcg_temp_free_i64(tcg_tmp
);
6765 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6766 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6767 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6768 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6770 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6772 int is_q
= extract32(insn
, 30, 1);
6773 int op2
= extract32(insn
, 22, 2);
6774 int imm4
= extract32(insn
, 11, 4);
6775 int rm
= extract32(insn
, 16, 5);
6776 int rn
= extract32(insn
, 5, 5);
6777 int rd
= extract32(insn
, 0, 5);
6778 int pos
= imm4
<< 3;
6779 TCGv_i64 tcg_resl
, tcg_resh
;
6781 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6782 unallocated_encoding(s
);
6786 if (!fp_access_check(s
)) {
6790 tcg_resh
= tcg_temp_new_i64();
6791 tcg_resl
= tcg_temp_new_i64();
6793 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6794 * either extracting 128 bits from a 128:128 concatenation, or
6795 * extracting 64 bits from a 64:64 concatenation.
6798 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6800 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6801 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6803 tcg_gen_movi_i64(tcg_resh
, 0);
6810 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6811 EltPosns
*elt
= eltposns
;
6818 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6820 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6823 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6824 tcg_hh
= tcg_temp_new_i64();
6825 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6826 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6827 tcg_temp_free_i64(tcg_hh
);
6831 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6832 tcg_temp_free_i64(tcg_resl
);
6833 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6834 tcg_temp_free_i64(tcg_resh
);
6838 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6839 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6840 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6841 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6843 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6845 int op2
= extract32(insn
, 22, 2);
6846 int is_q
= extract32(insn
, 30, 1);
6847 int rm
= extract32(insn
, 16, 5);
6848 int rn
= extract32(insn
, 5, 5);
6849 int rd
= extract32(insn
, 0, 5);
6850 int is_tblx
= extract32(insn
, 12, 1);
6851 int len
= extract32(insn
, 13, 2);
6852 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6853 TCGv_i32 tcg_regno
, tcg_numregs
;
6856 unallocated_encoding(s
);
6860 if (!fp_access_check(s
)) {
6864 /* This does a table lookup: for every byte element in the input
6865 * we index into a table formed from up to four vector registers,
6866 * and then the output is the result of the lookups. Our helper
6867 * function does the lookup operation for a single 64 bit part of
6870 tcg_resl
= tcg_temp_new_i64();
6871 tcg_resh
= tcg_temp_new_i64();
6874 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6876 tcg_gen_movi_i64(tcg_resl
, 0);
6878 if (is_tblx
&& is_q
) {
6879 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6881 tcg_gen_movi_i64(tcg_resh
, 0);
6884 tcg_idx
= tcg_temp_new_i64();
6885 tcg_regno
= tcg_const_i32(rn
);
6886 tcg_numregs
= tcg_const_i32(len
+ 1);
6887 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6888 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6889 tcg_regno
, tcg_numregs
);
6891 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6892 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6893 tcg_regno
, tcg_numregs
);
6895 tcg_temp_free_i64(tcg_idx
);
6896 tcg_temp_free_i32(tcg_regno
);
6897 tcg_temp_free_i32(tcg_numregs
);
6899 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6900 tcg_temp_free_i64(tcg_resl
);
6901 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6902 tcg_temp_free_i64(tcg_resh
);
6906 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6907 * +---+---+-------------+------+---+------+---+------------------+------+
6908 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6909 * +---+---+-------------+------+---+------+---+------------------+------+
6911 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6913 int rd
= extract32(insn
, 0, 5);
6914 int rn
= extract32(insn
, 5, 5);
6915 int rm
= extract32(insn
, 16, 5);
6916 int size
= extract32(insn
, 22, 2);
6917 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6918 * bit 2 indicates 1 vs 2 variant of the insn.
6920 int opcode
= extract32(insn
, 12, 2);
6921 bool part
= extract32(insn
, 14, 1);
6922 bool is_q
= extract32(insn
, 30, 1);
6923 int esize
= 8 << size
;
6925 int datasize
= is_q
? 128 : 64;
6926 int elements
= datasize
/ esize
;
6927 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6929 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6930 unallocated_encoding(s
);
6934 if (!fp_access_check(s
)) {
6938 tcg_resl
= tcg_const_i64(0);
6939 tcg_resh
= tcg_const_i64(0);
6940 tcg_res
= tcg_temp_new_i64();
6942 for (i
= 0; i
< elements
; i
++) {
6944 case 1: /* UZP1/2 */
6946 int midpoint
= elements
/ 2;
6948 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6950 read_vec_element(s
, tcg_res
, rm
,
6951 2 * (i
- midpoint
) + part
, size
);
6955 case 2: /* TRN1/2 */
6957 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6959 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6962 case 3: /* ZIP1/2 */
6964 int base
= part
* elements
/ 2;
6966 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6968 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6973 g_assert_not_reached();
6978 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6979 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6981 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6982 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6986 tcg_temp_free_i64(tcg_res
);
6988 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6989 tcg_temp_free_i64(tcg_resl
);
6990 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6991 tcg_temp_free_i64(tcg_resh
);
6995 * do_reduction_op helper
6997 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6998 * important for correct NaN propagation that we do these
6999 * operations in exactly the order specified by the pseudocode.
7001 * This is a recursive function, TCG temps should be freed by the
7002 * calling function once it is done with the values.
7004 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7005 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7007 if (esize
== size
) {
7009 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7012 /* We should have one register left here */
7013 assert(ctpop8(vmap
) == 1);
7014 element
= ctz32(vmap
);
7015 assert(element
< 8);
7017 tcg_elem
= tcg_temp_new_i32();
7018 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7021 int bits
= size
/ 2;
7022 int shift
= ctpop8(vmap
) / 2;
7023 int vmap_lo
= (vmap
>> shift
) & vmap
;
7024 int vmap_hi
= (vmap
& ~vmap_lo
);
7025 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7027 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7028 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7029 tcg_res
= tcg_temp_new_i32();
7032 case 0x0c: /* fmaxnmv half-precision */
7033 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7035 case 0x0f: /* fmaxv half-precision */
7036 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7038 case 0x1c: /* fminnmv half-precision */
7039 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7041 case 0x1f: /* fminv half-precision */
7042 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7044 case 0x2c: /* fmaxnmv */
7045 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7047 case 0x2f: /* fmaxv */
7048 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7050 case 0x3c: /* fminnmv */
7051 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7053 case 0x3f: /* fminv */
7054 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7057 g_assert_not_reached();
7060 tcg_temp_free_i32(tcg_hi
);
7061 tcg_temp_free_i32(tcg_lo
);
7066 /* AdvSIMD across lanes
7067 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7068 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7069 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7070 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7072 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7074 int rd
= extract32(insn
, 0, 5);
7075 int rn
= extract32(insn
, 5, 5);
7076 int size
= extract32(insn
, 22, 2);
7077 int opcode
= extract32(insn
, 12, 5);
7078 bool is_q
= extract32(insn
, 30, 1);
7079 bool is_u
= extract32(insn
, 29, 1);
7081 bool is_min
= false;
7085 TCGv_i64 tcg_res
, tcg_elt
;
7088 case 0x1b: /* ADDV */
7090 unallocated_encoding(s
);
7094 case 0x3: /* SADDLV, UADDLV */
7095 case 0xa: /* SMAXV, UMAXV */
7096 case 0x1a: /* SMINV, UMINV */
7097 if (size
== 3 || (size
== 2 && !is_q
)) {
7098 unallocated_encoding(s
);
7102 case 0xc: /* FMAXNMV, FMINNMV */
7103 case 0xf: /* FMAXV, FMINV */
7104 /* Bit 1 of size field encodes min vs max and the actual size
7105 * depends on the encoding of the U bit. If not set (and FP16
7106 * enabled) then we do half-precision float instead of single
7109 is_min
= extract32(size
, 1, 1);
7111 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7113 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7114 unallocated_encoding(s
);
7121 unallocated_encoding(s
);
7125 if (!fp_access_check(s
)) {
7130 elements
= (is_q
? 128 : 64) / esize
;
7132 tcg_res
= tcg_temp_new_i64();
7133 tcg_elt
= tcg_temp_new_i64();
7135 /* These instructions operate across all lanes of a vector
7136 * to produce a single result. We can guarantee that a 64
7137 * bit intermediate is sufficient:
7138 * + for [US]ADDLV the maximum element size is 32 bits, and
7139 * the result type is 64 bits
7140 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7141 * same as the element size, which is 32 bits at most
7142 * For the integer operations we can choose to work at 64
7143 * or 32 bits and truncate at the end; for simplicity
7144 * we use 64 bits always. The floating point
7145 * ops do require 32 bit intermediates, though.
7148 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7150 for (i
= 1; i
< elements
; i
++) {
7151 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7154 case 0x03: /* SADDLV / UADDLV */
7155 case 0x1b: /* ADDV */
7156 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7158 case 0x0a: /* SMAXV / UMAXV */
7160 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7162 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7165 case 0x1a: /* SMINV / UMINV */
7167 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7169 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7173 g_assert_not_reached();
7178 /* Floating point vector reduction ops which work across 32
7179 * bit (single) or 16 bit (half-precision) intermediates.
7180 * Note that correct NaN propagation requires that we do these
7181 * operations in exactly the order specified by the pseudocode.
7183 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7184 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7185 int vmap
= (1 << elements
) - 1;
7186 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7187 (is_q
? 128 : 64), vmap
, fpst
);
7188 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7189 tcg_temp_free_i32(tcg_res32
);
7190 tcg_temp_free_ptr(fpst
);
7193 tcg_temp_free_i64(tcg_elt
);
7195 /* Now truncate the result to the width required for the final output */
7196 if (opcode
== 0x03) {
7197 /* SADDLV, UADDLV: result is 2*esize */
7203 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7206 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7209 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7214 g_assert_not_reached();
7217 write_fp_dreg(s
, rd
, tcg_res
);
7218 tcg_temp_free_i64(tcg_res
);
7221 /* DUP (Element, Vector)
7223 * 31 30 29 21 20 16 15 10 9 5 4 0
7224 * +---+---+-------------------+--------+-------------+------+------+
7225 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7226 * +---+---+-------------------+--------+-------------+------+------+
7228 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7230 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7233 int size
= ctz32(imm5
);
7234 int index
= imm5
>> (size
+ 1);
7236 if (size
> 3 || (size
== 3 && !is_q
)) {
7237 unallocated_encoding(s
);
7241 if (!fp_access_check(s
)) {
7245 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7246 vec_reg_offset(s
, rn
, index
, size
),
7247 is_q
? 16 : 8, vec_full_reg_size(s
));
7250 /* DUP (element, scalar)
7251 * 31 21 20 16 15 10 9 5 4 0
7252 * +-----------------------+--------+-------------+------+------+
7253 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7254 * +-----------------------+--------+-------------+------+------+
7256 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7259 int size
= ctz32(imm5
);
7264 unallocated_encoding(s
);
7268 if (!fp_access_check(s
)) {
7272 index
= imm5
>> (size
+ 1);
7274 /* This instruction just extracts the specified element and
7275 * zero-extends it into the bottom of the destination register.
7277 tmp
= tcg_temp_new_i64();
7278 read_vec_element(s
, tmp
, rn
, index
, size
);
7279 write_fp_dreg(s
, rd
, tmp
);
7280 tcg_temp_free_i64(tmp
);
7285 * 31 30 29 21 20 16 15 10 9 5 4 0
7286 * +---+---+-------------------+--------+-------------+------+------+
7287 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7288 * +---+---+-------------------+--------+-------------+------+------+
7290 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7292 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7295 int size
= ctz32(imm5
);
7296 uint32_t dofs
, oprsz
, maxsz
;
7298 if (size
> 3 || ((size
== 3) && !is_q
)) {
7299 unallocated_encoding(s
);
7303 if (!fp_access_check(s
)) {
7307 dofs
= vec_full_reg_offset(s
, rd
);
7308 oprsz
= is_q
? 16 : 8;
7309 maxsz
= vec_full_reg_size(s
);
7311 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7316 * 31 21 20 16 15 14 11 10 9 5 4 0
7317 * +-----------------------+--------+------------+---+------+------+
7318 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7319 * +-----------------------+--------+------------+---+------+------+
7321 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7322 * index: encoded in imm5<4:size+1>
7324 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7327 int size
= ctz32(imm5
);
7328 int src_index
, dst_index
;
7332 unallocated_encoding(s
);
7336 if (!fp_access_check(s
)) {
7340 dst_index
= extract32(imm5
, 1+size
, 5);
7341 src_index
= extract32(imm4
, size
, 4);
7343 tmp
= tcg_temp_new_i64();
7345 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7346 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7348 tcg_temp_free_i64(tmp
);
7354 * 31 21 20 16 15 10 9 5 4 0
7355 * +-----------------------+--------+-------------+------+------+
7356 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7357 * +-----------------------+--------+-------------+------+------+
7359 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7360 * index: encoded in imm5<4:size+1>
7362 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7364 int size
= ctz32(imm5
);
7368 unallocated_encoding(s
);
7372 if (!fp_access_check(s
)) {
7376 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7377 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7384 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7385 * +---+---+-------------------+--------+-------------+------+------+
7386 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7387 * +---+---+-------------------+--------+-------------+------+------+
7389 * U: unsigned when set
7390 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7392 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7393 int rn
, int rd
, int imm5
)
7395 int size
= ctz32(imm5
);
7399 /* Check for UnallocatedEncodings */
7401 if (size
> 2 || (size
== 2 && !is_q
)) {
7402 unallocated_encoding(s
);
7407 || (size
< 3 && is_q
)
7408 || (size
== 3 && !is_q
)) {
7409 unallocated_encoding(s
);
7414 if (!fp_access_check(s
)) {
7418 element
= extract32(imm5
, 1+size
, 4);
7420 tcg_rd
= cpu_reg(s
, rd
);
7421 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7422 if (is_signed
&& !is_q
) {
7423 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7428 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7429 * +---+---+----+-----------------+------+---+------+---+------+------+
7430 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7431 * +---+---+----+-----------------+------+---+------+---+------+------+
7433 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7435 int rd
= extract32(insn
, 0, 5);
7436 int rn
= extract32(insn
, 5, 5);
7437 int imm4
= extract32(insn
, 11, 4);
7438 int op
= extract32(insn
, 29, 1);
7439 int is_q
= extract32(insn
, 30, 1);
7440 int imm5
= extract32(insn
, 16, 5);
7445 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7447 unallocated_encoding(s
);
7452 /* DUP (element - vector) */
7453 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7457 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7462 handle_simd_insg(s
, rd
, rn
, imm5
);
7464 unallocated_encoding(s
);
7469 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7470 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7473 unallocated_encoding(s
);
7479 /* AdvSIMD modified immediate
7480 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7481 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7482 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7483 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7485 * There are a number of operations that can be carried out here:
7486 * MOVI - move (shifted) imm into register
7487 * MVNI - move inverted (shifted) imm into register
7488 * ORR - bitwise OR of (shifted) imm with register
7489 * BIC - bitwise clear of (shifted) imm with register
7490 * With ARMv8.2 we also have:
7491 * FMOV half-precision
7493 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7495 int rd
= extract32(insn
, 0, 5);
7496 int cmode
= extract32(insn
, 12, 4);
7497 int cmode_3_1
= extract32(cmode
, 1, 3);
7498 int cmode_0
= extract32(cmode
, 0, 1);
7499 int o2
= extract32(insn
, 11, 1);
7500 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7501 bool is_neg
= extract32(insn
, 29, 1);
7502 bool is_q
= extract32(insn
, 30, 1);
7505 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7506 /* Check for FMOV (vector, immediate) - half-precision */
7507 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7508 unallocated_encoding(s
);
7513 if (!fp_access_check(s
)) {
7517 /* See AdvSIMDExpandImm() in ARM ARM */
7518 switch (cmode_3_1
) {
7519 case 0: /* Replicate(Zeros(24):imm8, 2) */
7520 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7521 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7522 case 3: /* Replicate(imm8:Zeros(24), 2) */
7524 int shift
= cmode_3_1
* 8;
7525 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7528 case 4: /* Replicate(Zeros(8):imm8, 4) */
7529 case 5: /* Replicate(imm8:Zeros(8), 4) */
7531 int shift
= (cmode_3_1
& 0x1) * 8;
7532 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7537 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7538 imm
= (abcdefgh
<< 16) | 0xffff;
7540 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7541 imm
= (abcdefgh
<< 8) | 0xff;
7543 imm
= bitfield_replicate(imm
, 32);
7546 if (!cmode_0
&& !is_neg
) {
7547 imm
= bitfield_replicate(abcdefgh
, 8);
7548 } else if (!cmode_0
&& is_neg
) {
7551 for (i
= 0; i
< 8; i
++) {
7552 if ((abcdefgh
) & (1 << i
)) {
7553 imm
|= 0xffULL
<< (i
* 8);
7556 } else if (cmode_0
) {
7558 imm
= (abcdefgh
& 0x3f) << 48;
7559 if (abcdefgh
& 0x80) {
7560 imm
|= 0x8000000000000000ULL
;
7562 if (abcdefgh
& 0x40) {
7563 imm
|= 0x3fc0000000000000ULL
;
7565 imm
|= 0x4000000000000000ULL
;
7569 /* FMOV (vector, immediate) - half-precision */
7570 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7571 /* now duplicate across the lanes */
7572 imm
= bitfield_replicate(imm
, 16);
7574 imm
= (abcdefgh
& 0x3f) << 19;
7575 if (abcdefgh
& 0x80) {
7578 if (abcdefgh
& 0x40) {
7589 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7590 g_assert_not_reached();
7593 if (cmode_3_1
!= 7 && is_neg
) {
7597 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7598 /* MOVI or MVNI, with MVNI negation handled above. */
7599 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7600 vec_full_reg_size(s
), imm
);
7602 /* ORR or BIC, with BIC negation to AND handled above. */
7604 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7606 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7611 /* AdvSIMD scalar copy
7612 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7613 * +-----+----+-----------------+------+---+------+---+------+------+
7614 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7615 * +-----+----+-----------------+------+---+------+---+------+------+
7617 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7619 int rd
= extract32(insn
, 0, 5);
7620 int rn
= extract32(insn
, 5, 5);
7621 int imm4
= extract32(insn
, 11, 4);
7622 int imm5
= extract32(insn
, 16, 5);
7623 int op
= extract32(insn
, 29, 1);
7625 if (op
!= 0 || imm4
!= 0) {
7626 unallocated_encoding(s
);
7630 /* DUP (element, scalar) */
7631 handle_simd_dupes(s
, rd
, rn
, imm5
);
7634 /* AdvSIMD scalar pairwise
7635 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7636 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7637 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7638 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7640 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7642 int u
= extract32(insn
, 29, 1);
7643 int size
= extract32(insn
, 22, 2);
7644 int opcode
= extract32(insn
, 12, 5);
7645 int rn
= extract32(insn
, 5, 5);
7646 int rd
= extract32(insn
, 0, 5);
7649 /* For some ops (the FP ones), size[1] is part of the encoding.
7650 * For ADDP strictly it is not but size[1] is always 1 for valid
7653 opcode
|= (extract32(size
, 1, 1) << 5);
7656 case 0x3b: /* ADDP */
7657 if (u
|| size
!= 3) {
7658 unallocated_encoding(s
);
7661 if (!fp_access_check(s
)) {
7667 case 0xc: /* FMAXNMP */
7668 case 0xd: /* FADDP */
7669 case 0xf: /* FMAXP */
7670 case 0x2c: /* FMINNMP */
7671 case 0x2f: /* FMINP */
7672 /* FP op, size[0] is 32 or 64 bit*/
7674 if (!dc_isar_feature(aa64_fp16
, s
)) {
7675 unallocated_encoding(s
);
7681 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7684 if (!fp_access_check(s
)) {
7688 fpst
= get_fpstatus_ptr(size
== MO_16
);
7691 unallocated_encoding(s
);
7695 if (size
== MO_64
) {
7696 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7697 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7698 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7700 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7701 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7704 case 0x3b: /* ADDP */
7705 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7707 case 0xc: /* FMAXNMP */
7708 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7710 case 0xd: /* FADDP */
7711 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7713 case 0xf: /* FMAXP */
7714 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7716 case 0x2c: /* FMINNMP */
7717 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7719 case 0x2f: /* FMINP */
7720 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7723 g_assert_not_reached();
7726 write_fp_dreg(s
, rd
, tcg_res
);
7728 tcg_temp_free_i64(tcg_op1
);
7729 tcg_temp_free_i64(tcg_op2
);
7730 tcg_temp_free_i64(tcg_res
);
7732 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7733 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7734 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7736 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7737 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7739 if (size
== MO_16
) {
7741 case 0xc: /* FMAXNMP */
7742 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7744 case 0xd: /* FADDP */
7745 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7747 case 0xf: /* FMAXP */
7748 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7750 case 0x2c: /* FMINNMP */
7751 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7753 case 0x2f: /* FMINP */
7754 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7757 g_assert_not_reached();
7761 case 0xc: /* FMAXNMP */
7762 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7764 case 0xd: /* FADDP */
7765 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7767 case 0xf: /* FMAXP */
7768 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7770 case 0x2c: /* FMINNMP */
7771 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7773 case 0x2f: /* FMINP */
7774 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7777 g_assert_not_reached();
7781 write_fp_sreg(s
, rd
, tcg_res
);
7783 tcg_temp_free_i32(tcg_op1
);
7784 tcg_temp_free_i32(tcg_op2
);
7785 tcg_temp_free_i32(tcg_res
);
7789 tcg_temp_free_ptr(fpst
);
7794 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7796 * This code is handles the common shifting code and is used by both
7797 * the vector and scalar code.
7799 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7800 TCGv_i64 tcg_rnd
, bool accumulate
,
7801 bool is_u
, int size
, int shift
)
7803 bool extended_result
= false;
7804 bool round
= tcg_rnd
!= NULL
;
7806 TCGv_i64 tcg_src_hi
;
7808 if (round
&& size
== 3) {
7809 extended_result
= true;
7810 ext_lshift
= 64 - shift
;
7811 tcg_src_hi
= tcg_temp_new_i64();
7812 } else if (shift
== 64) {
7813 if (!accumulate
&& is_u
) {
7814 /* result is zero */
7815 tcg_gen_movi_i64(tcg_res
, 0);
7820 /* Deal with the rounding step */
7822 if (extended_result
) {
7823 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7825 /* take care of sign extending tcg_res */
7826 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7827 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7828 tcg_src
, tcg_src_hi
,
7831 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7835 tcg_temp_free_i64(tcg_zero
);
7837 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7841 /* Now do the shift right */
7842 if (round
&& extended_result
) {
7843 /* extended case, >64 bit precision required */
7844 if (ext_lshift
== 0) {
7845 /* special case, only high bits matter */
7846 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7848 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7849 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7850 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7855 /* essentially shifting in 64 zeros */
7856 tcg_gen_movi_i64(tcg_src
, 0);
7858 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7862 /* effectively extending the sign-bit */
7863 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7865 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7871 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7873 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7876 if (extended_result
) {
7877 tcg_temp_free_i64(tcg_src_hi
);
7881 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7882 static void handle_scalar_simd_shri(DisasContext
*s
,
7883 bool is_u
, int immh
, int immb
,
7884 int opcode
, int rn
, int rd
)
7887 int immhb
= immh
<< 3 | immb
;
7888 int shift
= 2 * (8 << size
) - immhb
;
7889 bool accumulate
= false;
7891 bool insert
= false;
7896 if (!extract32(immh
, 3, 1)) {
7897 unallocated_encoding(s
);
7901 if (!fp_access_check(s
)) {
7906 case 0x02: /* SSRA / USRA (accumulate) */
7909 case 0x04: /* SRSHR / URSHR (rounding) */
7912 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7913 accumulate
= round
= true;
7915 case 0x08: /* SRI */
7921 uint64_t round_const
= 1ULL << (shift
- 1);
7922 tcg_round
= tcg_const_i64(round_const
);
7927 tcg_rn
= read_fp_dreg(s
, rn
);
7928 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7931 /* shift count same as element size is valid but does nothing;
7932 * special case to avoid potential shift by 64.
7934 int esize
= 8 << size
;
7935 if (shift
!= esize
) {
7936 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7937 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7940 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7941 accumulate
, is_u
, size
, shift
);
7944 write_fp_dreg(s
, rd
, tcg_rd
);
7946 tcg_temp_free_i64(tcg_rn
);
7947 tcg_temp_free_i64(tcg_rd
);
7949 tcg_temp_free_i64(tcg_round
);
7953 /* SHL/SLI - Scalar shift left */
7954 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7955 int immh
, int immb
, int opcode
,
7958 int size
= 32 - clz32(immh
) - 1;
7959 int immhb
= immh
<< 3 | immb
;
7960 int shift
= immhb
- (8 << size
);
7961 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7962 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7964 if (!extract32(immh
, 3, 1)) {
7965 unallocated_encoding(s
);
7969 if (!fp_access_check(s
)) {
7973 tcg_rn
= read_fp_dreg(s
, rn
);
7974 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7977 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7979 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7982 write_fp_dreg(s
, rd
, tcg_rd
);
7984 tcg_temp_free_i64(tcg_rn
);
7985 tcg_temp_free_i64(tcg_rd
);
7988 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7989 * (signed/unsigned) narrowing */
7990 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7991 bool is_u_shift
, bool is_u_narrow
,
7992 int immh
, int immb
, int opcode
,
7995 int immhb
= immh
<< 3 | immb
;
7996 int size
= 32 - clz32(immh
) - 1;
7997 int esize
= 8 << size
;
7998 int shift
= (2 * esize
) - immhb
;
7999 int elements
= is_scalar
? 1 : (64 / esize
);
8000 bool round
= extract32(opcode
, 0, 1);
8001 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8002 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8003 TCGv_i32 tcg_rd_narrowed
;
8006 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8007 { gen_helper_neon_narrow_sat_s8
,
8008 gen_helper_neon_unarrow_sat8
},
8009 { gen_helper_neon_narrow_sat_s16
,
8010 gen_helper_neon_unarrow_sat16
},
8011 { gen_helper_neon_narrow_sat_s32
,
8012 gen_helper_neon_unarrow_sat32
},
8015 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8016 gen_helper_neon_narrow_sat_u8
,
8017 gen_helper_neon_narrow_sat_u16
,
8018 gen_helper_neon_narrow_sat_u32
,
8021 NeonGenNarrowEnvFn
*narrowfn
;
8027 if (extract32(immh
, 3, 1)) {
8028 unallocated_encoding(s
);
8032 if (!fp_access_check(s
)) {
8037 narrowfn
= unsigned_narrow_fns
[size
];
8039 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8042 tcg_rn
= tcg_temp_new_i64();
8043 tcg_rd
= tcg_temp_new_i64();
8044 tcg_rd_narrowed
= tcg_temp_new_i32();
8045 tcg_final
= tcg_const_i64(0);
8048 uint64_t round_const
= 1ULL << (shift
- 1);
8049 tcg_round
= tcg_const_i64(round_const
);
8054 for (i
= 0; i
< elements
; i
++) {
8055 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8056 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8057 false, is_u_shift
, size
+1, shift
);
8058 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8059 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8060 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8064 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8066 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8070 tcg_temp_free_i64(tcg_round
);
8072 tcg_temp_free_i64(tcg_rn
);
8073 tcg_temp_free_i64(tcg_rd
);
8074 tcg_temp_free_i32(tcg_rd_narrowed
);
8075 tcg_temp_free_i64(tcg_final
);
8077 clear_vec_high(s
, is_q
, rd
);
8080 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8081 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8082 bool src_unsigned
, bool dst_unsigned
,
8083 int immh
, int immb
, int rn
, int rd
)
8085 int immhb
= immh
<< 3 | immb
;
8086 int size
= 32 - clz32(immh
) - 1;
8087 int shift
= immhb
- (8 << size
);
8091 assert(!(scalar
&& is_q
));
8094 if (!is_q
&& extract32(immh
, 3, 1)) {
8095 unallocated_encoding(s
);
8099 /* Since we use the variable-shift helpers we must
8100 * replicate the shift count into each element of
8101 * the tcg_shift value.
8105 shift
|= shift
<< 8;
8108 shift
|= shift
<< 16;
8114 g_assert_not_reached();
8118 if (!fp_access_check(s
)) {
8123 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8124 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8125 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8126 { NULL
, gen_helper_neon_qshl_u64
},
8128 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8129 int maxpass
= is_q
? 2 : 1;
8131 for (pass
= 0; pass
< maxpass
; pass
++) {
8132 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8134 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8135 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8136 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8138 tcg_temp_free_i64(tcg_op
);
8140 tcg_temp_free_i64(tcg_shift
);
8141 clear_vec_high(s
, is_q
, rd
);
8143 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8144 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8146 { gen_helper_neon_qshl_s8
,
8147 gen_helper_neon_qshl_s16
,
8148 gen_helper_neon_qshl_s32
},
8149 { gen_helper_neon_qshlu_s8
,
8150 gen_helper_neon_qshlu_s16
,
8151 gen_helper_neon_qshlu_s32
}
8153 { NULL
, NULL
, NULL
},
8154 { gen_helper_neon_qshl_u8
,
8155 gen_helper_neon_qshl_u16
,
8156 gen_helper_neon_qshl_u32
}
8159 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8160 MemOp memop
= scalar
? size
: MO_32
;
8161 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8163 for (pass
= 0; pass
< maxpass
; pass
++) {
8164 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8166 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8167 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8171 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8174 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8179 g_assert_not_reached();
8181 write_fp_sreg(s
, rd
, tcg_op
);
8183 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8186 tcg_temp_free_i32(tcg_op
);
8188 tcg_temp_free_i32(tcg_shift
);
8191 clear_vec_high(s
, is_q
, rd
);
8196 /* Common vector code for handling integer to FP conversion */
8197 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8198 int elements
, int is_signed
,
8199 int fracbits
, int size
)
8201 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8202 TCGv_i32 tcg_shift
= NULL
;
8204 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8207 if (fracbits
|| size
== MO_64
) {
8208 tcg_shift
= tcg_const_i32(fracbits
);
8211 if (size
== MO_64
) {
8212 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8213 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8215 for (pass
= 0; pass
< elements
; pass
++) {
8216 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8219 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8220 tcg_shift
, tcg_fpst
);
8222 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8223 tcg_shift
, tcg_fpst
);
8225 if (elements
== 1) {
8226 write_fp_dreg(s
, rd
, tcg_double
);
8228 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8232 tcg_temp_free_i64(tcg_int64
);
8233 tcg_temp_free_i64(tcg_double
);
8236 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8237 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8239 for (pass
= 0; pass
< elements
; pass
++) {
8240 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8246 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8247 tcg_shift
, tcg_fpst
);
8249 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8250 tcg_shift
, tcg_fpst
);
8254 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8256 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8263 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8264 tcg_shift
, tcg_fpst
);
8266 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8267 tcg_shift
, tcg_fpst
);
8271 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8273 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8278 g_assert_not_reached();
8281 if (elements
== 1) {
8282 write_fp_sreg(s
, rd
, tcg_float
);
8284 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8288 tcg_temp_free_i32(tcg_int32
);
8289 tcg_temp_free_i32(tcg_float
);
8292 tcg_temp_free_ptr(tcg_fpst
);
8294 tcg_temp_free_i32(tcg_shift
);
8297 clear_vec_high(s
, elements
<< size
== 16, rd
);
8300 /* UCVTF/SCVTF - Integer to FP conversion */
8301 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8302 bool is_q
, bool is_u
,
8303 int immh
, int immb
, int opcode
,
8306 int size
, elements
, fracbits
;
8307 int immhb
= immh
<< 3 | immb
;
8311 if (!is_scalar
&& !is_q
) {
8312 unallocated_encoding(s
);
8315 } else if (immh
& 4) {
8317 } else if (immh
& 2) {
8319 if (!dc_isar_feature(aa64_fp16
, s
)) {
8320 unallocated_encoding(s
);
8324 /* immh == 0 would be a failure of the decode logic */
8325 g_assert(immh
== 1);
8326 unallocated_encoding(s
);
8333 elements
= (8 << is_q
) >> size
;
8335 fracbits
= (16 << size
) - immhb
;
8337 if (!fp_access_check(s
)) {
8341 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8344 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8345 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8346 bool is_q
, bool is_u
,
8347 int immh
, int immb
, int rn
, int rd
)
8349 int immhb
= immh
<< 3 | immb
;
8350 int pass
, size
, fracbits
;
8351 TCGv_ptr tcg_fpstatus
;
8352 TCGv_i32 tcg_rmode
, tcg_shift
;
8356 if (!is_scalar
&& !is_q
) {
8357 unallocated_encoding(s
);
8360 } else if (immh
& 0x4) {
8362 } else if (immh
& 0x2) {
8364 if (!dc_isar_feature(aa64_fp16
, s
)) {
8365 unallocated_encoding(s
);
8369 /* Should have split out AdvSIMD modified immediate earlier. */
8371 unallocated_encoding(s
);
8375 if (!fp_access_check(s
)) {
8379 assert(!(is_scalar
&& is_q
));
8381 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8382 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8383 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8384 fracbits
= (16 << size
) - immhb
;
8385 tcg_shift
= tcg_const_i32(fracbits
);
8387 if (size
== MO_64
) {
8388 int maxpass
= is_scalar
? 1 : 2;
8390 for (pass
= 0; pass
< maxpass
; pass
++) {
8391 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8393 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8395 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8397 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8399 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8400 tcg_temp_free_i64(tcg_op
);
8402 clear_vec_high(s
, is_q
, rd
);
8404 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8405 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8410 fn
= gen_helper_vfp_touhh
;
8412 fn
= gen_helper_vfp_toshh
;
8417 fn
= gen_helper_vfp_touls
;
8419 fn
= gen_helper_vfp_tosls
;
8423 g_assert_not_reached();
8426 for (pass
= 0; pass
< maxpass
; pass
++) {
8427 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8429 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8430 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8432 write_fp_sreg(s
, rd
, tcg_op
);
8434 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8436 tcg_temp_free_i32(tcg_op
);
8439 clear_vec_high(s
, is_q
, rd
);
8443 tcg_temp_free_ptr(tcg_fpstatus
);
8444 tcg_temp_free_i32(tcg_shift
);
8445 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8446 tcg_temp_free_i32(tcg_rmode
);
8449 /* AdvSIMD scalar shift by immediate
8450 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8451 * +-----+---+-------------+------+------+--------+---+------+------+
8452 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8453 * +-----+---+-------------+------+------+--------+---+------+------+
8455 * This is the scalar version so it works on a fixed sized registers
8457 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8459 int rd
= extract32(insn
, 0, 5);
8460 int rn
= extract32(insn
, 5, 5);
8461 int opcode
= extract32(insn
, 11, 5);
8462 int immb
= extract32(insn
, 16, 3);
8463 int immh
= extract32(insn
, 19, 4);
8464 bool is_u
= extract32(insn
, 29, 1);
8467 unallocated_encoding(s
);
8472 case 0x08: /* SRI */
8474 unallocated_encoding(s
);
8478 case 0x00: /* SSHR / USHR */
8479 case 0x02: /* SSRA / USRA */
8480 case 0x04: /* SRSHR / URSHR */
8481 case 0x06: /* SRSRA / URSRA */
8482 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8484 case 0x0a: /* SHL / SLI */
8485 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8487 case 0x1c: /* SCVTF, UCVTF */
8488 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8491 case 0x10: /* SQSHRUN, SQSHRUN2 */
8492 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8494 unallocated_encoding(s
);
8497 handle_vec_simd_sqshrn(s
, true, false, false, true,
8498 immh
, immb
, opcode
, rn
, rd
);
8500 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8501 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8502 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8503 immh
, immb
, opcode
, rn
, rd
);
8505 case 0xc: /* SQSHLU */
8507 unallocated_encoding(s
);
8510 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8512 case 0xe: /* SQSHL, UQSHL */
8513 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8515 case 0x1f: /* FCVTZS, FCVTZU */
8516 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8519 unallocated_encoding(s
);
8524 /* AdvSIMD scalar three different
8525 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8526 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8527 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8528 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8530 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8532 bool is_u
= extract32(insn
, 29, 1);
8533 int size
= extract32(insn
, 22, 2);
8534 int opcode
= extract32(insn
, 12, 4);
8535 int rm
= extract32(insn
, 16, 5);
8536 int rn
= extract32(insn
, 5, 5);
8537 int rd
= extract32(insn
, 0, 5);
8540 unallocated_encoding(s
);
8545 case 0x9: /* SQDMLAL, SQDMLAL2 */
8546 case 0xb: /* SQDMLSL, SQDMLSL2 */
8547 case 0xd: /* SQDMULL, SQDMULL2 */
8548 if (size
== 0 || size
== 3) {
8549 unallocated_encoding(s
);
8554 unallocated_encoding(s
);
8558 if (!fp_access_check(s
)) {
8563 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8564 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8565 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8567 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8568 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8570 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8571 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8574 case 0xd: /* SQDMULL, SQDMULL2 */
8576 case 0xb: /* SQDMLSL, SQDMLSL2 */
8577 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8579 case 0x9: /* SQDMLAL, SQDMLAL2 */
8580 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8581 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8585 g_assert_not_reached();
8588 write_fp_dreg(s
, rd
, tcg_res
);
8590 tcg_temp_free_i64(tcg_op1
);
8591 tcg_temp_free_i64(tcg_op2
);
8592 tcg_temp_free_i64(tcg_res
);
8594 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8595 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8596 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8598 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8599 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8602 case 0xd: /* SQDMULL, SQDMULL2 */
8604 case 0xb: /* SQDMLSL, SQDMLSL2 */
8605 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8607 case 0x9: /* SQDMLAL, SQDMLAL2 */
8609 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8610 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8611 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8613 tcg_temp_free_i64(tcg_op3
);
8617 g_assert_not_reached();
8620 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8621 write_fp_dreg(s
, rd
, tcg_res
);
8623 tcg_temp_free_i32(tcg_op1
);
8624 tcg_temp_free_i32(tcg_op2
);
8625 tcg_temp_free_i64(tcg_res
);
8629 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8630 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8632 /* Handle 64x64->64 opcodes which are shared between the scalar
8633 * and vector 3-same groups. We cover every opcode where size == 3
8634 * is valid in either the three-reg-same (integer, not pairwise)
8635 * or scalar-three-reg-same groups.
8640 case 0x1: /* SQADD */
8642 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8644 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8647 case 0x5: /* SQSUB */
8649 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8651 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8654 case 0x6: /* CMGT, CMHI */
8655 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8656 * We implement this using setcond (test) and then negating.
8658 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8660 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8661 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8663 case 0x7: /* CMGE, CMHS */
8664 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8666 case 0x11: /* CMTST, CMEQ */
8671 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8673 case 0x8: /* SSHL, USHL */
8675 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8677 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8680 case 0x9: /* SQSHL, UQSHL */
8682 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8684 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8687 case 0xa: /* SRSHL, URSHL */
8689 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8691 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8694 case 0xb: /* SQRSHL, UQRSHL */
8696 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8698 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8701 case 0x10: /* ADD, SUB */
8703 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8705 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8709 g_assert_not_reached();
8713 /* Handle the 3-same-operands float operations; shared by the scalar
8714 * and vector encodings. The caller must filter out any encodings
8715 * not allocated for the encoding it is dealing with.
8717 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8718 int fpopcode
, int rd
, int rn
, int rm
)
8721 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8723 for (pass
= 0; pass
< elements
; pass
++) {
8726 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8727 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8728 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8730 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8731 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8734 case 0x39: /* FMLS */
8735 /* As usual for ARM, separate negation for fused multiply-add */
8736 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8738 case 0x19: /* FMLA */
8739 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8740 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8743 case 0x18: /* FMAXNM */
8744 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8746 case 0x1a: /* FADD */
8747 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8749 case 0x1b: /* FMULX */
8750 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8752 case 0x1c: /* FCMEQ */
8753 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8755 case 0x1e: /* FMAX */
8756 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8758 case 0x1f: /* FRECPS */
8759 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8761 case 0x38: /* FMINNM */
8762 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8764 case 0x3a: /* FSUB */
8765 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8767 case 0x3e: /* FMIN */
8768 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8770 case 0x3f: /* FRSQRTS */
8771 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8773 case 0x5b: /* FMUL */
8774 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8776 case 0x5c: /* FCMGE */
8777 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8779 case 0x5d: /* FACGE */
8780 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8782 case 0x5f: /* FDIV */
8783 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8785 case 0x7a: /* FABD */
8786 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8787 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8789 case 0x7c: /* FCMGT */
8790 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8792 case 0x7d: /* FACGT */
8793 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8796 g_assert_not_reached();
8799 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8801 tcg_temp_free_i64(tcg_res
);
8802 tcg_temp_free_i64(tcg_op1
);
8803 tcg_temp_free_i64(tcg_op2
);
8806 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8807 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8808 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8810 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8811 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8814 case 0x39: /* FMLS */
8815 /* As usual for ARM, separate negation for fused multiply-add */
8816 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8818 case 0x19: /* FMLA */
8819 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8820 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8823 case 0x1a: /* FADD */
8824 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8826 case 0x1b: /* FMULX */
8827 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8829 case 0x1c: /* FCMEQ */
8830 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8832 case 0x1e: /* FMAX */
8833 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8835 case 0x1f: /* FRECPS */
8836 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8838 case 0x18: /* FMAXNM */
8839 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8841 case 0x38: /* FMINNM */
8842 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8844 case 0x3a: /* FSUB */
8845 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8847 case 0x3e: /* FMIN */
8848 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8850 case 0x3f: /* FRSQRTS */
8851 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8853 case 0x5b: /* FMUL */
8854 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8856 case 0x5c: /* FCMGE */
8857 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8859 case 0x5d: /* FACGE */
8860 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8862 case 0x5f: /* FDIV */
8863 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8865 case 0x7a: /* FABD */
8866 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8867 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8869 case 0x7c: /* FCMGT */
8870 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8872 case 0x7d: /* FACGT */
8873 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8876 g_assert_not_reached();
8879 if (elements
== 1) {
8880 /* scalar single so clear high part */
8881 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8883 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8884 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8885 tcg_temp_free_i64(tcg_tmp
);
8887 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8890 tcg_temp_free_i32(tcg_res
);
8891 tcg_temp_free_i32(tcg_op1
);
8892 tcg_temp_free_i32(tcg_op2
);
8896 tcg_temp_free_ptr(fpst
);
8898 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8901 /* AdvSIMD scalar three same
8902 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8903 * +-----+---+-----------+------+---+------+--------+---+------+------+
8904 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8905 * +-----+---+-----------+------+---+------+--------+---+------+------+
8907 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8909 int rd
= extract32(insn
, 0, 5);
8910 int rn
= extract32(insn
, 5, 5);
8911 int opcode
= extract32(insn
, 11, 5);
8912 int rm
= extract32(insn
, 16, 5);
8913 int size
= extract32(insn
, 22, 2);
8914 bool u
= extract32(insn
, 29, 1);
8917 if (opcode
>= 0x18) {
8918 /* Floating point: U, size[1] and opcode indicate operation */
8919 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8921 case 0x1b: /* FMULX */
8922 case 0x1f: /* FRECPS */
8923 case 0x3f: /* FRSQRTS */
8924 case 0x5d: /* FACGE */
8925 case 0x7d: /* FACGT */
8926 case 0x1c: /* FCMEQ */
8927 case 0x5c: /* FCMGE */
8928 case 0x7c: /* FCMGT */
8929 case 0x7a: /* FABD */
8932 unallocated_encoding(s
);
8936 if (!fp_access_check(s
)) {
8940 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8945 case 0x1: /* SQADD, UQADD */
8946 case 0x5: /* SQSUB, UQSUB */
8947 case 0x9: /* SQSHL, UQSHL */
8948 case 0xb: /* SQRSHL, UQRSHL */
8950 case 0x8: /* SSHL, USHL */
8951 case 0xa: /* SRSHL, URSHL */
8952 case 0x6: /* CMGT, CMHI */
8953 case 0x7: /* CMGE, CMHS */
8954 case 0x11: /* CMTST, CMEQ */
8955 case 0x10: /* ADD, SUB (vector) */
8957 unallocated_encoding(s
);
8961 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8962 if (size
!= 1 && size
!= 2) {
8963 unallocated_encoding(s
);
8968 unallocated_encoding(s
);
8972 if (!fp_access_check(s
)) {
8976 tcg_rd
= tcg_temp_new_i64();
8979 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8980 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8982 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8983 tcg_temp_free_i64(tcg_rn
);
8984 tcg_temp_free_i64(tcg_rm
);
8986 /* Do a single operation on the lowest element in the vector.
8987 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8988 * no side effects for all these operations.
8989 * OPTME: special-purpose helpers would avoid doing some
8990 * unnecessary work in the helper for the 8 and 16 bit cases.
8992 NeonGenTwoOpEnvFn
*genenvfn
;
8993 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8994 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8995 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8997 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8998 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9001 case 0x1: /* SQADD, UQADD */
9003 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9004 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9005 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9006 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9008 genenvfn
= fns
[size
][u
];
9011 case 0x5: /* SQSUB, UQSUB */
9013 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9014 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9015 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9016 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9018 genenvfn
= fns
[size
][u
];
9021 case 0x9: /* SQSHL, UQSHL */
9023 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9024 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9025 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9026 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9028 genenvfn
= fns
[size
][u
];
9031 case 0xb: /* SQRSHL, UQRSHL */
9033 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9034 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9035 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9036 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9038 genenvfn
= fns
[size
][u
];
9041 case 0x16: /* SQDMULH, SQRDMULH */
9043 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9044 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9045 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9047 assert(size
== 1 || size
== 2);
9048 genenvfn
= fns
[size
- 1][u
];
9052 g_assert_not_reached();
9055 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9056 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9057 tcg_temp_free_i32(tcg_rd32
);
9058 tcg_temp_free_i32(tcg_rn
);
9059 tcg_temp_free_i32(tcg_rm
);
9062 write_fp_dreg(s
, rd
, tcg_rd
);
9064 tcg_temp_free_i64(tcg_rd
);
9067 /* AdvSIMD scalar three same FP16
9068 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9069 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9070 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9071 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9072 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9073 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9075 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9078 int rd
= extract32(insn
, 0, 5);
9079 int rn
= extract32(insn
, 5, 5);
9080 int opcode
= extract32(insn
, 11, 3);
9081 int rm
= extract32(insn
, 16, 5);
9082 bool u
= extract32(insn
, 29, 1);
9083 bool a
= extract32(insn
, 23, 1);
9084 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9091 case 0x03: /* FMULX */
9092 case 0x04: /* FCMEQ (reg) */
9093 case 0x07: /* FRECPS */
9094 case 0x0f: /* FRSQRTS */
9095 case 0x14: /* FCMGE (reg) */
9096 case 0x15: /* FACGE */
9097 case 0x1a: /* FABD */
9098 case 0x1c: /* FCMGT (reg) */
9099 case 0x1d: /* FACGT */
9102 unallocated_encoding(s
);
9106 if (!dc_isar_feature(aa64_fp16
, s
)) {
9107 unallocated_encoding(s
);
9110 if (!fp_access_check(s
)) {
9114 fpst
= get_fpstatus_ptr(true);
9116 tcg_op1
= read_fp_hreg(s
, rn
);
9117 tcg_op2
= read_fp_hreg(s
, rm
);
9118 tcg_res
= tcg_temp_new_i32();
9121 case 0x03: /* FMULX */
9122 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9124 case 0x04: /* FCMEQ (reg) */
9125 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9127 case 0x07: /* FRECPS */
9128 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9130 case 0x0f: /* FRSQRTS */
9131 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9133 case 0x14: /* FCMGE (reg) */
9134 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9136 case 0x15: /* FACGE */
9137 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9139 case 0x1a: /* FABD */
9140 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9141 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9143 case 0x1c: /* FCMGT (reg) */
9144 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9146 case 0x1d: /* FACGT */
9147 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9150 g_assert_not_reached();
9153 write_fp_sreg(s
, rd
, tcg_res
);
9156 tcg_temp_free_i32(tcg_res
);
9157 tcg_temp_free_i32(tcg_op1
);
9158 tcg_temp_free_i32(tcg_op2
);
9159 tcg_temp_free_ptr(fpst
);
9162 /* AdvSIMD scalar three same extra
9163 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9164 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9165 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9166 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9168 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9171 int rd
= extract32(insn
, 0, 5);
9172 int rn
= extract32(insn
, 5, 5);
9173 int opcode
= extract32(insn
, 11, 4);
9174 int rm
= extract32(insn
, 16, 5);
9175 int size
= extract32(insn
, 22, 2);
9176 bool u
= extract32(insn
, 29, 1);
9177 TCGv_i32 ele1
, ele2
, ele3
;
9181 switch (u
* 16 + opcode
) {
9182 case 0x10: /* SQRDMLAH (vector) */
9183 case 0x11: /* SQRDMLSH (vector) */
9184 if (size
!= 1 && size
!= 2) {
9185 unallocated_encoding(s
);
9188 feature
= dc_isar_feature(aa64_rdm
, s
);
9191 unallocated_encoding(s
);
9195 unallocated_encoding(s
);
9198 if (!fp_access_check(s
)) {
9202 /* Do a single operation on the lowest element in the vector.
9203 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9204 * with no side effects for all these operations.
9205 * OPTME: special-purpose helpers would avoid doing some
9206 * unnecessary work in the helper for the 16 bit cases.
9208 ele1
= tcg_temp_new_i32();
9209 ele2
= tcg_temp_new_i32();
9210 ele3
= tcg_temp_new_i32();
9212 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9213 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9214 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9217 case 0x0: /* SQRDMLAH */
9219 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9221 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9224 case 0x1: /* SQRDMLSH */
9226 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9228 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9232 g_assert_not_reached();
9234 tcg_temp_free_i32(ele1
);
9235 tcg_temp_free_i32(ele2
);
9237 res
= tcg_temp_new_i64();
9238 tcg_gen_extu_i32_i64(res
, ele3
);
9239 tcg_temp_free_i32(ele3
);
9241 write_fp_dreg(s
, rd
, res
);
9242 tcg_temp_free_i64(res
);
9245 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9246 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9247 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9249 /* Handle 64->64 opcodes which are shared between the scalar and
9250 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9251 * is valid in either group and also the double-precision fp ops.
9252 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9258 case 0x4: /* CLS, CLZ */
9260 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9262 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9266 /* This opcode is shared with CNT and RBIT but we have earlier
9267 * enforced that size == 3 if and only if this is the NOT insn.
9269 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9271 case 0x7: /* SQABS, SQNEG */
9273 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9275 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9278 case 0xa: /* CMLT */
9279 /* 64 bit integer comparison against zero, result is
9280 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9285 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9286 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9288 case 0x8: /* CMGT, CMGE */
9289 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9291 case 0x9: /* CMEQ, CMLE */
9292 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9294 case 0xb: /* ABS, NEG */
9296 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9298 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9301 case 0x2f: /* FABS */
9302 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9304 case 0x6f: /* FNEG */
9305 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9307 case 0x7f: /* FSQRT */
9308 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9310 case 0x1a: /* FCVTNS */
9311 case 0x1b: /* FCVTMS */
9312 case 0x1c: /* FCVTAS */
9313 case 0x3a: /* FCVTPS */
9314 case 0x3b: /* FCVTZS */
9316 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9317 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9318 tcg_temp_free_i32(tcg_shift
);
9321 case 0x5a: /* FCVTNU */
9322 case 0x5b: /* FCVTMU */
9323 case 0x5c: /* FCVTAU */
9324 case 0x7a: /* FCVTPU */
9325 case 0x7b: /* FCVTZU */
9327 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9328 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9329 tcg_temp_free_i32(tcg_shift
);
9332 case 0x18: /* FRINTN */
9333 case 0x19: /* FRINTM */
9334 case 0x38: /* FRINTP */
9335 case 0x39: /* FRINTZ */
9336 case 0x58: /* FRINTA */
9337 case 0x79: /* FRINTI */
9338 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9340 case 0x59: /* FRINTX */
9341 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9343 case 0x1e: /* FRINT32Z */
9344 case 0x5e: /* FRINT32X */
9345 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9347 case 0x1f: /* FRINT64Z */
9348 case 0x5f: /* FRINT64X */
9349 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9352 g_assert_not_reached();
9356 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9357 bool is_scalar
, bool is_u
, bool is_q
,
9358 int size
, int rn
, int rd
)
9360 bool is_double
= (size
== MO_64
);
9363 if (!fp_access_check(s
)) {
9367 fpst
= get_fpstatus_ptr(size
== MO_16
);
9370 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9371 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9372 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9373 NeonGenTwoDoubleOPFn
*genfn
;
9378 case 0x2e: /* FCMLT (zero) */
9381 case 0x2c: /* FCMGT (zero) */
9382 genfn
= gen_helper_neon_cgt_f64
;
9384 case 0x2d: /* FCMEQ (zero) */
9385 genfn
= gen_helper_neon_ceq_f64
;
9387 case 0x6d: /* FCMLE (zero) */
9390 case 0x6c: /* FCMGE (zero) */
9391 genfn
= gen_helper_neon_cge_f64
;
9394 g_assert_not_reached();
9397 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9398 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9400 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9402 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9404 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9406 tcg_temp_free_i64(tcg_res
);
9407 tcg_temp_free_i64(tcg_zero
);
9408 tcg_temp_free_i64(tcg_op
);
9410 clear_vec_high(s
, !is_scalar
, rd
);
9412 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9413 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9414 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9415 NeonGenTwoSingleOPFn
*genfn
;
9417 int pass
, maxpasses
;
9419 if (size
== MO_16
) {
9421 case 0x2e: /* FCMLT (zero) */
9424 case 0x2c: /* FCMGT (zero) */
9425 genfn
= gen_helper_advsimd_cgt_f16
;
9427 case 0x2d: /* FCMEQ (zero) */
9428 genfn
= gen_helper_advsimd_ceq_f16
;
9430 case 0x6d: /* FCMLE (zero) */
9433 case 0x6c: /* FCMGE (zero) */
9434 genfn
= gen_helper_advsimd_cge_f16
;
9437 g_assert_not_reached();
9441 case 0x2e: /* FCMLT (zero) */
9444 case 0x2c: /* FCMGT (zero) */
9445 genfn
= gen_helper_neon_cgt_f32
;
9447 case 0x2d: /* FCMEQ (zero) */
9448 genfn
= gen_helper_neon_ceq_f32
;
9450 case 0x6d: /* FCMLE (zero) */
9453 case 0x6c: /* FCMGE (zero) */
9454 genfn
= gen_helper_neon_cge_f32
;
9457 g_assert_not_reached();
9464 int vector_size
= 8 << is_q
;
9465 maxpasses
= vector_size
>> size
;
9468 for (pass
= 0; pass
< maxpasses
; pass
++) {
9469 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9471 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9473 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9476 write_fp_sreg(s
, rd
, tcg_res
);
9478 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9481 tcg_temp_free_i32(tcg_res
);
9482 tcg_temp_free_i32(tcg_zero
);
9483 tcg_temp_free_i32(tcg_op
);
9485 clear_vec_high(s
, is_q
, rd
);
9489 tcg_temp_free_ptr(fpst
);
9492 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9493 bool is_scalar
, bool is_u
, bool is_q
,
9494 int size
, int rn
, int rd
)
9496 bool is_double
= (size
== 3);
9497 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9500 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9501 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9504 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9505 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9507 case 0x3d: /* FRECPE */
9508 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9510 case 0x3f: /* FRECPX */
9511 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9513 case 0x7d: /* FRSQRTE */
9514 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9517 g_assert_not_reached();
9519 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9521 tcg_temp_free_i64(tcg_res
);
9522 tcg_temp_free_i64(tcg_op
);
9523 clear_vec_high(s
, !is_scalar
, rd
);
9525 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9526 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9527 int pass
, maxpasses
;
9532 maxpasses
= is_q
? 4 : 2;
9535 for (pass
= 0; pass
< maxpasses
; pass
++) {
9536 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9539 case 0x3c: /* URECPE */
9540 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9542 case 0x3d: /* FRECPE */
9543 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9545 case 0x3f: /* FRECPX */
9546 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9548 case 0x7d: /* FRSQRTE */
9549 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9552 g_assert_not_reached();
9556 write_fp_sreg(s
, rd
, tcg_res
);
9558 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9561 tcg_temp_free_i32(tcg_res
);
9562 tcg_temp_free_i32(tcg_op
);
9564 clear_vec_high(s
, is_q
, rd
);
9567 tcg_temp_free_ptr(fpst
);
9570 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9571 int opcode
, bool u
, bool is_q
,
9572 int size
, int rn
, int rd
)
9574 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9575 * in the source becomes a size element in the destination).
9578 TCGv_i32 tcg_res
[2];
9579 int destelt
= is_q
? 2 : 0;
9580 int passes
= scalar
? 1 : 2;
9583 tcg_res
[1] = tcg_const_i32(0);
9586 for (pass
= 0; pass
< passes
; pass
++) {
9587 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9588 NeonGenNarrowFn
*genfn
= NULL
;
9589 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9592 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9594 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9596 tcg_res
[pass
] = tcg_temp_new_i32();
9599 case 0x12: /* XTN, SQXTUN */
9601 static NeonGenNarrowFn
* const xtnfns
[3] = {
9602 gen_helper_neon_narrow_u8
,
9603 gen_helper_neon_narrow_u16
,
9604 tcg_gen_extrl_i64_i32
,
9606 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9607 gen_helper_neon_unarrow_sat8
,
9608 gen_helper_neon_unarrow_sat16
,
9609 gen_helper_neon_unarrow_sat32
,
9612 genenvfn
= sqxtunfns
[size
];
9614 genfn
= xtnfns
[size
];
9618 case 0x14: /* SQXTN, UQXTN */
9620 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9621 { gen_helper_neon_narrow_sat_s8
,
9622 gen_helper_neon_narrow_sat_u8
},
9623 { gen_helper_neon_narrow_sat_s16
,
9624 gen_helper_neon_narrow_sat_u16
},
9625 { gen_helper_neon_narrow_sat_s32
,
9626 gen_helper_neon_narrow_sat_u32
},
9628 genenvfn
= fns
[size
][u
];
9631 case 0x16: /* FCVTN, FCVTN2 */
9632 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9634 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9636 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9637 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9638 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9639 TCGv_i32 ahp
= get_ahp_flag();
9641 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9642 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9643 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9644 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9645 tcg_temp_free_i32(tcg_lo
);
9646 tcg_temp_free_i32(tcg_hi
);
9647 tcg_temp_free_ptr(fpst
);
9648 tcg_temp_free_i32(ahp
);
9651 case 0x56: /* FCVTXN, FCVTXN2 */
9652 /* 64 bit to 32 bit float conversion
9653 * with von Neumann rounding (round to odd)
9656 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9659 g_assert_not_reached();
9663 genfn(tcg_res
[pass
], tcg_op
);
9664 } else if (genenvfn
) {
9665 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9668 tcg_temp_free_i64(tcg_op
);
9671 for (pass
= 0; pass
< 2; pass
++) {
9672 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9673 tcg_temp_free_i32(tcg_res
[pass
]);
9675 clear_vec_high(s
, is_q
, rd
);
9678 /* Remaining saturating accumulating ops */
9679 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9680 bool is_q
, int size
, int rn
, int rd
)
9682 bool is_double
= (size
== 3);
9685 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9686 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9689 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9690 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9691 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9693 if (is_u
) { /* USQADD */
9694 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9695 } else { /* SUQADD */
9696 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9698 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9700 tcg_temp_free_i64(tcg_rd
);
9701 tcg_temp_free_i64(tcg_rn
);
9702 clear_vec_high(s
, !is_scalar
, rd
);
9704 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9705 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9706 int pass
, maxpasses
;
9711 maxpasses
= is_q
? 4 : 2;
9714 for (pass
= 0; pass
< maxpasses
; pass
++) {
9716 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9717 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9719 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9720 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9723 if (is_u
) { /* USQADD */
9726 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9729 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9732 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9735 g_assert_not_reached();
9737 } else { /* SUQADD */
9740 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9743 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9746 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9749 g_assert_not_reached();
9754 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9755 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9756 tcg_temp_free_i64(tcg_zero
);
9758 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9760 tcg_temp_free_i32(tcg_rd
);
9761 tcg_temp_free_i32(tcg_rn
);
9762 clear_vec_high(s
, is_q
, rd
);
9766 /* AdvSIMD scalar two reg misc
9767 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9768 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9769 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9770 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9772 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9774 int rd
= extract32(insn
, 0, 5);
9775 int rn
= extract32(insn
, 5, 5);
9776 int opcode
= extract32(insn
, 12, 5);
9777 int size
= extract32(insn
, 22, 2);
9778 bool u
= extract32(insn
, 29, 1);
9779 bool is_fcvt
= false;
9782 TCGv_ptr tcg_fpstatus
;
9785 case 0x3: /* USQADD / SUQADD*/
9786 if (!fp_access_check(s
)) {
9789 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9791 case 0x7: /* SQABS / SQNEG */
9793 case 0xa: /* CMLT */
9795 unallocated_encoding(s
);
9799 case 0x8: /* CMGT, CMGE */
9800 case 0x9: /* CMEQ, CMLE */
9801 case 0xb: /* ABS, NEG */
9803 unallocated_encoding(s
);
9807 case 0x12: /* SQXTUN */
9809 unallocated_encoding(s
);
9813 case 0x14: /* SQXTN, UQXTN */
9815 unallocated_encoding(s
);
9818 if (!fp_access_check(s
)) {
9821 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9826 /* Floating point: U, size[1] and opcode indicate operation;
9827 * size[0] indicates single or double precision.
9829 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9830 size
= extract32(size
, 0, 1) ? 3 : 2;
9832 case 0x2c: /* FCMGT (zero) */
9833 case 0x2d: /* FCMEQ (zero) */
9834 case 0x2e: /* FCMLT (zero) */
9835 case 0x6c: /* FCMGE (zero) */
9836 case 0x6d: /* FCMLE (zero) */
9837 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9839 case 0x1d: /* SCVTF */
9840 case 0x5d: /* UCVTF */
9842 bool is_signed
= (opcode
== 0x1d);
9843 if (!fp_access_check(s
)) {
9846 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9849 case 0x3d: /* FRECPE */
9850 case 0x3f: /* FRECPX */
9851 case 0x7d: /* FRSQRTE */
9852 if (!fp_access_check(s
)) {
9855 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9857 case 0x1a: /* FCVTNS */
9858 case 0x1b: /* FCVTMS */
9859 case 0x3a: /* FCVTPS */
9860 case 0x3b: /* FCVTZS */
9861 case 0x5a: /* FCVTNU */
9862 case 0x5b: /* FCVTMU */
9863 case 0x7a: /* FCVTPU */
9864 case 0x7b: /* FCVTZU */
9866 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9868 case 0x1c: /* FCVTAS */
9869 case 0x5c: /* FCVTAU */
9870 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9872 rmode
= FPROUNDING_TIEAWAY
;
9874 case 0x56: /* FCVTXN, FCVTXN2 */
9876 unallocated_encoding(s
);
9879 if (!fp_access_check(s
)) {
9882 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9885 unallocated_encoding(s
);
9890 unallocated_encoding(s
);
9894 if (!fp_access_check(s
)) {
9899 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9900 tcg_fpstatus
= get_fpstatus_ptr(false);
9901 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9904 tcg_fpstatus
= NULL
;
9908 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9909 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9911 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9912 write_fp_dreg(s
, rd
, tcg_rd
);
9913 tcg_temp_free_i64(tcg_rd
);
9914 tcg_temp_free_i64(tcg_rn
);
9916 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9917 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9919 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9922 case 0x7: /* SQABS, SQNEG */
9924 NeonGenOneOpEnvFn
*genfn
;
9925 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9926 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9927 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9928 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9930 genfn
= fns
[size
][u
];
9931 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9934 case 0x1a: /* FCVTNS */
9935 case 0x1b: /* FCVTMS */
9936 case 0x1c: /* FCVTAS */
9937 case 0x3a: /* FCVTPS */
9938 case 0x3b: /* FCVTZS */
9940 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9941 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9942 tcg_temp_free_i32(tcg_shift
);
9945 case 0x5a: /* FCVTNU */
9946 case 0x5b: /* FCVTMU */
9947 case 0x5c: /* FCVTAU */
9948 case 0x7a: /* FCVTPU */
9949 case 0x7b: /* FCVTZU */
9951 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9952 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9953 tcg_temp_free_i32(tcg_shift
);
9957 g_assert_not_reached();
9960 write_fp_sreg(s
, rd
, tcg_rd
);
9961 tcg_temp_free_i32(tcg_rd
);
9962 tcg_temp_free_i32(tcg_rn
);
9966 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9967 tcg_temp_free_i32(tcg_rmode
);
9968 tcg_temp_free_ptr(tcg_fpstatus
);
9972 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9973 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9974 int immh
, int immb
, int opcode
, int rn
, int rd
)
9976 int size
= 32 - clz32(immh
) - 1;
9977 int immhb
= immh
<< 3 | immb
;
9978 int shift
= 2 * (8 << size
) - immhb
;
9979 bool accumulate
= false;
9980 int dsize
= is_q
? 128 : 64;
9981 int esize
= 8 << size
;
9982 int elements
= dsize
/esize
;
9983 MemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9984 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9985 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9987 uint64_t round_const
;
9990 if (extract32(immh
, 3, 1) && !is_q
) {
9991 unallocated_encoding(s
);
9994 tcg_debug_assert(size
<= 3);
9996 if (!fp_access_check(s
)) {
10001 case 0x02: /* SSRA / USRA (accumulate) */
10003 /* Shift count same as element size produces zero to add. */
10004 if (shift
== 8 << size
) {
10007 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
10009 /* Shift count same as element size produces all sign to add. */
10010 if (shift
== 8 << size
) {
10013 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
10016 case 0x08: /* SRI */
10017 /* Shift count same as element size is valid but does nothing. */
10018 if (shift
== 8 << size
) {
10021 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
10024 case 0x00: /* SSHR / USHR */
10026 if (shift
== 8 << size
) {
10027 /* Shift count the same size as element size produces zero. */
10028 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
10029 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10031 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10034 /* Shift count the same size as element size produces all sign. */
10035 if (shift
== 8 << size
) {
10038 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10042 case 0x04: /* SRSHR / URSHR (rounding) */
10044 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10048 g_assert_not_reached();
10051 round_const
= 1ULL << (shift
- 1);
10052 tcg_round
= tcg_const_i64(round_const
);
10054 for (i
= 0; i
< elements
; i
++) {
10055 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10057 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10060 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10061 accumulate
, is_u
, size
, shift
);
10063 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10065 tcg_temp_free_i64(tcg_round
);
10068 clear_vec_high(s
, is_q
, rd
);
10071 /* SHL/SLI - Vector shift left */
10072 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10073 int immh
, int immb
, int opcode
, int rn
, int rd
)
10075 int size
= 32 - clz32(immh
) - 1;
10076 int immhb
= immh
<< 3 | immb
;
10077 int shift
= immhb
- (8 << size
);
10079 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10080 assert(size
>= 0 && size
<= 3);
10082 if (extract32(immh
, 3, 1) && !is_q
) {
10083 unallocated_encoding(s
);
10087 if (!fp_access_check(s
)) {
10092 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10094 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10098 /* USHLL/SHLL - Vector shift left with widening */
10099 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10100 int immh
, int immb
, int opcode
, int rn
, int rd
)
10102 int size
= 32 - clz32(immh
) - 1;
10103 int immhb
= immh
<< 3 | immb
;
10104 int shift
= immhb
- (8 << size
);
10106 int esize
= 8 << size
;
10107 int elements
= dsize
/esize
;
10108 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10109 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10113 unallocated_encoding(s
);
10117 if (!fp_access_check(s
)) {
10121 /* For the LL variants the store is larger than the load,
10122 * so if rd == rn we would overwrite parts of our input.
10123 * So load everything right now and use shifts in the main loop.
10125 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10127 for (i
= 0; i
< elements
; i
++) {
10128 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10129 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10130 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10131 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10135 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10136 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10137 int immh
, int immb
, int opcode
, int rn
, int rd
)
10139 int immhb
= immh
<< 3 | immb
;
10140 int size
= 32 - clz32(immh
) - 1;
10142 int esize
= 8 << size
;
10143 int elements
= dsize
/esize
;
10144 int shift
= (2 * esize
) - immhb
;
10145 bool round
= extract32(opcode
, 0, 1);
10146 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10147 TCGv_i64 tcg_round
;
10150 if (extract32(immh
, 3, 1)) {
10151 unallocated_encoding(s
);
10155 if (!fp_access_check(s
)) {
10159 tcg_rn
= tcg_temp_new_i64();
10160 tcg_rd
= tcg_temp_new_i64();
10161 tcg_final
= tcg_temp_new_i64();
10162 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10165 uint64_t round_const
= 1ULL << (shift
- 1);
10166 tcg_round
= tcg_const_i64(round_const
);
10171 for (i
= 0; i
< elements
; i
++) {
10172 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10173 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10174 false, true, size
+1, shift
);
10176 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10180 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10182 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10185 tcg_temp_free_i64(tcg_round
);
10187 tcg_temp_free_i64(tcg_rn
);
10188 tcg_temp_free_i64(tcg_rd
);
10189 tcg_temp_free_i64(tcg_final
);
10191 clear_vec_high(s
, is_q
, rd
);
10195 /* AdvSIMD shift by immediate
10196 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10197 * +---+---+---+-------------+------+------+--------+---+------+------+
10198 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10199 * +---+---+---+-------------+------+------+--------+---+------+------+
10201 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10203 int rd
= extract32(insn
, 0, 5);
10204 int rn
= extract32(insn
, 5, 5);
10205 int opcode
= extract32(insn
, 11, 5);
10206 int immb
= extract32(insn
, 16, 3);
10207 int immh
= extract32(insn
, 19, 4);
10208 bool is_u
= extract32(insn
, 29, 1);
10209 bool is_q
= extract32(insn
, 30, 1);
10212 case 0x08: /* SRI */
10214 unallocated_encoding(s
);
10218 case 0x00: /* SSHR / USHR */
10219 case 0x02: /* SSRA / USRA (accumulate) */
10220 case 0x04: /* SRSHR / URSHR (rounding) */
10221 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10222 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10224 case 0x0a: /* SHL / SLI */
10225 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10227 case 0x10: /* SHRN */
10228 case 0x11: /* RSHRN / SQRSHRUN */
10230 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10233 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10236 case 0x12: /* SQSHRN / UQSHRN */
10237 case 0x13: /* SQRSHRN / UQRSHRN */
10238 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10241 case 0x14: /* SSHLL / USHLL */
10242 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10244 case 0x1c: /* SCVTF / UCVTF */
10245 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10248 case 0xc: /* SQSHLU */
10250 unallocated_encoding(s
);
10253 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10255 case 0xe: /* SQSHL, UQSHL */
10256 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10258 case 0x1f: /* FCVTZS/ FCVTZU */
10259 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10262 unallocated_encoding(s
);
10267 /* Generate code to do a "long" addition or subtraction, ie one done in
10268 * TCGv_i64 on vector lanes twice the width specified by size.
10270 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10271 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10273 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10274 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10275 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10276 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10278 NeonGenTwo64OpFn
*genfn
;
10281 genfn
= fns
[size
][is_sub
];
10282 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10285 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10286 int opcode
, int rd
, int rn
, int rm
)
10288 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10289 TCGv_i64 tcg_res
[2];
10292 tcg_res
[0] = tcg_temp_new_i64();
10293 tcg_res
[1] = tcg_temp_new_i64();
10295 /* Does this op do an adding accumulate, a subtracting accumulate,
10296 * or no accumulate at all?
10314 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10315 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10318 /* size == 2 means two 32x32->64 operations; this is worth special
10319 * casing because we can generally handle it inline.
10322 for (pass
= 0; pass
< 2; pass
++) {
10323 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10324 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10325 TCGv_i64 tcg_passres
;
10326 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10328 int elt
= pass
+ is_q
* 2;
10330 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10331 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10334 tcg_passres
= tcg_res
[pass
];
10336 tcg_passres
= tcg_temp_new_i64();
10340 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10341 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10343 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10344 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10346 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10347 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10349 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10350 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10352 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10353 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10354 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10356 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10357 tcg_temp_free_i64(tcg_tmp1
);
10358 tcg_temp_free_i64(tcg_tmp2
);
10361 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10362 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10363 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10364 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10366 case 9: /* SQDMLAL, SQDMLAL2 */
10367 case 11: /* SQDMLSL, SQDMLSL2 */
10368 case 13: /* SQDMULL, SQDMULL2 */
10369 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10370 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10371 tcg_passres
, tcg_passres
);
10374 g_assert_not_reached();
10377 if (opcode
== 9 || opcode
== 11) {
10378 /* saturating accumulate ops */
10380 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10382 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10383 tcg_res
[pass
], tcg_passres
);
10384 } else if (accop
> 0) {
10385 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10386 } else if (accop
< 0) {
10387 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10391 tcg_temp_free_i64(tcg_passres
);
10394 tcg_temp_free_i64(tcg_op1
);
10395 tcg_temp_free_i64(tcg_op2
);
10398 /* size 0 or 1, generally helper functions */
10399 for (pass
= 0; pass
< 2; pass
++) {
10400 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10401 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10402 TCGv_i64 tcg_passres
;
10403 int elt
= pass
+ is_q
* 2;
10405 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10406 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10409 tcg_passres
= tcg_res
[pass
];
10411 tcg_passres
= tcg_temp_new_i64();
10415 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10416 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10418 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10419 static NeonGenWidenFn
* const widenfns
[2][2] = {
10420 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10421 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10423 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10425 widenfn(tcg_op2_64
, tcg_op2
);
10426 widenfn(tcg_passres
, tcg_op1
);
10427 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10428 tcg_passres
, tcg_op2_64
);
10429 tcg_temp_free_i64(tcg_op2_64
);
10432 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10433 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10436 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10438 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10442 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10444 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10448 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10449 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10450 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10453 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10455 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10459 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10461 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10465 case 9: /* SQDMLAL, SQDMLAL2 */
10466 case 11: /* SQDMLSL, SQDMLSL2 */
10467 case 13: /* SQDMULL, SQDMULL2 */
10469 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10470 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10471 tcg_passres
, tcg_passres
);
10473 case 14: /* PMULL */
10475 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10478 g_assert_not_reached();
10480 tcg_temp_free_i32(tcg_op1
);
10481 tcg_temp_free_i32(tcg_op2
);
10484 if (opcode
== 9 || opcode
== 11) {
10485 /* saturating accumulate ops */
10487 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10489 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10493 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10494 tcg_res
[pass
], tcg_passres
);
10496 tcg_temp_free_i64(tcg_passres
);
10501 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10502 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10503 tcg_temp_free_i64(tcg_res
[0]);
10504 tcg_temp_free_i64(tcg_res
[1]);
10507 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10508 int opcode
, int rd
, int rn
, int rm
)
10510 TCGv_i64 tcg_res
[2];
10511 int part
= is_q
? 2 : 0;
10514 for (pass
= 0; pass
< 2; pass
++) {
10515 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10516 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10517 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10518 static NeonGenWidenFn
* const widenfns
[3][2] = {
10519 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10520 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10521 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10523 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10525 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10526 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10527 widenfn(tcg_op2_wide
, tcg_op2
);
10528 tcg_temp_free_i32(tcg_op2
);
10529 tcg_res
[pass
] = tcg_temp_new_i64();
10530 gen_neon_addl(size
, (opcode
== 3),
10531 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10532 tcg_temp_free_i64(tcg_op1
);
10533 tcg_temp_free_i64(tcg_op2_wide
);
10536 for (pass
= 0; pass
< 2; pass
++) {
10537 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10538 tcg_temp_free_i64(tcg_res
[pass
]);
10542 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10544 tcg_gen_addi_i64(in
, in
, 1U << 31);
10545 tcg_gen_extrh_i64_i32(res
, in
);
10548 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10549 int opcode
, int rd
, int rn
, int rm
)
10551 TCGv_i32 tcg_res
[2];
10552 int part
= is_q
? 2 : 0;
10555 for (pass
= 0; pass
< 2; pass
++) {
10556 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10557 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10558 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10559 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10560 { gen_helper_neon_narrow_high_u8
,
10561 gen_helper_neon_narrow_round_high_u8
},
10562 { gen_helper_neon_narrow_high_u16
,
10563 gen_helper_neon_narrow_round_high_u16
},
10564 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10566 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10568 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10569 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10571 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10573 tcg_temp_free_i64(tcg_op1
);
10574 tcg_temp_free_i64(tcg_op2
);
10576 tcg_res
[pass
] = tcg_temp_new_i32();
10577 gennarrow(tcg_res
[pass
], tcg_wideres
);
10578 tcg_temp_free_i64(tcg_wideres
);
10581 for (pass
= 0; pass
< 2; pass
++) {
10582 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10583 tcg_temp_free_i32(tcg_res
[pass
]);
10585 clear_vec_high(s
, is_q
, rd
);
10588 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10590 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10591 * is the only three-reg-diff instruction which produces a
10592 * 128-bit wide result from a single operation. However since
10593 * it's possible to calculate the two halves more or less
10594 * separately we just use two helper calls.
10596 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10597 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10598 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10600 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10601 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10602 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10603 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10604 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10605 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10607 tcg_temp_free_i64(tcg_op1
);
10608 tcg_temp_free_i64(tcg_op2
);
10609 tcg_temp_free_i64(tcg_res
);
10612 /* AdvSIMD three different
10613 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10614 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10615 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10616 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10618 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10620 /* Instructions in this group fall into three basic classes
10621 * (in each case with the operation working on each element in
10622 * the input vectors):
10623 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10625 * (2) wide 64 x 128 -> 128
10626 * (3) narrowing 128 x 128 -> 64
10627 * Here we do initial decode, catch unallocated cases and
10628 * dispatch to separate functions for each class.
10630 int is_q
= extract32(insn
, 30, 1);
10631 int is_u
= extract32(insn
, 29, 1);
10632 int size
= extract32(insn
, 22, 2);
10633 int opcode
= extract32(insn
, 12, 4);
10634 int rm
= extract32(insn
, 16, 5);
10635 int rn
= extract32(insn
, 5, 5);
10636 int rd
= extract32(insn
, 0, 5);
10639 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10640 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10641 /* 64 x 128 -> 128 */
10643 unallocated_encoding(s
);
10646 if (!fp_access_check(s
)) {
10649 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10651 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10652 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10653 /* 128 x 128 -> 64 */
10655 unallocated_encoding(s
);
10658 if (!fp_access_check(s
)) {
10661 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10663 case 14: /* PMULL, PMULL2 */
10664 if (is_u
|| size
== 1 || size
== 2) {
10665 unallocated_encoding(s
);
10669 if (!dc_isar_feature(aa64_pmull
, s
)) {
10670 unallocated_encoding(s
);
10673 if (!fp_access_check(s
)) {
10676 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10680 case 9: /* SQDMLAL, SQDMLAL2 */
10681 case 11: /* SQDMLSL, SQDMLSL2 */
10682 case 13: /* SQDMULL, SQDMULL2 */
10683 if (is_u
|| size
== 0) {
10684 unallocated_encoding(s
);
10688 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10689 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10690 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10691 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10692 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10693 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10694 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10695 /* 64 x 64 -> 128 */
10697 unallocated_encoding(s
);
10701 if (!fp_access_check(s
)) {
10705 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10708 /* opcode 15 not allocated */
10709 unallocated_encoding(s
);
10714 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10715 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10717 int rd
= extract32(insn
, 0, 5);
10718 int rn
= extract32(insn
, 5, 5);
10719 int rm
= extract32(insn
, 16, 5);
10720 int size
= extract32(insn
, 22, 2);
10721 bool is_u
= extract32(insn
, 29, 1);
10722 bool is_q
= extract32(insn
, 30, 1);
10724 if (!fp_access_check(s
)) {
10728 switch (size
+ 4 * is_u
) {
10730 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10733 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10736 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10739 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10742 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10745 case 5: /* BSL bitwise select */
10746 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10748 case 6: /* BIT, bitwise insert if true */
10749 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10751 case 7: /* BIF, bitwise insert if false */
10752 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10756 g_assert_not_reached();
10760 /* Pairwise op subgroup of C3.6.16.
10762 * This is called directly or via the handle_3same_float for float pairwise
10763 * operations where the opcode and size are calculated differently.
10765 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10766 int size
, int rn
, int rm
, int rd
)
10771 /* Floating point operations need fpst */
10772 if (opcode
>= 0x58) {
10773 fpst
= get_fpstatus_ptr(false);
10778 if (!fp_access_check(s
)) {
10782 /* These operations work on the concatenated rm:rn, with each pair of
10783 * adjacent elements being operated on to produce an element in the result.
10786 TCGv_i64 tcg_res
[2];
10788 for (pass
= 0; pass
< 2; pass
++) {
10789 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10790 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10791 int passreg
= (pass
== 0) ? rn
: rm
;
10793 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10794 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10795 tcg_res
[pass
] = tcg_temp_new_i64();
10798 case 0x17: /* ADDP */
10799 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10801 case 0x58: /* FMAXNMP */
10802 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10804 case 0x5a: /* FADDP */
10805 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10807 case 0x5e: /* FMAXP */
10808 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10810 case 0x78: /* FMINNMP */
10811 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10813 case 0x7e: /* FMINP */
10814 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10817 g_assert_not_reached();
10820 tcg_temp_free_i64(tcg_op1
);
10821 tcg_temp_free_i64(tcg_op2
);
10824 for (pass
= 0; pass
< 2; pass
++) {
10825 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10826 tcg_temp_free_i64(tcg_res
[pass
]);
10829 int maxpass
= is_q
? 4 : 2;
10830 TCGv_i32 tcg_res
[4];
10832 for (pass
= 0; pass
< maxpass
; pass
++) {
10833 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10834 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10835 NeonGenTwoOpFn
*genfn
= NULL
;
10836 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10837 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10839 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10840 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10841 tcg_res
[pass
] = tcg_temp_new_i32();
10844 case 0x17: /* ADDP */
10846 static NeonGenTwoOpFn
* const fns
[3] = {
10847 gen_helper_neon_padd_u8
,
10848 gen_helper_neon_padd_u16
,
10854 case 0x14: /* SMAXP, UMAXP */
10856 static NeonGenTwoOpFn
* const fns
[3][2] = {
10857 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10858 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10859 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10861 genfn
= fns
[size
][u
];
10864 case 0x15: /* SMINP, UMINP */
10866 static NeonGenTwoOpFn
* const fns
[3][2] = {
10867 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10868 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10869 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10871 genfn
= fns
[size
][u
];
10874 /* The FP operations are all on single floats (32 bit) */
10875 case 0x58: /* FMAXNMP */
10876 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10878 case 0x5a: /* FADDP */
10879 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10881 case 0x5e: /* FMAXP */
10882 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10884 case 0x78: /* FMINNMP */
10885 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10887 case 0x7e: /* FMINP */
10888 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10891 g_assert_not_reached();
10894 /* FP ops called directly, otherwise call now */
10896 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10899 tcg_temp_free_i32(tcg_op1
);
10900 tcg_temp_free_i32(tcg_op2
);
10903 for (pass
= 0; pass
< maxpass
; pass
++) {
10904 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10905 tcg_temp_free_i32(tcg_res
[pass
]);
10907 clear_vec_high(s
, is_q
, rd
);
10911 tcg_temp_free_ptr(fpst
);
10915 /* Floating point op subgroup of C3.6.16. */
10916 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10918 /* For floating point ops, the U, size[1] and opcode bits
10919 * together indicate the operation. size[0] indicates single
10922 int fpopcode
= extract32(insn
, 11, 5)
10923 | (extract32(insn
, 23, 1) << 5)
10924 | (extract32(insn
, 29, 1) << 6);
10925 int is_q
= extract32(insn
, 30, 1);
10926 int size
= extract32(insn
, 22, 1);
10927 int rm
= extract32(insn
, 16, 5);
10928 int rn
= extract32(insn
, 5, 5);
10929 int rd
= extract32(insn
, 0, 5);
10931 int datasize
= is_q
? 128 : 64;
10932 int esize
= 32 << size
;
10933 int elements
= datasize
/ esize
;
10935 if (size
== 1 && !is_q
) {
10936 unallocated_encoding(s
);
10940 switch (fpopcode
) {
10941 case 0x58: /* FMAXNMP */
10942 case 0x5a: /* FADDP */
10943 case 0x5e: /* FMAXP */
10944 case 0x78: /* FMINNMP */
10945 case 0x7e: /* FMINP */
10946 if (size
&& !is_q
) {
10947 unallocated_encoding(s
);
10950 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10953 case 0x1b: /* FMULX */
10954 case 0x1f: /* FRECPS */
10955 case 0x3f: /* FRSQRTS */
10956 case 0x5d: /* FACGE */
10957 case 0x7d: /* FACGT */
10958 case 0x19: /* FMLA */
10959 case 0x39: /* FMLS */
10960 case 0x18: /* FMAXNM */
10961 case 0x1a: /* FADD */
10962 case 0x1c: /* FCMEQ */
10963 case 0x1e: /* FMAX */
10964 case 0x38: /* FMINNM */
10965 case 0x3a: /* FSUB */
10966 case 0x3e: /* FMIN */
10967 case 0x5b: /* FMUL */
10968 case 0x5c: /* FCMGE */
10969 case 0x5f: /* FDIV */
10970 case 0x7a: /* FABD */
10971 case 0x7c: /* FCMGT */
10972 if (!fp_access_check(s
)) {
10975 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10978 case 0x1d: /* FMLAL */
10979 case 0x3d: /* FMLSL */
10980 case 0x59: /* FMLAL2 */
10981 case 0x79: /* FMLSL2 */
10982 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
10983 unallocated_encoding(s
);
10986 if (fp_access_check(s
)) {
10987 int is_s
= extract32(insn
, 23, 1);
10988 int is_2
= extract32(insn
, 29, 1);
10989 int data
= (is_2
<< 1) | is_s
;
10990 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
10991 vec_full_reg_offset(s
, rn
),
10992 vec_full_reg_offset(s
, rm
), cpu_env
,
10993 is_q
? 16 : 8, vec_full_reg_size(s
),
10994 data
, gen_helper_gvec_fmlal_a64
);
10999 unallocated_encoding(s
);
11004 /* Integer op subgroup of C3.6.16. */
11005 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11007 int is_q
= extract32(insn
, 30, 1);
11008 int u
= extract32(insn
, 29, 1);
11009 int size
= extract32(insn
, 22, 2);
11010 int opcode
= extract32(insn
, 11, 5);
11011 int rm
= extract32(insn
, 16, 5);
11012 int rn
= extract32(insn
, 5, 5);
11013 int rd
= extract32(insn
, 0, 5);
11018 case 0x13: /* MUL, PMUL */
11019 if (u
&& size
!= 0) {
11020 unallocated_encoding(s
);
11024 case 0x0: /* SHADD, UHADD */
11025 case 0x2: /* SRHADD, URHADD */
11026 case 0x4: /* SHSUB, UHSUB */
11027 case 0xc: /* SMAX, UMAX */
11028 case 0xd: /* SMIN, UMIN */
11029 case 0xe: /* SABD, UABD */
11030 case 0xf: /* SABA, UABA */
11031 case 0x12: /* MLA, MLS */
11033 unallocated_encoding(s
);
11037 case 0x16: /* SQDMULH, SQRDMULH */
11038 if (size
== 0 || size
== 3) {
11039 unallocated_encoding(s
);
11044 if (size
== 3 && !is_q
) {
11045 unallocated_encoding(s
);
11051 if (!fp_access_check(s
)) {
11056 case 0x01: /* SQADD, UQADD */
11057 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11058 offsetof(CPUARMState
, vfp
.qc
),
11059 vec_full_reg_offset(s
, rn
),
11060 vec_full_reg_offset(s
, rm
),
11061 is_q
? 16 : 8, vec_full_reg_size(s
),
11062 (u
? uqadd_op
: sqadd_op
) + size
);
11064 case 0x05: /* SQSUB, UQSUB */
11065 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11066 offsetof(CPUARMState
, vfp
.qc
),
11067 vec_full_reg_offset(s
, rn
),
11068 vec_full_reg_offset(s
, rm
),
11069 is_q
? 16 : 8, vec_full_reg_size(s
),
11070 (u
? uqsub_op
: sqsub_op
) + size
);
11072 case 0x0c: /* SMAX, UMAX */
11074 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11076 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11079 case 0x0d: /* SMIN, UMIN */
11081 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11083 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11086 case 0x10: /* ADD, SUB */
11088 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11090 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11093 case 0x13: /* MUL, PMUL */
11094 if (!u
) { /* MUL */
11095 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11099 case 0x12: /* MLA, MLS */
11101 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11103 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11107 if (!u
) { /* CMTST */
11108 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11112 cond
= TCG_COND_EQ
;
11114 case 0x06: /* CMGT, CMHI */
11115 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11117 case 0x07: /* CMGE, CMHS */
11118 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11120 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11121 vec_full_reg_offset(s
, rn
),
11122 vec_full_reg_offset(s
, rm
),
11123 is_q
? 16 : 8, vec_full_reg_size(s
));
11129 for (pass
= 0; pass
< 2; pass
++) {
11130 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11131 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11132 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11134 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11135 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11137 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11139 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11141 tcg_temp_free_i64(tcg_res
);
11142 tcg_temp_free_i64(tcg_op1
);
11143 tcg_temp_free_i64(tcg_op2
);
11146 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11147 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11148 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11149 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11150 NeonGenTwoOpFn
*genfn
= NULL
;
11151 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11153 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11154 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11157 case 0x0: /* SHADD, UHADD */
11159 static NeonGenTwoOpFn
* const fns
[3][2] = {
11160 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11161 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11162 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11164 genfn
= fns
[size
][u
];
11167 case 0x2: /* SRHADD, URHADD */
11169 static NeonGenTwoOpFn
* const fns
[3][2] = {
11170 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11171 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11172 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11174 genfn
= fns
[size
][u
];
11177 case 0x4: /* SHSUB, UHSUB */
11179 static NeonGenTwoOpFn
* const fns
[3][2] = {
11180 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11181 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11182 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11184 genfn
= fns
[size
][u
];
11187 case 0x8: /* SSHL, USHL */
11189 static NeonGenTwoOpFn
* const fns
[3][2] = {
11190 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11191 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11192 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11194 genfn
= fns
[size
][u
];
11197 case 0x9: /* SQSHL, UQSHL */
11199 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11200 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11201 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11202 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11204 genenvfn
= fns
[size
][u
];
11207 case 0xa: /* SRSHL, URSHL */
11209 static NeonGenTwoOpFn
* const fns
[3][2] = {
11210 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11211 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11212 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11214 genfn
= fns
[size
][u
];
11217 case 0xb: /* SQRSHL, UQRSHL */
11219 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11220 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11221 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11222 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11224 genenvfn
= fns
[size
][u
];
11227 case 0xe: /* SABD, UABD */
11228 case 0xf: /* SABA, UABA */
11230 static NeonGenTwoOpFn
* const fns
[3][2] = {
11231 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11232 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11233 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11235 genfn
= fns
[size
][u
];
11238 case 0x13: /* MUL, PMUL */
11239 assert(u
); /* PMUL */
11241 genfn
= gen_helper_neon_mul_p8
;
11243 case 0x16: /* SQDMULH, SQRDMULH */
11245 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11246 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11247 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11249 assert(size
== 1 || size
== 2);
11250 genenvfn
= fns
[size
- 1][u
];
11254 g_assert_not_reached();
11258 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11260 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11263 if (opcode
== 0xf) {
11264 /* SABA, UABA: accumulating ops */
11265 static NeonGenTwoOpFn
* const fns
[3] = {
11266 gen_helper_neon_add_u8
,
11267 gen_helper_neon_add_u16
,
11271 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11272 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11275 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11277 tcg_temp_free_i32(tcg_res
);
11278 tcg_temp_free_i32(tcg_op1
);
11279 tcg_temp_free_i32(tcg_op2
);
11282 clear_vec_high(s
, is_q
, rd
);
11285 /* AdvSIMD three same
11286 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11287 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11288 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11289 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11291 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11293 int opcode
= extract32(insn
, 11, 5);
11296 case 0x3: /* logic ops */
11297 disas_simd_3same_logic(s
, insn
);
11299 case 0x17: /* ADDP */
11300 case 0x14: /* SMAXP, UMAXP */
11301 case 0x15: /* SMINP, UMINP */
11303 /* Pairwise operations */
11304 int is_q
= extract32(insn
, 30, 1);
11305 int u
= extract32(insn
, 29, 1);
11306 int size
= extract32(insn
, 22, 2);
11307 int rm
= extract32(insn
, 16, 5);
11308 int rn
= extract32(insn
, 5, 5);
11309 int rd
= extract32(insn
, 0, 5);
11310 if (opcode
== 0x17) {
11311 if (u
|| (size
== 3 && !is_q
)) {
11312 unallocated_encoding(s
);
11317 unallocated_encoding(s
);
11321 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11324 case 0x18 ... 0x31:
11325 /* floating point ops, sz[1] and U are part of opcode */
11326 disas_simd_3same_float(s
, insn
);
11329 disas_simd_3same_int(s
, insn
);
11335 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11337 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11338 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11339 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11340 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11342 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11343 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11346 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11348 int opcode
, fpopcode
;
11349 int is_q
, u
, a
, rm
, rn
, rd
;
11350 int datasize
, elements
;
11353 bool pairwise
= false;
11355 if (!dc_isar_feature(aa64_fp16
, s
)) {
11356 unallocated_encoding(s
);
11360 if (!fp_access_check(s
)) {
11364 /* For these floating point ops, the U, a and opcode bits
11365 * together indicate the operation.
11367 opcode
= extract32(insn
, 11, 3);
11368 u
= extract32(insn
, 29, 1);
11369 a
= extract32(insn
, 23, 1);
11370 is_q
= extract32(insn
, 30, 1);
11371 rm
= extract32(insn
, 16, 5);
11372 rn
= extract32(insn
, 5, 5);
11373 rd
= extract32(insn
, 0, 5);
11375 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11376 datasize
= is_q
? 128 : 64;
11377 elements
= datasize
/ 16;
11379 switch (fpopcode
) {
11380 case 0x10: /* FMAXNMP */
11381 case 0x12: /* FADDP */
11382 case 0x16: /* FMAXP */
11383 case 0x18: /* FMINNMP */
11384 case 0x1e: /* FMINP */
11389 fpst
= get_fpstatus_ptr(true);
11392 int maxpass
= is_q
? 8 : 4;
11393 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11394 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11395 TCGv_i32 tcg_res
[8];
11397 for (pass
= 0; pass
< maxpass
; pass
++) {
11398 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11399 int passelt
= (pass
<< 1) & (maxpass
- 1);
11401 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11402 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11403 tcg_res
[pass
] = tcg_temp_new_i32();
11405 switch (fpopcode
) {
11406 case 0x10: /* FMAXNMP */
11407 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11410 case 0x12: /* FADDP */
11411 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11413 case 0x16: /* FMAXP */
11414 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11416 case 0x18: /* FMINNMP */
11417 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11420 case 0x1e: /* FMINP */
11421 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11424 g_assert_not_reached();
11428 for (pass
= 0; pass
< maxpass
; pass
++) {
11429 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11430 tcg_temp_free_i32(tcg_res
[pass
]);
11433 tcg_temp_free_i32(tcg_op1
);
11434 tcg_temp_free_i32(tcg_op2
);
11437 for (pass
= 0; pass
< elements
; pass
++) {
11438 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11439 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11440 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11442 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11443 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11445 switch (fpopcode
) {
11446 case 0x0: /* FMAXNM */
11447 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11449 case 0x1: /* FMLA */
11450 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11451 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11454 case 0x2: /* FADD */
11455 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11457 case 0x3: /* FMULX */
11458 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11460 case 0x4: /* FCMEQ */
11461 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11463 case 0x6: /* FMAX */
11464 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11466 case 0x7: /* FRECPS */
11467 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11469 case 0x8: /* FMINNM */
11470 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11472 case 0x9: /* FMLS */
11473 /* As usual for ARM, separate negation for fused multiply-add */
11474 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11475 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11476 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11479 case 0xa: /* FSUB */
11480 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11482 case 0xe: /* FMIN */
11483 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11485 case 0xf: /* FRSQRTS */
11486 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11488 case 0x13: /* FMUL */
11489 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11491 case 0x14: /* FCMGE */
11492 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11494 case 0x15: /* FACGE */
11495 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11497 case 0x17: /* FDIV */
11498 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11500 case 0x1a: /* FABD */
11501 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11502 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11504 case 0x1c: /* FCMGT */
11505 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11507 case 0x1d: /* FACGT */
11508 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11511 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11512 __func__
, insn
, fpopcode
, s
->pc_curr
);
11513 g_assert_not_reached();
11516 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11517 tcg_temp_free_i32(tcg_res
);
11518 tcg_temp_free_i32(tcg_op1
);
11519 tcg_temp_free_i32(tcg_op2
);
11523 tcg_temp_free_ptr(fpst
);
11525 clear_vec_high(s
, is_q
, rd
);
11528 /* AdvSIMD three same extra
11529 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11530 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11531 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11532 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11534 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11536 int rd
= extract32(insn
, 0, 5);
11537 int rn
= extract32(insn
, 5, 5);
11538 int opcode
= extract32(insn
, 11, 4);
11539 int rm
= extract32(insn
, 16, 5);
11540 int size
= extract32(insn
, 22, 2);
11541 bool u
= extract32(insn
, 29, 1);
11542 bool is_q
= extract32(insn
, 30, 1);
11546 switch (u
* 16 + opcode
) {
11547 case 0x10: /* SQRDMLAH (vector) */
11548 case 0x11: /* SQRDMLSH (vector) */
11549 if (size
!= 1 && size
!= 2) {
11550 unallocated_encoding(s
);
11553 feature
= dc_isar_feature(aa64_rdm
, s
);
11555 case 0x02: /* SDOT (vector) */
11556 case 0x12: /* UDOT (vector) */
11557 if (size
!= MO_32
) {
11558 unallocated_encoding(s
);
11561 feature
= dc_isar_feature(aa64_dp
, s
);
11563 case 0x18: /* FCMLA, #0 */
11564 case 0x19: /* FCMLA, #90 */
11565 case 0x1a: /* FCMLA, #180 */
11566 case 0x1b: /* FCMLA, #270 */
11567 case 0x1c: /* FCADD, #90 */
11568 case 0x1e: /* FCADD, #270 */
11570 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11571 || (size
== 3 && !is_q
)) {
11572 unallocated_encoding(s
);
11575 feature
= dc_isar_feature(aa64_fcma
, s
);
11578 unallocated_encoding(s
);
11582 unallocated_encoding(s
);
11585 if (!fp_access_check(s
)) {
11590 case 0x0: /* SQRDMLAH (vector) */
11593 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11596 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11599 g_assert_not_reached();
11603 case 0x1: /* SQRDMLSH (vector) */
11606 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11609 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11612 g_assert_not_reached();
11616 case 0x2: /* SDOT / UDOT */
11617 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11618 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11621 case 0x8: /* FCMLA, #0 */
11622 case 0x9: /* FCMLA, #90 */
11623 case 0xa: /* FCMLA, #180 */
11624 case 0xb: /* FCMLA, #270 */
11625 rot
= extract32(opcode
, 0, 2);
11628 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11629 gen_helper_gvec_fcmlah
);
11632 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11633 gen_helper_gvec_fcmlas
);
11636 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11637 gen_helper_gvec_fcmlad
);
11640 g_assert_not_reached();
11644 case 0xc: /* FCADD, #90 */
11645 case 0xe: /* FCADD, #270 */
11646 rot
= extract32(opcode
, 1, 1);
11649 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11650 gen_helper_gvec_fcaddh
);
11653 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11654 gen_helper_gvec_fcadds
);
11657 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11658 gen_helper_gvec_fcaddd
);
11661 g_assert_not_reached();
11666 g_assert_not_reached();
11670 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11671 int size
, int rn
, int rd
)
11673 /* Handle 2-reg-misc ops which are widening (so each size element
11674 * in the source becomes a 2*size element in the destination.
11675 * The only instruction like this is FCVTL.
11680 /* 32 -> 64 bit fp conversion */
11681 TCGv_i64 tcg_res
[2];
11682 int srcelt
= is_q
? 2 : 0;
11684 for (pass
= 0; pass
< 2; pass
++) {
11685 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11686 tcg_res
[pass
] = tcg_temp_new_i64();
11688 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11689 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11690 tcg_temp_free_i32(tcg_op
);
11692 for (pass
= 0; pass
< 2; pass
++) {
11693 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11694 tcg_temp_free_i64(tcg_res
[pass
]);
11697 /* 16 -> 32 bit fp conversion */
11698 int srcelt
= is_q
? 4 : 0;
11699 TCGv_i32 tcg_res
[4];
11700 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11701 TCGv_i32 ahp
= get_ahp_flag();
11703 for (pass
= 0; pass
< 4; pass
++) {
11704 tcg_res
[pass
] = tcg_temp_new_i32();
11706 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11707 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11710 for (pass
= 0; pass
< 4; pass
++) {
11711 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11712 tcg_temp_free_i32(tcg_res
[pass
]);
11715 tcg_temp_free_ptr(fpst
);
11716 tcg_temp_free_i32(ahp
);
11720 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11721 bool is_q
, int size
, int rn
, int rd
)
11723 int op
= (opcode
<< 1) | u
;
11724 int opsz
= op
+ size
;
11725 int grp_size
= 3 - opsz
;
11726 int dsize
= is_q
? 128 : 64;
11730 unallocated_encoding(s
);
11734 if (!fp_access_check(s
)) {
11739 /* Special case bytes, use bswap op on each group of elements */
11740 int groups
= dsize
/ (8 << grp_size
);
11742 for (i
= 0; i
< groups
; i
++) {
11743 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11745 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11746 switch (grp_size
) {
11748 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11751 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11754 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11757 g_assert_not_reached();
11759 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11760 tcg_temp_free_i64(tcg_tmp
);
11762 clear_vec_high(s
, is_q
, rd
);
11764 int revmask
= (1 << grp_size
) - 1;
11765 int esize
= 8 << size
;
11766 int elements
= dsize
/ esize
;
11767 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11768 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11769 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11771 for (i
= 0; i
< elements
; i
++) {
11772 int e_rev
= (i
& 0xf) ^ revmask
;
11773 int off
= e_rev
* esize
;
11774 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11776 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11777 tcg_rn
, off
- 64, esize
);
11779 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11782 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11783 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11785 tcg_temp_free_i64(tcg_rd_hi
);
11786 tcg_temp_free_i64(tcg_rd
);
11787 tcg_temp_free_i64(tcg_rn
);
11791 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11792 bool is_q
, int size
, int rn
, int rd
)
11794 /* Implement the pairwise operations from 2-misc:
11795 * SADDLP, UADDLP, SADALP, UADALP.
11796 * These all add pairs of elements in the input to produce a
11797 * double-width result element in the output (possibly accumulating).
11799 bool accum
= (opcode
== 0x6);
11800 int maxpass
= is_q
? 2 : 1;
11802 TCGv_i64 tcg_res
[2];
11805 /* 32 + 32 -> 64 op */
11806 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11808 for (pass
= 0; pass
< maxpass
; pass
++) {
11809 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11810 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11812 tcg_res
[pass
] = tcg_temp_new_i64();
11814 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11815 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11816 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11818 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11819 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11822 tcg_temp_free_i64(tcg_op1
);
11823 tcg_temp_free_i64(tcg_op2
);
11826 for (pass
= 0; pass
< maxpass
; pass
++) {
11827 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11828 NeonGenOneOpFn
*genfn
;
11829 static NeonGenOneOpFn
* const fns
[2][2] = {
11830 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11831 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11834 genfn
= fns
[size
][u
];
11836 tcg_res
[pass
] = tcg_temp_new_i64();
11838 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11839 genfn(tcg_res
[pass
], tcg_op
);
11842 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11844 gen_helper_neon_addl_u16(tcg_res
[pass
],
11845 tcg_res
[pass
], tcg_op
);
11847 gen_helper_neon_addl_u32(tcg_res
[pass
],
11848 tcg_res
[pass
], tcg_op
);
11851 tcg_temp_free_i64(tcg_op
);
11855 tcg_res
[1] = tcg_const_i64(0);
11857 for (pass
= 0; pass
< 2; pass
++) {
11858 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11859 tcg_temp_free_i64(tcg_res
[pass
]);
11863 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11865 /* Implement SHLL and SHLL2 */
11867 int part
= is_q
? 2 : 0;
11868 TCGv_i64 tcg_res
[2];
11870 for (pass
= 0; pass
< 2; pass
++) {
11871 static NeonGenWidenFn
* const widenfns
[3] = {
11872 gen_helper_neon_widen_u8
,
11873 gen_helper_neon_widen_u16
,
11874 tcg_gen_extu_i32_i64
,
11876 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11877 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11879 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11880 tcg_res
[pass
] = tcg_temp_new_i64();
11881 widenfn(tcg_res
[pass
], tcg_op
);
11882 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11884 tcg_temp_free_i32(tcg_op
);
11887 for (pass
= 0; pass
< 2; pass
++) {
11888 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11889 tcg_temp_free_i64(tcg_res
[pass
]);
11893 /* AdvSIMD two reg misc
11894 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11895 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11896 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11897 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11899 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11901 int size
= extract32(insn
, 22, 2);
11902 int opcode
= extract32(insn
, 12, 5);
11903 bool u
= extract32(insn
, 29, 1);
11904 bool is_q
= extract32(insn
, 30, 1);
11905 int rn
= extract32(insn
, 5, 5);
11906 int rd
= extract32(insn
, 0, 5);
11907 bool need_fpstatus
= false;
11908 bool need_rmode
= false;
11910 TCGv_i32 tcg_rmode
;
11911 TCGv_ptr tcg_fpstatus
;
11914 case 0x0: /* REV64, REV32 */
11915 case 0x1: /* REV16 */
11916 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11918 case 0x5: /* CNT, NOT, RBIT */
11919 if (u
&& size
== 0) {
11922 } else if (u
&& size
== 1) {
11925 } else if (!u
&& size
== 0) {
11929 unallocated_encoding(s
);
11931 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11932 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11934 unallocated_encoding(s
);
11937 if (!fp_access_check(s
)) {
11941 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11943 case 0x4: /* CLS, CLZ */
11945 unallocated_encoding(s
);
11949 case 0x2: /* SADDLP, UADDLP */
11950 case 0x6: /* SADALP, UADALP */
11952 unallocated_encoding(s
);
11955 if (!fp_access_check(s
)) {
11958 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11960 case 0x13: /* SHLL, SHLL2 */
11961 if (u
== 0 || size
== 3) {
11962 unallocated_encoding(s
);
11965 if (!fp_access_check(s
)) {
11968 handle_shll(s
, is_q
, size
, rn
, rd
);
11970 case 0xa: /* CMLT */
11972 unallocated_encoding(s
);
11976 case 0x8: /* CMGT, CMGE */
11977 case 0x9: /* CMEQ, CMLE */
11978 case 0xb: /* ABS, NEG */
11979 if (size
== 3 && !is_q
) {
11980 unallocated_encoding(s
);
11984 case 0x3: /* SUQADD, USQADD */
11985 if (size
== 3 && !is_q
) {
11986 unallocated_encoding(s
);
11989 if (!fp_access_check(s
)) {
11992 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11994 case 0x7: /* SQABS, SQNEG */
11995 if (size
== 3 && !is_q
) {
11996 unallocated_encoding(s
);
12001 case 0x16 ... 0x1f:
12003 /* Floating point: U, size[1] and opcode indicate operation;
12004 * size[0] indicates single or double precision.
12006 int is_double
= extract32(size
, 0, 1);
12007 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12008 size
= is_double
? 3 : 2;
12010 case 0x2f: /* FABS */
12011 case 0x6f: /* FNEG */
12012 if (size
== 3 && !is_q
) {
12013 unallocated_encoding(s
);
12017 case 0x1d: /* SCVTF */
12018 case 0x5d: /* UCVTF */
12020 bool is_signed
= (opcode
== 0x1d) ? true : false;
12021 int elements
= is_double
? 2 : is_q
? 4 : 2;
12022 if (is_double
&& !is_q
) {
12023 unallocated_encoding(s
);
12026 if (!fp_access_check(s
)) {
12029 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12032 case 0x2c: /* FCMGT (zero) */
12033 case 0x2d: /* FCMEQ (zero) */
12034 case 0x2e: /* FCMLT (zero) */
12035 case 0x6c: /* FCMGE (zero) */
12036 case 0x6d: /* FCMLE (zero) */
12037 if (size
== 3 && !is_q
) {
12038 unallocated_encoding(s
);
12041 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12043 case 0x7f: /* FSQRT */
12044 if (size
== 3 && !is_q
) {
12045 unallocated_encoding(s
);
12049 case 0x1a: /* FCVTNS */
12050 case 0x1b: /* FCVTMS */
12051 case 0x3a: /* FCVTPS */
12052 case 0x3b: /* FCVTZS */
12053 case 0x5a: /* FCVTNU */
12054 case 0x5b: /* FCVTMU */
12055 case 0x7a: /* FCVTPU */
12056 case 0x7b: /* FCVTZU */
12057 need_fpstatus
= true;
12059 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12060 if (size
== 3 && !is_q
) {
12061 unallocated_encoding(s
);
12065 case 0x5c: /* FCVTAU */
12066 case 0x1c: /* FCVTAS */
12067 need_fpstatus
= true;
12069 rmode
= FPROUNDING_TIEAWAY
;
12070 if (size
== 3 && !is_q
) {
12071 unallocated_encoding(s
);
12075 case 0x3c: /* URECPE */
12077 unallocated_encoding(s
);
12081 case 0x3d: /* FRECPE */
12082 case 0x7d: /* FRSQRTE */
12083 if (size
== 3 && !is_q
) {
12084 unallocated_encoding(s
);
12087 if (!fp_access_check(s
)) {
12090 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12092 case 0x56: /* FCVTXN, FCVTXN2 */
12094 unallocated_encoding(s
);
12098 case 0x16: /* FCVTN, FCVTN2 */
12099 /* handle_2misc_narrow does a 2*size -> size operation, but these
12100 * instructions encode the source size rather than dest size.
12102 if (!fp_access_check(s
)) {
12105 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12107 case 0x17: /* FCVTL, FCVTL2 */
12108 if (!fp_access_check(s
)) {
12111 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12113 case 0x18: /* FRINTN */
12114 case 0x19: /* FRINTM */
12115 case 0x38: /* FRINTP */
12116 case 0x39: /* FRINTZ */
12118 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12120 case 0x59: /* FRINTX */
12121 case 0x79: /* FRINTI */
12122 need_fpstatus
= true;
12123 if (size
== 3 && !is_q
) {
12124 unallocated_encoding(s
);
12128 case 0x58: /* FRINTA */
12130 rmode
= FPROUNDING_TIEAWAY
;
12131 need_fpstatus
= true;
12132 if (size
== 3 && !is_q
) {
12133 unallocated_encoding(s
);
12137 case 0x7c: /* URSQRTE */
12139 unallocated_encoding(s
);
12142 need_fpstatus
= true;
12144 case 0x1e: /* FRINT32Z */
12145 case 0x1f: /* FRINT64Z */
12147 rmode
= FPROUNDING_ZERO
;
12149 case 0x5e: /* FRINT32X */
12150 case 0x5f: /* FRINT64X */
12151 need_fpstatus
= true;
12152 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12153 unallocated_encoding(s
);
12158 unallocated_encoding(s
);
12164 unallocated_encoding(s
);
12168 if (!fp_access_check(s
)) {
12172 if (need_fpstatus
|| need_rmode
) {
12173 tcg_fpstatus
= get_fpstatus_ptr(false);
12175 tcg_fpstatus
= NULL
;
12178 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12179 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12186 if (u
&& size
== 0) { /* NOT */
12187 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12192 if (u
) { /* ABS, NEG */
12193 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12195 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12201 /* All 64-bit element operations can be shared with scalar 2misc */
12204 /* Coverity claims (size == 3 && !is_q) has been eliminated
12205 * from all paths leading to here.
12207 tcg_debug_assert(is_q
);
12208 for (pass
= 0; pass
< 2; pass
++) {
12209 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12210 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12212 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12214 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12215 tcg_rmode
, tcg_fpstatus
);
12217 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12219 tcg_temp_free_i64(tcg_res
);
12220 tcg_temp_free_i64(tcg_op
);
12225 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12226 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12227 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12230 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12233 /* Special cases for 32 bit elements */
12235 case 0xa: /* CMLT */
12236 /* 32 bit integer comparison against zero, result is
12237 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12240 cond
= TCG_COND_LT
;
12242 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12243 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12245 case 0x8: /* CMGT, CMGE */
12246 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12248 case 0x9: /* CMEQ, CMLE */
12249 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12251 case 0x4: /* CLS */
12253 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12255 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12258 case 0x7: /* SQABS, SQNEG */
12260 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12262 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12265 case 0x2f: /* FABS */
12266 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12268 case 0x6f: /* FNEG */
12269 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12271 case 0x7f: /* FSQRT */
12272 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12274 case 0x1a: /* FCVTNS */
12275 case 0x1b: /* FCVTMS */
12276 case 0x1c: /* FCVTAS */
12277 case 0x3a: /* FCVTPS */
12278 case 0x3b: /* FCVTZS */
12280 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12281 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12282 tcg_shift
, tcg_fpstatus
);
12283 tcg_temp_free_i32(tcg_shift
);
12286 case 0x5a: /* FCVTNU */
12287 case 0x5b: /* FCVTMU */
12288 case 0x5c: /* FCVTAU */
12289 case 0x7a: /* FCVTPU */
12290 case 0x7b: /* FCVTZU */
12292 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12293 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12294 tcg_shift
, tcg_fpstatus
);
12295 tcg_temp_free_i32(tcg_shift
);
12298 case 0x18: /* FRINTN */
12299 case 0x19: /* FRINTM */
12300 case 0x38: /* FRINTP */
12301 case 0x39: /* FRINTZ */
12302 case 0x58: /* FRINTA */
12303 case 0x79: /* FRINTI */
12304 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12306 case 0x59: /* FRINTX */
12307 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12309 case 0x7c: /* URSQRTE */
12310 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12312 case 0x1e: /* FRINT32Z */
12313 case 0x5e: /* FRINT32X */
12314 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12316 case 0x1f: /* FRINT64Z */
12317 case 0x5f: /* FRINT64X */
12318 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12321 g_assert_not_reached();
12324 /* Use helpers for 8 and 16 bit elements */
12326 case 0x5: /* CNT, RBIT */
12327 /* For these two insns size is part of the opcode specifier
12328 * (handled earlier); they always operate on byte elements.
12331 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12333 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12336 case 0x7: /* SQABS, SQNEG */
12338 NeonGenOneOpEnvFn
*genfn
;
12339 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12340 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12341 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12343 genfn
= fns
[size
][u
];
12344 genfn(tcg_res
, cpu_env
, tcg_op
);
12347 case 0x8: /* CMGT, CMGE */
12348 case 0x9: /* CMEQ, CMLE */
12349 case 0xa: /* CMLT */
12351 static NeonGenTwoOpFn
* const fns
[3][2] = {
12352 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12353 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12354 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12356 NeonGenTwoOpFn
*genfn
;
12359 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12361 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12362 comp
= (opcode
- 0x8) * 2 + u
;
12363 /* ...but LE, LT are implemented as reverse GE, GT */
12364 reverse
= (comp
> 2);
12368 genfn
= fns
[comp
][size
];
12370 genfn(tcg_res
, tcg_zero
, tcg_op
);
12372 genfn(tcg_res
, tcg_op
, tcg_zero
);
12374 tcg_temp_free_i32(tcg_zero
);
12377 case 0x4: /* CLS, CLZ */
12380 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12382 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12386 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12388 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12393 g_assert_not_reached();
12397 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12399 tcg_temp_free_i32(tcg_res
);
12400 tcg_temp_free_i32(tcg_op
);
12403 clear_vec_high(s
, is_q
, rd
);
12406 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12407 tcg_temp_free_i32(tcg_rmode
);
12409 if (need_fpstatus
) {
12410 tcg_temp_free_ptr(tcg_fpstatus
);
12414 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12416 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12417 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12418 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12419 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12420 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12421 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12423 * This actually covers two groups where scalar access is governed by
12424 * bit 28. A bunch of the instructions (float to integral) only exist
12425 * in the vector form and are un-allocated for the scalar decode. Also
12426 * in the scalar decode Q is always 1.
12428 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12430 int fpop
, opcode
, a
, u
;
12434 bool only_in_vector
= false;
12437 TCGv_i32 tcg_rmode
= NULL
;
12438 TCGv_ptr tcg_fpstatus
= NULL
;
12439 bool need_rmode
= false;
12440 bool need_fpst
= true;
12443 if (!dc_isar_feature(aa64_fp16
, s
)) {
12444 unallocated_encoding(s
);
12448 rd
= extract32(insn
, 0, 5);
12449 rn
= extract32(insn
, 5, 5);
12451 a
= extract32(insn
, 23, 1);
12452 u
= extract32(insn
, 29, 1);
12453 is_scalar
= extract32(insn
, 28, 1);
12454 is_q
= extract32(insn
, 30, 1);
12456 opcode
= extract32(insn
, 12, 5);
12457 fpop
= deposit32(opcode
, 5, 1, a
);
12458 fpop
= deposit32(fpop
, 6, 1, u
);
12460 rd
= extract32(insn
, 0, 5);
12461 rn
= extract32(insn
, 5, 5);
12464 case 0x1d: /* SCVTF */
12465 case 0x5d: /* UCVTF */
12472 elements
= (is_q
? 8 : 4);
12475 if (!fp_access_check(s
)) {
12478 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12482 case 0x2c: /* FCMGT (zero) */
12483 case 0x2d: /* FCMEQ (zero) */
12484 case 0x2e: /* FCMLT (zero) */
12485 case 0x6c: /* FCMGE (zero) */
12486 case 0x6d: /* FCMLE (zero) */
12487 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12489 case 0x3d: /* FRECPE */
12490 case 0x3f: /* FRECPX */
12492 case 0x18: /* FRINTN */
12494 only_in_vector
= true;
12495 rmode
= FPROUNDING_TIEEVEN
;
12497 case 0x19: /* FRINTM */
12499 only_in_vector
= true;
12500 rmode
= FPROUNDING_NEGINF
;
12502 case 0x38: /* FRINTP */
12504 only_in_vector
= true;
12505 rmode
= FPROUNDING_POSINF
;
12507 case 0x39: /* FRINTZ */
12509 only_in_vector
= true;
12510 rmode
= FPROUNDING_ZERO
;
12512 case 0x58: /* FRINTA */
12514 only_in_vector
= true;
12515 rmode
= FPROUNDING_TIEAWAY
;
12517 case 0x59: /* FRINTX */
12518 case 0x79: /* FRINTI */
12519 only_in_vector
= true;
12520 /* current rounding mode */
12522 case 0x1a: /* FCVTNS */
12524 rmode
= FPROUNDING_TIEEVEN
;
12526 case 0x1b: /* FCVTMS */
12528 rmode
= FPROUNDING_NEGINF
;
12530 case 0x1c: /* FCVTAS */
12532 rmode
= FPROUNDING_TIEAWAY
;
12534 case 0x3a: /* FCVTPS */
12536 rmode
= FPROUNDING_POSINF
;
12538 case 0x3b: /* FCVTZS */
12540 rmode
= FPROUNDING_ZERO
;
12542 case 0x5a: /* FCVTNU */
12544 rmode
= FPROUNDING_TIEEVEN
;
12546 case 0x5b: /* FCVTMU */
12548 rmode
= FPROUNDING_NEGINF
;
12550 case 0x5c: /* FCVTAU */
12552 rmode
= FPROUNDING_TIEAWAY
;
12554 case 0x7a: /* FCVTPU */
12556 rmode
= FPROUNDING_POSINF
;
12558 case 0x7b: /* FCVTZU */
12560 rmode
= FPROUNDING_ZERO
;
12562 case 0x2f: /* FABS */
12563 case 0x6f: /* FNEG */
12566 case 0x7d: /* FRSQRTE */
12567 case 0x7f: /* FSQRT (vector) */
12570 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12571 g_assert_not_reached();
12575 /* Check additional constraints for the scalar encoding */
12578 unallocated_encoding(s
);
12581 /* FRINTxx is only in the vector form */
12582 if (only_in_vector
) {
12583 unallocated_encoding(s
);
12588 if (!fp_access_check(s
)) {
12592 if (need_rmode
|| need_fpst
) {
12593 tcg_fpstatus
= get_fpstatus_ptr(true);
12597 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12598 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12602 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12603 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12606 case 0x1a: /* FCVTNS */
12607 case 0x1b: /* FCVTMS */
12608 case 0x1c: /* FCVTAS */
12609 case 0x3a: /* FCVTPS */
12610 case 0x3b: /* FCVTZS */
12611 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12613 case 0x3d: /* FRECPE */
12614 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12616 case 0x3f: /* FRECPX */
12617 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12619 case 0x5a: /* FCVTNU */
12620 case 0x5b: /* FCVTMU */
12621 case 0x5c: /* FCVTAU */
12622 case 0x7a: /* FCVTPU */
12623 case 0x7b: /* FCVTZU */
12624 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12626 case 0x6f: /* FNEG */
12627 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12629 case 0x7d: /* FRSQRTE */
12630 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12633 g_assert_not_reached();
12636 /* limit any sign extension going on */
12637 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12638 write_fp_sreg(s
, rd
, tcg_res
);
12640 tcg_temp_free_i32(tcg_res
);
12641 tcg_temp_free_i32(tcg_op
);
12643 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12644 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12645 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12647 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12650 case 0x1a: /* FCVTNS */
12651 case 0x1b: /* FCVTMS */
12652 case 0x1c: /* FCVTAS */
12653 case 0x3a: /* FCVTPS */
12654 case 0x3b: /* FCVTZS */
12655 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12657 case 0x3d: /* FRECPE */
12658 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12660 case 0x5a: /* FCVTNU */
12661 case 0x5b: /* FCVTMU */
12662 case 0x5c: /* FCVTAU */
12663 case 0x7a: /* FCVTPU */
12664 case 0x7b: /* FCVTZU */
12665 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12667 case 0x18: /* FRINTN */
12668 case 0x19: /* FRINTM */
12669 case 0x38: /* FRINTP */
12670 case 0x39: /* FRINTZ */
12671 case 0x58: /* FRINTA */
12672 case 0x79: /* FRINTI */
12673 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12675 case 0x59: /* FRINTX */
12676 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12678 case 0x2f: /* FABS */
12679 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12681 case 0x6f: /* FNEG */
12682 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12684 case 0x7d: /* FRSQRTE */
12685 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12687 case 0x7f: /* FSQRT */
12688 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12691 g_assert_not_reached();
12694 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12696 tcg_temp_free_i32(tcg_res
);
12697 tcg_temp_free_i32(tcg_op
);
12700 clear_vec_high(s
, is_q
, rd
);
12704 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12705 tcg_temp_free_i32(tcg_rmode
);
12708 if (tcg_fpstatus
) {
12709 tcg_temp_free_ptr(tcg_fpstatus
);
12713 /* AdvSIMD scalar x indexed element
12714 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12715 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12716 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12717 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12718 * AdvSIMD vector x indexed element
12719 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12720 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12721 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12722 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12724 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12726 /* This encoding has two kinds of instruction:
12727 * normal, where we perform elt x idxelt => elt for each
12728 * element in the vector
12729 * long, where we perform elt x idxelt and generate a result of
12730 * double the width of the input element
12731 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12733 bool is_scalar
= extract32(insn
, 28, 1);
12734 bool is_q
= extract32(insn
, 30, 1);
12735 bool u
= extract32(insn
, 29, 1);
12736 int size
= extract32(insn
, 22, 2);
12737 int l
= extract32(insn
, 21, 1);
12738 int m
= extract32(insn
, 20, 1);
12739 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12740 int rm
= extract32(insn
, 16, 4);
12741 int opcode
= extract32(insn
, 12, 4);
12742 int h
= extract32(insn
, 11, 1);
12743 int rn
= extract32(insn
, 5, 5);
12744 int rd
= extract32(insn
, 0, 5);
12745 bool is_long
= false;
12747 bool is_fp16
= false;
12751 switch (16 * u
+ opcode
) {
12752 case 0x08: /* MUL */
12753 case 0x10: /* MLA */
12754 case 0x14: /* MLS */
12756 unallocated_encoding(s
);
12760 case 0x02: /* SMLAL, SMLAL2 */
12761 case 0x12: /* UMLAL, UMLAL2 */
12762 case 0x06: /* SMLSL, SMLSL2 */
12763 case 0x16: /* UMLSL, UMLSL2 */
12764 case 0x0a: /* SMULL, SMULL2 */
12765 case 0x1a: /* UMULL, UMULL2 */
12767 unallocated_encoding(s
);
12772 case 0x03: /* SQDMLAL, SQDMLAL2 */
12773 case 0x07: /* SQDMLSL, SQDMLSL2 */
12774 case 0x0b: /* SQDMULL, SQDMULL2 */
12777 case 0x0c: /* SQDMULH */
12778 case 0x0d: /* SQRDMULH */
12780 case 0x01: /* FMLA */
12781 case 0x05: /* FMLS */
12782 case 0x09: /* FMUL */
12783 case 0x19: /* FMULX */
12786 case 0x1d: /* SQRDMLAH */
12787 case 0x1f: /* SQRDMLSH */
12788 if (!dc_isar_feature(aa64_rdm
, s
)) {
12789 unallocated_encoding(s
);
12793 case 0x0e: /* SDOT */
12794 case 0x1e: /* UDOT */
12795 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12796 unallocated_encoding(s
);
12800 case 0x11: /* FCMLA #0 */
12801 case 0x13: /* FCMLA #90 */
12802 case 0x15: /* FCMLA #180 */
12803 case 0x17: /* FCMLA #270 */
12804 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12805 unallocated_encoding(s
);
12810 case 0x00: /* FMLAL */
12811 case 0x04: /* FMLSL */
12812 case 0x18: /* FMLAL2 */
12813 case 0x1c: /* FMLSL2 */
12814 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12815 unallocated_encoding(s
);
12819 /* is_fp, but we pass cpu_env not fp_status. */
12822 unallocated_encoding(s
);
12827 case 1: /* normal fp */
12828 /* convert insn encoded size to MemOp size */
12830 case 0: /* half-precision */
12834 case MO_32
: /* single precision */
12835 case MO_64
: /* double precision */
12838 unallocated_encoding(s
);
12843 case 2: /* complex fp */
12844 /* Each indexable element is a complex pair. */
12849 unallocated_encoding(s
);
12857 unallocated_encoding(s
);
12862 default: /* integer */
12866 unallocated_encoding(s
);
12871 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12872 unallocated_encoding(s
);
12876 /* Given MemOp size, adjust register and indexing. */
12879 index
= h
<< 2 | l
<< 1 | m
;
12882 index
= h
<< 1 | l
;
12887 unallocated_encoding(s
);
12894 g_assert_not_reached();
12897 if (!fp_access_check(s
)) {
12902 fpst
= get_fpstatus_ptr(is_fp16
);
12907 switch (16 * u
+ opcode
) {
12908 case 0x0e: /* SDOT */
12909 case 0x1e: /* UDOT */
12910 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12911 u
? gen_helper_gvec_udot_idx_b
12912 : gen_helper_gvec_sdot_idx_b
);
12914 case 0x11: /* FCMLA #0 */
12915 case 0x13: /* FCMLA #90 */
12916 case 0x15: /* FCMLA #180 */
12917 case 0x17: /* FCMLA #270 */
12919 int rot
= extract32(insn
, 13, 2);
12920 int data
= (index
<< 2) | rot
;
12921 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12922 vec_full_reg_offset(s
, rn
),
12923 vec_full_reg_offset(s
, rm
), fpst
,
12924 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12926 ? gen_helper_gvec_fcmlas_idx
12927 : gen_helper_gvec_fcmlah_idx
);
12928 tcg_temp_free_ptr(fpst
);
12932 case 0x00: /* FMLAL */
12933 case 0x04: /* FMLSL */
12934 case 0x18: /* FMLAL2 */
12935 case 0x1c: /* FMLSL2 */
12937 int is_s
= extract32(opcode
, 2, 1);
12939 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
12940 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12941 vec_full_reg_offset(s
, rn
),
12942 vec_full_reg_offset(s
, rm
), cpu_env
,
12943 is_q
? 16 : 8, vec_full_reg_size(s
),
12944 data
, gen_helper_gvec_fmlal_idx_a64
);
12950 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12953 assert(is_fp
&& is_q
&& !is_long
);
12955 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12957 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12958 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12959 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12961 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12963 switch (16 * u
+ opcode
) {
12964 case 0x05: /* FMLS */
12965 /* As usual for ARM, separate negation for fused multiply-add */
12966 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12968 case 0x01: /* FMLA */
12969 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12970 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12972 case 0x09: /* FMUL */
12973 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12975 case 0x19: /* FMULX */
12976 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12979 g_assert_not_reached();
12982 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12983 tcg_temp_free_i64(tcg_op
);
12984 tcg_temp_free_i64(tcg_res
);
12987 tcg_temp_free_i64(tcg_idx
);
12988 clear_vec_high(s
, !is_scalar
, rd
);
12989 } else if (!is_long
) {
12990 /* 32 bit floating point, or 16 or 32 bit integer.
12991 * For the 16 bit scalar case we use the usual Neon helpers and
12992 * rely on the fact that 0 op 0 == 0 with no side effects.
12994 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12995 int pass
, maxpasses
;
13000 maxpasses
= is_q
? 4 : 2;
13003 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13005 if (size
== 1 && !is_scalar
) {
13006 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13007 * the index into both halves of the 32 bit tcg_idx and then use
13008 * the usual Neon helpers.
13010 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13013 for (pass
= 0; pass
< maxpasses
; pass
++) {
13014 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13015 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13017 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13019 switch (16 * u
+ opcode
) {
13020 case 0x08: /* MUL */
13021 case 0x10: /* MLA */
13022 case 0x14: /* MLS */
13024 static NeonGenTwoOpFn
* const fns
[2][2] = {
13025 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13026 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13028 NeonGenTwoOpFn
*genfn
;
13029 bool is_sub
= opcode
== 0x4;
13032 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13034 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13036 if (opcode
== 0x8) {
13039 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13040 genfn
= fns
[size
- 1][is_sub
];
13041 genfn(tcg_res
, tcg_op
, tcg_res
);
13044 case 0x05: /* FMLS */
13045 case 0x01: /* FMLA */
13046 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13047 is_scalar
? size
: MO_32
);
13050 if (opcode
== 0x5) {
13051 /* As usual for ARM, separate negation for fused
13053 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13056 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13059 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13064 if (opcode
== 0x5) {
13065 /* As usual for ARM, separate negation for
13066 * fused multiply-add */
13067 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13069 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13073 g_assert_not_reached();
13076 case 0x09: /* FMUL */
13080 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13083 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13088 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13091 g_assert_not_reached();
13094 case 0x19: /* FMULX */
13098 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13101 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13106 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13109 g_assert_not_reached();
13112 case 0x0c: /* SQDMULH */
13114 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13117 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13121 case 0x0d: /* SQRDMULH */
13123 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13126 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13130 case 0x1d: /* SQRDMLAH */
13131 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13132 is_scalar
? size
: MO_32
);
13134 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13135 tcg_op
, tcg_idx
, tcg_res
);
13137 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13138 tcg_op
, tcg_idx
, tcg_res
);
13141 case 0x1f: /* SQRDMLSH */
13142 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13143 is_scalar
? size
: MO_32
);
13145 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13146 tcg_op
, tcg_idx
, tcg_res
);
13148 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13149 tcg_op
, tcg_idx
, tcg_res
);
13153 g_assert_not_reached();
13157 write_fp_sreg(s
, rd
, tcg_res
);
13159 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13162 tcg_temp_free_i32(tcg_op
);
13163 tcg_temp_free_i32(tcg_res
);
13166 tcg_temp_free_i32(tcg_idx
);
13167 clear_vec_high(s
, is_q
, rd
);
13169 /* long ops: 16x16->32 or 32x32->64 */
13170 TCGv_i64 tcg_res
[2];
13172 bool satop
= extract32(opcode
, 0, 1);
13173 MemOp memop
= MO_32
;
13180 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13182 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13184 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13185 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13186 TCGv_i64 tcg_passres
;
13192 passelt
= pass
+ (is_q
* 2);
13195 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13197 tcg_res
[pass
] = tcg_temp_new_i64();
13199 if (opcode
== 0xa || opcode
== 0xb) {
13200 /* Non-accumulating ops */
13201 tcg_passres
= tcg_res
[pass
];
13203 tcg_passres
= tcg_temp_new_i64();
13206 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13207 tcg_temp_free_i64(tcg_op
);
13210 /* saturating, doubling */
13211 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13212 tcg_passres
, tcg_passres
);
13215 if (opcode
== 0xa || opcode
== 0xb) {
13219 /* Accumulating op: handle accumulate step */
13220 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13223 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13224 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13226 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13227 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13229 case 0x7: /* SQDMLSL, SQDMLSL2 */
13230 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13232 case 0x3: /* SQDMLAL, SQDMLAL2 */
13233 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13238 g_assert_not_reached();
13240 tcg_temp_free_i64(tcg_passres
);
13242 tcg_temp_free_i64(tcg_idx
);
13244 clear_vec_high(s
, !is_scalar
, rd
);
13246 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13249 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13252 /* The simplest way to handle the 16x16 indexed ops is to
13253 * duplicate the index into both halves of the 32 bit tcg_idx
13254 * and then use the usual Neon helpers.
13256 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13259 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13260 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13261 TCGv_i64 tcg_passres
;
13264 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13266 read_vec_element_i32(s
, tcg_op
, rn
,
13267 pass
+ (is_q
* 2), MO_32
);
13270 tcg_res
[pass
] = tcg_temp_new_i64();
13272 if (opcode
== 0xa || opcode
== 0xb) {
13273 /* Non-accumulating ops */
13274 tcg_passres
= tcg_res
[pass
];
13276 tcg_passres
= tcg_temp_new_i64();
13279 if (memop
& MO_SIGN
) {
13280 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13282 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13285 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13286 tcg_passres
, tcg_passres
);
13288 tcg_temp_free_i32(tcg_op
);
13290 if (opcode
== 0xa || opcode
== 0xb) {
13294 /* Accumulating op: handle accumulate step */
13295 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13298 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13299 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13302 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13303 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13306 case 0x7: /* SQDMLSL, SQDMLSL2 */
13307 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13309 case 0x3: /* SQDMLAL, SQDMLAL2 */
13310 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13315 g_assert_not_reached();
13317 tcg_temp_free_i64(tcg_passres
);
13319 tcg_temp_free_i32(tcg_idx
);
13322 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13327 tcg_res
[1] = tcg_const_i64(0);
13330 for (pass
= 0; pass
< 2; pass
++) {
13331 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13332 tcg_temp_free_i64(tcg_res
[pass
]);
13337 tcg_temp_free_ptr(fpst
);
13342 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13343 * +-----------------+------+-----------+--------+-----+------+------+
13344 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13345 * +-----------------+------+-----------+--------+-----+------+------+
13347 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13349 int size
= extract32(insn
, 22, 2);
13350 int opcode
= extract32(insn
, 12, 5);
13351 int rn
= extract32(insn
, 5, 5);
13352 int rd
= extract32(insn
, 0, 5);
13354 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13355 TCGv_i32 tcg_decrypt
;
13356 CryptoThreeOpIntFn
*genfn
;
13358 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13359 unallocated_encoding(s
);
13364 case 0x4: /* AESE */
13366 genfn
= gen_helper_crypto_aese
;
13368 case 0x6: /* AESMC */
13370 genfn
= gen_helper_crypto_aesmc
;
13372 case 0x5: /* AESD */
13374 genfn
= gen_helper_crypto_aese
;
13376 case 0x7: /* AESIMC */
13378 genfn
= gen_helper_crypto_aesmc
;
13381 unallocated_encoding(s
);
13385 if (!fp_access_check(s
)) {
13389 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13390 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13391 tcg_decrypt
= tcg_const_i32(decrypt
);
13393 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13395 tcg_temp_free_ptr(tcg_rd_ptr
);
13396 tcg_temp_free_ptr(tcg_rn_ptr
);
13397 tcg_temp_free_i32(tcg_decrypt
);
13400 /* Crypto three-reg SHA
13401 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13402 * +-----------------+------+---+------+---+--------+-----+------+------+
13403 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13404 * +-----------------+------+---+------+---+--------+-----+------+------+
13406 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13408 int size
= extract32(insn
, 22, 2);
13409 int opcode
= extract32(insn
, 12, 3);
13410 int rm
= extract32(insn
, 16, 5);
13411 int rn
= extract32(insn
, 5, 5);
13412 int rd
= extract32(insn
, 0, 5);
13413 CryptoThreeOpFn
*genfn
;
13414 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13418 unallocated_encoding(s
);
13423 case 0: /* SHA1C */
13424 case 1: /* SHA1P */
13425 case 2: /* SHA1M */
13426 case 3: /* SHA1SU0 */
13428 feature
= dc_isar_feature(aa64_sha1
, s
);
13430 case 4: /* SHA256H */
13431 genfn
= gen_helper_crypto_sha256h
;
13432 feature
= dc_isar_feature(aa64_sha256
, s
);
13434 case 5: /* SHA256H2 */
13435 genfn
= gen_helper_crypto_sha256h2
;
13436 feature
= dc_isar_feature(aa64_sha256
, s
);
13438 case 6: /* SHA256SU1 */
13439 genfn
= gen_helper_crypto_sha256su1
;
13440 feature
= dc_isar_feature(aa64_sha256
, s
);
13443 unallocated_encoding(s
);
13448 unallocated_encoding(s
);
13452 if (!fp_access_check(s
)) {
13456 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13457 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13458 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13461 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13463 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13465 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13466 tcg_rm_ptr
, tcg_opcode
);
13467 tcg_temp_free_i32(tcg_opcode
);
13470 tcg_temp_free_ptr(tcg_rd_ptr
);
13471 tcg_temp_free_ptr(tcg_rn_ptr
);
13472 tcg_temp_free_ptr(tcg_rm_ptr
);
13475 /* Crypto two-reg SHA
13476 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13477 * +-----------------+------+-----------+--------+-----+------+------+
13478 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13479 * +-----------------+------+-----------+--------+-----+------+------+
13481 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13483 int size
= extract32(insn
, 22, 2);
13484 int opcode
= extract32(insn
, 12, 5);
13485 int rn
= extract32(insn
, 5, 5);
13486 int rd
= extract32(insn
, 0, 5);
13487 CryptoTwoOpFn
*genfn
;
13489 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13492 unallocated_encoding(s
);
13497 case 0: /* SHA1H */
13498 feature
= dc_isar_feature(aa64_sha1
, s
);
13499 genfn
= gen_helper_crypto_sha1h
;
13501 case 1: /* SHA1SU1 */
13502 feature
= dc_isar_feature(aa64_sha1
, s
);
13503 genfn
= gen_helper_crypto_sha1su1
;
13505 case 2: /* SHA256SU0 */
13506 feature
= dc_isar_feature(aa64_sha256
, s
);
13507 genfn
= gen_helper_crypto_sha256su0
;
13510 unallocated_encoding(s
);
13515 unallocated_encoding(s
);
13519 if (!fp_access_check(s
)) {
13523 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13524 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13526 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13528 tcg_temp_free_ptr(tcg_rd_ptr
);
13529 tcg_temp_free_ptr(tcg_rn_ptr
);
13532 /* Crypto three-reg SHA512
13533 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13534 * +-----------------------+------+---+---+-----+--------+------+------+
13535 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13536 * +-----------------------+------+---+---+-----+--------+------+------+
13538 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13540 int opcode
= extract32(insn
, 10, 2);
13541 int o
= extract32(insn
, 14, 1);
13542 int rm
= extract32(insn
, 16, 5);
13543 int rn
= extract32(insn
, 5, 5);
13544 int rd
= extract32(insn
, 0, 5);
13546 CryptoThreeOpFn
*genfn
;
13550 case 0: /* SHA512H */
13551 feature
= dc_isar_feature(aa64_sha512
, s
);
13552 genfn
= gen_helper_crypto_sha512h
;
13554 case 1: /* SHA512H2 */
13555 feature
= dc_isar_feature(aa64_sha512
, s
);
13556 genfn
= gen_helper_crypto_sha512h2
;
13558 case 2: /* SHA512SU1 */
13559 feature
= dc_isar_feature(aa64_sha512
, s
);
13560 genfn
= gen_helper_crypto_sha512su1
;
13563 feature
= dc_isar_feature(aa64_sha3
, s
);
13569 case 0: /* SM3PARTW1 */
13570 feature
= dc_isar_feature(aa64_sm3
, s
);
13571 genfn
= gen_helper_crypto_sm3partw1
;
13573 case 1: /* SM3PARTW2 */
13574 feature
= dc_isar_feature(aa64_sm3
, s
);
13575 genfn
= gen_helper_crypto_sm3partw2
;
13577 case 2: /* SM4EKEY */
13578 feature
= dc_isar_feature(aa64_sm4
, s
);
13579 genfn
= gen_helper_crypto_sm4ekey
;
13582 unallocated_encoding(s
);
13588 unallocated_encoding(s
);
13592 if (!fp_access_check(s
)) {
13597 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13599 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13600 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13601 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13603 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13605 tcg_temp_free_ptr(tcg_rd_ptr
);
13606 tcg_temp_free_ptr(tcg_rn_ptr
);
13607 tcg_temp_free_ptr(tcg_rm_ptr
);
13609 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13612 tcg_op1
= tcg_temp_new_i64();
13613 tcg_op2
= tcg_temp_new_i64();
13614 tcg_res
[0] = tcg_temp_new_i64();
13615 tcg_res
[1] = tcg_temp_new_i64();
13617 for (pass
= 0; pass
< 2; pass
++) {
13618 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13619 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13621 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13622 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13624 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13625 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13627 tcg_temp_free_i64(tcg_op1
);
13628 tcg_temp_free_i64(tcg_op2
);
13629 tcg_temp_free_i64(tcg_res
[0]);
13630 tcg_temp_free_i64(tcg_res
[1]);
13634 /* Crypto two-reg SHA512
13635 * 31 12 11 10 9 5 4 0
13636 * +-----------------------------------------+--------+------+------+
13637 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13638 * +-----------------------------------------+--------+------+------+
13640 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13642 int opcode
= extract32(insn
, 10, 2);
13643 int rn
= extract32(insn
, 5, 5);
13644 int rd
= extract32(insn
, 0, 5);
13645 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13647 CryptoTwoOpFn
*genfn
;
13650 case 0: /* SHA512SU0 */
13651 feature
= dc_isar_feature(aa64_sha512
, s
);
13652 genfn
= gen_helper_crypto_sha512su0
;
13655 feature
= dc_isar_feature(aa64_sm4
, s
);
13656 genfn
= gen_helper_crypto_sm4e
;
13659 unallocated_encoding(s
);
13664 unallocated_encoding(s
);
13668 if (!fp_access_check(s
)) {
13672 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13673 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13675 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13677 tcg_temp_free_ptr(tcg_rd_ptr
);
13678 tcg_temp_free_ptr(tcg_rn_ptr
);
13681 /* Crypto four-register
13682 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13683 * +-------------------+-----+------+---+------+------+------+
13684 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13685 * +-------------------+-----+------+---+------+------+------+
13687 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13689 int op0
= extract32(insn
, 21, 2);
13690 int rm
= extract32(insn
, 16, 5);
13691 int ra
= extract32(insn
, 10, 5);
13692 int rn
= extract32(insn
, 5, 5);
13693 int rd
= extract32(insn
, 0, 5);
13699 feature
= dc_isar_feature(aa64_sha3
, s
);
13701 case 2: /* SM3SS1 */
13702 feature
= dc_isar_feature(aa64_sm3
, s
);
13705 unallocated_encoding(s
);
13710 unallocated_encoding(s
);
13714 if (!fp_access_check(s
)) {
13719 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13722 tcg_op1
= tcg_temp_new_i64();
13723 tcg_op2
= tcg_temp_new_i64();
13724 tcg_op3
= tcg_temp_new_i64();
13725 tcg_res
[0] = tcg_temp_new_i64();
13726 tcg_res
[1] = tcg_temp_new_i64();
13728 for (pass
= 0; pass
< 2; pass
++) {
13729 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13730 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13731 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13735 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13738 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13740 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13742 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13743 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13745 tcg_temp_free_i64(tcg_op1
);
13746 tcg_temp_free_i64(tcg_op2
);
13747 tcg_temp_free_i64(tcg_op3
);
13748 tcg_temp_free_i64(tcg_res
[0]);
13749 tcg_temp_free_i64(tcg_res
[1]);
13751 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13753 tcg_op1
= tcg_temp_new_i32();
13754 tcg_op2
= tcg_temp_new_i32();
13755 tcg_op3
= tcg_temp_new_i32();
13756 tcg_res
= tcg_temp_new_i32();
13757 tcg_zero
= tcg_const_i32(0);
13759 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13760 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13761 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13763 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13764 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13765 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13766 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13768 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13769 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13770 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13771 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13773 tcg_temp_free_i32(tcg_op1
);
13774 tcg_temp_free_i32(tcg_op2
);
13775 tcg_temp_free_i32(tcg_op3
);
13776 tcg_temp_free_i32(tcg_res
);
13777 tcg_temp_free_i32(tcg_zero
);
13782 * 31 21 20 16 15 10 9 5 4 0
13783 * +-----------------------+------+--------+------+------+
13784 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13785 * +-----------------------+------+--------+------+------+
13787 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13789 int rm
= extract32(insn
, 16, 5);
13790 int imm6
= extract32(insn
, 10, 6);
13791 int rn
= extract32(insn
, 5, 5);
13792 int rd
= extract32(insn
, 0, 5);
13793 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13796 if (!dc_isar_feature(aa64_sha3
, s
)) {
13797 unallocated_encoding(s
);
13801 if (!fp_access_check(s
)) {
13805 tcg_op1
= tcg_temp_new_i64();
13806 tcg_op2
= tcg_temp_new_i64();
13807 tcg_res
[0] = tcg_temp_new_i64();
13808 tcg_res
[1] = tcg_temp_new_i64();
13810 for (pass
= 0; pass
< 2; pass
++) {
13811 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13812 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13814 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13815 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13817 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13818 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13820 tcg_temp_free_i64(tcg_op1
);
13821 tcg_temp_free_i64(tcg_op2
);
13822 tcg_temp_free_i64(tcg_res
[0]);
13823 tcg_temp_free_i64(tcg_res
[1]);
13826 /* Crypto three-reg imm2
13827 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13828 * +-----------------------+------+-----+------+--------+------+------+
13829 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13830 * +-----------------------+------+-----+------+--------+------+------+
13832 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13834 int opcode
= extract32(insn
, 10, 2);
13835 int imm2
= extract32(insn
, 12, 2);
13836 int rm
= extract32(insn
, 16, 5);
13837 int rn
= extract32(insn
, 5, 5);
13838 int rd
= extract32(insn
, 0, 5);
13839 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13840 TCGv_i32 tcg_imm2
, tcg_opcode
;
13842 if (!dc_isar_feature(aa64_sm3
, s
)) {
13843 unallocated_encoding(s
);
13847 if (!fp_access_check(s
)) {
13851 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13852 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13853 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13854 tcg_imm2
= tcg_const_i32(imm2
);
13855 tcg_opcode
= tcg_const_i32(opcode
);
13857 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13860 tcg_temp_free_ptr(tcg_rd_ptr
);
13861 tcg_temp_free_ptr(tcg_rn_ptr
);
13862 tcg_temp_free_ptr(tcg_rm_ptr
);
13863 tcg_temp_free_i32(tcg_imm2
);
13864 tcg_temp_free_i32(tcg_opcode
);
13867 /* C3.6 Data processing - SIMD, inc Crypto
13869 * As the decode gets a little complex we are using a table based
13870 * approach for this part of the decode.
13872 static const AArch64DecodeTable data_proc_simd
[] = {
13873 /* pattern , mask , fn */
13874 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13875 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13876 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13877 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13878 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13879 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13880 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13881 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13882 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13883 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13884 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13885 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13886 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13887 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13888 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13889 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13890 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13891 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13892 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13893 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13894 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13895 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13896 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13897 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13898 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13899 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13900 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13901 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13902 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13903 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13904 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13905 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13906 { 0x00000000, 0x00000000, NULL
}
13909 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13911 /* Note that this is called with all non-FP cases from
13912 * table C3-6 so it must UNDEF for entries not specifically
13913 * allocated to instructions in that table.
13915 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13919 unallocated_encoding(s
);
13923 /* C3.6 Data processing - SIMD and floating point */
13924 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13926 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13927 disas_data_proc_fp(s
, insn
);
13929 /* SIMD, including crypto */
13930 disas_data_proc_simd(s
, insn
);
13936 * @env: The cpu environment
13937 * @s: The DisasContext
13939 * Return true if the page is guarded.
13941 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13943 #ifdef CONFIG_USER_ONLY
13944 return false; /* FIXME */
13946 uint64_t addr
= s
->base
.pc_first
;
13947 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13948 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13949 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13952 * We test this immediately after reading an insn, which means
13953 * that any normal page must be in the TLB. The only exception
13954 * would be for executing from flash or device memory, which
13955 * does not retain the TLB entry.
13957 * FIXME: Assume false for those, for now. We could use
13958 * arm_cpu_get_phys_page_attrs_debug to re-read the page
13959 * table entry even for that case.
13961 return (tlb_hit(entry
->addr_code
, addr
) &&
13962 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
13967 * btype_destination_ok:
13968 * @insn: The instruction at the branch destination
13969 * @bt: SCTLR_ELx.BT
13970 * @btype: PSTATE.BTYPE, and is non-zero
13972 * On a guarded page, there are a limited number of insns
13973 * that may be present at the branch target:
13974 * - branch target identifiers,
13975 * - paciasp, pacibsp,
13978 * Anything else causes a Branch Target Exception.
13980 * Return true if the branch is compatible, false to raise BTITRAP.
13982 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
13984 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
13986 switch (extract32(insn
, 5, 7)) {
13987 case 0b011001: /* PACIASP */
13988 case 0b011011: /* PACIBSP */
13990 * If SCTLR_ELx.BT, then PACI*SP are not compatible
13991 * with btype == 3. Otherwise all btype are ok.
13993 return !bt
|| btype
!= 3;
13994 case 0b100000: /* BTI */
13995 /* Not compatible with any btype. */
13997 case 0b100010: /* BTI c */
13998 /* Not compatible with btype == 3 */
14000 case 0b100100: /* BTI j */
14001 /* Not compatible with btype == 2 */
14003 case 0b100110: /* BTI jc */
14004 /* Compatible with any btype. */
14008 switch (insn
& 0xffe0001fu
) {
14009 case 0xd4200000u
: /* BRK */
14010 case 0xd4400000u
: /* HLT */
14011 /* Give priority to the breakpoint exception. */
14018 /* C3.1 A64 instruction index by encoding */
14019 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14023 s
->pc_curr
= s
->base
.pc_next
;
14024 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14026 s
->base
.pc_next
+= 4;
14028 s
->fp_access_checked
= false;
14030 if (dc_isar_feature(aa64_bti
, s
)) {
14031 if (s
->base
.num_insns
== 1) {
14033 * At the first insn of the TB, compute s->guarded_page.
14034 * We delayed computing this until successfully reading
14035 * the first insn of the TB, above. This (mostly) ensures
14036 * that the softmmu tlb entry has been populated, and the
14037 * page table GP bit is available.
14039 * Note that we need to compute this even if btype == 0,
14040 * because this value is used for BR instructions later
14041 * where ENV is not available.
14043 s
->guarded_page
= is_guarded_page(env
, s
);
14045 /* First insn can have btype set to non-zero. */
14046 tcg_debug_assert(s
->btype
>= 0);
14049 * Note that the Branch Target Exception has fairly high
14050 * priority -- below debugging exceptions but above most
14051 * everything else. This allows us to handle this now
14052 * instead of waiting until the insn is otherwise decoded.
14056 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14057 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14058 syn_btitrap(s
->btype
),
14059 default_exception_el(s
));
14063 /* Not the first insn: btype must be 0. */
14064 tcg_debug_assert(s
->btype
== 0);
14068 switch (extract32(insn
, 25, 4)) {
14069 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14070 unallocated_encoding(s
);
14073 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14074 unallocated_encoding(s
);
14077 case 0x8: case 0x9: /* Data processing - immediate */
14078 disas_data_proc_imm(s
, insn
);
14080 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14081 disas_b_exc_sys(s
, insn
);
14086 case 0xe: /* Loads and stores */
14087 disas_ldst(s
, insn
);
14090 case 0xd: /* Data processing - register */
14091 disas_data_proc_reg(s
, insn
);
14094 case 0xf: /* Data processing - SIMD and floating point */
14095 disas_data_proc_simd_fp(s
, insn
);
14098 assert(FALSE
); /* all 15 cases should be handled above */
14102 /* if we allocated any temporaries, free them here */
14106 * After execution of most insns, btype is reset to 0.
14107 * Note that we set btype == -1 when the insn sets btype.
14109 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14114 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14117 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14118 CPUARMState
*env
= cpu
->env_ptr
;
14119 ARMCPU
*arm_cpu
= env_archcpu(env
);
14120 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14121 int bound
, core_mmu_idx
;
14123 dc
->isar
= &arm_cpu
->isar
;
14127 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14128 * there is no secure EL1, so we route exceptions to EL3.
14130 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14131 !arm_el_is_aa64(env
, 3);
14134 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14135 dc
->condexec_mask
= 0;
14136 dc
->condexec_cond
= 0;
14137 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14138 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14139 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14140 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14141 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14142 #if !defined(CONFIG_USER_ONLY)
14143 dc
->user
= (dc
->current_el
== 0);
14145 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14146 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14147 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14148 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14149 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14150 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14152 dc
->vec_stride
= 0;
14153 dc
->cp_regs
= arm_cpu
->cp_regs
;
14154 dc
->features
= env
->features
;
14156 /* Single step state. The code-generation logic here is:
14158 * generate code with no special handling for single-stepping (except
14159 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14160 * this happens anyway because those changes are all system register or
14162 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14163 * emit code for one insn
14164 * emit code to clear PSTATE.SS
14165 * emit code to generate software step exception for completed step
14166 * end TB (as usual for having generated an exception)
14167 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14168 * emit code to generate a software step exception
14171 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14172 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14173 dc
->is_ldex
= false;
14174 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14176 /* Bound the number of insns to execute to those left on the page. */
14177 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14179 /* If architectural single step active, limit to 1. */
14180 if (dc
->ss_active
) {
14183 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14185 init_tmp_a64_array(dc
);
14188 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14192 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14194 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14196 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14197 dc
->insn_start
= tcg_last_op();
14200 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14201 const CPUBreakpoint
*bp
)
14203 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14205 if (bp
->flags
& BP_CPU
) {
14206 gen_a64_set_pc_im(dc
->base
.pc_next
);
14207 gen_helper_check_breakpoints(cpu_env
);
14208 /* End the TB early; it likely won't be executed */
14209 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14211 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14212 /* The address covered by the breakpoint must be
14213 included in [tb->pc, tb->pc + tb->size) in order
14214 to for it to be properly cleared -- thus we
14215 increment the PC here so that the logic setting
14216 tb->size below does the right thing. */
14217 dc
->base
.pc_next
+= 4;
14218 dc
->base
.is_jmp
= DISAS_NORETURN
;
14224 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14226 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14227 CPUARMState
*env
= cpu
->env_ptr
;
14229 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14230 /* Singlestep state is Active-pending.
14231 * If we're in this state at the start of a TB then either
14232 * a) we just took an exception to an EL which is being debugged
14233 * and this is the first insn in the exception handler
14234 * b) debug exceptions were masked and we just unmasked them
14235 * without changing EL (eg by clearing PSTATE.D)
14236 * In either case we're going to take a swstep exception in the
14237 * "did not step an insn" case, and so the syndrome ISV and EX
14238 * bits should be zero.
14240 assert(dc
->base
.num_insns
== 1);
14241 gen_swstep_exception(dc
, 0, 0);
14242 dc
->base
.is_jmp
= DISAS_NORETURN
;
14244 disas_a64_insn(env
, dc
);
14247 translator_loop_temp_check(&dc
->base
);
14250 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14252 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14254 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14255 /* Note that this means single stepping WFI doesn't halt the CPU.
14256 * For conditional branch insns this is harmless unreachable code as
14257 * gen_goto_tb() has already handled emitting the debug exception
14258 * (and thus a tb-jump is not possible when singlestepping).
14260 switch (dc
->base
.is_jmp
) {
14262 gen_a64_set_pc_im(dc
->base
.pc_next
);
14266 if (dc
->base
.singlestep_enabled
) {
14267 gen_exception_internal(EXCP_DEBUG
);
14269 gen_step_complete_exception(dc
);
14272 case DISAS_NORETURN
:
14276 switch (dc
->base
.is_jmp
) {
14278 case DISAS_TOO_MANY
:
14279 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14283 gen_a64_set_pc_im(dc
->base
.pc_next
);
14286 tcg_gen_exit_tb(NULL
, 0);
14289 tcg_gen_lookup_and_goto_ptr();
14291 case DISAS_NORETURN
:
14295 gen_a64_set_pc_im(dc
->base
.pc_next
);
14296 gen_helper_wfe(cpu_env
);
14299 gen_a64_set_pc_im(dc
->base
.pc_next
);
14300 gen_helper_yield(cpu_env
);
14304 /* This is a special case because we don't want to just halt the CPU
14305 * if trying to debug across a WFI.
14307 TCGv_i32 tmp
= tcg_const_i32(4);
14309 gen_a64_set_pc_im(dc
->base
.pc_next
);
14310 gen_helper_wfi(cpu_env
, tmp
);
14311 tcg_temp_free_i32(tmp
);
14312 /* The helper doesn't necessarily throw an exception, but we
14313 * must go back to the main loop to check for interrupts anyway.
14315 tcg_gen_exit_tb(NULL
, 0);
14322 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14325 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14327 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14328 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14331 const TranslatorOps aarch64_translator_ops
= {
14332 .init_disas_context
= aarch64_tr_init_disas_context
,
14333 .tb_start
= aarch64_tr_tb_start
,
14334 .insn_start
= aarch64_tr_insn_start
,
14335 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14336 .translate_insn
= aarch64_tr_translate_insn
,
14337 .tb_stop
= aarch64_tr_tb_stop
,
14338 .disas_log
= aarch64_tr_disas_log
,