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1 /*
2 * AArch64 translation
3 *
4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "tcg-op.h"
24 #include "tcg-op-gvec.h"
25 #include "qemu/log.h"
26 #include "arm_ldst.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
30
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
33
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
36 #include "exec/log.h"
37
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40
41 static TCGv_i64 cpu_X[32];
42 static TCGv_i64 cpu_pc;
43
44 /* Load/store exclusive handling */
45 static TCGv_i64 cpu_exclusive_high;
46
47 static const char *regnames[] = {
48 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
49 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
50 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
51 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
52 };
53
54 enum a64_shift_type {
55 A64_SHIFT_TYPE_LSL = 0,
56 A64_SHIFT_TYPE_LSR = 1,
57 A64_SHIFT_TYPE_ASR = 2,
58 A64_SHIFT_TYPE_ROR = 3
59 };
60
61 /* Table based decoder typedefs - used when the relevant bits for decode
62 * are too awkwardly scattered across the instruction (eg SIMD).
63 */
64 typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn);
65
66 typedef struct AArch64DecodeTable {
67 uint32_t pattern;
68 uint32_t mask;
69 AArch64DecodeFn *disas_fn;
70 } AArch64DecodeTable;
71
72 /* Function prototype for gen_ functions for calling Neon helpers */
73 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
74 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
75 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
76 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
77 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
78 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
79 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
80 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
81 typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
82 typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
83 typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
84 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
85 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
86 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
87 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, TCGMemOp);
88
89 /* initialize TCG globals. */
90 void a64_translate_init(void)
91 {
92 int i;
93
94 cpu_pc = tcg_global_mem_new_i64(cpu_env,
95 offsetof(CPUARMState, pc),
96 "pc");
97 for (i = 0; i < 32; i++) {
98 cpu_X[i] = tcg_global_mem_new_i64(cpu_env,
99 offsetof(CPUARMState, xregs[i]),
100 regnames[i]);
101 }
102
103 cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env,
104 offsetof(CPUARMState, exclusive_high), "exclusive_high");
105 }
106
107 static inline int get_a64_user_mem_index(DisasContext *s)
108 {
109 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
110 * if EL1, access as if EL0; otherwise access at current EL
111 */
112 ARMMMUIdx useridx;
113
114 switch (s->mmu_idx) {
115 case ARMMMUIdx_S12NSE1:
116 useridx = ARMMMUIdx_S12NSE0;
117 break;
118 case ARMMMUIdx_S1SE1:
119 useridx = ARMMMUIdx_S1SE0;
120 break;
121 case ARMMMUIdx_S2NS:
122 g_assert_not_reached();
123 default:
124 useridx = s->mmu_idx;
125 break;
126 }
127 return arm_to_core_mmu_idx(useridx);
128 }
129
130 void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
131 fprintf_function cpu_fprintf, int flags)
132 {
133 ARMCPU *cpu = ARM_CPU(cs);
134 CPUARMState *env = &cpu->env;
135 uint32_t psr = pstate_read(env);
136 int i;
137 int el = arm_current_el(env);
138 const char *ns_status;
139
140 cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n",
141 env->pc, env->xregs[31]);
142 for (i = 0; i < 31; i++) {
143 cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]);
144 if ((i % 4) == 3) {
145 cpu_fprintf(f, "\n");
146 } else {
147 cpu_fprintf(f, " ");
148 }
149 }
150
151 if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) {
152 ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S ";
153 } else {
154 ns_status = "";
155 }
156
157 cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n",
158 psr,
159 psr & PSTATE_N ? 'N' : '-',
160 psr & PSTATE_Z ? 'Z' : '-',
161 psr & PSTATE_C ? 'C' : '-',
162 psr & PSTATE_V ? 'V' : '-',
163 ns_status,
164 el,
165 psr & PSTATE_SP ? 'h' : 't');
166
167 if (flags & CPU_DUMP_FPU) {
168 int numvfpregs = 32;
169 for (i = 0; i < numvfpregs; i++) {
170 uint64_t *q = aa64_vfp_qreg(env, i);
171 uint64_t vlo = q[0];
172 uint64_t vhi = q[1];
173 cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c",
174 i, vhi, vlo, (i & 1 ? '\n' : ' '));
175 }
176 cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n",
177 vfp_get_fpcr(env), vfp_get_fpsr(env));
178 }
179 }
180
181 void gen_a64_set_pc_im(uint64_t val)
182 {
183 tcg_gen_movi_i64(cpu_pc, val);
184 }
185
186 /* Load the PC from a generic TCG variable.
187 *
188 * If address tagging is enabled via the TCR TBI bits, then loading
189 * an address into the PC will clear out any tag in the it:
190 * + for EL2 and EL3 there is only one TBI bit, and if it is set
191 * then the address is zero-extended, clearing bits [63:56]
192 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
193 * and TBI1 controls addressses with bit 55 == 1.
194 * If the appropriate TBI bit is set for the address then
195 * the address is sign-extended from bit 55 into bits [63:56]
196 *
197 * We can avoid doing this for relative-branches, because the
198 * PC + offset can never overflow into the tag bits (assuming
199 * that virtual addresses are less than 56 bits wide, as they
200 * are currently), but we must handle it for branch-to-register.
201 */
202 static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
203 {
204
205 if (s->current_el <= 1) {
206 /* Test if NEITHER or BOTH TBI values are set. If so, no need to
207 * examine bit 55 of address, can just generate code.
208 * If mixed, then test via generated code
209 */
210 if (s->tbi0 && s->tbi1) {
211 TCGv_i64 tmp_reg = tcg_temp_new_i64();
212 /* Both bits set, sign extension from bit 55 into [63:56] will
213 * cover both cases
214 */
215 tcg_gen_shli_i64(tmp_reg, src, 8);
216 tcg_gen_sari_i64(cpu_pc, tmp_reg, 8);
217 tcg_temp_free_i64(tmp_reg);
218 } else if (!s->tbi0 && !s->tbi1) {
219 /* Neither bit set, just load it as-is */
220 tcg_gen_mov_i64(cpu_pc, src);
221 } else {
222 TCGv_i64 tcg_tmpval = tcg_temp_new_i64();
223 TCGv_i64 tcg_bit55 = tcg_temp_new_i64();
224 TCGv_i64 tcg_zero = tcg_const_i64(0);
225
226 tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55));
227
228 if (s->tbi0) {
229 /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
230 tcg_gen_andi_i64(tcg_tmpval, src,
231 0x00FFFFFFFFFFFFFFull);
232 tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero,
233 tcg_tmpval, src);
234 } else {
235 /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
236 tcg_gen_ori_i64(tcg_tmpval, src,
237 0xFF00000000000000ull);
238 tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero,
239 tcg_tmpval, src);
240 }
241 tcg_temp_free_i64(tcg_zero);
242 tcg_temp_free_i64(tcg_bit55);
243 tcg_temp_free_i64(tcg_tmpval);
244 }
245 } else { /* EL > 1 */
246 if (s->tbi0) {
247 /* Force tag byte to all zero */
248 tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
249 } else {
250 /* Load unmodified address */
251 tcg_gen_mov_i64(cpu_pc, src);
252 }
253 }
254 }
255
256 typedef struct DisasCompare64 {
257 TCGCond cond;
258 TCGv_i64 value;
259 } DisasCompare64;
260
261 static void a64_test_cc(DisasCompare64 *c64, int cc)
262 {
263 DisasCompare c32;
264
265 arm_test_cc(&c32, cc);
266
267 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
268 * properly. The NE/EQ comparisons are also fine with this choice. */
269 c64->cond = c32.cond;
270 c64->value = tcg_temp_new_i64();
271 tcg_gen_ext_i32_i64(c64->value, c32.value);
272
273 arm_free_cc(&c32);
274 }
275
276 static void a64_free_cc(DisasCompare64 *c64)
277 {
278 tcg_temp_free_i64(c64->value);
279 }
280
281 static void gen_exception_internal(int excp)
282 {
283 TCGv_i32 tcg_excp = tcg_const_i32(excp);
284
285 assert(excp_is_internal(excp));
286 gen_helper_exception_internal(cpu_env, tcg_excp);
287 tcg_temp_free_i32(tcg_excp);
288 }
289
290 static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
291 {
292 TCGv_i32 tcg_excp = tcg_const_i32(excp);
293 TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
294 TCGv_i32 tcg_el = tcg_const_i32(target_el);
295
296 gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
297 tcg_syn, tcg_el);
298 tcg_temp_free_i32(tcg_el);
299 tcg_temp_free_i32(tcg_syn);
300 tcg_temp_free_i32(tcg_excp);
301 }
302
303 static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
304 {
305 gen_a64_set_pc_im(s->pc - offset);
306 gen_exception_internal(excp);
307 s->base.is_jmp = DISAS_NORETURN;
308 }
309
310 static void gen_exception_insn(DisasContext *s, int offset, int excp,
311 uint32_t syndrome, uint32_t target_el)
312 {
313 gen_a64_set_pc_im(s->pc - offset);
314 gen_exception(excp, syndrome, target_el);
315 s->base.is_jmp = DISAS_NORETURN;
316 }
317
318 static void gen_exception_bkpt_insn(DisasContext *s, int offset,
319 uint32_t syndrome)
320 {
321 TCGv_i32 tcg_syn;
322
323 gen_a64_set_pc_im(s->pc - offset);
324 tcg_syn = tcg_const_i32(syndrome);
325 gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
326 tcg_temp_free_i32(tcg_syn);
327 s->base.is_jmp = DISAS_NORETURN;
328 }
329
330 static void gen_ss_advance(DisasContext *s)
331 {
332 /* If the singlestep state is Active-not-pending, advance to
333 * Active-pending.
334 */
335 if (s->ss_active) {
336 s->pstate_ss = 0;
337 gen_helper_clear_pstate_ss(cpu_env);
338 }
339 }
340
341 static void gen_step_complete_exception(DisasContext *s)
342 {
343 /* We just completed step of an insn. Move from Active-not-pending
344 * to Active-pending, and then also take the swstep exception.
345 * This corresponds to making the (IMPDEF) choice to prioritize
346 * swstep exceptions over asynchronous exceptions taken to an exception
347 * level where debug is disabled. This choice has the advantage that
348 * we do not need to maintain internal state corresponding to the
349 * ISV/EX syndrome bits between completion of the step and generation
350 * of the exception, and our syndrome information is always correct.
351 */
352 gen_ss_advance(s);
353 gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
354 default_exception_el(s));
355 s->base.is_jmp = DISAS_NORETURN;
356 }
357
358 static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest)
359 {
360 /* No direct tb linking with singlestep (either QEMU's or the ARM
361 * debug architecture kind) or deterministic io
362 */
363 if (s->base.singlestep_enabled || s->ss_active ||
364 (tb_cflags(s->base.tb) & CF_LAST_IO)) {
365 return false;
366 }
367
368 #ifndef CONFIG_USER_ONLY
369 /* Only link tbs from inside the same guest page */
370 if ((s->base.tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) {
371 return false;
372 }
373 #endif
374
375 return true;
376 }
377
378 static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
379 {
380 TranslationBlock *tb;
381
382 tb = s->base.tb;
383 if (use_goto_tb(s, n, dest)) {
384 tcg_gen_goto_tb(n);
385 gen_a64_set_pc_im(dest);
386 tcg_gen_exit_tb(tb, n);
387 s->base.is_jmp = DISAS_NORETURN;
388 } else {
389 gen_a64_set_pc_im(dest);
390 if (s->ss_active) {
391 gen_step_complete_exception(s);
392 } else if (s->base.singlestep_enabled) {
393 gen_exception_internal(EXCP_DEBUG);
394 } else {
395 tcg_gen_lookup_and_goto_ptr();
396 s->base.is_jmp = DISAS_NORETURN;
397 }
398 }
399 }
400
401 void unallocated_encoding(DisasContext *s)
402 {
403 /* Unallocated and reserved encodings are uncategorized */
404 gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
405 default_exception_el(s));
406 }
407
408 static void init_tmp_a64_array(DisasContext *s)
409 {
410 #ifdef CONFIG_DEBUG_TCG
411 memset(s->tmp_a64, 0, sizeof(s->tmp_a64));
412 #endif
413 s->tmp_a64_count = 0;
414 }
415
416 static void free_tmp_a64(DisasContext *s)
417 {
418 int i;
419 for (i = 0; i < s->tmp_a64_count; i++) {
420 tcg_temp_free_i64(s->tmp_a64[i]);
421 }
422 init_tmp_a64_array(s);
423 }
424
425 TCGv_i64 new_tmp_a64(DisasContext *s)
426 {
427 assert(s->tmp_a64_count < TMP_A64_MAX);
428 return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
429 }
430
431 TCGv_i64 new_tmp_a64_zero(DisasContext *s)
432 {
433 TCGv_i64 t = new_tmp_a64(s);
434 tcg_gen_movi_i64(t, 0);
435 return t;
436 }
437
438 /*
439 * Register access functions
440 *
441 * These functions are used for directly accessing a register in where
442 * changes to the final register value are likely to be made. If you
443 * need to use a register for temporary calculation (e.g. index type
444 * operations) use the read_* form.
445 *
446 * B1.2.1 Register mappings
447 *
448 * In instruction register encoding 31 can refer to ZR (zero register) or
449 * the SP (stack pointer) depending on context. In QEMU's case we map SP
450 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
451 * This is the point of the _sp forms.
452 */
453 TCGv_i64 cpu_reg(DisasContext *s, int reg)
454 {
455 if (reg == 31) {
456 return new_tmp_a64_zero(s);
457 } else {
458 return cpu_X[reg];
459 }
460 }
461
462 /* register access for when 31 == SP */
463 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg)
464 {
465 return cpu_X[reg];
466 }
467
468 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
469 * representing the register contents. This TCGv is an auto-freed
470 * temporary so it need not be explicitly freed, and may be modified.
471 */
472 TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf)
473 {
474 TCGv_i64 v = new_tmp_a64(s);
475 if (reg != 31) {
476 if (sf) {
477 tcg_gen_mov_i64(v, cpu_X[reg]);
478 } else {
479 tcg_gen_ext32u_i64(v, cpu_X[reg]);
480 }
481 } else {
482 tcg_gen_movi_i64(v, 0);
483 }
484 return v;
485 }
486
487 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf)
488 {
489 TCGv_i64 v = new_tmp_a64(s);
490 if (sf) {
491 tcg_gen_mov_i64(v, cpu_X[reg]);
492 } else {
493 tcg_gen_ext32u_i64(v, cpu_X[reg]);
494 }
495 return v;
496 }
497
498 /* Return the offset into CPUARMState of a slice (from
499 * the least significant end) of FP register Qn (ie
500 * Dn, Sn, Hn or Bn).
501 * (Note that this is not the same mapping as for A32; see cpu.h)
502 */
503 static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size)
504 {
505 return vec_reg_offset(s, regno, 0, size);
506 }
507
508 /* Offset of the high half of the 128 bit vector Qn */
509 static inline int fp_reg_hi_offset(DisasContext *s, int regno)
510 {
511 return vec_reg_offset(s, regno, 1, MO_64);
512 }
513
514 /* Convenience accessors for reading and writing single and double
515 * FP registers. Writing clears the upper parts of the associated
516 * 128 bit vector register, as required by the architecture.
517 * Note that unlike the GP register accessors, the values returned
518 * by the read functions must be manually freed.
519 */
520 static TCGv_i64 read_fp_dreg(DisasContext *s, int reg)
521 {
522 TCGv_i64 v = tcg_temp_new_i64();
523
524 tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64));
525 return v;
526 }
527
528 static TCGv_i32 read_fp_sreg(DisasContext *s, int reg)
529 {
530 TCGv_i32 v = tcg_temp_new_i32();
531
532 tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32));
533 return v;
534 }
535
536 static TCGv_i32 read_fp_hreg(DisasContext *s, int reg)
537 {
538 TCGv_i32 v = tcg_temp_new_i32();
539
540 tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16));
541 return v;
542 }
543
544 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
545 * If SVE is not enabled, then there are only 128 bits in the vector.
546 */
547 static void clear_vec_high(DisasContext *s, bool is_q, int rd)
548 {
549 unsigned ofs = fp_reg_offset(s, rd, MO_64);
550 unsigned vsz = vec_full_reg_size(s);
551
552 if (!is_q) {
553 TCGv_i64 tcg_zero = tcg_const_i64(0);
554 tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8);
555 tcg_temp_free_i64(tcg_zero);
556 }
557 if (vsz > 16) {
558 tcg_gen_gvec_dup8i(ofs + 16, vsz - 16, vsz - 16, 0);
559 }
560 }
561
562 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
563 {
564 unsigned ofs = fp_reg_offset(s, reg, MO_64);
565
566 tcg_gen_st_i64(v, cpu_env, ofs);
567 clear_vec_high(s, false, reg);
568 }
569
570 static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
571 {
572 TCGv_i64 tmp = tcg_temp_new_i64();
573
574 tcg_gen_extu_i32_i64(tmp, v);
575 write_fp_dreg(s, reg, tmp);
576 tcg_temp_free_i64(tmp);
577 }
578
579 TCGv_ptr get_fpstatus_ptr(bool is_f16)
580 {
581 TCGv_ptr statusptr = tcg_temp_new_ptr();
582 int offset;
583
584 /* In A64 all instructions (both FP and Neon) use the FPCR; there
585 * is no equivalent of the A32 Neon "standard FPSCR value".
586 * However half-precision operations operate under a different
587 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
588 */
589 if (is_f16) {
590 offset = offsetof(CPUARMState, vfp.fp_status_f16);
591 } else {
592 offset = offsetof(CPUARMState, vfp.fp_status);
593 }
594 tcg_gen_addi_ptr(statusptr, cpu_env, offset);
595 return statusptr;
596 }
597
598 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
599 static void gen_gvec_fn2(DisasContext *s, bool is_q, int rd, int rn,
600 GVecGen2Fn *gvec_fn, int vece)
601 {
602 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
603 is_q ? 16 : 8, vec_full_reg_size(s));
604 }
605
606 /* Expand a 2-operand + immediate AdvSIMD vector operation using
607 * an expander function.
608 */
609 static void gen_gvec_fn2i(DisasContext *s, bool is_q, int rd, int rn,
610 int64_t imm, GVecGen2iFn *gvec_fn, int vece)
611 {
612 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
613 imm, is_q ? 16 : 8, vec_full_reg_size(s));
614 }
615
616 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
617 static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm,
618 GVecGen3Fn *gvec_fn, int vece)
619 {
620 gvec_fn(vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
621 vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s));
622 }
623
624 /* Expand a 2-operand + immediate AdvSIMD vector operation using
625 * an op descriptor.
626 */
627 static void gen_gvec_op2i(DisasContext *s, bool is_q, int rd,
628 int rn, int64_t imm, const GVecGen2i *gvec_op)
629 {
630 tcg_gen_gvec_2i(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
631 is_q ? 16 : 8, vec_full_reg_size(s), imm, gvec_op);
632 }
633
634 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
635 static void gen_gvec_op3(DisasContext *s, bool is_q, int rd,
636 int rn, int rm, const GVecGen3 *gvec_op)
637 {
638 tcg_gen_gvec_3(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
639 vec_full_reg_offset(s, rm), is_q ? 16 : 8,
640 vec_full_reg_size(s), gvec_op);
641 }
642
643 /* Expand a 3-operand operation using an out-of-line helper. */
644 static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
645 int rn, int rm, int data, gen_helper_gvec_3 *fn)
646 {
647 tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd),
648 vec_full_reg_offset(s, rn),
649 vec_full_reg_offset(s, rm),
650 is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
651 }
652
653 /* Expand a 3-operand + env pointer operation using
654 * an out-of-line helper.
655 */
656 static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd,
657 int rn, int rm, gen_helper_gvec_3_ptr *fn)
658 {
659 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
660 vec_full_reg_offset(s, rn),
661 vec_full_reg_offset(s, rm), cpu_env,
662 is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
663 }
664
665 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
666 * an out-of-line helper.
667 */
668 static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
669 int rm, bool is_fp16, int data,
670 gen_helper_gvec_3_ptr *fn)
671 {
672 TCGv_ptr fpst = get_fpstatus_ptr(is_fp16);
673 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
674 vec_full_reg_offset(s, rn),
675 vec_full_reg_offset(s, rm), fpst,
676 is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
677 tcg_temp_free_ptr(fpst);
678 }
679
680 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
681 * than the 32 bit equivalent.
682 */
683 static inline void gen_set_NZ64(TCGv_i64 result)
684 {
685 tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result);
686 tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF);
687 }
688
689 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
690 static inline void gen_logic_CC(int sf, TCGv_i64 result)
691 {
692 if (sf) {
693 gen_set_NZ64(result);
694 } else {
695 tcg_gen_extrl_i64_i32(cpu_ZF, result);
696 tcg_gen_mov_i32(cpu_NF, cpu_ZF);
697 }
698 tcg_gen_movi_i32(cpu_CF, 0);
699 tcg_gen_movi_i32(cpu_VF, 0);
700 }
701
702 /* dest = T0 + T1; compute C, N, V and Z flags */
703 static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
704 {
705 if (sf) {
706 TCGv_i64 result, flag, tmp;
707 result = tcg_temp_new_i64();
708 flag = tcg_temp_new_i64();
709 tmp = tcg_temp_new_i64();
710
711 tcg_gen_movi_i64(tmp, 0);
712 tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp);
713
714 tcg_gen_extrl_i64_i32(cpu_CF, flag);
715
716 gen_set_NZ64(result);
717
718 tcg_gen_xor_i64(flag, result, t0);
719 tcg_gen_xor_i64(tmp, t0, t1);
720 tcg_gen_andc_i64(flag, flag, tmp);
721 tcg_temp_free_i64(tmp);
722 tcg_gen_extrh_i64_i32(cpu_VF, flag);
723
724 tcg_gen_mov_i64(dest, result);
725 tcg_temp_free_i64(result);
726 tcg_temp_free_i64(flag);
727 } else {
728 /* 32 bit arithmetic */
729 TCGv_i32 t0_32 = tcg_temp_new_i32();
730 TCGv_i32 t1_32 = tcg_temp_new_i32();
731 TCGv_i32 tmp = tcg_temp_new_i32();
732
733 tcg_gen_movi_i32(tmp, 0);
734 tcg_gen_extrl_i64_i32(t0_32, t0);
735 tcg_gen_extrl_i64_i32(t1_32, t1);
736 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp);
737 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
738 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
739 tcg_gen_xor_i32(tmp, t0_32, t1_32);
740 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
741 tcg_gen_extu_i32_i64(dest, cpu_NF);
742
743 tcg_temp_free_i32(tmp);
744 tcg_temp_free_i32(t0_32);
745 tcg_temp_free_i32(t1_32);
746 }
747 }
748
749 /* dest = T0 - T1; compute C, N, V and Z flags */
750 static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
751 {
752 if (sf) {
753 /* 64 bit arithmetic */
754 TCGv_i64 result, flag, tmp;
755
756 result = tcg_temp_new_i64();
757 flag = tcg_temp_new_i64();
758 tcg_gen_sub_i64(result, t0, t1);
759
760 gen_set_NZ64(result);
761
762 tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1);
763 tcg_gen_extrl_i64_i32(cpu_CF, flag);
764
765 tcg_gen_xor_i64(flag, result, t0);
766 tmp = tcg_temp_new_i64();
767 tcg_gen_xor_i64(tmp, t0, t1);
768 tcg_gen_and_i64(flag, flag, tmp);
769 tcg_temp_free_i64(tmp);
770 tcg_gen_extrh_i64_i32(cpu_VF, flag);
771 tcg_gen_mov_i64(dest, result);
772 tcg_temp_free_i64(flag);
773 tcg_temp_free_i64(result);
774 } else {
775 /* 32 bit arithmetic */
776 TCGv_i32 t0_32 = tcg_temp_new_i32();
777 TCGv_i32 t1_32 = tcg_temp_new_i32();
778 TCGv_i32 tmp;
779
780 tcg_gen_extrl_i64_i32(t0_32, t0);
781 tcg_gen_extrl_i64_i32(t1_32, t1);
782 tcg_gen_sub_i32(cpu_NF, t0_32, t1_32);
783 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
784 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32);
785 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
786 tmp = tcg_temp_new_i32();
787 tcg_gen_xor_i32(tmp, t0_32, t1_32);
788 tcg_temp_free_i32(t0_32);
789 tcg_temp_free_i32(t1_32);
790 tcg_gen_and_i32(cpu_VF, cpu_VF, tmp);
791 tcg_temp_free_i32(tmp);
792 tcg_gen_extu_i32_i64(dest, cpu_NF);
793 }
794 }
795
796 /* dest = T0 + T1 + CF; do not compute flags. */
797 static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
798 {
799 TCGv_i64 flag = tcg_temp_new_i64();
800 tcg_gen_extu_i32_i64(flag, cpu_CF);
801 tcg_gen_add_i64(dest, t0, t1);
802 tcg_gen_add_i64(dest, dest, flag);
803 tcg_temp_free_i64(flag);
804
805 if (!sf) {
806 tcg_gen_ext32u_i64(dest, dest);
807 }
808 }
809
810 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
811 static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
812 {
813 if (sf) {
814 TCGv_i64 result, cf_64, vf_64, tmp;
815 result = tcg_temp_new_i64();
816 cf_64 = tcg_temp_new_i64();
817 vf_64 = tcg_temp_new_i64();
818 tmp = tcg_const_i64(0);
819
820 tcg_gen_extu_i32_i64(cf_64, cpu_CF);
821 tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
822 tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
823 tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
824 gen_set_NZ64(result);
825
826 tcg_gen_xor_i64(vf_64, result, t0);
827 tcg_gen_xor_i64(tmp, t0, t1);
828 tcg_gen_andc_i64(vf_64, vf_64, tmp);
829 tcg_gen_extrh_i64_i32(cpu_VF, vf_64);
830
831 tcg_gen_mov_i64(dest, result);
832
833 tcg_temp_free_i64(tmp);
834 tcg_temp_free_i64(vf_64);
835 tcg_temp_free_i64(cf_64);
836 tcg_temp_free_i64(result);
837 } else {
838 TCGv_i32 t0_32, t1_32, tmp;
839 t0_32 = tcg_temp_new_i32();
840 t1_32 = tcg_temp_new_i32();
841 tmp = tcg_const_i32(0);
842
843 tcg_gen_extrl_i64_i32(t0_32, t0);
844 tcg_gen_extrl_i64_i32(t1_32, t1);
845 tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
846 tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
847
848 tcg_gen_mov_i32(cpu_ZF, cpu_NF);
849 tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
850 tcg_gen_xor_i32(tmp, t0_32, t1_32);
851 tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp);
852 tcg_gen_extu_i32_i64(dest, cpu_NF);
853
854 tcg_temp_free_i32(tmp);
855 tcg_temp_free_i32(t1_32);
856 tcg_temp_free_i32(t0_32);
857 }
858 }
859
860 /*
861 * Load/Store generators
862 */
863
864 /*
865 * Store from GPR register to memory.
866 */
867 static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
868 TCGv_i64 tcg_addr, int size, int memidx,
869 bool iss_valid,
870 unsigned int iss_srt,
871 bool iss_sf, bool iss_ar)
872 {
873 g_assert(size <= 3);
874 tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size);
875
876 if (iss_valid) {
877 uint32_t syn;
878
879 syn = syn_data_abort_with_iss(0,
880 size,
881 false,
882 iss_srt,
883 iss_sf,
884 iss_ar,
885 0, 0, 0, 0, 0, false);
886 disas_set_insn_syndrome(s, syn);
887 }
888 }
889
890 static void do_gpr_st(DisasContext *s, TCGv_i64 source,
891 TCGv_i64 tcg_addr, int size,
892 bool iss_valid,
893 unsigned int iss_srt,
894 bool iss_sf, bool iss_ar)
895 {
896 do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s),
897 iss_valid, iss_srt, iss_sf, iss_ar);
898 }
899
900 /*
901 * Load from memory to GPR register
902 */
903 static void do_gpr_ld_memidx(DisasContext *s,
904 TCGv_i64 dest, TCGv_i64 tcg_addr,
905 int size, bool is_signed,
906 bool extend, int memidx,
907 bool iss_valid, unsigned int iss_srt,
908 bool iss_sf, bool iss_ar)
909 {
910 TCGMemOp memop = s->be_data + size;
911
912 g_assert(size <= 3);
913
914 if (is_signed) {
915 memop += MO_SIGN;
916 }
917
918 tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
919
920 if (extend && is_signed) {
921 g_assert(size < 3);
922 tcg_gen_ext32u_i64(dest, dest);
923 }
924
925 if (iss_valid) {
926 uint32_t syn;
927
928 syn = syn_data_abort_with_iss(0,
929 size,
930 is_signed,
931 iss_srt,
932 iss_sf,
933 iss_ar,
934 0, 0, 0, 0, 0, false);
935 disas_set_insn_syndrome(s, syn);
936 }
937 }
938
939 static void do_gpr_ld(DisasContext *s,
940 TCGv_i64 dest, TCGv_i64 tcg_addr,
941 int size, bool is_signed, bool extend,
942 bool iss_valid, unsigned int iss_srt,
943 bool iss_sf, bool iss_ar)
944 {
945 do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
946 get_mem_index(s),
947 iss_valid, iss_srt, iss_sf, iss_ar);
948 }
949
950 /*
951 * Store from FP register to memory
952 */
953 static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
954 {
955 /* This writes the bottom N bits of a 128 bit wide vector to memory */
956 TCGv_i64 tmp = tcg_temp_new_i64();
957 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64));
958 if (size < 4) {
959 tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s),
960 s->be_data + size);
961 } else {
962 bool be = s->be_data == MO_BE;
963 TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
964
965 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
966 tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
967 s->be_data | MO_Q);
968 tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx));
969 tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
970 s->be_data | MO_Q);
971 tcg_temp_free_i64(tcg_hiaddr);
972 }
973
974 tcg_temp_free_i64(tmp);
975 }
976
977 /*
978 * Load from memory to FP register
979 */
980 static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
981 {
982 /* This always zero-extends and writes to a full 128 bit wide vector */
983 TCGv_i64 tmplo = tcg_temp_new_i64();
984 TCGv_i64 tmphi;
985
986 if (size < 4) {
987 TCGMemOp memop = s->be_data + size;
988 tmphi = tcg_const_i64(0);
989 tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
990 } else {
991 bool be = s->be_data == MO_BE;
992 TCGv_i64 tcg_hiaddr;
993
994 tmphi = tcg_temp_new_i64();
995 tcg_hiaddr = tcg_temp_new_i64();
996
997 tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
998 tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
999 s->be_data | MO_Q);
1000 tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
1001 s->be_data | MO_Q);
1002 tcg_temp_free_i64(tcg_hiaddr);
1003 }
1004
1005 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64));
1006 tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx));
1007
1008 tcg_temp_free_i64(tmplo);
1009 tcg_temp_free_i64(tmphi);
1010
1011 clear_vec_high(s, true, destidx);
1012 }
1013
1014 /*
1015 * Vector load/store helpers.
1016 *
1017 * The principal difference between this and a FP load is that we don't
1018 * zero extend as we are filling a partial chunk of the vector register.
1019 * These functions don't support 128 bit loads/stores, which would be
1020 * normal load/store operations.
1021 *
1022 * The _i32 versions are useful when operating on 32 bit quantities
1023 * (eg for floating point single or using Neon helper functions).
1024 */
1025
1026 /* Get value of an element within a vector register */
1027 static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx,
1028 int element, TCGMemOp memop)
1029 {
1030 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
1031 switch (memop) {
1032 case MO_8:
1033 tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off);
1034 break;
1035 case MO_16:
1036 tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off);
1037 break;
1038 case MO_32:
1039 tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off);
1040 break;
1041 case MO_8|MO_SIGN:
1042 tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off);
1043 break;
1044 case MO_16|MO_SIGN:
1045 tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off);
1046 break;
1047 case MO_32|MO_SIGN:
1048 tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off);
1049 break;
1050 case MO_64:
1051 case MO_64|MO_SIGN:
1052 tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off);
1053 break;
1054 default:
1055 g_assert_not_reached();
1056 }
1057 }
1058
1059 static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx,
1060 int element, TCGMemOp memop)
1061 {
1062 int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE);
1063 switch (memop) {
1064 case MO_8:
1065 tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off);
1066 break;
1067 case MO_16:
1068 tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off);
1069 break;
1070 case MO_8|MO_SIGN:
1071 tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off);
1072 break;
1073 case MO_16|MO_SIGN:
1074 tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off);
1075 break;
1076 case MO_32:
1077 case MO_32|MO_SIGN:
1078 tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off);
1079 break;
1080 default:
1081 g_assert_not_reached();
1082 }
1083 }
1084
1085 /* Set value of an element within a vector register */
1086 static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx,
1087 int element, TCGMemOp memop)
1088 {
1089 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
1090 switch (memop) {
1091 case MO_8:
1092 tcg_gen_st8_i64(tcg_src, cpu_env, vect_off);
1093 break;
1094 case MO_16:
1095 tcg_gen_st16_i64(tcg_src, cpu_env, vect_off);
1096 break;
1097 case MO_32:
1098 tcg_gen_st32_i64(tcg_src, cpu_env, vect_off);
1099 break;
1100 case MO_64:
1101 tcg_gen_st_i64(tcg_src, cpu_env, vect_off);
1102 break;
1103 default:
1104 g_assert_not_reached();
1105 }
1106 }
1107
1108 static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
1109 int destidx, int element, TCGMemOp memop)
1110 {
1111 int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE);
1112 switch (memop) {
1113 case MO_8:
1114 tcg_gen_st8_i32(tcg_src, cpu_env, vect_off);
1115 break;
1116 case MO_16:
1117 tcg_gen_st16_i32(tcg_src, cpu_env, vect_off);
1118 break;
1119 case MO_32:
1120 tcg_gen_st_i32(tcg_src, cpu_env, vect_off);
1121 break;
1122 default:
1123 g_assert_not_reached();
1124 }
1125 }
1126
1127 /* Store from vector register to memory */
1128 static void do_vec_st(DisasContext *s, int srcidx, int element,
1129 TCGv_i64 tcg_addr, int size)
1130 {
1131 TCGMemOp memop = s->be_data + size;
1132 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
1133
1134 read_vec_element(s, tcg_tmp, srcidx, element, size);
1135 tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
1136
1137 tcg_temp_free_i64(tcg_tmp);
1138 }
1139
1140 /* Load from memory to vector register */
1141 static void do_vec_ld(DisasContext *s, int destidx, int element,
1142 TCGv_i64 tcg_addr, int size)
1143 {
1144 TCGMemOp memop = s->be_data + size;
1145 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
1146
1147 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop);
1148 write_vec_element(s, tcg_tmp, destidx, element, size);
1149
1150 tcg_temp_free_i64(tcg_tmp);
1151 }
1152
1153 /* Check that FP/Neon access is enabled. If it is, return
1154 * true. If not, emit code to generate an appropriate exception,
1155 * and return false; the caller should not emit any code for
1156 * the instruction. Note that this check must happen after all
1157 * unallocated-encoding checks (otherwise the syndrome information
1158 * for the resulting exception will be incorrect).
1159 */
1160 static inline bool fp_access_check(DisasContext *s)
1161 {
1162 assert(!s->fp_access_checked);
1163 s->fp_access_checked = true;
1164
1165 if (!s->fp_excp_el) {
1166 return true;
1167 }
1168
1169 gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false),
1170 s->fp_excp_el);
1171 return false;
1172 }
1173
1174 /* Check that SVE access is enabled. If it is, return true.
1175 * If not, emit code to generate an appropriate exception and return false.
1176 */
1177 bool sve_access_check(DisasContext *s)
1178 {
1179 if (s->sve_excp_el) {
1180 gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),
1181 s->sve_excp_el);
1182 return false;
1183 }
1184 return fp_access_check(s);
1185 }
1186
1187 /*
1188 * This utility function is for doing register extension with an
1189 * optional shift. You will likely want to pass a temporary for the
1190 * destination register. See DecodeRegExtend() in the ARM ARM.
1191 */
1192 static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in,
1193 int option, unsigned int shift)
1194 {
1195 int extsize = extract32(option, 0, 2);
1196 bool is_signed = extract32(option, 2, 1);
1197
1198 if (is_signed) {
1199 switch (extsize) {
1200 case 0:
1201 tcg_gen_ext8s_i64(tcg_out, tcg_in);
1202 break;
1203 case 1:
1204 tcg_gen_ext16s_i64(tcg_out, tcg_in);
1205 break;
1206 case 2:
1207 tcg_gen_ext32s_i64(tcg_out, tcg_in);
1208 break;
1209 case 3:
1210 tcg_gen_mov_i64(tcg_out, tcg_in);
1211 break;
1212 }
1213 } else {
1214 switch (extsize) {
1215 case 0:
1216 tcg_gen_ext8u_i64(tcg_out, tcg_in);
1217 break;
1218 case 1:
1219 tcg_gen_ext16u_i64(tcg_out, tcg_in);
1220 break;
1221 case 2:
1222 tcg_gen_ext32u_i64(tcg_out, tcg_in);
1223 break;
1224 case 3:
1225 tcg_gen_mov_i64(tcg_out, tcg_in);
1226 break;
1227 }
1228 }
1229
1230 if (shift) {
1231 tcg_gen_shli_i64(tcg_out, tcg_out, shift);
1232 }
1233 }
1234
1235 static inline void gen_check_sp_alignment(DisasContext *s)
1236 {
1237 /* The AArch64 architecture mandates that (if enabled via PSTATE
1238 * or SCTLR bits) there is a check that SP is 16-aligned on every
1239 * SP-relative load or store (with an exception generated if it is not).
1240 * In line with general QEMU practice regarding misaligned accesses,
1241 * we omit these checks for the sake of guest program performance.
1242 * This function is provided as a hook so we can more easily add these
1243 * checks in future (possibly as a "favour catching guest program bugs
1244 * over speed" user selectable option).
1245 */
1246 }
1247
1248 /*
1249 * This provides a simple table based table lookup decoder. It is
1250 * intended to be used when the relevant bits for decode are too
1251 * awkwardly placed and switch/if based logic would be confusing and
1252 * deeply nested. Since it's a linear search through the table, tables
1253 * should be kept small.
1254 *
1255 * It returns the first handler where insn & mask == pattern, or
1256 * NULL if there is no match.
1257 * The table is terminated by an empty mask (i.e. 0)
1258 */
1259 static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
1260 uint32_t insn)
1261 {
1262 const AArch64DecodeTable *tptr = table;
1263
1264 while (tptr->mask) {
1265 if ((insn & tptr->mask) == tptr->pattern) {
1266 return tptr->disas_fn;
1267 }
1268 tptr++;
1269 }
1270 return NULL;
1271 }
1272
1273 /*
1274 * The instruction disassembly implemented here matches
1275 * the instruction encoding classifications in chapter C4
1276 * of the ARM Architecture Reference Manual (DDI0487B_a);
1277 * classification names and decode diagrams here should generally
1278 * match up with those in the manual.
1279 */
1280
1281 /* Unconditional branch (immediate)
1282 * 31 30 26 25 0
1283 * +----+-----------+-------------------------------------+
1284 * | op | 0 0 1 0 1 | imm26 |
1285 * +----+-----------+-------------------------------------+
1286 */
1287 static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
1288 {
1289 uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
1290
1291 if (insn & (1U << 31)) {
1292 /* BL Branch with link */
1293 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1294 }
1295
1296 /* B Branch / BL Branch with link */
1297 gen_goto_tb(s, 0, addr);
1298 }
1299
1300 /* Compare and branch (immediate)
1301 * 31 30 25 24 23 5 4 0
1302 * +----+-------------+----+---------------------+--------+
1303 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1304 * +----+-------------+----+---------------------+--------+
1305 */
1306 static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
1307 {
1308 unsigned int sf, op, rt;
1309 uint64_t addr;
1310 TCGLabel *label_match;
1311 TCGv_i64 tcg_cmp;
1312
1313 sf = extract32(insn, 31, 1);
1314 op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
1315 rt = extract32(insn, 0, 5);
1316 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1317
1318 tcg_cmp = read_cpu_reg(s, rt, sf);
1319 label_match = gen_new_label();
1320
1321 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1322 tcg_cmp, 0, label_match);
1323
1324 gen_goto_tb(s, 0, s->pc);
1325 gen_set_label(label_match);
1326 gen_goto_tb(s, 1, addr);
1327 }
1328
1329 /* Test and branch (immediate)
1330 * 31 30 25 24 23 19 18 5 4 0
1331 * +----+-------------+----+-------+-------------+------+
1332 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1333 * +----+-------------+----+-------+-------------+------+
1334 */
1335 static void disas_test_b_imm(DisasContext *s, uint32_t insn)
1336 {
1337 unsigned int bit_pos, op, rt;
1338 uint64_t addr;
1339 TCGLabel *label_match;
1340 TCGv_i64 tcg_cmp;
1341
1342 bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
1343 op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
1344 addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
1345 rt = extract32(insn, 0, 5);
1346
1347 tcg_cmp = tcg_temp_new_i64();
1348 tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos));
1349 label_match = gen_new_label();
1350 tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
1351 tcg_cmp, 0, label_match);
1352 tcg_temp_free_i64(tcg_cmp);
1353 gen_goto_tb(s, 0, s->pc);
1354 gen_set_label(label_match);
1355 gen_goto_tb(s, 1, addr);
1356 }
1357
1358 /* Conditional branch (immediate)
1359 * 31 25 24 23 5 4 3 0
1360 * +---------------+----+---------------------+----+------+
1361 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1362 * +---------------+----+---------------------+----+------+
1363 */
1364 static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
1365 {
1366 unsigned int cond;
1367 uint64_t addr;
1368
1369 if ((insn & (1 << 4)) || (insn & (1 << 24))) {
1370 unallocated_encoding(s);
1371 return;
1372 }
1373 addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
1374 cond = extract32(insn, 0, 4);
1375
1376 if (cond < 0x0e) {
1377 /* genuinely conditional branches */
1378 TCGLabel *label_match = gen_new_label();
1379 arm_gen_test_cc(cond, label_match);
1380 gen_goto_tb(s, 0, s->pc);
1381 gen_set_label(label_match);
1382 gen_goto_tb(s, 1, addr);
1383 } else {
1384 /* 0xe and 0xf are both "always" conditions */
1385 gen_goto_tb(s, 0, addr);
1386 }
1387 }
1388
1389 /* HINT instruction group, including various allocated HINTs */
1390 static void handle_hint(DisasContext *s, uint32_t insn,
1391 unsigned int op1, unsigned int op2, unsigned int crm)
1392 {
1393 unsigned int selector = crm << 3 | op2;
1394
1395 if (op1 != 3) {
1396 unallocated_encoding(s);
1397 return;
1398 }
1399
1400 switch (selector) {
1401 case 0: /* NOP */
1402 return;
1403 case 3: /* WFI */
1404 s->base.is_jmp = DISAS_WFI;
1405 return;
1406 /* When running in MTTCG we don't generate jumps to the yield and
1407 * WFE helpers as it won't affect the scheduling of other vCPUs.
1408 * If we wanted to more completely model WFE/SEV so we don't busy
1409 * spin unnecessarily we would need to do something more involved.
1410 */
1411 case 1: /* YIELD */
1412 if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
1413 s->base.is_jmp = DISAS_YIELD;
1414 }
1415 return;
1416 case 2: /* WFE */
1417 if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
1418 s->base.is_jmp = DISAS_WFE;
1419 }
1420 return;
1421 case 4: /* SEV */
1422 case 5: /* SEVL */
1423 /* we treat all as NOP at least for now */
1424 return;
1425 default:
1426 /* default specified as NOP equivalent */
1427 return;
1428 }
1429 }
1430
1431 static void gen_clrex(DisasContext *s, uint32_t insn)
1432 {
1433 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
1434 }
1435
1436 /* CLREX, DSB, DMB, ISB */
1437 static void handle_sync(DisasContext *s, uint32_t insn,
1438 unsigned int op1, unsigned int op2, unsigned int crm)
1439 {
1440 TCGBar bar;
1441
1442 if (op1 != 3) {
1443 unallocated_encoding(s);
1444 return;
1445 }
1446
1447 switch (op2) {
1448 case 2: /* CLREX */
1449 gen_clrex(s, insn);
1450 return;
1451 case 4: /* DSB */
1452 case 5: /* DMB */
1453 switch (crm & 3) {
1454 case 1: /* MBReqTypes_Reads */
1455 bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST;
1456 break;
1457 case 2: /* MBReqTypes_Writes */
1458 bar = TCG_BAR_SC | TCG_MO_ST_ST;
1459 break;
1460 default: /* MBReqTypes_All */
1461 bar = TCG_BAR_SC | TCG_MO_ALL;
1462 break;
1463 }
1464 tcg_gen_mb(bar);
1465 return;
1466 case 6: /* ISB */
1467 /* We need to break the TB after this insn to execute
1468 * a self-modified code correctly and also to take
1469 * any pending interrupts immediately.
1470 */
1471 gen_goto_tb(s, 0, s->pc);
1472 return;
1473 default:
1474 unallocated_encoding(s);
1475 return;
1476 }
1477 }
1478
1479 /* MSR (immediate) - move immediate to processor state field */
1480 static void handle_msr_i(DisasContext *s, uint32_t insn,
1481 unsigned int op1, unsigned int op2, unsigned int crm)
1482 {
1483 int op = op1 << 3 | op2;
1484 switch (op) {
1485 case 0x05: /* SPSel */
1486 if (s->current_el == 0) {
1487 unallocated_encoding(s);
1488 return;
1489 }
1490 /* fall through */
1491 case 0x1e: /* DAIFSet */
1492 case 0x1f: /* DAIFClear */
1493 {
1494 TCGv_i32 tcg_imm = tcg_const_i32(crm);
1495 TCGv_i32 tcg_op = tcg_const_i32(op);
1496 gen_a64_set_pc_im(s->pc - 4);
1497 gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
1498 tcg_temp_free_i32(tcg_imm);
1499 tcg_temp_free_i32(tcg_op);
1500 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1501 gen_a64_set_pc_im(s->pc);
1502 s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP);
1503 break;
1504 }
1505 default:
1506 unallocated_encoding(s);
1507 return;
1508 }
1509 }
1510
1511 static void gen_get_nzcv(TCGv_i64 tcg_rt)
1512 {
1513 TCGv_i32 tmp = tcg_temp_new_i32();
1514 TCGv_i32 nzcv = tcg_temp_new_i32();
1515
1516 /* build bit 31, N */
1517 tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31));
1518 /* build bit 30, Z */
1519 tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0);
1520 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1);
1521 /* build bit 29, C */
1522 tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1);
1523 /* build bit 28, V */
1524 tcg_gen_shri_i32(tmp, cpu_VF, 31);
1525 tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1);
1526 /* generate result */
1527 tcg_gen_extu_i32_i64(tcg_rt, nzcv);
1528
1529 tcg_temp_free_i32(nzcv);
1530 tcg_temp_free_i32(tmp);
1531 }
1532
1533 static void gen_set_nzcv(TCGv_i64 tcg_rt)
1534
1535 {
1536 TCGv_i32 nzcv = tcg_temp_new_i32();
1537
1538 /* take NZCV from R[t] */
1539 tcg_gen_extrl_i64_i32(nzcv, tcg_rt);
1540
1541 /* bit 31, N */
1542 tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31));
1543 /* bit 30, Z */
1544 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30));
1545 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0);
1546 /* bit 29, C */
1547 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29));
1548 tcg_gen_shri_i32(cpu_CF, cpu_CF, 29);
1549 /* bit 28, V */
1550 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28));
1551 tcg_gen_shli_i32(cpu_VF, cpu_VF, 3);
1552 tcg_temp_free_i32(nzcv);
1553 }
1554
1555 /* MRS - move from system register
1556 * MSR (register) - move to system register
1557 * SYS
1558 * SYSL
1559 * These are all essentially the same insn in 'read' and 'write'
1560 * versions, with varying op0 fields.
1561 */
1562 static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
1563 unsigned int op0, unsigned int op1, unsigned int op2,
1564 unsigned int crn, unsigned int crm, unsigned int rt)
1565 {
1566 const ARMCPRegInfo *ri;
1567 TCGv_i64 tcg_rt;
1568
1569 ri = get_arm_cp_reginfo(s->cp_regs,
1570 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP,
1571 crn, crm, op0, op1, op2));
1572
1573 if (!ri) {
1574 /* Unknown register; this might be a guest error or a QEMU
1575 * unimplemented feature.
1576 */
1577 qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 "
1578 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1579 isread ? "read" : "write", op0, op1, crn, crm, op2);
1580 unallocated_encoding(s);
1581 return;
1582 }
1583
1584 /* Check access permissions */
1585 if (!cp_access_ok(s->current_el, ri, isread)) {
1586 unallocated_encoding(s);
1587 return;
1588 }
1589
1590 if (ri->accessfn) {
1591 /* Emit code to perform further access permissions checks at
1592 * runtime; this may result in an exception.
1593 */
1594 TCGv_ptr tmpptr;
1595 TCGv_i32 tcg_syn, tcg_isread;
1596 uint32_t syndrome;
1597
1598 gen_a64_set_pc_im(s->pc - 4);
1599 tmpptr = tcg_const_ptr(ri);
1600 syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
1601 tcg_syn = tcg_const_i32(syndrome);
1602 tcg_isread = tcg_const_i32(isread);
1603 gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread);
1604 tcg_temp_free_ptr(tmpptr);
1605 tcg_temp_free_i32(tcg_syn);
1606 tcg_temp_free_i32(tcg_isread);
1607 }
1608
1609 /* Handle special cases first */
1610 switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) {
1611 case ARM_CP_NOP:
1612 return;
1613 case ARM_CP_NZCV:
1614 tcg_rt = cpu_reg(s, rt);
1615 if (isread) {
1616 gen_get_nzcv(tcg_rt);
1617 } else {
1618 gen_set_nzcv(tcg_rt);
1619 }
1620 return;
1621 case ARM_CP_CURRENTEL:
1622 /* Reads as current EL value from pstate, which is
1623 * guaranteed to be constant by the tb flags.
1624 */
1625 tcg_rt = cpu_reg(s, rt);
1626 tcg_gen_movi_i64(tcg_rt, s->current_el << 2);
1627 return;
1628 case ARM_CP_DC_ZVA:
1629 /* Writes clear the aligned block of memory which rt points into. */
1630 tcg_rt = cpu_reg(s, rt);
1631 gen_helper_dc_zva(cpu_env, tcg_rt);
1632 return;
1633 default:
1634 break;
1635 }
1636 if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
1637 return;
1638 } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
1639 return;
1640 }
1641
1642 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
1643 gen_io_start();
1644 }
1645
1646 tcg_rt = cpu_reg(s, rt);
1647
1648 if (isread) {
1649 if (ri->type & ARM_CP_CONST) {
1650 tcg_gen_movi_i64(tcg_rt, ri->resetvalue);
1651 } else if (ri->readfn) {
1652 TCGv_ptr tmpptr;
1653 tmpptr = tcg_const_ptr(ri);
1654 gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr);
1655 tcg_temp_free_ptr(tmpptr);
1656 } else {
1657 tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset);
1658 }
1659 } else {
1660 if (ri->type & ARM_CP_CONST) {
1661 /* If not forbidden by access permissions, treat as WI */
1662 return;
1663 } else if (ri->writefn) {
1664 TCGv_ptr tmpptr;
1665 tmpptr = tcg_const_ptr(ri);
1666 gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt);
1667 tcg_temp_free_ptr(tmpptr);
1668 } else {
1669 tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset);
1670 }
1671 }
1672
1673 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
1674 /* I/O operations must end the TB here (whether read or write) */
1675 gen_io_end();
1676 s->base.is_jmp = DISAS_UPDATE;
1677 } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
1678 /* We default to ending the TB on a coprocessor register write,
1679 * but allow this to be suppressed by the register definition
1680 * (usually only necessary to work around guest bugs).
1681 */
1682 s->base.is_jmp = DISAS_UPDATE;
1683 }
1684 }
1685
1686 /* System
1687 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1688 * +---------------------+---+-----+-----+-------+-------+-----+------+
1689 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1690 * +---------------------+---+-----+-----+-------+-------+-----+------+
1691 */
1692 static void disas_system(DisasContext *s, uint32_t insn)
1693 {
1694 unsigned int l, op0, op1, crn, crm, op2, rt;
1695 l = extract32(insn, 21, 1);
1696 op0 = extract32(insn, 19, 2);
1697 op1 = extract32(insn, 16, 3);
1698 crn = extract32(insn, 12, 4);
1699 crm = extract32(insn, 8, 4);
1700 op2 = extract32(insn, 5, 3);
1701 rt = extract32(insn, 0, 5);
1702
1703 if (op0 == 0) {
1704 if (l || rt != 31) {
1705 unallocated_encoding(s);
1706 return;
1707 }
1708 switch (crn) {
1709 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1710 handle_hint(s, insn, op1, op2, crm);
1711 break;
1712 case 3: /* CLREX, DSB, DMB, ISB */
1713 handle_sync(s, insn, op1, op2, crm);
1714 break;
1715 case 4: /* MSR (immediate) */
1716 handle_msr_i(s, insn, op1, op2, crm);
1717 break;
1718 default:
1719 unallocated_encoding(s);
1720 break;
1721 }
1722 return;
1723 }
1724 handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt);
1725 }
1726
1727 /* Exception generation
1728 *
1729 * 31 24 23 21 20 5 4 2 1 0
1730 * +-----------------+-----+------------------------+-----+----+
1731 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1732 * +-----------------------+------------------------+----------+
1733 */
1734 static void disas_exc(DisasContext *s, uint32_t insn)
1735 {
1736 int opc = extract32(insn, 21, 3);
1737 int op2_ll = extract32(insn, 0, 5);
1738 int imm16 = extract32(insn, 5, 16);
1739 TCGv_i32 tmp;
1740
1741 switch (opc) {
1742 case 0:
1743 /* For SVC, HVC and SMC we advance the single-step state
1744 * machine before taking the exception. This is architecturally
1745 * mandated, to ensure that single-stepping a system call
1746 * instruction works properly.
1747 */
1748 switch (op2_ll) {
1749 case 1: /* SVC */
1750 gen_ss_advance(s);
1751 gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16),
1752 default_exception_el(s));
1753 break;
1754 case 2: /* HVC */
1755 if (s->current_el == 0) {
1756 unallocated_encoding(s);
1757 break;
1758 }
1759 /* The pre HVC helper handles cases when HVC gets trapped
1760 * as an undefined insn by runtime configuration.
1761 */
1762 gen_a64_set_pc_im(s->pc - 4);
1763 gen_helper_pre_hvc(cpu_env);
1764 gen_ss_advance(s);
1765 gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
1766 break;
1767 case 3: /* SMC */
1768 if (s->current_el == 0) {
1769 unallocated_encoding(s);
1770 break;
1771 }
1772 gen_a64_set_pc_im(s->pc - 4);
1773 tmp = tcg_const_i32(syn_aa64_smc(imm16));
1774 gen_helper_pre_smc(cpu_env, tmp);
1775 tcg_temp_free_i32(tmp);
1776 gen_ss_advance(s);
1777 gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3);
1778 break;
1779 default:
1780 unallocated_encoding(s);
1781 break;
1782 }
1783 break;
1784 case 1:
1785 if (op2_ll != 0) {
1786 unallocated_encoding(s);
1787 break;
1788 }
1789 /* BRK */
1790 gen_exception_bkpt_insn(s, 4, syn_aa64_bkpt(imm16));
1791 break;
1792 case 2:
1793 if (op2_ll != 0) {
1794 unallocated_encoding(s);
1795 break;
1796 }
1797 /* HLT. This has two purposes.
1798 * Architecturally, it is an external halting debug instruction.
1799 * Since QEMU doesn't implement external debug, we treat this as
1800 * it is required for halting debug disabled: it will UNDEF.
1801 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1802 */
1803 if (semihosting_enabled() && imm16 == 0xf000) {
1804 #ifndef CONFIG_USER_ONLY
1805 /* In system mode, don't allow userspace access to semihosting,
1806 * to provide some semblance of security (and for consistency
1807 * with our 32-bit semihosting).
1808 */
1809 if (s->current_el == 0) {
1810 unsupported_encoding(s, insn);
1811 break;
1812 }
1813 #endif
1814 gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
1815 } else {
1816 unsupported_encoding(s, insn);
1817 }
1818 break;
1819 case 5:
1820 if (op2_ll < 1 || op2_ll > 3) {
1821 unallocated_encoding(s);
1822 break;
1823 }
1824 /* DCPS1, DCPS2, DCPS3 */
1825 unsupported_encoding(s, insn);
1826 break;
1827 default:
1828 unallocated_encoding(s);
1829 break;
1830 }
1831 }
1832
1833 /* Unconditional branch (register)
1834 * 31 25 24 21 20 16 15 10 9 5 4 0
1835 * +---------------+-------+-------+-------+------+-------+
1836 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1837 * +---------------+-------+-------+-------+------+-------+
1838 */
1839 static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
1840 {
1841 unsigned int opc, op2, op3, rn, op4;
1842
1843 opc = extract32(insn, 21, 4);
1844 op2 = extract32(insn, 16, 5);
1845 op3 = extract32(insn, 10, 6);
1846 rn = extract32(insn, 5, 5);
1847 op4 = extract32(insn, 0, 5);
1848
1849 if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
1850 unallocated_encoding(s);
1851 return;
1852 }
1853
1854 switch (opc) {
1855 case 0: /* BR */
1856 case 1: /* BLR */
1857 case 2: /* RET */
1858 gen_a64_set_pc(s, cpu_reg(s, rn));
1859 /* BLR also needs to load return address */
1860 if (opc == 1) {
1861 tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
1862 }
1863 break;
1864 case 4: /* ERET */
1865 if (s->current_el == 0) {
1866 unallocated_encoding(s);
1867 return;
1868 }
1869 if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
1870 gen_io_start();
1871 }
1872 gen_helper_exception_return(cpu_env);
1873 if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
1874 gen_io_end();
1875 }
1876 /* Must exit loop to check un-masked IRQs */
1877 s->base.is_jmp = DISAS_EXIT;
1878 return;
1879 case 5: /* DRPS */
1880 if (rn != 0x1f) {
1881 unallocated_encoding(s);
1882 } else {
1883 unsupported_encoding(s, insn);
1884 }
1885 return;
1886 default:
1887 unallocated_encoding(s);
1888 return;
1889 }
1890
1891 s->base.is_jmp = DISAS_JUMP;
1892 }
1893
1894 /* Branches, exception generating and system instructions */
1895 static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
1896 {
1897 switch (extract32(insn, 25, 7)) {
1898 case 0x0a: case 0x0b:
1899 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
1900 disas_uncond_b_imm(s, insn);
1901 break;
1902 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
1903 disas_comp_b_imm(s, insn);
1904 break;
1905 case 0x1b: case 0x5b: /* Test & branch (immediate) */
1906 disas_test_b_imm(s, insn);
1907 break;
1908 case 0x2a: /* Conditional branch (immediate) */
1909 disas_cond_b_imm(s, insn);
1910 break;
1911 case 0x6a: /* Exception generation / System */
1912 if (insn & (1 << 24)) {
1913 disas_system(s, insn);
1914 } else {
1915 disas_exc(s, insn);
1916 }
1917 break;
1918 case 0x6b: /* Unconditional branch (register) */
1919 disas_uncond_b_reg(s, insn);
1920 break;
1921 default:
1922 unallocated_encoding(s);
1923 break;
1924 }
1925 }
1926
1927 /*
1928 * Load/Store exclusive instructions are implemented by remembering
1929 * the value/address loaded, and seeing if these are the same
1930 * when the store is performed. This is not actually the architecturally
1931 * mandated semantics, but it works for typical guest code sequences
1932 * and avoids having to monitor regular stores.
1933 *
1934 * The store exclusive uses the atomic cmpxchg primitives to avoid
1935 * races in multi-threaded linux-user and when MTTCG softmmu is
1936 * enabled.
1937 */
1938 static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
1939 TCGv_i64 addr, int size, bool is_pair)
1940 {
1941 int idx = get_mem_index(s);
1942 TCGMemOp memop = s->be_data;
1943
1944 g_assert(size <= 3);
1945 if (is_pair) {
1946 g_assert(size >= 2);
1947 if (size == 2) {
1948 /* The pair must be single-copy atomic for the doubleword. */
1949 memop |= MO_64 | MO_ALIGN;
1950 tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
1951 if (s->be_data == MO_LE) {
1952 tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 0, 32);
1953 tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32);
1954 } else {
1955 tcg_gen_extract_i64(cpu_reg(s, rt), cpu_exclusive_val, 32, 32);
1956 tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32);
1957 }
1958 } else {
1959 /* The pair must be single-copy atomic for *each* doubleword, not
1960 the entire quadword, however it must be quadword aligned. */
1961 memop |= MO_64;
1962 tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx,
1963 memop | MO_ALIGN_16);
1964
1965 TCGv_i64 addr2 = tcg_temp_new_i64();
1966 tcg_gen_addi_i64(addr2, addr, 8);
1967 tcg_gen_qemu_ld_i64(cpu_exclusive_high, addr2, idx, memop);
1968 tcg_temp_free_i64(addr2);
1969
1970 tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
1971 tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high);
1972 }
1973 } else {
1974 memop |= size | MO_ALIGN;
1975 tcg_gen_qemu_ld_i64(cpu_exclusive_val, addr, idx, memop);
1976 tcg_gen_mov_i64(cpu_reg(s, rt), cpu_exclusive_val);
1977 }
1978 tcg_gen_mov_i64(cpu_exclusive_addr, addr);
1979 }
1980
1981 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
1982 TCGv_i64 addr, int size, int is_pair)
1983 {
1984 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
1985 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
1986 * [addr] = {Rt};
1987 * if (is_pair) {
1988 * [addr + datasize] = {Rt2};
1989 * }
1990 * {Rd} = 0;
1991 * } else {
1992 * {Rd} = 1;
1993 * }
1994 * env->exclusive_addr = -1;
1995 */
1996 TCGLabel *fail_label = gen_new_label();
1997 TCGLabel *done_label = gen_new_label();
1998 TCGv_i64 tmp;
1999
2000 tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label);
2001
2002 tmp = tcg_temp_new_i64();
2003 if (is_pair) {
2004 if (size == 2) {
2005 if (s->be_data == MO_LE) {
2006 tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2));
2007 } else {
2008 tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt));
2009 }
2010 tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr,
2011 cpu_exclusive_val, tmp,
2012 get_mem_index(s),
2013 MO_64 | MO_ALIGN | s->be_data);
2014 tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
2015 } else if (s->be_data == MO_LE) {
2016 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2017 gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env,
2018 cpu_exclusive_addr,
2019 cpu_reg(s, rt),
2020 cpu_reg(s, rt2));
2021 } else {
2022 gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr,
2023 cpu_reg(s, rt), cpu_reg(s, rt2));
2024 }
2025 } else {
2026 if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2027 gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env,
2028 cpu_exclusive_addr,
2029 cpu_reg(s, rt),
2030 cpu_reg(s, rt2));
2031 } else {
2032 gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr,
2033 cpu_reg(s, rt), cpu_reg(s, rt2));
2034 }
2035 }
2036 } else {
2037 tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_val,
2038 cpu_reg(s, rt), get_mem_index(s),
2039 size | MO_ALIGN | s->be_data);
2040 tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val);
2041 }
2042 tcg_gen_mov_i64(cpu_reg(s, rd), tmp);
2043 tcg_temp_free_i64(tmp);
2044 tcg_gen_br(done_label);
2045
2046 gen_set_label(fail_label);
2047 tcg_gen_movi_i64(cpu_reg(s, rd), 1);
2048 gen_set_label(done_label);
2049 tcg_gen_movi_i64(cpu_exclusive_addr, -1);
2050 }
2051
2052 static void gen_compare_and_swap(DisasContext *s, int rs, int rt,
2053 int rn, int size)
2054 {
2055 TCGv_i64 tcg_rs = cpu_reg(s, rs);
2056 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2057 int memidx = get_mem_index(s);
2058 TCGv_i64 addr = cpu_reg_sp(s, rn);
2059
2060 if (rn == 31) {
2061 gen_check_sp_alignment(s);
2062 }
2063 tcg_gen_atomic_cmpxchg_i64(tcg_rs, addr, tcg_rs, tcg_rt, memidx,
2064 size | MO_ALIGN | s->be_data);
2065 }
2066
2067 static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
2068 int rn, int size)
2069 {
2070 TCGv_i64 s1 = cpu_reg(s, rs);
2071 TCGv_i64 s2 = cpu_reg(s, rs + 1);
2072 TCGv_i64 t1 = cpu_reg(s, rt);
2073 TCGv_i64 t2 = cpu_reg(s, rt + 1);
2074 TCGv_i64 addr = cpu_reg_sp(s, rn);
2075 int memidx = get_mem_index(s);
2076
2077 if (rn == 31) {
2078 gen_check_sp_alignment(s);
2079 }
2080
2081 if (size == 2) {
2082 TCGv_i64 cmp = tcg_temp_new_i64();
2083 TCGv_i64 val = tcg_temp_new_i64();
2084
2085 if (s->be_data == MO_LE) {
2086 tcg_gen_concat32_i64(val, t1, t2);
2087 tcg_gen_concat32_i64(cmp, s1, s2);
2088 } else {
2089 tcg_gen_concat32_i64(val, t2, t1);
2090 tcg_gen_concat32_i64(cmp, s2, s1);
2091 }
2092
2093 tcg_gen_atomic_cmpxchg_i64(cmp, addr, cmp, val, memidx,
2094 MO_64 | MO_ALIGN | s->be_data);
2095 tcg_temp_free_i64(val);
2096
2097 if (s->be_data == MO_LE) {
2098 tcg_gen_extr32_i64(s1, s2, cmp);
2099 } else {
2100 tcg_gen_extr32_i64(s2, s1, cmp);
2101 }
2102 tcg_temp_free_i64(cmp);
2103 } else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
2104 TCGv_i32 tcg_rs = tcg_const_i32(rs);
2105
2106 if (s->be_data == MO_LE) {
2107 gen_helper_casp_le_parallel(cpu_env, tcg_rs, addr, t1, t2);
2108 } else {
2109 gen_helper_casp_be_parallel(cpu_env, tcg_rs, addr, t1, t2);
2110 }
2111 tcg_temp_free_i32(tcg_rs);
2112 } else {
2113 TCGv_i64 d1 = tcg_temp_new_i64();
2114 TCGv_i64 d2 = tcg_temp_new_i64();
2115 TCGv_i64 a2 = tcg_temp_new_i64();
2116 TCGv_i64 c1 = tcg_temp_new_i64();
2117 TCGv_i64 c2 = tcg_temp_new_i64();
2118 TCGv_i64 zero = tcg_const_i64(0);
2119
2120 /* Load the two words, in memory order. */
2121 tcg_gen_qemu_ld_i64(d1, addr, memidx,
2122 MO_64 | MO_ALIGN_16 | s->be_data);
2123 tcg_gen_addi_i64(a2, addr, 8);
2124 tcg_gen_qemu_ld_i64(d2, addr, memidx, MO_64 | s->be_data);
2125
2126 /* Compare the two words, also in memory order. */
2127 tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1);
2128 tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2);
2129 tcg_gen_and_i64(c2, c2, c1);
2130
2131 /* If compare equal, write back new data, else write back old data. */
2132 tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1);
2133 tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2);
2134 tcg_gen_qemu_st_i64(c1, addr, memidx, MO_64 | s->be_data);
2135 tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data);
2136 tcg_temp_free_i64(a2);
2137 tcg_temp_free_i64(c1);
2138 tcg_temp_free_i64(c2);
2139 tcg_temp_free_i64(zero);
2140
2141 /* Write back the data from memory to Rs. */
2142 tcg_gen_mov_i64(s1, d1);
2143 tcg_gen_mov_i64(s2, d2);
2144 tcg_temp_free_i64(d1);
2145 tcg_temp_free_i64(d2);
2146 }
2147 }
2148
2149 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2150 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2151 */
2152 static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc)
2153 {
2154 int opc0 = extract32(opc, 0, 1);
2155 int regsize;
2156
2157 if (is_signed) {
2158 regsize = opc0 ? 32 : 64;
2159 } else {
2160 regsize = size == 3 ? 64 : 32;
2161 }
2162 return regsize == 64;
2163 }
2164
2165 /* Load/store exclusive
2166 *
2167 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2168 * +-----+-------------+----+---+----+------+----+-------+------+------+
2169 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2170 * +-----+-------------+----+---+----+------+----+-------+------+------+
2171 *
2172 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2173 * L: 0 -> store, 1 -> load
2174 * o2: 0 -> exclusive, 1 -> not
2175 * o1: 0 -> single register, 1 -> register pair
2176 * o0: 1 -> load-acquire/store-release, 0 -> not
2177 */
2178 static void disas_ldst_excl(DisasContext *s, uint32_t insn)
2179 {
2180 int rt = extract32(insn, 0, 5);
2181 int rn = extract32(insn, 5, 5);
2182 int rt2 = extract32(insn, 10, 5);
2183 int rs = extract32(insn, 16, 5);
2184 int is_lasr = extract32(insn, 15, 1);
2185 int o2_L_o1_o0 = extract32(insn, 21, 3) * 2 | is_lasr;
2186 int size = extract32(insn, 30, 2);
2187 TCGv_i64 tcg_addr;
2188
2189 switch (o2_L_o1_o0) {
2190 case 0x0: /* STXR */
2191 case 0x1: /* STLXR */
2192 if (rn == 31) {
2193 gen_check_sp_alignment(s);
2194 }
2195 if (is_lasr) {
2196 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
2197 }
2198 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2199 gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, false);
2200 return;
2201
2202 case 0x4: /* LDXR */
2203 case 0x5: /* LDAXR */
2204 if (rn == 31) {
2205 gen_check_sp_alignment(s);
2206 }
2207 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2208 s->is_ldex = true;
2209 gen_load_exclusive(s, rt, rt2, tcg_addr, size, false);
2210 if (is_lasr) {
2211 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
2212 }
2213 return;
2214
2215 case 0x9: /* STLR */
2216 /* Generate ISS for non-exclusive accesses including LASR. */
2217 if (rn == 31) {
2218 gen_check_sp_alignment(s);
2219 }
2220 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
2221 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2222 do_gpr_st(s, cpu_reg(s, rt), tcg_addr, size, true, rt,
2223 disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
2224 return;
2225
2226 case 0xd: /* LDAR */
2227 /* Generate ISS for non-exclusive accesses including LASR. */
2228 if (rn == 31) {
2229 gen_check_sp_alignment(s);
2230 }
2231 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2232 do_gpr_ld(s, cpu_reg(s, rt), tcg_addr, size, false, false, true, rt,
2233 disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
2234 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
2235 return;
2236
2237 case 0x2: case 0x3: /* CASP / STXP */
2238 if (size & 2) { /* STXP / STLXP */
2239 if (rn == 31) {
2240 gen_check_sp_alignment(s);
2241 }
2242 if (is_lasr) {
2243 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
2244 }
2245 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2246 gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, true);
2247 return;
2248 }
2249 if (rt2 == 31
2250 && ((rt | rs) & 1) == 0
2251 && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) {
2252 /* CASP / CASPL */
2253 gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
2254 return;
2255 }
2256 break;
2257
2258 case 0x6: case 0x7: /* CASPA / LDXP */
2259 if (size & 2) { /* LDXP / LDAXP */
2260 if (rn == 31) {
2261 gen_check_sp_alignment(s);
2262 }
2263 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2264 s->is_ldex = true;
2265 gen_load_exclusive(s, rt, rt2, tcg_addr, size, true);
2266 if (is_lasr) {
2267 tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
2268 }
2269 return;
2270 }
2271 if (rt2 == 31
2272 && ((rt | rs) & 1) == 0
2273 && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) {
2274 /* CASPA / CASPAL */
2275 gen_compare_and_swap_pair(s, rs, rt, rn, size | 2);
2276 return;
2277 }
2278 break;
2279
2280 case 0xa: /* CAS */
2281 case 0xb: /* CASL */
2282 case 0xe: /* CASA */
2283 case 0xf: /* CASAL */
2284 if (rt2 == 31 && arm_dc_feature(s, ARM_FEATURE_V8_ATOMICS)) {
2285 gen_compare_and_swap(s, rs, rt, rn, size);
2286 return;
2287 }
2288 break;
2289 }
2290 unallocated_encoding(s);
2291 }
2292
2293 /*
2294 * Load register (literal)
2295 *
2296 * 31 30 29 27 26 25 24 23 5 4 0
2297 * +-----+-------+---+-----+-------------------+-------+
2298 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2299 * +-----+-------+---+-----+-------------------+-------+
2300 *
2301 * V: 1 -> vector (simd/fp)
2302 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2303 * 10-> 32 bit signed, 11 -> prefetch
2304 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2305 */
2306 static void disas_ld_lit(DisasContext *s, uint32_t insn)
2307 {
2308 int rt = extract32(insn, 0, 5);
2309 int64_t imm = sextract32(insn, 5, 19) << 2;
2310 bool is_vector = extract32(insn, 26, 1);
2311 int opc = extract32(insn, 30, 2);
2312 bool is_signed = false;
2313 int size = 2;
2314 TCGv_i64 tcg_rt, tcg_addr;
2315
2316 if (is_vector) {
2317 if (opc == 3) {
2318 unallocated_encoding(s);
2319 return;
2320 }
2321 size = 2 + opc;
2322 if (!fp_access_check(s)) {
2323 return;
2324 }
2325 } else {
2326 if (opc == 3) {
2327 /* PRFM (literal) : prefetch */
2328 return;
2329 }
2330 size = 2 + extract32(opc, 0, 1);
2331 is_signed = extract32(opc, 1, 1);
2332 }
2333
2334 tcg_rt = cpu_reg(s, rt);
2335
2336 tcg_addr = tcg_const_i64((s->pc - 4) + imm);
2337 if (is_vector) {
2338 do_fp_ld(s, rt, tcg_addr, size);
2339 } else {
2340 /* Only unsigned 32bit loads target 32bit registers. */
2341 bool iss_sf = opc != 0;
2342
2343 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false,
2344 true, rt, iss_sf, false);
2345 }
2346 tcg_temp_free_i64(tcg_addr);
2347 }
2348
2349 /*
2350 * LDNP (Load Pair - non-temporal hint)
2351 * LDP (Load Pair - non vector)
2352 * LDPSW (Load Pair Signed Word - non vector)
2353 * STNP (Store Pair - non-temporal hint)
2354 * STP (Store Pair - non vector)
2355 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2356 * LDP (Load Pair of SIMD&FP)
2357 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2358 * STP (Store Pair of SIMD&FP)
2359 *
2360 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2361 * +-----+-------+---+---+-------+---+-----------------------------+
2362 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2363 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2364 *
2365 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2366 * LDPSW 01
2367 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2368 * V: 0 -> GPR, 1 -> Vector
2369 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2370 * 10 -> signed offset, 11 -> pre-index
2371 * L: 0 -> Store 1 -> Load
2372 *
2373 * Rt, Rt2 = GPR or SIMD registers to be stored
2374 * Rn = general purpose register containing address
2375 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2376 */
2377 static void disas_ldst_pair(DisasContext *s, uint32_t insn)
2378 {
2379 int rt = extract32(insn, 0, 5);
2380 int rn = extract32(insn, 5, 5);
2381 int rt2 = extract32(insn, 10, 5);
2382 uint64_t offset = sextract64(insn, 15, 7);
2383 int index = extract32(insn, 23, 2);
2384 bool is_vector = extract32(insn, 26, 1);
2385 bool is_load = extract32(insn, 22, 1);
2386 int opc = extract32(insn, 30, 2);
2387
2388 bool is_signed = false;
2389 bool postindex = false;
2390 bool wback = false;
2391
2392 TCGv_i64 tcg_addr; /* calculated address */
2393 int size;
2394
2395 if (opc == 3) {
2396 unallocated_encoding(s);
2397 return;
2398 }
2399
2400 if (is_vector) {
2401 size = 2 + opc;
2402 } else {
2403 size = 2 + extract32(opc, 1, 1);
2404 is_signed = extract32(opc, 0, 1);
2405 if (!is_load && is_signed) {
2406 unallocated_encoding(s);
2407 return;
2408 }
2409 }
2410
2411 switch (index) {
2412 case 1: /* post-index */
2413 postindex = true;
2414 wback = true;
2415 break;
2416 case 0:
2417 /* signed offset with "non-temporal" hint. Since we don't emulate
2418 * caches we don't care about hints to the cache system about
2419 * data access patterns, and handle this identically to plain
2420 * signed offset.
2421 */
2422 if (is_signed) {
2423 /* There is no non-temporal-hint version of LDPSW */
2424 unallocated_encoding(s);
2425 return;
2426 }
2427 postindex = false;
2428 break;
2429 case 2: /* signed offset, rn not updated */
2430 postindex = false;
2431 break;
2432 case 3: /* pre-index */
2433 postindex = false;
2434 wback = true;
2435 break;
2436 }
2437
2438 if (is_vector && !fp_access_check(s)) {
2439 return;
2440 }
2441
2442 offset <<= size;
2443
2444 if (rn == 31) {
2445 gen_check_sp_alignment(s);
2446 }
2447
2448 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2449
2450 if (!postindex) {
2451 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2452 }
2453
2454 if (is_vector) {
2455 if (is_load) {
2456 do_fp_ld(s, rt, tcg_addr, size);
2457 } else {
2458 do_fp_st(s, rt, tcg_addr, size);
2459 }
2460 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
2461 if (is_load) {
2462 do_fp_ld(s, rt2, tcg_addr, size);
2463 } else {
2464 do_fp_st(s, rt2, tcg_addr, size);
2465 }
2466 } else {
2467 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2468 TCGv_i64 tcg_rt2 = cpu_reg(s, rt2);
2469
2470 if (is_load) {
2471 TCGv_i64 tmp = tcg_temp_new_i64();
2472
2473 /* Do not modify tcg_rt before recognizing any exception
2474 * from the second load.
2475 */
2476 do_gpr_ld(s, tmp, tcg_addr, size, is_signed, false,
2477 false, 0, false, false);
2478 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
2479 do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false,
2480 false, 0, false, false);
2481
2482 tcg_gen_mov_i64(tcg_rt, tmp);
2483 tcg_temp_free_i64(tmp);
2484 } else {
2485 do_gpr_st(s, tcg_rt, tcg_addr, size,
2486 false, 0, false, false);
2487 tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size);
2488 do_gpr_st(s, tcg_rt2, tcg_addr, size,
2489 false, 0, false, false);
2490 }
2491 }
2492
2493 if (wback) {
2494 if (postindex) {
2495 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size));
2496 } else {
2497 tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size);
2498 }
2499 tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
2500 }
2501 }
2502
2503 /*
2504 * Load/store (immediate post-indexed)
2505 * Load/store (immediate pre-indexed)
2506 * Load/store (unscaled immediate)
2507 *
2508 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2509 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2510 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2511 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2512 *
2513 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2514 10 -> unprivileged
2515 * V = 0 -> non-vector
2516 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2517 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2518 */
2519 static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
2520 int opc,
2521 int size,
2522 int rt,
2523 bool is_vector)
2524 {
2525 int rn = extract32(insn, 5, 5);
2526 int imm9 = sextract32(insn, 12, 9);
2527 int idx = extract32(insn, 10, 2);
2528 bool is_signed = false;
2529 bool is_store = false;
2530 bool is_extended = false;
2531 bool is_unpriv = (idx == 2);
2532 bool iss_valid = !is_vector;
2533 bool post_index;
2534 bool writeback;
2535
2536 TCGv_i64 tcg_addr;
2537
2538 if (is_vector) {
2539 size |= (opc & 2) << 1;
2540 if (size > 4 || is_unpriv) {
2541 unallocated_encoding(s);
2542 return;
2543 }
2544 is_store = ((opc & 1) == 0);
2545 if (!fp_access_check(s)) {
2546 return;
2547 }
2548 } else {
2549 if (size == 3 && opc == 2) {
2550 /* PRFM - prefetch */
2551 if (is_unpriv) {
2552 unallocated_encoding(s);
2553 return;
2554 }
2555 return;
2556 }
2557 if (opc == 3 && size > 1) {
2558 unallocated_encoding(s);
2559 return;
2560 }
2561 is_store = (opc == 0);
2562 is_signed = extract32(opc, 1, 1);
2563 is_extended = (size < 3) && extract32(opc, 0, 1);
2564 }
2565
2566 switch (idx) {
2567 case 0:
2568 case 2:
2569 post_index = false;
2570 writeback = false;
2571 break;
2572 case 1:
2573 post_index = true;
2574 writeback = true;
2575 break;
2576 case 3:
2577 post_index = false;
2578 writeback = true;
2579 break;
2580 default:
2581 g_assert_not_reached();
2582 }
2583
2584 if (rn == 31) {
2585 gen_check_sp_alignment(s);
2586 }
2587 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2588
2589 if (!post_index) {
2590 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
2591 }
2592
2593 if (is_vector) {
2594 if (is_store) {
2595 do_fp_st(s, rt, tcg_addr, size);
2596 } else {
2597 do_fp_ld(s, rt, tcg_addr, size);
2598 }
2599 } else {
2600 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2601 int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s);
2602 bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
2603
2604 if (is_store) {
2605 do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx,
2606 iss_valid, rt, iss_sf, false);
2607 } else {
2608 do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size,
2609 is_signed, is_extended, memidx,
2610 iss_valid, rt, iss_sf, false);
2611 }
2612 }
2613
2614 if (writeback) {
2615 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
2616 if (post_index) {
2617 tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9);
2618 }
2619 tcg_gen_mov_i64(tcg_rn, tcg_addr);
2620 }
2621 }
2622
2623 /*
2624 * Load/store (register offset)
2625 *
2626 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2627 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2628 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2629 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2630 *
2631 * For non-vector:
2632 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2633 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2634 * For vector:
2635 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2636 * opc<0>: 0 -> store, 1 -> load
2637 * V: 1 -> vector/simd
2638 * opt: extend encoding (see DecodeRegExtend)
2639 * S: if S=1 then scale (essentially index by sizeof(size))
2640 * Rt: register to transfer into/out of
2641 * Rn: address register or SP for base
2642 * Rm: offset register or ZR for offset
2643 */
2644 static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
2645 int opc,
2646 int size,
2647 int rt,
2648 bool is_vector)
2649 {
2650 int rn = extract32(insn, 5, 5);
2651 int shift = extract32(insn, 12, 1);
2652 int rm = extract32(insn, 16, 5);
2653 int opt = extract32(insn, 13, 3);
2654 bool is_signed = false;
2655 bool is_store = false;
2656 bool is_extended = false;
2657
2658 TCGv_i64 tcg_rm;
2659 TCGv_i64 tcg_addr;
2660
2661 if (extract32(opt, 1, 1) == 0) {
2662 unallocated_encoding(s);
2663 return;
2664 }
2665
2666 if (is_vector) {
2667 size |= (opc & 2) << 1;
2668 if (size > 4) {
2669 unallocated_encoding(s);
2670 return;
2671 }
2672 is_store = !extract32(opc, 0, 1);
2673 if (!fp_access_check(s)) {
2674 return;
2675 }
2676 } else {
2677 if (size == 3 && opc == 2) {
2678 /* PRFM - prefetch */
2679 return;
2680 }
2681 if (opc == 3 && size > 1) {
2682 unallocated_encoding(s);
2683 return;
2684 }
2685 is_store = (opc == 0);
2686 is_signed = extract32(opc, 1, 1);
2687 is_extended = (size < 3) && extract32(opc, 0, 1);
2688 }
2689
2690 if (rn == 31) {
2691 gen_check_sp_alignment(s);
2692 }
2693 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2694
2695 tcg_rm = read_cpu_reg(s, rm, 1);
2696 ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0);
2697
2698 tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm);
2699
2700 if (is_vector) {
2701 if (is_store) {
2702 do_fp_st(s, rt, tcg_addr, size);
2703 } else {
2704 do_fp_ld(s, rt, tcg_addr, size);
2705 }
2706 } else {
2707 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2708 bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
2709 if (is_store) {
2710 do_gpr_st(s, tcg_rt, tcg_addr, size,
2711 true, rt, iss_sf, false);
2712 } else {
2713 do_gpr_ld(s, tcg_rt, tcg_addr, size,
2714 is_signed, is_extended,
2715 true, rt, iss_sf, false);
2716 }
2717 }
2718 }
2719
2720 /*
2721 * Load/store (unsigned immediate)
2722 *
2723 * 31 30 29 27 26 25 24 23 22 21 10 9 5
2724 * +----+-------+---+-----+-----+------------+-------+------+
2725 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
2726 * +----+-------+---+-----+-----+------------+-------+------+
2727 *
2728 * For non-vector:
2729 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2730 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2731 * For vector:
2732 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2733 * opc<0>: 0 -> store, 1 -> load
2734 * Rn: base address register (inc SP)
2735 * Rt: target register
2736 */
2737 static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
2738 int opc,
2739 int size,
2740 int rt,
2741 bool is_vector)
2742 {
2743 int rn = extract32(insn, 5, 5);
2744 unsigned int imm12 = extract32(insn, 10, 12);
2745 unsigned int offset;
2746
2747 TCGv_i64 tcg_addr;
2748
2749 bool is_store;
2750 bool is_signed = false;
2751 bool is_extended = false;
2752
2753 if (is_vector) {
2754 size |= (opc & 2) << 1;
2755 if (size > 4) {
2756 unallocated_encoding(s);
2757 return;
2758 }
2759 is_store = !extract32(opc, 0, 1);
2760 if (!fp_access_check(s)) {
2761 return;
2762 }
2763 } else {
2764 if (size == 3 && opc == 2) {
2765 /* PRFM - prefetch */
2766 return;
2767 }
2768 if (opc == 3 && size > 1) {
2769 unallocated_encoding(s);
2770 return;
2771 }
2772 is_store = (opc == 0);
2773 is_signed = extract32(opc, 1, 1);
2774 is_extended = (size < 3) && extract32(opc, 0, 1);
2775 }
2776
2777 if (rn == 31) {
2778 gen_check_sp_alignment(s);
2779 }
2780 tcg_addr = read_cpu_reg_sp(s, rn, 1);
2781 offset = imm12 << size;
2782 tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
2783
2784 if (is_vector) {
2785 if (is_store) {
2786 do_fp_st(s, rt, tcg_addr, size);
2787 } else {
2788 do_fp_ld(s, rt, tcg_addr, size);
2789 }
2790 } else {
2791 TCGv_i64 tcg_rt = cpu_reg(s, rt);
2792 bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
2793 if (is_store) {
2794 do_gpr_st(s, tcg_rt, tcg_addr, size,
2795 true, rt, iss_sf, false);
2796 } else {
2797 do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended,
2798 true, rt, iss_sf, false);
2799 }
2800 }
2801 }
2802
2803 /* Atomic memory operations
2804 *
2805 * 31 30 27 26 24 22 21 16 15 12 10 5 0
2806 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
2807 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
2808 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
2809 *
2810 * Rt: the result register
2811 * Rn: base address or SP
2812 * Rs: the source register for the operation
2813 * V: vector flag (always 0 as of v8.3)
2814 * A: acquire flag
2815 * R: release flag
2816 */
2817 static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
2818 int size, int rt, bool is_vector)
2819 {
2820 int rs = extract32(insn, 16, 5);
2821 int rn = extract32(insn, 5, 5);
2822 int o3_opc = extract32(insn, 12, 4);
2823 int feature = ARM_FEATURE_V8_ATOMICS;
2824 TCGv_i64 tcg_rn, tcg_rs;
2825 AtomicThreeOpFn *fn;
2826
2827 if (is_vector) {
2828 unallocated_encoding(s);
2829 return;
2830 }
2831 switch (o3_opc) {
2832 case 000: /* LDADD */
2833 fn = tcg_gen_atomic_fetch_add_i64;
2834 break;
2835 case 001: /* LDCLR */
2836 fn = tcg_gen_atomic_fetch_and_i64;
2837 break;
2838 case 002: /* LDEOR */
2839 fn = tcg_gen_atomic_fetch_xor_i64;
2840 break;
2841 case 003: /* LDSET */
2842 fn = tcg_gen_atomic_fetch_or_i64;
2843 break;
2844 case 004: /* LDSMAX */
2845 fn = tcg_gen_atomic_fetch_smax_i64;
2846 break;
2847 case 005: /* LDSMIN */
2848 fn = tcg_gen_atomic_fetch_smin_i64;
2849 break;
2850 case 006: /* LDUMAX */
2851 fn = tcg_gen_atomic_fetch_umax_i64;
2852 break;
2853 case 007: /* LDUMIN */
2854 fn = tcg_gen_atomic_fetch_umin_i64;
2855 break;
2856 case 010: /* SWP */
2857 fn = tcg_gen_atomic_xchg_i64;
2858 break;
2859 default:
2860 unallocated_encoding(s);
2861 return;
2862 }
2863 if (!arm_dc_feature(s, feature)) {
2864 unallocated_encoding(s);
2865 return;
2866 }
2867
2868 if (rn == 31) {
2869 gen_check_sp_alignment(s);
2870 }
2871 tcg_rn = cpu_reg_sp(s, rn);
2872 tcg_rs = read_cpu_reg(s, rs, true);
2873
2874 if (o3_opc == 1) { /* LDCLR */
2875 tcg_gen_not_i64(tcg_rs, tcg_rs);
2876 }
2877
2878 /* The tcg atomic primitives are all full barriers. Therefore we
2879 * can ignore the Acquire and Release bits of this instruction.
2880 */
2881 fn(cpu_reg(s, rt), tcg_rn, tcg_rs, get_mem_index(s),
2882 s->be_data | size | MO_ALIGN);
2883 }
2884
2885 /* Load/store register (all forms) */
2886 static void disas_ldst_reg(DisasContext *s, uint32_t insn)
2887 {
2888 int rt = extract32(insn, 0, 5);
2889 int opc = extract32(insn, 22, 2);
2890 bool is_vector = extract32(insn, 26, 1);
2891 int size = extract32(insn, 30, 2);
2892
2893 switch (extract32(insn, 24, 2)) {
2894 case 0:
2895 if (extract32(insn, 21, 1) == 0) {
2896 /* Load/store register (unscaled immediate)
2897 * Load/store immediate pre/post-indexed
2898 * Load/store register unprivileged
2899 */
2900 disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector);
2901 return;
2902 }
2903 switch (extract32(insn, 10, 2)) {
2904 case 0:
2905 disas_ldst_atomic(s, insn, size, rt, is_vector);
2906 return;
2907 case 2:
2908 disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector);
2909 return;
2910 }
2911 break;
2912 case 1:
2913 disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector);
2914 return;
2915 }
2916 unallocated_encoding(s);
2917 }
2918
2919 /* AdvSIMD load/store multiple structures
2920 *
2921 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
2922 * +---+---+---------------+---+-------------+--------+------+------+------+
2923 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
2924 * +---+---+---------------+---+-------------+--------+------+------+------+
2925 *
2926 * AdvSIMD load/store multiple structures (post-indexed)
2927 *
2928 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
2929 * +---+---+---------------+---+---+---------+--------+------+------+------+
2930 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
2931 * +---+---+---------------+---+---+---------+--------+------+------+------+
2932 *
2933 * Rt: first (or only) SIMD&FP register to be transferred
2934 * Rn: base address or SP
2935 * Rm (post-index only): post-index register (when !31) or size dependent #imm
2936 */
2937 static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
2938 {
2939 int rt = extract32(insn, 0, 5);
2940 int rn = extract32(insn, 5, 5);
2941 int size = extract32(insn, 10, 2);
2942 int opcode = extract32(insn, 12, 4);
2943 bool is_store = !extract32(insn, 22, 1);
2944 bool is_postidx = extract32(insn, 23, 1);
2945 bool is_q = extract32(insn, 30, 1);
2946 TCGv_i64 tcg_addr, tcg_rn;
2947
2948 int ebytes = 1 << size;
2949 int elements = (is_q ? 128 : 64) / (8 << size);
2950 int rpt; /* num iterations */
2951 int selem; /* structure elements */
2952 int r;
2953
2954 if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) {
2955 unallocated_encoding(s);
2956 return;
2957 }
2958
2959 /* From the shared decode logic */
2960 switch (opcode) {
2961 case 0x0:
2962 rpt = 1;
2963 selem = 4;
2964 break;
2965 case 0x2:
2966 rpt = 4;
2967 selem = 1;
2968 break;
2969 case 0x4:
2970 rpt = 1;
2971 selem = 3;
2972 break;
2973 case 0x6:
2974 rpt = 3;
2975 selem = 1;
2976 break;
2977 case 0x7:
2978 rpt = 1;
2979 selem = 1;
2980 break;
2981 case 0x8:
2982 rpt = 1;
2983 selem = 2;
2984 break;
2985 case 0xa:
2986 rpt = 2;
2987 selem = 1;
2988 break;
2989 default:
2990 unallocated_encoding(s);
2991 return;
2992 }
2993
2994 if (size == 3 && !is_q && selem != 1) {
2995 /* reserved */
2996 unallocated_encoding(s);
2997 return;
2998 }
2999
3000 if (!fp_access_check(s)) {
3001 return;
3002 }
3003
3004 if (rn == 31) {
3005 gen_check_sp_alignment(s);
3006 }
3007
3008 tcg_rn = cpu_reg_sp(s, rn);
3009 tcg_addr = tcg_temp_new_i64();
3010 tcg_gen_mov_i64(tcg_addr, tcg_rn);
3011
3012 for (r = 0; r < rpt; r++) {
3013 int e;
3014 for (e = 0; e < elements; e++) {
3015 int tt = (rt + r) % 32;
3016 int xs;
3017 for (xs = 0; xs < selem; xs++) {
3018 if (is_store) {
3019 do_vec_st(s, tt, e, tcg_addr, size);
3020 } else {
3021 do_vec_ld(s, tt, e, tcg_addr, size);
3022
3023 /* For non-quad operations, setting a slice of the low
3024 * 64 bits of the register clears the high 64 bits (in
3025 * the ARM ARM pseudocode this is implicit in the fact
3026 * that 'rval' is a 64 bit wide variable).
3027 * For quad operations, we might still need to zero the
3028 * high bits of SVE. We optimize by noticing that we only
3029 * need to do this the first time we touch a register.
3030 */
3031 if (e == 0 && (r == 0 || xs == selem - 1)) {
3032 clear_vec_high(s, is_q, tt);
3033 }
3034 }
3035 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
3036 tt = (tt + 1) % 32;
3037 }
3038 }
3039 }
3040
3041 if (is_postidx) {
3042 int rm = extract32(insn, 16, 5);
3043 if (rm == 31) {
3044 tcg_gen_mov_i64(tcg_rn, tcg_addr);
3045 } else {
3046 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
3047 }
3048 }
3049 tcg_temp_free_i64(tcg_addr);
3050 }
3051
3052 /* AdvSIMD load/store single structure
3053 *
3054 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3055 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3056 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3057 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3058 *
3059 * AdvSIMD load/store single structure (post-indexed)
3060 *
3061 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3062 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3063 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3064 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3065 *
3066 * Rt: first (or only) SIMD&FP register to be transferred
3067 * Rn: base address or SP
3068 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3069 * index = encoded in Q:S:size dependent on size
3070 *
3071 * lane_size = encoded in R, opc
3072 * transfer width = encoded in opc, S, size
3073 */
3074 static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
3075 {
3076 int rt = extract32(insn, 0, 5);
3077 int rn = extract32(insn, 5, 5);
3078 int size = extract32(insn, 10, 2);
3079 int S = extract32(insn, 12, 1);
3080 int opc = extract32(insn, 13, 3);
3081 int R = extract32(insn, 21, 1);
3082 int is_load = extract32(insn, 22, 1);
3083 int is_postidx = extract32(insn, 23, 1);
3084 int is_q = extract32(insn, 30, 1);
3085
3086 int scale = extract32(opc, 1, 2);
3087 int selem = (extract32(opc, 0, 1) << 1 | R) + 1;
3088 bool replicate = false;
3089 int index = is_q << 3 | S << 2 | size;
3090 int ebytes, xs;
3091 TCGv_i64 tcg_addr, tcg_rn;
3092
3093 switch (scale) {
3094 case 3:
3095 if (!is_load || S) {
3096 unallocated_encoding(s);
3097 return;
3098 }
3099 scale = size;
3100 replicate = true;
3101 break;
3102 case 0:
3103 break;
3104 case 1:
3105 if (extract32(size, 0, 1)) {
3106 unallocated_encoding(s);
3107 return;
3108 }
3109 index >>= 1;
3110 break;
3111 case 2:
3112 if (extract32(size, 1, 1)) {
3113 unallocated_encoding(s);
3114 return;
3115 }
3116 if (!extract32(size, 0, 1)) {
3117 index >>= 2;
3118 } else {
3119 if (S) {
3120 unallocated_encoding(s);
3121 return;
3122 }
3123 index >>= 3;
3124 scale = 3;
3125 }
3126 break;
3127 default:
3128 g_assert_not_reached();
3129 }
3130
3131 if (!fp_access_check(s)) {
3132 return;
3133 }
3134
3135 ebytes = 1 << scale;
3136
3137 if (rn == 31) {
3138 gen_check_sp_alignment(s);
3139 }
3140
3141 tcg_rn = cpu_reg_sp(s, rn);
3142 tcg_addr = tcg_temp_new_i64();
3143 tcg_gen_mov_i64(tcg_addr, tcg_rn);
3144
3145 for (xs = 0; xs < selem; xs++) {
3146 if (replicate) {
3147 /* Load and replicate to all elements */
3148 uint64_t mulconst;
3149 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
3150
3151 tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr,
3152 get_mem_index(s), s->be_data + scale);
3153 switch (scale) {
3154 case 0:
3155 mulconst = 0x0101010101010101ULL;
3156 break;
3157 case 1:
3158 mulconst = 0x0001000100010001ULL;
3159 break;
3160 case 2:
3161 mulconst = 0x0000000100000001ULL;
3162 break;
3163 case 3:
3164 mulconst = 0;
3165 break;
3166 default:
3167 g_assert_not_reached();
3168 }
3169 if (mulconst) {
3170 tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst);
3171 }
3172 write_vec_element(s, tcg_tmp, rt, 0, MO_64);
3173 if (is_q) {
3174 write_vec_element(s, tcg_tmp, rt, 1, MO_64);
3175 }
3176 tcg_temp_free_i64(tcg_tmp);
3177 clear_vec_high(s, is_q, rt);
3178 } else {
3179 /* Load/store one element per register */
3180 if (is_load) {
3181 do_vec_ld(s, rt, index, tcg_addr, scale);
3182 } else {
3183 do_vec_st(s, rt, index, tcg_addr, scale);
3184 }
3185 }
3186 tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes);
3187 rt = (rt + 1) % 32;
3188 }
3189
3190 if (is_postidx) {
3191 int rm = extract32(insn, 16, 5);
3192 if (rm == 31) {
3193 tcg_gen_mov_i64(tcg_rn, tcg_addr);
3194 } else {
3195 tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm));
3196 }
3197 }
3198 tcg_temp_free_i64(tcg_addr);
3199 }
3200
3201 /* Loads and stores */
3202 static void disas_ldst(DisasContext *s, uint32_t insn)
3203 {
3204 switch (extract32(insn, 24, 6)) {
3205 case 0x08: /* Load/store exclusive */
3206 disas_ldst_excl(s, insn);
3207 break;
3208 case 0x18: case 0x1c: /* Load register (literal) */
3209 disas_ld_lit(s, insn);
3210 break;
3211 case 0x28: case 0x29:
3212 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3213 disas_ldst_pair(s, insn);
3214 break;
3215 case 0x38: case 0x39:
3216 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3217 disas_ldst_reg(s, insn);
3218 break;
3219 case 0x0c: /* AdvSIMD load/store multiple structures */
3220 disas_ldst_multiple_struct(s, insn);
3221 break;
3222 case 0x0d: /* AdvSIMD load/store single structure */
3223 disas_ldst_single_struct(s, insn);
3224 break;
3225 default:
3226 unallocated_encoding(s);
3227 break;
3228 }
3229 }
3230
3231 /* PC-rel. addressing
3232 * 31 30 29 28 24 23 5 4 0
3233 * +----+-------+-----------+-------------------+------+
3234 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3235 * +----+-------+-----------+-------------------+------+
3236 */
3237 static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
3238 {
3239 unsigned int page, rd;
3240 uint64_t base;
3241 uint64_t offset;
3242
3243 page = extract32(insn, 31, 1);
3244 /* SignExtend(immhi:immlo) -> offset */
3245 offset = sextract64(insn, 5, 19);
3246 offset = offset << 2 | extract32(insn, 29, 2);
3247 rd = extract32(insn, 0, 5);
3248 base = s->pc - 4;
3249
3250 if (page) {
3251 /* ADRP (page based) */
3252 base &= ~0xfff;
3253 offset <<= 12;
3254 }
3255
3256 tcg_gen_movi_i64(cpu_reg(s, rd), base + offset);
3257 }
3258
3259 /*
3260 * Add/subtract (immediate)
3261 *
3262 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3263 * +--+--+--+-----------+-----+-------------+-----+-----+
3264 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3265 * +--+--+--+-----------+-----+-------------+-----+-----+
3266 *
3267 * sf: 0 -> 32bit, 1 -> 64bit
3268 * op: 0 -> add , 1 -> sub
3269 * S: 1 -> set flags
3270 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3271 */
3272 static void disas_add_sub_imm(DisasContext *s, uint32_t insn)
3273 {
3274 int rd = extract32(insn, 0, 5);
3275 int rn = extract32(insn, 5, 5);
3276 uint64_t imm = extract32(insn, 10, 12);
3277 int shift = extract32(insn, 22, 2);
3278 bool setflags = extract32(insn, 29, 1);
3279 bool sub_op = extract32(insn, 30, 1);
3280 bool is_64bit = extract32(insn, 31, 1);
3281
3282 TCGv_i64 tcg_rn = cpu_reg_sp(s, rn);
3283 TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd);
3284 TCGv_i64 tcg_result;
3285
3286 switch (shift) {
3287 case 0x0:
3288 break;
3289 case 0x1:
3290 imm <<= 12;
3291 break;
3292 default:
3293 unallocated_encoding(s);
3294 return;
3295 }
3296
3297 tcg_result = tcg_temp_new_i64();
3298 if (!setflags) {
3299 if (sub_op) {
3300 tcg_gen_subi_i64(tcg_result, tcg_rn, imm);
3301 } else {
3302 tcg_gen_addi_i64(tcg_result, tcg_rn, imm);
3303 }
3304 } else {
3305 TCGv_i64 tcg_imm = tcg_const_i64(imm);
3306 if (sub_op) {
3307 gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
3308 } else {
3309 gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm);
3310 }
3311 tcg_temp_free_i64(tcg_imm);
3312 }
3313
3314 if (is_64bit) {
3315 tcg_gen_mov_i64(tcg_rd, tcg_result);
3316 } else {
3317 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3318 }
3319
3320 tcg_temp_free_i64(tcg_result);
3321 }
3322
3323 /* The input should be a value in the bottom e bits (with higher
3324 * bits zero); returns that value replicated into every element
3325 * of size e in a 64 bit integer.
3326 */
3327 static uint64_t bitfield_replicate(uint64_t mask, unsigned int e)
3328 {
3329 assert(e != 0);
3330 while (e < 64) {
3331 mask |= mask << e;
3332 e *= 2;
3333 }
3334 return mask;
3335 }
3336
3337 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3338 static inline uint64_t bitmask64(unsigned int length)
3339 {
3340 assert(length > 0 && length <= 64);
3341 return ~0ULL >> (64 - length);
3342 }
3343
3344 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3345 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3346 * value (ie should cause a guest UNDEF exception), and true if they are
3347 * valid, in which case the decoded bit pattern is written to result.
3348 */
3349 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
3350 unsigned int imms, unsigned int immr)
3351 {
3352 uint64_t mask;
3353 unsigned e, levels, s, r;
3354 int len;
3355
3356 assert(immn < 2 && imms < 64 && immr < 64);
3357
3358 /* The bit patterns we create here are 64 bit patterns which
3359 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3360 * 64 bits each. Each element contains the same value: a run
3361 * of between 1 and e-1 non-zero bits, rotated within the
3362 * element by between 0 and e-1 bits.
3363 *
3364 * The element size and run length are encoded into immn (1 bit)
3365 * and imms (6 bits) as follows:
3366 * 64 bit elements: immn = 1, imms = <length of run - 1>
3367 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3368 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3369 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3370 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3371 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3372 * Notice that immn = 0, imms = 11111x is the only combination
3373 * not covered by one of the above options; this is reserved.
3374 * Further, <length of run - 1> all-ones is a reserved pattern.
3375 *
3376 * In all cases the rotation is by immr % e (and immr is 6 bits).
3377 */
3378
3379 /* First determine the element size */
3380 len = 31 - clz32((immn << 6) | (~imms & 0x3f));
3381 if (len < 1) {
3382 /* This is the immn == 0, imms == 0x11111x case */
3383 return false;
3384 }
3385 e = 1 << len;
3386
3387 levels = e - 1;
3388 s = imms & levels;
3389 r = immr & levels;
3390
3391 if (s == levels) {
3392 /* <length of run - 1> mustn't be all-ones. */
3393 return false;
3394 }
3395
3396 /* Create the value of one element: s+1 set bits rotated
3397 * by r within the element (which is e bits wide)...
3398 */
3399 mask = bitmask64(s + 1);
3400 if (r) {
3401 mask = (mask >> r) | (mask << (e - r));
3402 mask &= bitmask64(e);
3403 }
3404 /* ...then replicate the element over the whole 64 bit value */
3405 mask = bitfield_replicate(mask, e);
3406 *result = mask;
3407 return true;
3408 }
3409
3410 /* Logical (immediate)
3411 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3412 * +----+-----+-------------+---+------+------+------+------+
3413 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3414 * +----+-----+-------------+---+------+------+------+------+
3415 */
3416 static void disas_logic_imm(DisasContext *s, uint32_t insn)
3417 {
3418 unsigned int sf, opc, is_n, immr, imms, rn, rd;
3419 TCGv_i64 tcg_rd, tcg_rn;
3420 uint64_t wmask;
3421 bool is_and = false;
3422
3423 sf = extract32(insn, 31, 1);
3424 opc = extract32(insn, 29, 2);
3425 is_n = extract32(insn, 22, 1);
3426 immr = extract32(insn, 16, 6);
3427 imms = extract32(insn, 10, 6);
3428 rn = extract32(insn, 5, 5);
3429 rd = extract32(insn, 0, 5);
3430
3431 if (!sf && is_n) {
3432 unallocated_encoding(s);
3433 return;
3434 }
3435
3436 if (opc == 0x3) { /* ANDS */
3437 tcg_rd = cpu_reg(s, rd);
3438 } else {
3439 tcg_rd = cpu_reg_sp(s, rd);
3440 }
3441 tcg_rn = cpu_reg(s, rn);
3442
3443 if (!logic_imm_decode_wmask(&wmask, is_n, imms, immr)) {
3444 /* some immediate field values are reserved */
3445 unallocated_encoding(s);
3446 return;
3447 }
3448
3449 if (!sf) {
3450 wmask &= 0xffffffff;
3451 }
3452
3453 switch (opc) {
3454 case 0x3: /* ANDS */
3455 case 0x0: /* AND */
3456 tcg_gen_andi_i64(tcg_rd, tcg_rn, wmask);
3457 is_and = true;
3458 break;
3459 case 0x1: /* ORR */
3460 tcg_gen_ori_i64(tcg_rd, tcg_rn, wmask);
3461 break;
3462 case 0x2: /* EOR */
3463 tcg_gen_xori_i64(tcg_rd, tcg_rn, wmask);
3464 break;
3465 default:
3466 assert(FALSE); /* must handle all above */
3467 break;
3468 }
3469
3470 if (!sf && !is_and) {
3471 /* zero extend final result; we know we can skip this for AND
3472 * since the immediate had the high 32 bits clear.
3473 */
3474 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3475 }
3476
3477 if (opc == 3) { /* ANDS */
3478 gen_logic_CC(sf, tcg_rd);
3479 }
3480 }
3481
3482 /*
3483 * Move wide (immediate)
3484 *
3485 * 31 30 29 28 23 22 21 20 5 4 0
3486 * +--+-----+-------------+-----+----------------+------+
3487 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3488 * +--+-----+-------------+-----+----------------+------+
3489 *
3490 * sf: 0 -> 32 bit, 1 -> 64 bit
3491 * opc: 00 -> N, 10 -> Z, 11 -> K
3492 * hw: shift/16 (0,16, and sf only 32, 48)
3493 */
3494 static void disas_movw_imm(DisasContext *s, uint32_t insn)
3495 {
3496 int rd = extract32(insn, 0, 5);
3497 uint64_t imm = extract32(insn, 5, 16);
3498 int sf = extract32(insn, 31, 1);
3499 int opc = extract32(insn, 29, 2);
3500 int pos = extract32(insn, 21, 2) << 4;
3501 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3502 TCGv_i64 tcg_imm;
3503
3504 if (!sf && (pos >= 32)) {
3505 unallocated_encoding(s);
3506 return;
3507 }
3508
3509 switch (opc) {
3510 case 0: /* MOVN */
3511 case 2: /* MOVZ */
3512 imm <<= pos;
3513 if (opc == 0) {
3514 imm = ~imm;
3515 }
3516 if (!sf) {
3517 imm &= 0xffffffffu;
3518 }
3519 tcg_gen_movi_i64(tcg_rd, imm);
3520 break;
3521 case 3: /* MOVK */
3522 tcg_imm = tcg_const_i64(imm);
3523 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16);
3524 tcg_temp_free_i64(tcg_imm);
3525 if (!sf) {
3526 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3527 }
3528 break;
3529 default:
3530 unallocated_encoding(s);
3531 break;
3532 }
3533 }
3534
3535 /* Bitfield
3536 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3537 * +----+-----+-------------+---+------+------+------+------+
3538 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3539 * +----+-----+-------------+---+------+------+------+------+
3540 */
3541 static void disas_bitfield(DisasContext *s, uint32_t insn)
3542 {
3543 unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
3544 TCGv_i64 tcg_rd, tcg_tmp;
3545
3546 sf = extract32(insn, 31, 1);
3547 opc = extract32(insn, 29, 2);
3548 n = extract32(insn, 22, 1);
3549 ri = extract32(insn, 16, 6);
3550 si = extract32(insn, 10, 6);
3551 rn = extract32(insn, 5, 5);
3552 rd = extract32(insn, 0, 5);
3553 bitsize = sf ? 64 : 32;
3554
3555 if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
3556 unallocated_encoding(s);
3557 return;
3558 }
3559
3560 tcg_rd = cpu_reg(s, rd);
3561
3562 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3563 to be smaller than bitsize, we'll never reference data outside the
3564 low 32-bits anyway. */
3565 tcg_tmp = read_cpu_reg(s, rn, 1);
3566
3567 /* Recognize simple(r) extractions. */
3568 if (si >= ri) {
3569 /* Wd<s-r:0> = Wn<s:r> */
3570 len = (si - ri) + 1;
3571 if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3572 tcg_gen_sextract_i64(tcg_rd, tcg_tmp, ri, len);
3573 goto done;
3574 } else if (opc == 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3575 tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
3576 return;
3577 }
3578 /* opc == 1, BXFIL fall through to deposit */
3579 tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
3580 pos = 0;
3581 } else {
3582 /* Handle the ri > si case with a deposit
3583 * Wd<32+s-r,32-r> = Wn<s:0>
3584 */
3585 len = si + 1;
3586 pos = (bitsize - ri) & (bitsize - 1);
3587 }
3588
3589 if (opc == 0 && len < ri) {
3590 /* SBFM: sign extend the destination field from len to fill
3591 the balance of the word. Let the deposit below insert all
3592 of those sign bits. */
3593 tcg_gen_sextract_i64(tcg_tmp, tcg_tmp, 0, len);
3594 len = ri;
3595 }
3596
3597 if (opc == 1) { /* BFM, BXFIL */
3598 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
3599 } else {
3600 /* SBFM or UBFM: We start with zero, and we haven't modified
3601 any bits outside bitsize, therefore the zero-extension
3602 below is unneeded. */
3603 tcg_gen_deposit_z_i64(tcg_rd, tcg_tmp, pos, len);
3604 return;
3605 }
3606
3607 done:
3608 if (!sf) { /* zero extend final result */
3609 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3610 }
3611 }
3612
3613 /* Extract
3614 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3615 * +----+------+-------------+---+----+------+--------+------+------+
3616 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3617 * +----+------+-------------+---+----+------+--------+------+------+
3618 */
3619 static void disas_extract(DisasContext *s, uint32_t insn)
3620 {
3621 unsigned int sf, n, rm, imm, rn, rd, bitsize, op21, op0;
3622
3623 sf = extract32(insn, 31, 1);
3624 n = extract32(insn, 22, 1);
3625 rm = extract32(insn, 16, 5);
3626 imm = extract32(insn, 10, 6);
3627 rn = extract32(insn, 5, 5);
3628 rd = extract32(insn, 0, 5);
3629 op21 = extract32(insn, 29, 2);
3630 op0 = extract32(insn, 21, 1);
3631 bitsize = sf ? 64 : 32;
3632
3633 if (sf != n || op21 || op0 || imm >= bitsize) {
3634 unallocated_encoding(s);
3635 } else {
3636 TCGv_i64 tcg_rd, tcg_rm, tcg_rn;
3637
3638 tcg_rd = cpu_reg(s, rd);
3639
3640 if (unlikely(imm == 0)) {
3641 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3642 * so an extract from bit 0 is a special case.
3643 */
3644 if (sf) {
3645 tcg_gen_mov_i64(tcg_rd, cpu_reg(s, rm));
3646 } else {
3647 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
3648 }
3649 } else if (rm == rn) { /* ROR */
3650 tcg_rm = cpu_reg(s, rm);
3651 if (sf) {
3652 tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
3653 } else {
3654 TCGv_i32 tmp = tcg_temp_new_i32();
3655 tcg_gen_extrl_i64_i32(tmp, tcg_rm);
3656 tcg_gen_rotri_i32(tmp, tmp, imm);
3657 tcg_gen_extu_i32_i64(tcg_rd, tmp);
3658 tcg_temp_free_i32(tmp);
3659 }
3660 } else {
3661 tcg_rm = read_cpu_reg(s, rm, sf);
3662 tcg_rn = read_cpu_reg(s, rn, sf);
3663 tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
3664 tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
3665 tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
3666 if (!sf) {
3667 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3668 }
3669 }
3670 }
3671 }
3672
3673 /* Data processing - immediate */
3674 static void disas_data_proc_imm(DisasContext *s, uint32_t insn)
3675 {
3676 switch (extract32(insn, 23, 6)) {
3677 case 0x20: case 0x21: /* PC-rel. addressing */
3678 disas_pc_rel_adr(s, insn);
3679 break;
3680 case 0x22: case 0x23: /* Add/subtract (immediate) */
3681 disas_add_sub_imm(s, insn);
3682 break;
3683 case 0x24: /* Logical (immediate) */
3684 disas_logic_imm(s, insn);
3685 break;
3686 case 0x25: /* Move wide (immediate) */
3687 disas_movw_imm(s, insn);
3688 break;
3689 case 0x26: /* Bitfield */
3690 disas_bitfield(s, insn);
3691 break;
3692 case 0x27: /* Extract */
3693 disas_extract(s, insn);
3694 break;
3695 default:
3696 unallocated_encoding(s);
3697 break;
3698 }
3699 }
3700
3701 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
3702 * Note that it is the caller's responsibility to ensure that the
3703 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
3704 * mandated semantics for out of range shifts.
3705 */
3706 static void shift_reg(TCGv_i64 dst, TCGv_i64 src, int sf,
3707 enum a64_shift_type shift_type, TCGv_i64 shift_amount)
3708 {
3709 switch (shift_type) {
3710 case A64_SHIFT_TYPE_LSL:
3711 tcg_gen_shl_i64(dst, src, shift_amount);
3712 break;
3713 case A64_SHIFT_TYPE_LSR:
3714 tcg_gen_shr_i64(dst, src, shift_amount);
3715 break;
3716 case A64_SHIFT_TYPE_ASR:
3717 if (!sf) {
3718 tcg_gen_ext32s_i64(dst, src);
3719 }
3720 tcg_gen_sar_i64(dst, sf ? src : dst, shift_amount);
3721 break;
3722 case A64_SHIFT_TYPE_ROR:
3723 if (sf) {
3724 tcg_gen_rotr_i64(dst, src, shift_amount);
3725 } else {
3726 TCGv_i32 t0, t1;
3727 t0 = tcg_temp_new_i32();
3728 t1 = tcg_temp_new_i32();
3729 tcg_gen_extrl_i64_i32(t0, src);
3730 tcg_gen_extrl_i64_i32(t1, shift_amount);
3731 tcg_gen_rotr_i32(t0, t0, t1);
3732 tcg_gen_extu_i32_i64(dst, t0);
3733 tcg_temp_free_i32(t0);
3734 tcg_temp_free_i32(t1);
3735 }
3736 break;
3737 default:
3738 assert(FALSE); /* all shift types should be handled */
3739 break;
3740 }
3741
3742 if (!sf) { /* zero extend final result */
3743 tcg_gen_ext32u_i64(dst, dst);
3744 }
3745 }
3746
3747 /* Shift a TCGv src by immediate, put result in dst.
3748 * The shift amount must be in range (this should always be true as the
3749 * relevant instructions will UNDEF on bad shift immediates).
3750 */
3751 static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src, int sf,
3752 enum a64_shift_type shift_type, unsigned int shift_i)
3753 {
3754 assert(shift_i < (sf ? 64 : 32));
3755
3756 if (shift_i == 0) {
3757 tcg_gen_mov_i64(dst, src);
3758 } else {
3759 TCGv_i64 shift_const;
3760
3761 shift_const = tcg_const_i64(shift_i);
3762 shift_reg(dst, src, sf, shift_type, shift_const);
3763 tcg_temp_free_i64(shift_const);
3764 }
3765 }
3766
3767 /* Logical (shifted register)
3768 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3769 * +----+-----+-----------+-------+---+------+--------+------+------+
3770 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
3771 * +----+-----+-----------+-------+---+------+--------+------+------+
3772 */
3773 static void disas_logic_reg(DisasContext *s, uint32_t insn)
3774 {
3775 TCGv_i64 tcg_rd, tcg_rn, tcg_rm;
3776 unsigned int sf, opc, shift_type, invert, rm, shift_amount, rn, rd;
3777
3778 sf = extract32(insn, 31, 1);
3779 opc = extract32(insn, 29, 2);
3780 shift_type = extract32(insn, 22, 2);
3781 invert = extract32(insn, 21, 1);
3782 rm = extract32(insn, 16, 5);
3783 shift_amount = extract32(insn, 10, 6);
3784 rn = extract32(insn, 5, 5);
3785 rd = extract32(insn, 0, 5);
3786
3787 if (!sf && (shift_amount & (1 << 5))) {
3788 unallocated_encoding(s);
3789 return;
3790 }
3791
3792 tcg_rd = cpu_reg(s, rd);
3793
3794 if (opc == 1 && shift_amount == 0 && shift_type == 0 && rn == 31) {
3795 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
3796 * register-register MOV and MVN, so it is worth special casing.
3797 */
3798 tcg_rm = cpu_reg(s, rm);
3799 if (invert) {
3800 tcg_gen_not_i64(tcg_rd, tcg_rm);
3801 if (!sf) {
3802 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3803 }
3804 } else {
3805 if (sf) {
3806 tcg_gen_mov_i64(tcg_rd, tcg_rm);
3807 } else {
3808 tcg_gen_ext32u_i64(tcg_rd, tcg_rm);
3809 }
3810 }
3811 return;
3812 }
3813
3814 tcg_rm = read_cpu_reg(s, rm, sf);
3815
3816 if (shift_amount) {
3817 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, shift_amount);
3818 }
3819
3820 tcg_rn = cpu_reg(s, rn);
3821
3822 switch (opc | (invert << 2)) {
3823 case 0: /* AND */
3824 case 3: /* ANDS */
3825 tcg_gen_and_i64(tcg_rd, tcg_rn, tcg_rm);
3826 break;
3827 case 1: /* ORR */
3828 tcg_gen_or_i64(tcg_rd, tcg_rn, tcg_rm);
3829 break;
3830 case 2: /* EOR */
3831 tcg_gen_xor_i64(tcg_rd, tcg_rn, tcg_rm);
3832 break;
3833 case 4: /* BIC */
3834 case 7: /* BICS */
3835 tcg_gen_andc_i64(tcg_rd, tcg_rn, tcg_rm);
3836 break;
3837 case 5: /* ORN */
3838 tcg_gen_orc_i64(tcg_rd, tcg_rn, tcg_rm);
3839 break;
3840 case 6: /* EON */
3841 tcg_gen_eqv_i64(tcg_rd, tcg_rn, tcg_rm);
3842 break;
3843 default:
3844 assert(FALSE);
3845 break;
3846 }
3847
3848 if (!sf) {
3849 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
3850 }
3851
3852 if (opc == 3) {
3853 gen_logic_CC(sf, tcg_rd);
3854 }
3855 }
3856
3857 /*
3858 * Add/subtract (extended register)
3859 *
3860 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
3861 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3862 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
3863 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
3864 *
3865 * sf: 0 -> 32bit, 1 -> 64bit
3866 * op: 0 -> add , 1 -> sub
3867 * S: 1 -> set flags
3868 * opt: 00
3869 * option: extension type (see DecodeRegExtend)
3870 * imm3: optional shift to Rm
3871 *
3872 * Rd = Rn + LSL(extend(Rm), amount)
3873 */
3874 static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn)
3875 {
3876 int rd = extract32(insn, 0, 5);
3877 int rn = extract32(insn, 5, 5);
3878 int imm3 = extract32(insn, 10, 3);
3879 int option = extract32(insn, 13, 3);
3880 int rm = extract32(insn, 16, 5);
3881 bool setflags = extract32(insn, 29, 1);
3882 bool sub_op = extract32(insn, 30, 1);
3883 bool sf = extract32(insn, 31, 1);
3884
3885 TCGv_i64 tcg_rm, tcg_rn; /* temps */
3886 TCGv_i64 tcg_rd;
3887 TCGv_i64 tcg_result;
3888
3889 if (imm3 > 4) {
3890 unallocated_encoding(s);
3891 return;
3892 }
3893
3894 /* non-flag setting ops may use SP */
3895 if (!setflags) {
3896 tcg_rd = cpu_reg_sp(s, rd);
3897 } else {
3898 tcg_rd = cpu_reg(s, rd);
3899 }
3900 tcg_rn = read_cpu_reg_sp(s, rn, sf);
3901
3902 tcg_rm = read_cpu_reg(s, rm, sf);
3903 ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);
3904
3905 tcg_result = tcg_temp_new_i64();
3906
3907 if (!setflags) {
3908 if (sub_op) {
3909 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3910 } else {
3911 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3912 }
3913 } else {
3914 if (sub_op) {
3915 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3916 } else {
3917 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3918 }
3919 }
3920
3921 if (sf) {
3922 tcg_gen_mov_i64(tcg_rd, tcg_result);
3923 } else {
3924 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3925 }
3926
3927 tcg_temp_free_i64(tcg_result);
3928 }
3929
3930 /*
3931 * Add/subtract (shifted register)
3932 *
3933 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
3934 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3935 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
3936 * +--+--+--+-----------+-----+--+-------+---------+------+------+
3937 *
3938 * sf: 0 -> 32bit, 1 -> 64bit
3939 * op: 0 -> add , 1 -> sub
3940 * S: 1 -> set flags
3941 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
3942 * imm6: Shift amount to apply to Rm before the add/sub
3943 */
3944 static void disas_add_sub_reg(DisasContext *s, uint32_t insn)
3945 {
3946 int rd = extract32(insn, 0, 5);
3947 int rn = extract32(insn, 5, 5);
3948 int imm6 = extract32(insn, 10, 6);
3949 int rm = extract32(insn, 16, 5);
3950 int shift_type = extract32(insn, 22, 2);
3951 bool setflags = extract32(insn, 29, 1);
3952 bool sub_op = extract32(insn, 30, 1);
3953 bool sf = extract32(insn, 31, 1);
3954
3955 TCGv_i64 tcg_rd = cpu_reg(s, rd);
3956 TCGv_i64 tcg_rn, tcg_rm;
3957 TCGv_i64 tcg_result;
3958
3959 if ((shift_type == 3) || (!sf && (imm6 > 31))) {
3960 unallocated_encoding(s);
3961 return;
3962 }
3963
3964 tcg_rn = read_cpu_reg(s, rn, sf);
3965 tcg_rm = read_cpu_reg(s, rm, sf);
3966
3967 shift_reg_imm(tcg_rm, tcg_rm, sf, shift_type, imm6);
3968
3969 tcg_result = tcg_temp_new_i64();
3970
3971 if (!setflags) {
3972 if (sub_op) {
3973 tcg_gen_sub_i64(tcg_result, tcg_rn, tcg_rm);
3974 } else {
3975 tcg_gen_add_i64(tcg_result, tcg_rn, tcg_rm);
3976 }
3977 } else {
3978 if (sub_op) {
3979 gen_sub_CC(sf, tcg_result, tcg_rn, tcg_rm);
3980 } else {
3981 gen_add_CC(sf, tcg_result, tcg_rn, tcg_rm);
3982 }
3983 }
3984
3985 if (sf) {
3986 tcg_gen_mov_i64(tcg_rd, tcg_result);
3987 } else {
3988 tcg_gen_ext32u_i64(tcg_rd, tcg_result);
3989 }
3990
3991 tcg_temp_free_i64(tcg_result);
3992 }
3993
3994 /* Data-processing (3 source)
3995 *
3996 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
3997 * +--+------+-----------+------+------+----+------+------+------+
3998 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
3999 * +--+------+-----------+------+------+----+------+------+------+
4000 */
4001 static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
4002 {
4003 int rd = extract32(insn, 0, 5);
4004 int rn = extract32(insn, 5, 5);
4005 int ra = extract32(insn, 10, 5);
4006 int rm = extract32(insn, 16, 5);
4007 int op_id = (extract32(insn, 29, 3) << 4) |
4008 (extract32(insn, 21, 3) << 1) |
4009 extract32(insn, 15, 1);
4010 bool sf = extract32(insn, 31, 1);
4011 bool is_sub = extract32(op_id, 0, 1);
4012 bool is_high = extract32(op_id, 2, 1);
4013 bool is_signed = false;
4014 TCGv_i64 tcg_op1;
4015 TCGv_i64 tcg_op2;
4016 TCGv_i64 tcg_tmp;
4017
4018 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4019 switch (op_id) {
4020 case 0x42: /* SMADDL */
4021 case 0x43: /* SMSUBL */
4022 case 0x44: /* SMULH */
4023 is_signed = true;
4024 break;
4025 case 0x0: /* MADD (32bit) */
4026 case 0x1: /* MSUB (32bit) */
4027 case 0x40: /* MADD (64bit) */
4028 case 0x41: /* MSUB (64bit) */
4029 case 0x4a: /* UMADDL */
4030 case 0x4b: /* UMSUBL */
4031 case 0x4c: /* UMULH */
4032 break;
4033 default:
4034 unallocated_encoding(s);
4035 return;
4036 }
4037
4038 if (is_high) {
4039 TCGv_i64 low_bits = tcg_temp_new_i64(); /* low bits discarded */
4040 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4041 TCGv_i64 tcg_rn = cpu_reg(s, rn);
4042 TCGv_i64 tcg_rm = cpu_reg(s, rm);
4043
4044 if (is_signed) {
4045 tcg_gen_muls2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
4046 } else {
4047 tcg_gen_mulu2_i64(low_bits, tcg_rd, tcg_rn, tcg_rm);
4048 }
4049
4050 tcg_temp_free_i64(low_bits);
4051 return;
4052 }
4053
4054 tcg_op1 = tcg_temp_new_i64();
4055 tcg_op2 = tcg_temp_new_i64();
4056 tcg_tmp = tcg_temp_new_i64();
4057
4058 if (op_id < 0x42) {
4059 tcg_gen_mov_i64(tcg_op1, cpu_reg(s, rn));
4060 tcg_gen_mov_i64(tcg_op2, cpu_reg(s, rm));
4061 } else {
4062 if (is_signed) {
4063 tcg_gen_ext32s_i64(tcg_op1, cpu_reg(s, rn));
4064 tcg_gen_ext32s_i64(tcg_op2, cpu_reg(s, rm));
4065 } else {
4066 tcg_gen_ext32u_i64(tcg_op1, cpu_reg(s, rn));
4067 tcg_gen_ext32u_i64(tcg_op2, cpu_reg(s, rm));
4068 }
4069 }
4070
4071 if (ra == 31 && !is_sub) {
4072 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4073 tcg_gen_mul_i64(cpu_reg(s, rd), tcg_op1, tcg_op2);
4074 } else {
4075 tcg_gen_mul_i64(tcg_tmp, tcg_op1, tcg_op2);
4076 if (is_sub) {
4077 tcg_gen_sub_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
4078 } else {
4079 tcg_gen_add_i64(cpu_reg(s, rd), cpu_reg(s, ra), tcg_tmp);
4080 }
4081 }
4082
4083 if (!sf) {
4084 tcg_gen_ext32u_i64(cpu_reg(s, rd), cpu_reg(s, rd));
4085 }
4086
4087 tcg_temp_free_i64(tcg_op1);
4088 tcg_temp_free_i64(tcg_op2);
4089 tcg_temp_free_i64(tcg_tmp);
4090 }
4091
4092 /* Add/subtract (with carry)
4093 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4094 * +--+--+--+------------------------+------+---------+------+-----+
4095 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4096 * +--+--+--+------------------------+------+---------+------+-----+
4097 * [000000]
4098 */
4099
4100 static void disas_adc_sbc(DisasContext *s, uint32_t insn)
4101 {
4102 unsigned int sf, op, setflags, rm, rn, rd;
4103 TCGv_i64 tcg_y, tcg_rn, tcg_rd;
4104
4105 if (extract32(insn, 10, 6) != 0) {
4106 unallocated_encoding(s);
4107 return;
4108 }
4109
4110 sf = extract32(insn, 31, 1);
4111 op = extract32(insn, 30, 1);
4112 setflags = extract32(insn, 29, 1);
4113 rm = extract32(insn, 16, 5);
4114 rn = extract32(insn, 5, 5);
4115 rd = extract32(insn, 0, 5);
4116
4117 tcg_rd = cpu_reg(s, rd);
4118 tcg_rn = cpu_reg(s, rn);
4119
4120 if (op) {
4121 tcg_y = new_tmp_a64(s);
4122 tcg_gen_not_i64(tcg_y, cpu_reg(s, rm));
4123 } else {
4124 tcg_y = cpu_reg(s, rm);
4125 }
4126
4127 if (setflags) {
4128 gen_adc_CC(sf, tcg_rd, tcg_rn, tcg_y);
4129 } else {
4130 gen_adc(sf, tcg_rd, tcg_rn, tcg_y);
4131 }
4132 }
4133
4134 /* Conditional compare (immediate / register)
4135 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4136 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4137 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4138 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4139 * [1] y [0] [0]
4140 */
4141 static void disas_cc(DisasContext *s, uint32_t insn)
4142 {
4143 unsigned int sf, op, y, cond, rn, nzcv, is_imm;
4144 TCGv_i32 tcg_t0, tcg_t1, tcg_t2;
4145 TCGv_i64 tcg_tmp, tcg_y, tcg_rn;
4146 DisasCompare c;
4147
4148 if (!extract32(insn, 29, 1)) {
4149 unallocated_encoding(s);
4150 return;
4151 }
4152 if (insn & (1 << 10 | 1 << 4)) {
4153 unallocated_encoding(s);
4154 return;
4155 }
4156 sf = extract32(insn, 31, 1);
4157 op = extract32(insn, 30, 1);
4158 is_imm = extract32(insn, 11, 1);
4159 y = extract32(insn, 16, 5); /* y = rm (reg) or imm5 (imm) */
4160 cond = extract32(insn, 12, 4);
4161 rn = extract32(insn, 5, 5);
4162 nzcv = extract32(insn, 0, 4);
4163
4164 /* Set T0 = !COND. */
4165 tcg_t0 = tcg_temp_new_i32();
4166 arm_test_cc(&c, cond);
4167 tcg_gen_setcondi_i32(tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
4168 arm_free_cc(&c);
4169
4170 /* Load the arguments for the new comparison. */
4171 if (is_imm) {
4172 tcg_y = new_tmp_a64(s);
4173 tcg_gen_movi_i64(tcg_y, y);
4174 } else {
4175 tcg_y = cpu_reg(s, y);
4176 }
4177 tcg_rn = cpu_reg(s, rn);
4178
4179 /* Set the flags for the new comparison. */
4180 tcg_tmp = tcg_temp_new_i64();
4181 if (op) {
4182 gen_sub_CC(sf, tcg_tmp, tcg_rn, tcg_y);
4183 } else {
4184 gen_add_CC(sf, tcg_tmp, tcg_rn, tcg_y);
4185 }
4186 tcg_temp_free_i64(tcg_tmp);
4187
4188 /* If COND was false, force the flags to #nzcv. Compute two masks
4189 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4190 * For tcg hosts that support ANDC, we can make do with just T1.
4191 * In either case, allow the tcg optimizer to delete any unused mask.
4192 */
4193 tcg_t1 = tcg_temp_new_i32();
4194 tcg_t2 = tcg_temp_new_i32();
4195 tcg_gen_neg_i32(tcg_t1, tcg_t0);
4196 tcg_gen_subi_i32(tcg_t2, tcg_t0, 1);
4197
4198 if (nzcv & 8) { /* N */
4199 tcg_gen_or_i32(cpu_NF, cpu_NF, tcg_t1);
4200 } else {
4201 if (TCG_TARGET_HAS_andc_i32) {
4202 tcg_gen_andc_i32(cpu_NF, cpu_NF, tcg_t1);
4203 } else {
4204 tcg_gen_and_i32(cpu_NF, cpu_NF, tcg_t2);
4205 }
4206 }
4207 if (nzcv & 4) { /* Z */
4208 if (TCG_TARGET_HAS_andc_i32) {
4209 tcg_gen_andc_i32(cpu_ZF, cpu_ZF, tcg_t1);
4210 } else {
4211 tcg_gen_and_i32(cpu_ZF, cpu_ZF, tcg_t2);
4212 }
4213 } else {
4214 tcg_gen_or_i32(cpu_ZF, cpu_ZF, tcg_t0);
4215 }
4216 if (nzcv & 2) { /* C */
4217 tcg_gen_or_i32(cpu_CF, cpu_CF, tcg_t0);
4218 } else {
4219 if (TCG_TARGET_HAS_andc_i32) {
4220 tcg_gen_andc_i32(cpu_CF, cpu_CF, tcg_t1);
4221 } else {
4222 tcg_gen_and_i32(cpu_CF, cpu_CF, tcg_t2);
4223 }
4224 }
4225 if (nzcv & 1) { /* V */
4226 tcg_gen_or_i32(cpu_VF, cpu_VF, tcg_t1);
4227 } else {
4228 if (TCG_TARGET_HAS_andc_i32) {
4229 tcg_gen_andc_i32(cpu_VF, cpu_VF, tcg_t1);
4230 } else {
4231 tcg_gen_and_i32(cpu_VF, cpu_VF, tcg_t2);
4232 }
4233 }
4234 tcg_temp_free_i32(tcg_t0);
4235 tcg_temp_free_i32(tcg_t1);
4236 tcg_temp_free_i32(tcg_t2);
4237 }
4238
4239 /* Conditional select
4240 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4241 * +----+----+---+-----------------+------+------+-----+------+------+
4242 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4243 * +----+----+---+-----------------+------+------+-----+------+------+
4244 */
4245 static void disas_cond_select(DisasContext *s, uint32_t insn)
4246 {
4247 unsigned int sf, else_inv, rm, cond, else_inc, rn, rd;
4248 TCGv_i64 tcg_rd, zero;
4249 DisasCompare64 c;
4250
4251 if (extract32(insn, 29, 1) || extract32(insn, 11, 1)) {
4252 /* S == 1 or op2<1> == 1 */
4253 unallocated_encoding(s);
4254 return;
4255 }
4256 sf = extract32(insn, 31, 1);
4257 else_inv = extract32(insn, 30, 1);
4258 rm = extract32(insn, 16, 5);
4259 cond = extract32(insn, 12, 4);
4260 else_inc = extract32(insn, 10, 1);
4261 rn = extract32(insn, 5, 5);
4262 rd = extract32(insn, 0, 5);
4263
4264 tcg_rd = cpu_reg(s, rd);
4265
4266 a64_test_cc(&c, cond);
4267 zero = tcg_const_i64(0);
4268
4269 if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
4270 /* CSET & CSETM. */
4271 tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero);
4272 if (else_inv) {
4273 tcg_gen_neg_i64(tcg_rd, tcg_rd);
4274 }
4275 } else {
4276 TCGv_i64 t_true = cpu_reg(s, rn);
4277 TCGv_i64 t_false = read_cpu_reg(s, rm, 1);
4278 if (else_inv && else_inc) {
4279 tcg_gen_neg_i64(t_false, t_false);
4280 } else if (else_inv) {
4281 tcg_gen_not_i64(t_false, t_false);
4282 } else if (else_inc) {
4283 tcg_gen_addi_i64(t_false, t_false, 1);
4284 }
4285 tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false);
4286 }
4287
4288 tcg_temp_free_i64(zero);
4289 a64_free_cc(&c);
4290
4291 if (!sf) {
4292 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
4293 }
4294 }
4295
4296 static void handle_clz(DisasContext *s, unsigned int sf,
4297 unsigned int rn, unsigned int rd)
4298 {
4299 TCGv_i64 tcg_rd, tcg_rn;
4300 tcg_rd = cpu_reg(s, rd);
4301 tcg_rn = cpu_reg(s, rn);
4302
4303 if (sf) {
4304 tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
4305 } else {
4306 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
4307 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
4308 tcg_gen_clzi_i32(tcg_tmp32, tcg_tmp32, 32);
4309 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
4310 tcg_temp_free_i32(tcg_tmp32);
4311 }
4312 }
4313
4314 static void handle_cls(DisasContext *s, unsigned int sf,
4315 unsigned int rn, unsigned int rd)
4316 {
4317 TCGv_i64 tcg_rd, tcg_rn;
4318 tcg_rd = cpu_reg(s, rd);
4319 tcg_rn = cpu_reg(s, rn);
4320
4321 if (sf) {
4322 tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
4323 } else {
4324 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
4325 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
4326 tcg_gen_clrsb_i32(tcg_tmp32, tcg_tmp32);
4327 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
4328 tcg_temp_free_i32(tcg_tmp32);
4329 }
4330 }
4331
4332 static void handle_rbit(DisasContext *s, unsigned int sf,
4333 unsigned int rn, unsigned int rd)
4334 {
4335 TCGv_i64 tcg_rd, tcg_rn;
4336 tcg_rd = cpu_reg(s, rd);
4337 tcg_rn = cpu_reg(s, rn);
4338
4339 if (sf) {
4340 gen_helper_rbit64(tcg_rd, tcg_rn);
4341 } else {
4342 TCGv_i32 tcg_tmp32 = tcg_temp_new_i32();
4343 tcg_gen_extrl_i64_i32(tcg_tmp32, tcg_rn);
4344 gen_helper_rbit(tcg_tmp32, tcg_tmp32);
4345 tcg_gen_extu_i32_i64(tcg_rd, tcg_tmp32);
4346 tcg_temp_free_i32(tcg_tmp32);
4347 }
4348 }
4349
4350 /* REV with sf==1, opcode==3 ("REV64") */
4351 static void handle_rev64(DisasContext *s, unsigned int sf,
4352 unsigned int rn, unsigned int rd)
4353 {
4354 if (!sf) {
4355 unallocated_encoding(s);
4356 return;
4357 }
4358 tcg_gen_bswap64_i64(cpu_reg(s, rd), cpu_reg(s, rn));
4359 }
4360
4361 /* REV with sf==0, opcode==2
4362 * REV32 (sf==1, opcode==2)
4363 */
4364 static void handle_rev32(DisasContext *s, unsigned int sf,
4365 unsigned int rn, unsigned int rd)
4366 {
4367 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4368
4369 if (sf) {
4370 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
4371 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
4372
4373 /* bswap32_i64 requires zero high word */
4374 tcg_gen_ext32u_i64(tcg_tmp, tcg_rn);
4375 tcg_gen_bswap32_i64(tcg_rd, tcg_tmp);
4376 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 32);
4377 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
4378 tcg_gen_concat32_i64(tcg_rd, tcg_rd, tcg_tmp);
4379
4380 tcg_temp_free_i64(tcg_tmp);
4381 } else {
4382 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rn));
4383 tcg_gen_bswap32_i64(tcg_rd, tcg_rd);
4384 }
4385 }
4386
4387 /* REV16 (opcode==1) */
4388 static void handle_rev16(DisasContext *s, unsigned int sf,
4389 unsigned int rn, unsigned int rd)
4390 {
4391 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4392 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
4393 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
4394 TCGv_i64 mask = tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00ff);
4395
4396 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8);
4397 tcg_gen_and_i64(tcg_rd, tcg_rn, mask);
4398 tcg_gen_and_i64(tcg_tmp, tcg_tmp, mask);
4399 tcg_gen_shli_i64(tcg_rd, tcg_rd, 8);
4400 tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp);
4401
4402 tcg_temp_free_i64(mask);
4403 tcg_temp_free_i64(tcg_tmp);
4404 }
4405
4406 /* Data-processing (1 source)
4407 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4408 * +----+---+---+-----------------+---------+--------+------+------+
4409 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4410 * +----+---+---+-----------------+---------+--------+------+------+
4411 */
4412 static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
4413 {
4414 unsigned int sf, opcode, rn, rd;
4415
4416 if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) {
4417 unallocated_encoding(s);
4418 return;
4419 }
4420
4421 sf = extract32(insn, 31, 1);
4422 opcode = extract32(insn, 10, 6);
4423 rn = extract32(insn, 5, 5);
4424 rd = extract32(insn, 0, 5);
4425
4426 switch (opcode) {
4427 case 0: /* RBIT */
4428 handle_rbit(s, sf, rn, rd);
4429 break;
4430 case 1: /* REV16 */
4431 handle_rev16(s, sf, rn, rd);
4432 break;
4433 case 2: /* REV32 */
4434 handle_rev32(s, sf, rn, rd);
4435 break;
4436 case 3: /* REV64 */
4437 handle_rev64(s, sf, rn, rd);
4438 break;
4439 case 4: /* CLZ */
4440 handle_clz(s, sf, rn, rd);
4441 break;
4442 case 5: /* CLS */
4443 handle_cls(s, sf, rn, rd);
4444 break;
4445 }
4446 }
4447
4448 static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
4449 unsigned int rm, unsigned int rn, unsigned int rd)
4450 {
4451 TCGv_i64 tcg_n, tcg_m, tcg_rd;
4452 tcg_rd = cpu_reg(s, rd);
4453
4454 if (!sf && is_signed) {
4455 tcg_n = new_tmp_a64(s);
4456 tcg_m = new_tmp_a64(s);
4457 tcg_gen_ext32s_i64(tcg_n, cpu_reg(s, rn));
4458 tcg_gen_ext32s_i64(tcg_m, cpu_reg(s, rm));
4459 } else {
4460 tcg_n = read_cpu_reg(s, rn, sf);
4461 tcg_m = read_cpu_reg(s, rm, sf);
4462 }
4463
4464 if (is_signed) {
4465 gen_helper_sdiv64(tcg_rd, tcg_n, tcg_m);
4466 } else {
4467 gen_helper_udiv64(tcg_rd, tcg_n, tcg_m);
4468 }
4469
4470 if (!sf) { /* zero extend final result */
4471 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
4472 }
4473 }
4474
4475 /* LSLV, LSRV, ASRV, RORV */
4476 static void handle_shift_reg(DisasContext *s,
4477 enum a64_shift_type shift_type, unsigned int sf,
4478 unsigned int rm, unsigned int rn, unsigned int rd)
4479 {
4480 TCGv_i64 tcg_shift = tcg_temp_new_i64();
4481 TCGv_i64 tcg_rd = cpu_reg(s, rd);
4482 TCGv_i64 tcg_rn = read_cpu_reg(s, rn, sf);
4483
4484 tcg_gen_andi_i64(tcg_shift, cpu_reg(s, rm), sf ? 63 : 31);
4485 shift_reg(tcg_rd, tcg_rn, sf, shift_type, tcg_shift);
4486 tcg_temp_free_i64(tcg_shift);
4487 }
4488
4489 /* CRC32[BHWX], CRC32C[BHWX] */
4490 static void handle_crc32(DisasContext *s,
4491 unsigned int sf, unsigned int sz, bool crc32c,
4492 unsigned int rm, unsigned int rn, unsigned int rd)
4493 {
4494 TCGv_i64 tcg_acc, tcg_val;
4495 TCGv_i32 tcg_bytes;
4496
4497 if (!arm_dc_feature(s, ARM_FEATURE_CRC)
4498 || (sf == 1 && sz != 3)
4499 || (sf == 0 && sz == 3)) {
4500 unallocated_encoding(s);
4501 return;
4502 }
4503
4504 if (sz == 3) {
4505 tcg_val = cpu_reg(s, rm);
4506 } else {
4507 uint64_t mask;
4508 switch (sz) {
4509 case 0:
4510 mask = 0xFF;
4511 break;
4512 case 1:
4513 mask = 0xFFFF;
4514 break;
4515 case 2:
4516 mask = 0xFFFFFFFF;
4517 break;
4518 default:
4519 g_assert_not_reached();
4520 }
4521 tcg_val = new_tmp_a64(s);
4522 tcg_gen_andi_i64(tcg_val, cpu_reg(s, rm), mask);
4523 }
4524
4525 tcg_acc = cpu_reg(s, rn);
4526 tcg_bytes = tcg_const_i32(1 << sz);
4527
4528 if (crc32c) {
4529 gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
4530 } else {
4531 gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes);
4532 }
4533
4534 tcg_temp_free_i32(tcg_bytes);
4535 }
4536
4537 /* Data-processing (2 source)
4538 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4539 * +----+---+---+-----------------+------+--------+------+------+
4540 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
4541 * +----+---+---+-----------------+------+--------+------+------+
4542 */
4543 static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
4544 {
4545 unsigned int sf, rm, opcode, rn, rd;
4546 sf = extract32(insn, 31, 1);
4547 rm = extract32(insn, 16, 5);
4548 opcode = extract32(insn, 10, 6);
4549 rn = extract32(insn, 5, 5);
4550 rd = extract32(insn, 0, 5);
4551
4552 if (extract32(insn, 29, 1)) {
4553 unallocated_encoding(s);
4554 return;
4555 }
4556
4557 switch (opcode) {
4558 case 2: /* UDIV */
4559 handle_div(s, false, sf, rm, rn, rd);
4560 break;
4561 case 3: /* SDIV */
4562 handle_div(s, true, sf, rm, rn, rd);
4563 break;
4564 case 8: /* LSLV */
4565 handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
4566 break;
4567 case 9: /* LSRV */
4568 handle_shift_reg(s, A64_SHIFT_TYPE_LSR, sf, rm, rn, rd);
4569 break;
4570 case 10: /* ASRV */
4571 handle_shift_reg(s, A64_SHIFT_TYPE_ASR, sf, rm, rn, rd);
4572 break;
4573 case 11: /* RORV */
4574 handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
4575 break;
4576 case 16:
4577 case 17:
4578 case 18:
4579 case 19:
4580 case 20:
4581 case 21:
4582 case 22:
4583 case 23: /* CRC32 */
4584 {
4585 int sz = extract32(opcode, 0, 2);
4586 bool crc32c = extract32(opcode, 2, 1);
4587 handle_crc32(s, sf, sz, crc32c, rm, rn, rd);
4588 break;
4589 }
4590 default:
4591 unallocated_encoding(s);
4592 break;
4593 }
4594 }
4595
4596 /* Data processing - register */
4597 static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
4598 {
4599 switch (extract32(insn, 24, 5)) {
4600 case 0x0a: /* Logical (shifted register) */
4601 disas_logic_reg(s, insn);
4602 break;
4603 case 0x0b: /* Add/subtract */
4604 if (insn & (1 << 21)) { /* (extended register) */
4605 disas_add_sub_ext_reg(s, insn);
4606 } else {
4607 disas_add_sub_reg(s, insn);
4608 }
4609 break;
4610 case 0x1b: /* Data-processing (3 source) */
4611 disas_data_proc_3src(s, insn);
4612 break;
4613 case 0x1a:
4614 switch (extract32(insn, 21, 3)) {
4615 case 0x0: /* Add/subtract (with carry) */
4616 disas_adc_sbc(s, insn);
4617 break;
4618 case 0x2: /* Conditional compare */
4619 disas_cc(s, insn); /* both imm and reg forms */
4620 break;
4621 case 0x4: /* Conditional select */
4622 disas_cond_select(s, insn);
4623 break;
4624 case 0x6: /* Data-processing */
4625 if (insn & (1 << 30)) { /* (1 source) */
4626 disas_data_proc_1src(s, insn);
4627 } else { /* (2 source) */
4628 disas_data_proc_2src(s, insn);
4629 }
4630 break;
4631 default:
4632 unallocated_encoding(s);
4633 break;
4634 }
4635 break;
4636 default:
4637 unallocated_encoding(s);
4638 break;
4639 }
4640 }
4641
4642 static void handle_fp_compare(DisasContext *s, int size,
4643 unsigned int rn, unsigned int rm,
4644 bool cmp_with_zero, bool signal_all_nans)
4645 {
4646 TCGv_i64 tcg_flags = tcg_temp_new_i64();
4647 TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
4648
4649 if (size == MO_64) {
4650 TCGv_i64 tcg_vn, tcg_vm;
4651
4652 tcg_vn = read_fp_dreg(s, rn);
4653 if (cmp_with_zero) {
4654 tcg_vm = tcg_const_i64(0);
4655 } else {
4656 tcg_vm = read_fp_dreg(s, rm);
4657 }
4658 if (signal_all_nans) {
4659 gen_helper_vfp_cmped_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4660 } else {
4661 gen_helper_vfp_cmpd_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4662 }
4663 tcg_temp_free_i64(tcg_vn);
4664 tcg_temp_free_i64(tcg_vm);
4665 } else {
4666 TCGv_i32 tcg_vn = tcg_temp_new_i32();
4667 TCGv_i32 tcg_vm = tcg_temp_new_i32();
4668
4669 read_vec_element_i32(s, tcg_vn, rn, 0, size);
4670 if (cmp_with_zero) {
4671 tcg_gen_movi_i32(tcg_vm, 0);
4672 } else {
4673 read_vec_element_i32(s, tcg_vm, rm, 0, size);
4674 }
4675
4676 switch (size) {
4677 case MO_32:
4678 if (signal_all_nans) {
4679 gen_helper_vfp_cmpes_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4680 } else {
4681 gen_helper_vfp_cmps_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4682 }
4683 break;
4684 case MO_16:
4685 if (signal_all_nans) {
4686 gen_helper_vfp_cmpeh_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4687 } else {
4688 gen_helper_vfp_cmph_a64(tcg_flags, tcg_vn, tcg_vm, fpst);
4689 }
4690 break;
4691 default:
4692 g_assert_not_reached();
4693 }
4694
4695 tcg_temp_free_i32(tcg_vn);
4696 tcg_temp_free_i32(tcg_vm);
4697 }
4698
4699 tcg_temp_free_ptr(fpst);
4700
4701 gen_set_nzcv(tcg_flags);
4702
4703 tcg_temp_free_i64(tcg_flags);
4704 }
4705
4706 /* Floating point compare
4707 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
4708 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4709 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
4710 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
4711 */
4712 static void disas_fp_compare(DisasContext *s, uint32_t insn)
4713 {
4714 unsigned int mos, type, rm, op, rn, opc, op2r;
4715 int size;
4716
4717 mos = extract32(insn, 29, 3);
4718 type = extract32(insn, 22, 2);
4719 rm = extract32(insn, 16, 5);
4720 op = extract32(insn, 14, 2);
4721 rn = extract32(insn, 5, 5);
4722 opc = extract32(insn, 3, 2);
4723 op2r = extract32(insn, 0, 3);
4724
4725 if (mos || op || op2r) {
4726 unallocated_encoding(s);
4727 return;
4728 }
4729
4730 switch (type) {
4731 case 0:
4732 size = MO_32;
4733 break;
4734 case 1:
4735 size = MO_64;
4736 break;
4737 case 3:
4738 size = MO_16;
4739 if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
4740 break;
4741 }
4742 /* fallthru */
4743 default:
4744 unallocated_encoding(s);
4745 return;
4746 }
4747
4748 if (!fp_access_check(s)) {
4749 return;
4750 }
4751
4752 handle_fp_compare(s, size, rn, rm, opc & 1, opc & 2);
4753 }
4754
4755 /* Floating point conditional compare
4756 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4757 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4758 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
4759 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
4760 */
4761 static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
4762 {
4763 unsigned int mos, type, rm, cond, rn, op, nzcv;
4764 TCGv_i64 tcg_flags;
4765 TCGLabel *label_continue = NULL;
4766 int size;
4767
4768 mos = extract32(insn, 29, 3);
4769 type = extract32(insn, 22, 2);
4770 rm = extract32(insn, 16, 5);
4771 cond = extract32(insn, 12, 4);
4772 rn = extract32(insn, 5, 5);
4773 op = extract32(insn, 4, 1);
4774 nzcv = extract32(insn, 0, 4);
4775
4776 if (mos) {
4777 unallocated_encoding(s);
4778 return;
4779 }
4780
4781 switch (type) {
4782 case 0:
4783 size = MO_32;
4784 break;
4785 case 1:
4786 size = MO_64;
4787 break;
4788 case 3:
4789 size = MO_16;
4790 if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
4791 break;
4792 }
4793 /* fallthru */
4794 default:
4795 unallocated_encoding(s);
4796 return;
4797 }
4798
4799 if (!fp_access_check(s)) {
4800 return;
4801 }
4802
4803 if (cond < 0x0e) { /* not always */
4804 TCGLabel *label_match = gen_new_label();
4805 label_continue = gen_new_label();
4806 arm_gen_test_cc(cond, label_match);
4807 /* nomatch: */
4808 tcg_flags = tcg_const_i64(nzcv << 28);
4809 gen_set_nzcv(tcg_flags);
4810 tcg_temp_free_i64(tcg_flags);
4811 tcg_gen_br(label_continue);
4812 gen_set_label(label_match);
4813 }
4814
4815 handle_fp_compare(s, size, rn, rm, false, op);
4816
4817 if (cond < 0x0e) {
4818 gen_set_label(label_continue);
4819 }
4820 }
4821
4822 /* Floating point conditional select
4823 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
4824 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4825 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
4826 * +---+---+---+-----------+------+---+------+------+-----+------+------+
4827 */
4828 static void disas_fp_csel(DisasContext *s, uint32_t insn)
4829 {
4830 unsigned int mos, type, rm, cond, rn, rd;
4831 TCGv_i64 t_true, t_false, t_zero;
4832 DisasCompare64 c;
4833 TCGMemOp sz;
4834
4835 mos = extract32(insn, 29, 3);
4836 type = extract32(insn, 22, 2);
4837 rm = extract32(insn, 16, 5);
4838 cond = extract32(insn, 12, 4);
4839 rn = extract32(insn, 5, 5);
4840 rd = extract32(insn, 0, 5);
4841
4842 if (mos) {
4843 unallocated_encoding(s);
4844 return;
4845 }
4846
4847 switch (type) {
4848 case 0:
4849 sz = MO_32;
4850 break;
4851 case 1:
4852 sz = MO_64;
4853 break;
4854 case 3:
4855 sz = MO_16;
4856 if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
4857 break;
4858 }
4859 /* fallthru */
4860 default:
4861 unallocated_encoding(s);
4862 return;
4863 }
4864
4865 if (!fp_access_check(s)) {
4866 return;
4867 }
4868
4869 /* Zero extend sreg & hreg inputs to 64 bits now. */
4870 t_true = tcg_temp_new_i64();
4871 t_false = tcg_temp_new_i64();
4872 read_vec_element(s, t_true, rn, 0, sz);
4873 read_vec_element(s, t_false, rm, 0, sz);
4874
4875 a64_test_cc(&c, cond);
4876 t_zero = tcg_const_i64(0);
4877 tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false);
4878 tcg_temp_free_i64(t_zero);
4879 tcg_temp_free_i64(t_false);
4880 a64_free_cc(&c);
4881
4882 /* Note that sregs & hregs write back zeros to the high bits,
4883 and we've already done the zero-extension. */
4884 write_fp_dreg(s, rd, t_true);
4885 tcg_temp_free_i64(t_true);
4886 }
4887
4888 /* Floating-point data-processing (1 source) - half precision */
4889 static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
4890 {
4891 TCGv_ptr fpst = NULL;
4892 TCGv_i32 tcg_op = read_fp_hreg(s, rn);
4893 TCGv_i32 tcg_res = tcg_temp_new_i32();
4894
4895 switch (opcode) {
4896 case 0x0: /* FMOV */
4897 tcg_gen_mov_i32(tcg_res, tcg_op);
4898 break;
4899 case 0x1: /* FABS */
4900 tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
4901 break;
4902 case 0x2: /* FNEG */
4903 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
4904 break;
4905 case 0x3: /* FSQRT */
4906 fpst = get_fpstatus_ptr(true);
4907 gen_helper_sqrt_f16(tcg_res, tcg_op, fpst);
4908 break;
4909 case 0x8: /* FRINTN */
4910 case 0x9: /* FRINTP */
4911 case 0xa: /* FRINTM */
4912 case 0xb: /* FRINTZ */
4913 case 0xc: /* FRINTA */
4914 {
4915 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
4916 fpst = get_fpstatus_ptr(true);
4917
4918 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
4919 gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
4920
4921 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
4922 tcg_temp_free_i32(tcg_rmode);
4923 break;
4924 }
4925 case 0xe: /* FRINTX */
4926 fpst = get_fpstatus_ptr(true);
4927 gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, fpst);
4928 break;
4929 case 0xf: /* FRINTI */
4930 fpst = get_fpstatus_ptr(true);
4931 gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst);
4932 break;
4933 default:
4934 abort();
4935 }
4936
4937 write_fp_sreg(s, rd, tcg_res);
4938
4939 if (fpst) {
4940 tcg_temp_free_ptr(fpst);
4941 }
4942 tcg_temp_free_i32(tcg_op);
4943 tcg_temp_free_i32(tcg_res);
4944 }
4945
4946 /* Floating-point data-processing (1 source) - single precision */
4947 static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
4948 {
4949 TCGv_ptr fpst;
4950 TCGv_i32 tcg_op;
4951 TCGv_i32 tcg_res;
4952
4953 fpst = get_fpstatus_ptr(false);
4954 tcg_op = read_fp_sreg(s, rn);
4955 tcg_res = tcg_temp_new_i32();
4956
4957 switch (opcode) {
4958 case 0x0: /* FMOV */
4959 tcg_gen_mov_i32(tcg_res, tcg_op);
4960 break;
4961 case 0x1: /* FABS */
4962 gen_helper_vfp_abss(tcg_res, tcg_op);
4963 break;
4964 case 0x2: /* FNEG */
4965 gen_helper_vfp_negs(tcg_res, tcg_op);
4966 break;
4967 case 0x3: /* FSQRT */
4968 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
4969 break;
4970 case 0x8: /* FRINTN */
4971 case 0x9: /* FRINTP */
4972 case 0xa: /* FRINTM */
4973 case 0xb: /* FRINTZ */
4974 case 0xc: /* FRINTA */
4975 {
4976 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
4977
4978 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
4979 gen_helper_rints(tcg_res, tcg_op, fpst);
4980
4981 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
4982 tcg_temp_free_i32(tcg_rmode);
4983 break;
4984 }
4985 case 0xe: /* FRINTX */
4986 gen_helper_rints_exact(tcg_res, tcg_op, fpst);
4987 break;
4988 case 0xf: /* FRINTI */
4989 gen_helper_rints(tcg_res, tcg_op, fpst);
4990 break;
4991 default:
4992 abort();
4993 }
4994
4995 write_fp_sreg(s, rd, tcg_res);
4996
4997 tcg_temp_free_ptr(fpst);
4998 tcg_temp_free_i32(tcg_op);
4999 tcg_temp_free_i32(tcg_res);
5000 }
5001
5002 /* Floating-point data-processing (1 source) - double precision */
5003 static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
5004 {
5005 TCGv_ptr fpst;
5006 TCGv_i64 tcg_op;
5007 TCGv_i64 tcg_res;
5008
5009 switch (opcode) {
5010 case 0x0: /* FMOV */
5011 gen_gvec_fn2(s, false, rd, rn, tcg_gen_gvec_mov, 0);
5012 return;
5013 }
5014
5015 fpst = get_fpstatus_ptr(false);
5016 tcg_op = read_fp_dreg(s, rn);
5017 tcg_res = tcg_temp_new_i64();
5018
5019 switch (opcode) {
5020 case 0x1: /* FABS */
5021 gen_helper_vfp_absd(tcg_res, tcg_op);
5022 break;
5023 case 0x2: /* FNEG */
5024 gen_helper_vfp_negd(tcg_res, tcg_op);
5025 break;
5026 case 0x3: /* FSQRT */
5027 gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
5028 break;
5029 case 0x8: /* FRINTN */
5030 case 0x9: /* FRINTP */
5031 case 0xa: /* FRINTM */
5032 case 0xb: /* FRINTZ */
5033 case 0xc: /* FRINTA */
5034 {
5035 TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
5036
5037 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5038 gen_helper_rintd(tcg_res, tcg_op, fpst);
5039
5040 gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
5041 tcg_temp_free_i32(tcg_rmode);
5042 break;
5043 }
5044 case 0xe: /* FRINTX */
5045 gen_helper_rintd_exact(tcg_res, tcg_op, fpst);
5046 break;
5047 case 0xf: /* FRINTI */
5048 gen_helper_rintd(tcg_res, tcg_op, fpst);
5049 break;
5050 default:
5051 abort();
5052 }
5053
5054 write_fp_dreg(s, rd, tcg_res);
5055
5056 tcg_temp_free_ptr(fpst);
5057 tcg_temp_free_i64(tcg_op);
5058 tcg_temp_free_i64(tcg_res);
5059 }
5060
5061 static void handle_fp_fcvt(DisasContext *s, int opcode,
5062 int rd, int rn, int dtype, int ntype)
5063 {
5064 switch (ntype) {
5065 case 0x0:
5066 {
5067 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
5068 if (dtype == 1) {
5069 /* Single to double */
5070 TCGv_i64 tcg_rd = tcg_temp_new_i64();
5071 gen_helper_vfp_fcvtds(tcg_rd, tcg_rn, cpu_env);
5072 write_fp_dreg(s, rd, tcg_rd);
5073 tcg_temp_free_i64(tcg_rd);
5074 } else {
5075 /* Single to half */
5076 TCGv_i32 tcg_rd = tcg_temp_new_i32();
5077 TCGv_i32 ahp = get_ahp_flag();
5078 TCGv_ptr fpst = get_fpstatus_ptr(false);
5079
5080 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd, tcg_rn, fpst, ahp);
5081 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5082 write_fp_sreg(s, rd, tcg_rd);
5083 tcg_temp_free_i32(tcg_rd);
5084 tcg_temp_free_i32(ahp);
5085 tcg_temp_free_ptr(fpst);
5086 }
5087 tcg_temp_free_i32(tcg_rn);
5088 break;
5089 }
5090 case 0x1:
5091 {
5092 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
5093 TCGv_i32 tcg_rd = tcg_temp_new_i32();
5094 if (dtype == 0) {
5095 /* Double to single */
5096 gen_helper_vfp_fcvtsd(tcg_rd, tcg_rn, cpu_env);
5097 } else {
5098 TCGv_ptr fpst = get_fpstatus_ptr(false);
5099 TCGv_i32 ahp = get_ahp_flag();
5100 /* Double to half */
5101 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd, tcg_rn, fpst, ahp);
5102 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5103 tcg_temp_free_ptr(fpst);
5104 tcg_temp_free_i32(ahp);
5105 }
5106 write_fp_sreg(s, rd, tcg_rd);
5107 tcg_temp_free_i32(tcg_rd);
5108 tcg_temp_free_i64(tcg_rn);
5109 break;
5110 }
5111 case 0x3:
5112 {
5113 TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
5114 TCGv_ptr tcg_fpst = get_fpstatus_ptr(false);
5115 TCGv_i32 tcg_ahp = get_ahp_flag();
5116 tcg_gen_ext16u_i32(tcg_rn, tcg_rn);
5117 if (dtype == 0) {
5118 /* Half to single */
5119 TCGv_i32 tcg_rd = tcg_temp_new_i32();
5120 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
5121 write_fp_sreg(s, rd, tcg_rd);
5122 tcg_temp_free_ptr(tcg_fpst);
5123 tcg_temp_free_i32(tcg_ahp);
5124 tcg_temp_free_i32(tcg_rd);
5125 } else {
5126 /* Half to double */
5127 TCGv_i64 tcg_rd = tcg_temp_new_i64();
5128 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
5129 write_fp_dreg(s, rd, tcg_rd);
5130 tcg_temp_free_i64(tcg_rd);
5131 }
5132 tcg_temp_free_i32(tcg_rn);
5133 break;
5134 }
5135 default:
5136 abort();
5137 }
5138 }
5139
5140 /* Floating point data-processing (1 source)
5141 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5142 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5143 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5144 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5145 */
5146 static void disas_fp_1src(DisasContext *s, uint32_t insn)
5147 {
5148 int type = extract32(insn, 22, 2);
5149 int opcode = extract32(insn, 15, 6);
5150 int rn = extract32(insn, 5, 5);
5151 int rd = extract32(insn, 0, 5);
5152
5153 switch (opcode) {
5154 case 0x4: case 0x5: case 0x7:
5155 {
5156 /* FCVT between half, single and double precision */
5157 int dtype = extract32(opcode, 0, 2);
5158 if (type == 2 || dtype == type) {
5159 unallocated_encoding(s);
5160 return;
5161 }
5162 if (!fp_access_check(s)) {
5163 return;
5164 }
5165
5166 handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
5167 break;
5168 }
5169 case 0x0 ... 0x3:
5170 case 0x8 ... 0xc:
5171 case 0xe ... 0xf:
5172 /* 32-to-32 and 64-to-64 ops */
5173 switch (type) {
5174 case 0:
5175 if (!fp_access_check(s)) {
5176 return;
5177 }
5178
5179 handle_fp_1src_single(s, opcode, rd, rn);
5180 break;
5181 case 1:
5182 if (!fp_access_check(s)) {
5183 return;
5184 }
5185
5186 handle_fp_1src_double(s, opcode, rd, rn);
5187 break;
5188 case 3:
5189 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
5190 unallocated_encoding(s);
5191 return;
5192 }
5193
5194 if (!fp_access_check(s)) {
5195 return;
5196 }
5197
5198 handle_fp_1src_half(s, opcode, rd, rn);
5199 break;
5200 default:
5201 unallocated_encoding(s);
5202 }
5203 break;
5204 default:
5205 unallocated_encoding(s);
5206 break;
5207 }
5208 }
5209
5210 /* Floating-point data-processing (2 source) - single precision */
5211 static void handle_fp_2src_single(DisasContext *s, int opcode,
5212 int rd, int rn, int rm)
5213 {
5214 TCGv_i32 tcg_op1;
5215 TCGv_i32 tcg_op2;
5216 TCGv_i32 tcg_res;
5217 TCGv_ptr fpst;
5218
5219 tcg_res = tcg_temp_new_i32();
5220 fpst = get_fpstatus_ptr(false);
5221 tcg_op1 = read_fp_sreg(s, rn);
5222 tcg_op2 = read_fp_sreg(s, rm);
5223
5224 switch (opcode) {
5225 case 0x0: /* FMUL */
5226 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
5227 break;
5228 case 0x1: /* FDIV */
5229 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
5230 break;
5231 case 0x2: /* FADD */
5232 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
5233 break;
5234 case 0x3: /* FSUB */
5235 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
5236 break;
5237 case 0x4: /* FMAX */
5238 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
5239 break;
5240 case 0x5: /* FMIN */
5241 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
5242 break;
5243 case 0x6: /* FMAXNM */
5244 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
5245 break;
5246 case 0x7: /* FMINNM */
5247 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
5248 break;
5249 case 0x8: /* FNMUL */
5250 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
5251 gen_helper_vfp_negs(tcg_res, tcg_res);
5252 break;
5253 }
5254
5255 write_fp_sreg(s, rd, tcg_res);
5256
5257 tcg_temp_free_ptr(fpst);
5258 tcg_temp_free_i32(tcg_op1);
5259 tcg_temp_free_i32(tcg_op2);
5260 tcg_temp_free_i32(tcg_res);
5261 }
5262
5263 /* Floating-point data-processing (2 source) - double precision */
5264 static void handle_fp_2src_double(DisasContext *s, int opcode,
5265 int rd, int rn, int rm)
5266 {
5267 TCGv_i64 tcg_op1;
5268 TCGv_i64 tcg_op2;
5269 TCGv_i64 tcg_res;
5270 TCGv_ptr fpst;
5271
5272 tcg_res = tcg_temp_new_i64();
5273 fpst = get_fpstatus_ptr(false);
5274 tcg_op1 = read_fp_dreg(s, rn);
5275 tcg_op2 = read_fp_dreg(s, rm);
5276
5277 switch (opcode) {
5278 case 0x0: /* FMUL */
5279 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
5280 break;
5281 case 0x1: /* FDIV */
5282 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
5283 break;
5284 case 0x2: /* FADD */
5285 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
5286 break;
5287 case 0x3: /* FSUB */
5288 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
5289 break;
5290 case 0x4: /* FMAX */
5291 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
5292 break;
5293 case 0x5: /* FMIN */
5294 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
5295 break;
5296 case 0x6: /* FMAXNM */
5297 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
5298 break;
5299 case 0x7: /* FMINNM */
5300 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
5301 break;
5302 case 0x8: /* FNMUL */
5303 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
5304 gen_helper_vfp_negd(tcg_res, tcg_res);
5305 break;
5306 }
5307
5308 write_fp_dreg(s, rd, tcg_res);
5309
5310 tcg_temp_free_ptr(fpst);
5311 tcg_temp_free_i64(tcg_op1);
5312 tcg_temp_free_i64(tcg_op2);
5313 tcg_temp_free_i64(tcg_res);
5314 }
5315
5316 /* Floating-point data-processing (2 source) - half precision */
5317 static void handle_fp_2src_half(DisasContext *s, int opcode,
5318 int rd, int rn, int rm)
5319 {
5320 TCGv_i32 tcg_op1;
5321 TCGv_i32 tcg_op2;
5322 TCGv_i32 tcg_res;
5323 TCGv_ptr fpst;
5324
5325 tcg_res = tcg_temp_new_i32();
5326 fpst = get_fpstatus_ptr(true);
5327 tcg_op1 = read_fp_hreg(s, rn);
5328 tcg_op2 = read_fp_hreg(s, rm);
5329
5330 switch (opcode) {
5331 case 0x0: /* FMUL */
5332 gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
5333 break;
5334 case 0x1: /* FDIV */
5335 gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
5336 break;
5337 case 0x2: /* FADD */
5338 gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
5339 break;
5340 case 0x3: /* FSUB */
5341 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
5342 break;
5343 case 0x4: /* FMAX */
5344 gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
5345 break;
5346 case 0x5: /* FMIN */
5347 gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
5348 break;
5349 case 0x6: /* FMAXNM */
5350 gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
5351 break;
5352 case 0x7: /* FMINNM */
5353 gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
5354 break;
5355 case 0x8: /* FNMUL */
5356 gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
5357 tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
5358 break;
5359 default:
5360 g_assert_not_reached();
5361 }
5362
5363 write_fp_sreg(s, rd, tcg_res);
5364
5365 tcg_temp_free_ptr(fpst);
5366 tcg_temp_free_i32(tcg_op1);
5367 tcg_temp_free_i32(tcg_op2);
5368 tcg_temp_free_i32(tcg_res);
5369 }
5370
5371 /* Floating point data-processing (2 source)
5372 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5373 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5374 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5375 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5376 */
5377 static void disas_fp_2src(DisasContext *s, uint32_t insn)
5378 {
5379 int type = extract32(insn, 22, 2);
5380 int rd = extract32(insn, 0, 5);
5381 int rn = extract32(insn, 5, 5);
5382 int rm = extract32(insn, 16, 5);
5383 int opcode = extract32(insn, 12, 4);
5384
5385 if (opcode > 8) {
5386 unallocated_encoding(s);
5387 return;
5388 }
5389
5390 switch (type) {
5391 case 0:
5392 if (!fp_access_check(s)) {
5393 return;
5394 }
5395 handle_fp_2src_single(s, opcode, rd, rn, rm);
5396 break;
5397 case 1:
5398 if (!fp_access_check(s)) {
5399 return;
5400 }
5401 handle_fp_2src_double(s, opcode, rd, rn, rm);
5402 break;
5403 case 3:
5404 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
5405 unallocated_encoding(s);
5406 return;
5407 }
5408 if (!fp_access_check(s)) {
5409 return;
5410 }
5411 handle_fp_2src_half(s, opcode, rd, rn, rm);
5412 break;
5413 default:
5414 unallocated_encoding(s);
5415 }
5416 }
5417
5418 /* Floating-point data-processing (3 source) - single precision */
5419 static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
5420 int rd, int rn, int rm, int ra)
5421 {
5422 TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
5423 TCGv_i32 tcg_res = tcg_temp_new_i32();
5424 TCGv_ptr fpst = get_fpstatus_ptr(false);
5425
5426 tcg_op1 = read_fp_sreg(s, rn);
5427 tcg_op2 = read_fp_sreg(s, rm);
5428 tcg_op3 = read_fp_sreg(s, ra);
5429
5430 /* These are fused multiply-add, and must be done as one
5431 * floating point operation with no rounding between the
5432 * multiplication and addition steps.
5433 * NB that doing the negations here as separate steps is
5434 * correct : an input NaN should come out with its sign bit
5435 * flipped if it is a negated-input.
5436 */
5437 if (o1 == true) {
5438 gen_helper_vfp_negs(tcg_op3, tcg_op3);
5439 }
5440
5441 if (o0 != o1) {
5442 gen_helper_vfp_negs(tcg_op1, tcg_op1);
5443 }
5444
5445 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
5446
5447 write_fp_sreg(s, rd, tcg_res);
5448
5449 tcg_temp_free_ptr(fpst);
5450 tcg_temp_free_i32(tcg_op1);
5451 tcg_temp_free_i32(tcg_op2);
5452 tcg_temp_free_i32(tcg_op3);
5453 tcg_temp_free_i32(tcg_res);
5454 }
5455
5456 /* Floating-point data-processing (3 source) - double precision */
5457 static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
5458 int rd, int rn, int rm, int ra)
5459 {
5460 TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
5461 TCGv_i64 tcg_res = tcg_temp_new_i64();
5462 TCGv_ptr fpst = get_fpstatus_ptr(false);
5463
5464 tcg_op1 = read_fp_dreg(s, rn);
5465 tcg_op2 = read_fp_dreg(s, rm);
5466 tcg_op3 = read_fp_dreg(s, ra);
5467
5468 /* These are fused multiply-add, and must be done as one
5469 * floating point operation with no rounding between the
5470 * multiplication and addition steps.
5471 * NB that doing the negations here as separate steps is
5472 * correct : an input NaN should come out with its sign bit
5473 * flipped if it is a negated-input.
5474 */
5475 if (o1 == true) {
5476 gen_helper_vfp_negd(tcg_op3, tcg_op3);
5477 }
5478
5479 if (o0 != o1) {
5480 gen_helper_vfp_negd(tcg_op1, tcg_op1);
5481 }
5482
5483 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
5484
5485 write_fp_dreg(s, rd, tcg_res);
5486
5487 tcg_temp_free_ptr(fpst);
5488 tcg_temp_free_i64(tcg_op1);
5489 tcg_temp_free_i64(tcg_op2);
5490 tcg_temp_free_i64(tcg_op3);
5491 tcg_temp_free_i64(tcg_res);
5492 }
5493
5494 /* Floating-point data-processing (3 source) - half precision */
5495 static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
5496 int rd, int rn, int rm, int ra)
5497 {
5498 TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
5499 TCGv_i32 tcg_res = tcg_temp_new_i32();
5500 TCGv_ptr fpst = get_fpstatus_ptr(true);
5501
5502 tcg_op1 = read_fp_hreg(s, rn);
5503 tcg_op2 = read_fp_hreg(s, rm);
5504 tcg_op3 = read_fp_hreg(s, ra);
5505
5506 /* These are fused multiply-add, and must be done as one
5507 * floating point operation with no rounding between the
5508 * multiplication and addition steps.
5509 * NB that doing the negations here as separate steps is
5510 * correct : an input NaN should come out with its sign bit
5511 * flipped if it is a negated-input.
5512 */
5513 if (o1 == true) {
5514 tcg_gen_xori_i32(tcg_op3, tcg_op3, 0x8000);
5515 }
5516
5517 if (o0 != o1) {
5518 tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
5519 }
5520
5521 gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
5522
5523 write_fp_sreg(s, rd, tcg_res);
5524
5525 tcg_temp_free_ptr(fpst);
5526 tcg_temp_free_i32(tcg_op1);
5527 tcg_temp_free_i32(tcg_op2);
5528 tcg_temp_free_i32(tcg_op3);
5529 tcg_temp_free_i32(tcg_res);
5530 }
5531
5532 /* Floating point data-processing (3 source)
5533 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
5534 * +---+---+---+-----------+------+----+------+----+------+------+------+
5535 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
5536 * +---+---+---+-----------+------+----+------+----+------+------+------+
5537 */
5538 static void disas_fp_3src(DisasContext *s, uint32_t insn)
5539 {
5540 int type = extract32(insn, 22, 2);
5541 int rd = extract32(insn, 0, 5);
5542 int rn = extract32(insn, 5, 5);
5543 int ra = extract32(insn, 10, 5);
5544 int rm = extract32(insn, 16, 5);
5545 bool o0 = extract32(insn, 15, 1);
5546 bool o1 = extract32(insn, 21, 1);
5547
5548 switch (type) {
5549 case 0:
5550 if (!fp_access_check(s)) {
5551 return;
5552 }
5553 handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra);
5554 break;
5555 case 1:
5556 if (!fp_access_check(s)) {
5557 return;
5558 }
5559 handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
5560 break;
5561 case 3:
5562 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
5563 unallocated_encoding(s);
5564 return;
5565 }
5566 if (!fp_access_check(s)) {
5567 return;
5568 }
5569 handle_fp_3src_half(s, o0, o1, rd, rn, rm, ra);
5570 break;
5571 default:
5572 unallocated_encoding(s);
5573 }
5574 }
5575
5576 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
5577 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
5578 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
5579 */
5580 uint64_t vfp_expand_imm(int size, uint8_t imm8)
5581 {
5582 uint64_t imm;
5583
5584 switch (size) {
5585 case MO_64:
5586 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
5587 (extract32(imm8, 6, 1) ? 0x3fc0 : 0x4000) |
5588 extract32(imm8, 0, 6);
5589 imm <<= 48;
5590 break;
5591 case MO_32:
5592 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
5593 (extract32(imm8, 6, 1) ? 0x3e00 : 0x4000) |
5594 (extract32(imm8, 0, 6) << 3);
5595 imm <<= 16;
5596 break;
5597 case MO_16:
5598 imm = (extract32(imm8, 7, 1) ? 0x8000 : 0) |
5599 (extract32(imm8, 6, 1) ? 0x3000 : 0x4000) |
5600 (extract32(imm8, 0, 6) << 6);
5601 break;
5602 default:
5603 g_assert_not_reached();
5604 }
5605 return imm;
5606 }
5607
5608 /* Floating point immediate
5609 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
5610 * +---+---+---+-----------+------+---+------------+-------+------+------+
5611 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
5612 * +---+---+---+-----------+------+---+------------+-------+------+------+
5613 */
5614 static void disas_fp_imm(DisasContext *s, uint32_t insn)
5615 {
5616 int rd = extract32(insn, 0, 5);
5617 int imm8 = extract32(insn, 13, 8);
5618 int type = extract32(insn, 22, 2);
5619 uint64_t imm;
5620 TCGv_i64 tcg_res;
5621 TCGMemOp sz;
5622
5623 switch (type) {
5624 case 0:
5625 sz = MO_32;
5626 break;
5627 case 1:
5628 sz = MO_64;
5629 break;
5630 case 3:
5631 sz = MO_16;
5632 if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
5633 break;
5634 }
5635 /* fallthru */
5636 default:
5637 unallocated_encoding(s);
5638 return;
5639 }
5640
5641 if (!fp_access_check(s)) {
5642 return;
5643 }
5644
5645 imm = vfp_expand_imm(sz, imm8);
5646
5647 tcg_res = tcg_const_i64(imm);
5648 write_fp_dreg(s, rd, tcg_res);
5649 tcg_temp_free_i64(tcg_res);
5650 }
5651
5652 /* Handle floating point <=> fixed point conversions. Note that we can
5653 * also deal with fp <=> integer conversions as a special case (scale == 64)
5654 * OPTME: consider handling that special case specially or at least skipping
5655 * the call to scalbn in the helpers for zero shifts.
5656 */
5657 static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
5658 bool itof, int rmode, int scale, int sf, int type)
5659 {
5660 bool is_signed = !(opcode & 1);
5661 TCGv_ptr tcg_fpstatus;
5662 TCGv_i32 tcg_shift, tcg_single;
5663 TCGv_i64 tcg_double;
5664
5665 tcg_fpstatus = get_fpstatus_ptr(type == 3);
5666
5667 tcg_shift = tcg_const_i32(64 - scale);
5668
5669 if (itof) {
5670 TCGv_i64 tcg_int = cpu_reg(s, rn);
5671 if (!sf) {
5672 TCGv_i64 tcg_extend = new_tmp_a64(s);
5673
5674 if (is_signed) {
5675 tcg_gen_ext32s_i64(tcg_extend, tcg_int);
5676 } else {
5677 tcg_gen_ext32u_i64(tcg_extend, tcg_int);
5678 }
5679
5680 tcg_int = tcg_extend;
5681 }
5682
5683 switch (type) {
5684 case 1: /* float64 */
5685 tcg_double = tcg_temp_new_i64();
5686 if (is_signed) {
5687 gen_helper_vfp_sqtod(tcg_double, tcg_int,
5688 tcg_shift, tcg_fpstatus);
5689 } else {
5690 gen_helper_vfp_uqtod(tcg_double, tcg_int,
5691 tcg_shift, tcg_fpstatus);
5692 }
5693 write_fp_dreg(s, rd, tcg_double);
5694 tcg_temp_free_i64(tcg_double);
5695 break;
5696
5697 case 0: /* float32 */
5698 tcg_single = tcg_temp_new_i32();
5699 if (is_signed) {
5700 gen_helper_vfp_sqtos(tcg_single, tcg_int,
5701 tcg_shift, tcg_fpstatus);
5702 } else {
5703 gen_helper_vfp_uqtos(tcg_single, tcg_int,
5704 tcg_shift, tcg_fpstatus);
5705 }
5706 write_fp_sreg(s, rd, tcg_single);
5707 tcg_temp_free_i32(tcg_single);
5708 break;
5709
5710 case 3: /* float16 */
5711 tcg_single = tcg_temp_new_i32();
5712 if (is_signed) {
5713 gen_helper_vfp_sqtoh(tcg_single, tcg_int,
5714 tcg_shift, tcg_fpstatus);
5715 } else {
5716 gen_helper_vfp_uqtoh(tcg_single, tcg_int,
5717 tcg_shift, tcg_fpstatus);
5718 }
5719 write_fp_sreg(s, rd, tcg_single);
5720 tcg_temp_free_i32(tcg_single);
5721 break;
5722
5723 default:
5724 g_assert_not_reached();
5725 }
5726 } else {
5727 TCGv_i64 tcg_int = cpu_reg(s, rd);
5728 TCGv_i32 tcg_rmode;
5729
5730 if (extract32(opcode, 2, 1)) {
5731 /* There are too many rounding modes to all fit into rmode,
5732 * so FCVTA[US] is a special case.
5733 */
5734 rmode = FPROUNDING_TIEAWAY;
5735 }
5736
5737 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
5738
5739 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
5740
5741 switch (type) {
5742 case 1: /* float64 */
5743 tcg_double = read_fp_dreg(s, rn);
5744 if (is_signed) {
5745 if (!sf) {
5746 gen_helper_vfp_tosld(tcg_int, tcg_double,
5747 tcg_shift, tcg_fpstatus);
5748 } else {
5749 gen_helper_vfp_tosqd(tcg_int, tcg_double,
5750 tcg_shift, tcg_fpstatus);
5751 }
5752 } else {
5753 if (!sf) {
5754 gen_helper_vfp_tould(tcg_int, tcg_double,
5755 tcg_shift, tcg_fpstatus);
5756 } else {
5757 gen_helper_vfp_touqd(tcg_int, tcg_double,
5758 tcg_shift, tcg_fpstatus);
5759 }
5760 }
5761 if (!sf) {
5762 tcg_gen_ext32u_i64(tcg_int, tcg_int);
5763 }
5764 tcg_temp_free_i64(tcg_double);
5765 break;
5766
5767 case 0: /* float32 */
5768 tcg_single = read_fp_sreg(s, rn);
5769 if (sf) {
5770 if (is_signed) {
5771 gen_helper_vfp_tosqs(tcg_int, tcg_single,
5772 tcg_shift, tcg_fpstatus);
5773 } else {
5774 gen_helper_vfp_touqs(tcg_int, tcg_single,
5775 tcg_shift, tcg_fpstatus);
5776 }
5777 } else {
5778 TCGv_i32 tcg_dest = tcg_temp_new_i32();
5779 if (is_signed) {
5780 gen_helper_vfp_tosls(tcg_dest, tcg_single,
5781 tcg_shift, tcg_fpstatus);
5782 } else {
5783 gen_helper_vfp_touls(tcg_dest, tcg_single,
5784 tcg_shift, tcg_fpstatus);
5785 }
5786 tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
5787 tcg_temp_free_i32(tcg_dest);
5788 }
5789 tcg_temp_free_i32(tcg_single);
5790 break;
5791
5792 case 3: /* float16 */
5793 tcg_single = read_fp_sreg(s, rn);
5794 if (sf) {
5795 if (is_signed) {
5796 gen_helper_vfp_tosqh(tcg_int, tcg_single,
5797 tcg_shift, tcg_fpstatus);
5798 } else {
5799 gen_helper_vfp_touqh(tcg_int, tcg_single,
5800 tcg_shift, tcg_fpstatus);
5801 }
5802 } else {
5803 TCGv_i32 tcg_dest = tcg_temp_new_i32();
5804 if (is_signed) {
5805 gen_helper_vfp_toslh(tcg_dest, tcg_single,
5806 tcg_shift, tcg_fpstatus);
5807 } else {
5808 gen_helper_vfp_toulh(tcg_dest, tcg_single,
5809 tcg_shift, tcg_fpstatus);
5810 }
5811 tcg_gen_extu_i32_i64(tcg_int, tcg_dest);
5812 tcg_temp_free_i32(tcg_dest);
5813 }
5814 tcg_temp_free_i32(tcg_single);
5815 break;
5816
5817 default:
5818 g_assert_not_reached();
5819 }
5820
5821 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
5822 tcg_temp_free_i32(tcg_rmode);
5823 }
5824
5825 tcg_temp_free_ptr(tcg_fpstatus);
5826 tcg_temp_free_i32(tcg_shift);
5827 }
5828
5829 /* Floating point <-> fixed point conversions
5830 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5831 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5832 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
5833 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
5834 */
5835 static void disas_fp_fixed_conv(DisasContext *s, uint32_t insn)
5836 {
5837 int rd = extract32(insn, 0, 5);
5838 int rn = extract32(insn, 5, 5);
5839 int scale = extract32(insn, 10, 6);
5840 int opcode = extract32(insn, 16, 3);
5841 int rmode = extract32(insn, 19, 2);
5842 int type = extract32(insn, 22, 2);
5843 bool sbit = extract32(insn, 29, 1);
5844 bool sf = extract32(insn, 31, 1);
5845 bool itof;
5846
5847 if (sbit || (!sf && scale < 32)) {
5848 unallocated_encoding(s);
5849 return;
5850 }
5851
5852 switch (type) {
5853 case 0: /* float32 */
5854 case 1: /* float64 */
5855 break;
5856 case 3: /* float16 */
5857 if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
5858 break;
5859 }
5860 /* fallthru */
5861 default:
5862 unallocated_encoding(s);
5863 return;
5864 }
5865
5866 switch ((rmode << 3) | opcode) {
5867 case 0x2: /* SCVTF */
5868 case 0x3: /* UCVTF */
5869 itof = true;
5870 break;
5871 case 0x18: /* FCVTZS */
5872 case 0x19: /* FCVTZU */
5873 itof = false;
5874 break;
5875 default:
5876 unallocated_encoding(s);
5877 return;
5878 }
5879
5880 if (!fp_access_check(s)) {
5881 return;
5882 }
5883
5884 handle_fpfpcvt(s, rd, rn, opcode, itof, FPROUNDING_ZERO, scale, sf, type);
5885 }
5886
5887 static void handle_fmov(DisasContext *s, int rd, int rn, int type, bool itof)
5888 {
5889 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
5890 * without conversion.
5891 */
5892
5893 if (itof) {
5894 TCGv_i64 tcg_rn = cpu_reg(s, rn);
5895 TCGv_i64 tmp;
5896
5897 switch (type) {
5898 case 0:
5899 /* 32 bit */
5900 tmp = tcg_temp_new_i64();
5901 tcg_gen_ext32u_i64(tmp, tcg_rn);
5902 write_fp_dreg(s, rd, tmp);
5903 tcg_temp_free_i64(tmp);
5904 break;
5905 case 1:
5906 /* 64 bit */
5907 write_fp_dreg(s, rd, tcg_rn);
5908 break;
5909 case 2:
5910 /* 64 bit to top half. */
5911 tcg_gen_st_i64(tcg_rn, cpu_env, fp_reg_hi_offset(s, rd));
5912 clear_vec_high(s, true, rd);
5913 break;
5914 case 3:
5915 /* 16 bit */
5916 tmp = tcg_temp_new_i64();
5917 tcg_gen_ext16u_i64(tmp, tcg_rn);
5918 write_fp_dreg(s, rd, tmp);
5919 tcg_temp_free_i64(tmp);
5920 break;
5921 default:
5922 g_assert_not_reached();
5923 }
5924 } else {
5925 TCGv_i64 tcg_rd = cpu_reg(s, rd);
5926
5927 switch (type) {
5928 case 0:
5929 /* 32 bit */
5930 tcg_gen_ld32u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_32));
5931 break;
5932 case 1:
5933 /* 64 bit */
5934 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_64));
5935 break;
5936 case 2:
5937 /* 64 bits from top half */
5938 tcg_gen_ld_i64(tcg_rd, cpu_env, fp_reg_hi_offset(s, rn));
5939 break;
5940 case 3:
5941 /* 16 bit */
5942 tcg_gen_ld16u_i64(tcg_rd, cpu_env, fp_reg_offset(s, rn, MO_16));
5943 break;
5944 default:
5945 g_assert_not_reached();
5946 }
5947 }
5948 }
5949
5950 /* Floating point <-> integer conversions
5951 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
5952 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5953 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
5954 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
5955 */
5956 static void disas_fp_int_conv(DisasContext *s, uint32_t insn)
5957 {
5958 int rd = extract32(insn, 0, 5);
5959 int rn = extract32(insn, 5, 5);
5960 int opcode = extract32(insn, 16, 3);
5961 int rmode = extract32(insn, 19, 2);
5962 int type = extract32(insn, 22, 2);
5963 bool sbit = extract32(insn, 29, 1);
5964 bool sf = extract32(insn, 31, 1);
5965
5966 if (sbit) {
5967 unallocated_encoding(s);
5968 return;
5969 }
5970
5971 if (opcode > 5) {
5972 /* FMOV */
5973 bool itof = opcode & 1;
5974
5975 if (rmode >= 2) {
5976 unallocated_encoding(s);
5977 return;
5978 }
5979
5980 switch (sf << 3 | type << 1 | rmode) {
5981 case 0x0: /* 32 bit */
5982 case 0xa: /* 64 bit */
5983 case 0xd: /* 64 bit to top half of quad */
5984 break;
5985 case 0x6: /* 16-bit float, 32-bit int */
5986 case 0xe: /* 16-bit float, 64-bit int */
5987 if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
5988 break;
5989 }
5990 /* fallthru */
5991 default:
5992 /* all other sf/type/rmode combinations are invalid */
5993 unallocated_encoding(s);
5994 return;
5995 }
5996
5997 if (!fp_access_check(s)) {
5998 return;
5999 }
6000 handle_fmov(s, rd, rn, type, itof);
6001 } else {
6002 /* actual FP conversions */
6003 bool itof = extract32(opcode, 1, 1);
6004
6005 if (rmode != 0 && opcode > 1) {
6006 unallocated_encoding(s);
6007 return;
6008 }
6009 switch (type) {
6010 case 0: /* float32 */
6011 case 1: /* float64 */
6012 break;
6013 case 3: /* float16 */
6014 if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
6015 break;
6016 }
6017 /* fallthru */
6018 default:
6019 unallocated_encoding(s);
6020 return;
6021 }
6022
6023 if (!fp_access_check(s)) {
6024 return;
6025 }
6026 handle_fpfpcvt(s, rd, rn, opcode, itof, rmode, 64, sf, type);
6027 }
6028 }
6029
6030 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6031 * 31 30 29 28 25 24 0
6032 * +---+---+---+---------+-----------------------------+
6033 * | | 0 | | 1 1 1 1 | |
6034 * +---+---+---+---------+-----------------------------+
6035 */
6036 static void disas_data_proc_fp(DisasContext *s, uint32_t insn)
6037 {
6038 if (extract32(insn, 24, 1)) {
6039 /* Floating point data-processing (3 source) */
6040 disas_fp_3src(s, insn);
6041 } else if (extract32(insn, 21, 1) == 0) {
6042 /* Floating point to fixed point conversions */
6043 disas_fp_fixed_conv(s, insn);
6044 } else {
6045 switch (extract32(insn, 10, 2)) {
6046 case 1:
6047 /* Floating point conditional compare */
6048 disas_fp_ccomp(s, insn);
6049 break;
6050 case 2:
6051 /* Floating point data-processing (2 source) */
6052 disas_fp_2src(s, insn);
6053 break;
6054 case 3:
6055 /* Floating point conditional select */
6056 disas_fp_csel(s, insn);
6057 break;
6058 case 0:
6059 switch (ctz32(extract32(insn, 12, 4))) {
6060 case 0: /* [15:12] == xxx1 */
6061 /* Floating point immediate */
6062 disas_fp_imm(s, insn);
6063 break;
6064 case 1: /* [15:12] == xx10 */
6065 /* Floating point compare */
6066 disas_fp_compare(s, insn);
6067 break;
6068 case 2: /* [15:12] == x100 */
6069 /* Floating point data-processing (1 source) */
6070 disas_fp_1src(s, insn);
6071 break;
6072 case 3: /* [15:12] == 1000 */
6073 unallocated_encoding(s);
6074 break;
6075 default: /* [15:12] == 0000 */
6076 /* Floating point <-> integer conversions */
6077 disas_fp_int_conv(s, insn);
6078 break;
6079 }
6080 break;
6081 }
6082 }
6083 }
6084
6085 static void do_ext64(DisasContext *s, TCGv_i64 tcg_left, TCGv_i64 tcg_right,
6086 int pos)
6087 {
6088 /* Extract 64 bits from the middle of two concatenated 64 bit
6089 * vector register slices left:right. The extracted bits start
6090 * at 'pos' bits into the right (least significant) side.
6091 * We return the result in tcg_right, and guarantee not to
6092 * trash tcg_left.
6093 */
6094 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
6095 assert(pos > 0 && pos < 64);
6096
6097 tcg_gen_shri_i64(tcg_right, tcg_right, pos);
6098 tcg_gen_shli_i64(tcg_tmp, tcg_left, 64 - pos);
6099 tcg_gen_or_i64(tcg_right, tcg_right, tcg_tmp);
6100
6101 tcg_temp_free_i64(tcg_tmp);
6102 }
6103
6104 /* EXT
6105 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6106 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6107 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6108 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6109 */
6110 static void disas_simd_ext(DisasContext *s, uint32_t insn)
6111 {
6112 int is_q = extract32(insn, 30, 1);
6113 int op2 = extract32(insn, 22, 2);
6114 int imm4 = extract32(insn, 11, 4);
6115 int rm = extract32(insn, 16, 5);
6116 int rn = extract32(insn, 5, 5);
6117 int rd = extract32(insn, 0, 5);
6118 int pos = imm4 << 3;
6119 TCGv_i64 tcg_resl, tcg_resh;
6120
6121 if (op2 != 0 || (!is_q && extract32(imm4, 3, 1))) {
6122 unallocated_encoding(s);
6123 return;
6124 }
6125
6126 if (!fp_access_check(s)) {
6127 return;
6128 }
6129
6130 tcg_resh = tcg_temp_new_i64();
6131 tcg_resl = tcg_temp_new_i64();
6132
6133 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6134 * either extracting 128 bits from a 128:128 concatenation, or
6135 * extracting 64 bits from a 64:64 concatenation.
6136 */
6137 if (!is_q) {
6138 read_vec_element(s, tcg_resl, rn, 0, MO_64);
6139 if (pos != 0) {
6140 read_vec_element(s, tcg_resh, rm, 0, MO_64);
6141 do_ext64(s, tcg_resh, tcg_resl, pos);
6142 }
6143 tcg_gen_movi_i64(tcg_resh, 0);
6144 } else {
6145 TCGv_i64 tcg_hh;
6146 typedef struct {
6147 int reg;
6148 int elt;
6149 } EltPosns;
6150 EltPosns eltposns[] = { {rn, 0}, {rn, 1}, {rm, 0}, {rm, 1} };
6151 EltPosns *elt = eltposns;
6152
6153 if (pos >= 64) {
6154 elt++;
6155 pos -= 64;
6156 }
6157
6158 read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64);
6159 elt++;
6160 read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64);
6161 elt++;
6162 if (pos != 0) {
6163 do_ext64(s, tcg_resh, tcg_resl, pos);
6164 tcg_hh = tcg_temp_new_i64();
6165 read_vec_element(s, tcg_hh, elt->reg, elt->elt, MO_64);
6166 do_ext64(s, tcg_hh, tcg_resh, pos);
6167 tcg_temp_free_i64(tcg_hh);
6168 }
6169 }
6170
6171 write_vec_element(s, tcg_resl, rd, 0, MO_64);
6172 tcg_temp_free_i64(tcg_resl);
6173 write_vec_element(s, tcg_resh, rd, 1, MO_64);
6174 tcg_temp_free_i64(tcg_resh);
6175 }
6176
6177 /* TBL/TBX
6178 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6179 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6180 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6181 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6182 */
6183 static void disas_simd_tb(DisasContext *s, uint32_t insn)
6184 {
6185 int op2 = extract32(insn, 22, 2);
6186 int is_q = extract32(insn, 30, 1);
6187 int rm = extract32(insn, 16, 5);
6188 int rn = extract32(insn, 5, 5);
6189 int rd = extract32(insn, 0, 5);
6190 int is_tblx = extract32(insn, 12, 1);
6191 int len = extract32(insn, 13, 2);
6192 TCGv_i64 tcg_resl, tcg_resh, tcg_idx;
6193 TCGv_i32 tcg_regno, tcg_numregs;
6194
6195 if (op2 != 0) {
6196 unallocated_encoding(s);
6197 return;
6198 }
6199
6200 if (!fp_access_check(s)) {
6201 return;
6202 }
6203
6204 /* This does a table lookup: for every byte element in the input
6205 * we index into a table formed from up to four vector registers,
6206 * and then the output is the result of the lookups. Our helper
6207 * function does the lookup operation for a single 64 bit part of
6208 * the input.
6209 */
6210 tcg_resl = tcg_temp_new_i64();
6211 tcg_resh = tcg_temp_new_i64();
6212
6213 if (is_tblx) {
6214 read_vec_element(s, tcg_resl, rd, 0, MO_64);
6215 } else {
6216 tcg_gen_movi_i64(tcg_resl, 0);
6217 }
6218 if (is_tblx && is_q) {
6219 read_vec_element(s, tcg_resh, rd, 1, MO_64);
6220 } else {
6221 tcg_gen_movi_i64(tcg_resh, 0);
6222 }
6223
6224 tcg_idx = tcg_temp_new_i64();
6225 tcg_regno = tcg_const_i32(rn);
6226 tcg_numregs = tcg_const_i32(len + 1);
6227 read_vec_element(s, tcg_idx, rm, 0, MO_64);
6228 gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,
6229 tcg_regno, tcg_numregs);
6230 if (is_q) {
6231 read_vec_element(s, tcg_idx, rm, 1, MO_64);
6232 gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,
6233 tcg_regno, tcg_numregs);
6234 }
6235 tcg_temp_free_i64(tcg_idx);
6236 tcg_temp_free_i32(tcg_regno);
6237 tcg_temp_free_i32(tcg_numregs);
6238
6239 write_vec_element(s, tcg_resl, rd, 0, MO_64);
6240 tcg_temp_free_i64(tcg_resl);
6241 write_vec_element(s, tcg_resh, rd, 1, MO_64);
6242 tcg_temp_free_i64(tcg_resh);
6243 }
6244
6245 /* ZIP/UZP/TRN
6246 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6247 * +---+---+-------------+------+---+------+---+------------------+------+
6248 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6249 * +---+---+-------------+------+---+------+---+------------------+------+
6250 */
6251 static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
6252 {
6253 int rd = extract32(insn, 0, 5);
6254 int rn = extract32(insn, 5, 5);
6255 int rm = extract32(insn, 16, 5);
6256 int size = extract32(insn, 22, 2);
6257 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6258 * bit 2 indicates 1 vs 2 variant of the insn.
6259 */
6260 int opcode = extract32(insn, 12, 2);
6261 bool part = extract32(insn, 14, 1);
6262 bool is_q = extract32(insn, 30, 1);
6263 int esize = 8 << size;
6264 int i, ofs;
6265 int datasize = is_q ? 128 : 64;
6266 int elements = datasize / esize;
6267 TCGv_i64 tcg_res, tcg_resl, tcg_resh;
6268
6269 if (opcode == 0 || (size == 3 && !is_q)) {
6270 unallocated_encoding(s);
6271 return;
6272 }
6273
6274 if (!fp_access_check(s)) {
6275 return;
6276 }
6277
6278 tcg_resl = tcg_const_i64(0);
6279 tcg_resh = tcg_const_i64(0);
6280 tcg_res = tcg_temp_new_i64();
6281
6282 for (i = 0; i < elements; i++) {
6283 switch (opcode) {
6284 case 1: /* UZP1/2 */
6285 {
6286 int midpoint = elements / 2;
6287 if (i < midpoint) {
6288 read_vec_element(s, tcg_res, rn, 2 * i + part, size);
6289 } else {
6290 read_vec_element(s, tcg_res, rm,
6291 2 * (i - midpoint) + part, size);
6292 }
6293 break;
6294 }
6295 case 2: /* TRN1/2 */
6296 if (i & 1) {
6297 read_vec_element(s, tcg_res, rm, (i & ~1) + part, size);
6298 } else {
6299 read_vec_element(s, tcg_res, rn, (i & ~1) + part, size);
6300 }
6301 break;
6302 case 3: /* ZIP1/2 */
6303 {
6304 int base = part * elements / 2;
6305 if (i & 1) {
6306 read_vec_element(s, tcg_res, rm, base + (i >> 1), size);
6307 } else {
6308 read_vec_element(s, tcg_res, rn, base + (i >> 1), size);
6309 }
6310 break;
6311 }
6312 default:
6313 g_assert_not_reached();
6314 }
6315
6316 ofs = i * esize;
6317 if (ofs < 64) {
6318 tcg_gen_shli_i64(tcg_res, tcg_res, ofs);
6319 tcg_gen_or_i64(tcg_resl, tcg_resl, tcg_res);
6320 } else {
6321 tcg_gen_shli_i64(tcg_res, tcg_res, ofs - 64);
6322 tcg_gen_or_i64(tcg_resh, tcg_resh, tcg_res);
6323 }
6324 }
6325
6326 tcg_temp_free_i64(tcg_res);
6327
6328 write_vec_element(s, tcg_resl, rd, 0, MO_64);
6329 tcg_temp_free_i64(tcg_resl);
6330 write_vec_element(s, tcg_resh, rd, 1, MO_64);
6331 tcg_temp_free_i64(tcg_resh);
6332 }
6333
6334 /*
6335 * do_reduction_op helper
6336 *
6337 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6338 * important for correct NaN propagation that we do these
6339 * operations in exactly the order specified by the pseudocode.
6340 *
6341 * This is a recursive function, TCG temps should be freed by the
6342 * calling function once it is done with the values.
6343 */
6344 static TCGv_i32 do_reduction_op(DisasContext *s, int fpopcode, int rn,
6345 int esize, int size, int vmap, TCGv_ptr fpst)
6346 {
6347 if (esize == size) {
6348 int element;
6349 TCGMemOp msize = esize == 16 ? MO_16 : MO_32;
6350 TCGv_i32 tcg_elem;
6351
6352 /* We should have one register left here */
6353 assert(ctpop8(vmap) == 1);
6354 element = ctz32(vmap);
6355 assert(element < 8);
6356
6357 tcg_elem = tcg_temp_new_i32();
6358 read_vec_element_i32(s, tcg_elem, rn, element, msize);
6359 return tcg_elem;
6360 } else {
6361 int bits = size / 2;
6362 int shift = ctpop8(vmap) / 2;
6363 int vmap_lo = (vmap >> shift) & vmap;
6364 int vmap_hi = (vmap & ~vmap_lo);
6365 TCGv_i32 tcg_hi, tcg_lo, tcg_res;
6366
6367 tcg_hi = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_hi, fpst);
6368 tcg_lo = do_reduction_op(s, fpopcode, rn, esize, bits, vmap_lo, fpst);
6369 tcg_res = tcg_temp_new_i32();
6370
6371 switch (fpopcode) {
6372 case 0x0c: /* fmaxnmv half-precision */
6373 gen_helper_advsimd_maxnumh(tcg_res, tcg_lo, tcg_hi, fpst);
6374 break;
6375 case 0x0f: /* fmaxv half-precision */
6376 gen_helper_advsimd_maxh(tcg_res, tcg_lo, tcg_hi, fpst);
6377 break;
6378 case 0x1c: /* fminnmv half-precision */
6379 gen_helper_advsimd_minnumh(tcg_res, tcg_lo, tcg_hi, fpst);
6380 break;
6381 case 0x1f: /* fminv half-precision */
6382 gen_helper_advsimd_minh(tcg_res, tcg_lo, tcg_hi, fpst);
6383 break;
6384 case 0x2c: /* fmaxnmv */
6385 gen_helper_vfp_maxnums(tcg_res, tcg_lo, tcg_hi, fpst);
6386 break;
6387 case 0x2f: /* fmaxv */
6388 gen_helper_vfp_maxs(tcg_res, tcg_lo, tcg_hi, fpst);
6389 break;
6390 case 0x3c: /* fminnmv */
6391 gen_helper_vfp_minnums(tcg_res, tcg_lo, tcg_hi, fpst);
6392 break;
6393 case 0x3f: /* fminv */
6394 gen_helper_vfp_mins(tcg_res, tcg_lo, tcg_hi, fpst);
6395 break;
6396 default:
6397 g_assert_not_reached();
6398 }
6399
6400 tcg_temp_free_i32(tcg_hi);
6401 tcg_temp_free_i32(tcg_lo);
6402 return tcg_res;
6403 }
6404 }
6405
6406 /* AdvSIMD across lanes
6407 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6408 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6409 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6410 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6411 */
6412 static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
6413 {
6414 int rd = extract32(insn, 0, 5);
6415 int rn = extract32(insn, 5, 5);
6416 int size = extract32(insn, 22, 2);
6417 int opcode = extract32(insn, 12, 5);
6418 bool is_q = extract32(insn, 30, 1);
6419 bool is_u = extract32(insn, 29, 1);
6420 bool is_fp = false;
6421 bool is_min = false;
6422 int esize;
6423 int elements;
6424 int i;
6425 TCGv_i64 tcg_res, tcg_elt;
6426
6427 switch (opcode) {
6428 case 0x1b: /* ADDV */
6429 if (is_u) {
6430 unallocated_encoding(s);
6431 return;
6432 }
6433 /* fall through */
6434 case 0x3: /* SADDLV, UADDLV */
6435 case 0xa: /* SMAXV, UMAXV */
6436 case 0x1a: /* SMINV, UMINV */
6437 if (size == 3 || (size == 2 && !is_q)) {
6438 unallocated_encoding(s);
6439 return;
6440 }
6441 break;
6442 case 0xc: /* FMAXNMV, FMINNMV */
6443 case 0xf: /* FMAXV, FMINV */
6444 /* Bit 1 of size field encodes min vs max and the actual size
6445 * depends on the encoding of the U bit. If not set (and FP16
6446 * enabled) then we do half-precision float instead of single
6447 * precision.
6448 */
6449 is_min = extract32(size, 1, 1);
6450 is_fp = true;
6451 if (!is_u && arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
6452 size = 1;
6453 } else if (!is_u || !is_q || extract32(size, 0, 1)) {
6454 unallocated_encoding(s);
6455 return;
6456 } else {
6457 size = 2;
6458 }
6459 break;
6460 default:
6461 unallocated_encoding(s);
6462 return;
6463 }
6464
6465 if (!fp_access_check(s)) {
6466 return;
6467 }
6468
6469 esize = 8 << size;
6470 elements = (is_q ? 128 : 64) / esize;
6471
6472 tcg_res = tcg_temp_new_i64();
6473 tcg_elt = tcg_temp_new_i64();
6474
6475 /* These instructions operate across all lanes of a vector
6476 * to produce a single result. We can guarantee that a 64
6477 * bit intermediate is sufficient:
6478 * + for [US]ADDLV the maximum element size is 32 bits, and
6479 * the result type is 64 bits
6480 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
6481 * same as the element size, which is 32 bits at most
6482 * For the integer operations we can choose to work at 64
6483 * or 32 bits and truncate at the end; for simplicity
6484 * we use 64 bits always. The floating point
6485 * ops do require 32 bit intermediates, though.
6486 */
6487 if (!is_fp) {
6488 read_vec_element(s, tcg_res, rn, 0, size | (is_u ? 0 : MO_SIGN));
6489
6490 for (i = 1; i < elements; i++) {
6491 read_vec_element(s, tcg_elt, rn, i, size | (is_u ? 0 : MO_SIGN));
6492
6493 switch (opcode) {
6494 case 0x03: /* SADDLV / UADDLV */
6495 case 0x1b: /* ADDV */
6496 tcg_gen_add_i64(tcg_res, tcg_res, tcg_elt);
6497 break;
6498 case 0x0a: /* SMAXV / UMAXV */
6499 if (is_u) {
6500 tcg_gen_umax_i64(tcg_res, tcg_res, tcg_elt);
6501 } else {
6502 tcg_gen_smax_i64(tcg_res, tcg_res, tcg_elt);
6503 }
6504 break;
6505 case 0x1a: /* SMINV / UMINV */
6506 if (is_u) {
6507 tcg_gen_umin_i64(tcg_res, tcg_res, tcg_elt);
6508 } else {
6509 tcg_gen_smin_i64(tcg_res, tcg_res, tcg_elt);
6510 }
6511 break;
6512 default:
6513 g_assert_not_reached();
6514 }
6515
6516 }
6517 } else {
6518 /* Floating point vector reduction ops which work across 32
6519 * bit (single) or 16 bit (half-precision) intermediates.
6520 * Note that correct NaN propagation requires that we do these
6521 * operations in exactly the order specified by the pseudocode.
6522 */
6523 TCGv_ptr fpst = get_fpstatus_ptr(size == MO_16);
6524 int fpopcode = opcode | is_min << 4 | is_u << 5;
6525 int vmap = (1 << elements) - 1;
6526 TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
6527 (is_q ? 128 : 64), vmap, fpst);
6528 tcg_gen_extu_i32_i64(tcg_res, tcg_res32);
6529 tcg_temp_free_i32(tcg_res32);
6530 tcg_temp_free_ptr(fpst);
6531 }
6532
6533 tcg_temp_free_i64(tcg_elt);
6534
6535 /* Now truncate the result to the width required for the final output */
6536 if (opcode == 0x03) {
6537 /* SADDLV, UADDLV: result is 2*esize */
6538 size++;
6539 }
6540
6541 switch (size) {
6542 case 0:
6543 tcg_gen_ext8u_i64(tcg_res, tcg_res);
6544 break;
6545 case 1:
6546 tcg_gen_ext16u_i64(tcg_res, tcg_res);
6547 break;
6548 case 2:
6549 tcg_gen_ext32u_i64(tcg_res, tcg_res);
6550 break;
6551 case 3:
6552 break;
6553 default:
6554 g_assert_not_reached();
6555 }
6556
6557 write_fp_dreg(s, rd, tcg_res);
6558 tcg_temp_free_i64(tcg_res);
6559 }
6560
6561 /* DUP (Element, Vector)
6562 *
6563 * 31 30 29 21 20 16 15 10 9 5 4 0
6564 * +---+---+-------------------+--------+-------------+------+------+
6565 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6566 * +---+---+-------------------+--------+-------------+------+------+
6567 *
6568 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6569 */
6570 static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
6571 int imm5)
6572 {
6573 int size = ctz32(imm5);
6574 int index = imm5 >> (size + 1);
6575
6576 if (size > 3 || (size == 3 && !is_q)) {
6577 unallocated_encoding(s);
6578 return;
6579 }
6580
6581 if (!fp_access_check(s)) {
6582 return;
6583 }
6584
6585 tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd),
6586 vec_reg_offset(s, rn, index, size),
6587 is_q ? 16 : 8, vec_full_reg_size(s));
6588 }
6589
6590 /* DUP (element, scalar)
6591 * 31 21 20 16 15 10 9 5 4 0
6592 * +-----------------------+--------+-------------+------+------+
6593 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
6594 * +-----------------------+--------+-------------+------+------+
6595 */
6596 static void handle_simd_dupes(DisasContext *s, int rd, int rn,
6597 int imm5)
6598 {
6599 int size = ctz32(imm5);
6600 int index;
6601 TCGv_i64 tmp;
6602
6603 if (size > 3) {
6604 unallocated_encoding(s);
6605 return;
6606 }
6607
6608 if (!fp_access_check(s)) {
6609 return;
6610 }
6611
6612 index = imm5 >> (size + 1);
6613
6614 /* This instruction just extracts the specified element and
6615 * zero-extends it into the bottom of the destination register.
6616 */
6617 tmp = tcg_temp_new_i64();
6618 read_vec_element(s, tmp, rn, index, size);
6619 write_fp_dreg(s, rd, tmp);
6620 tcg_temp_free_i64(tmp);
6621 }
6622
6623 /* DUP (General)
6624 *
6625 * 31 30 29 21 20 16 15 10 9 5 4 0
6626 * +---+---+-------------------+--------+-------------+------+------+
6627 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
6628 * +---+---+-------------------+--------+-------------+------+------+
6629 *
6630 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6631 */
6632 static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
6633 int imm5)
6634 {
6635 int size = ctz32(imm5);
6636 uint32_t dofs, oprsz, maxsz;
6637
6638 if (size > 3 || ((size == 3) && !is_q)) {
6639 unallocated_encoding(s);
6640 return;
6641 }
6642
6643 if (!fp_access_check(s)) {
6644 return;
6645 }
6646
6647 dofs = vec_full_reg_offset(s, rd);
6648 oprsz = is_q ? 16 : 8;
6649 maxsz = vec_full_reg_size(s);
6650
6651 tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn));
6652 }
6653
6654 /* INS (Element)
6655 *
6656 * 31 21 20 16 15 14 11 10 9 5 4 0
6657 * +-----------------------+--------+------------+---+------+------+
6658 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6659 * +-----------------------+--------+------------+---+------+------+
6660 *
6661 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6662 * index: encoded in imm5<4:size+1>
6663 */
6664 static void handle_simd_inse(DisasContext *s, int rd, int rn,
6665 int imm4, int imm5)
6666 {
6667 int size = ctz32(imm5);
6668 int src_index, dst_index;
6669 TCGv_i64 tmp;
6670
6671 if (size > 3) {
6672 unallocated_encoding(s);
6673 return;
6674 }
6675
6676 if (!fp_access_check(s)) {
6677 return;
6678 }
6679
6680 dst_index = extract32(imm5, 1+size, 5);
6681 src_index = extract32(imm4, size, 4);
6682
6683 tmp = tcg_temp_new_i64();
6684
6685 read_vec_element(s, tmp, rn, src_index, size);
6686 write_vec_element(s, tmp, rd, dst_index, size);
6687
6688 tcg_temp_free_i64(tmp);
6689 }
6690
6691
6692 /* INS (General)
6693 *
6694 * 31 21 20 16 15 10 9 5 4 0
6695 * +-----------------------+--------+-------------+------+------+
6696 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
6697 * +-----------------------+--------+-------------+------+------+
6698 *
6699 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6700 * index: encoded in imm5<4:size+1>
6701 */
6702 static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
6703 {
6704 int size = ctz32(imm5);
6705 int idx;
6706
6707 if (size > 3) {
6708 unallocated_encoding(s);
6709 return;
6710 }
6711
6712 if (!fp_access_check(s)) {
6713 return;
6714 }
6715
6716 idx = extract32(imm5, 1 + size, 4 - size);
6717 write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
6718 }
6719
6720 /*
6721 * UMOV (General)
6722 * SMOV (General)
6723 *
6724 * 31 30 29 21 20 16 15 12 10 9 5 4 0
6725 * +---+---+-------------------+--------+-------------+------+------+
6726 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
6727 * +---+---+-------------------+--------+-------------+------+------+
6728 *
6729 * U: unsigned when set
6730 * size: encoded in imm5 (see ARM ARM LowestSetBit())
6731 */
6732 static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
6733 int rn, int rd, int imm5)
6734 {
6735 int size = ctz32(imm5);
6736 int element;
6737 TCGv_i64 tcg_rd;
6738
6739 /* Check for UnallocatedEncodings */
6740 if (is_signed) {
6741 if (size > 2 || (size == 2 && !is_q)) {
6742 unallocated_encoding(s);
6743 return;
6744 }
6745 } else {
6746 if (size > 3
6747 || (size < 3 && is_q)
6748 || (size == 3 && !is_q)) {
6749 unallocated_encoding(s);
6750 return;
6751 }
6752 }
6753
6754 if (!fp_access_check(s)) {
6755 return;
6756 }
6757
6758 element = extract32(imm5, 1+size, 4);
6759
6760 tcg_rd = cpu_reg(s, rd);
6761 read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0));
6762 if (is_signed && !is_q) {
6763 tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
6764 }
6765 }
6766
6767 /* AdvSIMD copy
6768 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6769 * +---+---+----+-----------------+------+---+------+---+------+------+
6770 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6771 * +---+---+----+-----------------+------+---+------+---+------+------+
6772 */
6773 static void disas_simd_copy(DisasContext *s, uint32_t insn)
6774 {
6775 int rd = extract32(insn, 0, 5);
6776 int rn = extract32(insn, 5, 5);
6777 int imm4 = extract32(insn, 11, 4);
6778 int op = extract32(insn, 29, 1);
6779 int is_q = extract32(insn, 30, 1);
6780 int imm5 = extract32(insn, 16, 5);
6781
6782 if (op) {
6783 if (is_q) {
6784 /* INS (element) */
6785 handle_simd_inse(s, rd, rn, imm4, imm5);
6786 } else {
6787 unallocated_encoding(s);
6788 }
6789 } else {
6790 switch (imm4) {
6791 case 0:
6792 /* DUP (element - vector) */
6793 handle_simd_dupe(s, is_q, rd, rn, imm5);
6794 break;
6795 case 1:
6796 /* DUP (general) */
6797 handle_simd_dupg(s, is_q, rd, rn, imm5);
6798 break;
6799 case 3:
6800 if (is_q) {
6801 /* INS (general) */
6802 handle_simd_insg(s, rd, rn, imm5);
6803 } else {
6804 unallocated_encoding(s);
6805 }
6806 break;
6807 case 5:
6808 case 7:
6809 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
6810 handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5);
6811 break;
6812 default:
6813 unallocated_encoding(s);
6814 break;
6815 }
6816 }
6817 }
6818
6819 /* AdvSIMD modified immediate
6820 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
6821 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6822 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
6823 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
6824 *
6825 * There are a number of operations that can be carried out here:
6826 * MOVI - move (shifted) imm into register
6827 * MVNI - move inverted (shifted) imm into register
6828 * ORR - bitwise OR of (shifted) imm with register
6829 * BIC - bitwise clear of (shifted) imm with register
6830 * With ARMv8.2 we also have:
6831 * FMOV half-precision
6832 */
6833 static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
6834 {
6835 int rd = extract32(insn, 0, 5);
6836 int cmode = extract32(insn, 12, 4);
6837 int cmode_3_1 = extract32(cmode, 1, 3);
6838 int cmode_0 = extract32(cmode, 0, 1);
6839 int o2 = extract32(insn, 11, 1);
6840 uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
6841 bool is_neg = extract32(insn, 29, 1);
6842 bool is_q = extract32(insn, 30, 1);
6843 uint64_t imm = 0;
6844
6845 if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
6846 /* Check for FMOV (vector, immediate) - half-precision */
6847 if (!(arm_dc_feature(s, ARM_FEATURE_V8_FP16) && o2 && cmode == 0xf)) {
6848 unallocated_encoding(s);
6849 return;
6850 }
6851 }
6852
6853 if (!fp_access_check(s)) {
6854 return;
6855 }
6856
6857 /* See AdvSIMDExpandImm() in ARM ARM */
6858 switch (cmode_3_1) {
6859 case 0: /* Replicate(Zeros(24):imm8, 2) */
6860 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
6861 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
6862 case 3: /* Replicate(imm8:Zeros(24), 2) */
6863 {
6864 int shift = cmode_3_1 * 8;
6865 imm = bitfield_replicate(abcdefgh << shift, 32);
6866 break;
6867 }
6868 case 4: /* Replicate(Zeros(8):imm8, 4) */
6869 case 5: /* Replicate(imm8:Zeros(8), 4) */
6870 {
6871 int shift = (cmode_3_1 & 0x1) * 8;
6872 imm = bitfield_replicate(abcdefgh << shift, 16);
6873 break;
6874 }
6875 case 6:
6876 if (cmode_0) {
6877 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
6878 imm = (abcdefgh << 16) | 0xffff;
6879 } else {
6880 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
6881 imm = (abcdefgh << 8) | 0xff;
6882 }
6883 imm = bitfield_replicate(imm, 32);
6884 break;
6885 case 7:
6886 if (!cmode_0 && !is_neg) {
6887 imm = bitfield_replicate(abcdefgh, 8);
6888 } else if (!cmode_0 && is_neg) {
6889 int i;
6890 imm = 0;
6891 for (i = 0; i < 8; i++) {
6892 if ((abcdefgh) & (1 << i)) {
6893 imm |= 0xffULL << (i * 8);
6894 }
6895 }
6896 } else if (cmode_0) {
6897 if (is_neg) {
6898 imm = (abcdefgh & 0x3f) << 48;
6899 if (abcdefgh & 0x80) {
6900 imm |= 0x8000000000000000ULL;
6901 }
6902 if (abcdefgh & 0x40) {
6903 imm |= 0x3fc0000000000000ULL;
6904 } else {
6905 imm |= 0x4000000000000000ULL;
6906 }
6907 } else {
6908 if (o2) {
6909 /* FMOV (vector, immediate) - half-precision */
6910 imm = vfp_expand_imm(MO_16, abcdefgh);
6911 /* now duplicate across the lanes */
6912 imm = bitfield_replicate(imm, 16);
6913 } else {
6914 imm = (abcdefgh & 0x3f) << 19;
6915 if (abcdefgh & 0x80) {
6916 imm |= 0x80000000;
6917 }
6918 if (abcdefgh & 0x40) {
6919 imm |= 0x3e000000;
6920 } else {
6921 imm |= 0x40000000;
6922 }
6923 imm |= (imm << 32);
6924 }
6925 }
6926 }
6927 break;
6928 default:
6929 fprintf(stderr, "%s: cmode_3_1: %x\n", __func__, cmode_3_1);
6930 g_assert_not_reached();
6931 }
6932
6933 if (cmode_3_1 != 7 && is_neg) {
6934 imm = ~imm;
6935 }
6936
6937 if (!((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9)) {
6938 /* MOVI or MVNI, with MVNI negation handled above. */
6939 tcg_gen_gvec_dup64i(vec_full_reg_offset(s, rd), is_q ? 16 : 8,
6940 vec_full_reg_size(s), imm);
6941 } else {
6942 /* ORR or BIC, with BIC negation to AND handled above. */
6943 if (is_neg) {
6944 gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_andi, MO_64);
6945 } else {
6946 gen_gvec_fn2i(s, is_q, rd, rd, imm, tcg_gen_gvec_ori, MO_64);
6947 }
6948 }
6949 }
6950
6951 /* AdvSIMD scalar copy
6952 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
6953 * +-----+----+-----------------+------+---+------+---+------+------+
6954 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
6955 * +-----+----+-----------------+------+---+------+---+------+------+
6956 */
6957 static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
6958 {
6959 int rd = extract32(insn, 0, 5);
6960 int rn = extract32(insn, 5, 5);
6961 int imm4 = extract32(insn, 11, 4);
6962 int imm5 = extract32(insn, 16, 5);
6963 int op = extract32(insn, 29, 1);
6964
6965 if (op != 0 || imm4 != 0) {
6966 unallocated_encoding(s);
6967 return;
6968 }
6969
6970 /* DUP (element, scalar) */
6971 handle_simd_dupes(s, rd, rn, imm5);
6972 }
6973
6974 /* AdvSIMD scalar pairwise
6975 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6976 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6977 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6978 * +-----+---+-----------+------+-----------+--------+-----+------+------+
6979 */
6980 static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
6981 {
6982 int u = extract32(insn, 29, 1);
6983 int size = extract32(insn, 22, 2);
6984 int opcode = extract32(insn, 12, 5);
6985 int rn = extract32(insn, 5, 5);
6986 int rd = extract32(insn, 0, 5);
6987 TCGv_ptr fpst;
6988
6989 /* For some ops (the FP ones), size[1] is part of the encoding.
6990 * For ADDP strictly it is not but size[1] is always 1 for valid
6991 * encodings.
6992 */
6993 opcode |= (extract32(size, 1, 1) << 5);
6994
6995 switch (opcode) {
6996 case 0x3b: /* ADDP */
6997 if (u || size != 3) {
6998 unallocated_encoding(s);
6999 return;
7000 }
7001 if (!fp_access_check(s)) {
7002 return;
7003 }
7004
7005 fpst = NULL;
7006 break;
7007 case 0xc: /* FMAXNMP */
7008 case 0xd: /* FADDP */
7009 case 0xf: /* FMAXP */
7010 case 0x2c: /* FMINNMP */
7011 case 0x2f: /* FMINP */
7012 /* FP op, size[0] is 32 or 64 bit*/
7013 if (!u) {
7014 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
7015 unallocated_encoding(s);
7016 return;
7017 } else {
7018 size = MO_16;
7019 }
7020 } else {
7021 size = extract32(size, 0, 1) ? MO_64 : MO_32;
7022 }
7023
7024 if (!fp_access_check(s)) {
7025 return;
7026 }
7027
7028 fpst = get_fpstatus_ptr(size == MO_16);
7029 break;
7030 default:
7031 unallocated_encoding(s);
7032 return;
7033 }
7034
7035 if (size == MO_64) {
7036 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
7037 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
7038 TCGv_i64 tcg_res = tcg_temp_new_i64();
7039
7040 read_vec_element(s, tcg_op1, rn, 0, MO_64);
7041 read_vec_element(s, tcg_op2, rn, 1, MO_64);
7042
7043 switch (opcode) {
7044 case 0x3b: /* ADDP */
7045 tcg_gen_add_i64(tcg_res, tcg_op1, tcg_op2);
7046 break;
7047 case 0xc: /* FMAXNMP */
7048 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
7049 break;
7050 case 0xd: /* FADDP */
7051 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
7052 break;
7053 case 0xf: /* FMAXP */
7054 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
7055 break;
7056 case 0x2c: /* FMINNMP */
7057 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
7058 break;
7059 case 0x2f: /* FMINP */
7060 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
7061 break;
7062 default:
7063 g_assert_not_reached();
7064 }
7065
7066 write_fp_dreg(s, rd, tcg_res);
7067
7068 tcg_temp_free_i64(tcg_op1);
7069 tcg_temp_free_i64(tcg_op2);
7070 tcg_temp_free_i64(tcg_res);
7071 } else {
7072 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
7073 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
7074 TCGv_i32 tcg_res = tcg_temp_new_i32();
7075
7076 read_vec_element_i32(s, tcg_op1, rn, 0, size);
7077 read_vec_element_i32(s, tcg_op2, rn, 1, size);
7078
7079 if (size == MO_16) {
7080 switch (opcode) {
7081 case 0xc: /* FMAXNMP */
7082 gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
7083 break;
7084 case 0xd: /* FADDP */
7085 gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
7086 break;
7087 case 0xf: /* FMAXP */
7088 gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
7089 break;
7090 case 0x2c: /* FMINNMP */
7091 gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
7092 break;
7093 case 0x2f: /* FMINP */
7094 gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
7095 break;
7096 default:
7097 g_assert_not_reached();
7098 }
7099 } else {
7100 switch (opcode) {
7101 case 0xc: /* FMAXNMP */
7102 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
7103 break;
7104 case 0xd: /* FADDP */
7105 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
7106 break;
7107 case 0xf: /* FMAXP */
7108 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
7109 break;
7110 case 0x2c: /* FMINNMP */
7111 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
7112 break;
7113 case 0x2f: /* FMINP */
7114 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
7115 break;
7116 default:
7117 g_assert_not_reached();
7118 }
7119 }
7120
7121 write_fp_sreg(s, rd, tcg_res);
7122
7123 tcg_temp_free_i32(tcg_op1);
7124 tcg_temp_free_i32(tcg_op2);
7125 tcg_temp_free_i32(tcg_res);
7126 }
7127
7128 if (fpst) {
7129 tcg_temp_free_ptr(fpst);
7130 }
7131 }
7132
7133 /*
7134 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7135 *
7136 * This code is handles the common shifting code and is used by both
7137 * the vector and scalar code.
7138 */
7139 static void handle_shri_with_rndacc(TCGv_i64 tcg_res, TCGv_i64 tcg_src,
7140 TCGv_i64 tcg_rnd, bool accumulate,
7141 bool is_u, int size, int shift)
7142 {
7143 bool extended_result = false;
7144 bool round = tcg_rnd != NULL;
7145 int ext_lshift = 0;
7146 TCGv_i64 tcg_src_hi;
7147
7148 if (round && size == 3) {
7149 extended_result = true;
7150 ext_lshift = 64 - shift;
7151 tcg_src_hi = tcg_temp_new_i64();
7152 } else if (shift == 64) {
7153 if (!accumulate && is_u) {
7154 /* result is zero */
7155 tcg_gen_movi_i64(tcg_res, 0);
7156 return;
7157 }
7158 }
7159
7160 /* Deal with the rounding step */
7161 if (round) {
7162 if (extended_result) {
7163 TCGv_i64 tcg_zero = tcg_const_i64(0);
7164 if (!is_u) {
7165 /* take care of sign extending tcg_res */
7166 tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63);
7167 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
7168 tcg_src, tcg_src_hi,
7169 tcg_rnd, tcg_zero);
7170 } else {
7171 tcg_gen_add2_i64(tcg_src, tcg_src_hi,
7172 tcg_src, tcg_zero,
7173 tcg_rnd, tcg_zero);
7174 }
7175 tcg_temp_free_i64(tcg_zero);
7176 } else {
7177 tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd);
7178 }
7179 }
7180
7181 /* Now do the shift right */
7182 if (round && extended_result) {
7183 /* extended case, >64 bit precision required */
7184 if (ext_lshift == 0) {
7185 /* special case, only high bits matter */
7186 tcg_gen_mov_i64(tcg_src, tcg_src_hi);
7187 } else {
7188 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
7189 tcg_gen_shli_i64(tcg_src_hi, tcg_src_hi, ext_lshift);
7190 tcg_gen_or_i64(tcg_src, tcg_src, tcg_src_hi);
7191 }
7192 } else {
7193 if (is_u) {
7194 if (shift == 64) {
7195 /* essentially shifting in 64 zeros */
7196 tcg_gen_movi_i64(tcg_src, 0);
7197 } else {
7198 tcg_gen_shri_i64(tcg_src, tcg_src, shift);
7199 }
7200 } else {
7201 if (shift == 64) {
7202 /* effectively extending the sign-bit */
7203 tcg_gen_sari_i64(tcg_src, tcg_src, 63);
7204 } else {
7205 tcg_gen_sari_i64(tcg_src, tcg_src, shift);
7206 }
7207 }
7208 }
7209
7210 if (accumulate) {
7211 tcg_gen_add_i64(tcg_res, tcg_res, tcg_src);
7212 } else {
7213 tcg_gen_mov_i64(tcg_res, tcg_src);
7214 }
7215
7216 if (extended_result) {
7217 tcg_temp_free_i64(tcg_src_hi);
7218 }
7219 }
7220
7221 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7222 static void handle_scalar_simd_shri(DisasContext *s,
7223 bool is_u, int immh, int immb,
7224 int opcode, int rn, int rd)
7225 {
7226 const int size = 3;
7227 int immhb = immh << 3 | immb;
7228 int shift = 2 * (8 << size) - immhb;
7229 bool accumulate = false;
7230 bool round = false;
7231 bool insert = false;
7232 TCGv_i64 tcg_rn;
7233 TCGv_i64 tcg_rd;
7234 TCGv_i64 tcg_round;
7235
7236 if (!extract32(immh, 3, 1)) {
7237 unallocated_encoding(s);
7238 return;
7239 }
7240
7241 if (!fp_access_check(s)) {
7242 return;
7243 }
7244
7245 switch (opcode) {
7246 case 0x02: /* SSRA / USRA (accumulate) */
7247 accumulate = true;
7248 break;
7249 case 0x04: /* SRSHR / URSHR (rounding) */
7250 round = true;
7251 break;
7252 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7253 accumulate = round = true;
7254 break;
7255 case 0x08: /* SRI */
7256 insert = true;
7257 break;
7258 }
7259
7260 if (round) {
7261 uint64_t round_const = 1ULL << (shift - 1);
7262 tcg_round = tcg_const_i64(round_const);
7263 } else {
7264 tcg_round = NULL;
7265 }
7266
7267 tcg_rn = read_fp_dreg(s, rn);
7268 tcg_rd = (accumulate || insert) ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
7269
7270 if (insert) {
7271 /* shift count same as element size is valid but does nothing;
7272 * special case to avoid potential shift by 64.
7273 */
7274 int esize = 8 << size;
7275 if (shift != esize) {
7276 tcg_gen_shri_i64(tcg_rn, tcg_rn, shift);
7277 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, 0, esize - shift);
7278 }
7279 } else {
7280 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
7281 accumulate, is_u, size, shift);
7282 }
7283
7284 write_fp_dreg(s, rd, tcg_rd);
7285
7286 tcg_temp_free_i64(tcg_rn);
7287 tcg_temp_free_i64(tcg_rd);
7288 if (round) {
7289 tcg_temp_free_i64(tcg_round);
7290 }
7291 }
7292
7293 /* SHL/SLI - Scalar shift left */
7294 static void handle_scalar_simd_shli(DisasContext *s, bool insert,
7295 int immh, int immb, int opcode,
7296 int rn, int rd)
7297 {
7298 int size = 32 - clz32(immh) - 1;
7299 int immhb = immh << 3 | immb;
7300 int shift = immhb - (8 << size);
7301 TCGv_i64 tcg_rn = new_tmp_a64(s);
7302 TCGv_i64 tcg_rd = new_tmp_a64(s);
7303
7304 if (!extract32(immh, 3, 1)) {
7305 unallocated_encoding(s);
7306 return;
7307 }
7308
7309 if (!fp_access_check(s)) {
7310 return;
7311 }
7312
7313 tcg_rn = read_fp_dreg(s, rn);
7314 tcg_rd = insert ? read_fp_dreg(s, rd) : tcg_temp_new_i64();
7315
7316 if (insert) {
7317 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, shift, 64 - shift);
7318 } else {
7319 tcg_gen_shli_i64(tcg_rd, tcg_rn, shift);
7320 }
7321
7322 write_fp_dreg(s, rd, tcg_rd);
7323
7324 tcg_temp_free_i64(tcg_rn);
7325 tcg_temp_free_i64(tcg_rd);
7326 }
7327
7328 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7329 * (signed/unsigned) narrowing */
7330 static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q,
7331 bool is_u_shift, bool is_u_narrow,
7332 int immh, int immb, int opcode,
7333 int rn, int rd)
7334 {
7335 int immhb = immh << 3 | immb;
7336 int size = 32 - clz32(immh) - 1;
7337 int esize = 8 << size;
7338 int shift = (2 * esize) - immhb;
7339 int elements = is_scalar ? 1 : (64 / esize);
7340 bool round = extract32(opcode, 0, 1);
7341 TCGMemOp ldop = (size + 1) | (is_u_shift ? 0 : MO_SIGN);
7342 TCGv_i64 tcg_rn, tcg_rd, tcg_round;
7343 TCGv_i32 tcg_rd_narrowed;
7344 TCGv_i64 tcg_final;
7345
7346 static NeonGenNarrowEnvFn * const signed_narrow_fns[4][2] = {
7347 { gen_helper_neon_narrow_sat_s8,
7348 gen_helper_neon_unarrow_sat8 },
7349 { gen_helper_neon_narrow_sat_s16,
7350 gen_helper_neon_unarrow_sat16 },
7351 { gen_helper_neon_narrow_sat_s32,
7352 gen_helper_neon_unarrow_sat32 },
7353 { NULL, NULL },
7354 };
7355 static NeonGenNarrowEnvFn * const unsigned_narrow_fns[4] = {
7356 gen_helper_neon_narrow_sat_u8,
7357 gen_helper_neon_narrow_sat_u16,
7358 gen_helper_neon_narrow_sat_u32,
7359 NULL
7360 };
7361 NeonGenNarrowEnvFn *narrowfn;
7362
7363 int i;
7364
7365 assert(size < 4);
7366
7367 if (extract32(immh, 3, 1)) {
7368 unallocated_encoding(s);
7369 return;
7370 }
7371
7372 if (!fp_access_check(s)) {
7373 return;
7374 }
7375
7376 if (is_u_shift) {
7377 narrowfn = unsigned_narrow_fns[size];
7378 } else {
7379 narrowfn = signed_narrow_fns[size][is_u_narrow ? 1 : 0];
7380 }
7381
7382 tcg_rn = tcg_temp_new_i64();
7383 tcg_rd = tcg_temp_new_i64();
7384 tcg_rd_narrowed = tcg_temp_new_i32();
7385 tcg_final = tcg_const_i64(0);
7386
7387 if (round) {
7388 uint64_t round_const = 1ULL << (shift - 1);
7389 tcg_round = tcg_const_i64(round_const);
7390 } else {
7391 tcg_round = NULL;
7392 }
7393
7394 for (i = 0; i < elements; i++) {
7395 read_vec_element(s, tcg_rn, rn, i, ldop);
7396 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
7397 false, is_u_shift, size+1, shift);
7398 narrowfn(tcg_rd_narrowed, cpu_env, tcg_rd);
7399 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed);
7400 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
7401 }
7402
7403 if (!is_q) {
7404 write_vec_element(s, tcg_final, rd, 0, MO_64);
7405 } else {
7406 write_vec_element(s, tcg_final, rd, 1, MO_64);
7407 }
7408
7409 if (round) {
7410 tcg_temp_free_i64(tcg_round);
7411 }
7412 tcg_temp_free_i64(tcg_rn);
7413 tcg_temp_free_i64(tcg_rd);
7414 tcg_temp_free_i32(tcg_rd_narrowed);
7415 tcg_temp_free_i64(tcg_final);
7416
7417 clear_vec_high(s, is_q, rd);
7418 }
7419
7420 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7421 static void handle_simd_qshl(DisasContext *s, bool scalar, bool is_q,
7422 bool src_unsigned, bool dst_unsigned,
7423 int immh, int immb, int rn, int rd)
7424 {
7425 int immhb = immh << 3 | immb;
7426 int size = 32 - clz32(immh) - 1;
7427 int shift = immhb - (8 << size);
7428 int pass;
7429
7430 assert(immh != 0);
7431 assert(!(scalar && is_q));
7432
7433 if (!scalar) {
7434 if (!is_q && extract32(immh, 3, 1)) {
7435 unallocated_encoding(s);
7436 return;
7437 }
7438
7439 /* Since we use the variable-shift helpers we must
7440 * replicate the shift count into each element of
7441 * the tcg_shift value.
7442 */
7443 switch (size) {
7444 case 0:
7445 shift |= shift << 8;
7446 /* fall through */
7447 case 1:
7448 shift |= shift << 16;
7449 break;
7450 case 2:
7451 case 3:
7452 break;
7453 default:
7454 g_assert_not_reached();
7455 }
7456 }
7457
7458 if (!fp_access_check(s)) {
7459 return;
7460 }
7461
7462 if (size == 3) {
7463 TCGv_i64 tcg_shift = tcg_const_i64(shift);
7464 static NeonGenTwo64OpEnvFn * const fns[2][2] = {
7465 { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 },
7466 { NULL, gen_helper_neon_qshl_u64 },
7467 };
7468 NeonGenTwo64OpEnvFn *genfn = fns[src_unsigned][dst_unsigned];
7469 int maxpass = is_q ? 2 : 1;
7470
7471 for (pass = 0; pass < maxpass; pass++) {
7472 TCGv_i64 tcg_op = tcg_temp_new_i64();
7473
7474 read_vec_element(s, tcg_op, rn, pass, MO_64);
7475 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
7476 write_vec_element(s, tcg_op, rd, pass, MO_64);
7477
7478 tcg_temp_free_i64(tcg_op);
7479 }
7480 tcg_temp_free_i64(tcg_shift);
7481 clear_vec_high(s, is_q, rd);
7482 } else {
7483 TCGv_i32 tcg_shift = tcg_const_i32(shift);
7484 static NeonGenTwoOpEnvFn * const fns[2][2][3] = {
7485 {
7486 { gen_helper_neon_qshl_s8,
7487 gen_helper_neon_qshl_s16,
7488 gen_helper_neon_qshl_s32 },
7489 { gen_helper_neon_qshlu_s8,
7490 gen_helper_neon_qshlu_s16,
7491 gen_helper_neon_qshlu_s32 }
7492 }, {
7493 { NULL, NULL, NULL },
7494 { gen_helper_neon_qshl_u8,
7495 gen_helper_neon_qshl_u16,
7496 gen_helper_neon_qshl_u32 }
7497 }
7498 };
7499 NeonGenTwoOpEnvFn *genfn = fns[src_unsigned][dst_unsigned][size];
7500 TCGMemOp memop = scalar ? size : MO_32;
7501 int maxpass = scalar ? 1 : is_q ? 4 : 2;
7502
7503 for (pass = 0; pass < maxpass; pass++) {
7504 TCGv_i32 tcg_op = tcg_temp_new_i32();
7505
7506 read_vec_element_i32(s, tcg_op, rn, pass, memop);
7507 genfn(tcg_op, cpu_env, tcg_op, tcg_shift);
7508 if (scalar) {
7509 switch (size) {
7510 case 0:
7511 tcg_gen_ext8u_i32(tcg_op, tcg_op);
7512 break;
7513 case 1:
7514 tcg_gen_ext16u_i32(tcg_op, tcg_op);
7515 break;
7516 case 2:
7517 break;
7518 default:
7519 g_assert_not_reached();
7520 }
7521 write_fp_sreg(s, rd, tcg_op);
7522 } else {
7523 write_vec_element_i32(s, tcg_op, rd, pass, MO_32);
7524 }
7525
7526 tcg_temp_free_i32(tcg_op);
7527 }
7528 tcg_temp_free_i32(tcg_shift);
7529
7530 if (!scalar) {
7531 clear_vec_high(s, is_q, rd);
7532 }
7533 }
7534 }
7535
7536 /* Common vector code for handling integer to FP conversion */
7537 static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
7538 int elements, int is_signed,
7539 int fracbits, int size)
7540 {
7541 TCGv_ptr tcg_fpst = get_fpstatus_ptr(size == MO_16);
7542 TCGv_i32 tcg_shift = NULL;
7543
7544 TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
7545 int pass;
7546
7547 if (fracbits || size == MO_64) {
7548 tcg_shift = tcg_const_i32(fracbits);
7549 }
7550
7551 if (size == MO_64) {
7552 TCGv_i64 tcg_int64 = tcg_temp_new_i64();
7553 TCGv_i64 tcg_double = tcg_temp_new_i64();
7554
7555 for (pass = 0; pass < elements; pass++) {
7556 read_vec_element(s, tcg_int64, rn, pass, mop);
7557
7558 if (is_signed) {
7559 gen_helper_vfp_sqtod(tcg_double, tcg_int64,
7560 tcg_shift, tcg_fpst);
7561 } else {
7562 gen_helper_vfp_uqtod(tcg_double, tcg_int64,
7563 tcg_shift, tcg_fpst);
7564 }
7565 if (elements == 1) {
7566 write_fp_dreg(s, rd, tcg_double);
7567 } else {
7568 write_vec_element(s, tcg_double, rd, pass, MO_64);
7569 }
7570 }
7571
7572 tcg_temp_free_i64(tcg_int64);
7573 tcg_temp_free_i64(tcg_double);
7574
7575 } else {
7576 TCGv_i32 tcg_int32 = tcg_temp_new_i32();
7577 TCGv_i32 tcg_float = tcg_temp_new_i32();
7578
7579 for (pass = 0; pass < elements; pass++) {
7580 read_vec_element_i32(s, tcg_int32, rn, pass, mop);
7581
7582 switch (size) {
7583 case MO_32:
7584 if (fracbits) {
7585 if (is_signed) {
7586 gen_helper_vfp_sltos(tcg_float, tcg_int32,
7587 tcg_shift, tcg_fpst);
7588 } else {
7589 gen_helper_vfp_ultos(tcg_float, tcg_int32,
7590 tcg_shift, tcg_fpst);
7591 }
7592 } else {
7593 if (is_signed) {
7594 gen_helper_vfp_sitos(tcg_float, tcg_int32, tcg_fpst);
7595 } else {
7596 gen_helper_vfp_uitos(tcg_float, tcg_int32, tcg_fpst);
7597 }
7598 }
7599 break;
7600 case MO_16:
7601 if (fracbits) {
7602 if (is_signed) {
7603 gen_helper_vfp_sltoh(tcg_float, tcg_int32,
7604 tcg_shift, tcg_fpst);
7605 } else {
7606 gen_helper_vfp_ultoh(tcg_float, tcg_int32,
7607 tcg_shift, tcg_fpst);
7608 }
7609 } else {
7610 if (is_signed) {
7611 gen_helper_vfp_sitoh(tcg_float, tcg_int32, tcg_fpst);
7612 } else {
7613 gen_helper_vfp_uitoh(tcg_float, tcg_int32, tcg_fpst);
7614 }
7615 }
7616 break;
7617 default:
7618 g_assert_not_reached();
7619 }
7620
7621 if (elements == 1) {
7622 write_fp_sreg(s, rd, tcg_float);
7623 } else {
7624 write_vec_element_i32(s, tcg_float, rd, pass, size);
7625 }
7626 }
7627
7628 tcg_temp_free_i32(tcg_int32);
7629 tcg_temp_free_i32(tcg_float);
7630 }
7631
7632 tcg_temp_free_ptr(tcg_fpst);
7633 if (tcg_shift) {
7634 tcg_temp_free_i32(tcg_shift);
7635 }
7636
7637 clear_vec_high(s, elements << size == 16, rd);
7638 }
7639
7640 /* UCVTF/SCVTF - Integer to FP conversion */
7641 static void handle_simd_shift_intfp_conv(DisasContext *s, bool is_scalar,
7642 bool is_q, bool is_u,
7643 int immh, int immb, int opcode,
7644 int rn, int rd)
7645 {
7646 int size, elements, fracbits;
7647 int immhb = immh << 3 | immb;
7648
7649 if (immh & 8) {
7650 size = MO_64;
7651 if (!is_scalar && !is_q) {
7652 unallocated_encoding(s);
7653 return;
7654 }
7655 } else if (immh & 4) {
7656 size = MO_32;
7657 } else if (immh & 2) {
7658 size = MO_16;
7659 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
7660 unallocated_encoding(s);
7661 return;
7662 }
7663 } else {
7664 /* immh == 0 would be a failure of the decode logic */
7665 g_assert(immh == 1);
7666 unallocated_encoding(s);
7667 return;
7668 }
7669
7670 if (is_scalar) {
7671 elements = 1;
7672 } else {
7673 elements = (8 << is_q) >> size;
7674 }
7675 fracbits = (16 << size) - immhb;
7676
7677 if (!fp_access_check(s)) {
7678 return;
7679 }
7680
7681 handle_simd_intfp_conv(s, rd, rn, elements, !is_u, fracbits, size);
7682 }
7683
7684 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
7685 static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
7686 bool is_q, bool is_u,
7687 int immh, int immb, int rn, int rd)
7688 {
7689 int immhb = immh << 3 | immb;
7690 int pass, size, fracbits;
7691 TCGv_ptr tcg_fpstatus;
7692 TCGv_i32 tcg_rmode, tcg_shift;
7693
7694 if (immh & 0x8) {
7695 size = MO_64;
7696 if (!is_scalar && !is_q) {
7697 unallocated_encoding(s);
7698 return;
7699 }
7700 } else if (immh & 0x4) {
7701 size = MO_32;
7702 } else if (immh & 0x2) {
7703 size = MO_16;
7704 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
7705 unallocated_encoding(s);
7706 return;
7707 }
7708 } else {
7709 /* Should have split out AdvSIMD modified immediate earlier. */
7710 assert(immh == 1);
7711 unallocated_encoding(s);
7712 return;
7713 }
7714
7715 if (!fp_access_check(s)) {
7716 return;
7717 }
7718
7719 assert(!(is_scalar && is_q));
7720
7721 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO));
7722 tcg_fpstatus = get_fpstatus_ptr(size == MO_16);
7723 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
7724 fracbits = (16 << size) - immhb;
7725 tcg_shift = tcg_const_i32(fracbits);
7726
7727 if (size == MO_64) {
7728 int maxpass = is_scalar ? 1 : 2;
7729
7730 for (pass = 0; pass < maxpass; pass++) {
7731 TCGv_i64 tcg_op = tcg_temp_new_i64();
7732
7733 read_vec_element(s, tcg_op, rn, pass, MO_64);
7734 if (is_u) {
7735 gen_helper_vfp_touqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
7736 } else {
7737 gen_helper_vfp_tosqd(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
7738 }
7739 write_vec_element(s, tcg_op, rd, pass, MO_64);
7740 tcg_temp_free_i64(tcg_op);
7741 }
7742 clear_vec_high(s, is_q, rd);
7743 } else {
7744 void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
7745 int maxpass = is_scalar ? 1 : ((8 << is_q) >> size);
7746
7747 switch (size) {
7748 case MO_16:
7749 if (is_u) {
7750 fn = gen_helper_vfp_touhh;
7751 } else {
7752 fn = gen_helper_vfp_toshh;
7753 }
7754 break;
7755 case MO_32:
7756 if (is_u) {
7757 fn = gen_helper_vfp_touls;
7758 } else {
7759 fn = gen_helper_vfp_tosls;
7760 }
7761 break;
7762 default:
7763 g_assert_not_reached();
7764 }
7765
7766 for (pass = 0; pass < maxpass; pass++) {
7767 TCGv_i32 tcg_op = tcg_temp_new_i32();
7768
7769 read_vec_element_i32(s, tcg_op, rn, pass, size);
7770 fn(tcg_op, tcg_op, tcg_shift, tcg_fpstatus);
7771 if (is_scalar) {
7772 write_fp_sreg(s, rd, tcg_op);
7773 } else {
7774 write_vec_element_i32(s, tcg_op, rd, pass, size);
7775 }
7776 tcg_temp_free_i32(tcg_op);
7777 }
7778 if (!is_scalar) {
7779 clear_vec_high(s, is_q, rd);
7780 }
7781 }
7782
7783 tcg_temp_free_ptr(tcg_fpstatus);
7784 tcg_temp_free_i32(tcg_shift);
7785 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
7786 tcg_temp_free_i32(tcg_rmode);
7787 }
7788
7789 /* AdvSIMD scalar shift by immediate
7790 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
7791 * +-----+---+-------------+------+------+--------+---+------+------+
7792 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
7793 * +-----+---+-------------+------+------+--------+---+------+------+
7794 *
7795 * This is the scalar version so it works on a fixed sized registers
7796 */
7797 static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn)
7798 {
7799 int rd = extract32(insn, 0, 5);
7800 int rn = extract32(insn, 5, 5);
7801 int opcode = extract32(insn, 11, 5);
7802 int immb = extract32(insn, 16, 3);
7803 int immh = extract32(insn, 19, 4);
7804 bool is_u = extract32(insn, 29, 1);
7805
7806 if (immh == 0) {
7807 unallocated_encoding(s);
7808 return;
7809 }
7810
7811 switch (opcode) {
7812 case 0x08: /* SRI */
7813 if (!is_u) {
7814 unallocated_encoding(s);
7815 return;
7816 }
7817 /* fall through */
7818 case 0x00: /* SSHR / USHR */
7819 case 0x02: /* SSRA / USRA */
7820 case 0x04: /* SRSHR / URSHR */
7821 case 0x06: /* SRSRA / URSRA */
7822 handle_scalar_simd_shri(s, is_u, immh, immb, opcode, rn, rd);
7823 break;
7824 case 0x0a: /* SHL / SLI */
7825 handle_scalar_simd_shli(s, is_u, immh, immb, opcode, rn, rd);
7826 break;
7827 case 0x1c: /* SCVTF, UCVTF */
7828 handle_simd_shift_intfp_conv(s, true, false, is_u, immh, immb,
7829 opcode, rn, rd);
7830 break;
7831 case 0x10: /* SQSHRUN, SQSHRUN2 */
7832 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
7833 if (!is_u) {
7834 unallocated_encoding(s);
7835 return;
7836 }
7837 handle_vec_simd_sqshrn(s, true, false, false, true,
7838 immh, immb, opcode, rn, rd);
7839 break;
7840 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
7841 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
7842 handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
7843 immh, immb, opcode, rn, rd);
7844 break;
7845 case 0xc: /* SQSHLU */
7846 if (!is_u) {
7847 unallocated_encoding(s);
7848 return;
7849 }
7850 handle_simd_qshl(s, true, false, false, true, immh, immb, rn, rd);
7851 break;
7852 case 0xe: /* SQSHL, UQSHL */
7853 handle_simd_qshl(s, true, false, is_u, is_u, immh, immb, rn, rd);
7854 break;
7855 case 0x1f: /* FCVTZS, FCVTZU */
7856 handle_simd_shift_fpint_conv(s, true, false, is_u, immh, immb, rn, rd);
7857 break;
7858 default:
7859 unallocated_encoding(s);
7860 break;
7861 }
7862 }
7863
7864 /* AdvSIMD scalar three different
7865 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
7866 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7867 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
7868 * +-----+---+-----------+------+---+------+--------+-----+------+------+
7869 */
7870 static void disas_simd_scalar_three_reg_diff(DisasContext *s, uint32_t insn)
7871 {
7872 bool is_u = extract32(insn, 29, 1);
7873 int size = extract32(insn, 22, 2);
7874 int opcode = extract32(insn, 12, 4);
7875 int rm = extract32(insn, 16, 5);
7876 int rn = extract32(insn, 5, 5);
7877 int rd = extract32(insn, 0, 5);
7878
7879 if (is_u) {
7880 unallocated_encoding(s);
7881 return;
7882 }
7883
7884 switch (opcode) {
7885 case 0x9: /* SQDMLAL, SQDMLAL2 */
7886 case 0xb: /* SQDMLSL, SQDMLSL2 */
7887 case 0xd: /* SQDMULL, SQDMULL2 */
7888 if (size == 0 || size == 3) {
7889 unallocated_encoding(s);
7890 return;
7891 }
7892 break;
7893 default:
7894 unallocated_encoding(s);
7895 return;
7896 }
7897
7898 if (!fp_access_check(s)) {
7899 return;
7900 }
7901
7902 if (size == 2) {
7903 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
7904 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
7905 TCGv_i64 tcg_res = tcg_temp_new_i64();
7906
7907 read_vec_element(s, tcg_op1, rn, 0, MO_32 | MO_SIGN);
7908 read_vec_element(s, tcg_op2, rm, 0, MO_32 | MO_SIGN);
7909
7910 tcg_gen_mul_i64(tcg_res, tcg_op1, tcg_op2);
7911 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env, tcg_res, tcg_res);
7912
7913 switch (opcode) {
7914 case 0xd: /* SQDMULL, SQDMULL2 */
7915 break;
7916 case 0xb: /* SQDMLSL, SQDMLSL2 */
7917 tcg_gen_neg_i64(tcg_res, tcg_res);
7918 /* fall through */
7919 case 0x9: /* SQDMLAL, SQDMLAL2 */
7920 read_vec_element(s, tcg_op1, rd, 0, MO_64);
7921 gen_helper_neon_addl_saturate_s64(tcg_res, cpu_env,
7922 tcg_res, tcg_op1);
7923 break;
7924 default:
7925 g_assert_not_reached();
7926 }
7927
7928 write_fp_dreg(s, rd, tcg_res);
7929
7930 tcg_temp_free_i64(tcg_op1);
7931 tcg_temp_free_i64(tcg_op2);
7932 tcg_temp_free_i64(tcg_res);
7933 } else {
7934 TCGv_i32 tcg_op1 = read_fp_hreg(s, rn);
7935 TCGv_i32 tcg_op2 = read_fp_hreg(s, rm);
7936 TCGv_i64 tcg_res = tcg_temp_new_i64();
7937
7938 gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2);
7939 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_res);
7940
7941 switch (opcode) {
7942 case 0xd: /* SQDMULL, SQDMULL2 */
7943 break;
7944 case 0xb: /* SQDMLSL, SQDMLSL2 */
7945 gen_helper_neon_negl_u32(tcg_res, tcg_res);
7946 /* fall through */
7947 case 0x9: /* SQDMLAL, SQDMLAL2 */
7948 {
7949 TCGv_i64 tcg_op3 = tcg_temp_new_i64();
7950 read_vec_element(s, tcg_op3, rd, 0, MO_32);
7951 gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env,
7952 tcg_res, tcg_op3);
7953 tcg_temp_free_i64(tcg_op3);
7954 break;
7955 }
7956 default:
7957 g_assert_not_reached();
7958 }
7959
7960 tcg_gen_ext32u_i64(tcg_res, tcg_res);
7961 write_fp_dreg(s, rd, tcg_res);
7962
7963 tcg_temp_free_i32(tcg_op1);
7964 tcg_temp_free_i32(tcg_op2);
7965 tcg_temp_free_i64(tcg_res);
7966 }
7967 }
7968
7969 /* CMTST : test is "if (X & Y != 0)". */
7970 static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
7971 {
7972 tcg_gen_and_i32(d, a, b);
7973 tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0);
7974 tcg_gen_neg_i32(d, d);
7975 }
7976
7977 static void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
7978 {
7979 tcg_gen_and_i64(d, a, b);
7980 tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0);
7981 tcg_gen_neg_i64(d, d);
7982 }
7983
7984 static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
7985 {
7986 tcg_gen_and_vec(vece, d, a, b);
7987 tcg_gen_dupi_vec(vece, a, 0);
7988 tcg_gen_cmp_vec(TCG_COND_NE, vece, d, d, a);
7989 }
7990
7991 static void handle_3same_64(DisasContext *s, int opcode, bool u,
7992 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn, TCGv_i64 tcg_rm)
7993 {
7994 /* Handle 64x64->64 opcodes which are shared between the scalar
7995 * and vector 3-same groups. We cover every opcode where size == 3
7996 * is valid in either the three-reg-same (integer, not pairwise)
7997 * or scalar-three-reg-same groups.
7998 */
7999 TCGCond cond;
8000
8001 switch (opcode) {
8002 case 0x1: /* SQADD */
8003 if (u) {
8004 gen_helper_neon_qadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8005 } else {
8006 gen_helper_neon_qadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8007 }
8008 break;
8009 case 0x5: /* SQSUB */
8010 if (u) {
8011 gen_helper_neon_qsub_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8012 } else {
8013 gen_helper_neon_qsub_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8014 }
8015 break;
8016 case 0x6: /* CMGT, CMHI */
8017 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8018 * We implement this using setcond (test) and then negating.
8019 */
8020 cond = u ? TCG_COND_GTU : TCG_COND_GT;
8021 do_cmop:
8022 tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm);
8023 tcg_gen_neg_i64(tcg_rd, tcg_rd);
8024 break;
8025 case 0x7: /* CMGE, CMHS */
8026 cond = u ? TCG_COND_GEU : TCG_COND_GE;
8027 goto do_cmop;
8028 case 0x11: /* CMTST, CMEQ */
8029 if (u) {
8030 cond = TCG_COND_EQ;
8031 goto do_cmop;
8032 }
8033 gen_cmtst_i64(tcg_rd, tcg_rn, tcg_rm);
8034 break;
8035 case 0x8: /* SSHL, USHL */
8036 if (u) {
8037 gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm);
8038 } else {
8039 gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm);
8040 }
8041 break;
8042 case 0x9: /* SQSHL, UQSHL */
8043 if (u) {
8044 gen_helper_neon_qshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8045 } else {
8046 gen_helper_neon_qshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8047 }
8048 break;
8049 case 0xa: /* SRSHL, URSHL */
8050 if (u) {
8051 gen_helper_neon_rshl_u64(tcg_rd, tcg_rn, tcg_rm);
8052 } else {
8053 gen_helper_neon_rshl_s64(tcg_rd, tcg_rn, tcg_rm);
8054 }
8055 break;
8056 case 0xb: /* SQRSHL, UQRSHL */
8057 if (u) {
8058 gen_helper_neon_qrshl_u64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8059 } else {
8060 gen_helper_neon_qrshl_s64(tcg_rd, cpu_env, tcg_rn, tcg_rm);
8061 }
8062 break;
8063 case 0x10: /* ADD, SUB */
8064 if (u) {
8065 tcg_gen_sub_i64(tcg_rd, tcg_rn, tcg_rm);
8066 } else {
8067 tcg_gen_add_i64(tcg_rd, tcg_rn, tcg_rm);
8068 }
8069 break;
8070 default:
8071 g_assert_not_reached();
8072 }
8073 }
8074
8075 /* Handle the 3-same-operands float operations; shared by the scalar
8076 * and vector encodings. The caller must filter out any encodings
8077 * not allocated for the encoding it is dealing with.
8078 */
8079 static void handle_3same_float(DisasContext *s, int size, int elements,
8080 int fpopcode, int rd, int rn, int rm)
8081 {
8082 int pass;
8083 TCGv_ptr fpst = get_fpstatus_ptr(false);
8084
8085 for (pass = 0; pass < elements; pass++) {
8086 if (size) {
8087 /* Double */
8088 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
8089 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
8090 TCGv_i64 tcg_res = tcg_temp_new_i64();
8091
8092 read_vec_element(s, tcg_op1, rn, pass, MO_64);
8093 read_vec_element(s, tcg_op2, rm, pass, MO_64);
8094
8095 switch (fpopcode) {
8096 case 0x39: /* FMLS */
8097 /* As usual for ARM, separate negation for fused multiply-add */
8098 gen_helper_vfp_negd(tcg_op1, tcg_op1);
8099 /* fall through */
8100 case 0x19: /* FMLA */
8101 read_vec_element(s, tcg_res, rd, pass, MO_64);
8102 gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2,
8103 tcg_res, fpst);
8104 break;
8105 case 0x18: /* FMAXNM */
8106 gen_helper_vfp_maxnumd(tcg_res, tcg_op1, tcg_op2, fpst);
8107 break;
8108 case 0x1a: /* FADD */
8109 gen_helper_vfp_addd(tcg_res, tcg_op1, tcg_op2, fpst);
8110 break;
8111 case 0x1b: /* FMULX */
8112 gen_helper_vfp_mulxd(tcg_res, tcg_op1, tcg_op2, fpst);
8113 break;
8114 case 0x1c: /* FCMEQ */
8115 gen_helper_neon_ceq_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8116 break;
8117 case 0x1e: /* FMAX */
8118 gen_helper_vfp_maxd(tcg_res, tcg_op1, tcg_op2, fpst);
8119 break;
8120 case 0x1f: /* FRECPS */
8121 gen_helper_recpsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8122 break;
8123 case 0x38: /* FMINNM */
8124 gen_helper_vfp_minnumd(tcg_res, tcg_op1, tcg_op2, fpst);
8125 break;
8126 case 0x3a: /* FSUB */
8127 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
8128 break;
8129 case 0x3e: /* FMIN */
8130 gen_helper_vfp_mind(tcg_res, tcg_op1, tcg_op2, fpst);
8131 break;
8132 case 0x3f: /* FRSQRTS */
8133 gen_helper_rsqrtsf_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8134 break;
8135 case 0x5b: /* FMUL */
8136 gen_helper_vfp_muld(tcg_res, tcg_op1, tcg_op2, fpst);
8137 break;
8138 case 0x5c: /* FCMGE */
8139 gen_helper_neon_cge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8140 break;
8141 case 0x5d: /* FACGE */
8142 gen_helper_neon_acge_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8143 break;
8144 case 0x5f: /* FDIV */
8145 gen_helper_vfp_divd(tcg_res, tcg_op1, tcg_op2, fpst);
8146 break;
8147 case 0x7a: /* FABD */
8148 gen_helper_vfp_subd(tcg_res, tcg_op1, tcg_op2, fpst);
8149 gen_helper_vfp_absd(tcg_res, tcg_res);
8150 break;
8151 case 0x7c: /* FCMGT */
8152 gen_helper_neon_cgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8153 break;
8154 case 0x7d: /* FACGT */
8155 gen_helper_neon_acgt_f64(tcg_res, tcg_op1, tcg_op2, fpst);
8156 break;
8157 default:
8158 g_assert_not_reached();
8159 }
8160
8161 write_vec_element(s, tcg_res, rd, pass, MO_64);
8162
8163 tcg_temp_free_i64(tcg_res);
8164 tcg_temp_free_i64(tcg_op1);
8165 tcg_temp_free_i64(tcg_op2);
8166 } else {
8167 /* Single */
8168 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
8169 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
8170 TCGv_i32 tcg_res = tcg_temp_new_i32();
8171
8172 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
8173 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
8174
8175 switch (fpopcode) {
8176 case 0x39: /* FMLS */
8177 /* As usual for ARM, separate negation for fused multiply-add */
8178 gen_helper_vfp_negs(tcg_op1, tcg_op1);
8179 /* fall through */
8180 case 0x19: /* FMLA */
8181 read_vec_element_i32(s, tcg_res, rd, pass, MO_32);
8182 gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2,
8183 tcg_res, fpst);
8184 break;
8185 case 0x1a: /* FADD */
8186 gen_helper_vfp_adds(tcg_res, tcg_op1, tcg_op2, fpst);
8187 break;
8188 case 0x1b: /* FMULX */
8189 gen_helper_vfp_mulxs(tcg_res, tcg_op1, tcg_op2, fpst);
8190 break;
8191 case 0x1c: /* FCMEQ */
8192 gen_helper_neon_ceq_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8193 break;
8194 case 0x1e: /* FMAX */
8195 gen_helper_vfp_maxs(tcg_res, tcg_op1, tcg_op2, fpst);
8196 break;
8197 case 0x1f: /* FRECPS */
8198 gen_helper_recpsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8199 break;
8200 case 0x18: /* FMAXNM */
8201 gen_helper_vfp_maxnums(tcg_res, tcg_op1, tcg_op2, fpst);
8202 break;
8203 case 0x38: /* FMINNM */
8204 gen_helper_vfp_minnums(tcg_res, tcg_op1, tcg_op2, fpst);
8205 break;
8206 case 0x3a: /* FSUB */
8207 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
8208 break;
8209 case 0x3e: /* FMIN */
8210 gen_helper_vfp_mins(tcg_res, tcg_op1, tcg_op2, fpst);
8211 break;
8212 case 0x3f: /* FRSQRTS */
8213 gen_helper_rsqrtsf_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8214 break;
8215 case 0x5b: /* FMUL */
8216 gen_helper_vfp_muls(tcg_res, tcg_op1, tcg_op2, fpst);
8217 break;
8218 case 0x5c: /* FCMGE */
8219 gen_helper_neon_cge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8220 break;
8221 case 0x5d: /* FACGE */
8222 gen_helper_neon_acge_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8223 break;
8224 case 0x5f: /* FDIV */
8225 gen_helper_vfp_divs(tcg_res, tcg_op1, tcg_op2, fpst);
8226 break;
8227 case 0x7a: /* FABD */
8228 gen_helper_vfp_subs(tcg_res, tcg_op1, tcg_op2, fpst);
8229 gen_helper_vfp_abss(tcg_res, tcg_res);
8230 break;
8231 case 0x7c: /* FCMGT */
8232 gen_helper_neon_cgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8233 break;
8234 case 0x7d: /* FACGT */
8235 gen_helper_neon_acgt_f32(tcg_res, tcg_op1, tcg_op2, fpst);
8236 break;
8237 default:
8238 g_assert_not_reached();
8239 }
8240
8241 if (elements == 1) {
8242 /* scalar single so clear high part */
8243 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
8244
8245 tcg_gen_extu_i32_i64(tcg_tmp, tcg_res);
8246 write_vec_element(s, tcg_tmp, rd, pass, MO_64);
8247 tcg_temp_free_i64(tcg_tmp);
8248 } else {
8249 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
8250 }
8251
8252 tcg_temp_free_i32(tcg_res);
8253 tcg_temp_free_i32(tcg_op1);
8254 tcg_temp_free_i32(tcg_op2);
8255 }
8256 }
8257
8258 tcg_temp_free_ptr(fpst);
8259
8260 clear_vec_high(s, elements * (size ? 8 : 4) > 8, rd);
8261 }
8262
8263 /* AdvSIMD scalar three same
8264 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8265 * +-----+---+-----------+------+---+------+--------+---+------+------+
8266 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8267 * +-----+---+-----------+------+---+------+--------+---+------+------+
8268 */
8269 static void disas_simd_scalar_three_reg_same(DisasContext *s, uint32_t insn)
8270 {
8271 int rd = extract32(insn, 0, 5);
8272 int rn = extract32(insn, 5, 5);
8273 int opcode = extract32(insn, 11, 5);
8274 int rm = extract32(insn, 16, 5);
8275 int size = extract32(insn, 22, 2);
8276 bool u = extract32(insn, 29, 1);
8277 TCGv_i64 tcg_rd;
8278
8279 if (opcode >= 0x18) {
8280 /* Floating point: U, size[1] and opcode indicate operation */
8281 int fpopcode = opcode | (extract32(size, 1, 1) << 5) | (u << 6);
8282 switch (fpopcode) {
8283 case 0x1b: /* FMULX */
8284 case 0x1f: /* FRECPS */
8285 case 0x3f: /* FRSQRTS */
8286 case 0x5d: /* FACGE */
8287 case 0x7d: /* FACGT */
8288 case 0x1c: /* FCMEQ */
8289 case 0x5c: /* FCMGE */
8290 case 0x7c: /* FCMGT */
8291 case 0x7a: /* FABD */
8292 break;
8293 default:
8294 unallocated_encoding(s);
8295 return;
8296 }
8297
8298 if (!fp_access_check(s)) {
8299 return;
8300 }
8301
8302 handle_3same_float(s, extract32(size, 0, 1), 1, fpopcode, rd, rn, rm);
8303 return;
8304 }
8305
8306 switch (opcode) {
8307 case 0x1: /* SQADD, UQADD */
8308 case 0x5: /* SQSUB, UQSUB */
8309 case 0x9: /* SQSHL, UQSHL */
8310 case 0xb: /* SQRSHL, UQRSHL */
8311 break;
8312 case 0x8: /* SSHL, USHL */
8313 case 0xa: /* SRSHL, URSHL */
8314 case 0x6: /* CMGT, CMHI */
8315 case 0x7: /* CMGE, CMHS */
8316 case 0x11: /* CMTST, CMEQ */
8317 case 0x10: /* ADD, SUB (vector) */
8318 if (size != 3) {
8319 unallocated_encoding(s);
8320 return;
8321 }
8322 break;
8323 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8324 if (size != 1 && size != 2) {
8325 unallocated_encoding(s);
8326 return;
8327 }
8328 break;
8329 default:
8330 unallocated_encoding(s);
8331 return;
8332 }
8333
8334 if (!fp_access_check(s)) {
8335 return;
8336 }
8337
8338 tcg_rd = tcg_temp_new_i64();
8339
8340 if (size == 3) {
8341 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
8342 TCGv_i64 tcg_rm = read_fp_dreg(s, rm);
8343
8344 handle_3same_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rm);
8345 tcg_temp_free_i64(tcg_rn);
8346 tcg_temp_free_i64(tcg_rm);
8347 } else {
8348 /* Do a single operation on the lowest element in the vector.
8349 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8350 * no side effects for all these operations.
8351 * OPTME: special-purpose helpers would avoid doing some
8352 * unnecessary work in the helper for the 8 and 16 bit cases.
8353 */
8354 NeonGenTwoOpEnvFn *genenvfn;
8355 TCGv_i32 tcg_rn = tcg_temp_new_i32();
8356 TCGv_i32 tcg_rm = tcg_temp_new_i32();
8357 TCGv_i32 tcg_rd32 = tcg_temp_new_i32();
8358
8359 read_vec_element_i32(s, tcg_rn, rn, 0, size);
8360 read_vec_element_i32(s, tcg_rm, rm, 0, size);
8361
8362 switch (opcode) {
8363 case 0x1: /* SQADD, UQADD */
8364 {
8365 static NeonGenTwoOpEnvFn * const fns[3][2] = {
8366 { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
8367 { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
8368 { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
8369 };
8370 genenvfn = fns[size][u];
8371 break;
8372 }
8373 case 0x5: /* SQSUB, UQSUB */
8374 {
8375 static NeonGenTwoOpEnvFn * const fns[3][2] = {
8376 { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
8377 { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
8378 { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
8379 };
8380 genenvfn = fns[size][u];
8381 break;
8382 }
8383 case 0x9: /* SQSHL, UQSHL */
8384 {
8385 static NeonGenTwoOpEnvFn * const fns[3][2] = {
8386 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
8387 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
8388 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
8389 };
8390 genenvfn = fns[size][u];
8391 break;
8392 }
8393 case 0xb: /* SQRSHL, UQRSHL */
8394 {
8395 static NeonGenTwoOpEnvFn * const fns[3][2] = {
8396 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
8397 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
8398 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
8399 };
8400 genenvfn = fns[size][u];
8401 break;
8402 }
8403 case 0x16: /* SQDMULH, SQRDMULH */
8404 {
8405 static NeonGenTwoOpEnvFn * const fns[2][2] = {
8406 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
8407 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
8408 };
8409 assert(size == 1 || size == 2);
8410 genenvfn = fns[size - 1][u];
8411 break;
8412 }
8413 default:
8414 g_assert_not_reached();
8415 }
8416
8417 genenvfn(tcg_rd32, cpu_env, tcg_rn, tcg_rm);
8418 tcg_gen_extu_i32_i64(tcg_rd, tcg_rd32);
8419 tcg_temp_free_i32(tcg_rd32);
8420 tcg_temp_free_i32(tcg_rn);
8421 tcg_temp_free_i32(tcg_rm);
8422 }
8423
8424 write_fp_dreg(s, rd, tcg_rd);
8425
8426 tcg_temp_free_i64(tcg_rd);
8427 }
8428
8429 /* AdvSIMD scalar three same FP16
8430 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8431 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8432 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8433 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8434 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8435 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8436 */
8437 static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
8438 uint32_t insn)
8439 {
8440 int rd = extract32(insn, 0, 5);
8441 int rn = extract32(insn, 5, 5);
8442 int opcode = extract32(insn, 11, 3);
8443 int rm = extract32(insn, 16, 5);
8444 bool u = extract32(insn, 29, 1);
8445 bool a = extract32(insn, 23, 1);
8446 int fpopcode = opcode | (a << 3) | (u << 4);
8447 TCGv_ptr fpst;
8448 TCGv_i32 tcg_op1;
8449 TCGv_i32 tcg_op2;
8450 TCGv_i32 tcg_res;
8451
8452 switch (fpopcode) {
8453 case 0x03: /* FMULX */
8454 case 0x04: /* FCMEQ (reg) */
8455 case 0x07: /* FRECPS */
8456 case 0x0f: /* FRSQRTS */
8457 case 0x14: /* FCMGE (reg) */
8458 case 0x15: /* FACGE */
8459 case 0x1a: /* FABD */
8460 case 0x1c: /* FCMGT (reg) */
8461 case 0x1d: /* FACGT */
8462 break;
8463 default:
8464 unallocated_encoding(s);
8465 return;
8466 }
8467
8468 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
8469 unallocated_encoding(s);
8470 }
8471
8472 if (!fp_access_check(s)) {
8473 return;
8474 }
8475
8476 fpst = get_fpstatus_ptr(true);
8477
8478 tcg_op1 = read_fp_hreg(s, rn);
8479 tcg_op2 = read_fp_hreg(s, rm);
8480 tcg_res = tcg_temp_new_i32();
8481
8482 switch (fpopcode) {
8483 case 0x03: /* FMULX */
8484 gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
8485 break;
8486 case 0x04: /* FCMEQ (reg) */
8487 gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
8488 break;
8489 case 0x07: /* FRECPS */
8490 gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
8491 break;
8492 case 0x0f: /* FRSQRTS */
8493 gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
8494 break;
8495 case 0x14: /* FCMGE (reg) */
8496 gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
8497 break;
8498 case 0x15: /* FACGE */
8499 gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
8500 break;
8501 case 0x1a: /* FABD */
8502 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
8503 tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
8504 break;
8505 case 0x1c: /* FCMGT (reg) */
8506 gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
8507 break;
8508 case 0x1d: /* FACGT */
8509 gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
8510 break;
8511 default:
8512 g_assert_not_reached();
8513 }
8514
8515 write_fp_sreg(s, rd, tcg_res);
8516
8517
8518 tcg_temp_free_i32(tcg_res);
8519 tcg_temp_free_i32(tcg_op1);
8520 tcg_temp_free_i32(tcg_op2);
8521 tcg_temp_free_ptr(fpst);
8522 }
8523
8524 /* AdvSIMD scalar three same extra
8525 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
8526 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8527 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
8528 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
8529 */
8530 static void disas_simd_scalar_three_reg_same_extra(DisasContext *s,
8531 uint32_t insn)
8532 {
8533 int rd = extract32(insn, 0, 5);
8534 int rn = extract32(insn, 5, 5);
8535 int opcode = extract32(insn, 11, 4);
8536 int rm = extract32(insn, 16, 5);
8537 int size = extract32(insn, 22, 2);
8538 bool u = extract32(insn, 29, 1);
8539 TCGv_i32 ele1, ele2, ele3;
8540 TCGv_i64 res;
8541 int feature;
8542
8543 switch (u * 16 + opcode) {
8544 case 0x10: /* SQRDMLAH (vector) */
8545 case 0x11: /* SQRDMLSH (vector) */
8546 if (size != 1 && size != 2) {
8547 unallocated_encoding(s);
8548 return;
8549 }
8550 feature = ARM_FEATURE_V8_RDM;
8551 break;
8552 default:
8553 unallocated_encoding(s);
8554 return;
8555 }
8556 if (!arm_dc_feature(s, feature)) {
8557 unallocated_encoding(s);
8558 return;
8559 }
8560 if (!fp_access_check(s)) {
8561 return;
8562 }
8563
8564 /* Do a single operation on the lowest element in the vector.
8565 * We use the standard Neon helpers and rely on 0 OP 0 == 0
8566 * with no side effects for all these operations.
8567 * OPTME: special-purpose helpers would avoid doing some
8568 * unnecessary work in the helper for the 16 bit cases.
8569 */
8570 ele1 = tcg_temp_new_i32();
8571 ele2 = tcg_temp_new_i32();
8572 ele3 = tcg_temp_new_i32();
8573
8574 read_vec_element_i32(s, ele1, rn, 0, size);
8575 read_vec_element_i32(s, ele2, rm, 0, size);
8576 read_vec_element_i32(s, ele3, rd, 0, size);
8577
8578 switch (opcode) {
8579 case 0x0: /* SQRDMLAH */
8580 if (size == 1) {
8581 gen_helper_neon_qrdmlah_s16(ele3, cpu_env, ele1, ele2, ele3);
8582 } else {
8583 gen_helper_neon_qrdmlah_s32(ele3, cpu_env, ele1, ele2, ele3);
8584 }
8585 break;
8586 case 0x1: /* SQRDMLSH */
8587 if (size == 1) {
8588 gen_helper_neon_qrdmlsh_s16(ele3, cpu_env, ele1, ele2, ele3);
8589 } else {
8590 gen_helper_neon_qrdmlsh_s32(ele3, cpu_env, ele1, ele2, ele3);
8591 }
8592 break;
8593 default:
8594 g_assert_not_reached();
8595 }
8596 tcg_temp_free_i32(ele1);
8597 tcg_temp_free_i32(ele2);
8598
8599 res = tcg_temp_new_i64();
8600 tcg_gen_extu_i32_i64(res, ele3);
8601 tcg_temp_free_i32(ele3);
8602
8603 write_fp_dreg(s, rd, res);
8604 tcg_temp_free_i64(res);
8605 }
8606
8607 static void handle_2misc_64(DisasContext *s, int opcode, bool u,
8608 TCGv_i64 tcg_rd, TCGv_i64 tcg_rn,
8609 TCGv_i32 tcg_rmode, TCGv_ptr tcg_fpstatus)
8610 {
8611 /* Handle 64->64 opcodes which are shared between the scalar and
8612 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
8613 * is valid in either group and also the double-precision fp ops.
8614 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
8615 * requires them.
8616 */
8617 TCGCond cond;
8618
8619 switch (opcode) {
8620 case 0x4: /* CLS, CLZ */
8621 if (u) {
8622 tcg_gen_clzi_i64(tcg_rd, tcg_rn, 64);
8623 } else {
8624 tcg_gen_clrsb_i64(tcg_rd, tcg_rn);
8625 }
8626 break;
8627 case 0x5: /* NOT */
8628 /* This opcode is shared with CNT and RBIT but we have earlier
8629 * enforced that size == 3 if and only if this is the NOT insn.
8630 */
8631 tcg_gen_not_i64(tcg_rd, tcg_rn);
8632 break;
8633 case 0x7: /* SQABS, SQNEG */
8634 if (u) {
8635 gen_helper_neon_qneg_s64(tcg_rd, cpu_env, tcg_rn);
8636 } else {
8637 gen_helper_neon_qabs_s64(tcg_rd, cpu_env, tcg_rn);
8638 }
8639 break;
8640 case 0xa: /* CMLT */
8641 /* 64 bit integer comparison against zero, result is
8642 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
8643 * subtracting 1.
8644 */
8645 cond = TCG_COND_LT;
8646 do_cmop:
8647 tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0);
8648 tcg_gen_neg_i64(tcg_rd, tcg_rd);
8649 break;
8650 case 0x8: /* CMGT, CMGE */
8651 cond = u ? TCG_COND_GE : TCG_COND_GT;
8652 goto do_cmop;
8653 case 0x9: /* CMEQ, CMLE */
8654 cond = u ? TCG_COND_LE : TCG_COND_EQ;
8655 goto do_cmop;
8656 case 0xb: /* ABS, NEG */
8657 if (u) {
8658 tcg_gen_neg_i64(tcg_rd, tcg_rn);
8659 } else {
8660 TCGv_i64 tcg_zero = tcg_const_i64(0);
8661 tcg_gen_neg_i64(tcg_rd, tcg_rn);
8662 tcg_gen_movcond_i64(TCG_COND_GT, tcg_rd, tcg_rn, tcg_zero,
8663 tcg_rn, tcg_rd);
8664 tcg_temp_free_i64(tcg_zero);
8665 }
8666 break;
8667 case 0x2f: /* FABS */
8668 gen_helper_vfp_absd(tcg_rd, tcg_rn);
8669 break;
8670 case 0x6f: /* FNEG */
8671 gen_helper_vfp_negd(tcg_rd, tcg_rn);
8672 break;
8673 case 0x7f: /* FSQRT */
8674 gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
8675 break;
8676 case 0x1a: /* FCVTNS */
8677 case 0x1b: /* FCVTMS */
8678 case 0x1c: /* FCVTAS */
8679 case 0x3a: /* FCVTPS */
8680 case 0x3b: /* FCVTZS */
8681 {
8682 TCGv_i32 tcg_shift = tcg_const_i32(0);
8683 gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
8684 tcg_temp_free_i32(tcg_shift);
8685 break;
8686 }
8687 case 0x5a: /* FCVTNU */
8688 case 0x5b: /* FCVTMU */
8689 case 0x5c: /* FCVTAU */
8690 case 0x7a: /* FCVTPU */
8691 case 0x7b: /* FCVTZU */
8692 {
8693 TCGv_i32 tcg_shift = tcg_const_i32(0);
8694 gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
8695 tcg_temp_free_i32(tcg_shift);
8696 break;
8697 }
8698 case 0x18: /* FRINTN */
8699 case 0x19: /* FRINTM */
8700 case 0x38: /* FRINTP */
8701 case 0x39: /* FRINTZ */
8702 case 0x58: /* FRINTA */
8703 case 0x79: /* FRINTI */
8704 gen_helper_rintd(tcg_rd, tcg_rn, tcg_fpstatus);
8705 break;
8706 case 0x59: /* FRINTX */
8707 gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus);
8708 break;
8709 default:
8710 g_assert_not_reached();
8711 }
8712 }
8713
8714 static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
8715 bool is_scalar, bool is_u, bool is_q,
8716 int size, int rn, int rd)
8717 {
8718 bool is_double = (size == MO_64);
8719 TCGv_ptr fpst;
8720
8721 if (!fp_access_check(s)) {
8722 return;
8723 }
8724
8725 fpst = get_fpstatus_ptr(size == MO_16);
8726
8727 if (is_double) {
8728 TCGv_i64 tcg_op = tcg_temp_new_i64();
8729 TCGv_i64 tcg_zero = tcg_const_i64(0);
8730 TCGv_i64 tcg_res = tcg_temp_new_i64();
8731 NeonGenTwoDoubleOPFn *genfn;
8732 bool swap = false;
8733 int pass;
8734
8735 switch (opcode) {
8736 case 0x2e: /* FCMLT (zero) */
8737 swap = true;
8738 /* fallthrough */
8739 case 0x2c: /* FCMGT (zero) */
8740 genfn = gen_helper_neon_cgt_f64;
8741 break;
8742 case 0x2d: /* FCMEQ (zero) */
8743 genfn = gen_helper_neon_ceq_f64;
8744 break;
8745 case 0x6d: /* FCMLE (zero) */
8746 swap = true;
8747 /* fall through */
8748 case 0x6c: /* FCMGE (zero) */
8749 genfn = gen_helper_neon_cge_f64;
8750 break;
8751 default:
8752 g_assert_not_reached();
8753 }
8754
8755 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
8756 read_vec_element(s, tcg_op, rn, pass, MO_64);
8757 if (swap) {
8758 genfn(tcg_res, tcg_zero, tcg_op, fpst);
8759 } else {
8760 genfn(tcg_res, tcg_op, tcg_zero, fpst);
8761 }
8762 write_vec_element(s, tcg_res, rd, pass, MO_64);
8763 }
8764 tcg_temp_free_i64(tcg_res);
8765 tcg_temp_free_i64(tcg_zero);
8766 tcg_temp_free_i64(tcg_op);
8767
8768 clear_vec_high(s, !is_scalar, rd);
8769 } else {
8770 TCGv_i32 tcg_op = tcg_temp_new_i32();
8771 TCGv_i32 tcg_zero = tcg_const_i32(0);
8772 TCGv_i32 tcg_res = tcg_temp_new_i32();
8773 NeonGenTwoSingleOPFn *genfn;
8774 bool swap = false;
8775 int pass, maxpasses;
8776
8777 if (size == MO_16) {
8778 switch (opcode) {
8779 case 0x2e: /* FCMLT (zero) */
8780 swap = true;
8781 /* fall through */
8782 case 0x2c: /* FCMGT (zero) */
8783 genfn = gen_helper_advsimd_cgt_f16;
8784 break;
8785 case 0x2d: /* FCMEQ (zero) */
8786 genfn = gen_helper_advsimd_ceq_f16;
8787 break;
8788 case 0x6d: /* FCMLE (zero) */
8789 swap = true;
8790 /* fall through */
8791 case 0x6c: /* FCMGE (zero) */
8792 genfn = gen_helper_advsimd_cge_f16;
8793 break;
8794 default:
8795 g_assert_not_reached();
8796 }
8797 } else {
8798 switch (opcode) {
8799 case 0x2e: /* FCMLT (zero) */
8800 swap = true;
8801 /* fall through */
8802 case 0x2c: /* FCMGT (zero) */
8803 genfn = gen_helper_neon_cgt_f32;
8804 break;
8805 case 0x2d: /* FCMEQ (zero) */
8806 genfn = gen_helper_neon_ceq_f32;
8807 break;
8808 case 0x6d: /* FCMLE (zero) */
8809 swap = true;
8810 /* fall through */
8811 case 0x6c: /* FCMGE (zero) */
8812 genfn = gen_helper_neon_cge_f32;
8813 break;
8814 default:
8815 g_assert_not_reached();
8816 }
8817 }
8818
8819 if (is_scalar) {
8820 maxpasses = 1;
8821 } else {
8822 int vector_size = 8 << is_q;
8823 maxpasses = vector_size >> size;
8824 }
8825
8826 for (pass = 0; pass < maxpasses; pass++) {
8827 read_vec_element_i32(s, tcg_op, rn, pass, size);
8828 if (swap) {
8829 genfn(tcg_res, tcg_zero, tcg_op, fpst);
8830 } else {
8831 genfn(tcg_res, tcg_op, tcg_zero, fpst);
8832 }
8833 if (is_scalar) {
8834 write_fp_sreg(s, rd, tcg_res);
8835 } else {
8836 write_vec_element_i32(s, tcg_res, rd, pass, size);
8837 }
8838 }
8839 tcg_temp_free_i32(tcg_res);
8840 tcg_temp_free_i32(tcg_zero);
8841 tcg_temp_free_i32(tcg_op);
8842 if (!is_scalar) {
8843 clear_vec_high(s, is_q, rd);
8844 }
8845 }
8846
8847 tcg_temp_free_ptr(fpst);
8848 }
8849
8850 static void handle_2misc_reciprocal(DisasContext *s, int opcode,
8851 bool is_scalar, bool is_u, bool is_q,
8852 int size, int rn, int rd)
8853 {
8854 bool is_double = (size == 3);
8855 TCGv_ptr fpst = get_fpstatus_ptr(false);
8856
8857 if (is_double) {
8858 TCGv_i64 tcg_op = tcg_temp_new_i64();
8859 TCGv_i64 tcg_res = tcg_temp_new_i64();
8860 int pass;
8861
8862 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
8863 read_vec_element(s, tcg_op, rn, pass, MO_64);
8864 switch (opcode) {
8865 case 0x3d: /* FRECPE */
8866 gen_helper_recpe_f64(tcg_res, tcg_op, fpst);
8867 break;
8868 case 0x3f: /* FRECPX */
8869 gen_helper_frecpx_f64(tcg_res, tcg_op, fpst);
8870 break;
8871 case 0x7d: /* FRSQRTE */
8872 gen_helper_rsqrte_f64(tcg_res, tcg_op, fpst);
8873 break;
8874 default:
8875 g_assert_not_reached();
8876 }
8877 write_vec_element(s, tcg_res, rd, pass, MO_64);
8878 }
8879 tcg_temp_free_i64(tcg_res);
8880 tcg_temp_free_i64(tcg_op);
8881 clear_vec_high(s, !is_scalar, rd);
8882 } else {
8883 TCGv_i32 tcg_op = tcg_temp_new_i32();
8884 TCGv_i32 tcg_res = tcg_temp_new_i32();
8885 int pass, maxpasses;
8886
8887 if (is_scalar) {
8888 maxpasses = 1;
8889 } else {
8890 maxpasses = is_q ? 4 : 2;
8891 }
8892
8893 for (pass = 0; pass < maxpasses; pass++) {
8894 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
8895
8896 switch (opcode) {
8897 case 0x3c: /* URECPE */
8898 gen_helper_recpe_u32(tcg_res, tcg_op, fpst);
8899 break;
8900 case 0x3d: /* FRECPE */
8901 gen_helper_recpe_f32(tcg_res, tcg_op, fpst);
8902 break;
8903 case 0x3f: /* FRECPX */
8904 gen_helper_frecpx_f32(tcg_res, tcg_op, fpst);
8905 break;
8906 case 0x7d: /* FRSQRTE */
8907 gen_helper_rsqrte_f32(tcg_res, tcg_op, fpst);
8908 break;
8909 default:
8910 g_assert_not_reached();
8911 }
8912
8913 if (is_scalar) {
8914 write_fp_sreg(s, rd, tcg_res);
8915 } else {
8916 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
8917 }
8918 }
8919 tcg_temp_free_i32(tcg_res);
8920 tcg_temp_free_i32(tcg_op);
8921 if (!is_scalar) {
8922 clear_vec_high(s, is_q, rd);
8923 }
8924 }
8925 tcg_temp_free_ptr(fpst);
8926 }
8927
8928 static void handle_2misc_narrow(DisasContext *s, bool scalar,
8929 int opcode, bool u, bool is_q,
8930 int size, int rn, int rd)
8931 {
8932 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
8933 * in the source becomes a size element in the destination).
8934 */
8935 int pass;
8936 TCGv_i32 tcg_res[2];
8937 int destelt = is_q ? 2 : 0;
8938 int passes = scalar ? 1 : 2;
8939
8940 if (scalar) {
8941 tcg_res[1] = tcg_const_i32(0);
8942 }
8943
8944 for (pass = 0; pass < passes; pass++) {
8945 TCGv_i64 tcg_op = tcg_temp_new_i64();
8946 NeonGenNarrowFn *genfn = NULL;
8947 NeonGenNarrowEnvFn *genenvfn = NULL;
8948
8949 if (scalar) {
8950 read_vec_element(s, tcg_op, rn, pass, size + 1);
8951 } else {
8952 read_vec_element(s, tcg_op, rn, pass, MO_64);
8953 }
8954 tcg_res[pass] = tcg_temp_new_i32();
8955
8956 switch (opcode) {
8957 case 0x12: /* XTN, SQXTUN */
8958 {
8959 static NeonGenNarrowFn * const xtnfns[3] = {
8960 gen_helper_neon_narrow_u8,
8961 gen_helper_neon_narrow_u16,
8962 tcg_gen_extrl_i64_i32,
8963 };
8964 static NeonGenNarrowEnvFn * const sqxtunfns[3] = {
8965 gen_helper_neon_unarrow_sat8,
8966 gen_helper_neon_unarrow_sat16,
8967 gen_helper_neon_unarrow_sat32,
8968 };
8969 if (u) {
8970 genenvfn = sqxtunfns[size];
8971 } else {
8972 genfn = xtnfns[size];
8973 }
8974 break;
8975 }
8976 case 0x14: /* SQXTN, UQXTN */
8977 {
8978 static NeonGenNarrowEnvFn * const fns[3][2] = {
8979 { gen_helper_neon_narrow_sat_s8,
8980 gen_helper_neon_narrow_sat_u8 },
8981 { gen_helper_neon_narrow_sat_s16,
8982 gen_helper_neon_narrow_sat_u16 },
8983 { gen_helper_neon_narrow_sat_s32,
8984 gen_helper_neon_narrow_sat_u32 },
8985 };
8986 genenvfn = fns[size][u];
8987 break;
8988 }
8989 case 0x16: /* FCVTN, FCVTN2 */
8990 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
8991 if (size == 2) {
8992 gen_helper_vfp_fcvtsd(tcg_res[pass], tcg_op, cpu_env);
8993 } else {
8994 TCGv_i32 tcg_lo = tcg_temp_new_i32();
8995 TCGv_i32 tcg_hi = tcg_temp_new_i32();
8996 TCGv_ptr fpst = get_fpstatus_ptr(false);
8997 TCGv_i32 ahp = get_ahp_flag();
8998
8999 tcg_gen_extr_i64_i32(tcg_lo, tcg_hi, tcg_op);
9000 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo, tcg_lo, fpst, ahp);
9001 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi, tcg_hi, fpst, ahp);
9002 tcg_gen_deposit_i32(tcg_res[pass], tcg_lo, tcg_hi, 16, 16);
9003 tcg_temp_free_i32(tcg_lo);
9004 tcg_temp_free_i32(tcg_hi);
9005 tcg_temp_free_ptr(fpst);
9006 tcg_temp_free_i32(ahp);
9007 }
9008 break;
9009 case 0x56: /* FCVTXN, FCVTXN2 */
9010 /* 64 bit to 32 bit float conversion
9011 * with von Neumann rounding (round to odd)
9012 */
9013 assert(size == 2);
9014 gen_helper_fcvtx_f64_to_f32(tcg_res[pass], tcg_op, cpu_env);
9015 break;
9016 default:
9017 g_assert_not_reached();
9018 }
9019
9020 if (genfn) {
9021 genfn(tcg_res[pass], tcg_op);
9022 } else if (genenvfn) {
9023 genenvfn(tcg_res[pass], cpu_env, tcg_op);
9024 }
9025
9026 tcg_temp_free_i64(tcg_op);
9027 }
9028
9029 for (pass = 0; pass < 2; pass++) {
9030 write_vec_element_i32(s, tcg_res[pass], rd, destelt + pass, MO_32);
9031 tcg_temp_free_i32(tcg_res[pass]);
9032 }
9033 clear_vec_high(s, is_q, rd);
9034 }
9035
9036 /* Remaining saturating accumulating ops */
9037 static void handle_2misc_satacc(DisasContext *s, bool is_scalar, bool is_u,
9038 bool is_q, int size, int rn, int rd)
9039 {
9040 bool is_double = (size == 3);
9041
9042 if (is_double) {
9043 TCGv_i64 tcg_rn = tcg_temp_new_i64();
9044 TCGv_i64 tcg_rd = tcg_temp_new_i64();
9045 int pass;
9046
9047 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
9048 read_vec_element(s, tcg_rn, rn, pass, MO_64);
9049 read_vec_element(s, tcg_rd, rd, pass, MO_64);
9050
9051 if (is_u) { /* USQADD */
9052 gen_helper_neon_uqadd_s64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9053 } else { /* SUQADD */
9054 gen_helper_neon_sqadd_u64(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9055 }
9056 write_vec_element(s, tcg_rd, rd, pass, MO_64);
9057 }
9058 tcg_temp_free_i64(tcg_rd);
9059 tcg_temp_free_i64(tcg_rn);
9060 clear_vec_high(s, !is_scalar, rd);
9061 } else {
9062 TCGv_i32 tcg_rn = tcg_temp_new_i32();
9063 TCGv_i32 tcg_rd = tcg_temp_new_i32();
9064 int pass, maxpasses;
9065
9066 if (is_scalar) {
9067 maxpasses = 1;
9068 } else {
9069 maxpasses = is_q ? 4 : 2;
9070 }
9071
9072 for (pass = 0; pass < maxpasses; pass++) {
9073 if (is_scalar) {
9074 read_vec_element_i32(s, tcg_rn, rn, pass, size);
9075 read_vec_element_i32(s, tcg_rd, rd, pass, size);
9076 } else {
9077 read_vec_element_i32(s, tcg_rn, rn, pass, MO_32);
9078 read_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
9079 }
9080
9081 if (is_u) { /* USQADD */
9082 switch (size) {
9083 case 0:
9084 gen_helper_neon_uqadd_s8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9085 break;
9086 case 1:
9087 gen_helper_neon_uqadd_s16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9088 break;
9089 case 2:
9090 gen_helper_neon_uqadd_s32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9091 break;
9092 default:
9093 g_assert_not_reached();
9094 }
9095 } else { /* SUQADD */
9096 switch (size) {
9097 case 0:
9098 gen_helper_neon_sqadd_u8(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9099 break;
9100 case 1:
9101 gen_helper_neon_sqadd_u16(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9102 break;
9103 case 2:
9104 gen_helper_neon_sqadd_u32(tcg_rd, cpu_env, tcg_rn, tcg_rd);
9105 break;
9106 default:
9107 g_assert_not_reached();
9108 }
9109 }
9110
9111 if (is_scalar) {
9112 TCGv_i64 tcg_zero = tcg_const_i64(0);
9113 write_vec_element(s, tcg_zero, rd, 0, MO_64);
9114 tcg_temp_free_i64(tcg_zero);
9115 }
9116 write_vec_element_i32(s, tcg_rd, rd, pass, MO_32);
9117 }
9118 tcg_temp_free_i32(tcg_rd);
9119 tcg_temp_free_i32(tcg_rn);
9120 clear_vec_high(s, is_q, rd);
9121 }
9122 }
9123
9124 /* AdvSIMD scalar two reg misc
9125 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9126 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9127 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9128 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9129 */
9130 static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
9131 {
9132 int rd = extract32(insn, 0, 5);
9133 int rn = extract32(insn, 5, 5);
9134 int opcode = extract32(insn, 12, 5);
9135 int size = extract32(insn, 22, 2);
9136 bool u = extract32(insn, 29, 1);
9137 bool is_fcvt = false;
9138 int rmode;
9139 TCGv_i32 tcg_rmode;
9140 TCGv_ptr tcg_fpstatus;
9141
9142 switch (opcode) {
9143 case 0x3: /* USQADD / SUQADD*/
9144 if (!fp_access_check(s)) {
9145 return;
9146 }
9147 handle_2misc_satacc(s, true, u, false, size, rn, rd);
9148 return;
9149 case 0x7: /* SQABS / SQNEG */
9150 break;
9151 case 0xa: /* CMLT */
9152 if (u) {
9153 unallocated_encoding(s);
9154 return;
9155 }
9156 /* fall through */
9157 case 0x8: /* CMGT, CMGE */
9158 case 0x9: /* CMEQ, CMLE */
9159 case 0xb: /* ABS, NEG */
9160 if (size != 3) {
9161 unallocated_encoding(s);
9162 return;
9163 }
9164 break;
9165 case 0x12: /* SQXTUN */
9166 if (!u) {
9167 unallocated_encoding(s);
9168 return;
9169 }
9170 /* fall through */
9171 case 0x14: /* SQXTN, UQXTN */
9172 if (size == 3) {
9173 unallocated_encoding(s);
9174 return;
9175 }
9176 if (!fp_access_check(s)) {
9177 return;
9178 }
9179 handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
9180 return;
9181 case 0xc ... 0xf:
9182 case 0x16 ... 0x1d:
9183 case 0x1f:
9184 /* Floating point: U, size[1] and opcode indicate operation;
9185 * size[0] indicates single or double precision.
9186 */
9187 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
9188 size = extract32(size, 0, 1) ? 3 : 2;
9189 switch (opcode) {
9190 case 0x2c: /* FCMGT (zero) */
9191 case 0x2d: /* FCMEQ (zero) */
9192 case 0x2e: /* FCMLT (zero) */
9193 case 0x6c: /* FCMGE (zero) */
9194 case 0x6d: /* FCMLE (zero) */
9195 handle_2misc_fcmp_zero(s, opcode, true, u, true, size, rn, rd);
9196 return;
9197 case 0x1d: /* SCVTF */
9198 case 0x5d: /* UCVTF */
9199 {
9200 bool is_signed = (opcode == 0x1d);
9201 if (!fp_access_check(s)) {
9202 return;
9203 }
9204 handle_simd_intfp_conv(s, rd, rn, 1, is_signed, 0, size);
9205 return;
9206 }
9207 case 0x3d: /* FRECPE */
9208 case 0x3f: /* FRECPX */
9209 case 0x7d: /* FRSQRTE */
9210 if (!fp_access_check(s)) {
9211 return;
9212 }
9213 handle_2misc_reciprocal(s, opcode, true, u, true, size, rn, rd);
9214 return;
9215 case 0x1a: /* FCVTNS */
9216 case 0x1b: /* FCVTMS */
9217 case 0x3a: /* FCVTPS */
9218 case 0x3b: /* FCVTZS */
9219 case 0x5a: /* FCVTNU */
9220 case 0x5b: /* FCVTMU */
9221 case 0x7a: /* FCVTPU */
9222 case 0x7b: /* FCVTZU */
9223 is_fcvt = true;
9224 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
9225 break;
9226 case 0x1c: /* FCVTAS */
9227 case 0x5c: /* FCVTAU */
9228 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9229 is_fcvt = true;
9230 rmode = FPROUNDING_TIEAWAY;
9231 break;
9232 case 0x56: /* FCVTXN, FCVTXN2 */
9233 if (size == 2) {
9234 unallocated_encoding(s);
9235 return;
9236 }
9237 if (!fp_access_check(s)) {
9238 return;
9239 }
9240 handle_2misc_narrow(s, true, opcode, u, false, size - 1, rn, rd);
9241 return;
9242 default:
9243 unallocated_encoding(s);
9244 return;
9245 }
9246 break;
9247 default:
9248 unallocated_encoding(s);
9249 return;
9250 }
9251
9252 if (!fp_access_check(s)) {
9253 return;
9254 }
9255
9256 if (is_fcvt) {
9257 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
9258 tcg_fpstatus = get_fpstatus_ptr(false);
9259 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
9260 } else {
9261 tcg_rmode = NULL;
9262 tcg_fpstatus = NULL;
9263 }
9264
9265 if (size == 3) {
9266 TCGv_i64 tcg_rn = read_fp_dreg(s, rn);
9267 TCGv_i64 tcg_rd = tcg_temp_new_i64();
9268
9269 handle_2misc_64(s, opcode, u, tcg_rd, tcg_rn, tcg_rmode, tcg_fpstatus);
9270 write_fp_dreg(s, rd, tcg_rd);
9271 tcg_temp_free_i64(tcg_rd);
9272 tcg_temp_free_i64(tcg_rn);
9273 } else {
9274 TCGv_i32 tcg_rn = tcg_temp_new_i32();
9275 TCGv_i32 tcg_rd = tcg_temp_new_i32();
9276
9277 read_vec_element_i32(s, tcg_rn, rn, 0, size);
9278
9279 switch (opcode) {
9280 case 0x7: /* SQABS, SQNEG */
9281 {
9282 NeonGenOneOpEnvFn *genfn;
9283 static NeonGenOneOpEnvFn * const fns[3][2] = {
9284 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
9285 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
9286 { gen_helper_neon_qabs_s32, gen_helper_neon_qneg_s32 },
9287 };
9288 genfn = fns[size][u];
9289 genfn(tcg_rd, cpu_env, tcg_rn);
9290 break;
9291 }
9292 case 0x1a: /* FCVTNS */
9293 case 0x1b: /* FCVTMS */
9294 case 0x1c: /* FCVTAS */
9295 case 0x3a: /* FCVTPS */
9296 case 0x3b: /* FCVTZS */
9297 {
9298 TCGv_i32 tcg_shift = tcg_const_i32(0);
9299 gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
9300 tcg_temp_free_i32(tcg_shift);
9301 break;
9302 }
9303 case 0x5a: /* FCVTNU */
9304 case 0x5b: /* FCVTMU */
9305 case 0x5c: /* FCVTAU */
9306 case 0x7a: /* FCVTPU */
9307 case 0x7b: /* FCVTZU */
9308 {
9309 TCGv_i32 tcg_shift = tcg_const_i32(0);
9310 gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus);
9311 tcg_temp_free_i32(tcg_shift);
9312 break;
9313 }
9314 default:
9315 g_assert_not_reached();
9316 }
9317
9318 write_fp_sreg(s, rd, tcg_rd);
9319 tcg_temp_free_i32(tcg_rd);
9320 tcg_temp_free_i32(tcg_rn);
9321 }
9322
9323 if (is_fcvt) {
9324 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
9325 tcg_temp_free_i32(tcg_rmode);
9326 tcg_temp_free_ptr(tcg_fpstatus);
9327 }
9328 }
9329
9330 static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9331 {
9332 tcg_gen_vec_sar8i_i64(a, a, shift);
9333 tcg_gen_vec_add8_i64(d, d, a);
9334 }
9335
9336 static void gen_ssra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9337 {
9338 tcg_gen_vec_sar16i_i64(a, a, shift);
9339 tcg_gen_vec_add16_i64(d, d, a);
9340 }
9341
9342 static void gen_ssra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
9343 {
9344 tcg_gen_sari_i32(a, a, shift);
9345 tcg_gen_add_i32(d, d, a);
9346 }
9347
9348 static void gen_ssra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9349 {
9350 tcg_gen_sari_i64(a, a, shift);
9351 tcg_gen_add_i64(d, d, a);
9352 }
9353
9354 static void gen_ssra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
9355 {
9356 tcg_gen_sari_vec(vece, a, a, sh);
9357 tcg_gen_add_vec(vece, d, d, a);
9358 }
9359
9360 static void gen_usra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9361 {
9362 tcg_gen_vec_shr8i_i64(a, a, shift);
9363 tcg_gen_vec_add8_i64(d, d, a);
9364 }
9365
9366 static void gen_usra16_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9367 {
9368 tcg_gen_vec_shr16i_i64(a, a, shift);
9369 tcg_gen_vec_add16_i64(d, d, a);
9370 }
9371
9372 static void gen_usra32_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
9373 {
9374 tcg_gen_shri_i32(a, a, shift);
9375 tcg_gen_add_i32(d, d, a);
9376 }
9377
9378 static void gen_usra64_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9379 {
9380 tcg_gen_shri_i64(a, a, shift);
9381 tcg_gen_add_i64(d, d, a);
9382 }
9383
9384 static void gen_usra_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
9385 {
9386 tcg_gen_shri_vec(vece, a, a, sh);
9387 tcg_gen_add_vec(vece, d, d, a);
9388 }
9389
9390 static void gen_shr8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9391 {
9392 uint64_t mask = dup_const(MO_8, 0xff >> shift);
9393 TCGv_i64 t = tcg_temp_new_i64();
9394
9395 tcg_gen_shri_i64(t, a, shift);
9396 tcg_gen_andi_i64(t, t, mask);
9397 tcg_gen_andi_i64(d, d, ~mask);
9398 tcg_gen_or_i64(d, d, t);
9399 tcg_temp_free_i64(t);
9400 }
9401
9402 static void gen_shr16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9403 {
9404 uint64_t mask = dup_const(MO_16, 0xffff >> shift);
9405 TCGv_i64 t = tcg_temp_new_i64();
9406
9407 tcg_gen_shri_i64(t, a, shift);
9408 tcg_gen_andi_i64(t, t, mask);
9409 tcg_gen_andi_i64(d, d, ~mask);
9410 tcg_gen_or_i64(d, d, t);
9411 tcg_temp_free_i64(t);
9412 }
9413
9414 static void gen_shr32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
9415 {
9416 tcg_gen_shri_i32(a, a, shift);
9417 tcg_gen_deposit_i32(d, d, a, 0, 32 - shift);
9418 }
9419
9420 static void gen_shr64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9421 {
9422 tcg_gen_shri_i64(a, a, shift);
9423 tcg_gen_deposit_i64(d, d, a, 0, 64 - shift);
9424 }
9425
9426 static void gen_shr_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
9427 {
9428 uint64_t mask = (2ull << ((8 << vece) - 1)) - 1;
9429 TCGv_vec t = tcg_temp_new_vec_matching(d);
9430 TCGv_vec m = tcg_temp_new_vec_matching(d);
9431
9432 tcg_gen_dupi_vec(vece, m, mask ^ (mask >> sh));
9433 tcg_gen_shri_vec(vece, t, a, sh);
9434 tcg_gen_and_vec(vece, d, d, m);
9435 tcg_gen_or_vec(vece, d, d, t);
9436
9437 tcg_temp_free_vec(t);
9438 tcg_temp_free_vec(m);
9439 }
9440
9441 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9442 static void handle_vec_simd_shri(DisasContext *s, bool is_q, bool is_u,
9443 int immh, int immb, int opcode, int rn, int rd)
9444 {
9445 static const GVecGen2i ssra_op[4] = {
9446 { .fni8 = gen_ssra8_i64,
9447 .fniv = gen_ssra_vec,
9448 .load_dest = true,
9449 .opc = INDEX_op_sari_vec,
9450 .vece = MO_8 },
9451 { .fni8 = gen_ssra16_i64,
9452 .fniv = gen_ssra_vec,
9453 .load_dest = true,
9454 .opc = INDEX_op_sari_vec,
9455 .vece = MO_16 },
9456 { .fni4 = gen_ssra32_i32,
9457 .fniv = gen_ssra_vec,
9458 .load_dest = true,
9459 .opc = INDEX_op_sari_vec,
9460 .vece = MO_32 },
9461 { .fni8 = gen_ssra64_i64,
9462 .fniv = gen_ssra_vec,
9463 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
9464 .load_dest = true,
9465 .opc = INDEX_op_sari_vec,
9466 .vece = MO_64 },
9467 };
9468 static const GVecGen2i usra_op[4] = {
9469 { .fni8 = gen_usra8_i64,
9470 .fniv = gen_usra_vec,
9471 .load_dest = true,
9472 .opc = INDEX_op_shri_vec,
9473 .vece = MO_8, },
9474 { .fni8 = gen_usra16_i64,
9475 .fniv = gen_usra_vec,
9476 .load_dest = true,
9477 .opc = INDEX_op_shri_vec,
9478 .vece = MO_16, },
9479 { .fni4 = gen_usra32_i32,
9480 .fniv = gen_usra_vec,
9481 .load_dest = true,
9482 .opc = INDEX_op_shri_vec,
9483 .vece = MO_32, },
9484 { .fni8 = gen_usra64_i64,
9485 .fniv = gen_usra_vec,
9486 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
9487 .load_dest = true,
9488 .opc = INDEX_op_shri_vec,
9489 .vece = MO_64, },
9490 };
9491 static const GVecGen2i sri_op[4] = {
9492 { .fni8 = gen_shr8_ins_i64,
9493 .fniv = gen_shr_ins_vec,
9494 .load_dest = true,
9495 .opc = INDEX_op_shri_vec,
9496 .vece = MO_8 },
9497 { .fni8 = gen_shr16_ins_i64,
9498 .fniv = gen_shr_ins_vec,
9499 .load_dest = true,
9500 .opc = INDEX_op_shri_vec,
9501 .vece = MO_16 },
9502 { .fni4 = gen_shr32_ins_i32,
9503 .fniv = gen_shr_ins_vec,
9504 .load_dest = true,
9505 .opc = INDEX_op_shri_vec,
9506 .vece = MO_32 },
9507 { .fni8 = gen_shr64_ins_i64,
9508 .fniv = gen_shr_ins_vec,
9509 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
9510 .load_dest = true,
9511 .opc = INDEX_op_shri_vec,
9512 .vece = MO_64 },
9513 };
9514
9515 int size = 32 - clz32(immh) - 1;
9516 int immhb = immh << 3 | immb;
9517 int shift = 2 * (8 << size) - immhb;
9518 bool accumulate = false;
9519 int dsize = is_q ? 128 : 64;
9520 int esize = 8 << size;
9521 int elements = dsize/esize;
9522 TCGMemOp memop = size | (is_u ? 0 : MO_SIGN);
9523 TCGv_i64 tcg_rn = new_tmp_a64(s);
9524 TCGv_i64 tcg_rd = new_tmp_a64(s);
9525 TCGv_i64 tcg_round;
9526 uint64_t round_const;
9527 int i;
9528
9529 if (extract32(immh, 3, 1) && !is_q) {
9530 unallocated_encoding(s);
9531 return;
9532 }
9533 tcg_debug_assert(size <= 3);
9534
9535 if (!fp_access_check(s)) {
9536 return;
9537 }
9538
9539 switch (opcode) {
9540 case 0x02: /* SSRA / USRA (accumulate) */
9541 if (is_u) {
9542 /* Shift count same as element size produces zero to add. */
9543 if (shift == 8 << size) {
9544 goto done;
9545 }
9546 gen_gvec_op2i(s, is_q, rd, rn, shift, &usra_op[size]);
9547 } else {
9548 /* Shift count same as element size produces all sign to add. */
9549 if (shift == 8 << size) {
9550 shift -= 1;
9551 }
9552 gen_gvec_op2i(s, is_q, rd, rn, shift, &ssra_op[size]);
9553 }
9554 return;
9555 case 0x08: /* SRI */
9556 /* Shift count same as element size is valid but does nothing. */
9557 if (shift == 8 << size) {
9558 goto done;
9559 }
9560 gen_gvec_op2i(s, is_q, rd, rn, shift, &sri_op[size]);
9561 return;
9562
9563 case 0x00: /* SSHR / USHR */
9564 if (is_u) {
9565 if (shift == 8 << size) {
9566 /* Shift count the same size as element size produces zero. */
9567 tcg_gen_gvec_dup8i(vec_full_reg_offset(s, rd),
9568 is_q ? 16 : 8, vec_full_reg_size(s), 0);
9569 } else {
9570 gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shri, size);
9571 }
9572 } else {
9573 /* Shift count the same size as element size produces all sign. */
9574 if (shift == 8 << size) {
9575 shift -= 1;
9576 }
9577 gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_sari, size);
9578 }
9579 return;
9580
9581 case 0x04: /* SRSHR / URSHR (rounding) */
9582 break;
9583 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9584 accumulate = true;
9585 break;
9586 default:
9587 g_assert_not_reached();
9588 }
9589
9590 round_const = 1ULL << (shift - 1);
9591 tcg_round = tcg_const_i64(round_const);
9592
9593 for (i = 0; i < elements; i++) {
9594 read_vec_element(s, tcg_rn, rn, i, memop);
9595 if (accumulate) {
9596 read_vec_element(s, tcg_rd, rd, i, memop);
9597 }
9598
9599 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
9600 accumulate, is_u, size, shift);
9601
9602 write_vec_element(s, tcg_rd, rd, i, size);
9603 }
9604 tcg_temp_free_i64(tcg_round);
9605
9606 done:
9607 clear_vec_high(s, is_q, rd);
9608 }
9609
9610 static void gen_shl8_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9611 {
9612 uint64_t mask = dup_const(MO_8, 0xff << shift);
9613 TCGv_i64 t = tcg_temp_new_i64();
9614
9615 tcg_gen_shli_i64(t, a, shift);
9616 tcg_gen_andi_i64(t, t, mask);
9617 tcg_gen_andi_i64(d, d, ~mask);
9618 tcg_gen_or_i64(d, d, t);
9619 tcg_temp_free_i64(t);
9620 }
9621
9622 static void gen_shl16_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9623 {
9624 uint64_t mask = dup_const(MO_16, 0xffff << shift);
9625 TCGv_i64 t = tcg_temp_new_i64();
9626
9627 tcg_gen_shli_i64(t, a, shift);
9628 tcg_gen_andi_i64(t, t, mask);
9629 tcg_gen_andi_i64(d, d, ~mask);
9630 tcg_gen_or_i64(d, d, t);
9631 tcg_temp_free_i64(t);
9632 }
9633
9634 static void gen_shl32_ins_i32(TCGv_i32 d, TCGv_i32 a, int32_t shift)
9635 {
9636 tcg_gen_deposit_i32(d, d, a, shift, 32 - shift);
9637 }
9638
9639 static void gen_shl64_ins_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift)
9640 {
9641 tcg_gen_deposit_i64(d, d, a, shift, 64 - shift);
9642 }
9643
9644 static void gen_shl_ins_vec(unsigned vece, TCGv_vec d, TCGv_vec a, int64_t sh)
9645 {
9646 uint64_t mask = (1ull << sh) - 1;
9647 TCGv_vec t = tcg_temp_new_vec_matching(d);
9648 TCGv_vec m = tcg_temp_new_vec_matching(d);
9649
9650 tcg_gen_dupi_vec(vece, m, mask);
9651 tcg_gen_shli_vec(vece, t, a, sh);
9652 tcg_gen_and_vec(vece, d, d, m);
9653 tcg_gen_or_vec(vece, d, d, t);
9654
9655 tcg_temp_free_vec(t);
9656 tcg_temp_free_vec(m);
9657 }
9658
9659 /* SHL/SLI - Vector shift left */
9660 static void handle_vec_simd_shli(DisasContext *s, bool is_q, bool insert,
9661 int immh, int immb, int opcode, int rn, int rd)
9662 {
9663 static const GVecGen2i shi_op[4] = {
9664 { .fni8 = gen_shl8_ins_i64,
9665 .fniv = gen_shl_ins_vec,
9666 .opc = INDEX_op_shli_vec,
9667 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
9668 .load_dest = true,
9669 .vece = MO_8 },
9670 { .fni8 = gen_shl16_ins_i64,
9671 .fniv = gen_shl_ins_vec,
9672 .opc = INDEX_op_shli_vec,
9673 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
9674 .load_dest = true,
9675 .vece = MO_16 },
9676 { .fni4 = gen_shl32_ins_i32,
9677 .fniv = gen_shl_ins_vec,
9678 .opc = INDEX_op_shli_vec,
9679 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
9680 .load_dest = true,
9681 .vece = MO_32 },
9682 { .fni8 = gen_shl64_ins_i64,
9683 .fniv = gen_shl_ins_vec,
9684 .opc = INDEX_op_shli_vec,
9685 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
9686 .load_dest = true,
9687 .vece = MO_64 },
9688 };
9689 int size = 32 - clz32(immh) - 1;
9690 int immhb = immh << 3 | immb;
9691 int shift = immhb - (8 << size);
9692
9693 if (extract32(immh, 3, 1) && !is_q) {
9694 unallocated_encoding(s);
9695 return;
9696 }
9697
9698 if (size > 3 && !is_q) {
9699 unallocated_encoding(s);
9700 return;
9701 }
9702
9703 if (!fp_access_check(s)) {
9704 return;
9705 }
9706
9707 if (insert) {
9708 gen_gvec_op2i(s, is_q, rd, rn, shift, &shi_op[size]);
9709 } else {
9710 gen_gvec_fn2i(s, is_q, rd, rn, shift, tcg_gen_gvec_shli, size);
9711 }
9712 }
9713
9714 /* USHLL/SHLL - Vector shift left with widening */
9715 static void handle_vec_simd_wshli(DisasContext *s, bool is_q, bool is_u,
9716 int immh, int immb, int opcode, int rn, int rd)
9717 {
9718 int size = 32 - clz32(immh) - 1;
9719 int immhb = immh << 3 | immb;
9720 int shift = immhb - (8 << size);
9721 int dsize = 64;
9722 int esize = 8 << size;
9723 int elements = dsize/esize;
9724 TCGv_i64 tcg_rn = new_tmp_a64(s);
9725 TCGv_i64 tcg_rd = new_tmp_a64(s);
9726 int i;
9727
9728 if (size >= 3) {
9729 unallocated_encoding(s);
9730 return;
9731 }
9732
9733 if (!fp_access_check(s)) {
9734 return;
9735 }
9736
9737 /* For the LL variants the store is larger than the load,
9738 * so if rd == rn we would overwrite parts of our input.
9739 * So load everything right now and use shifts in the main loop.
9740 */
9741 read_vec_element(s, tcg_rn, rn, is_q ? 1 : 0, MO_64);
9742
9743 for (i = 0; i < elements; i++) {
9744 tcg_gen_shri_i64(tcg_rd, tcg_rn, i * esize);
9745 ext_and_shift_reg(tcg_rd, tcg_rd, size | (!is_u << 2), 0);
9746 tcg_gen_shli_i64(tcg_rd, tcg_rd, shift);
9747 write_vec_element(s, tcg_rd, rd, i, size + 1);
9748 }
9749 }
9750
9751 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
9752 static void handle_vec_simd_shrn(DisasContext *s, bool is_q,
9753 int immh, int immb, int opcode, int rn, int rd)
9754 {
9755 int immhb = immh << 3 | immb;
9756 int size = 32 - clz32(immh) - 1;
9757 int dsize = 64;
9758 int esize = 8 << size;
9759 int elements = dsize/esize;
9760 int shift = (2 * esize) - immhb;
9761 bool round = extract32(opcode, 0, 1);
9762 TCGv_i64 tcg_rn, tcg_rd, tcg_final;
9763 TCGv_i64 tcg_round;
9764 int i;
9765
9766 if (extract32(immh, 3, 1)) {
9767 unallocated_encoding(s);
9768 return;
9769 }
9770
9771 if (!fp_access_check(s)) {
9772 return;
9773 }
9774
9775 tcg_rn = tcg_temp_new_i64();
9776 tcg_rd = tcg_temp_new_i64();
9777 tcg_final = tcg_temp_new_i64();
9778 read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64);
9779
9780 if (round) {
9781 uint64_t round_const = 1ULL << (shift - 1);
9782 tcg_round = tcg_const_i64(round_const);
9783 } else {
9784 tcg_round = NULL;
9785 }
9786
9787 for (i = 0; i < elements; i++) {
9788 read_vec_element(s, tcg_rn, rn, i, size+1);
9789 handle_shri_with_rndacc(tcg_rd, tcg_rn, tcg_round,
9790 false, true, size+1, shift);
9791
9792 tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize);
9793 }
9794
9795 if (!is_q) {
9796 write_vec_element(s, tcg_final, rd, 0, MO_64);
9797 } else {
9798 write_vec_element(s, tcg_final, rd, 1, MO_64);
9799 }
9800 if (round) {
9801 tcg_temp_free_i64(tcg_round);
9802 }
9803 tcg_temp_free_i64(tcg_rn);
9804 tcg_temp_free_i64(tcg_rd);
9805 tcg_temp_free_i64(tcg_final);
9806
9807 clear_vec_high(s, is_q, rd);
9808 }
9809
9810
9811 /* AdvSIMD shift by immediate
9812 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9813 * +---+---+---+-------------+------+------+--------+---+------+------+
9814 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9815 * +---+---+---+-------------+------+------+--------+---+------+------+
9816 */
9817 static void disas_simd_shift_imm(DisasContext *s, uint32_t insn)
9818 {
9819 int rd = extract32(insn, 0, 5);
9820 int rn = extract32(insn, 5, 5);
9821 int opcode = extract32(insn, 11, 5);
9822 int immb = extract32(insn, 16, 3);
9823 int immh = extract32(insn, 19, 4);
9824 bool is_u = extract32(insn, 29, 1);
9825 bool is_q = extract32(insn, 30, 1);
9826
9827 switch (opcode) {
9828 case 0x08: /* SRI */
9829 if (!is_u) {
9830 unallocated_encoding(s);
9831 return;
9832 }
9833 /* fall through */
9834 case 0x00: /* SSHR / USHR */
9835 case 0x02: /* SSRA / USRA (accumulate) */
9836 case 0x04: /* SRSHR / URSHR (rounding) */
9837 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9838 handle_vec_simd_shri(s, is_q, is_u, immh, immb, opcode, rn, rd);
9839 break;
9840 case 0x0a: /* SHL / SLI */
9841 handle_vec_simd_shli(s, is_q, is_u, immh, immb, opcode, rn, rd);
9842 break;
9843 case 0x10: /* SHRN */
9844 case 0x11: /* RSHRN / SQRSHRUN */
9845 if (is_u) {
9846 handle_vec_simd_sqshrn(s, false, is_q, false, true, immh, immb,
9847 opcode, rn, rd);
9848 } else {
9849 handle_vec_simd_shrn(s, is_q, immh, immb, opcode, rn, rd);
9850 }
9851 break;
9852 case 0x12: /* SQSHRN / UQSHRN */
9853 case 0x13: /* SQRSHRN / UQRSHRN */
9854 handle_vec_simd_sqshrn(s, false, is_q, is_u, is_u, immh, immb,
9855 opcode, rn, rd);
9856 break;
9857 case 0x14: /* SSHLL / USHLL */
9858 handle_vec_simd_wshli(s, is_q, is_u, immh, immb, opcode, rn, rd);
9859 break;
9860 case 0x1c: /* SCVTF / UCVTF */
9861 handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
9862 opcode, rn, rd);
9863 break;
9864 case 0xc: /* SQSHLU */
9865 if (!is_u) {
9866 unallocated_encoding(s);
9867 return;
9868 }
9869 handle_simd_qshl(s, false, is_q, false, true, immh, immb, rn, rd);
9870 break;
9871 case 0xe: /* SQSHL, UQSHL */
9872 handle_simd_qshl(s, false, is_q, is_u, is_u, immh, immb, rn, rd);
9873 break;
9874 case 0x1f: /* FCVTZS/ FCVTZU */
9875 handle_simd_shift_fpint_conv(s, false, is_q, is_u, immh, immb, rn, rd);
9876 return;
9877 default:
9878 unallocated_encoding(s);
9879 return;
9880 }
9881 }
9882
9883 /* Generate code to do a "long" addition or subtraction, ie one done in
9884 * TCGv_i64 on vector lanes twice the width specified by size.
9885 */
9886 static void gen_neon_addl(int size, bool is_sub, TCGv_i64 tcg_res,
9887 TCGv_i64 tcg_op1, TCGv_i64 tcg_op2)
9888 {
9889 static NeonGenTwo64OpFn * const fns[3][2] = {
9890 { gen_helper_neon_addl_u16, gen_helper_neon_subl_u16 },
9891 { gen_helper_neon_addl_u32, gen_helper_neon_subl_u32 },
9892 { tcg_gen_add_i64, tcg_gen_sub_i64 },
9893 };
9894 NeonGenTwo64OpFn *genfn;
9895 assert(size < 3);
9896
9897 genfn = fns[size][is_sub];
9898 genfn(tcg_res, tcg_op1, tcg_op2);
9899 }
9900
9901 static void handle_3rd_widening(DisasContext *s, int is_q, int is_u, int size,
9902 int opcode, int rd, int rn, int rm)
9903 {
9904 /* 3-reg-different widening insns: 64 x 64 -> 128 */
9905 TCGv_i64 tcg_res[2];
9906 int pass, accop;
9907
9908 tcg_res[0] = tcg_temp_new_i64();
9909 tcg_res[1] = tcg_temp_new_i64();
9910
9911 /* Does this op do an adding accumulate, a subtracting accumulate,
9912 * or no accumulate at all?
9913 */
9914 switch (opcode) {
9915 case 5:
9916 case 8:
9917 case 9:
9918 accop = 1;
9919 break;
9920 case 10:
9921 case 11:
9922 accop = -1;
9923 break;
9924 default:
9925 accop = 0;
9926 break;
9927 }
9928
9929 if (accop != 0) {
9930 read_vec_element(s, tcg_res[0], rd, 0, MO_64);
9931 read_vec_element(s, tcg_res[1], rd, 1, MO_64);
9932 }
9933
9934 /* size == 2 means two 32x32->64 operations; this is worth special
9935 * casing because we can generally handle it inline.
9936 */
9937 if (size == 2) {
9938 for (pass = 0; pass < 2; pass++) {
9939 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
9940 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
9941 TCGv_i64 tcg_passres;
9942 TCGMemOp memop = MO_32 | (is_u ? 0 : MO_SIGN);
9943
9944 int elt = pass + is_q * 2;
9945
9946 read_vec_element(s, tcg_op1, rn, elt, memop);
9947 read_vec_element(s, tcg_op2, rm, elt, memop);
9948
9949 if (accop == 0) {
9950 tcg_passres = tcg_res[pass];
9951 } else {
9952 tcg_passres = tcg_temp_new_i64();
9953 }
9954
9955 switch (opcode) {
9956 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
9957 tcg_gen_add_i64(tcg_passres, tcg_op1, tcg_op2);
9958 break;
9959 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
9960 tcg_gen_sub_i64(tcg_passres, tcg_op1, tcg_op2);
9961 break;
9962 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
9963 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
9964 {
9965 TCGv_i64 tcg_tmp1 = tcg_temp_new_i64();
9966 TCGv_i64 tcg_tmp2 = tcg_temp_new_i64();
9967
9968 tcg_gen_sub_i64(tcg_tmp1, tcg_op1, tcg_op2);
9969 tcg_gen_sub_i64(tcg_tmp2, tcg_op2, tcg_op1);
9970 tcg_gen_movcond_i64(is_u ? TCG_COND_GEU : TCG_COND_GE,
9971 tcg_passres,
9972 tcg_op1, tcg_op2, tcg_tmp1, tcg_tmp2);
9973 tcg_temp_free_i64(tcg_tmp1);
9974 tcg_temp_free_i64(tcg_tmp2);
9975 break;
9976 }
9977 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
9978 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
9979 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
9980 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
9981 break;
9982 case 9: /* SQDMLAL, SQDMLAL2 */
9983 case 11: /* SQDMLSL, SQDMLSL2 */
9984 case 13: /* SQDMULL, SQDMULL2 */
9985 tcg_gen_mul_i64(tcg_passres, tcg_op1, tcg_op2);
9986 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
9987 tcg_passres, tcg_passres);
9988 break;
9989 default:
9990 g_assert_not_reached();
9991 }
9992
9993 if (opcode == 9 || opcode == 11) {
9994 /* saturating accumulate ops */
9995 if (accop < 0) {
9996 tcg_gen_neg_i64(tcg_passres, tcg_passres);
9997 }
9998 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
9999 tcg_res[pass], tcg_passres);
10000 } else if (accop > 0) {
10001 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10002 } else if (accop < 0) {
10003 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
10004 }
10005
10006 if (accop != 0) {
10007 tcg_temp_free_i64(tcg_passres);
10008 }
10009
10010 tcg_temp_free_i64(tcg_op1);
10011 tcg_temp_free_i64(tcg_op2);
10012 }
10013 } else {
10014 /* size 0 or 1, generally helper functions */
10015 for (pass = 0; pass < 2; pass++) {
10016 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
10017 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
10018 TCGv_i64 tcg_passres;
10019 int elt = pass + is_q * 2;
10020
10021 read_vec_element_i32(s, tcg_op1, rn, elt, MO_32);
10022 read_vec_element_i32(s, tcg_op2, rm, elt, MO_32);
10023
10024 if (accop == 0) {
10025 tcg_passres = tcg_res[pass];
10026 } else {
10027 tcg_passres = tcg_temp_new_i64();
10028 }
10029
10030 switch (opcode) {
10031 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10032 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10033 {
10034 TCGv_i64 tcg_op2_64 = tcg_temp_new_i64();
10035 static NeonGenWidenFn * const widenfns[2][2] = {
10036 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
10037 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
10038 };
10039 NeonGenWidenFn *widenfn = widenfns[size][is_u];
10040
10041 widenfn(tcg_op2_64, tcg_op2);
10042 widenfn(tcg_passres, tcg_op1);
10043 gen_neon_addl(size, (opcode == 2), tcg_passres,
10044 tcg_passres, tcg_op2_64);
10045 tcg_temp_free_i64(tcg_op2_64);
10046 break;
10047 }
10048 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10049 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10050 if (size == 0) {
10051 if (is_u) {
10052 gen_helper_neon_abdl_u16(tcg_passres, tcg_op1, tcg_op2);
10053 } else {
10054 gen_helper_neon_abdl_s16(tcg_passres, tcg_op1, tcg_op2);
10055 }
10056 } else {
10057 if (is_u) {
10058 gen_helper_neon_abdl_u32(tcg_passres, tcg_op1, tcg_op2);
10059 } else {
10060 gen_helper_neon_abdl_s32(tcg_passres, tcg_op1, tcg_op2);
10061 }
10062 }
10063 break;
10064 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10065 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10066 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10067 if (size == 0) {
10068 if (is_u) {
10069 gen_helper_neon_mull_u8(tcg_passres, tcg_op1, tcg_op2);
10070 } else {
10071 gen_helper_neon_mull_s8(tcg_passres, tcg_op1, tcg_op2);
10072 }
10073 } else {
10074 if (is_u) {
10075 gen_helper_neon_mull_u16(tcg_passres, tcg_op1, tcg_op2);
10076 } else {
10077 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
10078 }
10079 }
10080 break;
10081 case 9: /* SQDMLAL, SQDMLAL2 */
10082 case 11: /* SQDMLSL, SQDMLSL2 */
10083 case 13: /* SQDMULL, SQDMULL2 */
10084 assert(size == 1);
10085 gen_helper_neon_mull_s16(tcg_passres, tcg_op1, tcg_op2);
10086 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
10087 tcg_passres, tcg_passres);
10088 break;
10089 case 14: /* PMULL */
10090 assert(size == 0);
10091 gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2);
10092 break;
10093 default:
10094 g_assert_not_reached();
10095 }
10096 tcg_temp_free_i32(tcg_op1);
10097 tcg_temp_free_i32(tcg_op2);
10098
10099 if (accop != 0) {
10100 if (opcode == 9 || opcode == 11) {
10101 /* saturating accumulate ops */
10102 if (accop < 0) {
10103 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
10104 }
10105 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
10106 tcg_res[pass],
10107 tcg_passres);
10108 } else {
10109 gen_neon_addl(size, (accop < 0), tcg_res[pass],
10110 tcg_res[pass], tcg_passres);
10111 }
10112 tcg_temp_free_i64(tcg_passres);
10113 }
10114 }
10115 }
10116
10117 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
10118 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
10119 tcg_temp_free_i64(tcg_res[0]);
10120 tcg_temp_free_i64(tcg_res[1]);
10121 }
10122
10123 static void handle_3rd_wide(DisasContext *s, int is_q, int is_u, int size,
10124 int opcode, int rd, int rn, int rm)
10125 {
10126 TCGv_i64 tcg_res[2];
10127 int part = is_q ? 2 : 0;
10128 int pass;
10129
10130 for (pass = 0; pass < 2; pass++) {
10131 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10132 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
10133 TCGv_i64 tcg_op2_wide = tcg_temp_new_i64();
10134 static NeonGenWidenFn * const widenfns[3][2] = {
10135 { gen_helper_neon_widen_s8, gen_helper_neon_widen_u8 },
10136 { gen_helper_neon_widen_s16, gen_helper_neon_widen_u16 },
10137 { tcg_gen_ext_i32_i64, tcg_gen_extu_i32_i64 },
10138 };
10139 NeonGenWidenFn *widenfn = widenfns[size][is_u];
10140
10141 read_vec_element(s, tcg_op1, rn, pass, MO_64);
10142 read_vec_element_i32(s, tcg_op2, rm, part + pass, MO_32);
10143 widenfn(tcg_op2_wide, tcg_op2);
10144 tcg_temp_free_i32(tcg_op2);
10145 tcg_res[pass] = tcg_temp_new_i64();
10146 gen_neon_addl(size, (opcode == 3),
10147 tcg_res[pass], tcg_op1, tcg_op2_wide);
10148 tcg_temp_free_i64(tcg_op1);
10149 tcg_temp_free_i64(tcg_op2_wide);
10150 }
10151
10152 for (pass = 0; pass < 2; pass++) {
10153 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10154 tcg_temp_free_i64(tcg_res[pass]);
10155 }
10156 }
10157
10158 static void do_narrow_round_high_u32(TCGv_i32 res, TCGv_i64 in)
10159 {
10160 tcg_gen_addi_i64(in, in, 1U << 31);
10161 tcg_gen_extrh_i64_i32(res, in);
10162 }
10163
10164 static void handle_3rd_narrowing(DisasContext *s, int is_q, int is_u, int size,
10165 int opcode, int rd, int rn, int rm)
10166 {
10167 TCGv_i32 tcg_res[2];
10168 int part = is_q ? 2 : 0;
10169 int pass;
10170
10171 for (pass = 0; pass < 2; pass++) {
10172 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10173 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
10174 TCGv_i64 tcg_wideres = tcg_temp_new_i64();
10175 static NeonGenNarrowFn * const narrowfns[3][2] = {
10176 { gen_helper_neon_narrow_high_u8,
10177 gen_helper_neon_narrow_round_high_u8 },
10178 { gen_helper_neon_narrow_high_u16,
10179 gen_helper_neon_narrow_round_high_u16 },
10180 { tcg_gen_extrh_i64_i32, do_narrow_round_high_u32 },
10181 };
10182 NeonGenNarrowFn *gennarrow = narrowfns[size][is_u];
10183
10184 read_vec_element(s, tcg_op1, rn, pass, MO_64);
10185 read_vec_element(s, tcg_op2, rm, pass, MO_64);
10186
10187 gen_neon_addl(size, (opcode == 6), tcg_wideres, tcg_op1, tcg_op2);
10188
10189 tcg_temp_free_i64(tcg_op1);
10190 tcg_temp_free_i64(tcg_op2);
10191
10192 tcg_res[pass] = tcg_temp_new_i32();
10193 gennarrow(tcg_res[pass], tcg_wideres);
10194 tcg_temp_free_i64(tcg_wideres);
10195 }
10196
10197 for (pass = 0; pass < 2; pass++) {
10198 write_vec_element_i32(s, tcg_res[pass], rd, pass + part, MO_32);
10199 tcg_temp_free_i32(tcg_res[pass]);
10200 }
10201 clear_vec_high(s, is_q, rd);
10202 }
10203
10204 static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int rm)
10205 {
10206 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10207 * is the only three-reg-diff instruction which produces a
10208 * 128-bit wide result from a single operation. However since
10209 * it's possible to calculate the two halves more or less
10210 * separately we just use two helper calls.
10211 */
10212 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10213 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
10214 TCGv_i64 tcg_res = tcg_temp_new_i64();
10215
10216 read_vec_element(s, tcg_op1, rn, is_q, MO_64);
10217 read_vec_element(s, tcg_op2, rm, is_q, MO_64);
10218 gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2);
10219 write_vec_element(s, tcg_res, rd, 0, MO_64);
10220 gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2);
10221 write_vec_element(s, tcg_res, rd, 1, MO_64);
10222
10223 tcg_temp_free_i64(tcg_op1);
10224 tcg_temp_free_i64(tcg_op2);
10225 tcg_temp_free_i64(tcg_res);
10226 }
10227
10228 /* AdvSIMD three different
10229 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10230 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10231 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10232 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10233 */
10234 static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
10235 {
10236 /* Instructions in this group fall into three basic classes
10237 * (in each case with the operation working on each element in
10238 * the input vectors):
10239 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10240 * 128 bit input)
10241 * (2) wide 64 x 128 -> 128
10242 * (3) narrowing 128 x 128 -> 64
10243 * Here we do initial decode, catch unallocated cases and
10244 * dispatch to separate functions for each class.
10245 */
10246 int is_q = extract32(insn, 30, 1);
10247 int is_u = extract32(insn, 29, 1);
10248 int size = extract32(insn, 22, 2);
10249 int opcode = extract32(insn, 12, 4);
10250 int rm = extract32(insn, 16, 5);
10251 int rn = extract32(insn, 5, 5);
10252 int rd = extract32(insn, 0, 5);
10253
10254 switch (opcode) {
10255 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10256 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10257 /* 64 x 128 -> 128 */
10258 if (size == 3) {
10259 unallocated_encoding(s);
10260 return;
10261 }
10262 if (!fp_access_check(s)) {
10263 return;
10264 }
10265 handle_3rd_wide(s, is_q, is_u, size, opcode, rd, rn, rm);
10266 break;
10267 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10268 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10269 /* 128 x 128 -> 64 */
10270 if (size == 3) {
10271 unallocated_encoding(s);
10272 return;
10273 }
10274 if (!fp_access_check(s)) {
10275 return;
10276 }
10277 handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm);
10278 break;
10279 case 14: /* PMULL, PMULL2 */
10280 if (is_u || size == 1 || size == 2) {
10281 unallocated_encoding(s);
10282 return;
10283 }
10284 if (size == 3) {
10285 if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
10286 unallocated_encoding(s);
10287 return;
10288 }
10289 if (!fp_access_check(s)) {
10290 return;
10291 }
10292 handle_pmull_64(s, is_q, rd, rn, rm);
10293 return;
10294 }
10295 goto is_widening;
10296 case 9: /* SQDMLAL, SQDMLAL2 */
10297 case 11: /* SQDMLSL, SQDMLSL2 */
10298 case 13: /* SQDMULL, SQDMULL2 */
10299 if (is_u || size == 0) {
10300 unallocated_encoding(s);
10301 return;
10302 }
10303 /* fall through */
10304 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10305 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10306 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10307 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10308 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10309 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10310 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10311 /* 64 x 64 -> 128 */
10312 if (size == 3) {
10313 unallocated_encoding(s);
10314 return;
10315 }
10316 is_widening:
10317 if (!fp_access_check(s)) {
10318 return;
10319 }
10320
10321 handle_3rd_widening(s, is_q, is_u, size, opcode, rd, rn, rm);
10322 break;
10323 default:
10324 /* opcode 15 not allocated */
10325 unallocated_encoding(s);
10326 break;
10327 }
10328 }
10329
10330 static void gen_bsl_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
10331 {
10332 tcg_gen_xor_i64(rn, rn, rm);
10333 tcg_gen_and_i64(rn, rn, rd);
10334 tcg_gen_xor_i64(rd, rm, rn);
10335 }
10336
10337 static void gen_bit_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
10338 {
10339 tcg_gen_xor_i64(rn, rn, rd);
10340 tcg_gen_and_i64(rn, rn, rm);
10341 tcg_gen_xor_i64(rd, rd, rn);
10342 }
10343
10344 static void gen_bif_i64(TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
10345 {
10346 tcg_gen_xor_i64(rn, rn, rd);
10347 tcg_gen_andc_i64(rn, rn, rm);
10348 tcg_gen_xor_i64(rd, rd, rn);
10349 }
10350
10351 static void gen_bsl_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
10352 {
10353 tcg_gen_xor_vec(vece, rn, rn, rm);
10354 tcg_gen_and_vec(vece, rn, rn, rd);
10355 tcg_gen_xor_vec(vece, rd, rm, rn);
10356 }
10357
10358 static void gen_bit_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
10359 {
10360 tcg_gen_xor_vec(vece, rn, rn, rd);
10361 tcg_gen_and_vec(vece, rn, rn, rm);
10362 tcg_gen_xor_vec(vece, rd, rd, rn);
10363 }
10364
10365 static void gen_bif_vec(unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
10366 {
10367 tcg_gen_xor_vec(vece, rn, rn, rd);
10368 tcg_gen_andc_vec(vece, rn, rn, rm);
10369 tcg_gen_xor_vec(vece, rd, rd, rn);
10370 }
10371
10372 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10373 static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
10374 {
10375 static const GVecGen3 bsl_op = {
10376 .fni8 = gen_bsl_i64,
10377 .fniv = gen_bsl_vec,
10378 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
10379 .load_dest = true
10380 };
10381 static const GVecGen3 bit_op = {
10382 .fni8 = gen_bit_i64,
10383 .fniv = gen_bit_vec,
10384 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
10385 .load_dest = true
10386 };
10387 static const GVecGen3 bif_op = {
10388 .fni8 = gen_bif_i64,
10389 .fniv = gen_bif_vec,
10390 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
10391 .load_dest = true
10392 };
10393
10394 int rd = extract32(insn, 0, 5);
10395 int rn = extract32(insn, 5, 5);
10396 int rm = extract32(insn, 16, 5);
10397 int size = extract32(insn, 22, 2);
10398 bool is_u = extract32(insn, 29, 1);
10399 bool is_q = extract32(insn, 30, 1);
10400
10401 if (!fp_access_check(s)) {
10402 return;
10403 }
10404
10405 switch (size + 4 * is_u) {
10406 case 0: /* AND */
10407 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0);
10408 return;
10409 case 1: /* BIC */
10410 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
10411 return;
10412 case 2: /* ORR */
10413 if (rn == rm) { /* MOV */
10414 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0);
10415 } else {
10416 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
10417 }
10418 return;
10419 case 3: /* ORN */
10420 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);
10421 return;
10422 case 4: /* EOR */
10423 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0);
10424 return;
10425
10426 case 5: /* BSL bitwise select */
10427 gen_gvec_op3(s, is_q, rd, rn, rm, &bsl_op);
10428 return;
10429 case 6: /* BIT, bitwise insert if true */
10430 gen_gvec_op3(s, is_q, rd, rn, rm, &bit_op);
10431 return;
10432 case 7: /* BIF, bitwise insert if false */
10433 gen_gvec_op3(s, is_q, rd, rn, rm, &bif_op);
10434 return;
10435
10436 default:
10437 g_assert_not_reached();
10438 }
10439 }
10440
10441 /* Pairwise op subgroup of C3.6.16.
10442 *
10443 * This is called directly or via the handle_3same_float for float pairwise
10444 * operations where the opcode and size are calculated differently.
10445 */
10446 static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
10447 int size, int rn, int rm, int rd)
10448 {
10449 TCGv_ptr fpst;
10450 int pass;
10451
10452 /* Floating point operations need fpst */
10453 if (opcode >= 0x58) {
10454 fpst = get_fpstatus_ptr(false);
10455 } else {
10456 fpst = NULL;
10457 }
10458
10459 if (!fp_access_check(s)) {
10460 return;
10461 }
10462
10463 /* These operations work on the concatenated rm:rn, with each pair of
10464 * adjacent elements being operated on to produce an element in the result.
10465 */
10466 if (size == 3) {
10467 TCGv_i64 tcg_res[2];
10468
10469 for (pass = 0; pass < 2; pass++) {
10470 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10471 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
10472 int passreg = (pass == 0) ? rn : rm;
10473
10474 read_vec_element(s, tcg_op1, passreg, 0, MO_64);
10475 read_vec_element(s, tcg_op2, passreg, 1, MO_64);
10476 tcg_res[pass] = tcg_temp_new_i64();
10477
10478 switch (opcode) {
10479 case 0x17: /* ADDP */
10480 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
10481 break;
10482 case 0x58: /* FMAXNMP */
10483 gen_helper_vfp_maxnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10484 break;
10485 case 0x5a: /* FADDP */
10486 gen_helper_vfp_addd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10487 break;
10488 case 0x5e: /* FMAXP */
10489 gen_helper_vfp_maxd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10490 break;
10491 case 0x78: /* FMINNMP */
10492 gen_helper_vfp_minnumd(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10493 break;
10494 case 0x7e: /* FMINP */
10495 gen_helper_vfp_mind(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10496 break;
10497 default:
10498 g_assert_not_reached();
10499 }
10500
10501 tcg_temp_free_i64(tcg_op1);
10502 tcg_temp_free_i64(tcg_op2);
10503 }
10504
10505 for (pass = 0; pass < 2; pass++) {
10506 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
10507 tcg_temp_free_i64(tcg_res[pass]);
10508 }
10509 } else {
10510 int maxpass = is_q ? 4 : 2;
10511 TCGv_i32 tcg_res[4];
10512
10513 for (pass = 0; pass < maxpass; pass++) {
10514 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
10515 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
10516 NeonGenTwoOpFn *genfn = NULL;
10517 int passreg = pass < (maxpass / 2) ? rn : rm;
10518 int passelt = (is_q && (pass & 1)) ? 2 : 0;
10519
10520 read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_32);
10521 read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_32);
10522 tcg_res[pass] = tcg_temp_new_i32();
10523
10524 switch (opcode) {
10525 case 0x17: /* ADDP */
10526 {
10527 static NeonGenTwoOpFn * const fns[3] = {
10528 gen_helper_neon_padd_u8,
10529 gen_helper_neon_padd_u16,
10530 tcg_gen_add_i32,
10531 };
10532 genfn = fns[size];
10533 break;
10534 }
10535 case 0x14: /* SMAXP, UMAXP */
10536 {
10537 static NeonGenTwoOpFn * const fns[3][2] = {
10538 { gen_helper_neon_pmax_s8, gen_helper_neon_pmax_u8 },
10539 { gen_helper_neon_pmax_s16, gen_helper_neon_pmax_u16 },
10540 { tcg_gen_smax_i32, tcg_gen_umax_i32 },
10541 };
10542 genfn = fns[size][u];
10543 break;
10544 }
10545 case 0x15: /* SMINP, UMINP */
10546 {
10547 static NeonGenTwoOpFn * const fns[3][2] = {
10548 { gen_helper_neon_pmin_s8, gen_helper_neon_pmin_u8 },
10549 { gen_helper_neon_pmin_s16, gen_helper_neon_pmin_u16 },
10550 { tcg_gen_smin_i32, tcg_gen_umin_i32 },
10551 };
10552 genfn = fns[size][u];
10553 break;
10554 }
10555 /* The FP operations are all on single floats (32 bit) */
10556 case 0x58: /* FMAXNMP */
10557 gen_helper_vfp_maxnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10558 break;
10559 case 0x5a: /* FADDP */
10560 gen_helper_vfp_adds(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10561 break;
10562 case 0x5e: /* FMAXP */
10563 gen_helper_vfp_maxs(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10564 break;
10565 case 0x78: /* FMINNMP */
10566 gen_helper_vfp_minnums(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10567 break;
10568 case 0x7e: /* FMINP */
10569 gen_helper_vfp_mins(tcg_res[pass], tcg_op1, tcg_op2, fpst);
10570 break;
10571 default:
10572 g_assert_not_reached();
10573 }
10574
10575 /* FP ops called directly, otherwise call now */
10576 if (genfn) {
10577 genfn(tcg_res[pass], tcg_op1, tcg_op2);
10578 }
10579
10580 tcg_temp_free_i32(tcg_op1);
10581 tcg_temp_free_i32(tcg_op2);
10582 }
10583
10584 for (pass = 0; pass < maxpass; pass++) {
10585 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
10586 tcg_temp_free_i32(tcg_res[pass]);
10587 }
10588 clear_vec_high(s, is_q, rd);
10589 }
10590
10591 if (fpst) {
10592 tcg_temp_free_ptr(fpst);
10593 }
10594 }
10595
10596 /* Floating point op subgroup of C3.6.16. */
10597 static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
10598 {
10599 /* For floating point ops, the U, size[1] and opcode bits
10600 * together indicate the operation. size[0] indicates single
10601 * or double.
10602 */
10603 int fpopcode = extract32(insn, 11, 5)
10604 | (extract32(insn, 23, 1) << 5)
10605 | (extract32(insn, 29, 1) << 6);
10606 int is_q = extract32(insn, 30, 1);
10607 int size = extract32(insn, 22, 1);
10608 int rm = extract32(insn, 16, 5);
10609 int rn = extract32(insn, 5, 5);
10610 int rd = extract32(insn, 0, 5);
10611
10612 int datasize = is_q ? 128 : 64;
10613 int esize = 32 << size;
10614 int elements = datasize / esize;
10615
10616 if (size == 1 && !is_q) {
10617 unallocated_encoding(s);
10618 return;
10619 }
10620
10621 switch (fpopcode) {
10622 case 0x58: /* FMAXNMP */
10623 case 0x5a: /* FADDP */
10624 case 0x5e: /* FMAXP */
10625 case 0x78: /* FMINNMP */
10626 case 0x7e: /* FMINP */
10627 if (size && !is_q) {
10628 unallocated_encoding(s);
10629 return;
10630 }
10631 handle_simd_3same_pair(s, is_q, 0, fpopcode, size ? MO_64 : MO_32,
10632 rn, rm, rd);
10633 return;
10634 case 0x1b: /* FMULX */
10635 case 0x1f: /* FRECPS */
10636 case 0x3f: /* FRSQRTS */
10637 case 0x5d: /* FACGE */
10638 case 0x7d: /* FACGT */
10639 case 0x19: /* FMLA */
10640 case 0x39: /* FMLS */
10641 case 0x18: /* FMAXNM */
10642 case 0x1a: /* FADD */
10643 case 0x1c: /* FCMEQ */
10644 case 0x1e: /* FMAX */
10645 case 0x38: /* FMINNM */
10646 case 0x3a: /* FSUB */
10647 case 0x3e: /* FMIN */
10648 case 0x5b: /* FMUL */
10649 case 0x5c: /* FCMGE */
10650 case 0x5f: /* FDIV */
10651 case 0x7a: /* FABD */
10652 case 0x7c: /* FCMGT */
10653 if (!fp_access_check(s)) {
10654 return;
10655 }
10656
10657 handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
10658 return;
10659 default:
10660 unallocated_encoding(s);
10661 return;
10662 }
10663 }
10664
10665 static void gen_mla8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
10666 {
10667 gen_helper_neon_mul_u8(a, a, b);
10668 gen_helper_neon_add_u8(d, d, a);
10669 }
10670
10671 static void gen_mla16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
10672 {
10673 gen_helper_neon_mul_u16(a, a, b);
10674 gen_helper_neon_add_u16(d, d, a);
10675 }
10676
10677 static void gen_mla32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
10678 {
10679 tcg_gen_mul_i32(a, a, b);
10680 tcg_gen_add_i32(d, d, a);
10681 }
10682
10683 static void gen_mla64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
10684 {
10685 tcg_gen_mul_i64(a, a, b);
10686 tcg_gen_add_i64(d, d, a);
10687 }
10688
10689 static void gen_mla_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
10690 {
10691 tcg_gen_mul_vec(vece, a, a, b);
10692 tcg_gen_add_vec(vece, d, d, a);
10693 }
10694
10695 static void gen_mls8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
10696 {
10697 gen_helper_neon_mul_u8(a, a, b);
10698 gen_helper_neon_sub_u8(d, d, a);
10699 }
10700
10701 static void gen_mls16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
10702 {
10703 gen_helper_neon_mul_u16(a, a, b);
10704 gen_helper_neon_sub_u16(d, d, a);
10705 }
10706
10707 static void gen_mls32_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
10708 {
10709 tcg_gen_mul_i32(a, a, b);
10710 tcg_gen_sub_i32(d, d, a);
10711 }
10712
10713 static void gen_mls64_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
10714 {
10715 tcg_gen_mul_i64(a, a, b);
10716 tcg_gen_sub_i64(d, d, a);
10717 }
10718
10719 static void gen_mls_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)
10720 {
10721 tcg_gen_mul_vec(vece, a, a, b);
10722 tcg_gen_sub_vec(vece, d, d, a);
10723 }
10724
10725 /* Integer op subgroup of C3.6.16. */
10726 static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
10727 {
10728 static const GVecGen3 cmtst_op[4] = {
10729 { .fni4 = gen_helper_neon_tst_u8,
10730 .fniv = gen_cmtst_vec,
10731 .vece = MO_8 },
10732 { .fni4 = gen_helper_neon_tst_u16,
10733 .fniv = gen_cmtst_vec,
10734 .vece = MO_16 },
10735 { .fni4 = gen_cmtst_i32,
10736 .fniv = gen_cmtst_vec,
10737 .vece = MO_32 },
10738 { .fni8 = gen_cmtst_i64,
10739 .fniv = gen_cmtst_vec,
10740 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
10741 .vece = MO_64 },
10742 };
10743 static const GVecGen3 mla_op[4] = {
10744 { .fni4 = gen_mla8_i32,
10745 .fniv = gen_mla_vec,
10746 .opc = INDEX_op_mul_vec,
10747 .load_dest = true,
10748 .vece = MO_8 },
10749 { .fni4 = gen_mla16_i32,
10750 .fniv = gen_mla_vec,
10751 .opc = INDEX_op_mul_vec,
10752 .load_dest = true,
10753 .vece = MO_16 },
10754 { .fni4 = gen_mla32_i32,
10755 .fniv = gen_mla_vec,
10756 .opc = INDEX_op_mul_vec,
10757 .load_dest = true,
10758 .vece = MO_32 },
10759 { .fni8 = gen_mla64_i64,
10760 .fniv = gen_mla_vec,
10761 .opc = INDEX_op_mul_vec,
10762 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
10763 .load_dest = true,
10764 .vece = MO_64 },
10765 };
10766 static const GVecGen3 mls_op[4] = {
10767 { .fni4 = gen_mls8_i32,
10768 .fniv = gen_mls_vec,
10769 .opc = INDEX_op_mul_vec,
10770 .load_dest = true,
10771 .vece = MO_8 },
10772 { .fni4 = gen_mls16_i32,
10773 .fniv = gen_mls_vec,
10774 .opc = INDEX_op_mul_vec,
10775 .load_dest = true,
10776 .vece = MO_16 },
10777 { .fni4 = gen_mls32_i32,
10778 .fniv = gen_mls_vec,
10779 .opc = INDEX_op_mul_vec,
10780 .load_dest = true,
10781 .vece = MO_32 },
10782 { .fni8 = gen_mls64_i64,
10783 .fniv = gen_mls_vec,
10784 .opc = INDEX_op_mul_vec,
10785 .prefer_i64 = TCG_TARGET_REG_BITS == 64,
10786 .load_dest = true,
10787 .vece = MO_64 },
10788 };
10789
10790 int is_q = extract32(insn, 30, 1);
10791 int u = extract32(insn, 29, 1);
10792 int size = extract32(insn, 22, 2);
10793 int opcode = extract32(insn, 11, 5);
10794 int rm = extract32(insn, 16, 5);
10795 int rn = extract32(insn, 5, 5);
10796 int rd = extract32(insn, 0, 5);
10797 int pass;
10798 TCGCond cond;
10799
10800 switch (opcode) {
10801 case 0x13: /* MUL, PMUL */
10802 if (u && size != 0) {
10803 unallocated_encoding(s);
10804 return;
10805 }
10806 /* fall through */
10807 case 0x0: /* SHADD, UHADD */
10808 case 0x2: /* SRHADD, URHADD */
10809 case 0x4: /* SHSUB, UHSUB */
10810 case 0xc: /* SMAX, UMAX */
10811 case 0xd: /* SMIN, UMIN */
10812 case 0xe: /* SABD, UABD */
10813 case 0xf: /* SABA, UABA */
10814 case 0x12: /* MLA, MLS */
10815 if (size == 3) {
10816 unallocated_encoding(s);
10817 return;
10818 }
10819 break;
10820 case 0x16: /* SQDMULH, SQRDMULH */
10821 if (size == 0 || size == 3) {
10822 unallocated_encoding(s);
10823 return;
10824 }
10825 break;
10826 default:
10827 if (size == 3 && !is_q) {
10828 unallocated_encoding(s);
10829 return;
10830 }
10831 break;
10832 }
10833
10834 if (!fp_access_check(s)) {
10835 return;
10836 }
10837
10838 switch (opcode) {
10839 case 0x10: /* ADD, SUB */
10840 if (u) {
10841 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size);
10842 } else {
10843 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size);
10844 }
10845 return;
10846 case 0x13: /* MUL, PMUL */
10847 if (!u) { /* MUL */
10848 gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size);
10849 return;
10850 }
10851 break;
10852 case 0x12: /* MLA, MLS */
10853 if (u) {
10854 gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]);
10855 } else {
10856 gen_gvec_op3(s, is_q, rd, rn, rm, &mla_op[size]);
10857 }
10858 return;
10859 case 0x11:
10860 if (!u) { /* CMTST */
10861 gen_gvec_op3(s, is_q, rd, rn, rm, &cmtst_op[size]);
10862 return;
10863 }
10864 /* else CMEQ */
10865 cond = TCG_COND_EQ;
10866 goto do_gvec_cmp;
10867 case 0x06: /* CMGT, CMHI */
10868 cond = u ? TCG_COND_GTU : TCG_COND_GT;
10869 goto do_gvec_cmp;
10870 case 0x07: /* CMGE, CMHS */
10871 cond = u ? TCG_COND_GEU : TCG_COND_GE;
10872 do_gvec_cmp:
10873 tcg_gen_gvec_cmp(cond, size, vec_full_reg_offset(s, rd),
10874 vec_full_reg_offset(s, rn),
10875 vec_full_reg_offset(s, rm),
10876 is_q ? 16 : 8, vec_full_reg_size(s));
10877 return;
10878 }
10879
10880 if (size == 3) {
10881 assert(is_q);
10882 for (pass = 0; pass < 2; pass++) {
10883 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
10884 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
10885 TCGv_i64 tcg_res = tcg_temp_new_i64();
10886
10887 read_vec_element(s, tcg_op1, rn, pass, MO_64);
10888 read_vec_element(s, tcg_op2, rm, pass, MO_64);
10889
10890 handle_3same_64(s, opcode, u, tcg_res, tcg_op1, tcg_op2);
10891
10892 write_vec_element(s, tcg_res, rd, pass, MO_64);
10893
10894 tcg_temp_free_i64(tcg_res);
10895 tcg_temp_free_i64(tcg_op1);
10896 tcg_temp_free_i64(tcg_op2);
10897 }
10898 } else {
10899 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
10900 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
10901 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
10902 TCGv_i32 tcg_res = tcg_temp_new_i32();
10903 NeonGenTwoOpFn *genfn = NULL;
10904 NeonGenTwoOpEnvFn *genenvfn = NULL;
10905
10906 read_vec_element_i32(s, tcg_op1, rn, pass, MO_32);
10907 read_vec_element_i32(s, tcg_op2, rm, pass, MO_32);
10908
10909 switch (opcode) {
10910 case 0x0: /* SHADD, UHADD */
10911 {
10912 static NeonGenTwoOpFn * const fns[3][2] = {
10913 { gen_helper_neon_hadd_s8, gen_helper_neon_hadd_u8 },
10914 { gen_helper_neon_hadd_s16, gen_helper_neon_hadd_u16 },
10915 { gen_helper_neon_hadd_s32, gen_helper_neon_hadd_u32 },
10916 };
10917 genfn = fns[size][u];
10918 break;
10919 }
10920 case 0x1: /* SQADD, UQADD */
10921 {
10922 static NeonGenTwoOpEnvFn * const fns[3][2] = {
10923 { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 },
10924 { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 },
10925 { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 },
10926 };
10927 genenvfn = fns[size][u];
10928 break;
10929 }
10930 case 0x2: /* SRHADD, URHADD */
10931 {
10932 static NeonGenTwoOpFn * const fns[3][2] = {
10933 { gen_helper_neon_rhadd_s8, gen_helper_neon_rhadd_u8 },
10934 { gen_helper_neon_rhadd_s16, gen_helper_neon_rhadd_u16 },
10935 { gen_helper_neon_rhadd_s32, gen_helper_neon_rhadd_u32 },
10936 };
10937 genfn = fns[size][u];
10938 break;
10939 }
10940 case 0x4: /* SHSUB, UHSUB */
10941 {
10942 static NeonGenTwoOpFn * const fns[3][2] = {
10943 { gen_helper_neon_hsub_s8, gen_helper_neon_hsub_u8 },
10944 { gen_helper_neon_hsub_s16, gen_helper_neon_hsub_u16 },
10945 { gen_helper_neon_hsub_s32, gen_helper_neon_hsub_u32 },
10946 };
10947 genfn = fns[size][u];
10948 break;
10949 }
10950 case 0x5: /* SQSUB, UQSUB */
10951 {
10952 static NeonGenTwoOpEnvFn * const fns[3][2] = {
10953 { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 },
10954 { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 },
10955 { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 },
10956 };
10957 genenvfn = fns[size][u];
10958 break;
10959 }
10960 case 0x8: /* SSHL, USHL */
10961 {
10962 static NeonGenTwoOpFn * const fns[3][2] = {
10963 { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 },
10964 { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 },
10965 { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 },
10966 };
10967 genfn = fns[size][u];
10968 break;
10969 }
10970 case 0x9: /* SQSHL, UQSHL */
10971 {
10972 static NeonGenTwoOpEnvFn * const fns[3][2] = {
10973 { gen_helper_neon_qshl_s8, gen_helper_neon_qshl_u8 },
10974 { gen_helper_neon_qshl_s16, gen_helper_neon_qshl_u16 },
10975 { gen_helper_neon_qshl_s32, gen_helper_neon_qshl_u32 },
10976 };
10977 genenvfn = fns[size][u];
10978 break;
10979 }
10980 case 0xa: /* SRSHL, URSHL */
10981 {
10982 static NeonGenTwoOpFn * const fns[3][2] = {
10983 { gen_helper_neon_rshl_s8, gen_helper_neon_rshl_u8 },
10984 { gen_helper_neon_rshl_s16, gen_helper_neon_rshl_u16 },
10985 { gen_helper_neon_rshl_s32, gen_helper_neon_rshl_u32 },
10986 };
10987 genfn = fns[size][u];
10988 break;
10989 }
10990 case 0xb: /* SQRSHL, UQRSHL */
10991 {
10992 static NeonGenTwoOpEnvFn * const fns[3][2] = {
10993 { gen_helper_neon_qrshl_s8, gen_helper_neon_qrshl_u8 },
10994 { gen_helper_neon_qrshl_s16, gen_helper_neon_qrshl_u16 },
10995 { gen_helper_neon_qrshl_s32, gen_helper_neon_qrshl_u32 },
10996 };
10997 genenvfn = fns[size][u];
10998 break;
10999 }
11000 case 0xc: /* SMAX, UMAX */
11001 {
11002 static NeonGenTwoOpFn * const fns[3][2] = {
11003 { gen_helper_neon_max_s8, gen_helper_neon_max_u8 },
11004 { gen_helper_neon_max_s16, gen_helper_neon_max_u16 },
11005 { tcg_gen_smax_i32, tcg_gen_umax_i32 },
11006 };
11007 genfn = fns[size][u];
11008 break;
11009 }
11010
11011 case 0xd: /* SMIN, UMIN */
11012 {
11013 static NeonGenTwoOpFn * const fns[3][2] = {
11014 { gen_helper_neon_min_s8, gen_helper_neon_min_u8 },
11015 { gen_helper_neon_min_s16, gen_helper_neon_min_u16 },
11016 { tcg_gen_smin_i32, tcg_gen_umin_i32 },
11017 };
11018 genfn = fns[size][u];
11019 break;
11020 }
11021 case 0xe: /* SABD, UABD */
11022 case 0xf: /* SABA, UABA */
11023 {
11024 static NeonGenTwoOpFn * const fns[3][2] = {
11025 { gen_helper_neon_abd_s8, gen_helper_neon_abd_u8 },
11026 { gen_helper_neon_abd_s16, gen_helper_neon_abd_u16 },
11027 { gen_helper_neon_abd_s32, gen_helper_neon_abd_u32 },
11028 };
11029 genfn = fns[size][u];
11030 break;
11031 }
11032 case 0x13: /* MUL, PMUL */
11033 assert(u); /* PMUL */
11034 assert(size == 0);
11035 genfn = gen_helper_neon_mul_p8;
11036 break;
11037 case 0x16: /* SQDMULH, SQRDMULH */
11038 {
11039 static NeonGenTwoOpEnvFn * const fns[2][2] = {
11040 { gen_helper_neon_qdmulh_s16, gen_helper_neon_qrdmulh_s16 },
11041 { gen_helper_neon_qdmulh_s32, gen_helper_neon_qrdmulh_s32 },
11042 };
11043 assert(size == 1 || size == 2);
11044 genenvfn = fns[size - 1][u];
11045 break;
11046 }
11047 default:
11048 g_assert_not_reached();
11049 }
11050
11051 if (genenvfn) {
11052 genenvfn(tcg_res, cpu_env, tcg_op1, tcg_op2);
11053 } else {
11054 genfn(tcg_res, tcg_op1, tcg_op2);
11055 }
11056
11057 if (opcode == 0xf) {
11058 /* SABA, UABA: accumulating ops */
11059 static NeonGenTwoOpFn * const fns[3] = {
11060 gen_helper_neon_add_u8,
11061 gen_helper_neon_add_u16,
11062 tcg_gen_add_i32,
11063 };
11064
11065 read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
11066 fns[size](tcg_res, tcg_op1, tcg_res);
11067 }
11068
11069 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
11070
11071 tcg_temp_free_i32(tcg_res);
11072 tcg_temp_free_i32(tcg_op1);
11073 tcg_temp_free_i32(tcg_op2);
11074 }
11075 }
11076 clear_vec_high(s, is_q, rd);
11077 }
11078
11079 /* AdvSIMD three same
11080 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11081 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11082 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11083 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11084 */
11085 static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
11086 {
11087 int opcode = extract32(insn, 11, 5);
11088
11089 switch (opcode) {
11090 case 0x3: /* logic ops */
11091 disas_simd_3same_logic(s, insn);
11092 break;
11093 case 0x17: /* ADDP */
11094 case 0x14: /* SMAXP, UMAXP */
11095 case 0x15: /* SMINP, UMINP */
11096 {
11097 /* Pairwise operations */
11098 int is_q = extract32(insn, 30, 1);
11099 int u = extract32(insn, 29, 1);
11100 int size = extract32(insn, 22, 2);
11101 int rm = extract32(insn, 16, 5);
11102 int rn = extract32(insn, 5, 5);
11103 int rd = extract32(insn, 0, 5);
11104 if (opcode == 0x17) {
11105 if (u || (size == 3 && !is_q)) {
11106 unallocated_encoding(s);
11107 return;
11108 }
11109 } else {
11110 if (size == 3) {
11111 unallocated_encoding(s);
11112 return;
11113 }
11114 }
11115 handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd);
11116 break;
11117 }
11118 case 0x18 ... 0x31:
11119 /* floating point ops, sz[1] and U are part of opcode */
11120 disas_simd_3same_float(s, insn);
11121 break;
11122 default:
11123 disas_simd_3same_int(s, insn);
11124 break;
11125 }
11126 }
11127
11128 /*
11129 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11130 *
11131 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11132 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11133 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11134 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11135 *
11136 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11137 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11138 *
11139 */
11140 static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
11141 {
11142 int opcode, fpopcode;
11143 int is_q, u, a, rm, rn, rd;
11144 int datasize, elements;
11145 int pass;
11146 TCGv_ptr fpst;
11147 bool pairwise = false;
11148
11149 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
11150 unallocated_encoding(s);
11151 return;
11152 }
11153
11154 if (!fp_access_check(s)) {
11155 return;
11156 }
11157
11158 /* For these floating point ops, the U, a and opcode bits
11159 * together indicate the operation.
11160 */
11161 opcode = extract32(insn, 11, 3);
11162 u = extract32(insn, 29, 1);
11163 a = extract32(insn, 23, 1);
11164 is_q = extract32(insn, 30, 1);
11165 rm = extract32(insn, 16, 5);
11166 rn = extract32(insn, 5, 5);
11167 rd = extract32(insn, 0, 5);
11168
11169 fpopcode = opcode | (a << 3) | (u << 4);
11170 datasize = is_q ? 128 : 64;
11171 elements = datasize / 16;
11172
11173 switch (fpopcode) {
11174 case 0x10: /* FMAXNMP */
11175 case 0x12: /* FADDP */
11176 case 0x16: /* FMAXP */
11177 case 0x18: /* FMINNMP */
11178 case 0x1e: /* FMINP */
11179 pairwise = true;
11180 break;
11181 }
11182
11183 fpst = get_fpstatus_ptr(true);
11184
11185 if (pairwise) {
11186 int maxpass = is_q ? 8 : 4;
11187 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
11188 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
11189 TCGv_i32 tcg_res[8];
11190
11191 for (pass = 0; pass < maxpass; pass++) {
11192 int passreg = pass < (maxpass / 2) ? rn : rm;
11193 int passelt = (pass << 1) & (maxpass - 1);
11194
11195 read_vec_element_i32(s, tcg_op1, passreg, passelt, MO_16);
11196 read_vec_element_i32(s, tcg_op2, passreg, passelt + 1, MO_16);
11197 tcg_res[pass] = tcg_temp_new_i32();
11198
11199 switch (fpopcode) {
11200 case 0x10: /* FMAXNMP */
11201 gen_helper_advsimd_maxnumh(tcg_res[pass], tcg_op1, tcg_op2,
11202 fpst);
11203 break;
11204 case 0x12: /* FADDP */
11205 gen_helper_advsimd_addh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11206 break;
11207 case 0x16: /* FMAXP */
11208 gen_helper_advsimd_maxh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11209 break;
11210 case 0x18: /* FMINNMP */
11211 gen_helper_advsimd_minnumh(tcg_res[pass], tcg_op1, tcg_op2,
11212 fpst);
11213 break;
11214 case 0x1e: /* FMINP */
11215 gen_helper_advsimd_minh(tcg_res[pass], tcg_op1, tcg_op2, fpst);
11216 break;
11217 default:
11218 g_assert_not_reached();
11219 }
11220 }
11221
11222 for (pass = 0; pass < maxpass; pass++) {
11223 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_16);
11224 tcg_temp_free_i32(tcg_res[pass]);
11225 }
11226
11227 tcg_temp_free_i32(tcg_op1);
11228 tcg_temp_free_i32(tcg_op2);
11229
11230 } else {
11231 for (pass = 0; pass < elements; pass++) {
11232 TCGv_i32 tcg_op1 = tcg_temp_new_i32();
11233 TCGv_i32 tcg_op2 = tcg_temp_new_i32();
11234 TCGv_i32 tcg_res = tcg_temp_new_i32();
11235
11236 read_vec_element_i32(s, tcg_op1, rn, pass, MO_16);
11237 read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
11238
11239 switch (fpopcode) {
11240 case 0x0: /* FMAXNM */
11241 gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
11242 break;
11243 case 0x1: /* FMLA */
11244 read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
11245 gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
11246 fpst);
11247 break;
11248 case 0x2: /* FADD */
11249 gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
11250 break;
11251 case 0x3: /* FMULX */
11252 gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst);
11253 break;
11254 case 0x4: /* FCMEQ */
11255 gen_helper_advsimd_ceq_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11256 break;
11257 case 0x6: /* FMAX */
11258 gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
11259 break;
11260 case 0x7: /* FRECPS */
11261 gen_helper_recpsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11262 break;
11263 case 0x8: /* FMINNM */
11264 gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
11265 break;
11266 case 0x9: /* FMLS */
11267 /* As usual for ARM, separate negation for fused multiply-add */
11268 tcg_gen_xori_i32(tcg_op1, tcg_op1, 0x8000);
11269 read_vec_element_i32(s, tcg_res, rd, pass, MO_16);
11270 gen_helper_advsimd_muladdh(tcg_res, tcg_op1, tcg_op2, tcg_res,
11271 fpst);
11272 break;
11273 case 0xa: /* FSUB */
11274 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
11275 break;
11276 case 0xe: /* FMIN */
11277 gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
11278 break;
11279 case 0xf: /* FRSQRTS */
11280 gen_helper_rsqrtsf_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11281 break;
11282 case 0x13: /* FMUL */
11283 gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
11284 break;
11285 case 0x14: /* FCMGE */
11286 gen_helper_advsimd_cge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11287 break;
11288 case 0x15: /* FACGE */
11289 gen_helper_advsimd_acge_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11290 break;
11291 case 0x17: /* FDIV */
11292 gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
11293 break;
11294 case 0x1a: /* FABD */
11295 gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
11296 tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff);
11297 break;
11298 case 0x1c: /* FCMGT */
11299 gen_helper_advsimd_cgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11300 break;
11301 case 0x1d: /* FACGT */
11302 gen_helper_advsimd_acgt_f16(tcg_res, tcg_op1, tcg_op2, fpst);
11303 break;
11304 default:
11305 fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
11306 __func__, insn, fpopcode, s->pc);
11307 g_assert_not_reached();
11308 }
11309
11310 write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
11311 tcg_temp_free_i32(tcg_res);
11312 tcg_temp_free_i32(tcg_op1);
11313 tcg_temp_free_i32(tcg_op2);
11314 }
11315 }
11316
11317 tcg_temp_free_ptr(fpst);
11318
11319 clear_vec_high(s, is_q, rd);
11320 }
11321
11322 /* AdvSIMD three same extra
11323 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11324 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11325 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11326 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11327 */
11328 static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
11329 {
11330 int rd = extract32(insn, 0, 5);
11331 int rn = extract32(insn, 5, 5);
11332 int opcode = extract32(insn, 11, 4);
11333 int rm = extract32(insn, 16, 5);
11334 int size = extract32(insn, 22, 2);
11335 bool u = extract32(insn, 29, 1);
11336 bool is_q = extract32(insn, 30, 1);
11337 int feature, rot;
11338
11339 switch (u * 16 + opcode) {
11340 case 0x10: /* SQRDMLAH (vector) */
11341 case 0x11: /* SQRDMLSH (vector) */
11342 if (size != 1 && size != 2) {
11343 unallocated_encoding(s);
11344 return;
11345 }
11346 feature = ARM_FEATURE_V8_RDM;
11347 break;
11348 case 0x02: /* SDOT (vector) */
11349 case 0x12: /* UDOT (vector) */
11350 if (size != MO_32) {
11351 unallocated_encoding(s);
11352 return;
11353 }
11354 feature = ARM_FEATURE_V8_DOTPROD;
11355 break;
11356 case 0x8: /* FCMLA, #0 */
11357 case 0x9: /* FCMLA, #90 */
11358 case 0xa: /* FCMLA, #180 */
11359 case 0xb: /* FCMLA, #270 */
11360 case 0xc: /* FCADD, #90 */
11361 case 0xe: /* FCADD, #270 */
11362 if (size == 0
11363 || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16))
11364 || (size == 3 && !is_q)) {
11365 unallocated_encoding(s);
11366 return;
11367 }
11368 feature = ARM_FEATURE_V8_FCMA;
11369 break;
11370 default:
11371 unallocated_encoding(s);
11372 return;
11373 }
11374 if (!arm_dc_feature(s, feature)) {
11375 unallocated_encoding(s);
11376 return;
11377 }
11378 if (!fp_access_check(s)) {
11379 return;
11380 }
11381
11382 switch (opcode) {
11383 case 0x0: /* SQRDMLAH (vector) */
11384 switch (size) {
11385 case 1:
11386 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16);
11387 break;
11388 case 2:
11389 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32);
11390 break;
11391 default:
11392 g_assert_not_reached();
11393 }
11394 return;
11395
11396 case 0x1: /* SQRDMLSH (vector) */
11397 switch (size) {
11398 case 1:
11399 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16);
11400 break;
11401 case 2:
11402 gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32);
11403 break;
11404 default:
11405 g_assert_not_reached();
11406 }
11407 return;
11408
11409 case 0x2: /* SDOT / UDOT */
11410 gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0,
11411 u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b);
11412 return;
11413
11414 case 0x8: /* FCMLA, #0 */
11415 case 0x9: /* FCMLA, #90 */
11416 case 0xa: /* FCMLA, #180 */
11417 case 0xb: /* FCMLA, #270 */
11418 rot = extract32(opcode, 0, 2);
11419 switch (size) {
11420 case 1:
11421 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, true, rot,
11422 gen_helper_gvec_fcmlah);
11423 break;
11424 case 2:
11425 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
11426 gen_helper_gvec_fcmlas);
11427 break;
11428 case 3:
11429 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, rot,
11430 gen_helper_gvec_fcmlad);
11431 break;
11432 default:
11433 g_assert_not_reached();
11434 }
11435 return;
11436
11437 case 0xc: /* FCADD, #90 */
11438 case 0xe: /* FCADD, #270 */
11439 rot = extract32(opcode, 1, 1);
11440 switch (size) {
11441 case 1:
11442 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
11443 gen_helper_gvec_fcaddh);
11444 break;
11445 case 2:
11446 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
11447 gen_helper_gvec_fcadds);
11448 break;
11449 case 3:
11450 gen_gvec_op3_fpst(s, is_q, rd, rn, rm, size == 1, rot,
11451 gen_helper_gvec_fcaddd);
11452 break;
11453 default:
11454 g_assert_not_reached();
11455 }
11456 return;
11457
11458 default:
11459 g_assert_not_reached();
11460 }
11461 }
11462
11463 static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
11464 int size, int rn, int rd)
11465 {
11466 /* Handle 2-reg-misc ops which are widening (so each size element
11467 * in the source becomes a 2*size element in the destination.
11468 * The only instruction like this is FCVTL.
11469 */
11470 int pass;
11471
11472 if (size == 3) {
11473 /* 32 -> 64 bit fp conversion */
11474 TCGv_i64 tcg_res[2];
11475 int srcelt = is_q ? 2 : 0;
11476
11477 for (pass = 0; pass < 2; pass++) {
11478 TCGv_i32 tcg_op = tcg_temp_new_i32();
11479 tcg_res[pass] = tcg_temp_new_i64();
11480
11481 read_vec_element_i32(s, tcg_op, rn, srcelt + pass, MO_32);
11482 gen_helper_vfp_fcvtds(tcg_res[pass], tcg_op, cpu_env);
11483 tcg_temp_free_i32(tcg_op);
11484 }
11485 for (pass = 0; pass < 2; pass++) {
11486 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
11487 tcg_temp_free_i64(tcg_res[pass]);
11488 }
11489 } else {
11490 /* 16 -> 32 bit fp conversion */
11491 int srcelt = is_q ? 4 : 0;
11492 TCGv_i32 tcg_res[4];
11493 TCGv_ptr fpst = get_fpstatus_ptr(false);
11494 TCGv_i32 ahp = get_ahp_flag();
11495
11496 for (pass = 0; pass < 4; pass++) {
11497 tcg_res[pass] = tcg_temp_new_i32();
11498
11499 read_vec_element_i32(s, tcg_res[pass], rn, srcelt + pass, MO_16);
11500 gen_helper_vfp_fcvt_f16_to_f32(tcg_res[pass], tcg_res[pass],
11501 fpst, ahp);
11502 }
11503 for (pass = 0; pass < 4; pass++) {
11504 write_vec_element_i32(s, tcg_res[pass], rd, pass, MO_32);
11505 tcg_temp_free_i32(tcg_res[pass]);
11506 }
11507
11508 tcg_temp_free_ptr(fpst);
11509 tcg_temp_free_i32(ahp);
11510 }
11511 }
11512
11513 static void handle_rev(DisasContext *s, int opcode, bool u,
11514 bool is_q, int size, int rn, int rd)
11515 {
11516 int op = (opcode << 1) | u;
11517 int opsz = op + size;
11518 int grp_size = 3 - opsz;
11519 int dsize = is_q ? 128 : 64;
11520 int i;
11521
11522 if (opsz >= 3) {
11523 unallocated_encoding(s);
11524 return;
11525 }
11526
11527 if (!fp_access_check(s)) {
11528 return;
11529 }
11530
11531 if (size == 0) {
11532 /* Special case bytes, use bswap op on each group of elements */
11533 int groups = dsize / (8 << grp_size);
11534
11535 for (i = 0; i < groups; i++) {
11536 TCGv_i64 tcg_tmp = tcg_temp_new_i64();
11537
11538 read_vec_element(s, tcg_tmp, rn, i, grp_size);
11539 switch (grp_size) {
11540 case MO_16:
11541 tcg_gen_bswap16_i64(tcg_tmp, tcg_tmp);
11542 break;
11543 case MO_32:
11544 tcg_gen_bswap32_i64(tcg_tmp, tcg_tmp);
11545 break;
11546 case MO_64:
11547 tcg_gen_bswap64_i64(tcg_tmp, tcg_tmp);
11548 break;
11549 default:
11550 g_assert_not_reached();
11551 }
11552 write_vec_element(s, tcg_tmp, rd, i, grp_size);
11553 tcg_temp_free_i64(tcg_tmp);
11554 }
11555 clear_vec_high(s, is_q, rd);
11556 } else {
11557 int revmask = (1 << grp_size) - 1;
11558 int esize = 8 << size;
11559 int elements = dsize / esize;
11560 TCGv_i64 tcg_rn = tcg_temp_new_i64();
11561 TCGv_i64 tcg_rd = tcg_const_i64(0);
11562 TCGv_i64 tcg_rd_hi = tcg_const_i64(0);
11563
11564 for (i = 0; i < elements; i++) {
11565 int e_rev = (i & 0xf) ^ revmask;
11566 int off = e_rev * esize;
11567 read_vec_element(s, tcg_rn, rn, i, size);
11568 if (off >= 64) {
11569 tcg_gen_deposit_i64(tcg_rd_hi, tcg_rd_hi,
11570 tcg_rn, off - 64, esize);
11571 } else {
11572 tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_rn, off, esize);
11573 }
11574 }
11575 write_vec_element(s, tcg_rd, rd, 0, MO_64);
11576 write_vec_element(s, tcg_rd_hi, rd, 1, MO_64);
11577
11578 tcg_temp_free_i64(tcg_rd_hi);
11579 tcg_temp_free_i64(tcg_rd);
11580 tcg_temp_free_i64(tcg_rn);
11581 }
11582 }
11583
11584 static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
11585 bool is_q, int size, int rn, int rd)
11586 {
11587 /* Implement the pairwise operations from 2-misc:
11588 * SADDLP, UADDLP, SADALP, UADALP.
11589 * These all add pairs of elements in the input to produce a
11590 * double-width result element in the output (possibly accumulating).
11591 */
11592 bool accum = (opcode == 0x6);
11593 int maxpass = is_q ? 2 : 1;
11594 int pass;
11595 TCGv_i64 tcg_res[2];
11596
11597 if (size == 2) {
11598 /* 32 + 32 -> 64 op */
11599 TCGMemOp memop = size + (u ? 0 : MO_SIGN);
11600
11601 for (pass = 0; pass < maxpass; pass++) {
11602 TCGv_i64 tcg_op1 = tcg_temp_new_i64();
11603 TCGv_i64 tcg_op2 = tcg_temp_new_i64();
11604
11605 tcg_res[pass] = tcg_temp_new_i64();
11606
11607 read_vec_element(s, tcg_op1, rn, pass * 2, memop);
11608 read_vec_element(s, tcg_op2, rn, pass * 2 + 1, memop);
11609 tcg_gen_add_i64(tcg_res[pass], tcg_op1, tcg_op2);
11610 if (accum) {
11611 read_vec_element(s, tcg_op1, rd, pass, MO_64);
11612 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
11613 }
11614
11615 tcg_temp_free_i64(tcg_op1);
11616 tcg_temp_free_i64(tcg_op2);
11617 }
11618 } else {
11619 for (pass = 0; pass < maxpass; pass++) {
11620 TCGv_i64 tcg_op = tcg_temp_new_i64();
11621 NeonGenOneOpFn *genfn;
11622 static NeonGenOneOpFn * const fns[2][2] = {
11623 { gen_helper_neon_addlp_s8, gen_helper_neon_addlp_u8 },
11624 { gen_helper_neon_addlp_s16, gen_helper_neon_addlp_u16 },
11625 };
11626
11627 genfn = fns[size][u];
11628
11629 tcg_res[pass] = tcg_temp_new_i64();
11630
11631 read_vec_element(s, tcg_op, rn, pass, MO_64);
11632 genfn(tcg_res[pass], tcg_op);
11633
11634 if (accum) {
11635 read_vec_element(s, tcg_op, rd, pass, MO_64);
11636 if (size == 0) {
11637 gen_helper_neon_addl_u16(tcg_res[pass],
11638 tcg_res[pass], tcg_op);
11639 } else {
11640 gen_helper_neon_addl_u32(tcg_res[pass],
11641 tcg_res[pass], tcg_op);
11642 }
11643 }
11644 tcg_temp_free_i64(tcg_op);
11645 }
11646 }
11647 if (!is_q) {
11648 tcg_res[1] = tcg_const_i64(0);
11649 }
11650 for (pass = 0; pass < 2; pass++) {
11651 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
11652 tcg_temp_free_i64(tcg_res[pass]);
11653 }
11654 }
11655
11656 static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
11657 {
11658 /* Implement SHLL and SHLL2 */
11659 int pass;
11660 int part = is_q ? 2 : 0;
11661 TCGv_i64 tcg_res[2];
11662
11663 for (pass = 0; pass < 2; pass++) {
11664 static NeonGenWidenFn * const widenfns[3] = {
11665 gen_helper_neon_widen_u8,
11666 gen_helper_neon_widen_u16,
11667 tcg_gen_extu_i32_i64,
11668 };
11669 NeonGenWidenFn *widenfn = widenfns[size];
11670 TCGv_i32 tcg_op = tcg_temp_new_i32();
11671
11672 read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
11673 tcg_res[pass] = tcg_temp_new_i64();
11674 widenfn(tcg_res[pass], tcg_op);
11675 tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
11676
11677 tcg_temp_free_i32(tcg_op);
11678 }
11679
11680 for (pass = 0; pass < 2; pass++) {
11681 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
11682 tcg_temp_free_i64(tcg_res[pass]);
11683 }
11684 }
11685
11686 /* AdvSIMD two reg misc
11687 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11688 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11689 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11690 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11691 */
11692 static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
11693 {
11694 int size = extract32(insn, 22, 2);
11695 int opcode = extract32(insn, 12, 5);
11696 bool u = extract32(insn, 29, 1);
11697 bool is_q = extract32(insn, 30, 1);
11698 int rn = extract32(insn, 5, 5);
11699 int rd = extract32(insn, 0, 5);
11700 bool need_fpstatus = false;
11701 bool need_rmode = false;
11702 int rmode = -1;
11703 TCGv_i32 tcg_rmode;
11704 TCGv_ptr tcg_fpstatus;
11705
11706 switch (opcode) {
11707 case 0x0: /* REV64, REV32 */
11708 case 0x1: /* REV16 */
11709 handle_rev(s, opcode, u, is_q, size, rn, rd);
11710 return;
11711 case 0x5: /* CNT, NOT, RBIT */
11712 if (u && size == 0) {
11713 /* NOT */
11714 break;
11715 } else if (u && size == 1) {
11716 /* RBIT */
11717 break;
11718 } else if (!u && size == 0) {
11719 /* CNT */
11720 break;
11721 }
11722 unallocated_encoding(s);
11723 return;
11724 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11725 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11726 if (size == 3) {
11727 unallocated_encoding(s);
11728 return;
11729 }
11730 if (!fp_access_check(s)) {
11731 return;
11732 }
11733
11734 handle_2misc_narrow(s, false, opcode, u, is_q, size, rn, rd);
11735 return;
11736 case 0x4: /* CLS, CLZ */
11737 if (size == 3) {
11738 unallocated_encoding(s);
11739 return;
11740 }
11741 break;
11742 case 0x2: /* SADDLP, UADDLP */
11743 case 0x6: /* SADALP, UADALP */
11744 if (size == 3) {
11745 unallocated_encoding(s);
11746 return;
11747 }
11748 if (!fp_access_check(s)) {
11749 return;
11750 }
11751 handle_2misc_pairwise(s, opcode, u, is_q, size, rn, rd);
11752 return;
11753 case 0x13: /* SHLL, SHLL2 */
11754 if (u == 0 || size == 3) {
11755 unallocated_encoding(s);
11756 return;
11757 }
11758 if (!fp_access_check(s)) {
11759 return;
11760 }
11761 handle_shll(s, is_q, size, rn, rd);
11762 return;
11763 case 0xa: /* CMLT */
11764 if (u == 1) {
11765 unallocated_encoding(s);
11766 return;
11767 }
11768 /* fall through */
11769 case 0x8: /* CMGT, CMGE */
11770 case 0x9: /* CMEQ, CMLE */
11771 case 0xb: /* ABS, NEG */
11772 if (size == 3 && !is_q) {
11773 unallocated_encoding(s);
11774 return;
11775 }
11776 break;
11777 case 0x3: /* SUQADD, USQADD */
11778 if (size == 3 && !is_q) {
11779 unallocated_encoding(s);
11780 return;
11781 }
11782 if (!fp_access_check(s)) {
11783 return;
11784 }
11785 handle_2misc_satacc(s, false, u, is_q, size, rn, rd);
11786 return;
11787 case 0x7: /* SQABS, SQNEG */
11788 if (size == 3 && !is_q) {
11789 unallocated_encoding(s);
11790 return;
11791 }
11792 break;
11793 case 0xc ... 0xf:
11794 case 0x16 ... 0x1d:
11795 case 0x1f:
11796 {
11797 /* Floating point: U, size[1] and opcode indicate operation;
11798 * size[0] indicates single or double precision.
11799 */
11800 int is_double = extract32(size, 0, 1);
11801 opcode |= (extract32(size, 1, 1) << 5) | (u << 6);
11802 size = is_double ? 3 : 2;
11803 switch (opcode) {
11804 case 0x2f: /* FABS */
11805 case 0x6f: /* FNEG */
11806 if (size == 3 && !is_q) {
11807 unallocated_encoding(s);
11808 return;
11809 }
11810 break;
11811 case 0x1d: /* SCVTF */
11812 case 0x5d: /* UCVTF */
11813 {
11814 bool is_signed = (opcode == 0x1d) ? true : false;
11815 int elements = is_double ? 2 : is_q ? 4 : 2;
11816 if (is_double && !is_q) {
11817 unallocated_encoding(s);
11818 return;
11819 }
11820 if (!fp_access_check(s)) {
11821 return;
11822 }
11823 handle_simd_intfp_conv(s, rd, rn, elements, is_signed, 0, size);
11824 return;
11825 }
11826 case 0x2c: /* FCMGT (zero) */
11827 case 0x2d: /* FCMEQ (zero) */
11828 case 0x2e: /* FCMLT (zero) */
11829 case 0x6c: /* FCMGE (zero) */
11830 case 0x6d: /* FCMLE (zero) */
11831 if (size == 3 && !is_q) {
11832 unallocated_encoding(s);
11833 return;
11834 }
11835 handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
11836 return;
11837 case 0x7f: /* FSQRT */
11838 if (size == 3 && !is_q) {
11839 unallocated_encoding(s);
11840 return;
11841 }
11842 break;
11843 case 0x1a: /* FCVTNS */
11844 case 0x1b: /* FCVTMS */
11845 case 0x3a: /* FCVTPS */
11846 case 0x3b: /* FCVTZS */
11847 case 0x5a: /* FCVTNU */
11848 case 0x5b: /* FCVTMU */
11849 case 0x7a: /* FCVTPU */
11850 case 0x7b: /* FCVTZU */
11851 need_fpstatus = true;
11852 need_rmode = true;
11853 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
11854 if (size == 3 && !is_q) {
11855 unallocated_encoding(s);
11856 return;
11857 }
11858 break;
11859 case 0x5c: /* FCVTAU */
11860 case 0x1c: /* FCVTAS */
11861 need_fpstatus = true;
11862 need_rmode = true;
11863 rmode = FPROUNDING_TIEAWAY;
11864 if (size == 3 && !is_q) {
11865 unallocated_encoding(s);
11866 return;
11867 }
11868 break;
11869 case 0x3c: /* URECPE */
11870 if (size == 3) {
11871 unallocated_encoding(s);
11872 return;
11873 }
11874 /* fall through */
11875 case 0x3d: /* FRECPE */
11876 case 0x7d: /* FRSQRTE */
11877 if (size == 3 && !is_q) {
11878 unallocated_encoding(s);
11879 return;
11880 }
11881 if (!fp_access_check(s)) {
11882 return;
11883 }
11884 handle_2misc_reciprocal(s, opcode, false, u, is_q, size, rn, rd);
11885 return;
11886 case 0x56: /* FCVTXN, FCVTXN2 */
11887 if (size == 2) {
11888 unallocated_encoding(s);
11889 return;
11890 }
11891 /* fall through */
11892 case 0x16: /* FCVTN, FCVTN2 */
11893 /* handle_2misc_narrow does a 2*size -> size operation, but these
11894 * instructions encode the source size rather than dest size.
11895 */
11896 if (!fp_access_check(s)) {
11897 return;
11898 }
11899 handle_2misc_narrow(s, false, opcode, 0, is_q, size - 1, rn, rd);
11900 return;
11901 case 0x17: /* FCVTL, FCVTL2 */
11902 if (!fp_access_check(s)) {
11903 return;
11904 }
11905 handle_2misc_widening(s, opcode, is_q, size, rn, rd);
11906 return;
11907 case 0x18: /* FRINTN */
11908 case 0x19: /* FRINTM */
11909 case 0x38: /* FRINTP */
11910 case 0x39: /* FRINTZ */
11911 need_rmode = true;
11912 rmode = extract32(opcode, 5, 1) | (extract32(opcode, 0, 1) << 1);
11913 /* fall through */
11914 case 0x59: /* FRINTX */
11915 case 0x79: /* FRINTI */
11916 need_fpstatus = true;
11917 if (size == 3 && !is_q) {
11918 unallocated_encoding(s);
11919 return;
11920 }
11921 break;
11922 case 0x58: /* FRINTA */
11923 need_rmode = true;
11924 rmode = FPROUNDING_TIEAWAY;
11925 need_fpstatus = true;
11926 if (size == 3 && !is_q) {
11927 unallocated_encoding(s);
11928 return;
11929 }
11930 break;
11931 case 0x7c: /* URSQRTE */
11932 if (size == 3) {
11933 unallocated_encoding(s);
11934 return;
11935 }
11936 need_fpstatus = true;
11937 break;
11938 default:
11939 unallocated_encoding(s);
11940 return;
11941 }
11942 break;
11943 }
11944 default:
11945 unallocated_encoding(s);
11946 return;
11947 }
11948
11949 if (!fp_access_check(s)) {
11950 return;
11951 }
11952
11953 if (need_fpstatus || need_rmode) {
11954 tcg_fpstatus = get_fpstatus_ptr(false);
11955 } else {
11956 tcg_fpstatus = NULL;
11957 }
11958 if (need_rmode) {
11959 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
11960 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
11961 } else {
11962 tcg_rmode = NULL;
11963 }
11964
11965 switch (opcode) {
11966 case 0x5:
11967 if (u && size == 0) { /* NOT */
11968 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_not, 0);
11969 return;
11970 }
11971 break;
11972 case 0xb:
11973 if (u) { /* NEG */
11974 gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size);
11975 return;
11976 }
11977 break;
11978 }
11979
11980 if (size == 3) {
11981 /* All 64-bit element operations can be shared with scalar 2misc */
11982 int pass;
11983
11984 /* Coverity claims (size == 3 && !is_q) has been eliminated
11985 * from all paths leading to here.
11986 */
11987 tcg_debug_assert(is_q);
11988 for (pass = 0; pass < 2; pass++) {
11989 TCGv_i64 tcg_op = tcg_temp_new_i64();
11990 TCGv_i64 tcg_res = tcg_temp_new_i64();
11991
11992 read_vec_element(s, tcg_op, rn, pass, MO_64);
11993
11994 handle_2misc_64(s, opcode, u, tcg_res, tcg_op,
11995 tcg_rmode, tcg_fpstatus);
11996
11997 write_vec_element(s, tcg_res, rd, pass, MO_64);
11998
11999 tcg_temp_free_i64(tcg_res);
12000 tcg_temp_free_i64(tcg_op);
12001 }
12002 } else {
12003 int pass;
12004
12005 for (pass = 0; pass < (is_q ? 4 : 2); pass++) {
12006 TCGv_i32 tcg_op = tcg_temp_new_i32();
12007 TCGv_i32 tcg_res = tcg_temp_new_i32();
12008 TCGCond cond;
12009
12010 read_vec_element_i32(s, tcg_op, rn, pass, MO_32);
12011
12012 if (size == 2) {
12013 /* Special cases for 32 bit elements */
12014 switch (opcode) {
12015 case 0xa: /* CMLT */
12016 /* 32 bit integer comparison against zero, result is
12017 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12018 * and inverting.
12019 */
12020 cond = TCG_COND_LT;
12021 do_cmop:
12022 tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0);
12023 tcg_gen_neg_i32(tcg_res, tcg_res);
12024 break;
12025 case 0x8: /* CMGT, CMGE */
12026 cond = u ? TCG_COND_GE : TCG_COND_GT;
12027 goto do_cmop;
12028 case 0x9: /* CMEQ, CMLE */
12029 cond = u ? TCG_COND_LE : TCG_COND_EQ;
12030 goto do_cmop;
12031 case 0x4: /* CLS */
12032 if (u) {
12033 tcg_gen_clzi_i32(tcg_res, tcg_op, 32);
12034 } else {
12035 tcg_gen_clrsb_i32(tcg_res, tcg_op);
12036 }
12037 break;
12038 case 0x7: /* SQABS, SQNEG */
12039 if (u) {
12040 gen_helper_neon_qneg_s32(tcg_res, cpu_env, tcg_op);
12041 } else {
12042 gen_helper_neon_qabs_s32(tcg_res, cpu_env, tcg_op);
12043 }
12044 break;
12045 case 0xb: /* ABS, NEG */
12046 if (u) {
12047 tcg_gen_neg_i32(tcg_res, tcg_op);
12048 } else {
12049 TCGv_i32 tcg_zero = tcg_const_i32(0);
12050 tcg_gen_neg_i32(tcg_res, tcg_op);
12051 tcg_gen_movcond_i32(TCG_COND_GT, tcg_res, tcg_op,
12052 tcg_zero, tcg_op, tcg_res);
12053 tcg_temp_free_i32(tcg_zero);
12054 }
12055 break;
12056 case 0x2f: /* FABS */
12057 gen_helper_vfp_abss(tcg_res, tcg_op);
12058 break;
12059 case 0x6f: /* FNEG */
12060 gen_helper_vfp_negs(tcg_res, tcg_op);
12061 break;
12062 case 0x7f: /* FSQRT */
12063 gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
12064 break;
12065 case 0x1a: /* FCVTNS */
12066 case 0x1b: /* FCVTMS */
12067 case 0x1c: /* FCVTAS */
12068 case 0x3a: /* FCVTPS */
12069 case 0x3b: /* FCVTZS */
12070 {
12071 TCGv_i32 tcg_shift = tcg_const_i32(0);
12072 gen_helper_vfp_tosls(tcg_res, tcg_op,
12073 tcg_shift, tcg_fpstatus);
12074 tcg_temp_free_i32(tcg_shift);
12075 break;
12076 }
12077 case 0x5a: /* FCVTNU */
12078 case 0x5b: /* FCVTMU */
12079 case 0x5c: /* FCVTAU */
12080 case 0x7a: /* FCVTPU */
12081 case 0x7b: /* FCVTZU */
12082 {
12083 TCGv_i32 tcg_shift = tcg_const_i32(0);
12084 gen_helper_vfp_touls(tcg_res, tcg_op,
12085 tcg_shift, tcg_fpstatus);
12086 tcg_temp_free_i32(tcg_shift);
12087 break;
12088 }
12089 case 0x18: /* FRINTN */
12090 case 0x19: /* FRINTM */
12091 case 0x38: /* FRINTP */
12092 case 0x39: /* FRINTZ */
12093 case 0x58: /* FRINTA */
12094 case 0x79: /* FRINTI */
12095 gen_helper_rints(tcg_res, tcg_op, tcg_fpstatus);
12096 break;
12097 case 0x59: /* FRINTX */
12098 gen_helper_rints_exact(tcg_res, tcg_op, tcg_fpstatus);
12099 break;
12100 case 0x7c: /* URSQRTE */
12101 gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus);
12102 break;
12103 default:
12104 g_assert_not_reached();
12105 }
12106 } else {
12107 /* Use helpers for 8 and 16 bit elements */
12108 switch (opcode) {
12109 case 0x5: /* CNT, RBIT */
12110 /* For these two insns size is part of the opcode specifier
12111 * (handled earlier); they always operate on byte elements.
12112 */
12113 if (u) {
12114 gen_helper_neon_rbit_u8(tcg_res, tcg_op);
12115 } else {
12116 gen_helper_neon_cnt_u8(tcg_res, tcg_op);
12117 }
12118 break;
12119 case 0x7: /* SQABS, SQNEG */
12120 {
12121 NeonGenOneOpEnvFn *genfn;
12122 static NeonGenOneOpEnvFn * const fns[2][2] = {
12123 { gen_helper_neon_qabs_s8, gen_helper_neon_qneg_s8 },
12124 { gen_helper_neon_qabs_s16, gen_helper_neon_qneg_s16 },
12125 };
12126 genfn = fns[size][u];
12127 genfn(tcg_res, cpu_env, tcg_op);
12128 break;
12129 }
12130 case 0x8: /* CMGT, CMGE */
12131 case 0x9: /* CMEQ, CMLE */
12132 case 0xa: /* CMLT */
12133 {
12134 static NeonGenTwoOpFn * const fns[3][2] = {
12135 { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 },
12136 { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 },
12137 { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 },
12138 };
12139 NeonGenTwoOpFn *genfn;
12140 int comp;
12141 bool reverse;
12142 TCGv_i32 tcg_zero = tcg_const_i32(0);
12143
12144 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12145 comp = (opcode - 0x8) * 2 + u;
12146 /* ...but LE, LT are implemented as reverse GE, GT */
12147 reverse = (comp > 2);
12148 if (reverse) {
12149 comp = 4 - comp;
12150 }
12151 genfn = fns[comp][size];
12152 if (reverse) {
12153 genfn(tcg_res, tcg_zero, tcg_op);
12154 } else {
12155 genfn(tcg_res, tcg_op, tcg_zero);
12156 }
12157 tcg_temp_free_i32(tcg_zero);
12158 break;
12159 }
12160 case 0xb: /* ABS, NEG */
12161 if (u) {
12162 TCGv_i32 tcg_zero = tcg_const_i32(0);
12163 if (size) {
12164 gen_helper_neon_sub_u16(tcg_res, tcg_zero, tcg_op);
12165 } else {
12166 gen_helper_neon_sub_u8(tcg_res, tcg_zero, tcg_op);
12167 }
12168 tcg_temp_free_i32(tcg_zero);
12169 } else {
12170 if (size) {
12171 gen_helper_neon_abs_s16(tcg_res, tcg_op);
12172 } else {
12173 gen_helper_neon_abs_s8(tcg_res, tcg_op);
12174 }
12175 }
12176 break;
12177 case 0x4: /* CLS, CLZ */
12178 if (u) {
12179 if (size == 0) {
12180 gen_helper_neon_clz_u8(tcg_res, tcg_op);
12181 } else {
12182 gen_helper_neon_clz_u16(tcg_res, tcg_op);
12183 }
12184 } else {
12185 if (size == 0) {
12186 gen_helper_neon_cls_s8(tcg_res, tcg_op);
12187 } else {
12188 gen_helper_neon_cls_s16(tcg_res, tcg_op);
12189 }
12190 }
12191 break;
12192 default:
12193 g_assert_not_reached();
12194 }
12195 }
12196
12197 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
12198
12199 tcg_temp_free_i32(tcg_res);
12200 tcg_temp_free_i32(tcg_op);
12201 }
12202 }
12203 clear_vec_high(s, is_q, rd);
12204
12205 if (need_rmode) {
12206 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
12207 tcg_temp_free_i32(tcg_rmode);
12208 }
12209 if (need_fpstatus) {
12210 tcg_temp_free_ptr(tcg_fpstatus);
12211 }
12212 }
12213
12214 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12215 *
12216 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12217 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12218 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12219 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12220 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12221 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12222 *
12223 * This actually covers two groups where scalar access is governed by
12224 * bit 28. A bunch of the instructions (float to integral) only exist
12225 * in the vector form and are un-allocated for the scalar decode. Also
12226 * in the scalar decode Q is always 1.
12227 */
12228 static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
12229 {
12230 int fpop, opcode, a, u;
12231 int rn, rd;
12232 bool is_q;
12233 bool is_scalar;
12234 bool only_in_vector = false;
12235
12236 int pass;
12237 TCGv_i32 tcg_rmode = NULL;
12238 TCGv_ptr tcg_fpstatus = NULL;
12239 bool need_rmode = false;
12240 bool need_fpst = true;
12241 int rmode;
12242
12243 if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
12244 unallocated_encoding(s);
12245 return;
12246 }
12247
12248 rd = extract32(insn, 0, 5);
12249 rn = extract32(insn, 5, 5);
12250
12251 a = extract32(insn, 23, 1);
12252 u = extract32(insn, 29, 1);
12253 is_scalar = extract32(insn, 28, 1);
12254 is_q = extract32(insn, 30, 1);
12255
12256 opcode = extract32(insn, 12, 5);
12257 fpop = deposit32(opcode, 5, 1, a);
12258 fpop = deposit32(fpop, 6, 1, u);
12259
12260 rd = extract32(insn, 0, 5);
12261 rn = extract32(insn, 5, 5);
12262
12263 switch (fpop) {
12264 case 0x1d: /* SCVTF */
12265 case 0x5d: /* UCVTF */
12266 {
12267 int elements;
12268
12269 if (is_scalar) {
12270 elements = 1;
12271 } else {
12272 elements = (is_q ? 8 : 4);
12273 }
12274
12275 if (!fp_access_check(s)) {
12276 return;
12277 }
12278 handle_simd_intfp_conv(s, rd, rn, elements, !u, 0, MO_16);
12279 return;
12280 }
12281 break;
12282 case 0x2c: /* FCMGT (zero) */
12283 case 0x2d: /* FCMEQ (zero) */
12284 case 0x2e: /* FCMLT (zero) */
12285 case 0x6c: /* FCMGE (zero) */
12286 case 0x6d: /* FCMLE (zero) */
12287 handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd);
12288 return;
12289 case 0x3d: /* FRECPE */
12290 case 0x3f: /* FRECPX */
12291 break;
12292 case 0x18: /* FRINTN */
12293 need_rmode = true;
12294 only_in_vector = true;
12295 rmode = FPROUNDING_TIEEVEN;
12296 break;
12297 case 0x19: /* FRINTM */
12298 need_rmode = true;
12299 only_in_vector = true;
12300 rmode = FPROUNDING_NEGINF;
12301 break;
12302 case 0x38: /* FRINTP */
12303 need_rmode = true;
12304 only_in_vector = true;
12305 rmode = FPROUNDING_POSINF;
12306 break;
12307 case 0x39: /* FRINTZ */
12308 need_rmode = true;
12309 only_in_vector = true;
12310 rmode = FPROUNDING_ZERO;
12311 break;
12312 case 0x58: /* FRINTA */
12313 need_rmode = true;
12314 only_in_vector = true;
12315 rmode = FPROUNDING_TIEAWAY;
12316 break;
12317 case 0x59: /* FRINTX */
12318 case 0x79: /* FRINTI */
12319 only_in_vector = true;
12320 /* current rounding mode */
12321 break;
12322 case 0x1a: /* FCVTNS */
12323 need_rmode = true;
12324 rmode = FPROUNDING_TIEEVEN;
12325 break;
12326 case 0x1b: /* FCVTMS */
12327 need_rmode = true;
12328 rmode = FPROUNDING_NEGINF;
12329 break;
12330 case 0x1c: /* FCVTAS */
12331 need_rmode = true;
12332 rmode = FPROUNDING_TIEAWAY;
12333 break;
12334 case 0x3a: /* FCVTPS */
12335 need_rmode = true;
12336 rmode = FPROUNDING_POSINF;
12337 break;
12338 case 0x3b: /* FCVTZS */
12339 need_rmode = true;
12340 rmode = FPROUNDING_ZERO;
12341 break;
12342 case 0x5a: /* FCVTNU */
12343 need_rmode = true;
12344 rmode = FPROUNDING_TIEEVEN;
12345 break;
12346 case 0x5b: /* FCVTMU */
12347 need_rmode = true;
12348 rmode = FPROUNDING_NEGINF;
12349 break;
12350 case 0x5c: /* FCVTAU */
12351 need_rmode = true;
12352 rmode = FPROUNDING_TIEAWAY;
12353 break;
12354 case 0x7a: /* FCVTPU */
12355 need_rmode = true;
12356 rmode = FPROUNDING_POSINF;
12357 break;
12358 case 0x7b: /* FCVTZU */
12359 need_rmode = true;
12360 rmode = FPROUNDING_ZERO;
12361 break;
12362 case 0x2f: /* FABS */
12363 case 0x6f: /* FNEG */
12364 need_fpst = false;
12365 break;
12366 case 0x7d: /* FRSQRTE */
12367 case 0x7f: /* FSQRT (vector) */
12368 break;
12369 default:
12370 fprintf(stderr, "%s: insn %#04x fpop %#2x\n", __func__, insn, fpop);
12371 g_assert_not_reached();
12372 }
12373
12374
12375 /* Check additional constraints for the scalar encoding */
12376 if (is_scalar) {
12377 if (!is_q) {
12378 unallocated_encoding(s);
12379 return;
12380 }
12381 /* FRINTxx is only in the vector form */
12382 if (only_in_vector) {
12383 unallocated_encoding(s);
12384 return;
12385 }
12386 }
12387
12388 if (!fp_access_check(s)) {
12389 return;
12390 }
12391
12392 if (need_rmode || need_fpst) {
12393 tcg_fpstatus = get_fpstatus_ptr(true);
12394 }
12395
12396 if (need_rmode) {
12397 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(rmode));
12398 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
12399 }
12400
12401 if (is_scalar) {
12402 TCGv_i32 tcg_op = read_fp_hreg(s, rn);
12403 TCGv_i32 tcg_res = tcg_temp_new_i32();
12404
12405 switch (fpop) {
12406 case 0x1a: /* FCVTNS */
12407 case 0x1b: /* FCVTMS */
12408 case 0x1c: /* FCVTAS */
12409 case 0x3a: /* FCVTPS */
12410 case 0x3b: /* FCVTZS */
12411 gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
12412 break;
12413 case 0x3d: /* FRECPE */
12414 gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
12415 break;
12416 case 0x3f: /* FRECPX */
12417 gen_helper_frecpx_f16(tcg_res, tcg_op, tcg_fpstatus);
12418 break;
12419 case 0x5a: /* FCVTNU */
12420 case 0x5b: /* FCVTMU */
12421 case 0x5c: /* FCVTAU */
12422 case 0x7a: /* FCVTPU */
12423 case 0x7b: /* FCVTZU */
12424 gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
12425 break;
12426 case 0x6f: /* FNEG */
12427 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
12428 break;
12429 case 0x7d: /* FRSQRTE */
12430 gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
12431 break;
12432 default:
12433 g_assert_not_reached();
12434 }
12435
12436 /* limit any sign extension going on */
12437 tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff);
12438 write_fp_sreg(s, rd, tcg_res);
12439
12440 tcg_temp_free_i32(tcg_res);
12441 tcg_temp_free_i32(tcg_op);
12442 } else {
12443 for (pass = 0; pass < (is_q ? 8 : 4); pass++) {
12444 TCGv_i32 tcg_op = tcg_temp_new_i32();
12445 TCGv_i32 tcg_res = tcg_temp_new_i32();
12446
12447 read_vec_element_i32(s, tcg_op, rn, pass, MO_16);
12448
12449 switch (fpop) {
12450 case 0x1a: /* FCVTNS */
12451 case 0x1b: /* FCVTMS */
12452 case 0x1c: /* FCVTAS */
12453 case 0x3a: /* FCVTPS */
12454 case 0x3b: /* FCVTZS */
12455 gen_helper_advsimd_f16tosinth(tcg_res, tcg_op, tcg_fpstatus);
12456 break;
12457 case 0x3d: /* FRECPE */
12458 gen_helper_recpe_f16(tcg_res, tcg_op, tcg_fpstatus);
12459 break;
12460 case 0x5a: /* FCVTNU */
12461 case 0x5b: /* FCVTMU */
12462 case 0x5c: /* FCVTAU */
12463 case 0x7a: /* FCVTPU */
12464 case 0x7b: /* FCVTZU */
12465 gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus);
12466 break;
12467 case 0x18: /* FRINTN */
12468 case 0x19: /* FRINTM */
12469 case 0x38: /* FRINTP */
12470 case 0x39: /* FRINTZ */
12471 case 0x58: /* FRINTA */
12472 case 0x79: /* FRINTI */
12473 gen_helper_advsimd_rinth(tcg_res, tcg_op, tcg_fpstatus);
12474 break;
12475 case 0x59: /* FRINTX */
12476 gen_helper_advsimd_rinth_exact(tcg_res, tcg_op, tcg_fpstatus);
12477 break;
12478 case 0x2f: /* FABS */
12479 tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff);
12480 break;
12481 case 0x6f: /* FNEG */
12482 tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000);
12483 break;
12484 case 0x7d: /* FRSQRTE */
12485 gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus);
12486 break;
12487 case 0x7f: /* FSQRT */
12488 gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus);
12489 break;
12490 default:
12491 g_assert_not_reached();
12492 }
12493
12494 write_vec_element_i32(s, tcg_res, rd, pass, MO_16);
12495
12496 tcg_temp_free_i32(tcg_res);
12497 tcg_temp_free_i32(tcg_op);
12498 }
12499
12500 clear_vec_high(s, is_q, rd);
12501 }
12502
12503 if (tcg_rmode) {
12504 gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus);
12505 tcg_temp_free_i32(tcg_rmode);
12506 }
12507
12508 if (tcg_fpstatus) {
12509 tcg_temp_free_ptr(tcg_fpstatus);
12510 }
12511 }
12512
12513 /* AdvSIMD scalar x indexed element
12514 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12515 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12516 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12517 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12518 * AdvSIMD vector x indexed element
12519 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12520 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12521 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12522 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12523 */
12524 static void disas_simd_indexed(DisasContext *s, uint32_t insn)
12525 {
12526 /* This encoding has two kinds of instruction:
12527 * normal, where we perform elt x idxelt => elt for each
12528 * element in the vector
12529 * long, where we perform elt x idxelt and generate a result of
12530 * double the width of the input element
12531 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12532 */
12533 bool is_scalar = extract32(insn, 28, 1);
12534 bool is_q = extract32(insn, 30, 1);
12535 bool u = extract32(insn, 29, 1);
12536 int size = extract32(insn, 22, 2);
12537 int l = extract32(insn, 21, 1);
12538 int m = extract32(insn, 20, 1);
12539 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12540 int rm = extract32(insn, 16, 4);
12541 int opcode = extract32(insn, 12, 4);
12542 int h = extract32(insn, 11, 1);
12543 int rn = extract32(insn, 5, 5);
12544 int rd = extract32(insn, 0, 5);
12545 bool is_long = false;
12546 int is_fp = 0;
12547 bool is_fp16 = false;
12548 int index;
12549 TCGv_ptr fpst;
12550
12551 switch (16 * u + opcode) {
12552 case 0x08: /* MUL */
12553 case 0x10: /* MLA */
12554 case 0x14: /* MLS */
12555 if (is_scalar) {
12556 unallocated_encoding(s);
12557 return;
12558 }
12559 break;
12560 case 0x02: /* SMLAL, SMLAL2 */
12561 case 0x12: /* UMLAL, UMLAL2 */
12562 case 0x06: /* SMLSL, SMLSL2 */
12563 case 0x16: /* UMLSL, UMLSL2 */
12564 case 0x0a: /* SMULL, SMULL2 */
12565 case 0x1a: /* UMULL, UMULL2 */
12566 if (is_scalar) {
12567 unallocated_encoding(s);
12568 return;
12569 }
12570 is_long = true;
12571 break;
12572 case 0x03: /* SQDMLAL, SQDMLAL2 */
12573 case 0x07: /* SQDMLSL, SQDMLSL2 */
12574 case 0x0b: /* SQDMULL, SQDMULL2 */
12575 is_long = true;
12576 break;
12577 case 0x0c: /* SQDMULH */
12578 case 0x0d: /* SQRDMULH */
12579 break;
12580 case 0x01: /* FMLA */
12581 case 0x05: /* FMLS */
12582 case 0x09: /* FMUL */
12583 case 0x19: /* FMULX */
12584 is_fp = 1;
12585 break;
12586 case 0x1d: /* SQRDMLAH */
12587 case 0x1f: /* SQRDMLSH */
12588 if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) {
12589 unallocated_encoding(s);
12590 return;
12591 }
12592 break;
12593 case 0x0e: /* SDOT */
12594 case 0x1e: /* UDOT */
12595 if (size != MO_32 || !arm_dc_feature(s, ARM_FEATURE_V8_DOTPROD)) {
12596 unallocated_encoding(s);
12597 return;
12598 }
12599 break;
12600 case 0x11: /* FCMLA #0 */
12601 case 0x13: /* FCMLA #90 */
12602 case 0x15: /* FCMLA #180 */
12603 case 0x17: /* FCMLA #270 */
12604 if (!arm_dc_feature(s, ARM_FEATURE_V8_FCMA)) {
12605 unallocated_encoding(s);
12606 return;
12607 }
12608 is_fp = 2;
12609 break;
12610 default:
12611 unallocated_encoding(s);
12612 return;
12613 }
12614
12615 switch (is_fp) {
12616 case 1: /* normal fp */
12617 /* convert insn encoded size to TCGMemOp size */
12618 switch (size) {
12619 case 0: /* half-precision */
12620 size = MO_16;
12621 is_fp16 = true;
12622 break;
12623 case MO_32: /* single precision */
12624 case MO_64: /* double precision */
12625 break;
12626 default:
12627 unallocated_encoding(s);
12628 return;
12629 }
12630 break;
12631
12632 case 2: /* complex fp */
12633 /* Each indexable element is a complex pair. */
12634 size <<= 1;
12635 switch (size) {
12636 case MO_32:
12637 if (h && !is_q) {
12638 unallocated_encoding(s);
12639 return;
12640 }
12641 is_fp16 = true;
12642 break;
12643 case MO_64:
12644 break;
12645 default:
12646 unallocated_encoding(s);
12647 return;
12648 }
12649 break;
12650
12651 default: /* integer */
12652 switch (size) {
12653 case MO_8:
12654 case MO_64:
12655 unallocated_encoding(s);
12656 return;
12657 }
12658 break;
12659 }
12660 if (is_fp16 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
12661 unallocated_encoding(s);
12662 return;
12663 }
12664
12665 /* Given TCGMemOp size, adjust register and indexing. */
12666 switch (size) {
12667 case MO_16:
12668 index = h << 2 | l << 1 | m;
12669 break;
12670 case MO_32:
12671 index = h << 1 | l;
12672 rm |= m << 4;
12673 break;
12674 case MO_64:
12675 if (l || !is_q) {
12676 unallocated_encoding(s);
12677 return;
12678 }
12679 index = h;
12680 rm |= m << 4;
12681 break;
12682 default:
12683 g_assert_not_reached();
12684 }
12685
12686 if (!fp_access_check(s)) {
12687 return;
12688 }
12689
12690 if (is_fp) {
12691 fpst = get_fpstatus_ptr(is_fp16);
12692 } else {
12693 fpst = NULL;
12694 }
12695
12696 switch (16 * u + opcode) {
12697 case 0x0e: /* SDOT */
12698 case 0x1e: /* UDOT */
12699 gen_gvec_op3_ool(s, is_q, rd, rn, rm, index,
12700 u ? gen_helper_gvec_udot_idx_b
12701 : gen_helper_gvec_sdot_idx_b);
12702 return;
12703 case 0x11: /* FCMLA #0 */
12704 case 0x13: /* FCMLA #90 */
12705 case 0x15: /* FCMLA #180 */
12706 case 0x17: /* FCMLA #270 */
12707 {
12708 int rot = extract32(insn, 13, 2);
12709 int data = (index << 2) | rot;
12710 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
12711 vec_full_reg_offset(s, rn),
12712 vec_full_reg_offset(s, rm), fpst,
12713 is_q ? 16 : 8, vec_full_reg_size(s), data,
12714 size == MO_64
12715 ? gen_helper_gvec_fcmlas_idx
12716 : gen_helper_gvec_fcmlah_idx);
12717 tcg_temp_free_ptr(fpst);
12718 }
12719 return;
12720 }
12721
12722 if (size == 3) {
12723 TCGv_i64 tcg_idx = tcg_temp_new_i64();
12724 int pass;
12725
12726 assert(is_fp && is_q && !is_long);
12727
12728 read_vec_element(s, tcg_idx, rm, index, MO_64);
12729
12730 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
12731 TCGv_i64 tcg_op = tcg_temp_new_i64();
12732 TCGv_i64 tcg_res = tcg_temp_new_i64();
12733
12734 read_vec_element(s, tcg_op, rn, pass, MO_64);
12735
12736 switch (16 * u + opcode) {
12737 case 0x05: /* FMLS */
12738 /* As usual for ARM, separate negation for fused multiply-add */
12739 gen_helper_vfp_negd(tcg_op, tcg_op);
12740 /* fall through */
12741 case 0x01: /* FMLA */
12742 read_vec_element(s, tcg_res, rd, pass, MO_64);
12743 gen_helper_vfp_muladdd(tcg_res, tcg_op, tcg_idx, tcg_res, fpst);
12744 break;
12745 case 0x09: /* FMUL */
12746 gen_helper_vfp_muld(tcg_res, tcg_op, tcg_idx, fpst);
12747 break;
12748 case 0x19: /* FMULX */
12749 gen_helper_vfp_mulxd(tcg_res, tcg_op, tcg_idx, fpst);
12750 break;
12751 default:
12752 g_assert_not_reached();
12753 }
12754
12755 write_vec_element(s, tcg_res, rd, pass, MO_64);
12756 tcg_temp_free_i64(tcg_op);
12757 tcg_temp_free_i64(tcg_res);
12758 }
12759
12760 tcg_temp_free_i64(tcg_idx);
12761 clear_vec_high(s, !is_scalar, rd);
12762 } else if (!is_long) {
12763 /* 32 bit floating point, or 16 or 32 bit integer.
12764 * For the 16 bit scalar case we use the usual Neon helpers and
12765 * rely on the fact that 0 op 0 == 0 with no side effects.
12766 */
12767 TCGv_i32 tcg_idx = tcg_temp_new_i32();
12768 int pass, maxpasses;
12769
12770 if (is_scalar) {
12771 maxpasses = 1;
12772 } else {
12773 maxpasses = is_q ? 4 : 2;
12774 }
12775
12776 read_vec_element_i32(s, tcg_idx, rm, index, size);
12777
12778 if (size == 1 && !is_scalar) {
12779 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12780 * the index into both halves of the 32 bit tcg_idx and then use
12781 * the usual Neon helpers.
12782 */
12783 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
12784 }
12785
12786 for (pass = 0; pass < maxpasses; pass++) {
12787 TCGv_i32 tcg_op = tcg_temp_new_i32();
12788 TCGv_i32 tcg_res = tcg_temp_new_i32();
12789
12790 read_vec_element_i32(s, tcg_op, rn, pass, is_scalar ? size : MO_32);
12791
12792 switch (16 * u + opcode) {
12793 case 0x08: /* MUL */
12794 case 0x10: /* MLA */
12795 case 0x14: /* MLS */
12796 {
12797 static NeonGenTwoOpFn * const fns[2][2] = {
12798 { gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
12799 { tcg_gen_add_i32, tcg_gen_sub_i32 },
12800 };
12801 NeonGenTwoOpFn *genfn;
12802 bool is_sub = opcode == 0x4;
12803
12804 if (size == 1) {
12805 gen_helper_neon_mul_u16(tcg_res, tcg_op, tcg_idx);
12806 } else {
12807 tcg_gen_mul_i32(tcg_res, tcg_op, tcg_idx);
12808 }
12809 if (opcode == 0x8) {
12810 break;
12811 }
12812 read_vec_element_i32(s, tcg_op, rd, pass, MO_32);
12813 genfn = fns[size - 1][is_sub];
12814 genfn(tcg_res, tcg_op, tcg_res);
12815 break;
12816 }
12817 case 0x05: /* FMLS */
12818 case 0x01: /* FMLA */
12819 read_vec_element_i32(s, tcg_res, rd, pass,
12820 is_scalar ? size : MO_32);
12821 switch (size) {
12822 case 1:
12823 if (opcode == 0x5) {
12824 /* As usual for ARM, separate negation for fused
12825 * multiply-add */
12826 tcg_gen_xori_i32(tcg_op, tcg_op, 0x80008000);
12827 }
12828 if (is_scalar) {
12829 gen_helper_advsimd_muladdh(tcg_res, tcg_op, tcg_idx,
12830 tcg_res, fpst);
12831 } else {
12832 gen_helper_advsimd_muladd2h(tcg_res, tcg_op, tcg_idx,
12833 tcg_res, fpst);
12834 }
12835 break;
12836 case 2:
12837 if (opcode == 0x5) {
12838 /* As usual for ARM, separate negation for
12839 * fused multiply-add */
12840 tcg_gen_xori_i32(tcg_op, tcg_op, 0x80000000);
12841 }
12842 gen_helper_vfp_muladds(tcg_res, tcg_op, tcg_idx,
12843 tcg_res, fpst);
12844 break;
12845 default:
12846 g_assert_not_reached();
12847 }
12848 break;
12849 case 0x09: /* FMUL */
12850 switch (size) {
12851 case 1:
12852 if (is_scalar) {
12853 gen_helper_advsimd_mulh(tcg_res, tcg_op,
12854 tcg_idx, fpst);
12855 } else {
12856 gen_helper_advsimd_mul2h(tcg_res, tcg_op,
12857 tcg_idx, fpst);
12858 }
12859 break;
12860 case 2:
12861 gen_helper_vfp_muls(tcg_res, tcg_op, tcg_idx, fpst);
12862 break;
12863 default:
12864 g_assert_not_reached();
12865 }
12866 break;
12867 case 0x19: /* FMULX */
12868 switch (size) {
12869 case 1:
12870 if (is_scalar) {
12871 gen_helper_advsimd_mulxh(tcg_res, tcg_op,
12872 tcg_idx, fpst);
12873 } else {
12874 gen_helper_advsimd_mulx2h(tcg_res, tcg_op,
12875 tcg_idx, fpst);
12876 }
12877 break;
12878 case 2:
12879 gen_helper_vfp_mulxs(tcg_res, tcg_op, tcg_idx, fpst);
12880 break;
12881 default:
12882 g_assert_not_reached();
12883 }
12884 break;
12885 case 0x0c: /* SQDMULH */
12886 if (size == 1) {
12887 gen_helper_neon_qdmulh_s16(tcg_res, cpu_env,
12888 tcg_op, tcg_idx);
12889 } else {
12890 gen_helper_neon_qdmulh_s32(tcg_res, cpu_env,
12891 tcg_op, tcg_idx);
12892 }
12893 break;
12894 case 0x0d: /* SQRDMULH */
12895 if (size == 1) {
12896 gen_helper_neon_qrdmulh_s16(tcg_res, cpu_env,
12897 tcg_op, tcg_idx);
12898 } else {
12899 gen_helper_neon_qrdmulh_s32(tcg_res, cpu_env,
12900 tcg_op, tcg_idx);
12901 }
12902 break;
12903 case 0x1d: /* SQRDMLAH */
12904 read_vec_element_i32(s, tcg_res, rd, pass,
12905 is_scalar ? size : MO_32);
12906 if (size == 1) {
12907 gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env,
12908 tcg_op, tcg_idx, tcg_res);
12909 } else {
12910 gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env,
12911 tcg_op, tcg_idx, tcg_res);
12912 }
12913 break;
12914 case 0x1f: /* SQRDMLSH */
12915 read_vec_element_i32(s, tcg_res, rd, pass,
12916 is_scalar ? size : MO_32);
12917 if (size == 1) {
12918 gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env,
12919 tcg_op, tcg_idx, tcg_res);
12920 } else {
12921 gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env,
12922 tcg_op, tcg_idx, tcg_res);
12923 }
12924 break;
12925 default:
12926 g_assert_not_reached();
12927 }
12928
12929 if (is_scalar) {
12930 write_fp_sreg(s, rd, tcg_res);
12931 } else {
12932 write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
12933 }
12934
12935 tcg_temp_free_i32(tcg_op);
12936 tcg_temp_free_i32(tcg_res);
12937 }
12938
12939 tcg_temp_free_i32(tcg_idx);
12940 clear_vec_high(s, is_q, rd);
12941 } else {
12942 /* long ops: 16x16->32 or 32x32->64 */
12943 TCGv_i64 tcg_res[2];
12944 int pass;
12945 bool satop = extract32(opcode, 0, 1);
12946 TCGMemOp memop = MO_32;
12947
12948 if (satop || !u) {
12949 memop |= MO_SIGN;
12950 }
12951
12952 if (size == 2) {
12953 TCGv_i64 tcg_idx = tcg_temp_new_i64();
12954
12955 read_vec_element(s, tcg_idx, rm, index, memop);
12956
12957 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
12958 TCGv_i64 tcg_op = tcg_temp_new_i64();
12959 TCGv_i64 tcg_passres;
12960 int passelt;
12961
12962 if (is_scalar) {
12963 passelt = 0;
12964 } else {
12965 passelt = pass + (is_q * 2);
12966 }
12967
12968 read_vec_element(s, tcg_op, rn, passelt, memop);
12969
12970 tcg_res[pass] = tcg_temp_new_i64();
12971
12972 if (opcode == 0xa || opcode == 0xb) {
12973 /* Non-accumulating ops */
12974 tcg_passres = tcg_res[pass];
12975 } else {
12976 tcg_passres = tcg_temp_new_i64();
12977 }
12978
12979 tcg_gen_mul_i64(tcg_passres, tcg_op, tcg_idx);
12980 tcg_temp_free_i64(tcg_op);
12981
12982 if (satop) {
12983 /* saturating, doubling */
12984 gen_helper_neon_addl_saturate_s64(tcg_passres, cpu_env,
12985 tcg_passres, tcg_passres);
12986 }
12987
12988 if (opcode == 0xa || opcode == 0xb) {
12989 continue;
12990 }
12991
12992 /* Accumulating op: handle accumulate step */
12993 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
12994
12995 switch (opcode) {
12996 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
12997 tcg_gen_add_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
12998 break;
12999 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13000 tcg_gen_sub_i64(tcg_res[pass], tcg_res[pass], tcg_passres);
13001 break;
13002 case 0x7: /* SQDMLSL, SQDMLSL2 */
13003 tcg_gen_neg_i64(tcg_passres, tcg_passres);
13004 /* fall through */
13005 case 0x3: /* SQDMLAL, SQDMLAL2 */
13006 gen_helper_neon_addl_saturate_s64(tcg_res[pass], cpu_env,
13007 tcg_res[pass],
13008 tcg_passres);
13009 break;
13010 default:
13011 g_assert_not_reached();
13012 }
13013 tcg_temp_free_i64(tcg_passres);
13014 }
13015 tcg_temp_free_i64(tcg_idx);
13016
13017 clear_vec_high(s, !is_scalar, rd);
13018 } else {
13019 TCGv_i32 tcg_idx = tcg_temp_new_i32();
13020
13021 assert(size == 1);
13022 read_vec_element_i32(s, tcg_idx, rm, index, size);
13023
13024 if (!is_scalar) {
13025 /* The simplest way to handle the 16x16 indexed ops is to
13026 * duplicate the index into both halves of the 32 bit tcg_idx
13027 * and then use the usual Neon helpers.
13028 */
13029 tcg_gen_deposit_i32(tcg_idx, tcg_idx, tcg_idx, 16, 16);
13030 }
13031
13032 for (pass = 0; pass < (is_scalar ? 1 : 2); pass++) {
13033 TCGv_i32 tcg_op = tcg_temp_new_i32();
13034 TCGv_i64 tcg_passres;
13035
13036 if (is_scalar) {
13037 read_vec_element_i32(s, tcg_op, rn, pass, size);
13038 } else {
13039 read_vec_element_i32(s, tcg_op, rn,
13040 pass + (is_q * 2), MO_32);
13041 }
13042
13043 tcg_res[pass] = tcg_temp_new_i64();
13044
13045 if (opcode == 0xa || opcode == 0xb) {
13046 /* Non-accumulating ops */
13047 tcg_passres = tcg_res[pass];
13048 } else {
13049 tcg_passres = tcg_temp_new_i64();
13050 }
13051
13052 if (memop & MO_SIGN) {
13053 gen_helper_neon_mull_s16(tcg_passres, tcg_op, tcg_idx);
13054 } else {
13055 gen_helper_neon_mull_u16(tcg_passres, tcg_op, tcg_idx);
13056 }
13057 if (satop) {
13058 gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env,
13059 tcg_passres, tcg_passres);
13060 }
13061 tcg_temp_free_i32(tcg_op);
13062
13063 if (opcode == 0xa || opcode == 0xb) {
13064 continue;
13065 }
13066
13067 /* Accumulating op: handle accumulate step */
13068 read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
13069
13070 switch (opcode) {
13071 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13072 gen_helper_neon_addl_u32(tcg_res[pass], tcg_res[pass],
13073 tcg_passres);
13074 break;
13075 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13076 gen_helper_neon_subl_u32(tcg_res[pass], tcg_res[pass],
13077 tcg_passres);
13078 break;
13079 case 0x7: /* SQDMLSL, SQDMLSL2 */
13080 gen_helper_neon_negl_u32(tcg_passres, tcg_passres);
13081 /* fall through */
13082 case 0x3: /* SQDMLAL, SQDMLAL2 */
13083 gen_helper_neon_addl_saturate_s32(tcg_res[pass], cpu_env,
13084 tcg_res[pass],
13085 tcg_passres);
13086 break;
13087 default:
13088 g_assert_not_reached();
13089 }
13090 tcg_temp_free_i64(tcg_passres);
13091 }
13092 tcg_temp_free_i32(tcg_idx);
13093
13094 if (is_scalar) {
13095 tcg_gen_ext32u_i64(tcg_res[0], tcg_res[0]);
13096 }
13097 }
13098
13099 if (is_scalar) {
13100 tcg_res[1] = tcg_const_i64(0);
13101 }
13102
13103 for (pass = 0; pass < 2; pass++) {
13104 write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
13105 tcg_temp_free_i64(tcg_res[pass]);
13106 }
13107 }
13108
13109 if (fpst) {
13110 tcg_temp_free_ptr(fpst);
13111 }
13112 }
13113
13114 /* Crypto AES
13115 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13116 * +-----------------+------+-----------+--------+-----+------+------+
13117 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13118 * +-----------------+------+-----------+--------+-----+------+------+
13119 */
13120 static void disas_crypto_aes(DisasContext *s, uint32_t insn)
13121 {
13122 int size = extract32(insn, 22, 2);
13123 int opcode = extract32(insn, 12, 5);
13124 int rn = extract32(insn, 5, 5);
13125 int rd = extract32(insn, 0, 5);
13126 int decrypt;
13127 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
13128 TCGv_i32 tcg_decrypt;
13129 CryptoThreeOpIntFn *genfn;
13130
13131 if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)
13132 || size != 0) {
13133 unallocated_encoding(s);
13134 return;
13135 }
13136
13137 switch (opcode) {
13138 case 0x4: /* AESE */
13139 decrypt = 0;
13140 genfn = gen_helper_crypto_aese;
13141 break;
13142 case 0x6: /* AESMC */
13143 decrypt = 0;
13144 genfn = gen_helper_crypto_aesmc;
13145 break;
13146 case 0x5: /* AESD */
13147 decrypt = 1;
13148 genfn = gen_helper_crypto_aese;
13149 break;
13150 case 0x7: /* AESIMC */
13151 decrypt = 1;
13152 genfn = gen_helper_crypto_aesmc;
13153 break;
13154 default:
13155 unallocated_encoding(s);
13156 return;
13157 }
13158
13159 if (!fp_access_check(s)) {
13160 return;
13161 }
13162
13163 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13164 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13165 tcg_decrypt = tcg_const_i32(decrypt);
13166
13167 genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt);
13168
13169 tcg_temp_free_ptr(tcg_rd_ptr);
13170 tcg_temp_free_ptr(tcg_rn_ptr);
13171 tcg_temp_free_i32(tcg_decrypt);
13172 }
13173
13174 /* Crypto three-reg SHA
13175 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13176 * +-----------------+------+---+------+---+--------+-----+------+------+
13177 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13178 * +-----------------+------+---+------+---+--------+-----+------+------+
13179 */
13180 static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn)
13181 {
13182 int size = extract32(insn, 22, 2);
13183 int opcode = extract32(insn, 12, 3);
13184 int rm = extract32(insn, 16, 5);
13185 int rn = extract32(insn, 5, 5);
13186 int rd = extract32(insn, 0, 5);
13187 CryptoThreeOpFn *genfn;
13188 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
13189 int feature = ARM_FEATURE_V8_SHA256;
13190
13191 if (size != 0) {
13192 unallocated_encoding(s);
13193 return;
13194 }
13195
13196 switch (opcode) {
13197 case 0: /* SHA1C */
13198 case 1: /* SHA1P */
13199 case 2: /* SHA1M */
13200 case 3: /* SHA1SU0 */
13201 genfn = NULL;
13202 feature = ARM_FEATURE_V8_SHA1;
13203 break;
13204 case 4: /* SHA256H */
13205 genfn = gen_helper_crypto_sha256h;
13206 break;
13207 case 5: /* SHA256H2 */
13208 genfn = gen_helper_crypto_sha256h2;
13209 break;
13210 case 6: /* SHA256SU1 */
13211 genfn = gen_helper_crypto_sha256su1;
13212 break;
13213 default:
13214 unallocated_encoding(s);
13215 return;
13216 }
13217
13218 if (!arm_dc_feature(s, feature)) {
13219 unallocated_encoding(s);
13220 return;
13221 }
13222
13223 if (!fp_access_check(s)) {
13224 return;
13225 }
13226
13227 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13228 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13229 tcg_rm_ptr = vec_full_reg_ptr(s, rm);
13230
13231 if (genfn) {
13232 genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
13233 } else {
13234 TCGv_i32 tcg_opcode = tcg_const_i32(opcode);
13235
13236 gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr,
13237 tcg_rm_ptr, tcg_opcode);
13238 tcg_temp_free_i32(tcg_opcode);
13239 }
13240
13241 tcg_temp_free_ptr(tcg_rd_ptr);
13242 tcg_temp_free_ptr(tcg_rn_ptr);
13243 tcg_temp_free_ptr(tcg_rm_ptr);
13244 }
13245
13246 /* Crypto two-reg SHA
13247 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13248 * +-----------------+------+-----------+--------+-----+------+------+
13249 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13250 * +-----------------+------+-----------+--------+-----+------+------+
13251 */
13252 static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
13253 {
13254 int size = extract32(insn, 22, 2);
13255 int opcode = extract32(insn, 12, 5);
13256 int rn = extract32(insn, 5, 5);
13257 int rd = extract32(insn, 0, 5);
13258 CryptoTwoOpFn *genfn;
13259 int feature;
13260 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
13261
13262 if (size != 0) {
13263 unallocated_encoding(s);
13264 return;
13265 }
13266
13267 switch (opcode) {
13268 case 0: /* SHA1H */
13269 feature = ARM_FEATURE_V8_SHA1;
13270 genfn = gen_helper_crypto_sha1h;
13271 break;
13272 case 1: /* SHA1SU1 */
13273 feature = ARM_FEATURE_V8_SHA1;
13274 genfn = gen_helper_crypto_sha1su1;
13275 break;
13276 case 2: /* SHA256SU0 */
13277 feature = ARM_FEATURE_V8_SHA256;
13278 genfn = gen_helper_crypto_sha256su0;
13279 break;
13280 default:
13281 unallocated_encoding(s);
13282 return;
13283 }
13284
13285 if (!arm_dc_feature(s, feature)) {
13286 unallocated_encoding(s);
13287 return;
13288 }
13289
13290 if (!fp_access_check(s)) {
13291 return;
13292 }
13293
13294 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13295 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13296
13297 genfn(tcg_rd_ptr, tcg_rn_ptr);
13298
13299 tcg_temp_free_ptr(tcg_rd_ptr);
13300 tcg_temp_free_ptr(tcg_rn_ptr);
13301 }
13302
13303 /* Crypto three-reg SHA512
13304 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13305 * +-----------------------+------+---+---+-----+--------+------+------+
13306 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13307 * +-----------------------+------+---+---+-----+--------+------+------+
13308 */
13309 static void disas_crypto_three_reg_sha512(DisasContext *s, uint32_t insn)
13310 {
13311 int opcode = extract32(insn, 10, 2);
13312 int o = extract32(insn, 14, 1);
13313 int rm = extract32(insn, 16, 5);
13314 int rn = extract32(insn, 5, 5);
13315 int rd = extract32(insn, 0, 5);
13316 int feature;
13317 CryptoThreeOpFn *genfn;
13318
13319 if (o == 0) {
13320 switch (opcode) {
13321 case 0: /* SHA512H */
13322 feature = ARM_FEATURE_V8_SHA512;
13323 genfn = gen_helper_crypto_sha512h;
13324 break;
13325 case 1: /* SHA512H2 */
13326 feature = ARM_FEATURE_V8_SHA512;
13327 genfn = gen_helper_crypto_sha512h2;
13328 break;
13329 case 2: /* SHA512SU1 */
13330 feature = ARM_FEATURE_V8_SHA512;
13331 genfn = gen_helper_crypto_sha512su1;
13332 break;
13333 case 3: /* RAX1 */
13334 feature = ARM_FEATURE_V8_SHA3;
13335 genfn = NULL;
13336 break;
13337 }
13338 } else {
13339 switch (opcode) {
13340 case 0: /* SM3PARTW1 */
13341 feature = ARM_FEATURE_V8_SM3;
13342 genfn = gen_helper_crypto_sm3partw1;
13343 break;
13344 case 1: /* SM3PARTW2 */
13345 feature = ARM_FEATURE_V8_SM3;
13346 genfn = gen_helper_crypto_sm3partw2;
13347 break;
13348 case 2: /* SM4EKEY */
13349 feature = ARM_FEATURE_V8_SM4;
13350 genfn = gen_helper_crypto_sm4ekey;
13351 break;
13352 default:
13353 unallocated_encoding(s);
13354 return;
13355 }
13356 }
13357
13358 if (!arm_dc_feature(s, feature)) {
13359 unallocated_encoding(s);
13360 return;
13361 }
13362
13363 if (!fp_access_check(s)) {
13364 return;
13365 }
13366
13367 if (genfn) {
13368 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
13369
13370 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13371 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13372 tcg_rm_ptr = vec_full_reg_ptr(s, rm);
13373
13374 genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr);
13375
13376 tcg_temp_free_ptr(tcg_rd_ptr);
13377 tcg_temp_free_ptr(tcg_rn_ptr);
13378 tcg_temp_free_ptr(tcg_rm_ptr);
13379 } else {
13380 TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
13381 int pass;
13382
13383 tcg_op1 = tcg_temp_new_i64();
13384 tcg_op2 = tcg_temp_new_i64();
13385 tcg_res[0] = tcg_temp_new_i64();
13386 tcg_res[1] = tcg_temp_new_i64();
13387
13388 for (pass = 0; pass < 2; pass++) {
13389 read_vec_element(s, tcg_op1, rn, pass, MO_64);
13390 read_vec_element(s, tcg_op2, rm, pass, MO_64);
13391
13392 tcg_gen_rotli_i64(tcg_res[pass], tcg_op2, 1);
13393 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
13394 }
13395 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
13396 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
13397
13398 tcg_temp_free_i64(tcg_op1);
13399 tcg_temp_free_i64(tcg_op2);
13400 tcg_temp_free_i64(tcg_res[0]);
13401 tcg_temp_free_i64(tcg_res[1]);
13402 }
13403 }
13404
13405 /* Crypto two-reg SHA512
13406 * 31 12 11 10 9 5 4 0
13407 * +-----------------------------------------+--------+------+------+
13408 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13409 * +-----------------------------------------+--------+------+------+
13410 */
13411 static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
13412 {
13413 int opcode = extract32(insn, 10, 2);
13414 int rn = extract32(insn, 5, 5);
13415 int rd = extract32(insn, 0, 5);
13416 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr;
13417 int feature;
13418 CryptoTwoOpFn *genfn;
13419
13420 switch (opcode) {
13421 case 0: /* SHA512SU0 */
13422 feature = ARM_FEATURE_V8_SHA512;
13423 genfn = gen_helper_crypto_sha512su0;
13424 break;
13425 case 1: /* SM4E */
13426 feature = ARM_FEATURE_V8_SM4;
13427 genfn = gen_helper_crypto_sm4e;
13428 break;
13429 default:
13430 unallocated_encoding(s);
13431 return;
13432 }
13433
13434 if (!arm_dc_feature(s, feature)) {
13435 unallocated_encoding(s);
13436 return;
13437 }
13438
13439 if (!fp_access_check(s)) {
13440 return;
13441 }
13442
13443 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13444 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13445
13446 genfn(tcg_rd_ptr, tcg_rn_ptr);
13447
13448 tcg_temp_free_ptr(tcg_rd_ptr);
13449 tcg_temp_free_ptr(tcg_rn_ptr);
13450 }
13451
13452 /* Crypto four-register
13453 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13454 * +-------------------+-----+------+---+------+------+------+
13455 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13456 * +-------------------+-----+------+---+------+------+------+
13457 */
13458 static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
13459 {
13460 int op0 = extract32(insn, 21, 2);
13461 int rm = extract32(insn, 16, 5);
13462 int ra = extract32(insn, 10, 5);
13463 int rn = extract32(insn, 5, 5);
13464 int rd = extract32(insn, 0, 5);
13465 int feature;
13466
13467 switch (op0) {
13468 case 0: /* EOR3 */
13469 case 1: /* BCAX */
13470 feature = ARM_FEATURE_V8_SHA3;
13471 break;
13472 case 2: /* SM3SS1 */
13473 feature = ARM_FEATURE_V8_SM3;
13474 break;
13475 default:
13476 unallocated_encoding(s);
13477 return;
13478 }
13479
13480 if (!arm_dc_feature(s, feature)) {
13481 unallocated_encoding(s);
13482 return;
13483 }
13484
13485 if (!fp_access_check(s)) {
13486 return;
13487 }
13488
13489 if (op0 < 2) {
13490 TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2];
13491 int pass;
13492
13493 tcg_op1 = tcg_temp_new_i64();
13494 tcg_op2 = tcg_temp_new_i64();
13495 tcg_op3 = tcg_temp_new_i64();
13496 tcg_res[0] = tcg_temp_new_i64();
13497 tcg_res[1] = tcg_temp_new_i64();
13498
13499 for (pass = 0; pass < 2; pass++) {
13500 read_vec_element(s, tcg_op1, rn, pass, MO_64);
13501 read_vec_element(s, tcg_op2, rm, pass, MO_64);
13502 read_vec_element(s, tcg_op3, ra, pass, MO_64);
13503
13504 if (op0 == 0) {
13505 /* EOR3 */
13506 tcg_gen_xor_i64(tcg_res[pass], tcg_op2, tcg_op3);
13507 } else {
13508 /* BCAX */
13509 tcg_gen_andc_i64(tcg_res[pass], tcg_op2, tcg_op3);
13510 }
13511 tcg_gen_xor_i64(tcg_res[pass], tcg_res[pass], tcg_op1);
13512 }
13513 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
13514 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
13515
13516 tcg_temp_free_i64(tcg_op1);
13517 tcg_temp_free_i64(tcg_op2);
13518 tcg_temp_free_i64(tcg_op3);
13519 tcg_temp_free_i64(tcg_res[0]);
13520 tcg_temp_free_i64(tcg_res[1]);
13521 } else {
13522 TCGv_i32 tcg_op1, tcg_op2, tcg_op3, tcg_res, tcg_zero;
13523
13524 tcg_op1 = tcg_temp_new_i32();
13525 tcg_op2 = tcg_temp_new_i32();
13526 tcg_op3 = tcg_temp_new_i32();
13527 tcg_res = tcg_temp_new_i32();
13528 tcg_zero = tcg_const_i32(0);
13529
13530 read_vec_element_i32(s, tcg_op1, rn, 3, MO_32);
13531 read_vec_element_i32(s, tcg_op2, rm, 3, MO_32);
13532 read_vec_element_i32(s, tcg_op3, ra, 3, MO_32);
13533
13534 tcg_gen_rotri_i32(tcg_res, tcg_op1, 20);
13535 tcg_gen_add_i32(tcg_res, tcg_res, tcg_op2);
13536 tcg_gen_add_i32(tcg_res, tcg_res, tcg_op3);
13537 tcg_gen_rotri_i32(tcg_res, tcg_res, 25);
13538
13539 write_vec_element_i32(s, tcg_zero, rd, 0, MO_32);
13540 write_vec_element_i32(s, tcg_zero, rd, 1, MO_32);
13541 write_vec_element_i32(s, tcg_zero, rd, 2, MO_32);
13542 write_vec_element_i32(s, tcg_res, rd, 3, MO_32);
13543
13544 tcg_temp_free_i32(tcg_op1);
13545 tcg_temp_free_i32(tcg_op2);
13546 tcg_temp_free_i32(tcg_op3);
13547 tcg_temp_free_i32(tcg_res);
13548 tcg_temp_free_i32(tcg_zero);
13549 }
13550 }
13551
13552 /* Crypto XAR
13553 * 31 21 20 16 15 10 9 5 4 0
13554 * +-----------------------+------+--------+------+------+
13555 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13556 * +-----------------------+------+--------+------+------+
13557 */
13558 static void disas_crypto_xar(DisasContext *s, uint32_t insn)
13559 {
13560 int rm = extract32(insn, 16, 5);
13561 int imm6 = extract32(insn, 10, 6);
13562 int rn = extract32(insn, 5, 5);
13563 int rd = extract32(insn, 0, 5);
13564 TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
13565 int pass;
13566
13567 if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) {
13568 unallocated_encoding(s);
13569 return;
13570 }
13571
13572 if (!fp_access_check(s)) {
13573 return;
13574 }
13575
13576 tcg_op1 = tcg_temp_new_i64();
13577 tcg_op2 = tcg_temp_new_i64();
13578 tcg_res[0] = tcg_temp_new_i64();
13579 tcg_res[1] = tcg_temp_new_i64();
13580
13581 for (pass = 0; pass < 2; pass++) {
13582 read_vec_element(s, tcg_op1, rn, pass, MO_64);
13583 read_vec_element(s, tcg_op2, rm, pass, MO_64);
13584
13585 tcg_gen_xor_i64(tcg_res[pass], tcg_op1, tcg_op2);
13586 tcg_gen_rotri_i64(tcg_res[pass], tcg_res[pass], imm6);
13587 }
13588 write_vec_element(s, tcg_res[0], rd, 0, MO_64);
13589 write_vec_element(s, tcg_res[1], rd, 1, MO_64);
13590
13591 tcg_temp_free_i64(tcg_op1);
13592 tcg_temp_free_i64(tcg_op2);
13593 tcg_temp_free_i64(tcg_res[0]);
13594 tcg_temp_free_i64(tcg_res[1]);
13595 }
13596
13597 /* Crypto three-reg imm2
13598 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13599 * +-----------------------+------+-----+------+--------+------+------+
13600 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13601 * +-----------------------+------+-----+------+--------+------+------+
13602 */
13603 static void disas_crypto_three_reg_imm2(DisasContext *s, uint32_t insn)
13604 {
13605 int opcode = extract32(insn, 10, 2);
13606 int imm2 = extract32(insn, 12, 2);
13607 int rm = extract32(insn, 16, 5);
13608 int rn = extract32(insn, 5, 5);
13609 int rd = extract32(insn, 0, 5);
13610 TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr;
13611 TCGv_i32 tcg_imm2, tcg_opcode;
13612
13613 if (!arm_dc_feature(s, ARM_FEATURE_V8_SM3)) {
13614 unallocated_encoding(s);
13615 return;
13616 }
13617
13618 if (!fp_access_check(s)) {
13619 return;
13620 }
13621
13622 tcg_rd_ptr = vec_full_reg_ptr(s, rd);
13623 tcg_rn_ptr = vec_full_reg_ptr(s, rn);
13624 tcg_rm_ptr = vec_full_reg_ptr(s, rm);
13625 tcg_imm2 = tcg_const_i32(imm2);
13626 tcg_opcode = tcg_const_i32(opcode);
13627
13628 gen_helper_crypto_sm3tt(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr, tcg_imm2,
13629 tcg_opcode);
13630
13631 tcg_temp_free_ptr(tcg_rd_ptr);
13632 tcg_temp_free_ptr(tcg_rn_ptr);
13633 tcg_temp_free_ptr(tcg_rm_ptr);
13634 tcg_temp_free_i32(tcg_imm2);
13635 tcg_temp_free_i32(tcg_opcode);
13636 }
13637
13638 /* C3.6 Data processing - SIMD, inc Crypto
13639 *
13640 * As the decode gets a little complex we are using a table based
13641 * approach for this part of the decode.
13642 */
13643 static const AArch64DecodeTable data_proc_simd[] = {
13644 /* pattern , mask , fn */
13645 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same },
13646 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra },
13647 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
13648 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
13649 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
13650 { 0x0e000400, 0x9fe08400, disas_simd_copy },
13651 { 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */
13652 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13653 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
13654 { 0x0f000400, 0x9f800400, disas_simd_shift_imm },
13655 { 0x0e000000, 0xbf208c00, disas_simd_tb },
13656 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn },
13657 { 0x2e000000, 0xbf208400, disas_simd_ext },
13658 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same },
13659 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra },
13660 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
13661 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
13662 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
13663 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },
13664 { 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
13665 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
13666 { 0x4e280800, 0xff3e0c00, disas_crypto_aes },
13667 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha },
13668 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha },
13669 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 },
13670 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 },
13671 { 0xce000000, 0xff808000, disas_crypto_four_reg },
13672 { 0xce800000, 0xffe00000, disas_crypto_xar },
13673 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2 },
13674 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
13675 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16 },
13676 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16 },
13677 { 0x00000000, 0x00000000, NULL }
13678 };
13679
13680 static void disas_data_proc_simd(DisasContext *s, uint32_t insn)
13681 {
13682 /* Note that this is called with all non-FP cases from
13683 * table C3-6 so it must UNDEF for entries not specifically
13684 * allocated to instructions in that table.
13685 */
13686 AArch64DecodeFn *fn = lookup_disas_fn(&data_proc_simd[0], insn);
13687 if (fn) {
13688 fn(s, insn);
13689 } else {
13690 unallocated_encoding(s);
13691 }
13692 }
13693
13694 /* C3.6 Data processing - SIMD and floating point */
13695 static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn)
13696 {
13697 if (extract32(insn, 28, 1) == 1 && extract32(insn, 30, 1) == 0) {
13698 disas_data_proc_fp(s, insn);
13699 } else {
13700 /* SIMD, including crypto */
13701 disas_data_proc_simd(s, insn);
13702 }
13703 }
13704
13705 /* C3.1 A64 instruction index by encoding */
13706 static void disas_a64_insn(CPUARMState *env, DisasContext *s)
13707 {
13708 uint32_t insn;
13709
13710 insn = arm_ldl_code(env, s->pc, s->sctlr_b);
13711 s->insn = insn;
13712 s->pc += 4;
13713
13714 s->fp_access_checked = false;
13715
13716 switch (extract32(insn, 25, 4)) {
13717 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
13718 unallocated_encoding(s);
13719 break;
13720 case 0x2:
13721 if (!arm_dc_feature(s, ARM_FEATURE_SVE) || !disas_sve(s, insn)) {
13722 unallocated_encoding(s);
13723 }
13724 break;
13725 case 0x8: case 0x9: /* Data processing - immediate */
13726 disas_data_proc_imm(s, insn);
13727 break;
13728 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13729 disas_b_exc_sys(s, insn);
13730 break;
13731 case 0x4:
13732 case 0x6:
13733 case 0xc:
13734 case 0xe: /* Loads and stores */
13735 disas_ldst(s, insn);
13736 break;
13737 case 0x5:
13738 case 0xd: /* Data processing - register */
13739 disas_data_proc_reg(s, insn);
13740 break;
13741 case 0x7:
13742 case 0xf: /* Data processing - SIMD and floating point */
13743 disas_data_proc_simd_fp(s, insn);
13744 break;
13745 default:
13746 assert(FALSE); /* all 15 cases should be handled above */
13747 break;
13748 }
13749
13750 /* if we allocated any temporaries, free them here */
13751 free_tmp_a64(s);
13752 }
13753
13754 static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
13755 CPUState *cpu)
13756 {
13757 DisasContext *dc = container_of(dcbase, DisasContext, base);
13758 CPUARMState *env = cpu->env_ptr;
13759 ARMCPU *arm_cpu = arm_env_get_cpu(env);
13760 int bound;
13761
13762 dc->pc = dc->base.pc_first;
13763 dc->condjmp = 0;
13764
13765 dc->aarch64 = 1;
13766 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
13767 * there is no secure EL1, so we route exceptions to EL3.
13768 */
13769 dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
13770 !arm_el_is_aa64(env, 3);
13771 dc->thumb = 0;
13772 dc->sctlr_b = 0;
13773 dc->be_data = ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE;
13774 dc->condexec_mask = 0;
13775 dc->condexec_cond = 0;
13776 dc->mmu_idx = core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb->flags));
13777 dc->tbi0 = ARM_TBFLAG_TBI0(dc->base.tb->flags);
13778 dc->tbi1 = ARM_TBFLAG_TBI1(dc->base.tb->flags);
13779 dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
13780 #if !defined(CONFIG_USER_ONLY)
13781 dc->user = (dc->current_el == 0);
13782 #endif
13783 dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
13784 dc->sve_excp_el = ARM_TBFLAG_SVEEXC_EL(dc->base.tb->flags);
13785 dc->sve_len = (ARM_TBFLAG_ZCR_LEN(dc->base.tb->flags) + 1) * 16;
13786 dc->vec_len = 0;
13787 dc->vec_stride = 0;
13788 dc->cp_regs = arm_cpu->cp_regs;
13789 dc->features = env->features;
13790
13791 /* Single step state. The code-generation logic here is:
13792 * SS_ACTIVE == 0:
13793 * generate code with no special handling for single-stepping (except
13794 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
13795 * this happens anyway because those changes are all system register or
13796 * PSTATE writes).
13797 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
13798 * emit code for one insn
13799 * emit code to clear PSTATE.SS
13800 * emit code to generate software step exception for completed step
13801 * end TB (as usual for having generated an exception)
13802 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
13803 * emit code to generate a software step exception
13804 * end the TB
13805 */
13806 dc->ss_active = ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags);
13807 dc->pstate_ss = ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags);
13808 dc->is_ldex = false;
13809 dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
13810
13811 /* Bound the number of insns to execute to those left on the page. */
13812 bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
13813
13814 /* If architectural single step active, limit to 1. */
13815 if (dc->ss_active) {
13816 bound = 1;
13817 }
13818 dc->base.max_insns = MIN(dc->base.max_insns, bound);
13819
13820 init_tmp_a64_array(dc);
13821 }
13822
13823 static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
13824 {
13825 tcg_clear_temp_count();
13826 }
13827
13828 static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
13829 {
13830 DisasContext *dc = container_of(dcbase, DisasContext, base);
13831
13832 tcg_gen_insn_start(dc->pc, 0, 0);
13833 dc->insn_start = tcg_last_op();
13834 }
13835
13836 static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
13837 const CPUBreakpoint *bp)
13838 {
13839 DisasContext *dc = container_of(dcbase, DisasContext, base);
13840
13841 if (bp->flags & BP_CPU) {
13842 gen_a64_set_pc_im(dc->pc);
13843 gen_helper_check_breakpoints(cpu_env);
13844 /* End the TB early; it likely won't be executed */
13845 dc->base.is_jmp = DISAS_TOO_MANY;
13846 } else {
13847 gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
13848 /* The address covered by the breakpoint must be
13849 included in [tb->pc, tb->pc + tb->size) in order
13850 to for it to be properly cleared -- thus we
13851 increment the PC here so that the logic setting
13852 tb->size below does the right thing. */
13853 dc->pc += 4;
13854 dc->base.is_jmp = DISAS_NORETURN;
13855 }
13856
13857 return true;
13858 }
13859
13860 static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
13861 {
13862 DisasContext *dc = container_of(dcbase, DisasContext, base);
13863 CPUARMState *env = cpu->env_ptr;
13864
13865 if (dc->ss_active && !dc->pstate_ss) {
13866 /* Singlestep state is Active-pending.
13867 * If we're in this state at the start of a TB then either
13868 * a) we just took an exception to an EL which is being debugged
13869 * and this is the first insn in the exception handler
13870 * b) debug exceptions were masked and we just unmasked them
13871 * without changing EL (eg by clearing PSTATE.D)
13872 * In either case we're going to take a swstep exception in the
13873 * "did not step an insn" case, and so the syndrome ISV and EX
13874 * bits should be zero.
13875 */
13876 assert(dc->base.num_insns == 1);
13877 gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
13878 default_exception_el(dc));
13879 dc->base.is_jmp = DISAS_NORETURN;
13880 } else {
13881 disas_a64_insn(env, dc);
13882 }
13883
13884 dc->base.pc_next = dc->pc;
13885 translator_loop_temp_check(&dc->base);
13886 }
13887
13888 static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
13889 {
13890 DisasContext *dc = container_of(dcbase, DisasContext, base);
13891
13892 if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
13893 /* Note that this means single stepping WFI doesn't halt the CPU.
13894 * For conditional branch insns this is harmless unreachable code as
13895 * gen_goto_tb() has already handled emitting the debug exception
13896 * (and thus a tb-jump is not possible when singlestepping).
13897 */
13898 switch (dc->base.is_jmp) {
13899 default:
13900 gen_a64_set_pc_im(dc->pc);
13901 /* fall through */
13902 case DISAS_EXIT:
13903 case DISAS_JUMP:
13904 if (dc->base.singlestep_enabled) {
13905 gen_exception_internal(EXCP_DEBUG);
13906 } else {
13907 gen_step_complete_exception(dc);
13908 }
13909 break;
13910 case DISAS_NORETURN:
13911 break;
13912 }
13913 } else {
13914 switch (dc->base.is_jmp) {
13915 case DISAS_NEXT:
13916 case DISAS_TOO_MANY:
13917 gen_goto_tb(dc, 1, dc->pc);
13918 break;
13919 default:
13920 case DISAS_UPDATE:
13921 gen_a64_set_pc_im(dc->pc);
13922 /* fall through */
13923 case DISAS_EXIT:
13924 tcg_gen_exit_tb(NULL, 0);
13925 break;
13926 case DISAS_JUMP:
13927 tcg_gen_lookup_and_goto_ptr();
13928 break;
13929 case DISAS_NORETURN:
13930 case DISAS_SWI:
13931 break;
13932 case DISAS_WFE:
13933 gen_a64_set_pc_im(dc->pc);
13934 gen_helper_wfe(cpu_env);
13935 break;
13936 case DISAS_YIELD:
13937 gen_a64_set_pc_im(dc->pc);
13938 gen_helper_yield(cpu_env);
13939 break;
13940 case DISAS_WFI:
13941 {
13942 /* This is a special case because we don't want to just halt the CPU
13943 * if trying to debug across a WFI.
13944 */
13945 TCGv_i32 tmp = tcg_const_i32(4);
13946
13947 gen_a64_set_pc_im(dc->pc);
13948 gen_helper_wfi(cpu_env, tmp);
13949 tcg_temp_free_i32(tmp);
13950 /* The helper doesn't necessarily throw an exception, but we
13951 * must go back to the main loop to check for interrupts anyway.
13952 */
13953 tcg_gen_exit_tb(NULL, 0);
13954 break;
13955 }
13956 }
13957 }
13958
13959 /* Functions above can change dc->pc, so re-align db->pc_next */
13960 dc->base.pc_next = dc->pc;
13961 }
13962
13963 static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
13964 CPUState *cpu)
13965 {
13966 DisasContext *dc = container_of(dcbase, DisasContext, base);
13967
13968 qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
13969 log_target_disas(cpu, dc->base.pc_first, dc->base.tb->size);
13970 }
13971
13972 const TranslatorOps aarch64_translator_ops = {
13973 .init_disas_context = aarch64_tr_init_disas_context,
13974 .tb_start = aarch64_tr_tb_start,
13975 .insn_start = aarch64_tr_insn_start,
13976 .breakpoint_check = aarch64_tr_breakpoint_check,
13977 .translate_insn = aarch64_tr_translate_insn,
13978 .tb_stop = aarch64_tr_tb_stop,
13979 .disas_log = aarch64_tr_disas_log,
13980 };