4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx
);
128 static void reset_btype(DisasContext
*s
)
131 TCGv_i32 zero
= tcg_const_i32(0);
132 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
133 tcg_temp_free_i32(zero
);
138 static void set_btype(DisasContext
*s
, int val
)
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val
>= 1 && val
<= 3);
145 tcg_val
= tcg_const_i32(val
);
146 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
147 tcg_temp_free_i32(tcg_val
);
151 void gen_a64_set_pc_im(uint64_t val
)
153 tcg_gen_movi_i64(cpu_pc
, val
);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
183 TCGv_i64 tcg_zero
= tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
191 dst
, dst
, tcg_zero
, dst
, src
);
192 tcg_temp_free_i64(tcg_zero
);
197 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
207 * Return a "clean" address for ADDR according to TBID.
208 * This is always a fresh temporary, as we need to be able to
209 * increment this independently of a dirty write-back address.
211 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
213 TCGv_i64 clean
= new_tmp_a64(s
);
215 * In order to get the correct value in the FAR_ELx register,
216 * we must present the memory subsystem with the "dirty" address
217 * including the TBI. In system mode we can make this work via
218 * the TLB, dropping the TBI during translation. But for user-only
219 * mode we don't have that option, and must remove the top byte now.
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
224 tcg_gen_mov_i64(clean
, addr
);
229 typedef struct DisasCompare64
{
234 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
238 arm_test_cc(&c32
, cc
);
240 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
241 * properly. The NE/EQ comparisons are also fine with this choice. */
242 c64
->cond
= c32
.cond
;
243 c64
->value
= tcg_temp_new_i64();
244 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
249 static void a64_free_cc(DisasCompare64
*c64
)
251 tcg_temp_free_i64(c64
->value
);
254 static void gen_exception_internal(int excp
)
256 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
258 assert(excp_is_internal(excp
));
259 gen_helper_exception_internal(cpu_env
, tcg_excp
);
260 tcg_temp_free_i32(tcg_excp
);
263 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
265 gen_a64_set_pc_im(pc
);
266 gen_exception_internal(excp
);
267 s
->base
.is_jmp
= DISAS_NORETURN
;
270 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
271 uint32_t syndrome
, uint32_t target_el
)
273 gen_a64_set_pc_im(pc
);
274 gen_exception(excp
, syndrome
, target_el
);
275 s
->base
.is_jmp
= DISAS_NORETURN
;
278 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
282 gen_a64_set_pc_im(s
->pc_curr
);
283 tcg_syn
= tcg_const_i32(syndrome
);
284 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
285 tcg_temp_free_i32(tcg_syn
);
286 s
->base
.is_jmp
= DISAS_NORETURN
;
289 static void gen_step_complete_exception(DisasContext
*s
)
291 /* We just completed step of an insn. Move from Active-not-pending
292 * to Active-pending, and then also take the swstep exception.
293 * This corresponds to making the (IMPDEF) choice to prioritize
294 * swstep exceptions over asynchronous exceptions taken to an exception
295 * level where debug is disabled. This choice has the advantage that
296 * we do not need to maintain internal state corresponding to the
297 * ISV/EX syndrome bits between completion of the step and generation
298 * of the exception, and our syndrome information is always correct.
301 gen_swstep_exception(s
, 1, s
->is_ldex
);
302 s
->base
.is_jmp
= DISAS_NORETURN
;
305 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
307 /* No direct tb linking with singlestep (either QEMU's or the ARM
308 * debug architecture kind) or deterministic io
310 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
311 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
315 #ifndef CONFIG_USER_ONLY
316 /* Only link tbs from inside the same guest page */
317 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
325 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
327 TranslationBlock
*tb
;
330 if (use_goto_tb(s
, n
, dest
)) {
332 gen_a64_set_pc_im(dest
);
333 tcg_gen_exit_tb(tb
, n
);
334 s
->base
.is_jmp
= DISAS_NORETURN
;
336 gen_a64_set_pc_im(dest
);
338 gen_step_complete_exception(s
);
339 } else if (s
->base
.singlestep_enabled
) {
340 gen_exception_internal(EXCP_DEBUG
);
342 tcg_gen_lookup_and_goto_ptr();
343 s
->base
.is_jmp
= DISAS_NORETURN
;
348 void unallocated_encoding(DisasContext
*s
)
350 /* Unallocated and reserved encodings are uncategorized */
351 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
352 default_exception_el(s
));
355 static void init_tmp_a64_array(DisasContext
*s
)
357 #ifdef CONFIG_DEBUG_TCG
358 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
360 s
->tmp_a64_count
= 0;
363 static void free_tmp_a64(DisasContext
*s
)
366 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
367 tcg_temp_free_i64(s
->tmp_a64
[i
]);
369 init_tmp_a64_array(s
);
372 TCGv_i64
new_tmp_a64(DisasContext
*s
)
374 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
375 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
378 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
380 TCGv_i64 t
= new_tmp_a64(s
);
381 tcg_gen_movi_i64(t
, 0);
386 * Register access functions
388 * These functions are used for directly accessing a register in where
389 * changes to the final register value are likely to be made. If you
390 * need to use a register for temporary calculation (e.g. index type
391 * operations) use the read_* form.
393 * B1.2.1 Register mappings
395 * In instruction register encoding 31 can refer to ZR (zero register) or
396 * the SP (stack pointer) depending on context. In QEMU's case we map SP
397 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
398 * This is the point of the _sp forms.
400 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
403 return new_tmp_a64_zero(s
);
409 /* register access for when 31 == SP */
410 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
415 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
416 * representing the register contents. This TCGv is an auto-freed
417 * temporary so it need not be explicitly freed, and may be modified.
419 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
421 TCGv_i64 v
= new_tmp_a64(s
);
424 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
426 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
429 tcg_gen_movi_i64(v
, 0);
434 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
436 TCGv_i64 v
= new_tmp_a64(s
);
438 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
440 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
445 /* Return the offset into CPUARMState of a slice (from
446 * the least significant end) of FP register Qn (ie
448 * (Note that this is not the same mapping as for A32; see cpu.h)
450 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
452 return vec_reg_offset(s
, regno
, 0, size
);
455 /* Offset of the high half of the 128 bit vector Qn */
456 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
458 return vec_reg_offset(s
, regno
, 1, MO_64
);
461 /* Convenience accessors for reading and writing single and double
462 * FP registers. Writing clears the upper parts of the associated
463 * 128 bit vector register, as required by the architecture.
464 * Note that unlike the GP register accessors, the values returned
465 * by the read functions must be manually freed.
467 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
469 TCGv_i64 v
= tcg_temp_new_i64();
471 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
475 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
477 TCGv_i32 v
= tcg_temp_new_i32();
479 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
483 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
485 TCGv_i32 v
= tcg_temp_new_i32();
487 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
491 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
492 * If SVE is not enabled, then there are only 128 bits in the vector.
494 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
496 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
497 unsigned vsz
= vec_full_reg_size(s
);
499 /* Nop move, with side effect of clearing the tail. */
500 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
503 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
505 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
507 tcg_gen_st_i64(v
, cpu_env
, ofs
);
508 clear_vec_high(s
, false, reg
);
511 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
513 TCGv_i64 tmp
= tcg_temp_new_i64();
515 tcg_gen_extu_i32_i64(tmp
, v
);
516 write_fp_dreg(s
, reg
, tmp
);
517 tcg_temp_free_i64(tmp
);
520 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
522 TCGv_ptr statusptr
= tcg_temp_new_ptr();
525 /* In A64 all instructions (both FP and Neon) use the FPCR; there
526 * is no equivalent of the A32 Neon "standard FPSCR value".
527 * However half-precision operations operate under a different
528 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
531 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
533 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
535 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
539 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
540 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
541 GVecGen2Fn
*gvec_fn
, int vece
)
543 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
544 is_q
? 16 : 8, vec_full_reg_size(s
));
547 /* Expand a 2-operand + immediate AdvSIMD vector operation using
548 * an expander function.
550 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
551 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
553 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
554 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
557 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
558 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
559 GVecGen3Fn
*gvec_fn
, int vece
)
561 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
562 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
565 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
566 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
567 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
569 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
570 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
571 is_q
? 16 : 8, vec_full_reg_size(s
));
574 /* Expand a 2-operand operation using an out-of-line helper. */
575 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
576 int rn
, int data
, gen_helper_gvec_2
*fn
)
578 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
579 vec_full_reg_offset(s
, rn
),
580 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
583 /* Expand a 3-operand operation using an out-of-line helper. */
584 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
585 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
587 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
588 vec_full_reg_offset(s
, rn
),
589 vec_full_reg_offset(s
, rm
),
590 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
593 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
594 * an out-of-line helper.
596 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
597 int rm
, bool is_fp16
, int data
,
598 gen_helper_gvec_3_ptr
*fn
)
600 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
601 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
602 vec_full_reg_offset(s
, rn
),
603 vec_full_reg_offset(s
, rm
), fpst
,
604 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
605 tcg_temp_free_ptr(fpst
);
608 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
609 * than the 32 bit equivalent.
611 static inline void gen_set_NZ64(TCGv_i64 result
)
613 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
614 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
617 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
618 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
621 gen_set_NZ64(result
);
623 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
624 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
626 tcg_gen_movi_i32(cpu_CF
, 0);
627 tcg_gen_movi_i32(cpu_VF
, 0);
630 /* dest = T0 + T1; compute C, N, V and Z flags */
631 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
634 TCGv_i64 result
, flag
, tmp
;
635 result
= tcg_temp_new_i64();
636 flag
= tcg_temp_new_i64();
637 tmp
= tcg_temp_new_i64();
639 tcg_gen_movi_i64(tmp
, 0);
640 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
642 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
644 gen_set_NZ64(result
);
646 tcg_gen_xor_i64(flag
, result
, t0
);
647 tcg_gen_xor_i64(tmp
, t0
, t1
);
648 tcg_gen_andc_i64(flag
, flag
, tmp
);
649 tcg_temp_free_i64(tmp
);
650 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
652 tcg_gen_mov_i64(dest
, result
);
653 tcg_temp_free_i64(result
);
654 tcg_temp_free_i64(flag
);
656 /* 32 bit arithmetic */
657 TCGv_i32 t0_32
= tcg_temp_new_i32();
658 TCGv_i32 t1_32
= tcg_temp_new_i32();
659 TCGv_i32 tmp
= tcg_temp_new_i32();
661 tcg_gen_movi_i32(tmp
, 0);
662 tcg_gen_extrl_i64_i32(t0_32
, t0
);
663 tcg_gen_extrl_i64_i32(t1_32
, t1
);
664 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
665 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
666 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
667 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
668 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
669 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
671 tcg_temp_free_i32(tmp
);
672 tcg_temp_free_i32(t0_32
);
673 tcg_temp_free_i32(t1_32
);
677 /* dest = T0 - T1; compute C, N, V and Z flags */
678 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
681 /* 64 bit arithmetic */
682 TCGv_i64 result
, flag
, tmp
;
684 result
= tcg_temp_new_i64();
685 flag
= tcg_temp_new_i64();
686 tcg_gen_sub_i64(result
, t0
, t1
);
688 gen_set_NZ64(result
);
690 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
691 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
693 tcg_gen_xor_i64(flag
, result
, t0
);
694 tmp
= tcg_temp_new_i64();
695 tcg_gen_xor_i64(tmp
, t0
, t1
);
696 tcg_gen_and_i64(flag
, flag
, tmp
);
697 tcg_temp_free_i64(tmp
);
698 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
699 tcg_gen_mov_i64(dest
, result
);
700 tcg_temp_free_i64(flag
);
701 tcg_temp_free_i64(result
);
703 /* 32 bit arithmetic */
704 TCGv_i32 t0_32
= tcg_temp_new_i32();
705 TCGv_i32 t1_32
= tcg_temp_new_i32();
708 tcg_gen_extrl_i64_i32(t0_32
, t0
);
709 tcg_gen_extrl_i64_i32(t1_32
, t1
);
710 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
711 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
712 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
713 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
714 tmp
= tcg_temp_new_i32();
715 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
716 tcg_temp_free_i32(t0_32
);
717 tcg_temp_free_i32(t1_32
);
718 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
719 tcg_temp_free_i32(tmp
);
720 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
724 /* dest = T0 + T1 + CF; do not compute flags. */
725 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
727 TCGv_i64 flag
= tcg_temp_new_i64();
728 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
729 tcg_gen_add_i64(dest
, t0
, t1
);
730 tcg_gen_add_i64(dest
, dest
, flag
);
731 tcg_temp_free_i64(flag
);
734 tcg_gen_ext32u_i64(dest
, dest
);
738 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
739 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
742 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
743 result
= tcg_temp_new_i64();
744 cf_64
= tcg_temp_new_i64();
745 vf_64
= tcg_temp_new_i64();
746 tmp
= tcg_const_i64(0);
748 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
749 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
750 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
751 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
752 gen_set_NZ64(result
);
754 tcg_gen_xor_i64(vf_64
, result
, t0
);
755 tcg_gen_xor_i64(tmp
, t0
, t1
);
756 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
757 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
759 tcg_gen_mov_i64(dest
, result
);
761 tcg_temp_free_i64(tmp
);
762 tcg_temp_free_i64(vf_64
);
763 tcg_temp_free_i64(cf_64
);
764 tcg_temp_free_i64(result
);
766 TCGv_i32 t0_32
, t1_32
, tmp
;
767 t0_32
= tcg_temp_new_i32();
768 t1_32
= tcg_temp_new_i32();
769 tmp
= tcg_const_i32(0);
771 tcg_gen_extrl_i64_i32(t0_32
, t0
);
772 tcg_gen_extrl_i64_i32(t1_32
, t1
);
773 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
774 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
776 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
777 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
778 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
779 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
780 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
782 tcg_temp_free_i32(tmp
);
783 tcg_temp_free_i32(t1_32
);
784 tcg_temp_free_i32(t0_32
);
789 * Load/Store generators
793 * Store from GPR register to memory.
795 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
796 TCGv_i64 tcg_addr
, int size
, int memidx
,
798 unsigned int iss_srt
,
799 bool iss_sf
, bool iss_ar
)
802 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
807 syn
= syn_data_abort_with_iss(0,
813 0, 0, 0, 0, 0, false);
814 disas_set_insn_syndrome(s
, syn
);
818 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
819 TCGv_i64 tcg_addr
, int size
,
821 unsigned int iss_srt
,
822 bool iss_sf
, bool iss_ar
)
824 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
825 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
829 * Load from memory to GPR register
831 static void do_gpr_ld_memidx(DisasContext
*s
,
832 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
833 int size
, bool is_signed
,
834 bool extend
, int memidx
,
835 bool iss_valid
, unsigned int iss_srt
,
836 bool iss_sf
, bool iss_ar
)
838 MemOp memop
= s
->be_data
+ size
;
846 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
848 if (extend
&& is_signed
) {
850 tcg_gen_ext32u_i64(dest
, dest
);
856 syn
= syn_data_abort_with_iss(0,
862 0, 0, 0, 0, 0, false);
863 disas_set_insn_syndrome(s
, syn
);
867 static void do_gpr_ld(DisasContext
*s
,
868 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
869 int size
, bool is_signed
, bool extend
,
870 bool iss_valid
, unsigned int iss_srt
,
871 bool iss_sf
, bool iss_ar
)
873 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
875 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
879 * Store from FP register to memory
881 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
883 /* This writes the bottom N bits of a 128 bit wide vector to memory */
884 TCGv_i64 tmp
= tcg_temp_new_i64();
885 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
887 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
890 bool be
= s
->be_data
== MO_BE
;
891 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
893 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
894 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
896 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
897 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
899 tcg_temp_free_i64(tcg_hiaddr
);
902 tcg_temp_free_i64(tmp
);
906 * Load from memory to FP register
908 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
910 /* This always zero-extends and writes to a full 128 bit wide vector */
911 TCGv_i64 tmplo
= tcg_temp_new_i64();
912 TCGv_i64 tmphi
= NULL
;
915 MemOp memop
= s
->be_data
+ size
;
916 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
918 bool be
= s
->be_data
== MO_BE
;
921 tmphi
= tcg_temp_new_i64();
922 tcg_hiaddr
= tcg_temp_new_i64();
924 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
925 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
927 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
929 tcg_temp_free_i64(tcg_hiaddr
);
932 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
933 tcg_temp_free_i64(tmplo
);
936 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
937 tcg_temp_free_i64(tmphi
);
939 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
943 * Vector load/store helpers.
945 * The principal difference between this and a FP load is that we don't
946 * zero extend as we are filling a partial chunk of the vector register.
947 * These functions don't support 128 bit loads/stores, which would be
948 * normal load/store operations.
950 * The _i32 versions are useful when operating on 32 bit quantities
951 * (eg for floating point single or using Neon helper functions).
954 /* Get value of an element within a vector register */
955 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
956 int element
, MemOp memop
)
958 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
961 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
964 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
967 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
980 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
983 g_assert_not_reached();
987 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
988 int element
, MemOp memop
)
990 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
993 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
996 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
999 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1009 g_assert_not_reached();
1013 /* Set value of an element within a vector register */
1014 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1015 int element
, MemOp memop
)
1017 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1020 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1023 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1026 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1032 g_assert_not_reached();
1036 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1037 int destidx
, int element
, MemOp memop
)
1039 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1042 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1045 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1048 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1051 g_assert_not_reached();
1055 /* Store from vector register to memory */
1056 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1057 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1059 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1061 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1062 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1064 tcg_temp_free_i64(tcg_tmp
);
1067 /* Load from memory to vector register */
1068 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1069 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1071 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1073 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1074 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1076 tcg_temp_free_i64(tcg_tmp
);
1079 /* Check that FP/Neon access is enabled. If it is, return
1080 * true. If not, emit code to generate an appropriate exception,
1081 * and return false; the caller should not emit any code for
1082 * the instruction. Note that this check must happen after all
1083 * unallocated-encoding checks (otherwise the syndrome information
1084 * for the resulting exception will be incorrect).
1086 static inline bool fp_access_check(DisasContext
*s
)
1088 assert(!s
->fp_access_checked
);
1089 s
->fp_access_checked
= true;
1091 if (!s
->fp_excp_el
) {
1095 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1096 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1100 /* Check that SVE access is enabled. If it is, return true.
1101 * If not, emit code to generate an appropriate exception and return false.
1103 bool sve_access_check(DisasContext
*s
)
1105 if (s
->sve_excp_el
) {
1106 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1110 return fp_access_check(s
);
1114 * This utility function is for doing register extension with an
1115 * optional shift. You will likely want to pass a temporary for the
1116 * destination register. See DecodeRegExtend() in the ARM ARM.
1118 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1119 int option
, unsigned int shift
)
1121 int extsize
= extract32(option
, 0, 2);
1122 bool is_signed
= extract32(option
, 2, 1);
1127 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1130 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1133 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1142 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1145 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1157 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1161 static inline void gen_check_sp_alignment(DisasContext
*s
)
1163 /* The AArch64 architecture mandates that (if enabled via PSTATE
1164 * or SCTLR bits) there is a check that SP is 16-aligned on every
1165 * SP-relative load or store (with an exception generated if it is not).
1166 * In line with general QEMU practice regarding misaligned accesses,
1167 * we omit these checks for the sake of guest program performance.
1168 * This function is provided as a hook so we can more easily add these
1169 * checks in future (possibly as a "favour catching guest program bugs
1170 * over speed" user selectable option).
1175 * This provides a simple table based table lookup decoder. It is
1176 * intended to be used when the relevant bits for decode are too
1177 * awkwardly placed and switch/if based logic would be confusing and
1178 * deeply nested. Since it's a linear search through the table, tables
1179 * should be kept small.
1181 * It returns the first handler where insn & mask == pattern, or
1182 * NULL if there is no match.
1183 * The table is terminated by an empty mask (i.e. 0)
1185 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1188 const AArch64DecodeTable
*tptr
= table
;
1190 while (tptr
->mask
) {
1191 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1192 return tptr
->disas_fn
;
1200 * The instruction disassembly implemented here matches
1201 * the instruction encoding classifications in chapter C4
1202 * of the ARM Architecture Reference Manual (DDI0487B_a);
1203 * classification names and decode diagrams here should generally
1204 * match up with those in the manual.
1207 /* Unconditional branch (immediate)
1209 * +----+-----------+-------------------------------------+
1210 * | op | 0 0 1 0 1 | imm26 |
1211 * +----+-----------+-------------------------------------+
1213 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1215 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1217 if (insn
& (1U << 31)) {
1218 /* BL Branch with link */
1219 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1222 /* B Branch / BL Branch with link */
1224 gen_goto_tb(s
, 0, addr
);
1227 /* Compare and branch (immediate)
1228 * 31 30 25 24 23 5 4 0
1229 * +----+-------------+----+---------------------+--------+
1230 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1231 * +----+-------------+----+---------------------+--------+
1233 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1235 unsigned int sf
, op
, rt
;
1237 TCGLabel
*label_match
;
1240 sf
= extract32(insn
, 31, 1);
1241 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1242 rt
= extract32(insn
, 0, 5);
1243 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1245 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1246 label_match
= gen_new_label();
1249 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1250 tcg_cmp
, 0, label_match
);
1252 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1253 gen_set_label(label_match
);
1254 gen_goto_tb(s
, 1, addr
);
1257 /* Test and branch (immediate)
1258 * 31 30 25 24 23 19 18 5 4 0
1259 * +----+-------------+----+-------+-------------+------+
1260 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1261 * +----+-------------+----+-------+-------------+------+
1263 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1265 unsigned int bit_pos
, op
, rt
;
1267 TCGLabel
*label_match
;
1270 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1271 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1272 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1273 rt
= extract32(insn
, 0, 5);
1275 tcg_cmp
= tcg_temp_new_i64();
1276 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1277 label_match
= gen_new_label();
1280 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1281 tcg_cmp
, 0, label_match
);
1282 tcg_temp_free_i64(tcg_cmp
);
1283 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1284 gen_set_label(label_match
);
1285 gen_goto_tb(s
, 1, addr
);
1288 /* Conditional branch (immediate)
1289 * 31 25 24 23 5 4 3 0
1290 * +---------------+----+---------------------+----+------+
1291 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1292 * +---------------+----+---------------------+----+------+
1294 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1299 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1300 unallocated_encoding(s
);
1303 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1304 cond
= extract32(insn
, 0, 4);
1308 /* genuinely conditional branches */
1309 TCGLabel
*label_match
= gen_new_label();
1310 arm_gen_test_cc(cond
, label_match
);
1311 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1312 gen_set_label(label_match
);
1313 gen_goto_tb(s
, 1, addr
);
1315 /* 0xe and 0xf are both "always" conditions */
1316 gen_goto_tb(s
, 0, addr
);
1320 /* HINT instruction group, including various allocated HINTs */
1321 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1322 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1324 unsigned int selector
= crm
<< 3 | op2
;
1327 unallocated_encoding(s
);
1332 case 0b00000: /* NOP */
1334 case 0b00011: /* WFI */
1335 s
->base
.is_jmp
= DISAS_WFI
;
1337 case 0b00001: /* YIELD */
1338 /* When running in MTTCG we don't generate jumps to the yield and
1339 * WFE helpers as it won't affect the scheduling of other vCPUs.
1340 * If we wanted to more completely model WFE/SEV so we don't busy
1341 * spin unnecessarily we would need to do something more involved.
1343 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1344 s
->base
.is_jmp
= DISAS_YIELD
;
1347 case 0b00010: /* WFE */
1348 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1349 s
->base
.is_jmp
= DISAS_WFE
;
1352 case 0b00100: /* SEV */
1353 case 0b00101: /* SEVL */
1354 /* we treat all as NOP at least for now */
1356 case 0b00111: /* XPACLRI */
1357 if (s
->pauth_active
) {
1358 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1361 case 0b01000: /* PACIA1716 */
1362 if (s
->pauth_active
) {
1363 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1366 case 0b01010: /* PACIB1716 */
1367 if (s
->pauth_active
) {
1368 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1371 case 0b01100: /* AUTIA1716 */
1372 if (s
->pauth_active
) {
1373 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1376 case 0b01110: /* AUTIB1716 */
1377 if (s
->pauth_active
) {
1378 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1381 case 0b11000: /* PACIAZ */
1382 if (s
->pauth_active
) {
1383 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1384 new_tmp_a64_zero(s
));
1387 case 0b11001: /* PACIASP */
1388 if (s
->pauth_active
) {
1389 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1392 case 0b11010: /* PACIBZ */
1393 if (s
->pauth_active
) {
1394 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1395 new_tmp_a64_zero(s
));
1398 case 0b11011: /* PACIBSP */
1399 if (s
->pauth_active
) {
1400 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1403 case 0b11100: /* AUTIAZ */
1404 if (s
->pauth_active
) {
1405 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1406 new_tmp_a64_zero(s
));
1409 case 0b11101: /* AUTIASP */
1410 if (s
->pauth_active
) {
1411 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1414 case 0b11110: /* AUTIBZ */
1415 if (s
->pauth_active
) {
1416 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1417 new_tmp_a64_zero(s
));
1420 case 0b11111: /* AUTIBSP */
1421 if (s
->pauth_active
) {
1422 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1426 /* default specified as NOP equivalent */
1431 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1433 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1436 /* CLREX, DSB, DMB, ISB */
1437 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1438 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1443 unallocated_encoding(s
);
1454 case 1: /* MBReqTypes_Reads */
1455 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1457 case 2: /* MBReqTypes_Writes */
1458 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1460 default: /* MBReqTypes_All */
1461 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1467 /* We need to break the TB after this insn to execute
1468 * a self-modified code correctly and also to take
1469 * any pending interrupts immediately.
1472 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1476 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1477 goto do_unallocated
;
1480 * TODO: There is no speculation barrier opcode for TCG;
1481 * MB and end the TB instead.
1483 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1484 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1489 unallocated_encoding(s
);
1494 static void gen_xaflag(void)
1496 TCGv_i32 z
= tcg_temp_new_i32();
1498 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1507 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1508 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1511 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1512 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1514 /* (!C & Z) << 31 -> -(Z & ~C) */
1515 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1516 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1519 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1521 tcg_temp_free_i32(z
);
1524 static void gen_axflag(void)
1526 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1527 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1529 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1530 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1532 tcg_gen_movi_i32(cpu_NF
, 0);
1533 tcg_gen_movi_i32(cpu_VF
, 0);
1536 /* MSR (immediate) - move immediate to processor state field */
1537 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1538 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1541 int op
= op1
<< 3 | op2
;
1543 /* End the TB by default, chaining is ok. */
1544 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1547 case 0x00: /* CFINV */
1548 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1549 goto do_unallocated
;
1551 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1552 s
->base
.is_jmp
= DISAS_NEXT
;
1555 case 0x01: /* XAFlag */
1556 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1557 goto do_unallocated
;
1560 s
->base
.is_jmp
= DISAS_NEXT
;
1563 case 0x02: /* AXFlag */
1564 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1565 goto do_unallocated
;
1568 s
->base
.is_jmp
= DISAS_NEXT
;
1571 case 0x03: /* UAO */
1572 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1573 goto do_unallocated
;
1576 set_pstate_bits(PSTATE_UAO
);
1578 clear_pstate_bits(PSTATE_UAO
);
1580 t1
= tcg_const_i32(s
->current_el
);
1581 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1582 tcg_temp_free_i32(t1
);
1585 case 0x04: /* PAN */
1586 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1587 goto do_unallocated
;
1590 set_pstate_bits(PSTATE_PAN
);
1592 clear_pstate_bits(PSTATE_PAN
);
1594 t1
= tcg_const_i32(s
->current_el
);
1595 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1596 tcg_temp_free_i32(t1
);
1599 case 0x05: /* SPSel */
1600 if (s
->current_el
== 0) {
1601 goto do_unallocated
;
1603 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1604 gen_helper_msr_i_spsel(cpu_env
, t1
);
1605 tcg_temp_free_i32(t1
);
1608 case 0x1e: /* DAIFSet */
1609 t1
= tcg_const_i32(crm
);
1610 gen_helper_msr_i_daifset(cpu_env
, t1
);
1611 tcg_temp_free_i32(t1
);
1614 case 0x1f: /* DAIFClear */
1615 t1
= tcg_const_i32(crm
);
1616 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1617 tcg_temp_free_i32(t1
);
1618 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1619 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1622 case 0x1c: /* TCO */
1623 if (dc_isar_feature(aa64_mte
, s
)) {
1624 /* Full MTE is enabled -- set the TCO bit as directed. */
1626 set_pstate_bits(PSTATE_TCO
);
1628 clear_pstate_bits(PSTATE_TCO
);
1630 t1
= tcg_const_i32(s
->current_el
);
1631 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1632 tcg_temp_free_i32(t1
);
1633 /* Many factors, including TCO, go into MTE_ACTIVE. */
1634 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1635 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1636 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1637 s
->base
.is_jmp
= DISAS_NEXT
;
1639 goto do_unallocated
;
1645 unallocated_encoding(s
);
1650 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1652 TCGv_i32 tmp
= tcg_temp_new_i32();
1653 TCGv_i32 nzcv
= tcg_temp_new_i32();
1655 /* build bit 31, N */
1656 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1657 /* build bit 30, Z */
1658 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1659 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1660 /* build bit 29, C */
1661 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1662 /* build bit 28, V */
1663 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1664 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1665 /* generate result */
1666 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1668 tcg_temp_free_i32(nzcv
);
1669 tcg_temp_free_i32(tmp
);
1672 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1674 TCGv_i32 nzcv
= tcg_temp_new_i32();
1676 /* take NZCV from R[t] */
1677 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1680 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1682 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1683 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1685 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1686 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1688 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1689 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1690 tcg_temp_free_i32(nzcv
);
1693 /* MRS - move from system register
1694 * MSR (register) - move to system register
1697 * These are all essentially the same insn in 'read' and 'write'
1698 * versions, with varying op0 fields.
1700 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1701 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1702 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1704 const ARMCPRegInfo
*ri
;
1707 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1708 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1709 crn
, crm
, op0
, op1
, op2
));
1712 /* Unknown register; this might be a guest error or a QEMU
1713 * unimplemented feature.
1715 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1716 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1717 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1718 unallocated_encoding(s
);
1722 /* Check access permissions */
1723 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1724 unallocated_encoding(s
);
1729 /* Emit code to perform further access permissions checks at
1730 * runtime; this may result in an exception.
1733 TCGv_i32 tcg_syn
, tcg_isread
;
1736 gen_a64_set_pc_im(s
->pc_curr
);
1737 tmpptr
= tcg_const_ptr(ri
);
1738 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1739 tcg_syn
= tcg_const_i32(syndrome
);
1740 tcg_isread
= tcg_const_i32(isread
);
1741 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1742 tcg_temp_free_ptr(tmpptr
);
1743 tcg_temp_free_i32(tcg_syn
);
1744 tcg_temp_free_i32(tcg_isread
);
1745 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1747 * The readfn or writefn might raise an exception;
1748 * synchronize the CPU state in case it does.
1750 gen_a64_set_pc_im(s
->pc_curr
);
1753 /* Handle special cases first */
1754 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1758 tcg_rt
= cpu_reg(s
, rt
);
1760 gen_get_nzcv(tcg_rt
);
1762 gen_set_nzcv(tcg_rt
);
1765 case ARM_CP_CURRENTEL
:
1766 /* Reads as current EL value from pstate, which is
1767 * guaranteed to be constant by the tb flags.
1769 tcg_rt
= cpu_reg(s
, rt
);
1770 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1773 /* Writes clear the aligned block of memory which rt points into. */
1774 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1775 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1780 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1782 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1786 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1790 tcg_rt
= cpu_reg(s
, rt
);
1793 if (ri
->type
& ARM_CP_CONST
) {
1794 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1795 } else if (ri
->readfn
) {
1797 tmpptr
= tcg_const_ptr(ri
);
1798 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1799 tcg_temp_free_ptr(tmpptr
);
1801 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1804 if (ri
->type
& ARM_CP_CONST
) {
1805 /* If not forbidden by access permissions, treat as WI */
1807 } else if (ri
->writefn
) {
1809 tmpptr
= tcg_const_ptr(ri
);
1810 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1811 tcg_temp_free_ptr(tmpptr
);
1813 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1817 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1818 /* I/O operations must end the TB here (whether read or write) */
1819 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1821 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1823 * A write to any coprocessor regiser that ends a TB
1824 * must rebuild the hflags for the next TB.
1826 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1827 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1828 tcg_temp_free_i32(tcg_el
);
1830 * We default to ending the TB on a coprocessor register write,
1831 * but allow this to be suppressed by the register definition
1832 * (usually only necessary to work around guest bugs).
1834 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1839 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1840 * +---------------------+---+-----+-----+-------+-------+-----+------+
1841 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1842 * +---------------------+---+-----+-----+-------+-------+-----+------+
1844 static void disas_system(DisasContext
*s
, uint32_t insn
)
1846 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1847 l
= extract32(insn
, 21, 1);
1848 op0
= extract32(insn
, 19, 2);
1849 op1
= extract32(insn
, 16, 3);
1850 crn
= extract32(insn
, 12, 4);
1851 crm
= extract32(insn
, 8, 4);
1852 op2
= extract32(insn
, 5, 3);
1853 rt
= extract32(insn
, 0, 5);
1856 if (l
|| rt
!= 31) {
1857 unallocated_encoding(s
);
1861 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1862 handle_hint(s
, insn
, op1
, op2
, crm
);
1864 case 3: /* CLREX, DSB, DMB, ISB */
1865 handle_sync(s
, insn
, op1
, op2
, crm
);
1867 case 4: /* MSR (immediate) */
1868 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1871 unallocated_encoding(s
);
1876 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1879 /* Exception generation
1881 * 31 24 23 21 20 5 4 2 1 0
1882 * +-----------------+-----+------------------------+-----+----+
1883 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1884 * +-----------------------+------------------------+----------+
1886 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1888 int opc
= extract32(insn
, 21, 3);
1889 int op2_ll
= extract32(insn
, 0, 5);
1890 int imm16
= extract32(insn
, 5, 16);
1895 /* For SVC, HVC and SMC we advance the single-step state
1896 * machine before taking the exception. This is architecturally
1897 * mandated, to ensure that single-stepping a system call
1898 * instruction works properly.
1903 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1904 syn_aa64_svc(imm16
), default_exception_el(s
));
1907 if (s
->current_el
== 0) {
1908 unallocated_encoding(s
);
1911 /* The pre HVC helper handles cases when HVC gets trapped
1912 * as an undefined insn by runtime configuration.
1914 gen_a64_set_pc_im(s
->pc_curr
);
1915 gen_helper_pre_hvc(cpu_env
);
1917 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1918 syn_aa64_hvc(imm16
), 2);
1921 if (s
->current_el
== 0) {
1922 unallocated_encoding(s
);
1925 gen_a64_set_pc_im(s
->pc_curr
);
1926 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1927 gen_helper_pre_smc(cpu_env
, tmp
);
1928 tcg_temp_free_i32(tmp
);
1930 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1931 syn_aa64_smc(imm16
), 3);
1934 unallocated_encoding(s
);
1940 unallocated_encoding(s
);
1944 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1948 unallocated_encoding(s
);
1951 /* HLT. This has two purposes.
1952 * Architecturally, it is an external halting debug instruction.
1953 * Since QEMU doesn't implement external debug, we treat this as
1954 * it is required for halting debug disabled: it will UNDEF.
1955 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1957 if (semihosting_enabled() && imm16
== 0xf000) {
1958 #ifndef CONFIG_USER_ONLY
1959 /* In system mode, don't allow userspace access to semihosting,
1960 * to provide some semblance of security (and for consistency
1961 * with our 32-bit semihosting).
1963 if (s
->current_el
== 0) {
1964 unsupported_encoding(s
, insn
);
1968 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1970 unsupported_encoding(s
, insn
);
1974 if (op2_ll
< 1 || op2_ll
> 3) {
1975 unallocated_encoding(s
);
1978 /* DCPS1, DCPS2, DCPS3 */
1979 unsupported_encoding(s
, insn
);
1982 unallocated_encoding(s
);
1987 /* Unconditional branch (register)
1988 * 31 25 24 21 20 16 15 10 9 5 4 0
1989 * +---------------+-------+-------+-------+------+-------+
1990 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1991 * +---------------+-------+-------+-------+------+-------+
1993 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1995 unsigned int opc
, op2
, op3
, rn
, op4
;
1996 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2000 opc
= extract32(insn
, 21, 4);
2001 op2
= extract32(insn
, 16, 5);
2002 op3
= extract32(insn
, 10, 6);
2003 rn
= extract32(insn
, 5, 5);
2004 op4
= extract32(insn
, 0, 5);
2007 goto do_unallocated
;
2019 goto do_unallocated
;
2021 dst
= cpu_reg(s
, rn
);
2026 if (!dc_isar_feature(aa64_pauth
, s
)) {
2027 goto do_unallocated
;
2031 if (rn
!= 0x1f || op4
!= 0x1f) {
2032 goto do_unallocated
;
2035 modifier
= cpu_X
[31];
2037 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2039 goto do_unallocated
;
2041 modifier
= new_tmp_a64_zero(s
);
2043 if (s
->pauth_active
) {
2044 dst
= new_tmp_a64(s
);
2046 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2048 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2051 dst
= cpu_reg(s
, rn
);
2056 goto do_unallocated
;
2058 gen_a64_set_pc(s
, dst
);
2059 /* BLR also needs to load return address */
2061 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2067 if (!dc_isar_feature(aa64_pauth
, s
)) {
2068 goto do_unallocated
;
2070 if ((op3
& ~1) != 2) {
2071 goto do_unallocated
;
2073 btype_mod
= opc
& 1;
2074 if (s
->pauth_active
) {
2075 dst
= new_tmp_a64(s
);
2076 modifier
= cpu_reg_sp(s
, op4
);
2078 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2080 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2083 dst
= cpu_reg(s
, rn
);
2085 gen_a64_set_pc(s
, dst
);
2086 /* BLRAA also needs to load return address */
2088 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2093 if (s
->current_el
== 0) {
2094 goto do_unallocated
;
2099 goto do_unallocated
;
2101 dst
= tcg_temp_new_i64();
2102 tcg_gen_ld_i64(dst
, cpu_env
,
2103 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2106 case 2: /* ERETAA */
2107 case 3: /* ERETAB */
2108 if (!dc_isar_feature(aa64_pauth
, s
)) {
2109 goto do_unallocated
;
2111 if (rn
!= 0x1f || op4
!= 0x1f) {
2112 goto do_unallocated
;
2114 dst
= tcg_temp_new_i64();
2115 tcg_gen_ld_i64(dst
, cpu_env
,
2116 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2117 if (s
->pauth_active
) {
2118 modifier
= cpu_X
[31];
2120 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2122 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2128 goto do_unallocated
;
2130 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2134 gen_helper_exception_return(cpu_env
, dst
);
2135 tcg_temp_free_i64(dst
);
2136 /* Must exit loop to check un-masked IRQs */
2137 s
->base
.is_jmp
= DISAS_EXIT
;
2141 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2142 goto do_unallocated
;
2144 unsupported_encoding(s
, insn
);
2150 unallocated_encoding(s
);
2154 switch (btype_mod
) {
2156 if (dc_isar_feature(aa64_bti
, s
)) {
2157 /* BR to {x16,x17} or !guard -> 1, else 3. */
2158 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2163 if (dc_isar_feature(aa64_bti
, s
)) {
2164 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2169 default: /* RET or none of the above. */
2170 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2174 s
->base
.is_jmp
= DISAS_JUMP
;
2177 /* Branches, exception generating and system instructions */
2178 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2180 switch (extract32(insn
, 25, 7)) {
2181 case 0x0a: case 0x0b:
2182 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2183 disas_uncond_b_imm(s
, insn
);
2185 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2186 disas_comp_b_imm(s
, insn
);
2188 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2189 disas_test_b_imm(s
, insn
);
2191 case 0x2a: /* Conditional branch (immediate) */
2192 disas_cond_b_imm(s
, insn
);
2194 case 0x6a: /* Exception generation / System */
2195 if (insn
& (1 << 24)) {
2196 if (extract32(insn
, 22, 2) == 0) {
2197 disas_system(s
, insn
);
2199 unallocated_encoding(s
);
2205 case 0x6b: /* Unconditional branch (register) */
2206 disas_uncond_b_reg(s
, insn
);
2209 unallocated_encoding(s
);
2215 * Load/Store exclusive instructions are implemented by remembering
2216 * the value/address loaded, and seeing if these are the same
2217 * when the store is performed. This is not actually the architecturally
2218 * mandated semantics, but it works for typical guest code sequences
2219 * and avoids having to monitor regular stores.
2221 * The store exclusive uses the atomic cmpxchg primitives to avoid
2222 * races in multi-threaded linux-user and when MTTCG softmmu is
2225 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2226 TCGv_i64 addr
, int size
, bool is_pair
)
2228 int idx
= get_mem_index(s
);
2229 MemOp memop
= s
->be_data
;
2231 g_assert(size
<= 3);
2233 g_assert(size
>= 2);
2235 /* The pair must be single-copy atomic for the doubleword. */
2236 memop
|= MO_64
| MO_ALIGN
;
2237 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2238 if (s
->be_data
== MO_LE
) {
2239 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2240 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2242 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2243 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2246 /* The pair must be single-copy atomic for *each* doubleword, not
2247 the entire quadword, however it must be quadword aligned. */
2249 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2250 memop
| MO_ALIGN_16
);
2252 TCGv_i64 addr2
= tcg_temp_new_i64();
2253 tcg_gen_addi_i64(addr2
, addr
, 8);
2254 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2255 tcg_temp_free_i64(addr2
);
2257 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2258 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2261 memop
|= size
| MO_ALIGN
;
2262 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2263 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2265 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2268 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2269 TCGv_i64 addr
, int size
, int is_pair
)
2271 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2272 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2275 * [addr + datasize] = {Rt2};
2281 * env->exclusive_addr = -1;
2283 TCGLabel
*fail_label
= gen_new_label();
2284 TCGLabel
*done_label
= gen_new_label();
2287 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2289 tmp
= tcg_temp_new_i64();
2292 if (s
->be_data
== MO_LE
) {
2293 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2295 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2297 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2298 cpu_exclusive_val
, tmp
,
2300 MO_64
| MO_ALIGN
| s
->be_data
);
2301 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2302 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2303 if (!HAVE_CMPXCHG128
) {
2304 gen_helper_exit_atomic(cpu_env
);
2305 s
->base
.is_jmp
= DISAS_NORETURN
;
2306 } else if (s
->be_data
== MO_LE
) {
2307 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2312 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2317 } else if (s
->be_data
== MO_LE
) {
2318 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2319 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2321 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2322 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2325 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2326 cpu_reg(s
, rt
), get_mem_index(s
),
2327 size
| MO_ALIGN
| s
->be_data
);
2328 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2330 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2331 tcg_temp_free_i64(tmp
);
2332 tcg_gen_br(done_label
);
2334 gen_set_label(fail_label
);
2335 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2336 gen_set_label(done_label
);
2337 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2340 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2343 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2344 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2345 int memidx
= get_mem_index(s
);
2346 TCGv_i64 clean_addr
;
2349 gen_check_sp_alignment(s
);
2351 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2352 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2353 size
| MO_ALIGN
| s
->be_data
);
2356 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2359 TCGv_i64 s1
= cpu_reg(s
, rs
);
2360 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2361 TCGv_i64 t1
= cpu_reg(s
, rt
);
2362 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2363 TCGv_i64 clean_addr
;
2364 int memidx
= get_mem_index(s
);
2367 gen_check_sp_alignment(s
);
2369 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2372 TCGv_i64 cmp
= tcg_temp_new_i64();
2373 TCGv_i64 val
= tcg_temp_new_i64();
2375 if (s
->be_data
== MO_LE
) {
2376 tcg_gen_concat32_i64(val
, t1
, t2
);
2377 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2379 tcg_gen_concat32_i64(val
, t2
, t1
);
2380 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2383 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2384 MO_64
| MO_ALIGN
| s
->be_data
);
2385 tcg_temp_free_i64(val
);
2387 if (s
->be_data
== MO_LE
) {
2388 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2390 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2392 tcg_temp_free_i64(cmp
);
2393 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2394 if (HAVE_CMPXCHG128
) {
2395 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2396 if (s
->be_data
== MO_LE
) {
2397 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2398 clean_addr
, t1
, t2
);
2400 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2401 clean_addr
, t1
, t2
);
2403 tcg_temp_free_i32(tcg_rs
);
2405 gen_helper_exit_atomic(cpu_env
);
2406 s
->base
.is_jmp
= DISAS_NORETURN
;
2409 TCGv_i64 d1
= tcg_temp_new_i64();
2410 TCGv_i64 d2
= tcg_temp_new_i64();
2411 TCGv_i64 a2
= tcg_temp_new_i64();
2412 TCGv_i64 c1
= tcg_temp_new_i64();
2413 TCGv_i64 c2
= tcg_temp_new_i64();
2414 TCGv_i64 zero
= tcg_const_i64(0);
2416 /* Load the two words, in memory order. */
2417 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2418 MO_64
| MO_ALIGN_16
| s
->be_data
);
2419 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2420 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2422 /* Compare the two words, also in memory order. */
2423 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2424 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2425 tcg_gen_and_i64(c2
, c2
, c1
);
2427 /* If compare equal, write back new data, else write back old data. */
2428 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2429 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2430 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2431 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2432 tcg_temp_free_i64(a2
);
2433 tcg_temp_free_i64(c1
);
2434 tcg_temp_free_i64(c2
);
2435 tcg_temp_free_i64(zero
);
2437 /* Write back the data from memory to Rs. */
2438 tcg_gen_mov_i64(s1
, d1
);
2439 tcg_gen_mov_i64(s2
, d2
);
2440 tcg_temp_free_i64(d1
);
2441 tcg_temp_free_i64(d2
);
2445 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2446 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2448 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2450 int opc0
= extract32(opc
, 0, 1);
2454 regsize
= opc0
? 32 : 64;
2456 regsize
= size
== 3 ? 64 : 32;
2458 return regsize
== 64;
2461 /* Load/store exclusive
2463 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2464 * +-----+-------------+----+---+----+------+----+-------+------+------+
2465 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2466 * +-----+-------------+----+---+----+------+----+-------+------+------+
2468 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2469 * L: 0 -> store, 1 -> load
2470 * o2: 0 -> exclusive, 1 -> not
2471 * o1: 0 -> single register, 1 -> register pair
2472 * o0: 1 -> load-acquire/store-release, 0 -> not
2474 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2476 int rt
= extract32(insn
, 0, 5);
2477 int rn
= extract32(insn
, 5, 5);
2478 int rt2
= extract32(insn
, 10, 5);
2479 int rs
= extract32(insn
, 16, 5);
2480 int is_lasr
= extract32(insn
, 15, 1);
2481 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2482 int size
= extract32(insn
, 30, 2);
2483 TCGv_i64 clean_addr
;
2485 switch (o2_L_o1_o0
) {
2486 case 0x0: /* STXR */
2487 case 0x1: /* STLXR */
2489 gen_check_sp_alignment(s
);
2492 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2494 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2495 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2498 case 0x4: /* LDXR */
2499 case 0x5: /* LDAXR */
2501 gen_check_sp_alignment(s
);
2503 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2505 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2507 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2511 case 0x8: /* STLLR */
2512 if (!dc_isar_feature(aa64_lor
, s
)) {
2515 /* StoreLORelease is the same as Store-Release for QEMU. */
2517 case 0x9: /* STLR */
2518 /* Generate ISS for non-exclusive accesses including LASR. */
2520 gen_check_sp_alignment(s
);
2522 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2523 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2524 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2525 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2528 case 0xc: /* LDLAR */
2529 if (!dc_isar_feature(aa64_lor
, s
)) {
2532 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2534 case 0xd: /* LDAR */
2535 /* Generate ISS for non-exclusive accesses including LASR. */
2537 gen_check_sp_alignment(s
);
2539 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2540 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2541 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2542 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2545 case 0x2: case 0x3: /* CASP / STXP */
2546 if (size
& 2) { /* STXP / STLXP */
2548 gen_check_sp_alignment(s
);
2551 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2553 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2554 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2558 && ((rt
| rs
) & 1) == 0
2559 && dc_isar_feature(aa64_atomics
, s
)) {
2561 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2566 case 0x6: case 0x7: /* CASPA / LDXP */
2567 if (size
& 2) { /* LDXP / LDAXP */
2569 gen_check_sp_alignment(s
);
2571 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2573 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2575 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2580 && ((rt
| rs
) & 1) == 0
2581 && dc_isar_feature(aa64_atomics
, s
)) {
2582 /* CASPA / CASPAL */
2583 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2589 case 0xb: /* CASL */
2590 case 0xe: /* CASA */
2591 case 0xf: /* CASAL */
2592 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2593 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2598 unallocated_encoding(s
);
2602 * Load register (literal)
2604 * 31 30 29 27 26 25 24 23 5 4 0
2605 * +-----+-------+---+-----+-------------------+-------+
2606 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2607 * +-----+-------+---+-----+-------------------+-------+
2609 * V: 1 -> vector (simd/fp)
2610 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2611 * 10-> 32 bit signed, 11 -> prefetch
2612 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2614 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2616 int rt
= extract32(insn
, 0, 5);
2617 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2618 bool is_vector
= extract32(insn
, 26, 1);
2619 int opc
= extract32(insn
, 30, 2);
2620 bool is_signed
= false;
2622 TCGv_i64 tcg_rt
, clean_addr
;
2626 unallocated_encoding(s
);
2630 if (!fp_access_check(s
)) {
2635 /* PRFM (literal) : prefetch */
2638 size
= 2 + extract32(opc
, 0, 1);
2639 is_signed
= extract32(opc
, 1, 1);
2642 tcg_rt
= cpu_reg(s
, rt
);
2644 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2646 do_fp_ld(s
, rt
, clean_addr
, size
);
2648 /* Only unsigned 32bit loads target 32bit registers. */
2649 bool iss_sf
= opc
!= 0;
2651 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2652 true, rt
, iss_sf
, false);
2654 tcg_temp_free_i64(clean_addr
);
2658 * LDNP (Load Pair - non-temporal hint)
2659 * LDP (Load Pair - non vector)
2660 * LDPSW (Load Pair Signed Word - non vector)
2661 * STNP (Store Pair - non-temporal hint)
2662 * STP (Store Pair - non vector)
2663 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2664 * LDP (Load Pair of SIMD&FP)
2665 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2666 * STP (Store Pair of SIMD&FP)
2668 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2669 * +-----+-------+---+---+-------+---+-----------------------------+
2670 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2671 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2673 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2675 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2676 * V: 0 -> GPR, 1 -> Vector
2677 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2678 * 10 -> signed offset, 11 -> pre-index
2679 * L: 0 -> Store 1 -> Load
2681 * Rt, Rt2 = GPR or SIMD registers to be stored
2682 * Rn = general purpose register containing address
2683 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2685 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2687 int rt
= extract32(insn
, 0, 5);
2688 int rn
= extract32(insn
, 5, 5);
2689 int rt2
= extract32(insn
, 10, 5);
2690 uint64_t offset
= sextract64(insn
, 15, 7);
2691 int index
= extract32(insn
, 23, 2);
2692 bool is_vector
= extract32(insn
, 26, 1);
2693 bool is_load
= extract32(insn
, 22, 1);
2694 int opc
= extract32(insn
, 30, 2);
2696 bool is_signed
= false;
2697 bool postindex
= false;
2700 TCGv_i64 clean_addr
, dirty_addr
;
2705 unallocated_encoding(s
);
2712 size
= 2 + extract32(opc
, 1, 1);
2713 is_signed
= extract32(opc
, 0, 1);
2714 if (!is_load
&& is_signed
) {
2715 unallocated_encoding(s
);
2721 case 1: /* post-index */
2726 /* signed offset with "non-temporal" hint. Since we don't emulate
2727 * caches we don't care about hints to the cache system about
2728 * data access patterns, and handle this identically to plain
2732 /* There is no non-temporal-hint version of LDPSW */
2733 unallocated_encoding(s
);
2738 case 2: /* signed offset, rn not updated */
2741 case 3: /* pre-index */
2747 if (is_vector
&& !fp_access_check(s
)) {
2754 gen_check_sp_alignment(s
);
2757 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2759 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2761 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2765 do_fp_ld(s
, rt
, clean_addr
, size
);
2767 do_fp_st(s
, rt
, clean_addr
, size
);
2769 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2771 do_fp_ld(s
, rt2
, clean_addr
, size
);
2773 do_fp_st(s
, rt2
, clean_addr
, size
);
2776 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2777 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2780 TCGv_i64 tmp
= tcg_temp_new_i64();
2782 /* Do not modify tcg_rt before recognizing any exception
2783 * from the second load.
2785 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2786 false, 0, false, false);
2787 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2788 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2789 false, 0, false, false);
2791 tcg_gen_mov_i64(tcg_rt
, tmp
);
2792 tcg_temp_free_i64(tmp
);
2794 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2795 false, 0, false, false);
2796 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2797 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2798 false, 0, false, false);
2804 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2806 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2811 * Load/store (immediate post-indexed)
2812 * Load/store (immediate pre-indexed)
2813 * Load/store (unscaled immediate)
2815 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2816 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2817 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2818 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2820 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2822 * V = 0 -> non-vector
2823 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2824 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2826 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2832 int rn
= extract32(insn
, 5, 5);
2833 int imm9
= sextract32(insn
, 12, 9);
2834 int idx
= extract32(insn
, 10, 2);
2835 bool is_signed
= false;
2836 bool is_store
= false;
2837 bool is_extended
= false;
2838 bool is_unpriv
= (idx
== 2);
2839 bool iss_valid
= !is_vector
;
2843 TCGv_i64 clean_addr
, dirty_addr
;
2846 size
|= (opc
& 2) << 1;
2847 if (size
> 4 || is_unpriv
) {
2848 unallocated_encoding(s
);
2851 is_store
= ((opc
& 1) == 0);
2852 if (!fp_access_check(s
)) {
2856 if (size
== 3 && opc
== 2) {
2857 /* PRFM - prefetch */
2859 unallocated_encoding(s
);
2864 if (opc
== 3 && size
> 1) {
2865 unallocated_encoding(s
);
2868 is_store
= (opc
== 0);
2869 is_signed
= extract32(opc
, 1, 1);
2870 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2888 g_assert_not_reached();
2892 gen_check_sp_alignment(s
);
2895 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2897 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2899 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2903 do_fp_st(s
, rt
, clean_addr
, size
);
2905 do_fp_ld(s
, rt
, clean_addr
, size
);
2908 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2909 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2910 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2913 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2914 iss_valid
, rt
, iss_sf
, false);
2916 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2917 is_signed
, is_extended
, memidx
,
2918 iss_valid
, rt
, iss_sf
, false);
2923 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2925 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2927 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2932 * Load/store (register offset)
2934 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2935 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2936 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2937 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2940 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2941 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2943 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2944 * opc<0>: 0 -> store, 1 -> load
2945 * V: 1 -> vector/simd
2946 * opt: extend encoding (see DecodeRegExtend)
2947 * S: if S=1 then scale (essentially index by sizeof(size))
2948 * Rt: register to transfer into/out of
2949 * Rn: address register or SP for base
2950 * Rm: offset register or ZR for offset
2952 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2958 int rn
= extract32(insn
, 5, 5);
2959 int shift
= extract32(insn
, 12, 1);
2960 int rm
= extract32(insn
, 16, 5);
2961 int opt
= extract32(insn
, 13, 3);
2962 bool is_signed
= false;
2963 bool is_store
= false;
2964 bool is_extended
= false;
2966 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2968 if (extract32(opt
, 1, 1) == 0) {
2969 unallocated_encoding(s
);
2974 size
|= (opc
& 2) << 1;
2976 unallocated_encoding(s
);
2979 is_store
= !extract32(opc
, 0, 1);
2980 if (!fp_access_check(s
)) {
2984 if (size
== 3 && opc
== 2) {
2985 /* PRFM - prefetch */
2988 if (opc
== 3 && size
> 1) {
2989 unallocated_encoding(s
);
2992 is_store
= (opc
== 0);
2993 is_signed
= extract32(opc
, 1, 1);
2994 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2998 gen_check_sp_alignment(s
);
3000 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3002 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3003 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3005 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3006 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3010 do_fp_st(s
, rt
, clean_addr
, size
);
3012 do_fp_ld(s
, rt
, clean_addr
, size
);
3015 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3016 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3018 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3019 true, rt
, iss_sf
, false);
3021 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3022 is_signed
, is_extended
,
3023 true, rt
, iss_sf
, false);
3029 * Load/store (unsigned immediate)
3031 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3032 * +----+-------+---+-----+-----+------------+-------+------+
3033 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3034 * +----+-------+---+-----+-----+------------+-------+------+
3037 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3038 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3040 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3041 * opc<0>: 0 -> store, 1 -> load
3042 * Rn: base address register (inc SP)
3043 * Rt: target register
3045 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3051 int rn
= extract32(insn
, 5, 5);
3052 unsigned int imm12
= extract32(insn
, 10, 12);
3053 unsigned int offset
;
3055 TCGv_i64 clean_addr
, dirty_addr
;
3058 bool is_signed
= false;
3059 bool is_extended
= false;
3062 size
|= (opc
& 2) << 1;
3064 unallocated_encoding(s
);
3067 is_store
= !extract32(opc
, 0, 1);
3068 if (!fp_access_check(s
)) {
3072 if (size
== 3 && opc
== 2) {
3073 /* PRFM - prefetch */
3076 if (opc
== 3 && size
> 1) {
3077 unallocated_encoding(s
);
3080 is_store
= (opc
== 0);
3081 is_signed
= extract32(opc
, 1, 1);
3082 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3086 gen_check_sp_alignment(s
);
3088 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3089 offset
= imm12
<< size
;
3090 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3091 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3095 do_fp_st(s
, rt
, clean_addr
, size
);
3097 do_fp_ld(s
, rt
, clean_addr
, size
);
3100 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3101 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3103 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3104 true, rt
, iss_sf
, false);
3106 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3107 true, rt
, iss_sf
, false);
3112 /* Atomic memory operations
3114 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3115 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3116 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3117 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3119 * Rt: the result register
3120 * Rn: base address or SP
3121 * Rs: the source register for the operation
3122 * V: vector flag (always 0 as of v8.3)
3126 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3127 int size
, int rt
, bool is_vector
)
3129 int rs
= extract32(insn
, 16, 5);
3130 int rn
= extract32(insn
, 5, 5);
3131 int o3_opc
= extract32(insn
, 12, 4);
3132 bool r
= extract32(insn
, 22, 1);
3133 bool a
= extract32(insn
, 23, 1);
3134 TCGv_i64 tcg_rs
, clean_addr
;
3135 AtomicThreeOpFn
*fn
;
3137 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3138 unallocated_encoding(s
);
3142 case 000: /* LDADD */
3143 fn
= tcg_gen_atomic_fetch_add_i64
;
3145 case 001: /* LDCLR */
3146 fn
= tcg_gen_atomic_fetch_and_i64
;
3148 case 002: /* LDEOR */
3149 fn
= tcg_gen_atomic_fetch_xor_i64
;
3151 case 003: /* LDSET */
3152 fn
= tcg_gen_atomic_fetch_or_i64
;
3154 case 004: /* LDSMAX */
3155 fn
= tcg_gen_atomic_fetch_smax_i64
;
3157 case 005: /* LDSMIN */
3158 fn
= tcg_gen_atomic_fetch_smin_i64
;
3160 case 006: /* LDUMAX */
3161 fn
= tcg_gen_atomic_fetch_umax_i64
;
3163 case 007: /* LDUMIN */
3164 fn
= tcg_gen_atomic_fetch_umin_i64
;
3167 fn
= tcg_gen_atomic_xchg_i64
;
3169 case 014: /* LDAPR, LDAPRH, LDAPRB */
3170 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3171 rs
!= 31 || a
!= 1 || r
!= 0) {
3172 unallocated_encoding(s
);
3177 unallocated_encoding(s
);
3182 gen_check_sp_alignment(s
);
3184 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3186 if (o3_opc
== 014) {
3188 * LDAPR* are a special case because they are a simple load, not a
3189 * fetch-and-do-something op.
3190 * The architectural consistency requirements here are weaker than
3191 * full load-acquire (we only need "load-acquire processor consistent"),
3192 * but we choose to implement them as full LDAQ.
3194 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3195 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3196 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3200 tcg_rs
= read_cpu_reg(s
, rs
, true);
3202 if (o3_opc
== 1) { /* LDCLR */
3203 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3206 /* The tcg atomic primitives are all full barriers. Therefore we
3207 * can ignore the Acquire and Release bits of this instruction.
3209 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3210 s
->be_data
| size
| MO_ALIGN
);
3214 * PAC memory operations
3216 * 31 30 27 26 24 22 21 12 11 10 5 0
3217 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3218 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3219 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3221 * Rt: the result register
3222 * Rn: base address or SP
3223 * V: vector flag (always 0 as of v8.3)
3224 * M: clear for key DA, set for key DB
3225 * W: pre-indexing flag
3228 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3229 int size
, int rt
, bool is_vector
)
3231 int rn
= extract32(insn
, 5, 5);
3232 bool is_wback
= extract32(insn
, 11, 1);
3233 bool use_key_a
= !extract32(insn
, 23, 1);
3235 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3237 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3238 unallocated_encoding(s
);
3243 gen_check_sp_alignment(s
);
3245 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3247 if (s
->pauth_active
) {
3249 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3251 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3255 /* Form the 10-bit signed, scaled offset. */
3256 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3257 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3258 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3260 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3261 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3263 tcg_rt
= cpu_reg(s
, rt
);
3264 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3265 /* extend */ false, /* iss_valid */ !is_wback
,
3266 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3269 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3274 * LDAPR/STLR (unscaled immediate)
3276 * 31 30 24 22 21 12 10 5 0
3277 * +------+-------------+-----+---+--------+-----+----+-----+
3278 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3279 * +------+-------------+-----+---+--------+-----+----+-----+
3281 * Rt: source or destination register
3283 * imm9: unscaled immediate offset
3284 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3285 * size: size of load/store
3287 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3289 int rt
= extract32(insn
, 0, 5);
3290 int rn
= extract32(insn
, 5, 5);
3291 int offset
= sextract32(insn
, 12, 9);
3292 int opc
= extract32(insn
, 22, 2);
3293 int size
= extract32(insn
, 30, 2);
3294 TCGv_i64 clean_addr
, dirty_addr
;
3295 bool is_store
= false;
3296 bool is_signed
= false;
3297 bool extend
= false;
3300 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3301 unallocated_encoding(s
);
3306 case 0: /* STLURB */
3309 case 1: /* LDAPUR* */
3311 case 2: /* LDAPURS* 64-bit variant */
3313 unallocated_encoding(s
);
3318 case 3: /* LDAPURS* 32-bit variant */
3320 unallocated_encoding(s
);
3324 extend
= true; /* zero-extend 32->64 after signed load */
3327 g_assert_not_reached();
3330 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3333 gen_check_sp_alignment(s
);
3336 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3337 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3338 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3341 /* Store-Release semantics */
3342 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3343 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3346 * Load-AcquirePC semantics; we implement as the slightly more
3347 * restrictive Load-Acquire.
3349 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3350 true, rt
, iss_sf
, true);
3351 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3355 /* Load/store register (all forms) */
3356 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3358 int rt
= extract32(insn
, 0, 5);
3359 int opc
= extract32(insn
, 22, 2);
3360 bool is_vector
= extract32(insn
, 26, 1);
3361 int size
= extract32(insn
, 30, 2);
3363 switch (extract32(insn
, 24, 2)) {
3365 if (extract32(insn
, 21, 1) == 0) {
3366 /* Load/store register (unscaled immediate)
3367 * Load/store immediate pre/post-indexed
3368 * Load/store register unprivileged
3370 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3373 switch (extract32(insn
, 10, 2)) {
3375 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3378 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3381 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3386 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3389 unallocated_encoding(s
);
3392 /* AdvSIMD load/store multiple structures
3394 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3395 * +---+---+---------------+---+-------------+--------+------+------+------+
3396 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3397 * +---+---+---------------+---+-------------+--------+------+------+------+
3399 * AdvSIMD load/store multiple structures (post-indexed)
3401 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3402 * +---+---+---------------+---+---+---------+--------+------+------+------+
3403 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3404 * +---+---+---------------+---+---+---------+--------+------+------+------+
3406 * Rt: first (or only) SIMD&FP register to be transferred
3407 * Rn: base address or SP
3408 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3410 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3412 int rt
= extract32(insn
, 0, 5);
3413 int rn
= extract32(insn
, 5, 5);
3414 int rm
= extract32(insn
, 16, 5);
3415 int size
= extract32(insn
, 10, 2);
3416 int opcode
= extract32(insn
, 12, 4);
3417 bool is_store
= !extract32(insn
, 22, 1);
3418 bool is_postidx
= extract32(insn
, 23, 1);
3419 bool is_q
= extract32(insn
, 30, 1);
3420 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3421 MemOp endian
= s
->be_data
;
3423 int ebytes
; /* bytes per element */
3424 int elements
; /* elements per vector */
3425 int rpt
; /* num iterations */
3426 int selem
; /* structure elements */
3429 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3430 unallocated_encoding(s
);
3434 if (!is_postidx
&& rm
!= 0) {
3435 unallocated_encoding(s
);
3439 /* From the shared decode logic */
3470 unallocated_encoding(s
);
3474 if (size
== 3 && !is_q
&& selem
!= 1) {
3476 unallocated_encoding(s
);
3480 if (!fp_access_check(s
)) {
3485 gen_check_sp_alignment(s
);
3488 /* For our purposes, bytes are always little-endian. */
3493 /* Consecutive little-endian elements from a single register
3494 * can be promoted to a larger little-endian operation.
3496 if (selem
== 1 && endian
== MO_LE
) {
3500 elements
= (is_q
? 16 : 8) / ebytes
;
3502 tcg_rn
= cpu_reg_sp(s
, rn
);
3503 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3504 tcg_ebytes
= tcg_const_i64(ebytes
);
3506 for (r
= 0; r
< rpt
; r
++) {
3508 for (e
= 0; e
< elements
; e
++) {
3510 for (xs
= 0; xs
< selem
; xs
++) {
3511 int tt
= (rt
+ r
+ xs
) % 32;
3513 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3515 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3517 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3521 tcg_temp_free_i64(tcg_ebytes
);
3524 /* For non-quad operations, setting a slice of the low
3525 * 64 bits of the register clears the high 64 bits (in
3526 * the ARM ARM pseudocode this is implicit in the fact
3527 * that 'rval' is a 64 bit wide variable).
3528 * For quad operations, we might still need to zero the
3531 for (r
= 0; r
< rpt
* selem
; r
++) {
3532 int tt
= (rt
+ r
) % 32;
3533 clear_vec_high(s
, is_q
, tt
);
3539 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3541 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3546 /* AdvSIMD load/store single structure
3548 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3549 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3550 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3551 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3553 * AdvSIMD load/store single structure (post-indexed)
3555 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3556 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3557 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3558 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3560 * Rt: first (or only) SIMD&FP register to be transferred
3561 * Rn: base address or SP
3562 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3563 * index = encoded in Q:S:size dependent on size
3565 * lane_size = encoded in R, opc
3566 * transfer width = encoded in opc, S, size
3568 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3570 int rt
= extract32(insn
, 0, 5);
3571 int rn
= extract32(insn
, 5, 5);
3572 int rm
= extract32(insn
, 16, 5);
3573 int size
= extract32(insn
, 10, 2);
3574 int S
= extract32(insn
, 12, 1);
3575 int opc
= extract32(insn
, 13, 3);
3576 int R
= extract32(insn
, 21, 1);
3577 int is_load
= extract32(insn
, 22, 1);
3578 int is_postidx
= extract32(insn
, 23, 1);
3579 int is_q
= extract32(insn
, 30, 1);
3581 int scale
= extract32(opc
, 1, 2);
3582 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3583 bool replicate
= false;
3584 int index
= is_q
<< 3 | S
<< 2 | size
;
3586 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3588 if (extract32(insn
, 31, 1)) {
3589 unallocated_encoding(s
);
3592 if (!is_postidx
&& rm
!= 0) {
3593 unallocated_encoding(s
);
3599 if (!is_load
|| S
) {
3600 unallocated_encoding(s
);
3609 if (extract32(size
, 0, 1)) {
3610 unallocated_encoding(s
);
3616 if (extract32(size
, 1, 1)) {
3617 unallocated_encoding(s
);
3620 if (!extract32(size
, 0, 1)) {
3624 unallocated_encoding(s
);
3632 g_assert_not_reached();
3635 if (!fp_access_check(s
)) {
3639 ebytes
= 1 << scale
;
3642 gen_check_sp_alignment(s
);
3645 tcg_rn
= cpu_reg_sp(s
, rn
);
3646 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3647 tcg_ebytes
= tcg_const_i64(ebytes
);
3649 for (xs
= 0; xs
< selem
; xs
++) {
3651 /* Load and replicate to all elements */
3652 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3654 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3655 get_mem_index(s
), s
->be_data
+ scale
);
3656 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3657 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3659 tcg_temp_free_i64(tcg_tmp
);
3661 /* Load/store one element per register */
3663 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3665 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3668 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3671 tcg_temp_free_i64(tcg_ebytes
);
3675 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3677 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3682 /* Loads and stores */
3683 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3685 switch (extract32(insn
, 24, 6)) {
3686 case 0x08: /* Load/store exclusive */
3687 disas_ldst_excl(s
, insn
);
3689 case 0x18: case 0x1c: /* Load register (literal) */
3690 disas_ld_lit(s
, insn
);
3692 case 0x28: case 0x29:
3693 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3694 disas_ldst_pair(s
, insn
);
3696 case 0x38: case 0x39:
3697 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3698 disas_ldst_reg(s
, insn
);
3700 case 0x0c: /* AdvSIMD load/store multiple structures */
3701 disas_ldst_multiple_struct(s
, insn
);
3703 case 0x0d: /* AdvSIMD load/store single structure */
3704 disas_ldst_single_struct(s
, insn
);
3706 case 0x19: /* LDAPR/STLR (unscaled immediate) */
3707 if (extract32(insn
, 10, 2) != 0 ||
3708 extract32(insn
, 21, 1) != 0) {
3709 unallocated_encoding(s
);
3712 disas_ldst_ldapr_stlr(s
, insn
);
3715 unallocated_encoding(s
);
3720 /* PC-rel. addressing
3721 * 31 30 29 28 24 23 5 4 0
3722 * +----+-------+-----------+-------------------+------+
3723 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3724 * +----+-------+-----------+-------------------+------+
3726 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3728 unsigned int page
, rd
;
3732 page
= extract32(insn
, 31, 1);
3733 /* SignExtend(immhi:immlo) -> offset */
3734 offset
= sextract64(insn
, 5, 19);
3735 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3736 rd
= extract32(insn
, 0, 5);
3740 /* ADRP (page based) */
3745 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3749 * Add/subtract (immediate)
3751 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3752 * +--+--+--+-----------+-----+-------------+-----+-----+
3753 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3754 * +--+--+--+-----------+-----+-------------+-----+-----+
3756 * sf: 0 -> 32bit, 1 -> 64bit
3757 * op: 0 -> add , 1 -> sub
3759 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3761 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3763 int rd
= extract32(insn
, 0, 5);
3764 int rn
= extract32(insn
, 5, 5);
3765 uint64_t imm
= extract32(insn
, 10, 12);
3766 int shift
= extract32(insn
, 22, 2);
3767 bool setflags
= extract32(insn
, 29, 1);
3768 bool sub_op
= extract32(insn
, 30, 1);
3769 bool is_64bit
= extract32(insn
, 31, 1);
3771 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3772 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3773 TCGv_i64 tcg_result
;
3782 unallocated_encoding(s
);
3786 tcg_result
= tcg_temp_new_i64();
3789 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3791 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3794 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3796 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3798 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3800 tcg_temp_free_i64(tcg_imm
);
3804 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3806 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3809 tcg_temp_free_i64(tcg_result
);
3812 /* The input should be a value in the bottom e bits (with higher
3813 * bits zero); returns that value replicated into every element
3814 * of size e in a 64 bit integer.
3816 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3826 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3827 static inline uint64_t bitmask64(unsigned int length
)
3829 assert(length
> 0 && length
<= 64);
3830 return ~0ULL >> (64 - length
);
3833 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3834 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3835 * value (ie should cause a guest UNDEF exception), and true if they are
3836 * valid, in which case the decoded bit pattern is written to result.
3838 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3839 unsigned int imms
, unsigned int immr
)
3842 unsigned e
, levels
, s
, r
;
3845 assert(immn
< 2 && imms
< 64 && immr
< 64);
3847 /* The bit patterns we create here are 64 bit patterns which
3848 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3849 * 64 bits each. Each element contains the same value: a run
3850 * of between 1 and e-1 non-zero bits, rotated within the
3851 * element by between 0 and e-1 bits.
3853 * The element size and run length are encoded into immn (1 bit)
3854 * and imms (6 bits) as follows:
3855 * 64 bit elements: immn = 1, imms = <length of run - 1>
3856 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3857 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3858 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3859 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3860 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3861 * Notice that immn = 0, imms = 11111x is the only combination
3862 * not covered by one of the above options; this is reserved.
3863 * Further, <length of run - 1> all-ones is a reserved pattern.
3865 * In all cases the rotation is by immr % e (and immr is 6 bits).
3868 /* First determine the element size */
3869 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3871 /* This is the immn == 0, imms == 0x11111x case */
3881 /* <length of run - 1> mustn't be all-ones. */
3885 /* Create the value of one element: s+1 set bits rotated
3886 * by r within the element (which is e bits wide)...
3888 mask
= bitmask64(s
+ 1);
3890 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3891 mask
&= bitmask64(e
);
3893 /* ...then replicate the element over the whole 64 bit value */
3894 mask
= bitfield_replicate(mask
, e
);
3899 /* Logical (immediate)
3900 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3901 * +----+-----+-------------+---+------+------+------+------+
3902 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3903 * +----+-----+-------------+---+------+------+------+------+
3905 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3907 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3908 TCGv_i64 tcg_rd
, tcg_rn
;
3910 bool is_and
= false;
3912 sf
= extract32(insn
, 31, 1);
3913 opc
= extract32(insn
, 29, 2);
3914 is_n
= extract32(insn
, 22, 1);
3915 immr
= extract32(insn
, 16, 6);
3916 imms
= extract32(insn
, 10, 6);
3917 rn
= extract32(insn
, 5, 5);
3918 rd
= extract32(insn
, 0, 5);
3921 unallocated_encoding(s
);
3925 if (opc
== 0x3) { /* ANDS */
3926 tcg_rd
= cpu_reg(s
, rd
);
3928 tcg_rd
= cpu_reg_sp(s
, rd
);
3930 tcg_rn
= cpu_reg(s
, rn
);
3932 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3933 /* some immediate field values are reserved */
3934 unallocated_encoding(s
);
3939 wmask
&= 0xffffffff;
3943 case 0x3: /* ANDS */
3945 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3949 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3952 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3955 assert(FALSE
); /* must handle all above */
3959 if (!sf
&& !is_and
) {
3960 /* zero extend final result; we know we can skip this for AND
3961 * since the immediate had the high 32 bits clear.
3963 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3966 if (opc
== 3) { /* ANDS */
3967 gen_logic_CC(sf
, tcg_rd
);
3972 * Move wide (immediate)
3974 * 31 30 29 28 23 22 21 20 5 4 0
3975 * +--+-----+-------------+-----+----------------+------+
3976 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3977 * +--+-----+-------------+-----+----------------+------+
3979 * sf: 0 -> 32 bit, 1 -> 64 bit
3980 * opc: 00 -> N, 10 -> Z, 11 -> K
3981 * hw: shift/16 (0,16, and sf only 32, 48)
3983 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3985 int rd
= extract32(insn
, 0, 5);
3986 uint64_t imm
= extract32(insn
, 5, 16);
3987 int sf
= extract32(insn
, 31, 1);
3988 int opc
= extract32(insn
, 29, 2);
3989 int pos
= extract32(insn
, 21, 2) << 4;
3990 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3993 if (!sf
&& (pos
>= 32)) {
3994 unallocated_encoding(s
);
4008 tcg_gen_movi_i64(tcg_rd
, imm
);
4011 tcg_imm
= tcg_const_i64(imm
);
4012 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4013 tcg_temp_free_i64(tcg_imm
);
4015 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4019 unallocated_encoding(s
);
4025 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4026 * +----+-----+-------------+---+------+------+------+------+
4027 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4028 * +----+-----+-------------+---+------+------+------+------+
4030 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4032 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4033 TCGv_i64 tcg_rd
, tcg_tmp
;
4035 sf
= extract32(insn
, 31, 1);
4036 opc
= extract32(insn
, 29, 2);
4037 n
= extract32(insn
, 22, 1);
4038 ri
= extract32(insn
, 16, 6);
4039 si
= extract32(insn
, 10, 6);
4040 rn
= extract32(insn
, 5, 5);
4041 rd
= extract32(insn
, 0, 5);
4042 bitsize
= sf
? 64 : 32;
4044 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4045 unallocated_encoding(s
);
4049 tcg_rd
= cpu_reg(s
, rd
);
4051 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4052 to be smaller than bitsize, we'll never reference data outside the
4053 low 32-bits anyway. */
4054 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4056 /* Recognize simple(r) extractions. */
4058 /* Wd<s-r:0> = Wn<s:r> */
4059 len
= (si
- ri
) + 1;
4060 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4061 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4063 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4064 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4067 /* opc == 1, BFXIL fall through to deposit */
4068 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4071 /* Handle the ri > si case with a deposit
4072 * Wd<32+s-r,32-r> = Wn<s:0>
4075 pos
= (bitsize
- ri
) & (bitsize
- 1);
4078 if (opc
== 0 && len
< ri
) {
4079 /* SBFM: sign extend the destination field from len to fill
4080 the balance of the word. Let the deposit below insert all
4081 of those sign bits. */
4082 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4086 if (opc
== 1) { /* BFM, BFXIL */
4087 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4089 /* SBFM or UBFM: We start with zero, and we haven't modified
4090 any bits outside bitsize, therefore the zero-extension
4091 below is unneeded. */
4092 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4097 if (!sf
) { /* zero extend final result */
4098 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4103 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4104 * +----+------+-------------+---+----+------+--------+------+------+
4105 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4106 * +----+------+-------------+---+----+------+--------+------+------+
4108 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4110 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4112 sf
= extract32(insn
, 31, 1);
4113 n
= extract32(insn
, 22, 1);
4114 rm
= extract32(insn
, 16, 5);
4115 imm
= extract32(insn
, 10, 6);
4116 rn
= extract32(insn
, 5, 5);
4117 rd
= extract32(insn
, 0, 5);
4118 op21
= extract32(insn
, 29, 2);
4119 op0
= extract32(insn
, 21, 1);
4120 bitsize
= sf
? 64 : 32;
4122 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4123 unallocated_encoding(s
);
4125 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4127 tcg_rd
= cpu_reg(s
, rd
);
4129 if (unlikely(imm
== 0)) {
4130 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4131 * so an extract from bit 0 is a special case.
4134 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4136 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4139 tcg_rm
= cpu_reg(s
, rm
);
4140 tcg_rn
= cpu_reg(s
, rn
);
4143 /* Specialization to ROR happens in EXTRACT2. */
4144 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4146 TCGv_i32 t0
= tcg_temp_new_i32();
4148 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4150 tcg_gen_rotri_i32(t0
, t0
, imm
);
4152 TCGv_i32 t1
= tcg_temp_new_i32();
4153 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4154 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4155 tcg_temp_free_i32(t1
);
4157 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4158 tcg_temp_free_i32(t0
);
4164 /* Data processing - immediate */
4165 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4167 switch (extract32(insn
, 23, 6)) {
4168 case 0x20: case 0x21: /* PC-rel. addressing */
4169 disas_pc_rel_adr(s
, insn
);
4171 case 0x22: case 0x23: /* Add/subtract (immediate) */
4172 disas_add_sub_imm(s
, insn
);
4174 case 0x24: /* Logical (immediate) */
4175 disas_logic_imm(s
, insn
);
4177 case 0x25: /* Move wide (immediate) */
4178 disas_movw_imm(s
, insn
);
4180 case 0x26: /* Bitfield */
4181 disas_bitfield(s
, insn
);
4183 case 0x27: /* Extract */
4184 disas_extract(s
, insn
);
4187 unallocated_encoding(s
);
4192 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4193 * Note that it is the caller's responsibility to ensure that the
4194 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4195 * mandated semantics for out of range shifts.
4197 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4198 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4200 switch (shift_type
) {
4201 case A64_SHIFT_TYPE_LSL
:
4202 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4204 case A64_SHIFT_TYPE_LSR
:
4205 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4207 case A64_SHIFT_TYPE_ASR
:
4209 tcg_gen_ext32s_i64(dst
, src
);
4211 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4213 case A64_SHIFT_TYPE_ROR
:
4215 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4218 t0
= tcg_temp_new_i32();
4219 t1
= tcg_temp_new_i32();
4220 tcg_gen_extrl_i64_i32(t0
, src
);
4221 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4222 tcg_gen_rotr_i32(t0
, t0
, t1
);
4223 tcg_gen_extu_i32_i64(dst
, t0
);
4224 tcg_temp_free_i32(t0
);
4225 tcg_temp_free_i32(t1
);
4229 assert(FALSE
); /* all shift types should be handled */
4233 if (!sf
) { /* zero extend final result */
4234 tcg_gen_ext32u_i64(dst
, dst
);
4238 /* Shift a TCGv src by immediate, put result in dst.
4239 * The shift amount must be in range (this should always be true as the
4240 * relevant instructions will UNDEF on bad shift immediates).
4242 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4243 enum a64_shift_type shift_type
, unsigned int shift_i
)
4245 assert(shift_i
< (sf
? 64 : 32));
4248 tcg_gen_mov_i64(dst
, src
);
4250 TCGv_i64 shift_const
;
4252 shift_const
= tcg_const_i64(shift_i
);
4253 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4254 tcg_temp_free_i64(shift_const
);
4258 /* Logical (shifted register)
4259 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4260 * +----+-----+-----------+-------+---+------+--------+------+------+
4261 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4262 * +----+-----+-----------+-------+---+------+--------+------+------+
4264 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4266 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4267 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4269 sf
= extract32(insn
, 31, 1);
4270 opc
= extract32(insn
, 29, 2);
4271 shift_type
= extract32(insn
, 22, 2);
4272 invert
= extract32(insn
, 21, 1);
4273 rm
= extract32(insn
, 16, 5);
4274 shift_amount
= extract32(insn
, 10, 6);
4275 rn
= extract32(insn
, 5, 5);
4276 rd
= extract32(insn
, 0, 5);
4278 if (!sf
&& (shift_amount
& (1 << 5))) {
4279 unallocated_encoding(s
);
4283 tcg_rd
= cpu_reg(s
, rd
);
4285 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4286 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4287 * register-register MOV and MVN, so it is worth special casing.
4289 tcg_rm
= cpu_reg(s
, rm
);
4291 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4293 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4297 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4299 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4305 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4308 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4311 tcg_rn
= cpu_reg(s
, rn
);
4313 switch (opc
| (invert
<< 2)) {
4316 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4319 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4322 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4326 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4329 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4332 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4340 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4344 gen_logic_CC(sf
, tcg_rd
);
4349 * Add/subtract (extended register)
4351 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4352 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4353 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4354 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4356 * sf: 0 -> 32bit, 1 -> 64bit
4357 * op: 0 -> add , 1 -> sub
4360 * option: extension type (see DecodeRegExtend)
4361 * imm3: optional shift to Rm
4363 * Rd = Rn + LSL(extend(Rm), amount)
4365 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4367 int rd
= extract32(insn
, 0, 5);
4368 int rn
= extract32(insn
, 5, 5);
4369 int imm3
= extract32(insn
, 10, 3);
4370 int option
= extract32(insn
, 13, 3);
4371 int rm
= extract32(insn
, 16, 5);
4372 int opt
= extract32(insn
, 22, 2);
4373 bool setflags
= extract32(insn
, 29, 1);
4374 bool sub_op
= extract32(insn
, 30, 1);
4375 bool sf
= extract32(insn
, 31, 1);
4377 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4379 TCGv_i64 tcg_result
;
4381 if (imm3
> 4 || opt
!= 0) {
4382 unallocated_encoding(s
);
4386 /* non-flag setting ops may use SP */
4388 tcg_rd
= cpu_reg_sp(s
, rd
);
4390 tcg_rd
= cpu_reg(s
, rd
);
4392 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4394 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4395 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4397 tcg_result
= tcg_temp_new_i64();
4401 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4403 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4407 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4409 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4414 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4416 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4419 tcg_temp_free_i64(tcg_result
);
4423 * Add/subtract (shifted register)
4425 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4426 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4427 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4428 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4430 * sf: 0 -> 32bit, 1 -> 64bit
4431 * op: 0 -> add , 1 -> sub
4433 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4434 * imm6: Shift amount to apply to Rm before the add/sub
4436 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4438 int rd
= extract32(insn
, 0, 5);
4439 int rn
= extract32(insn
, 5, 5);
4440 int imm6
= extract32(insn
, 10, 6);
4441 int rm
= extract32(insn
, 16, 5);
4442 int shift_type
= extract32(insn
, 22, 2);
4443 bool setflags
= extract32(insn
, 29, 1);
4444 bool sub_op
= extract32(insn
, 30, 1);
4445 bool sf
= extract32(insn
, 31, 1);
4447 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4448 TCGv_i64 tcg_rn
, tcg_rm
;
4449 TCGv_i64 tcg_result
;
4451 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4452 unallocated_encoding(s
);
4456 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4457 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4459 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4461 tcg_result
= tcg_temp_new_i64();
4465 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4467 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4471 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4473 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4478 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4480 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4483 tcg_temp_free_i64(tcg_result
);
4486 /* Data-processing (3 source)
4488 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4489 * +--+------+-----------+------+------+----+------+------+------+
4490 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4491 * +--+------+-----------+------+------+----+------+------+------+
4493 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4495 int rd
= extract32(insn
, 0, 5);
4496 int rn
= extract32(insn
, 5, 5);
4497 int ra
= extract32(insn
, 10, 5);
4498 int rm
= extract32(insn
, 16, 5);
4499 int op_id
= (extract32(insn
, 29, 3) << 4) |
4500 (extract32(insn
, 21, 3) << 1) |
4501 extract32(insn
, 15, 1);
4502 bool sf
= extract32(insn
, 31, 1);
4503 bool is_sub
= extract32(op_id
, 0, 1);
4504 bool is_high
= extract32(op_id
, 2, 1);
4505 bool is_signed
= false;
4510 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4512 case 0x42: /* SMADDL */
4513 case 0x43: /* SMSUBL */
4514 case 0x44: /* SMULH */
4517 case 0x0: /* MADD (32bit) */
4518 case 0x1: /* MSUB (32bit) */
4519 case 0x40: /* MADD (64bit) */
4520 case 0x41: /* MSUB (64bit) */
4521 case 0x4a: /* UMADDL */
4522 case 0x4b: /* UMSUBL */
4523 case 0x4c: /* UMULH */
4526 unallocated_encoding(s
);
4531 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4532 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4533 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4534 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4537 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4539 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4542 tcg_temp_free_i64(low_bits
);
4546 tcg_op1
= tcg_temp_new_i64();
4547 tcg_op2
= tcg_temp_new_i64();
4548 tcg_tmp
= tcg_temp_new_i64();
4551 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4552 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4555 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4556 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4558 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4559 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4563 if (ra
== 31 && !is_sub
) {
4564 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4565 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4567 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4569 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4571 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4576 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4579 tcg_temp_free_i64(tcg_op1
);
4580 tcg_temp_free_i64(tcg_op2
);
4581 tcg_temp_free_i64(tcg_tmp
);
4584 /* Add/subtract (with carry)
4585 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4586 * +--+--+--+------------------------+------+-------------+------+-----+
4587 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4588 * +--+--+--+------------------------+------+-------------+------+-----+
4591 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4593 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4594 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4596 sf
= extract32(insn
, 31, 1);
4597 op
= extract32(insn
, 30, 1);
4598 setflags
= extract32(insn
, 29, 1);
4599 rm
= extract32(insn
, 16, 5);
4600 rn
= extract32(insn
, 5, 5);
4601 rd
= extract32(insn
, 0, 5);
4603 tcg_rd
= cpu_reg(s
, rd
);
4604 tcg_rn
= cpu_reg(s
, rn
);
4607 tcg_y
= new_tmp_a64(s
);
4608 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4610 tcg_y
= cpu_reg(s
, rm
);
4614 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4616 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4621 * Rotate right into flags
4622 * 31 30 29 21 15 10 5 4 0
4623 * +--+--+--+-----------------+--------+-----------+------+--+------+
4624 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4625 * +--+--+--+-----------------+--------+-----------+------+--+------+
4627 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4629 int mask
= extract32(insn
, 0, 4);
4630 int o2
= extract32(insn
, 4, 1);
4631 int rn
= extract32(insn
, 5, 5);
4632 int imm6
= extract32(insn
, 15, 6);
4633 int sf_op_s
= extract32(insn
, 29, 3);
4637 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4638 unallocated_encoding(s
);
4642 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4643 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4645 nzcv
= tcg_temp_new_i32();
4646 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4648 if (mask
& 8) { /* N */
4649 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4651 if (mask
& 4) { /* Z */
4652 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4653 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4655 if (mask
& 2) { /* C */
4656 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4658 if (mask
& 1) { /* V */
4659 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4662 tcg_temp_free_i32(nzcv
);
4666 * Evaluate into flags
4667 * 31 30 29 21 15 14 10 5 4 0
4668 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4669 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4670 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4672 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4674 int o3_mask
= extract32(insn
, 0, 5);
4675 int rn
= extract32(insn
, 5, 5);
4676 int o2
= extract32(insn
, 15, 6);
4677 int sz
= extract32(insn
, 14, 1);
4678 int sf_op_s
= extract32(insn
, 29, 3);
4682 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4683 !dc_isar_feature(aa64_condm_4
, s
)) {
4684 unallocated_encoding(s
);
4687 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4689 tmp
= tcg_temp_new_i32();
4690 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4691 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4692 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4693 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4694 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4695 tcg_temp_free_i32(tmp
);
4698 /* Conditional compare (immediate / register)
4699 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4700 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4701 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4702 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4705 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4707 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4708 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4709 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4712 if (!extract32(insn
, 29, 1)) {
4713 unallocated_encoding(s
);
4716 if (insn
& (1 << 10 | 1 << 4)) {
4717 unallocated_encoding(s
);
4720 sf
= extract32(insn
, 31, 1);
4721 op
= extract32(insn
, 30, 1);
4722 is_imm
= extract32(insn
, 11, 1);
4723 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4724 cond
= extract32(insn
, 12, 4);
4725 rn
= extract32(insn
, 5, 5);
4726 nzcv
= extract32(insn
, 0, 4);
4728 /* Set T0 = !COND. */
4729 tcg_t0
= tcg_temp_new_i32();
4730 arm_test_cc(&c
, cond
);
4731 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4734 /* Load the arguments for the new comparison. */
4736 tcg_y
= new_tmp_a64(s
);
4737 tcg_gen_movi_i64(tcg_y
, y
);
4739 tcg_y
= cpu_reg(s
, y
);
4741 tcg_rn
= cpu_reg(s
, rn
);
4743 /* Set the flags for the new comparison. */
4744 tcg_tmp
= tcg_temp_new_i64();
4746 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4748 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4750 tcg_temp_free_i64(tcg_tmp
);
4752 /* If COND was false, force the flags to #nzcv. Compute two masks
4753 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4754 * For tcg hosts that support ANDC, we can make do with just T1.
4755 * In either case, allow the tcg optimizer to delete any unused mask.
4757 tcg_t1
= tcg_temp_new_i32();
4758 tcg_t2
= tcg_temp_new_i32();
4759 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4760 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4762 if (nzcv
& 8) { /* N */
4763 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4765 if (TCG_TARGET_HAS_andc_i32
) {
4766 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4768 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4771 if (nzcv
& 4) { /* Z */
4772 if (TCG_TARGET_HAS_andc_i32
) {
4773 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4775 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4778 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4780 if (nzcv
& 2) { /* C */
4781 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4783 if (TCG_TARGET_HAS_andc_i32
) {
4784 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4786 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4789 if (nzcv
& 1) { /* V */
4790 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4792 if (TCG_TARGET_HAS_andc_i32
) {
4793 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4795 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4798 tcg_temp_free_i32(tcg_t0
);
4799 tcg_temp_free_i32(tcg_t1
);
4800 tcg_temp_free_i32(tcg_t2
);
4803 /* Conditional select
4804 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4805 * +----+----+---+-----------------+------+------+-----+------+------+
4806 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4807 * +----+----+---+-----------------+------+------+-----+------+------+
4809 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4811 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4812 TCGv_i64 tcg_rd
, zero
;
4815 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4816 /* S == 1 or op2<1> == 1 */
4817 unallocated_encoding(s
);
4820 sf
= extract32(insn
, 31, 1);
4821 else_inv
= extract32(insn
, 30, 1);
4822 rm
= extract32(insn
, 16, 5);
4823 cond
= extract32(insn
, 12, 4);
4824 else_inc
= extract32(insn
, 10, 1);
4825 rn
= extract32(insn
, 5, 5);
4826 rd
= extract32(insn
, 0, 5);
4828 tcg_rd
= cpu_reg(s
, rd
);
4830 a64_test_cc(&c
, cond
);
4831 zero
= tcg_const_i64(0);
4833 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4835 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4837 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4840 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4841 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4842 if (else_inv
&& else_inc
) {
4843 tcg_gen_neg_i64(t_false
, t_false
);
4844 } else if (else_inv
) {
4845 tcg_gen_not_i64(t_false
, t_false
);
4846 } else if (else_inc
) {
4847 tcg_gen_addi_i64(t_false
, t_false
, 1);
4849 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4852 tcg_temp_free_i64(zero
);
4856 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4860 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4861 unsigned int rn
, unsigned int rd
)
4863 TCGv_i64 tcg_rd
, tcg_rn
;
4864 tcg_rd
= cpu_reg(s
, rd
);
4865 tcg_rn
= cpu_reg(s
, rn
);
4868 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4870 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4871 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4872 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4873 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4874 tcg_temp_free_i32(tcg_tmp32
);
4878 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4879 unsigned int rn
, unsigned int rd
)
4881 TCGv_i64 tcg_rd
, tcg_rn
;
4882 tcg_rd
= cpu_reg(s
, rd
);
4883 tcg_rn
= cpu_reg(s
, rn
);
4886 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4888 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4889 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4890 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4891 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4892 tcg_temp_free_i32(tcg_tmp32
);
4896 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4897 unsigned int rn
, unsigned int rd
)
4899 TCGv_i64 tcg_rd
, tcg_rn
;
4900 tcg_rd
= cpu_reg(s
, rd
);
4901 tcg_rn
= cpu_reg(s
, rn
);
4904 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4906 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4907 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4908 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4909 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4910 tcg_temp_free_i32(tcg_tmp32
);
4914 /* REV with sf==1, opcode==3 ("REV64") */
4915 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4916 unsigned int rn
, unsigned int rd
)
4919 unallocated_encoding(s
);
4922 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4925 /* REV with sf==0, opcode==2
4926 * REV32 (sf==1, opcode==2)
4928 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4929 unsigned int rn
, unsigned int rd
)
4931 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4934 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4935 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4937 /* bswap32_i64 requires zero high word */
4938 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4939 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4940 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4941 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4942 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4944 tcg_temp_free_i64(tcg_tmp
);
4946 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4947 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4951 /* REV16 (opcode==1) */
4952 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4953 unsigned int rn
, unsigned int rd
)
4955 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4956 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4957 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4958 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4960 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4961 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4962 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4963 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4964 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4966 tcg_temp_free_i64(mask
);
4967 tcg_temp_free_i64(tcg_tmp
);
4970 /* Data-processing (1 source)
4971 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4972 * +----+---+---+-----------------+---------+--------+------+------+
4973 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4974 * +----+---+---+-----------------+---------+--------+------+------+
4976 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4978 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4981 if (extract32(insn
, 29, 1)) {
4982 unallocated_encoding(s
);
4986 sf
= extract32(insn
, 31, 1);
4987 opcode
= extract32(insn
, 10, 6);
4988 opcode2
= extract32(insn
, 16, 5);
4989 rn
= extract32(insn
, 5, 5);
4990 rd
= extract32(insn
, 0, 5);
4992 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4994 switch (MAP(sf
, opcode2
, opcode
)) {
4995 case MAP(0, 0x00, 0x00): /* RBIT */
4996 case MAP(1, 0x00, 0x00):
4997 handle_rbit(s
, sf
, rn
, rd
);
4999 case MAP(0, 0x00, 0x01): /* REV16 */
5000 case MAP(1, 0x00, 0x01):
5001 handle_rev16(s
, sf
, rn
, rd
);
5003 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5004 case MAP(1, 0x00, 0x02):
5005 handle_rev32(s
, sf
, rn
, rd
);
5007 case MAP(1, 0x00, 0x03): /* REV64 */
5008 handle_rev64(s
, sf
, rn
, rd
);
5010 case MAP(0, 0x00, 0x04): /* CLZ */
5011 case MAP(1, 0x00, 0x04):
5012 handle_clz(s
, sf
, rn
, rd
);
5014 case MAP(0, 0x00, 0x05): /* CLS */
5015 case MAP(1, 0x00, 0x05):
5016 handle_cls(s
, sf
, rn
, rd
);
5018 case MAP(1, 0x01, 0x00): /* PACIA */
5019 if (s
->pauth_active
) {
5020 tcg_rd
= cpu_reg(s
, rd
);
5021 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5022 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5023 goto do_unallocated
;
5026 case MAP(1, 0x01, 0x01): /* PACIB */
5027 if (s
->pauth_active
) {
5028 tcg_rd
= cpu_reg(s
, rd
);
5029 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5030 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5031 goto do_unallocated
;
5034 case MAP(1, 0x01, 0x02): /* PACDA */
5035 if (s
->pauth_active
) {
5036 tcg_rd
= cpu_reg(s
, rd
);
5037 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5038 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5039 goto do_unallocated
;
5042 case MAP(1, 0x01, 0x03): /* PACDB */
5043 if (s
->pauth_active
) {
5044 tcg_rd
= cpu_reg(s
, rd
);
5045 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5046 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5047 goto do_unallocated
;
5050 case MAP(1, 0x01, 0x04): /* AUTIA */
5051 if (s
->pauth_active
) {
5052 tcg_rd
= cpu_reg(s
, rd
);
5053 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5054 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5055 goto do_unallocated
;
5058 case MAP(1, 0x01, 0x05): /* AUTIB */
5059 if (s
->pauth_active
) {
5060 tcg_rd
= cpu_reg(s
, rd
);
5061 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5062 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5063 goto do_unallocated
;
5066 case MAP(1, 0x01, 0x06): /* AUTDA */
5067 if (s
->pauth_active
) {
5068 tcg_rd
= cpu_reg(s
, rd
);
5069 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5070 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5071 goto do_unallocated
;
5074 case MAP(1, 0x01, 0x07): /* AUTDB */
5075 if (s
->pauth_active
) {
5076 tcg_rd
= cpu_reg(s
, rd
);
5077 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5078 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5079 goto do_unallocated
;
5082 case MAP(1, 0x01, 0x08): /* PACIZA */
5083 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5084 goto do_unallocated
;
5085 } else if (s
->pauth_active
) {
5086 tcg_rd
= cpu_reg(s
, rd
);
5087 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5090 case MAP(1, 0x01, 0x09): /* PACIZB */
5091 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5092 goto do_unallocated
;
5093 } else if (s
->pauth_active
) {
5094 tcg_rd
= cpu_reg(s
, rd
);
5095 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5098 case MAP(1, 0x01, 0x0a): /* PACDZA */
5099 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5100 goto do_unallocated
;
5101 } else if (s
->pauth_active
) {
5102 tcg_rd
= cpu_reg(s
, rd
);
5103 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5106 case MAP(1, 0x01, 0x0b): /* PACDZB */
5107 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5108 goto do_unallocated
;
5109 } else if (s
->pauth_active
) {
5110 tcg_rd
= cpu_reg(s
, rd
);
5111 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5114 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5115 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5116 goto do_unallocated
;
5117 } else if (s
->pauth_active
) {
5118 tcg_rd
= cpu_reg(s
, rd
);
5119 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5122 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5123 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5124 goto do_unallocated
;
5125 } else if (s
->pauth_active
) {
5126 tcg_rd
= cpu_reg(s
, rd
);
5127 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5130 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5131 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5132 goto do_unallocated
;
5133 } else if (s
->pauth_active
) {
5134 tcg_rd
= cpu_reg(s
, rd
);
5135 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5138 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5139 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5140 goto do_unallocated
;
5141 } else if (s
->pauth_active
) {
5142 tcg_rd
= cpu_reg(s
, rd
);
5143 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5146 case MAP(1, 0x01, 0x10): /* XPACI */
5147 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5148 goto do_unallocated
;
5149 } else if (s
->pauth_active
) {
5150 tcg_rd
= cpu_reg(s
, rd
);
5151 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5154 case MAP(1, 0x01, 0x11): /* XPACD */
5155 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5156 goto do_unallocated
;
5157 } else if (s
->pauth_active
) {
5158 tcg_rd
= cpu_reg(s
, rd
);
5159 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5164 unallocated_encoding(s
);
5171 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5172 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5174 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5175 tcg_rd
= cpu_reg(s
, rd
);
5177 if (!sf
&& is_signed
) {
5178 tcg_n
= new_tmp_a64(s
);
5179 tcg_m
= new_tmp_a64(s
);
5180 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5181 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5183 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5184 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5188 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5190 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5193 if (!sf
) { /* zero extend final result */
5194 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5198 /* LSLV, LSRV, ASRV, RORV */
5199 static void handle_shift_reg(DisasContext
*s
,
5200 enum a64_shift_type shift_type
, unsigned int sf
,
5201 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5203 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5204 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5205 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5207 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5208 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5209 tcg_temp_free_i64(tcg_shift
);
5212 /* CRC32[BHWX], CRC32C[BHWX] */
5213 static void handle_crc32(DisasContext
*s
,
5214 unsigned int sf
, unsigned int sz
, bool crc32c
,
5215 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5217 TCGv_i64 tcg_acc
, tcg_val
;
5220 if (!dc_isar_feature(aa64_crc32
, s
)
5221 || (sf
== 1 && sz
!= 3)
5222 || (sf
== 0 && sz
== 3)) {
5223 unallocated_encoding(s
);
5228 tcg_val
= cpu_reg(s
, rm
);
5242 g_assert_not_reached();
5244 tcg_val
= new_tmp_a64(s
);
5245 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5248 tcg_acc
= cpu_reg(s
, rn
);
5249 tcg_bytes
= tcg_const_i32(1 << sz
);
5252 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5254 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5257 tcg_temp_free_i32(tcg_bytes
);
5260 /* Data-processing (2 source)
5261 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5262 * +----+---+---+-----------------+------+--------+------+------+
5263 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5264 * +----+---+---+-----------------+------+--------+------+------+
5266 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5268 unsigned int sf
, rm
, opcode
, rn
, rd
;
5269 sf
= extract32(insn
, 31, 1);
5270 rm
= extract32(insn
, 16, 5);
5271 opcode
= extract32(insn
, 10, 6);
5272 rn
= extract32(insn
, 5, 5);
5273 rd
= extract32(insn
, 0, 5);
5275 if (extract32(insn
, 29, 1)) {
5276 unallocated_encoding(s
);
5282 handle_div(s
, false, sf
, rm
, rn
, rd
);
5285 handle_div(s
, true, sf
, rm
, rn
, rd
);
5288 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5291 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5294 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5297 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5299 case 12: /* PACGA */
5300 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5301 goto do_unallocated
;
5303 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5304 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5313 case 23: /* CRC32 */
5315 int sz
= extract32(opcode
, 0, 2);
5316 bool crc32c
= extract32(opcode
, 2, 1);
5317 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5322 unallocated_encoding(s
);
5328 * Data processing - register
5329 * 31 30 29 28 25 21 20 16 10 0
5330 * +--+---+--+---+-------+-----+-------+-------+---------+
5331 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5332 * +--+---+--+---+-------+-----+-------+-------+---------+
5334 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5336 int op0
= extract32(insn
, 30, 1);
5337 int op1
= extract32(insn
, 28, 1);
5338 int op2
= extract32(insn
, 21, 4);
5339 int op3
= extract32(insn
, 10, 6);
5344 /* Add/sub (extended register) */
5345 disas_add_sub_ext_reg(s
, insn
);
5347 /* Add/sub (shifted register) */
5348 disas_add_sub_reg(s
, insn
);
5351 /* Logical (shifted register) */
5352 disas_logic_reg(s
, insn
);
5360 case 0x00: /* Add/subtract (with carry) */
5361 disas_adc_sbc(s
, insn
);
5364 case 0x01: /* Rotate right into flags */
5366 disas_rotate_right_into_flags(s
, insn
);
5369 case 0x02: /* Evaluate into flags */
5373 disas_evaluate_into_flags(s
, insn
);
5377 goto do_unallocated
;
5381 case 0x2: /* Conditional compare */
5382 disas_cc(s
, insn
); /* both imm and reg forms */
5385 case 0x4: /* Conditional select */
5386 disas_cond_select(s
, insn
);
5389 case 0x6: /* Data-processing */
5390 if (op0
) { /* (1 source) */
5391 disas_data_proc_1src(s
, insn
);
5392 } else { /* (2 source) */
5393 disas_data_proc_2src(s
, insn
);
5396 case 0x8 ... 0xf: /* (3 source) */
5397 disas_data_proc_3src(s
, insn
);
5402 unallocated_encoding(s
);
5407 static void handle_fp_compare(DisasContext
*s
, int size
,
5408 unsigned int rn
, unsigned int rm
,
5409 bool cmp_with_zero
, bool signal_all_nans
)
5411 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5412 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5414 if (size
== MO_64
) {
5415 TCGv_i64 tcg_vn
, tcg_vm
;
5417 tcg_vn
= read_fp_dreg(s
, rn
);
5418 if (cmp_with_zero
) {
5419 tcg_vm
= tcg_const_i64(0);
5421 tcg_vm
= read_fp_dreg(s
, rm
);
5423 if (signal_all_nans
) {
5424 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5426 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5428 tcg_temp_free_i64(tcg_vn
);
5429 tcg_temp_free_i64(tcg_vm
);
5431 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5432 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5434 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5435 if (cmp_with_zero
) {
5436 tcg_gen_movi_i32(tcg_vm
, 0);
5438 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5443 if (signal_all_nans
) {
5444 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5446 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5450 if (signal_all_nans
) {
5451 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5453 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5457 g_assert_not_reached();
5460 tcg_temp_free_i32(tcg_vn
);
5461 tcg_temp_free_i32(tcg_vm
);
5464 tcg_temp_free_ptr(fpst
);
5466 gen_set_nzcv(tcg_flags
);
5468 tcg_temp_free_i64(tcg_flags
);
5471 /* Floating point compare
5472 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5473 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5474 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5475 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5477 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5479 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5482 mos
= extract32(insn
, 29, 3);
5483 type
= extract32(insn
, 22, 2);
5484 rm
= extract32(insn
, 16, 5);
5485 op
= extract32(insn
, 14, 2);
5486 rn
= extract32(insn
, 5, 5);
5487 opc
= extract32(insn
, 3, 2);
5488 op2r
= extract32(insn
, 0, 3);
5490 if (mos
|| op
|| op2r
) {
5491 unallocated_encoding(s
);
5504 if (dc_isar_feature(aa64_fp16
, s
)) {
5509 unallocated_encoding(s
);
5513 if (!fp_access_check(s
)) {
5517 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5520 /* Floating point conditional compare
5521 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5522 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5523 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5524 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5526 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5528 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5530 TCGLabel
*label_continue
= NULL
;
5533 mos
= extract32(insn
, 29, 3);
5534 type
= extract32(insn
, 22, 2);
5535 rm
= extract32(insn
, 16, 5);
5536 cond
= extract32(insn
, 12, 4);
5537 rn
= extract32(insn
, 5, 5);
5538 op
= extract32(insn
, 4, 1);
5539 nzcv
= extract32(insn
, 0, 4);
5542 unallocated_encoding(s
);
5555 if (dc_isar_feature(aa64_fp16
, s
)) {
5560 unallocated_encoding(s
);
5564 if (!fp_access_check(s
)) {
5568 if (cond
< 0x0e) { /* not always */
5569 TCGLabel
*label_match
= gen_new_label();
5570 label_continue
= gen_new_label();
5571 arm_gen_test_cc(cond
, label_match
);
5573 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5574 gen_set_nzcv(tcg_flags
);
5575 tcg_temp_free_i64(tcg_flags
);
5576 tcg_gen_br(label_continue
);
5577 gen_set_label(label_match
);
5580 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5583 gen_set_label(label_continue
);
5587 /* Floating point conditional select
5588 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5589 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5590 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5591 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5593 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5595 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5596 TCGv_i64 t_true
, t_false
, t_zero
;
5600 mos
= extract32(insn
, 29, 3);
5601 type
= extract32(insn
, 22, 2);
5602 rm
= extract32(insn
, 16, 5);
5603 cond
= extract32(insn
, 12, 4);
5604 rn
= extract32(insn
, 5, 5);
5605 rd
= extract32(insn
, 0, 5);
5608 unallocated_encoding(s
);
5621 if (dc_isar_feature(aa64_fp16
, s
)) {
5626 unallocated_encoding(s
);
5630 if (!fp_access_check(s
)) {
5634 /* Zero extend sreg & hreg inputs to 64 bits now. */
5635 t_true
= tcg_temp_new_i64();
5636 t_false
= tcg_temp_new_i64();
5637 read_vec_element(s
, t_true
, rn
, 0, sz
);
5638 read_vec_element(s
, t_false
, rm
, 0, sz
);
5640 a64_test_cc(&c
, cond
);
5641 t_zero
= tcg_const_i64(0);
5642 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5643 tcg_temp_free_i64(t_zero
);
5644 tcg_temp_free_i64(t_false
);
5647 /* Note that sregs & hregs write back zeros to the high bits,
5648 and we've already done the zero-extension. */
5649 write_fp_dreg(s
, rd
, t_true
);
5650 tcg_temp_free_i64(t_true
);
5653 /* Floating-point data-processing (1 source) - half precision */
5654 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5656 TCGv_ptr fpst
= NULL
;
5657 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5658 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5661 case 0x0: /* FMOV */
5662 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5664 case 0x1: /* FABS */
5665 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5667 case 0x2: /* FNEG */
5668 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5670 case 0x3: /* FSQRT */
5671 fpst
= get_fpstatus_ptr(true);
5672 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5674 case 0x8: /* FRINTN */
5675 case 0x9: /* FRINTP */
5676 case 0xa: /* FRINTM */
5677 case 0xb: /* FRINTZ */
5678 case 0xc: /* FRINTA */
5680 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5681 fpst
= get_fpstatus_ptr(true);
5683 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5684 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5686 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5687 tcg_temp_free_i32(tcg_rmode
);
5690 case 0xe: /* FRINTX */
5691 fpst
= get_fpstatus_ptr(true);
5692 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5694 case 0xf: /* FRINTI */
5695 fpst
= get_fpstatus_ptr(true);
5696 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5702 write_fp_sreg(s
, rd
, tcg_res
);
5705 tcg_temp_free_ptr(fpst
);
5707 tcg_temp_free_i32(tcg_op
);
5708 tcg_temp_free_i32(tcg_res
);
5711 /* Floating-point data-processing (1 source) - single precision */
5712 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5714 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5715 TCGv_i32 tcg_op
, tcg_res
;
5719 tcg_op
= read_fp_sreg(s
, rn
);
5720 tcg_res
= tcg_temp_new_i32();
5723 case 0x0: /* FMOV */
5724 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5726 case 0x1: /* FABS */
5727 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5729 case 0x2: /* FNEG */
5730 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5732 case 0x3: /* FSQRT */
5733 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5735 case 0x8: /* FRINTN */
5736 case 0x9: /* FRINTP */
5737 case 0xa: /* FRINTM */
5738 case 0xb: /* FRINTZ */
5739 case 0xc: /* FRINTA */
5740 rmode
= arm_rmode_to_sf(opcode
& 7);
5741 gen_fpst
= gen_helper_rints
;
5743 case 0xe: /* FRINTX */
5744 gen_fpst
= gen_helper_rints_exact
;
5746 case 0xf: /* FRINTI */
5747 gen_fpst
= gen_helper_rints
;
5749 case 0x10: /* FRINT32Z */
5750 rmode
= float_round_to_zero
;
5751 gen_fpst
= gen_helper_frint32_s
;
5753 case 0x11: /* FRINT32X */
5754 gen_fpst
= gen_helper_frint32_s
;
5756 case 0x12: /* FRINT64Z */
5757 rmode
= float_round_to_zero
;
5758 gen_fpst
= gen_helper_frint64_s
;
5760 case 0x13: /* FRINT64X */
5761 gen_fpst
= gen_helper_frint64_s
;
5764 g_assert_not_reached();
5767 fpst
= get_fpstatus_ptr(false);
5769 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5770 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5771 gen_fpst(tcg_res
, tcg_op
, fpst
);
5772 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5773 tcg_temp_free_i32(tcg_rmode
);
5775 gen_fpst(tcg_res
, tcg_op
, fpst
);
5777 tcg_temp_free_ptr(fpst
);
5780 write_fp_sreg(s
, rd
, tcg_res
);
5781 tcg_temp_free_i32(tcg_op
);
5782 tcg_temp_free_i32(tcg_res
);
5785 /* Floating-point data-processing (1 source) - double precision */
5786 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5788 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5789 TCGv_i64 tcg_op
, tcg_res
;
5794 case 0x0: /* FMOV */
5795 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5799 tcg_op
= read_fp_dreg(s
, rn
);
5800 tcg_res
= tcg_temp_new_i64();
5803 case 0x1: /* FABS */
5804 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5806 case 0x2: /* FNEG */
5807 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5809 case 0x3: /* FSQRT */
5810 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5812 case 0x8: /* FRINTN */
5813 case 0x9: /* FRINTP */
5814 case 0xa: /* FRINTM */
5815 case 0xb: /* FRINTZ */
5816 case 0xc: /* FRINTA */
5817 rmode
= arm_rmode_to_sf(opcode
& 7);
5818 gen_fpst
= gen_helper_rintd
;
5820 case 0xe: /* FRINTX */
5821 gen_fpst
= gen_helper_rintd_exact
;
5823 case 0xf: /* FRINTI */
5824 gen_fpst
= gen_helper_rintd
;
5826 case 0x10: /* FRINT32Z */
5827 rmode
= float_round_to_zero
;
5828 gen_fpst
= gen_helper_frint32_d
;
5830 case 0x11: /* FRINT32X */
5831 gen_fpst
= gen_helper_frint32_d
;
5833 case 0x12: /* FRINT64Z */
5834 rmode
= float_round_to_zero
;
5835 gen_fpst
= gen_helper_frint64_d
;
5837 case 0x13: /* FRINT64X */
5838 gen_fpst
= gen_helper_frint64_d
;
5841 g_assert_not_reached();
5844 fpst
= get_fpstatus_ptr(false);
5846 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5847 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5848 gen_fpst(tcg_res
, tcg_op
, fpst
);
5849 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5850 tcg_temp_free_i32(tcg_rmode
);
5852 gen_fpst(tcg_res
, tcg_op
, fpst
);
5854 tcg_temp_free_ptr(fpst
);
5857 write_fp_dreg(s
, rd
, tcg_res
);
5858 tcg_temp_free_i64(tcg_op
);
5859 tcg_temp_free_i64(tcg_res
);
5862 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5863 int rd
, int rn
, int dtype
, int ntype
)
5868 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5870 /* Single to double */
5871 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5872 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5873 write_fp_dreg(s
, rd
, tcg_rd
);
5874 tcg_temp_free_i64(tcg_rd
);
5876 /* Single to half */
5877 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5878 TCGv_i32 ahp
= get_ahp_flag();
5879 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5881 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5882 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5883 write_fp_sreg(s
, rd
, tcg_rd
);
5884 tcg_temp_free_i32(tcg_rd
);
5885 tcg_temp_free_i32(ahp
);
5886 tcg_temp_free_ptr(fpst
);
5888 tcg_temp_free_i32(tcg_rn
);
5893 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5894 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5896 /* Double to single */
5897 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5899 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5900 TCGv_i32 ahp
= get_ahp_flag();
5901 /* Double to half */
5902 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5903 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5904 tcg_temp_free_ptr(fpst
);
5905 tcg_temp_free_i32(ahp
);
5907 write_fp_sreg(s
, rd
, tcg_rd
);
5908 tcg_temp_free_i32(tcg_rd
);
5909 tcg_temp_free_i64(tcg_rn
);
5914 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5915 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5916 TCGv_i32 tcg_ahp
= get_ahp_flag();
5917 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5919 /* Half to single */
5920 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5921 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5922 write_fp_sreg(s
, rd
, tcg_rd
);
5923 tcg_temp_free_i32(tcg_rd
);
5925 /* Half to double */
5926 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5927 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5928 write_fp_dreg(s
, rd
, tcg_rd
);
5929 tcg_temp_free_i64(tcg_rd
);
5931 tcg_temp_free_i32(tcg_rn
);
5932 tcg_temp_free_ptr(tcg_fpst
);
5933 tcg_temp_free_i32(tcg_ahp
);
5941 /* Floating point data-processing (1 source)
5942 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5943 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5944 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5945 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5947 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5949 int mos
= extract32(insn
, 29, 3);
5950 int type
= extract32(insn
, 22, 2);
5951 int opcode
= extract32(insn
, 15, 6);
5952 int rn
= extract32(insn
, 5, 5);
5953 int rd
= extract32(insn
, 0, 5);
5956 unallocated_encoding(s
);
5961 case 0x4: case 0x5: case 0x7:
5963 /* FCVT between half, single and double precision */
5964 int dtype
= extract32(opcode
, 0, 2);
5965 if (type
== 2 || dtype
== type
) {
5966 unallocated_encoding(s
);
5969 if (!fp_access_check(s
)) {
5973 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5977 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5978 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5979 unallocated_encoding(s
);
5986 /* 32-to-32 and 64-to-64 ops */
5989 if (!fp_access_check(s
)) {
5992 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5995 if (!fp_access_check(s
)) {
5998 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6001 if (!dc_isar_feature(aa64_fp16
, s
)) {
6002 unallocated_encoding(s
);
6006 if (!fp_access_check(s
)) {
6009 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6012 unallocated_encoding(s
);
6017 unallocated_encoding(s
);
6022 /* Floating-point data-processing (2 source) - single precision */
6023 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6024 int rd
, int rn
, int rm
)
6031 tcg_res
= tcg_temp_new_i32();
6032 fpst
= get_fpstatus_ptr(false);
6033 tcg_op1
= read_fp_sreg(s
, rn
);
6034 tcg_op2
= read_fp_sreg(s
, rm
);
6037 case 0x0: /* FMUL */
6038 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6040 case 0x1: /* FDIV */
6041 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6043 case 0x2: /* FADD */
6044 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6046 case 0x3: /* FSUB */
6047 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6049 case 0x4: /* FMAX */
6050 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6052 case 0x5: /* FMIN */
6053 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6055 case 0x6: /* FMAXNM */
6056 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6058 case 0x7: /* FMINNM */
6059 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6061 case 0x8: /* FNMUL */
6062 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6063 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6067 write_fp_sreg(s
, rd
, tcg_res
);
6069 tcg_temp_free_ptr(fpst
);
6070 tcg_temp_free_i32(tcg_op1
);
6071 tcg_temp_free_i32(tcg_op2
);
6072 tcg_temp_free_i32(tcg_res
);
6075 /* Floating-point data-processing (2 source) - double precision */
6076 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6077 int rd
, int rn
, int rm
)
6084 tcg_res
= tcg_temp_new_i64();
6085 fpst
= get_fpstatus_ptr(false);
6086 tcg_op1
= read_fp_dreg(s
, rn
);
6087 tcg_op2
= read_fp_dreg(s
, rm
);
6090 case 0x0: /* FMUL */
6091 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6093 case 0x1: /* FDIV */
6094 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6096 case 0x2: /* FADD */
6097 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6099 case 0x3: /* FSUB */
6100 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6102 case 0x4: /* FMAX */
6103 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6105 case 0x5: /* FMIN */
6106 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6108 case 0x6: /* FMAXNM */
6109 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6111 case 0x7: /* FMINNM */
6112 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6114 case 0x8: /* FNMUL */
6115 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6116 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6120 write_fp_dreg(s
, rd
, tcg_res
);
6122 tcg_temp_free_ptr(fpst
);
6123 tcg_temp_free_i64(tcg_op1
);
6124 tcg_temp_free_i64(tcg_op2
);
6125 tcg_temp_free_i64(tcg_res
);
6128 /* Floating-point data-processing (2 source) - half precision */
6129 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6130 int rd
, int rn
, int rm
)
6137 tcg_res
= tcg_temp_new_i32();
6138 fpst
= get_fpstatus_ptr(true);
6139 tcg_op1
= read_fp_hreg(s
, rn
);
6140 tcg_op2
= read_fp_hreg(s
, rm
);
6143 case 0x0: /* FMUL */
6144 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6146 case 0x1: /* FDIV */
6147 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6149 case 0x2: /* FADD */
6150 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6152 case 0x3: /* FSUB */
6153 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6155 case 0x4: /* FMAX */
6156 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6158 case 0x5: /* FMIN */
6159 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6161 case 0x6: /* FMAXNM */
6162 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6164 case 0x7: /* FMINNM */
6165 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6167 case 0x8: /* FNMUL */
6168 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6169 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6172 g_assert_not_reached();
6175 write_fp_sreg(s
, rd
, tcg_res
);
6177 tcg_temp_free_ptr(fpst
);
6178 tcg_temp_free_i32(tcg_op1
);
6179 tcg_temp_free_i32(tcg_op2
);
6180 tcg_temp_free_i32(tcg_res
);
6183 /* Floating point data-processing (2 source)
6184 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6185 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6186 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6187 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6189 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6191 int mos
= extract32(insn
, 29, 3);
6192 int type
= extract32(insn
, 22, 2);
6193 int rd
= extract32(insn
, 0, 5);
6194 int rn
= extract32(insn
, 5, 5);
6195 int rm
= extract32(insn
, 16, 5);
6196 int opcode
= extract32(insn
, 12, 4);
6198 if (opcode
> 8 || mos
) {
6199 unallocated_encoding(s
);
6205 if (!fp_access_check(s
)) {
6208 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6211 if (!fp_access_check(s
)) {
6214 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6217 if (!dc_isar_feature(aa64_fp16
, s
)) {
6218 unallocated_encoding(s
);
6221 if (!fp_access_check(s
)) {
6224 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6227 unallocated_encoding(s
);
6231 /* Floating-point data-processing (3 source) - single precision */
6232 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6233 int rd
, int rn
, int rm
, int ra
)
6235 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6236 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6237 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6239 tcg_op1
= read_fp_sreg(s
, rn
);
6240 tcg_op2
= read_fp_sreg(s
, rm
);
6241 tcg_op3
= read_fp_sreg(s
, ra
);
6243 /* These are fused multiply-add, and must be done as one
6244 * floating point operation with no rounding between the
6245 * multiplication and addition steps.
6246 * NB that doing the negations here as separate steps is
6247 * correct : an input NaN should come out with its sign bit
6248 * flipped if it is a negated-input.
6251 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6255 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6258 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6260 write_fp_sreg(s
, rd
, tcg_res
);
6262 tcg_temp_free_ptr(fpst
);
6263 tcg_temp_free_i32(tcg_op1
);
6264 tcg_temp_free_i32(tcg_op2
);
6265 tcg_temp_free_i32(tcg_op3
);
6266 tcg_temp_free_i32(tcg_res
);
6269 /* Floating-point data-processing (3 source) - double precision */
6270 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6271 int rd
, int rn
, int rm
, int ra
)
6273 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6274 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6275 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6277 tcg_op1
= read_fp_dreg(s
, rn
);
6278 tcg_op2
= read_fp_dreg(s
, rm
);
6279 tcg_op3
= read_fp_dreg(s
, ra
);
6281 /* These are fused multiply-add, and must be done as one
6282 * floating point operation with no rounding between the
6283 * multiplication and addition steps.
6284 * NB that doing the negations here as separate steps is
6285 * correct : an input NaN should come out with its sign bit
6286 * flipped if it is a negated-input.
6289 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6293 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6296 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6298 write_fp_dreg(s
, rd
, tcg_res
);
6300 tcg_temp_free_ptr(fpst
);
6301 tcg_temp_free_i64(tcg_op1
);
6302 tcg_temp_free_i64(tcg_op2
);
6303 tcg_temp_free_i64(tcg_op3
);
6304 tcg_temp_free_i64(tcg_res
);
6307 /* Floating-point data-processing (3 source) - half precision */
6308 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6309 int rd
, int rn
, int rm
, int ra
)
6311 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6312 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6313 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6315 tcg_op1
= read_fp_hreg(s
, rn
);
6316 tcg_op2
= read_fp_hreg(s
, rm
);
6317 tcg_op3
= read_fp_hreg(s
, ra
);
6319 /* These are fused multiply-add, and must be done as one
6320 * floating point operation with no rounding between the
6321 * multiplication and addition steps.
6322 * NB that doing the negations here as separate steps is
6323 * correct : an input NaN should come out with its sign bit
6324 * flipped if it is a negated-input.
6327 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6331 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6334 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6336 write_fp_sreg(s
, rd
, tcg_res
);
6338 tcg_temp_free_ptr(fpst
);
6339 tcg_temp_free_i32(tcg_op1
);
6340 tcg_temp_free_i32(tcg_op2
);
6341 tcg_temp_free_i32(tcg_op3
);
6342 tcg_temp_free_i32(tcg_res
);
6345 /* Floating point data-processing (3 source)
6346 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6347 * +---+---+---+-----------+------+----+------+----+------+------+------+
6348 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6349 * +---+---+---+-----------+------+----+------+----+------+------+------+
6351 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6353 int mos
= extract32(insn
, 29, 3);
6354 int type
= extract32(insn
, 22, 2);
6355 int rd
= extract32(insn
, 0, 5);
6356 int rn
= extract32(insn
, 5, 5);
6357 int ra
= extract32(insn
, 10, 5);
6358 int rm
= extract32(insn
, 16, 5);
6359 bool o0
= extract32(insn
, 15, 1);
6360 bool o1
= extract32(insn
, 21, 1);
6363 unallocated_encoding(s
);
6369 if (!fp_access_check(s
)) {
6372 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6375 if (!fp_access_check(s
)) {
6378 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6381 if (!dc_isar_feature(aa64_fp16
, s
)) {
6382 unallocated_encoding(s
);
6385 if (!fp_access_check(s
)) {
6388 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6391 unallocated_encoding(s
);
6395 /* Floating point immediate
6396 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6397 * +---+---+---+-----------+------+---+------------+-------+------+------+
6398 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6399 * +---+---+---+-----------+------+---+------------+-------+------+------+
6401 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6403 int rd
= extract32(insn
, 0, 5);
6404 int imm5
= extract32(insn
, 5, 5);
6405 int imm8
= extract32(insn
, 13, 8);
6406 int type
= extract32(insn
, 22, 2);
6407 int mos
= extract32(insn
, 29, 3);
6413 unallocated_encoding(s
);
6426 if (dc_isar_feature(aa64_fp16
, s
)) {
6431 unallocated_encoding(s
);
6435 if (!fp_access_check(s
)) {
6439 imm
= vfp_expand_imm(sz
, imm8
);
6441 tcg_res
= tcg_const_i64(imm
);
6442 write_fp_dreg(s
, rd
, tcg_res
);
6443 tcg_temp_free_i64(tcg_res
);
6446 /* Handle floating point <=> fixed point conversions. Note that we can
6447 * also deal with fp <=> integer conversions as a special case (scale == 64)
6448 * OPTME: consider handling that special case specially or at least skipping
6449 * the call to scalbn in the helpers for zero shifts.
6451 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6452 bool itof
, int rmode
, int scale
, int sf
, int type
)
6454 bool is_signed
= !(opcode
& 1);
6455 TCGv_ptr tcg_fpstatus
;
6456 TCGv_i32 tcg_shift
, tcg_single
;
6457 TCGv_i64 tcg_double
;
6459 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6461 tcg_shift
= tcg_const_i32(64 - scale
);
6464 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6466 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6469 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6471 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6474 tcg_int
= tcg_extend
;
6478 case 1: /* float64 */
6479 tcg_double
= tcg_temp_new_i64();
6481 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6482 tcg_shift
, tcg_fpstatus
);
6484 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6485 tcg_shift
, tcg_fpstatus
);
6487 write_fp_dreg(s
, rd
, tcg_double
);
6488 tcg_temp_free_i64(tcg_double
);
6491 case 0: /* float32 */
6492 tcg_single
= tcg_temp_new_i32();
6494 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6495 tcg_shift
, tcg_fpstatus
);
6497 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6498 tcg_shift
, tcg_fpstatus
);
6500 write_fp_sreg(s
, rd
, tcg_single
);
6501 tcg_temp_free_i32(tcg_single
);
6504 case 3: /* float16 */
6505 tcg_single
= tcg_temp_new_i32();
6507 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6508 tcg_shift
, tcg_fpstatus
);
6510 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6511 tcg_shift
, tcg_fpstatus
);
6513 write_fp_sreg(s
, rd
, tcg_single
);
6514 tcg_temp_free_i32(tcg_single
);
6518 g_assert_not_reached();
6521 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6524 if (extract32(opcode
, 2, 1)) {
6525 /* There are too many rounding modes to all fit into rmode,
6526 * so FCVTA[US] is a special case.
6528 rmode
= FPROUNDING_TIEAWAY
;
6531 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6533 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6536 case 1: /* float64 */
6537 tcg_double
= read_fp_dreg(s
, rn
);
6540 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6541 tcg_shift
, tcg_fpstatus
);
6543 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6544 tcg_shift
, tcg_fpstatus
);
6548 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6549 tcg_shift
, tcg_fpstatus
);
6551 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6552 tcg_shift
, tcg_fpstatus
);
6556 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6558 tcg_temp_free_i64(tcg_double
);
6561 case 0: /* float32 */
6562 tcg_single
= read_fp_sreg(s
, rn
);
6565 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6566 tcg_shift
, tcg_fpstatus
);
6568 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6569 tcg_shift
, tcg_fpstatus
);
6572 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6574 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6575 tcg_shift
, tcg_fpstatus
);
6577 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6578 tcg_shift
, tcg_fpstatus
);
6580 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6581 tcg_temp_free_i32(tcg_dest
);
6583 tcg_temp_free_i32(tcg_single
);
6586 case 3: /* float16 */
6587 tcg_single
= read_fp_sreg(s
, rn
);
6590 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6591 tcg_shift
, tcg_fpstatus
);
6593 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6594 tcg_shift
, tcg_fpstatus
);
6597 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6599 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6600 tcg_shift
, tcg_fpstatus
);
6602 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6603 tcg_shift
, tcg_fpstatus
);
6605 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6606 tcg_temp_free_i32(tcg_dest
);
6608 tcg_temp_free_i32(tcg_single
);
6612 g_assert_not_reached();
6615 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6616 tcg_temp_free_i32(tcg_rmode
);
6619 tcg_temp_free_ptr(tcg_fpstatus
);
6620 tcg_temp_free_i32(tcg_shift
);
6623 /* Floating point <-> fixed point conversions
6624 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6625 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6626 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6627 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6629 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6631 int rd
= extract32(insn
, 0, 5);
6632 int rn
= extract32(insn
, 5, 5);
6633 int scale
= extract32(insn
, 10, 6);
6634 int opcode
= extract32(insn
, 16, 3);
6635 int rmode
= extract32(insn
, 19, 2);
6636 int type
= extract32(insn
, 22, 2);
6637 bool sbit
= extract32(insn
, 29, 1);
6638 bool sf
= extract32(insn
, 31, 1);
6641 if (sbit
|| (!sf
&& scale
< 32)) {
6642 unallocated_encoding(s
);
6647 case 0: /* float32 */
6648 case 1: /* float64 */
6650 case 3: /* float16 */
6651 if (dc_isar_feature(aa64_fp16
, s
)) {
6656 unallocated_encoding(s
);
6660 switch ((rmode
<< 3) | opcode
) {
6661 case 0x2: /* SCVTF */
6662 case 0x3: /* UCVTF */
6665 case 0x18: /* FCVTZS */
6666 case 0x19: /* FCVTZU */
6670 unallocated_encoding(s
);
6674 if (!fp_access_check(s
)) {
6678 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6681 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6683 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6684 * without conversion.
6688 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6694 tmp
= tcg_temp_new_i64();
6695 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6696 write_fp_dreg(s
, rd
, tmp
);
6697 tcg_temp_free_i64(tmp
);
6701 write_fp_dreg(s
, rd
, tcg_rn
);
6704 /* 64 bit to top half. */
6705 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6706 clear_vec_high(s
, true, rd
);
6710 tmp
= tcg_temp_new_i64();
6711 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6712 write_fp_dreg(s
, rd
, tmp
);
6713 tcg_temp_free_i64(tmp
);
6716 g_assert_not_reached();
6719 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6724 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6728 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6731 /* 64 bits from top half */
6732 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6736 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6739 g_assert_not_reached();
6744 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6746 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6747 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6749 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6751 tcg_temp_free_ptr(fpstatus
);
6753 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6754 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6755 tcg_gen_movi_i32(cpu_CF
, 0);
6756 tcg_gen_movi_i32(cpu_NF
, 0);
6757 tcg_gen_movi_i32(cpu_VF
, 0);
6759 tcg_temp_free_i64(t
);
6762 /* Floating point <-> integer conversions
6763 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6764 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6765 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6766 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6768 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6770 int rd
= extract32(insn
, 0, 5);
6771 int rn
= extract32(insn
, 5, 5);
6772 int opcode
= extract32(insn
, 16, 3);
6773 int rmode
= extract32(insn
, 19, 2);
6774 int type
= extract32(insn
, 22, 2);
6775 bool sbit
= extract32(insn
, 29, 1);
6776 bool sf
= extract32(insn
, 31, 1);
6780 goto do_unallocated
;
6788 case 4: /* FCVTAS */
6789 case 5: /* FCVTAU */
6791 goto do_unallocated
;
6794 case 0: /* FCVT[NPMZ]S */
6795 case 1: /* FCVT[NPMZ]U */
6797 case 0: /* float32 */
6798 case 1: /* float64 */
6800 case 3: /* float16 */
6801 if (!dc_isar_feature(aa64_fp16
, s
)) {
6802 goto do_unallocated
;
6806 goto do_unallocated
;
6808 if (!fp_access_check(s
)) {
6811 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6815 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6816 case 0b01100110: /* FMOV half <-> 32-bit int */
6818 case 0b11100110: /* FMOV half <-> 64-bit int */
6820 if (!dc_isar_feature(aa64_fp16
, s
)) {
6821 goto do_unallocated
;
6824 case 0b00000110: /* FMOV 32-bit */
6826 case 0b10100110: /* FMOV 64-bit */
6828 case 0b11001110: /* FMOV top half of 128-bit */
6830 if (!fp_access_check(s
)) {
6834 handle_fmov(s
, rd
, rn
, type
, itof
);
6837 case 0b00111110: /* FJCVTZS */
6838 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6839 goto do_unallocated
;
6840 } else if (fp_access_check(s
)) {
6841 handle_fjcvtzs(s
, rd
, rn
);
6847 unallocated_encoding(s
);
6854 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6855 * 31 30 29 28 25 24 0
6856 * +---+---+---+---------+-----------------------------+
6857 * | | 0 | | 1 1 1 1 | |
6858 * +---+---+---+---------+-----------------------------+
6860 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6862 if (extract32(insn
, 24, 1)) {
6863 /* Floating point data-processing (3 source) */
6864 disas_fp_3src(s
, insn
);
6865 } else if (extract32(insn
, 21, 1) == 0) {
6866 /* Floating point to fixed point conversions */
6867 disas_fp_fixed_conv(s
, insn
);
6869 switch (extract32(insn
, 10, 2)) {
6871 /* Floating point conditional compare */
6872 disas_fp_ccomp(s
, insn
);
6875 /* Floating point data-processing (2 source) */
6876 disas_fp_2src(s
, insn
);
6879 /* Floating point conditional select */
6880 disas_fp_csel(s
, insn
);
6883 switch (ctz32(extract32(insn
, 12, 4))) {
6884 case 0: /* [15:12] == xxx1 */
6885 /* Floating point immediate */
6886 disas_fp_imm(s
, insn
);
6888 case 1: /* [15:12] == xx10 */
6889 /* Floating point compare */
6890 disas_fp_compare(s
, insn
);
6892 case 2: /* [15:12] == x100 */
6893 /* Floating point data-processing (1 source) */
6894 disas_fp_1src(s
, insn
);
6896 case 3: /* [15:12] == 1000 */
6897 unallocated_encoding(s
);
6899 default: /* [15:12] == 0000 */
6900 /* Floating point <-> integer conversions */
6901 disas_fp_int_conv(s
, insn
);
6909 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6912 /* Extract 64 bits from the middle of two concatenated 64 bit
6913 * vector register slices left:right. The extracted bits start
6914 * at 'pos' bits into the right (least significant) side.
6915 * We return the result in tcg_right, and guarantee not to
6918 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6919 assert(pos
> 0 && pos
< 64);
6921 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6922 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6923 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6925 tcg_temp_free_i64(tcg_tmp
);
6929 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6930 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6931 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6932 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6934 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6936 int is_q
= extract32(insn
, 30, 1);
6937 int op2
= extract32(insn
, 22, 2);
6938 int imm4
= extract32(insn
, 11, 4);
6939 int rm
= extract32(insn
, 16, 5);
6940 int rn
= extract32(insn
, 5, 5);
6941 int rd
= extract32(insn
, 0, 5);
6942 int pos
= imm4
<< 3;
6943 TCGv_i64 tcg_resl
, tcg_resh
;
6945 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6946 unallocated_encoding(s
);
6950 if (!fp_access_check(s
)) {
6954 tcg_resh
= tcg_temp_new_i64();
6955 tcg_resl
= tcg_temp_new_i64();
6957 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6958 * either extracting 128 bits from a 128:128 concatenation, or
6959 * extracting 64 bits from a 64:64 concatenation.
6962 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6964 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6965 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6973 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6974 EltPosns
*elt
= eltposns
;
6981 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6983 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6986 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6987 tcg_hh
= tcg_temp_new_i64();
6988 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6989 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6990 tcg_temp_free_i64(tcg_hh
);
6994 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6995 tcg_temp_free_i64(tcg_resl
);
6997 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6999 tcg_temp_free_i64(tcg_resh
);
7000 clear_vec_high(s
, is_q
, rd
);
7004 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7005 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7006 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7007 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7009 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7011 int op2
= extract32(insn
, 22, 2);
7012 int is_q
= extract32(insn
, 30, 1);
7013 int rm
= extract32(insn
, 16, 5);
7014 int rn
= extract32(insn
, 5, 5);
7015 int rd
= extract32(insn
, 0, 5);
7016 int is_tblx
= extract32(insn
, 12, 1);
7017 int len
= extract32(insn
, 13, 2);
7018 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7019 TCGv_i32 tcg_regno
, tcg_numregs
;
7022 unallocated_encoding(s
);
7026 if (!fp_access_check(s
)) {
7030 /* This does a table lookup: for every byte element in the input
7031 * we index into a table formed from up to four vector registers,
7032 * and then the output is the result of the lookups. Our helper
7033 * function does the lookup operation for a single 64 bit part of
7036 tcg_resl
= tcg_temp_new_i64();
7040 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7042 tcg_gen_movi_i64(tcg_resl
, 0);
7046 tcg_resh
= tcg_temp_new_i64();
7048 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7050 tcg_gen_movi_i64(tcg_resh
, 0);
7054 tcg_idx
= tcg_temp_new_i64();
7055 tcg_regno
= tcg_const_i32(rn
);
7056 tcg_numregs
= tcg_const_i32(len
+ 1);
7057 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7058 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7059 tcg_regno
, tcg_numregs
);
7061 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7062 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7063 tcg_regno
, tcg_numregs
);
7065 tcg_temp_free_i64(tcg_idx
);
7066 tcg_temp_free_i32(tcg_regno
);
7067 tcg_temp_free_i32(tcg_numregs
);
7069 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7070 tcg_temp_free_i64(tcg_resl
);
7073 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7074 tcg_temp_free_i64(tcg_resh
);
7076 clear_vec_high(s
, is_q
, rd
);
7080 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7081 * +---+---+-------------+------+---+------+---+------------------+------+
7082 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7083 * +---+---+-------------+------+---+------+---+------------------+------+
7085 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7087 int rd
= extract32(insn
, 0, 5);
7088 int rn
= extract32(insn
, 5, 5);
7089 int rm
= extract32(insn
, 16, 5);
7090 int size
= extract32(insn
, 22, 2);
7091 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7092 * bit 2 indicates 1 vs 2 variant of the insn.
7094 int opcode
= extract32(insn
, 12, 2);
7095 bool part
= extract32(insn
, 14, 1);
7096 bool is_q
= extract32(insn
, 30, 1);
7097 int esize
= 8 << size
;
7099 int datasize
= is_q
? 128 : 64;
7100 int elements
= datasize
/ esize
;
7101 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7103 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7104 unallocated_encoding(s
);
7108 if (!fp_access_check(s
)) {
7112 tcg_resl
= tcg_const_i64(0);
7113 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7114 tcg_res
= tcg_temp_new_i64();
7116 for (i
= 0; i
< elements
; i
++) {
7118 case 1: /* UZP1/2 */
7120 int midpoint
= elements
/ 2;
7122 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7124 read_vec_element(s
, tcg_res
, rm
,
7125 2 * (i
- midpoint
) + part
, size
);
7129 case 2: /* TRN1/2 */
7131 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7133 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7136 case 3: /* ZIP1/2 */
7138 int base
= part
* elements
/ 2;
7140 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7142 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7147 g_assert_not_reached();
7152 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7153 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7155 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7156 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7160 tcg_temp_free_i64(tcg_res
);
7162 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7163 tcg_temp_free_i64(tcg_resl
);
7166 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7167 tcg_temp_free_i64(tcg_resh
);
7169 clear_vec_high(s
, is_q
, rd
);
7173 * do_reduction_op helper
7175 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7176 * important for correct NaN propagation that we do these
7177 * operations in exactly the order specified by the pseudocode.
7179 * This is a recursive function, TCG temps should be freed by the
7180 * calling function once it is done with the values.
7182 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7183 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7185 if (esize
== size
) {
7187 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7190 /* We should have one register left here */
7191 assert(ctpop8(vmap
) == 1);
7192 element
= ctz32(vmap
);
7193 assert(element
< 8);
7195 tcg_elem
= tcg_temp_new_i32();
7196 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7199 int bits
= size
/ 2;
7200 int shift
= ctpop8(vmap
) / 2;
7201 int vmap_lo
= (vmap
>> shift
) & vmap
;
7202 int vmap_hi
= (vmap
& ~vmap_lo
);
7203 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7205 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7206 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7207 tcg_res
= tcg_temp_new_i32();
7210 case 0x0c: /* fmaxnmv half-precision */
7211 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7213 case 0x0f: /* fmaxv half-precision */
7214 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7216 case 0x1c: /* fminnmv half-precision */
7217 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7219 case 0x1f: /* fminv half-precision */
7220 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7222 case 0x2c: /* fmaxnmv */
7223 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7225 case 0x2f: /* fmaxv */
7226 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7228 case 0x3c: /* fminnmv */
7229 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7231 case 0x3f: /* fminv */
7232 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7235 g_assert_not_reached();
7238 tcg_temp_free_i32(tcg_hi
);
7239 tcg_temp_free_i32(tcg_lo
);
7244 /* AdvSIMD across lanes
7245 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7246 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7247 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7248 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7250 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7252 int rd
= extract32(insn
, 0, 5);
7253 int rn
= extract32(insn
, 5, 5);
7254 int size
= extract32(insn
, 22, 2);
7255 int opcode
= extract32(insn
, 12, 5);
7256 bool is_q
= extract32(insn
, 30, 1);
7257 bool is_u
= extract32(insn
, 29, 1);
7259 bool is_min
= false;
7263 TCGv_i64 tcg_res
, tcg_elt
;
7266 case 0x1b: /* ADDV */
7268 unallocated_encoding(s
);
7272 case 0x3: /* SADDLV, UADDLV */
7273 case 0xa: /* SMAXV, UMAXV */
7274 case 0x1a: /* SMINV, UMINV */
7275 if (size
== 3 || (size
== 2 && !is_q
)) {
7276 unallocated_encoding(s
);
7280 case 0xc: /* FMAXNMV, FMINNMV */
7281 case 0xf: /* FMAXV, FMINV */
7282 /* Bit 1 of size field encodes min vs max and the actual size
7283 * depends on the encoding of the U bit. If not set (and FP16
7284 * enabled) then we do half-precision float instead of single
7287 is_min
= extract32(size
, 1, 1);
7289 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7291 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7292 unallocated_encoding(s
);
7299 unallocated_encoding(s
);
7303 if (!fp_access_check(s
)) {
7308 elements
= (is_q
? 128 : 64) / esize
;
7310 tcg_res
= tcg_temp_new_i64();
7311 tcg_elt
= tcg_temp_new_i64();
7313 /* These instructions operate across all lanes of a vector
7314 * to produce a single result. We can guarantee that a 64
7315 * bit intermediate is sufficient:
7316 * + for [US]ADDLV the maximum element size is 32 bits, and
7317 * the result type is 64 bits
7318 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7319 * same as the element size, which is 32 bits at most
7320 * For the integer operations we can choose to work at 64
7321 * or 32 bits and truncate at the end; for simplicity
7322 * we use 64 bits always. The floating point
7323 * ops do require 32 bit intermediates, though.
7326 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7328 for (i
= 1; i
< elements
; i
++) {
7329 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7332 case 0x03: /* SADDLV / UADDLV */
7333 case 0x1b: /* ADDV */
7334 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7336 case 0x0a: /* SMAXV / UMAXV */
7338 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7340 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7343 case 0x1a: /* SMINV / UMINV */
7345 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7347 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7351 g_assert_not_reached();
7356 /* Floating point vector reduction ops which work across 32
7357 * bit (single) or 16 bit (half-precision) intermediates.
7358 * Note that correct NaN propagation requires that we do these
7359 * operations in exactly the order specified by the pseudocode.
7361 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7362 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7363 int vmap
= (1 << elements
) - 1;
7364 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7365 (is_q
? 128 : 64), vmap
, fpst
);
7366 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7367 tcg_temp_free_i32(tcg_res32
);
7368 tcg_temp_free_ptr(fpst
);
7371 tcg_temp_free_i64(tcg_elt
);
7373 /* Now truncate the result to the width required for the final output */
7374 if (opcode
== 0x03) {
7375 /* SADDLV, UADDLV: result is 2*esize */
7381 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7384 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7387 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7392 g_assert_not_reached();
7395 write_fp_dreg(s
, rd
, tcg_res
);
7396 tcg_temp_free_i64(tcg_res
);
7399 /* DUP (Element, Vector)
7401 * 31 30 29 21 20 16 15 10 9 5 4 0
7402 * +---+---+-------------------+--------+-------------+------+------+
7403 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7404 * +---+---+-------------------+--------+-------------+------+------+
7406 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7408 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7411 int size
= ctz32(imm5
);
7414 if (size
> 3 || (size
== 3 && !is_q
)) {
7415 unallocated_encoding(s
);
7419 if (!fp_access_check(s
)) {
7423 index
= imm5
>> (size
+ 1);
7424 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7425 vec_reg_offset(s
, rn
, index
, size
),
7426 is_q
? 16 : 8, vec_full_reg_size(s
));
7429 /* DUP (element, scalar)
7430 * 31 21 20 16 15 10 9 5 4 0
7431 * +-----------------------+--------+-------------+------+------+
7432 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7433 * +-----------------------+--------+-------------+------+------+
7435 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7438 int size
= ctz32(imm5
);
7443 unallocated_encoding(s
);
7447 if (!fp_access_check(s
)) {
7451 index
= imm5
>> (size
+ 1);
7453 /* This instruction just extracts the specified element and
7454 * zero-extends it into the bottom of the destination register.
7456 tmp
= tcg_temp_new_i64();
7457 read_vec_element(s
, tmp
, rn
, index
, size
);
7458 write_fp_dreg(s
, rd
, tmp
);
7459 tcg_temp_free_i64(tmp
);
7464 * 31 30 29 21 20 16 15 10 9 5 4 0
7465 * +---+---+-------------------+--------+-------------+------+------+
7466 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7467 * +---+---+-------------------+--------+-------------+------+------+
7469 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7471 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7474 int size
= ctz32(imm5
);
7475 uint32_t dofs
, oprsz
, maxsz
;
7477 if (size
> 3 || ((size
== 3) && !is_q
)) {
7478 unallocated_encoding(s
);
7482 if (!fp_access_check(s
)) {
7486 dofs
= vec_full_reg_offset(s
, rd
);
7487 oprsz
= is_q
? 16 : 8;
7488 maxsz
= vec_full_reg_size(s
);
7490 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7495 * 31 21 20 16 15 14 11 10 9 5 4 0
7496 * +-----------------------+--------+------------+---+------+------+
7497 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7498 * +-----------------------+--------+------------+---+------+------+
7500 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7501 * index: encoded in imm5<4:size+1>
7503 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7506 int size
= ctz32(imm5
);
7507 int src_index
, dst_index
;
7511 unallocated_encoding(s
);
7515 if (!fp_access_check(s
)) {
7519 dst_index
= extract32(imm5
, 1+size
, 5);
7520 src_index
= extract32(imm4
, size
, 4);
7522 tmp
= tcg_temp_new_i64();
7524 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7525 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7527 tcg_temp_free_i64(tmp
);
7529 /* INS is considered a 128-bit write for SVE. */
7530 clear_vec_high(s
, true, rd
);
7536 * 31 21 20 16 15 10 9 5 4 0
7537 * +-----------------------+--------+-------------+------+------+
7538 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7539 * +-----------------------+--------+-------------+------+------+
7541 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7542 * index: encoded in imm5<4:size+1>
7544 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7546 int size
= ctz32(imm5
);
7550 unallocated_encoding(s
);
7554 if (!fp_access_check(s
)) {
7558 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7559 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7561 /* INS is considered a 128-bit write for SVE. */
7562 clear_vec_high(s
, true, rd
);
7569 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7570 * +---+---+-------------------+--------+-------------+------+------+
7571 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7572 * +---+---+-------------------+--------+-------------+------+------+
7574 * U: unsigned when set
7575 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7577 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7578 int rn
, int rd
, int imm5
)
7580 int size
= ctz32(imm5
);
7584 /* Check for UnallocatedEncodings */
7586 if (size
> 2 || (size
== 2 && !is_q
)) {
7587 unallocated_encoding(s
);
7592 || (size
< 3 && is_q
)
7593 || (size
== 3 && !is_q
)) {
7594 unallocated_encoding(s
);
7599 if (!fp_access_check(s
)) {
7603 element
= extract32(imm5
, 1+size
, 4);
7605 tcg_rd
= cpu_reg(s
, rd
);
7606 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7607 if (is_signed
&& !is_q
) {
7608 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7613 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7614 * +---+---+----+-----------------+------+---+------+---+------+------+
7615 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7616 * +---+---+----+-----------------+------+---+------+---+------+------+
7618 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7620 int rd
= extract32(insn
, 0, 5);
7621 int rn
= extract32(insn
, 5, 5);
7622 int imm4
= extract32(insn
, 11, 4);
7623 int op
= extract32(insn
, 29, 1);
7624 int is_q
= extract32(insn
, 30, 1);
7625 int imm5
= extract32(insn
, 16, 5);
7630 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7632 unallocated_encoding(s
);
7637 /* DUP (element - vector) */
7638 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7642 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7647 handle_simd_insg(s
, rd
, rn
, imm5
);
7649 unallocated_encoding(s
);
7654 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7655 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7658 unallocated_encoding(s
);
7664 /* AdvSIMD modified immediate
7665 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7666 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7667 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7668 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7670 * There are a number of operations that can be carried out here:
7671 * MOVI - move (shifted) imm into register
7672 * MVNI - move inverted (shifted) imm into register
7673 * ORR - bitwise OR of (shifted) imm with register
7674 * BIC - bitwise clear of (shifted) imm with register
7675 * With ARMv8.2 we also have:
7676 * FMOV half-precision
7678 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7680 int rd
= extract32(insn
, 0, 5);
7681 int cmode
= extract32(insn
, 12, 4);
7682 int cmode_3_1
= extract32(cmode
, 1, 3);
7683 int cmode_0
= extract32(cmode
, 0, 1);
7684 int o2
= extract32(insn
, 11, 1);
7685 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7686 bool is_neg
= extract32(insn
, 29, 1);
7687 bool is_q
= extract32(insn
, 30, 1);
7690 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7691 /* Check for FMOV (vector, immediate) - half-precision */
7692 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7693 unallocated_encoding(s
);
7698 if (!fp_access_check(s
)) {
7702 /* See AdvSIMDExpandImm() in ARM ARM */
7703 switch (cmode_3_1
) {
7704 case 0: /* Replicate(Zeros(24):imm8, 2) */
7705 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7706 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7707 case 3: /* Replicate(imm8:Zeros(24), 2) */
7709 int shift
= cmode_3_1
* 8;
7710 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7713 case 4: /* Replicate(Zeros(8):imm8, 4) */
7714 case 5: /* Replicate(imm8:Zeros(8), 4) */
7716 int shift
= (cmode_3_1
& 0x1) * 8;
7717 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7722 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7723 imm
= (abcdefgh
<< 16) | 0xffff;
7725 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7726 imm
= (abcdefgh
<< 8) | 0xff;
7728 imm
= bitfield_replicate(imm
, 32);
7731 if (!cmode_0
&& !is_neg
) {
7732 imm
= bitfield_replicate(abcdefgh
, 8);
7733 } else if (!cmode_0
&& is_neg
) {
7736 for (i
= 0; i
< 8; i
++) {
7737 if ((abcdefgh
) & (1 << i
)) {
7738 imm
|= 0xffULL
<< (i
* 8);
7741 } else if (cmode_0
) {
7743 imm
= (abcdefgh
& 0x3f) << 48;
7744 if (abcdefgh
& 0x80) {
7745 imm
|= 0x8000000000000000ULL
;
7747 if (abcdefgh
& 0x40) {
7748 imm
|= 0x3fc0000000000000ULL
;
7750 imm
|= 0x4000000000000000ULL
;
7754 /* FMOV (vector, immediate) - half-precision */
7755 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7756 /* now duplicate across the lanes */
7757 imm
= bitfield_replicate(imm
, 16);
7759 imm
= (abcdefgh
& 0x3f) << 19;
7760 if (abcdefgh
& 0x80) {
7763 if (abcdefgh
& 0x40) {
7774 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7775 g_assert_not_reached();
7778 if (cmode_3_1
!= 7 && is_neg
) {
7782 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7783 /* MOVI or MVNI, with MVNI negation handled above. */
7784 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7785 vec_full_reg_size(s
), imm
);
7787 /* ORR or BIC, with BIC negation to AND handled above. */
7789 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7791 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7796 /* AdvSIMD scalar copy
7797 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7798 * +-----+----+-----------------+------+---+------+---+------+------+
7799 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7800 * +-----+----+-----------------+------+---+------+---+------+------+
7802 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7804 int rd
= extract32(insn
, 0, 5);
7805 int rn
= extract32(insn
, 5, 5);
7806 int imm4
= extract32(insn
, 11, 4);
7807 int imm5
= extract32(insn
, 16, 5);
7808 int op
= extract32(insn
, 29, 1);
7810 if (op
!= 0 || imm4
!= 0) {
7811 unallocated_encoding(s
);
7815 /* DUP (element, scalar) */
7816 handle_simd_dupes(s
, rd
, rn
, imm5
);
7819 /* AdvSIMD scalar pairwise
7820 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7821 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7822 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7823 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7825 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7827 int u
= extract32(insn
, 29, 1);
7828 int size
= extract32(insn
, 22, 2);
7829 int opcode
= extract32(insn
, 12, 5);
7830 int rn
= extract32(insn
, 5, 5);
7831 int rd
= extract32(insn
, 0, 5);
7834 /* For some ops (the FP ones), size[1] is part of the encoding.
7835 * For ADDP strictly it is not but size[1] is always 1 for valid
7838 opcode
|= (extract32(size
, 1, 1) << 5);
7841 case 0x3b: /* ADDP */
7842 if (u
|| size
!= 3) {
7843 unallocated_encoding(s
);
7846 if (!fp_access_check(s
)) {
7852 case 0xc: /* FMAXNMP */
7853 case 0xd: /* FADDP */
7854 case 0xf: /* FMAXP */
7855 case 0x2c: /* FMINNMP */
7856 case 0x2f: /* FMINP */
7857 /* FP op, size[0] is 32 or 64 bit*/
7859 if (!dc_isar_feature(aa64_fp16
, s
)) {
7860 unallocated_encoding(s
);
7866 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7869 if (!fp_access_check(s
)) {
7873 fpst
= get_fpstatus_ptr(size
== MO_16
);
7876 unallocated_encoding(s
);
7880 if (size
== MO_64
) {
7881 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7882 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7883 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7885 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7886 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7889 case 0x3b: /* ADDP */
7890 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7892 case 0xc: /* FMAXNMP */
7893 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7895 case 0xd: /* FADDP */
7896 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7898 case 0xf: /* FMAXP */
7899 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7901 case 0x2c: /* FMINNMP */
7902 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7904 case 0x2f: /* FMINP */
7905 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7908 g_assert_not_reached();
7911 write_fp_dreg(s
, rd
, tcg_res
);
7913 tcg_temp_free_i64(tcg_op1
);
7914 tcg_temp_free_i64(tcg_op2
);
7915 tcg_temp_free_i64(tcg_res
);
7917 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7918 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7919 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7921 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7922 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7924 if (size
== MO_16
) {
7926 case 0xc: /* FMAXNMP */
7927 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7929 case 0xd: /* FADDP */
7930 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7932 case 0xf: /* FMAXP */
7933 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7935 case 0x2c: /* FMINNMP */
7936 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7938 case 0x2f: /* FMINP */
7939 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7942 g_assert_not_reached();
7946 case 0xc: /* FMAXNMP */
7947 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7949 case 0xd: /* FADDP */
7950 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7952 case 0xf: /* FMAXP */
7953 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7955 case 0x2c: /* FMINNMP */
7956 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7958 case 0x2f: /* FMINP */
7959 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7962 g_assert_not_reached();
7966 write_fp_sreg(s
, rd
, tcg_res
);
7968 tcg_temp_free_i32(tcg_op1
);
7969 tcg_temp_free_i32(tcg_op2
);
7970 tcg_temp_free_i32(tcg_res
);
7974 tcg_temp_free_ptr(fpst
);
7979 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7981 * This code is handles the common shifting code and is used by both
7982 * the vector and scalar code.
7984 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7985 TCGv_i64 tcg_rnd
, bool accumulate
,
7986 bool is_u
, int size
, int shift
)
7988 bool extended_result
= false;
7989 bool round
= tcg_rnd
!= NULL
;
7991 TCGv_i64 tcg_src_hi
;
7993 if (round
&& size
== 3) {
7994 extended_result
= true;
7995 ext_lshift
= 64 - shift
;
7996 tcg_src_hi
= tcg_temp_new_i64();
7997 } else if (shift
== 64) {
7998 if (!accumulate
&& is_u
) {
7999 /* result is zero */
8000 tcg_gen_movi_i64(tcg_res
, 0);
8005 /* Deal with the rounding step */
8007 if (extended_result
) {
8008 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8010 /* take care of sign extending tcg_res */
8011 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8012 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8013 tcg_src
, tcg_src_hi
,
8016 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8020 tcg_temp_free_i64(tcg_zero
);
8022 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8026 /* Now do the shift right */
8027 if (round
&& extended_result
) {
8028 /* extended case, >64 bit precision required */
8029 if (ext_lshift
== 0) {
8030 /* special case, only high bits matter */
8031 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8033 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8034 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8035 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8040 /* essentially shifting in 64 zeros */
8041 tcg_gen_movi_i64(tcg_src
, 0);
8043 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8047 /* effectively extending the sign-bit */
8048 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8050 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8056 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8058 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8061 if (extended_result
) {
8062 tcg_temp_free_i64(tcg_src_hi
);
8066 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8067 static void handle_scalar_simd_shri(DisasContext
*s
,
8068 bool is_u
, int immh
, int immb
,
8069 int opcode
, int rn
, int rd
)
8072 int immhb
= immh
<< 3 | immb
;
8073 int shift
= 2 * (8 << size
) - immhb
;
8074 bool accumulate
= false;
8076 bool insert
= false;
8081 if (!extract32(immh
, 3, 1)) {
8082 unallocated_encoding(s
);
8086 if (!fp_access_check(s
)) {
8091 case 0x02: /* SSRA / USRA (accumulate) */
8094 case 0x04: /* SRSHR / URSHR (rounding) */
8097 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8098 accumulate
= round
= true;
8100 case 0x08: /* SRI */
8106 uint64_t round_const
= 1ULL << (shift
- 1);
8107 tcg_round
= tcg_const_i64(round_const
);
8112 tcg_rn
= read_fp_dreg(s
, rn
);
8113 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8116 /* shift count same as element size is valid but does nothing;
8117 * special case to avoid potential shift by 64.
8119 int esize
= 8 << size
;
8120 if (shift
!= esize
) {
8121 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8122 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8125 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8126 accumulate
, is_u
, size
, shift
);
8129 write_fp_dreg(s
, rd
, tcg_rd
);
8131 tcg_temp_free_i64(tcg_rn
);
8132 tcg_temp_free_i64(tcg_rd
);
8134 tcg_temp_free_i64(tcg_round
);
8138 /* SHL/SLI - Scalar shift left */
8139 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8140 int immh
, int immb
, int opcode
,
8143 int size
= 32 - clz32(immh
) - 1;
8144 int immhb
= immh
<< 3 | immb
;
8145 int shift
= immhb
- (8 << size
);
8146 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8147 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8149 if (!extract32(immh
, 3, 1)) {
8150 unallocated_encoding(s
);
8154 if (!fp_access_check(s
)) {
8158 tcg_rn
= read_fp_dreg(s
, rn
);
8159 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8162 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8164 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8167 write_fp_dreg(s
, rd
, tcg_rd
);
8169 tcg_temp_free_i64(tcg_rn
);
8170 tcg_temp_free_i64(tcg_rd
);
8173 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8174 * (signed/unsigned) narrowing */
8175 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8176 bool is_u_shift
, bool is_u_narrow
,
8177 int immh
, int immb
, int opcode
,
8180 int immhb
= immh
<< 3 | immb
;
8181 int size
= 32 - clz32(immh
) - 1;
8182 int esize
= 8 << size
;
8183 int shift
= (2 * esize
) - immhb
;
8184 int elements
= is_scalar
? 1 : (64 / esize
);
8185 bool round
= extract32(opcode
, 0, 1);
8186 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8187 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8188 TCGv_i32 tcg_rd_narrowed
;
8191 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8192 { gen_helper_neon_narrow_sat_s8
,
8193 gen_helper_neon_unarrow_sat8
},
8194 { gen_helper_neon_narrow_sat_s16
,
8195 gen_helper_neon_unarrow_sat16
},
8196 { gen_helper_neon_narrow_sat_s32
,
8197 gen_helper_neon_unarrow_sat32
},
8200 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8201 gen_helper_neon_narrow_sat_u8
,
8202 gen_helper_neon_narrow_sat_u16
,
8203 gen_helper_neon_narrow_sat_u32
,
8206 NeonGenNarrowEnvFn
*narrowfn
;
8212 if (extract32(immh
, 3, 1)) {
8213 unallocated_encoding(s
);
8217 if (!fp_access_check(s
)) {
8222 narrowfn
= unsigned_narrow_fns
[size
];
8224 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8227 tcg_rn
= tcg_temp_new_i64();
8228 tcg_rd
= tcg_temp_new_i64();
8229 tcg_rd_narrowed
= tcg_temp_new_i32();
8230 tcg_final
= tcg_const_i64(0);
8233 uint64_t round_const
= 1ULL << (shift
- 1);
8234 tcg_round
= tcg_const_i64(round_const
);
8239 for (i
= 0; i
< elements
; i
++) {
8240 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8241 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8242 false, is_u_shift
, size
+1, shift
);
8243 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8244 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8245 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8249 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8251 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8255 tcg_temp_free_i64(tcg_round
);
8257 tcg_temp_free_i64(tcg_rn
);
8258 tcg_temp_free_i64(tcg_rd
);
8259 tcg_temp_free_i32(tcg_rd_narrowed
);
8260 tcg_temp_free_i64(tcg_final
);
8262 clear_vec_high(s
, is_q
, rd
);
8265 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8266 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8267 bool src_unsigned
, bool dst_unsigned
,
8268 int immh
, int immb
, int rn
, int rd
)
8270 int immhb
= immh
<< 3 | immb
;
8271 int size
= 32 - clz32(immh
) - 1;
8272 int shift
= immhb
- (8 << size
);
8276 assert(!(scalar
&& is_q
));
8279 if (!is_q
&& extract32(immh
, 3, 1)) {
8280 unallocated_encoding(s
);
8284 /* Since we use the variable-shift helpers we must
8285 * replicate the shift count into each element of
8286 * the tcg_shift value.
8290 shift
|= shift
<< 8;
8293 shift
|= shift
<< 16;
8299 g_assert_not_reached();
8303 if (!fp_access_check(s
)) {
8308 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8309 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8310 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8311 { NULL
, gen_helper_neon_qshl_u64
},
8313 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8314 int maxpass
= is_q
? 2 : 1;
8316 for (pass
= 0; pass
< maxpass
; pass
++) {
8317 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8319 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8320 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8321 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8323 tcg_temp_free_i64(tcg_op
);
8325 tcg_temp_free_i64(tcg_shift
);
8326 clear_vec_high(s
, is_q
, rd
);
8328 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8329 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8331 { gen_helper_neon_qshl_s8
,
8332 gen_helper_neon_qshl_s16
,
8333 gen_helper_neon_qshl_s32
},
8334 { gen_helper_neon_qshlu_s8
,
8335 gen_helper_neon_qshlu_s16
,
8336 gen_helper_neon_qshlu_s32
}
8338 { NULL
, NULL
, NULL
},
8339 { gen_helper_neon_qshl_u8
,
8340 gen_helper_neon_qshl_u16
,
8341 gen_helper_neon_qshl_u32
}
8344 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8345 MemOp memop
= scalar
? size
: MO_32
;
8346 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8348 for (pass
= 0; pass
< maxpass
; pass
++) {
8349 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8351 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8352 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8356 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8359 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8364 g_assert_not_reached();
8366 write_fp_sreg(s
, rd
, tcg_op
);
8368 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8371 tcg_temp_free_i32(tcg_op
);
8373 tcg_temp_free_i32(tcg_shift
);
8376 clear_vec_high(s
, is_q
, rd
);
8381 /* Common vector code for handling integer to FP conversion */
8382 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8383 int elements
, int is_signed
,
8384 int fracbits
, int size
)
8386 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8387 TCGv_i32 tcg_shift
= NULL
;
8389 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8392 if (fracbits
|| size
== MO_64
) {
8393 tcg_shift
= tcg_const_i32(fracbits
);
8396 if (size
== MO_64
) {
8397 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8398 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8400 for (pass
= 0; pass
< elements
; pass
++) {
8401 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8404 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8405 tcg_shift
, tcg_fpst
);
8407 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8408 tcg_shift
, tcg_fpst
);
8410 if (elements
== 1) {
8411 write_fp_dreg(s
, rd
, tcg_double
);
8413 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8417 tcg_temp_free_i64(tcg_int64
);
8418 tcg_temp_free_i64(tcg_double
);
8421 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8422 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8424 for (pass
= 0; pass
< elements
; pass
++) {
8425 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8431 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8432 tcg_shift
, tcg_fpst
);
8434 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8435 tcg_shift
, tcg_fpst
);
8439 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8441 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8448 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8449 tcg_shift
, tcg_fpst
);
8451 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8452 tcg_shift
, tcg_fpst
);
8456 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8458 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8463 g_assert_not_reached();
8466 if (elements
== 1) {
8467 write_fp_sreg(s
, rd
, tcg_float
);
8469 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8473 tcg_temp_free_i32(tcg_int32
);
8474 tcg_temp_free_i32(tcg_float
);
8477 tcg_temp_free_ptr(tcg_fpst
);
8479 tcg_temp_free_i32(tcg_shift
);
8482 clear_vec_high(s
, elements
<< size
== 16, rd
);
8485 /* UCVTF/SCVTF - Integer to FP conversion */
8486 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8487 bool is_q
, bool is_u
,
8488 int immh
, int immb
, int opcode
,
8491 int size
, elements
, fracbits
;
8492 int immhb
= immh
<< 3 | immb
;
8496 if (!is_scalar
&& !is_q
) {
8497 unallocated_encoding(s
);
8500 } else if (immh
& 4) {
8502 } else if (immh
& 2) {
8504 if (!dc_isar_feature(aa64_fp16
, s
)) {
8505 unallocated_encoding(s
);
8509 /* immh == 0 would be a failure of the decode logic */
8510 g_assert(immh
== 1);
8511 unallocated_encoding(s
);
8518 elements
= (8 << is_q
) >> size
;
8520 fracbits
= (16 << size
) - immhb
;
8522 if (!fp_access_check(s
)) {
8526 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8529 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8530 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8531 bool is_q
, bool is_u
,
8532 int immh
, int immb
, int rn
, int rd
)
8534 int immhb
= immh
<< 3 | immb
;
8535 int pass
, size
, fracbits
;
8536 TCGv_ptr tcg_fpstatus
;
8537 TCGv_i32 tcg_rmode
, tcg_shift
;
8541 if (!is_scalar
&& !is_q
) {
8542 unallocated_encoding(s
);
8545 } else if (immh
& 0x4) {
8547 } else if (immh
& 0x2) {
8549 if (!dc_isar_feature(aa64_fp16
, s
)) {
8550 unallocated_encoding(s
);
8554 /* Should have split out AdvSIMD modified immediate earlier. */
8556 unallocated_encoding(s
);
8560 if (!fp_access_check(s
)) {
8564 assert(!(is_scalar
&& is_q
));
8566 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8567 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8568 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8569 fracbits
= (16 << size
) - immhb
;
8570 tcg_shift
= tcg_const_i32(fracbits
);
8572 if (size
== MO_64
) {
8573 int maxpass
= is_scalar
? 1 : 2;
8575 for (pass
= 0; pass
< maxpass
; pass
++) {
8576 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8578 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8580 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8582 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8584 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8585 tcg_temp_free_i64(tcg_op
);
8587 clear_vec_high(s
, is_q
, rd
);
8589 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8590 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8595 fn
= gen_helper_vfp_touhh
;
8597 fn
= gen_helper_vfp_toshh
;
8602 fn
= gen_helper_vfp_touls
;
8604 fn
= gen_helper_vfp_tosls
;
8608 g_assert_not_reached();
8611 for (pass
= 0; pass
< maxpass
; pass
++) {
8612 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8614 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8615 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8617 write_fp_sreg(s
, rd
, tcg_op
);
8619 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8621 tcg_temp_free_i32(tcg_op
);
8624 clear_vec_high(s
, is_q
, rd
);
8628 tcg_temp_free_ptr(tcg_fpstatus
);
8629 tcg_temp_free_i32(tcg_shift
);
8630 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8631 tcg_temp_free_i32(tcg_rmode
);
8634 /* AdvSIMD scalar shift by immediate
8635 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8636 * +-----+---+-------------+------+------+--------+---+------+------+
8637 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8638 * +-----+---+-------------+------+------+--------+---+------+------+
8640 * This is the scalar version so it works on a fixed sized registers
8642 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8644 int rd
= extract32(insn
, 0, 5);
8645 int rn
= extract32(insn
, 5, 5);
8646 int opcode
= extract32(insn
, 11, 5);
8647 int immb
= extract32(insn
, 16, 3);
8648 int immh
= extract32(insn
, 19, 4);
8649 bool is_u
= extract32(insn
, 29, 1);
8652 unallocated_encoding(s
);
8657 case 0x08: /* SRI */
8659 unallocated_encoding(s
);
8663 case 0x00: /* SSHR / USHR */
8664 case 0x02: /* SSRA / USRA */
8665 case 0x04: /* SRSHR / URSHR */
8666 case 0x06: /* SRSRA / URSRA */
8667 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8669 case 0x0a: /* SHL / SLI */
8670 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8672 case 0x1c: /* SCVTF, UCVTF */
8673 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8676 case 0x10: /* SQSHRUN, SQSHRUN2 */
8677 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8679 unallocated_encoding(s
);
8682 handle_vec_simd_sqshrn(s
, true, false, false, true,
8683 immh
, immb
, opcode
, rn
, rd
);
8685 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8686 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8687 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8688 immh
, immb
, opcode
, rn
, rd
);
8690 case 0xc: /* SQSHLU */
8692 unallocated_encoding(s
);
8695 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8697 case 0xe: /* SQSHL, UQSHL */
8698 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8700 case 0x1f: /* FCVTZS, FCVTZU */
8701 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8704 unallocated_encoding(s
);
8709 /* AdvSIMD scalar three different
8710 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8711 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8712 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8713 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8715 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8717 bool is_u
= extract32(insn
, 29, 1);
8718 int size
= extract32(insn
, 22, 2);
8719 int opcode
= extract32(insn
, 12, 4);
8720 int rm
= extract32(insn
, 16, 5);
8721 int rn
= extract32(insn
, 5, 5);
8722 int rd
= extract32(insn
, 0, 5);
8725 unallocated_encoding(s
);
8730 case 0x9: /* SQDMLAL, SQDMLAL2 */
8731 case 0xb: /* SQDMLSL, SQDMLSL2 */
8732 case 0xd: /* SQDMULL, SQDMULL2 */
8733 if (size
== 0 || size
== 3) {
8734 unallocated_encoding(s
);
8739 unallocated_encoding(s
);
8743 if (!fp_access_check(s
)) {
8748 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8749 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8750 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8752 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8753 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8755 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8756 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8759 case 0xd: /* SQDMULL, SQDMULL2 */
8761 case 0xb: /* SQDMLSL, SQDMLSL2 */
8762 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8764 case 0x9: /* SQDMLAL, SQDMLAL2 */
8765 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8766 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8770 g_assert_not_reached();
8773 write_fp_dreg(s
, rd
, tcg_res
);
8775 tcg_temp_free_i64(tcg_op1
);
8776 tcg_temp_free_i64(tcg_op2
);
8777 tcg_temp_free_i64(tcg_res
);
8779 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8780 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8781 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8783 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8784 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8787 case 0xd: /* SQDMULL, SQDMULL2 */
8789 case 0xb: /* SQDMLSL, SQDMLSL2 */
8790 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8792 case 0x9: /* SQDMLAL, SQDMLAL2 */
8794 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8795 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8796 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8798 tcg_temp_free_i64(tcg_op3
);
8802 g_assert_not_reached();
8805 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8806 write_fp_dreg(s
, rd
, tcg_res
);
8808 tcg_temp_free_i32(tcg_op1
);
8809 tcg_temp_free_i32(tcg_op2
);
8810 tcg_temp_free_i64(tcg_res
);
8814 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8815 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8817 /* Handle 64x64->64 opcodes which are shared between the scalar
8818 * and vector 3-same groups. We cover every opcode where size == 3
8819 * is valid in either the three-reg-same (integer, not pairwise)
8820 * or scalar-three-reg-same groups.
8825 case 0x1: /* SQADD */
8827 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8829 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8832 case 0x5: /* SQSUB */
8834 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8836 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8839 case 0x6: /* CMGT, CMHI */
8840 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8841 * We implement this using setcond (test) and then negating.
8843 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8845 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8846 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8848 case 0x7: /* CMGE, CMHS */
8849 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8851 case 0x11: /* CMTST, CMEQ */
8856 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8858 case 0x8: /* SSHL, USHL */
8860 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8862 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8865 case 0x9: /* SQSHL, UQSHL */
8867 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8869 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8872 case 0xa: /* SRSHL, URSHL */
8874 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8876 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8879 case 0xb: /* SQRSHL, UQRSHL */
8881 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8883 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8886 case 0x10: /* ADD, SUB */
8888 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8890 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8894 g_assert_not_reached();
8898 /* Handle the 3-same-operands float operations; shared by the scalar
8899 * and vector encodings. The caller must filter out any encodings
8900 * not allocated for the encoding it is dealing with.
8902 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8903 int fpopcode
, int rd
, int rn
, int rm
)
8906 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8908 for (pass
= 0; pass
< elements
; pass
++) {
8911 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8912 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8913 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8915 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8916 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8919 case 0x39: /* FMLS */
8920 /* As usual for ARM, separate negation for fused multiply-add */
8921 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8923 case 0x19: /* FMLA */
8924 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8925 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8928 case 0x18: /* FMAXNM */
8929 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8931 case 0x1a: /* FADD */
8932 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8934 case 0x1b: /* FMULX */
8935 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8937 case 0x1c: /* FCMEQ */
8938 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8940 case 0x1e: /* FMAX */
8941 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8943 case 0x1f: /* FRECPS */
8944 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8946 case 0x38: /* FMINNM */
8947 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8949 case 0x3a: /* FSUB */
8950 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8952 case 0x3e: /* FMIN */
8953 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8955 case 0x3f: /* FRSQRTS */
8956 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8958 case 0x5b: /* FMUL */
8959 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8961 case 0x5c: /* FCMGE */
8962 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8964 case 0x5d: /* FACGE */
8965 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8967 case 0x5f: /* FDIV */
8968 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8970 case 0x7a: /* FABD */
8971 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8972 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8974 case 0x7c: /* FCMGT */
8975 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8977 case 0x7d: /* FACGT */
8978 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8981 g_assert_not_reached();
8984 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8986 tcg_temp_free_i64(tcg_res
);
8987 tcg_temp_free_i64(tcg_op1
);
8988 tcg_temp_free_i64(tcg_op2
);
8991 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8992 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8993 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8995 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8996 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8999 case 0x39: /* FMLS */
9000 /* As usual for ARM, separate negation for fused multiply-add */
9001 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9003 case 0x19: /* FMLA */
9004 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9005 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9008 case 0x1a: /* FADD */
9009 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9011 case 0x1b: /* FMULX */
9012 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9014 case 0x1c: /* FCMEQ */
9015 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9017 case 0x1e: /* FMAX */
9018 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9020 case 0x1f: /* FRECPS */
9021 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9023 case 0x18: /* FMAXNM */
9024 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9026 case 0x38: /* FMINNM */
9027 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9029 case 0x3a: /* FSUB */
9030 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9032 case 0x3e: /* FMIN */
9033 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9035 case 0x3f: /* FRSQRTS */
9036 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9038 case 0x5b: /* FMUL */
9039 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9041 case 0x5c: /* FCMGE */
9042 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9044 case 0x5d: /* FACGE */
9045 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9047 case 0x5f: /* FDIV */
9048 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9050 case 0x7a: /* FABD */
9051 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9052 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9054 case 0x7c: /* FCMGT */
9055 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9057 case 0x7d: /* FACGT */
9058 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9061 g_assert_not_reached();
9064 if (elements
== 1) {
9065 /* scalar single so clear high part */
9066 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9068 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9069 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9070 tcg_temp_free_i64(tcg_tmp
);
9072 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9075 tcg_temp_free_i32(tcg_res
);
9076 tcg_temp_free_i32(tcg_op1
);
9077 tcg_temp_free_i32(tcg_op2
);
9081 tcg_temp_free_ptr(fpst
);
9083 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9086 /* AdvSIMD scalar three same
9087 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9088 * +-----+---+-----------+------+---+------+--------+---+------+------+
9089 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9090 * +-----+---+-----------+------+---+------+--------+---+------+------+
9092 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9094 int rd
= extract32(insn
, 0, 5);
9095 int rn
= extract32(insn
, 5, 5);
9096 int opcode
= extract32(insn
, 11, 5);
9097 int rm
= extract32(insn
, 16, 5);
9098 int size
= extract32(insn
, 22, 2);
9099 bool u
= extract32(insn
, 29, 1);
9102 if (opcode
>= 0x18) {
9103 /* Floating point: U, size[1] and opcode indicate operation */
9104 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9106 case 0x1b: /* FMULX */
9107 case 0x1f: /* FRECPS */
9108 case 0x3f: /* FRSQRTS */
9109 case 0x5d: /* FACGE */
9110 case 0x7d: /* FACGT */
9111 case 0x1c: /* FCMEQ */
9112 case 0x5c: /* FCMGE */
9113 case 0x7c: /* FCMGT */
9114 case 0x7a: /* FABD */
9117 unallocated_encoding(s
);
9121 if (!fp_access_check(s
)) {
9125 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9130 case 0x1: /* SQADD, UQADD */
9131 case 0x5: /* SQSUB, UQSUB */
9132 case 0x9: /* SQSHL, UQSHL */
9133 case 0xb: /* SQRSHL, UQRSHL */
9135 case 0x8: /* SSHL, USHL */
9136 case 0xa: /* SRSHL, URSHL */
9137 case 0x6: /* CMGT, CMHI */
9138 case 0x7: /* CMGE, CMHS */
9139 case 0x11: /* CMTST, CMEQ */
9140 case 0x10: /* ADD, SUB (vector) */
9142 unallocated_encoding(s
);
9146 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9147 if (size
!= 1 && size
!= 2) {
9148 unallocated_encoding(s
);
9153 unallocated_encoding(s
);
9157 if (!fp_access_check(s
)) {
9161 tcg_rd
= tcg_temp_new_i64();
9164 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9165 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9167 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9168 tcg_temp_free_i64(tcg_rn
);
9169 tcg_temp_free_i64(tcg_rm
);
9171 /* Do a single operation on the lowest element in the vector.
9172 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9173 * no side effects for all these operations.
9174 * OPTME: special-purpose helpers would avoid doing some
9175 * unnecessary work in the helper for the 8 and 16 bit cases.
9177 NeonGenTwoOpEnvFn
*genenvfn
;
9178 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9179 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9180 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9182 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9183 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9186 case 0x1: /* SQADD, UQADD */
9188 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9189 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9190 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9191 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9193 genenvfn
= fns
[size
][u
];
9196 case 0x5: /* SQSUB, UQSUB */
9198 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9199 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9200 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9201 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9203 genenvfn
= fns
[size
][u
];
9206 case 0x9: /* SQSHL, UQSHL */
9208 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9209 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9210 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9211 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9213 genenvfn
= fns
[size
][u
];
9216 case 0xb: /* SQRSHL, UQRSHL */
9218 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9219 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9220 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9221 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9223 genenvfn
= fns
[size
][u
];
9226 case 0x16: /* SQDMULH, SQRDMULH */
9228 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9229 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9230 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9232 assert(size
== 1 || size
== 2);
9233 genenvfn
= fns
[size
- 1][u
];
9237 g_assert_not_reached();
9240 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9241 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9242 tcg_temp_free_i32(tcg_rd32
);
9243 tcg_temp_free_i32(tcg_rn
);
9244 tcg_temp_free_i32(tcg_rm
);
9247 write_fp_dreg(s
, rd
, tcg_rd
);
9249 tcg_temp_free_i64(tcg_rd
);
9252 /* AdvSIMD scalar three same FP16
9253 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9254 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9255 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9256 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9257 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9258 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9260 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9263 int rd
= extract32(insn
, 0, 5);
9264 int rn
= extract32(insn
, 5, 5);
9265 int opcode
= extract32(insn
, 11, 3);
9266 int rm
= extract32(insn
, 16, 5);
9267 bool u
= extract32(insn
, 29, 1);
9268 bool a
= extract32(insn
, 23, 1);
9269 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9276 case 0x03: /* FMULX */
9277 case 0x04: /* FCMEQ (reg) */
9278 case 0x07: /* FRECPS */
9279 case 0x0f: /* FRSQRTS */
9280 case 0x14: /* FCMGE (reg) */
9281 case 0x15: /* FACGE */
9282 case 0x1a: /* FABD */
9283 case 0x1c: /* FCMGT (reg) */
9284 case 0x1d: /* FACGT */
9287 unallocated_encoding(s
);
9291 if (!dc_isar_feature(aa64_fp16
, s
)) {
9292 unallocated_encoding(s
);
9295 if (!fp_access_check(s
)) {
9299 fpst
= get_fpstatus_ptr(true);
9301 tcg_op1
= read_fp_hreg(s
, rn
);
9302 tcg_op2
= read_fp_hreg(s
, rm
);
9303 tcg_res
= tcg_temp_new_i32();
9306 case 0x03: /* FMULX */
9307 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9309 case 0x04: /* FCMEQ (reg) */
9310 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9312 case 0x07: /* FRECPS */
9313 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9315 case 0x0f: /* FRSQRTS */
9316 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9318 case 0x14: /* FCMGE (reg) */
9319 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9321 case 0x15: /* FACGE */
9322 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9324 case 0x1a: /* FABD */
9325 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9326 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9328 case 0x1c: /* FCMGT (reg) */
9329 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9331 case 0x1d: /* FACGT */
9332 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9335 g_assert_not_reached();
9338 write_fp_sreg(s
, rd
, tcg_res
);
9341 tcg_temp_free_i32(tcg_res
);
9342 tcg_temp_free_i32(tcg_op1
);
9343 tcg_temp_free_i32(tcg_op2
);
9344 tcg_temp_free_ptr(fpst
);
9347 /* AdvSIMD scalar three same extra
9348 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9349 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9350 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9351 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9353 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9356 int rd
= extract32(insn
, 0, 5);
9357 int rn
= extract32(insn
, 5, 5);
9358 int opcode
= extract32(insn
, 11, 4);
9359 int rm
= extract32(insn
, 16, 5);
9360 int size
= extract32(insn
, 22, 2);
9361 bool u
= extract32(insn
, 29, 1);
9362 TCGv_i32 ele1
, ele2
, ele3
;
9366 switch (u
* 16 + opcode
) {
9367 case 0x10: /* SQRDMLAH (vector) */
9368 case 0x11: /* SQRDMLSH (vector) */
9369 if (size
!= 1 && size
!= 2) {
9370 unallocated_encoding(s
);
9373 feature
= dc_isar_feature(aa64_rdm
, s
);
9376 unallocated_encoding(s
);
9380 unallocated_encoding(s
);
9383 if (!fp_access_check(s
)) {
9387 /* Do a single operation on the lowest element in the vector.
9388 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9389 * with no side effects for all these operations.
9390 * OPTME: special-purpose helpers would avoid doing some
9391 * unnecessary work in the helper for the 16 bit cases.
9393 ele1
= tcg_temp_new_i32();
9394 ele2
= tcg_temp_new_i32();
9395 ele3
= tcg_temp_new_i32();
9397 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9398 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9399 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9402 case 0x0: /* SQRDMLAH */
9404 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9406 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9409 case 0x1: /* SQRDMLSH */
9411 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9413 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9417 g_assert_not_reached();
9419 tcg_temp_free_i32(ele1
);
9420 tcg_temp_free_i32(ele2
);
9422 res
= tcg_temp_new_i64();
9423 tcg_gen_extu_i32_i64(res
, ele3
);
9424 tcg_temp_free_i32(ele3
);
9426 write_fp_dreg(s
, rd
, res
);
9427 tcg_temp_free_i64(res
);
9430 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9431 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9432 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9434 /* Handle 64->64 opcodes which are shared between the scalar and
9435 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9436 * is valid in either group and also the double-precision fp ops.
9437 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9443 case 0x4: /* CLS, CLZ */
9445 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9447 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9451 /* This opcode is shared with CNT and RBIT but we have earlier
9452 * enforced that size == 3 if and only if this is the NOT insn.
9454 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9456 case 0x7: /* SQABS, SQNEG */
9458 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9460 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9463 case 0xa: /* CMLT */
9464 /* 64 bit integer comparison against zero, result is
9465 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9470 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9471 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9473 case 0x8: /* CMGT, CMGE */
9474 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9476 case 0x9: /* CMEQ, CMLE */
9477 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9479 case 0xb: /* ABS, NEG */
9481 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9483 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9486 case 0x2f: /* FABS */
9487 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9489 case 0x6f: /* FNEG */
9490 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9492 case 0x7f: /* FSQRT */
9493 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9495 case 0x1a: /* FCVTNS */
9496 case 0x1b: /* FCVTMS */
9497 case 0x1c: /* FCVTAS */
9498 case 0x3a: /* FCVTPS */
9499 case 0x3b: /* FCVTZS */
9501 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9502 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9503 tcg_temp_free_i32(tcg_shift
);
9506 case 0x5a: /* FCVTNU */
9507 case 0x5b: /* FCVTMU */
9508 case 0x5c: /* FCVTAU */
9509 case 0x7a: /* FCVTPU */
9510 case 0x7b: /* FCVTZU */
9512 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9513 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9514 tcg_temp_free_i32(tcg_shift
);
9517 case 0x18: /* FRINTN */
9518 case 0x19: /* FRINTM */
9519 case 0x38: /* FRINTP */
9520 case 0x39: /* FRINTZ */
9521 case 0x58: /* FRINTA */
9522 case 0x79: /* FRINTI */
9523 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9525 case 0x59: /* FRINTX */
9526 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9528 case 0x1e: /* FRINT32Z */
9529 case 0x5e: /* FRINT32X */
9530 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9532 case 0x1f: /* FRINT64Z */
9533 case 0x5f: /* FRINT64X */
9534 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9537 g_assert_not_reached();
9541 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9542 bool is_scalar
, bool is_u
, bool is_q
,
9543 int size
, int rn
, int rd
)
9545 bool is_double
= (size
== MO_64
);
9548 if (!fp_access_check(s
)) {
9552 fpst
= get_fpstatus_ptr(size
== MO_16
);
9555 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9556 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9557 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9558 NeonGenTwoDoubleOpFn
*genfn
;
9563 case 0x2e: /* FCMLT (zero) */
9566 case 0x2c: /* FCMGT (zero) */
9567 genfn
= gen_helper_neon_cgt_f64
;
9569 case 0x2d: /* FCMEQ (zero) */
9570 genfn
= gen_helper_neon_ceq_f64
;
9572 case 0x6d: /* FCMLE (zero) */
9575 case 0x6c: /* FCMGE (zero) */
9576 genfn
= gen_helper_neon_cge_f64
;
9579 g_assert_not_reached();
9582 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9583 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9585 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9587 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9589 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9591 tcg_temp_free_i64(tcg_res
);
9592 tcg_temp_free_i64(tcg_zero
);
9593 tcg_temp_free_i64(tcg_op
);
9595 clear_vec_high(s
, !is_scalar
, rd
);
9597 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9598 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9599 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9600 NeonGenTwoSingleOpFn
*genfn
;
9602 int pass
, maxpasses
;
9604 if (size
== MO_16
) {
9606 case 0x2e: /* FCMLT (zero) */
9609 case 0x2c: /* FCMGT (zero) */
9610 genfn
= gen_helper_advsimd_cgt_f16
;
9612 case 0x2d: /* FCMEQ (zero) */
9613 genfn
= gen_helper_advsimd_ceq_f16
;
9615 case 0x6d: /* FCMLE (zero) */
9618 case 0x6c: /* FCMGE (zero) */
9619 genfn
= gen_helper_advsimd_cge_f16
;
9622 g_assert_not_reached();
9626 case 0x2e: /* FCMLT (zero) */
9629 case 0x2c: /* FCMGT (zero) */
9630 genfn
= gen_helper_neon_cgt_f32
;
9632 case 0x2d: /* FCMEQ (zero) */
9633 genfn
= gen_helper_neon_ceq_f32
;
9635 case 0x6d: /* FCMLE (zero) */
9638 case 0x6c: /* FCMGE (zero) */
9639 genfn
= gen_helper_neon_cge_f32
;
9642 g_assert_not_reached();
9649 int vector_size
= 8 << is_q
;
9650 maxpasses
= vector_size
>> size
;
9653 for (pass
= 0; pass
< maxpasses
; pass
++) {
9654 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9656 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9658 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9661 write_fp_sreg(s
, rd
, tcg_res
);
9663 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9666 tcg_temp_free_i32(tcg_res
);
9667 tcg_temp_free_i32(tcg_zero
);
9668 tcg_temp_free_i32(tcg_op
);
9670 clear_vec_high(s
, is_q
, rd
);
9674 tcg_temp_free_ptr(fpst
);
9677 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9678 bool is_scalar
, bool is_u
, bool is_q
,
9679 int size
, int rn
, int rd
)
9681 bool is_double
= (size
== 3);
9682 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9685 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9686 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9689 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9690 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9692 case 0x3d: /* FRECPE */
9693 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9695 case 0x3f: /* FRECPX */
9696 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9698 case 0x7d: /* FRSQRTE */
9699 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9702 g_assert_not_reached();
9704 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9706 tcg_temp_free_i64(tcg_res
);
9707 tcg_temp_free_i64(tcg_op
);
9708 clear_vec_high(s
, !is_scalar
, rd
);
9710 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9711 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9712 int pass
, maxpasses
;
9717 maxpasses
= is_q
? 4 : 2;
9720 for (pass
= 0; pass
< maxpasses
; pass
++) {
9721 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9724 case 0x3c: /* URECPE */
9725 gen_helper_recpe_u32(tcg_res
, tcg_op
);
9727 case 0x3d: /* FRECPE */
9728 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9730 case 0x3f: /* FRECPX */
9731 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9733 case 0x7d: /* FRSQRTE */
9734 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9737 g_assert_not_reached();
9741 write_fp_sreg(s
, rd
, tcg_res
);
9743 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9746 tcg_temp_free_i32(tcg_res
);
9747 tcg_temp_free_i32(tcg_op
);
9749 clear_vec_high(s
, is_q
, rd
);
9752 tcg_temp_free_ptr(fpst
);
9755 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9756 int opcode
, bool u
, bool is_q
,
9757 int size
, int rn
, int rd
)
9759 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9760 * in the source becomes a size element in the destination).
9763 TCGv_i32 tcg_res
[2];
9764 int destelt
= is_q
? 2 : 0;
9765 int passes
= scalar
? 1 : 2;
9768 tcg_res
[1] = tcg_const_i32(0);
9771 for (pass
= 0; pass
< passes
; pass
++) {
9772 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9773 NeonGenNarrowFn
*genfn
= NULL
;
9774 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9777 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9779 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9781 tcg_res
[pass
] = tcg_temp_new_i32();
9784 case 0x12: /* XTN, SQXTUN */
9786 static NeonGenNarrowFn
* const xtnfns
[3] = {
9787 gen_helper_neon_narrow_u8
,
9788 gen_helper_neon_narrow_u16
,
9789 tcg_gen_extrl_i64_i32
,
9791 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9792 gen_helper_neon_unarrow_sat8
,
9793 gen_helper_neon_unarrow_sat16
,
9794 gen_helper_neon_unarrow_sat32
,
9797 genenvfn
= sqxtunfns
[size
];
9799 genfn
= xtnfns
[size
];
9803 case 0x14: /* SQXTN, UQXTN */
9805 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9806 { gen_helper_neon_narrow_sat_s8
,
9807 gen_helper_neon_narrow_sat_u8
},
9808 { gen_helper_neon_narrow_sat_s16
,
9809 gen_helper_neon_narrow_sat_u16
},
9810 { gen_helper_neon_narrow_sat_s32
,
9811 gen_helper_neon_narrow_sat_u32
},
9813 genenvfn
= fns
[size
][u
];
9816 case 0x16: /* FCVTN, FCVTN2 */
9817 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9819 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9821 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9822 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9823 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9824 TCGv_i32 ahp
= get_ahp_flag();
9826 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9827 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9828 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9829 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9830 tcg_temp_free_i32(tcg_lo
);
9831 tcg_temp_free_i32(tcg_hi
);
9832 tcg_temp_free_ptr(fpst
);
9833 tcg_temp_free_i32(ahp
);
9836 case 0x56: /* FCVTXN, FCVTXN2 */
9837 /* 64 bit to 32 bit float conversion
9838 * with von Neumann rounding (round to odd)
9841 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9844 g_assert_not_reached();
9848 genfn(tcg_res
[pass
], tcg_op
);
9849 } else if (genenvfn
) {
9850 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9853 tcg_temp_free_i64(tcg_op
);
9856 for (pass
= 0; pass
< 2; pass
++) {
9857 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9858 tcg_temp_free_i32(tcg_res
[pass
]);
9860 clear_vec_high(s
, is_q
, rd
);
9863 /* Remaining saturating accumulating ops */
9864 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9865 bool is_q
, int size
, int rn
, int rd
)
9867 bool is_double
= (size
== 3);
9870 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9871 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9874 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9875 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9876 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9878 if (is_u
) { /* USQADD */
9879 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9880 } else { /* SUQADD */
9881 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9883 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9885 tcg_temp_free_i64(tcg_rd
);
9886 tcg_temp_free_i64(tcg_rn
);
9887 clear_vec_high(s
, !is_scalar
, rd
);
9889 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9890 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9891 int pass
, maxpasses
;
9896 maxpasses
= is_q
? 4 : 2;
9899 for (pass
= 0; pass
< maxpasses
; pass
++) {
9901 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9902 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9904 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9905 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9908 if (is_u
) { /* USQADD */
9911 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9914 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9917 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9920 g_assert_not_reached();
9922 } else { /* SUQADD */
9925 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9928 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9931 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9934 g_assert_not_reached();
9939 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9940 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9941 tcg_temp_free_i64(tcg_zero
);
9943 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9945 tcg_temp_free_i32(tcg_rd
);
9946 tcg_temp_free_i32(tcg_rn
);
9947 clear_vec_high(s
, is_q
, rd
);
9951 /* AdvSIMD scalar two reg misc
9952 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9953 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9954 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9955 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9957 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9959 int rd
= extract32(insn
, 0, 5);
9960 int rn
= extract32(insn
, 5, 5);
9961 int opcode
= extract32(insn
, 12, 5);
9962 int size
= extract32(insn
, 22, 2);
9963 bool u
= extract32(insn
, 29, 1);
9964 bool is_fcvt
= false;
9967 TCGv_ptr tcg_fpstatus
;
9970 case 0x3: /* USQADD / SUQADD*/
9971 if (!fp_access_check(s
)) {
9974 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9976 case 0x7: /* SQABS / SQNEG */
9978 case 0xa: /* CMLT */
9980 unallocated_encoding(s
);
9984 case 0x8: /* CMGT, CMGE */
9985 case 0x9: /* CMEQ, CMLE */
9986 case 0xb: /* ABS, NEG */
9988 unallocated_encoding(s
);
9992 case 0x12: /* SQXTUN */
9994 unallocated_encoding(s
);
9998 case 0x14: /* SQXTN, UQXTN */
10000 unallocated_encoding(s
);
10003 if (!fp_access_check(s
)) {
10006 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10009 case 0x16 ... 0x1d:
10011 /* Floating point: U, size[1] and opcode indicate operation;
10012 * size[0] indicates single or double precision.
10014 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10015 size
= extract32(size
, 0, 1) ? 3 : 2;
10017 case 0x2c: /* FCMGT (zero) */
10018 case 0x2d: /* FCMEQ (zero) */
10019 case 0x2e: /* FCMLT (zero) */
10020 case 0x6c: /* FCMGE (zero) */
10021 case 0x6d: /* FCMLE (zero) */
10022 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10024 case 0x1d: /* SCVTF */
10025 case 0x5d: /* UCVTF */
10027 bool is_signed
= (opcode
== 0x1d);
10028 if (!fp_access_check(s
)) {
10031 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10034 case 0x3d: /* FRECPE */
10035 case 0x3f: /* FRECPX */
10036 case 0x7d: /* FRSQRTE */
10037 if (!fp_access_check(s
)) {
10040 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10042 case 0x1a: /* FCVTNS */
10043 case 0x1b: /* FCVTMS */
10044 case 0x3a: /* FCVTPS */
10045 case 0x3b: /* FCVTZS */
10046 case 0x5a: /* FCVTNU */
10047 case 0x5b: /* FCVTMU */
10048 case 0x7a: /* FCVTPU */
10049 case 0x7b: /* FCVTZU */
10051 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10053 case 0x1c: /* FCVTAS */
10054 case 0x5c: /* FCVTAU */
10055 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10057 rmode
= FPROUNDING_TIEAWAY
;
10059 case 0x56: /* FCVTXN, FCVTXN2 */
10061 unallocated_encoding(s
);
10064 if (!fp_access_check(s
)) {
10067 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10070 unallocated_encoding(s
);
10075 unallocated_encoding(s
);
10079 if (!fp_access_check(s
)) {
10084 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10085 tcg_fpstatus
= get_fpstatus_ptr(false);
10086 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10089 tcg_fpstatus
= NULL
;
10093 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10094 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10096 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10097 write_fp_dreg(s
, rd
, tcg_rd
);
10098 tcg_temp_free_i64(tcg_rd
);
10099 tcg_temp_free_i64(tcg_rn
);
10101 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10102 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10104 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10107 case 0x7: /* SQABS, SQNEG */
10109 NeonGenOneOpEnvFn
*genfn
;
10110 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10111 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10112 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10113 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10115 genfn
= fns
[size
][u
];
10116 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10119 case 0x1a: /* FCVTNS */
10120 case 0x1b: /* FCVTMS */
10121 case 0x1c: /* FCVTAS */
10122 case 0x3a: /* FCVTPS */
10123 case 0x3b: /* FCVTZS */
10125 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10126 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10127 tcg_temp_free_i32(tcg_shift
);
10130 case 0x5a: /* FCVTNU */
10131 case 0x5b: /* FCVTMU */
10132 case 0x5c: /* FCVTAU */
10133 case 0x7a: /* FCVTPU */
10134 case 0x7b: /* FCVTZU */
10136 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10137 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10138 tcg_temp_free_i32(tcg_shift
);
10142 g_assert_not_reached();
10145 write_fp_sreg(s
, rd
, tcg_rd
);
10146 tcg_temp_free_i32(tcg_rd
);
10147 tcg_temp_free_i32(tcg_rn
);
10151 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10152 tcg_temp_free_i32(tcg_rmode
);
10153 tcg_temp_free_ptr(tcg_fpstatus
);
10157 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10158 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10159 int immh
, int immb
, int opcode
, int rn
, int rd
)
10161 int size
= 32 - clz32(immh
) - 1;
10162 int immhb
= immh
<< 3 | immb
;
10163 int shift
= 2 * (8 << size
) - immhb
;
10164 GVecGen2iFn
*gvec_fn
;
10166 if (extract32(immh
, 3, 1) && !is_q
) {
10167 unallocated_encoding(s
);
10170 tcg_debug_assert(size
<= 3);
10172 if (!fp_access_check(s
)) {
10177 case 0x02: /* SSRA / USRA (accumulate) */
10178 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10181 case 0x08: /* SRI */
10182 gvec_fn
= gen_gvec_sri
;
10185 case 0x00: /* SSHR / USHR */
10187 if (shift
== 8 << size
) {
10188 /* Shift count the same size as element size produces zero. */
10189 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10190 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10193 gvec_fn
= tcg_gen_gvec_shri
;
10195 /* Shift count the same size as element size produces all sign. */
10196 if (shift
== 8 << size
) {
10199 gvec_fn
= tcg_gen_gvec_sari
;
10203 case 0x04: /* SRSHR / URSHR (rounding) */
10204 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10207 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10208 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10212 g_assert_not_reached();
10215 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10218 /* SHL/SLI - Vector shift left */
10219 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10220 int immh
, int immb
, int opcode
, int rn
, int rd
)
10222 int size
= 32 - clz32(immh
) - 1;
10223 int immhb
= immh
<< 3 | immb
;
10224 int shift
= immhb
- (8 << size
);
10226 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10227 assert(size
>= 0 && size
<= 3);
10229 if (extract32(immh
, 3, 1) && !is_q
) {
10230 unallocated_encoding(s
);
10234 if (!fp_access_check(s
)) {
10239 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10241 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10245 /* USHLL/SHLL - Vector shift left with widening */
10246 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10247 int immh
, int immb
, int opcode
, int rn
, int rd
)
10249 int size
= 32 - clz32(immh
) - 1;
10250 int immhb
= immh
<< 3 | immb
;
10251 int shift
= immhb
- (8 << size
);
10253 int esize
= 8 << size
;
10254 int elements
= dsize
/esize
;
10255 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10256 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10260 unallocated_encoding(s
);
10264 if (!fp_access_check(s
)) {
10268 /* For the LL variants the store is larger than the load,
10269 * so if rd == rn we would overwrite parts of our input.
10270 * So load everything right now and use shifts in the main loop.
10272 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10274 for (i
= 0; i
< elements
; i
++) {
10275 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10276 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10277 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10278 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10282 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10283 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10284 int immh
, int immb
, int opcode
, int rn
, int rd
)
10286 int immhb
= immh
<< 3 | immb
;
10287 int size
= 32 - clz32(immh
) - 1;
10289 int esize
= 8 << size
;
10290 int elements
= dsize
/esize
;
10291 int shift
= (2 * esize
) - immhb
;
10292 bool round
= extract32(opcode
, 0, 1);
10293 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10294 TCGv_i64 tcg_round
;
10297 if (extract32(immh
, 3, 1)) {
10298 unallocated_encoding(s
);
10302 if (!fp_access_check(s
)) {
10306 tcg_rn
= tcg_temp_new_i64();
10307 tcg_rd
= tcg_temp_new_i64();
10308 tcg_final
= tcg_temp_new_i64();
10309 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10312 uint64_t round_const
= 1ULL << (shift
- 1);
10313 tcg_round
= tcg_const_i64(round_const
);
10318 for (i
= 0; i
< elements
; i
++) {
10319 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10320 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10321 false, true, size
+1, shift
);
10323 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10327 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10329 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10332 tcg_temp_free_i64(tcg_round
);
10334 tcg_temp_free_i64(tcg_rn
);
10335 tcg_temp_free_i64(tcg_rd
);
10336 tcg_temp_free_i64(tcg_final
);
10338 clear_vec_high(s
, is_q
, rd
);
10342 /* AdvSIMD shift by immediate
10343 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10344 * +---+---+---+-------------+------+------+--------+---+------+------+
10345 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10346 * +---+---+---+-------------+------+------+--------+---+------+------+
10348 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10350 int rd
= extract32(insn
, 0, 5);
10351 int rn
= extract32(insn
, 5, 5);
10352 int opcode
= extract32(insn
, 11, 5);
10353 int immb
= extract32(insn
, 16, 3);
10354 int immh
= extract32(insn
, 19, 4);
10355 bool is_u
= extract32(insn
, 29, 1);
10356 bool is_q
= extract32(insn
, 30, 1);
10358 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10362 case 0x08: /* SRI */
10364 unallocated_encoding(s
);
10368 case 0x00: /* SSHR / USHR */
10369 case 0x02: /* SSRA / USRA (accumulate) */
10370 case 0x04: /* SRSHR / URSHR (rounding) */
10371 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10372 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10374 case 0x0a: /* SHL / SLI */
10375 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10377 case 0x10: /* SHRN */
10378 case 0x11: /* RSHRN / SQRSHRUN */
10380 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10383 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10386 case 0x12: /* SQSHRN / UQSHRN */
10387 case 0x13: /* SQRSHRN / UQRSHRN */
10388 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10391 case 0x14: /* SSHLL / USHLL */
10392 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10394 case 0x1c: /* SCVTF / UCVTF */
10395 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10398 case 0xc: /* SQSHLU */
10400 unallocated_encoding(s
);
10403 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10405 case 0xe: /* SQSHL, UQSHL */
10406 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10408 case 0x1f: /* FCVTZS/ FCVTZU */
10409 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10412 unallocated_encoding(s
);
10417 /* Generate code to do a "long" addition or subtraction, ie one done in
10418 * TCGv_i64 on vector lanes twice the width specified by size.
10420 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10421 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10423 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10424 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10425 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10426 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10428 NeonGenTwo64OpFn
*genfn
;
10431 genfn
= fns
[size
][is_sub
];
10432 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10435 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10436 int opcode
, int rd
, int rn
, int rm
)
10438 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10439 TCGv_i64 tcg_res
[2];
10442 tcg_res
[0] = tcg_temp_new_i64();
10443 tcg_res
[1] = tcg_temp_new_i64();
10445 /* Does this op do an adding accumulate, a subtracting accumulate,
10446 * or no accumulate at all?
10464 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10465 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10468 /* size == 2 means two 32x32->64 operations; this is worth special
10469 * casing because we can generally handle it inline.
10472 for (pass
= 0; pass
< 2; pass
++) {
10473 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10474 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10475 TCGv_i64 tcg_passres
;
10476 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10478 int elt
= pass
+ is_q
* 2;
10480 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10481 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10484 tcg_passres
= tcg_res
[pass
];
10486 tcg_passres
= tcg_temp_new_i64();
10490 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10491 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10493 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10494 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10496 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10497 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10499 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10500 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10502 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10503 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10504 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10506 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10507 tcg_temp_free_i64(tcg_tmp1
);
10508 tcg_temp_free_i64(tcg_tmp2
);
10511 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10512 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10513 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10514 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10516 case 9: /* SQDMLAL, SQDMLAL2 */
10517 case 11: /* SQDMLSL, SQDMLSL2 */
10518 case 13: /* SQDMULL, SQDMULL2 */
10519 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10520 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10521 tcg_passres
, tcg_passres
);
10524 g_assert_not_reached();
10527 if (opcode
== 9 || opcode
== 11) {
10528 /* saturating accumulate ops */
10530 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10532 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10533 tcg_res
[pass
], tcg_passres
);
10534 } else if (accop
> 0) {
10535 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10536 } else if (accop
< 0) {
10537 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10541 tcg_temp_free_i64(tcg_passres
);
10544 tcg_temp_free_i64(tcg_op1
);
10545 tcg_temp_free_i64(tcg_op2
);
10548 /* size 0 or 1, generally helper functions */
10549 for (pass
= 0; pass
< 2; pass
++) {
10550 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10551 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10552 TCGv_i64 tcg_passres
;
10553 int elt
= pass
+ is_q
* 2;
10555 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10556 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10559 tcg_passres
= tcg_res
[pass
];
10561 tcg_passres
= tcg_temp_new_i64();
10565 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10566 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10568 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10569 static NeonGenWidenFn
* const widenfns
[2][2] = {
10570 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10571 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10573 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10575 widenfn(tcg_op2_64
, tcg_op2
);
10576 widenfn(tcg_passres
, tcg_op1
);
10577 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10578 tcg_passres
, tcg_op2_64
);
10579 tcg_temp_free_i64(tcg_op2_64
);
10582 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10583 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10586 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10588 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10592 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10594 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10598 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10599 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10600 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10603 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10605 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10609 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10611 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10615 case 9: /* SQDMLAL, SQDMLAL2 */
10616 case 11: /* SQDMLSL, SQDMLSL2 */
10617 case 13: /* SQDMULL, SQDMULL2 */
10619 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10620 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10621 tcg_passres
, tcg_passres
);
10624 g_assert_not_reached();
10626 tcg_temp_free_i32(tcg_op1
);
10627 tcg_temp_free_i32(tcg_op2
);
10630 if (opcode
== 9 || opcode
== 11) {
10631 /* saturating accumulate ops */
10633 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10635 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10639 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10640 tcg_res
[pass
], tcg_passres
);
10642 tcg_temp_free_i64(tcg_passres
);
10647 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10648 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10649 tcg_temp_free_i64(tcg_res
[0]);
10650 tcg_temp_free_i64(tcg_res
[1]);
10653 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10654 int opcode
, int rd
, int rn
, int rm
)
10656 TCGv_i64 tcg_res
[2];
10657 int part
= is_q
? 2 : 0;
10660 for (pass
= 0; pass
< 2; pass
++) {
10661 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10662 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10663 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10664 static NeonGenWidenFn
* const widenfns
[3][2] = {
10665 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10666 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10667 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10669 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10671 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10672 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10673 widenfn(tcg_op2_wide
, tcg_op2
);
10674 tcg_temp_free_i32(tcg_op2
);
10675 tcg_res
[pass
] = tcg_temp_new_i64();
10676 gen_neon_addl(size
, (opcode
== 3),
10677 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10678 tcg_temp_free_i64(tcg_op1
);
10679 tcg_temp_free_i64(tcg_op2_wide
);
10682 for (pass
= 0; pass
< 2; pass
++) {
10683 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10684 tcg_temp_free_i64(tcg_res
[pass
]);
10688 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10690 tcg_gen_addi_i64(in
, in
, 1U << 31);
10691 tcg_gen_extrh_i64_i32(res
, in
);
10694 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10695 int opcode
, int rd
, int rn
, int rm
)
10697 TCGv_i32 tcg_res
[2];
10698 int part
= is_q
? 2 : 0;
10701 for (pass
= 0; pass
< 2; pass
++) {
10702 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10703 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10704 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10705 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10706 { gen_helper_neon_narrow_high_u8
,
10707 gen_helper_neon_narrow_round_high_u8
},
10708 { gen_helper_neon_narrow_high_u16
,
10709 gen_helper_neon_narrow_round_high_u16
},
10710 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10712 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10714 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10715 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10717 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10719 tcg_temp_free_i64(tcg_op1
);
10720 tcg_temp_free_i64(tcg_op2
);
10722 tcg_res
[pass
] = tcg_temp_new_i32();
10723 gennarrow(tcg_res
[pass
], tcg_wideres
);
10724 tcg_temp_free_i64(tcg_wideres
);
10727 for (pass
= 0; pass
< 2; pass
++) {
10728 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10729 tcg_temp_free_i32(tcg_res
[pass
]);
10731 clear_vec_high(s
, is_q
, rd
);
10734 /* AdvSIMD three different
10735 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10736 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10737 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10738 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10740 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10742 /* Instructions in this group fall into three basic classes
10743 * (in each case with the operation working on each element in
10744 * the input vectors):
10745 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10747 * (2) wide 64 x 128 -> 128
10748 * (3) narrowing 128 x 128 -> 64
10749 * Here we do initial decode, catch unallocated cases and
10750 * dispatch to separate functions for each class.
10752 int is_q
= extract32(insn
, 30, 1);
10753 int is_u
= extract32(insn
, 29, 1);
10754 int size
= extract32(insn
, 22, 2);
10755 int opcode
= extract32(insn
, 12, 4);
10756 int rm
= extract32(insn
, 16, 5);
10757 int rn
= extract32(insn
, 5, 5);
10758 int rd
= extract32(insn
, 0, 5);
10761 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10762 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10763 /* 64 x 128 -> 128 */
10765 unallocated_encoding(s
);
10768 if (!fp_access_check(s
)) {
10771 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10773 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10774 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10775 /* 128 x 128 -> 64 */
10777 unallocated_encoding(s
);
10780 if (!fp_access_check(s
)) {
10783 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10785 case 14: /* PMULL, PMULL2 */
10787 unallocated_encoding(s
);
10791 case 0: /* PMULL.P8 */
10792 if (!fp_access_check(s
)) {
10795 /* The Q field specifies lo/hi half input for this insn. */
10796 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10797 gen_helper_neon_pmull_h
);
10800 case 3: /* PMULL.P64 */
10801 if (!dc_isar_feature(aa64_pmull
, s
)) {
10802 unallocated_encoding(s
);
10805 if (!fp_access_check(s
)) {
10808 /* The Q field specifies lo/hi half input for this insn. */
10809 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10810 gen_helper_gvec_pmull_q
);
10814 unallocated_encoding(s
);
10818 case 9: /* SQDMLAL, SQDMLAL2 */
10819 case 11: /* SQDMLSL, SQDMLSL2 */
10820 case 13: /* SQDMULL, SQDMULL2 */
10821 if (is_u
|| size
== 0) {
10822 unallocated_encoding(s
);
10826 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10827 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10828 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10829 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10830 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10831 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10832 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10833 /* 64 x 64 -> 128 */
10835 unallocated_encoding(s
);
10838 if (!fp_access_check(s
)) {
10842 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10845 /* opcode 15 not allocated */
10846 unallocated_encoding(s
);
10851 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10852 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10854 int rd
= extract32(insn
, 0, 5);
10855 int rn
= extract32(insn
, 5, 5);
10856 int rm
= extract32(insn
, 16, 5);
10857 int size
= extract32(insn
, 22, 2);
10858 bool is_u
= extract32(insn
, 29, 1);
10859 bool is_q
= extract32(insn
, 30, 1);
10861 if (!fp_access_check(s
)) {
10865 switch (size
+ 4 * is_u
) {
10867 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10870 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10873 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10876 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10879 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10882 case 5: /* BSL bitwise select */
10883 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10885 case 6: /* BIT, bitwise insert if true */
10886 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10888 case 7: /* BIF, bitwise insert if false */
10889 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10893 g_assert_not_reached();
10897 /* Pairwise op subgroup of C3.6.16.
10899 * This is called directly or via the handle_3same_float for float pairwise
10900 * operations where the opcode and size are calculated differently.
10902 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10903 int size
, int rn
, int rm
, int rd
)
10908 /* Floating point operations need fpst */
10909 if (opcode
>= 0x58) {
10910 fpst
= get_fpstatus_ptr(false);
10915 if (!fp_access_check(s
)) {
10919 /* These operations work on the concatenated rm:rn, with each pair of
10920 * adjacent elements being operated on to produce an element in the result.
10923 TCGv_i64 tcg_res
[2];
10925 for (pass
= 0; pass
< 2; pass
++) {
10926 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10927 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10928 int passreg
= (pass
== 0) ? rn
: rm
;
10930 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10931 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10932 tcg_res
[pass
] = tcg_temp_new_i64();
10935 case 0x17: /* ADDP */
10936 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10938 case 0x58: /* FMAXNMP */
10939 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10941 case 0x5a: /* FADDP */
10942 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10944 case 0x5e: /* FMAXP */
10945 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10947 case 0x78: /* FMINNMP */
10948 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10950 case 0x7e: /* FMINP */
10951 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10954 g_assert_not_reached();
10957 tcg_temp_free_i64(tcg_op1
);
10958 tcg_temp_free_i64(tcg_op2
);
10961 for (pass
= 0; pass
< 2; pass
++) {
10962 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10963 tcg_temp_free_i64(tcg_res
[pass
]);
10966 int maxpass
= is_q
? 4 : 2;
10967 TCGv_i32 tcg_res
[4];
10969 for (pass
= 0; pass
< maxpass
; pass
++) {
10970 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10971 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10972 NeonGenTwoOpFn
*genfn
= NULL
;
10973 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10974 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10976 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10977 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10978 tcg_res
[pass
] = tcg_temp_new_i32();
10981 case 0x17: /* ADDP */
10983 static NeonGenTwoOpFn
* const fns
[3] = {
10984 gen_helper_neon_padd_u8
,
10985 gen_helper_neon_padd_u16
,
10991 case 0x14: /* SMAXP, UMAXP */
10993 static NeonGenTwoOpFn
* const fns
[3][2] = {
10994 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10995 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10996 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10998 genfn
= fns
[size
][u
];
11001 case 0x15: /* SMINP, UMINP */
11003 static NeonGenTwoOpFn
* const fns
[3][2] = {
11004 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11005 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11006 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11008 genfn
= fns
[size
][u
];
11011 /* The FP operations are all on single floats (32 bit) */
11012 case 0x58: /* FMAXNMP */
11013 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11015 case 0x5a: /* FADDP */
11016 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11018 case 0x5e: /* FMAXP */
11019 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11021 case 0x78: /* FMINNMP */
11022 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11024 case 0x7e: /* FMINP */
11025 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11028 g_assert_not_reached();
11031 /* FP ops called directly, otherwise call now */
11033 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11036 tcg_temp_free_i32(tcg_op1
);
11037 tcg_temp_free_i32(tcg_op2
);
11040 for (pass
= 0; pass
< maxpass
; pass
++) {
11041 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11042 tcg_temp_free_i32(tcg_res
[pass
]);
11044 clear_vec_high(s
, is_q
, rd
);
11048 tcg_temp_free_ptr(fpst
);
11052 /* Floating point op subgroup of C3.6.16. */
11053 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11055 /* For floating point ops, the U, size[1] and opcode bits
11056 * together indicate the operation. size[0] indicates single
11059 int fpopcode
= extract32(insn
, 11, 5)
11060 | (extract32(insn
, 23, 1) << 5)
11061 | (extract32(insn
, 29, 1) << 6);
11062 int is_q
= extract32(insn
, 30, 1);
11063 int size
= extract32(insn
, 22, 1);
11064 int rm
= extract32(insn
, 16, 5);
11065 int rn
= extract32(insn
, 5, 5);
11066 int rd
= extract32(insn
, 0, 5);
11068 int datasize
= is_q
? 128 : 64;
11069 int esize
= 32 << size
;
11070 int elements
= datasize
/ esize
;
11072 if (size
== 1 && !is_q
) {
11073 unallocated_encoding(s
);
11077 switch (fpopcode
) {
11078 case 0x58: /* FMAXNMP */
11079 case 0x5a: /* FADDP */
11080 case 0x5e: /* FMAXP */
11081 case 0x78: /* FMINNMP */
11082 case 0x7e: /* FMINP */
11083 if (size
&& !is_q
) {
11084 unallocated_encoding(s
);
11087 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11090 case 0x1b: /* FMULX */
11091 case 0x1f: /* FRECPS */
11092 case 0x3f: /* FRSQRTS */
11093 case 0x5d: /* FACGE */
11094 case 0x7d: /* FACGT */
11095 case 0x19: /* FMLA */
11096 case 0x39: /* FMLS */
11097 case 0x18: /* FMAXNM */
11098 case 0x1a: /* FADD */
11099 case 0x1c: /* FCMEQ */
11100 case 0x1e: /* FMAX */
11101 case 0x38: /* FMINNM */
11102 case 0x3a: /* FSUB */
11103 case 0x3e: /* FMIN */
11104 case 0x5b: /* FMUL */
11105 case 0x5c: /* FCMGE */
11106 case 0x5f: /* FDIV */
11107 case 0x7a: /* FABD */
11108 case 0x7c: /* FCMGT */
11109 if (!fp_access_check(s
)) {
11112 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11115 case 0x1d: /* FMLAL */
11116 case 0x3d: /* FMLSL */
11117 case 0x59: /* FMLAL2 */
11118 case 0x79: /* FMLSL2 */
11119 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11120 unallocated_encoding(s
);
11123 if (fp_access_check(s
)) {
11124 int is_s
= extract32(insn
, 23, 1);
11125 int is_2
= extract32(insn
, 29, 1);
11126 int data
= (is_2
<< 1) | is_s
;
11127 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11128 vec_full_reg_offset(s
, rn
),
11129 vec_full_reg_offset(s
, rm
), cpu_env
,
11130 is_q
? 16 : 8, vec_full_reg_size(s
),
11131 data
, gen_helper_gvec_fmlal_a64
);
11136 unallocated_encoding(s
);
11141 /* Integer op subgroup of C3.6.16. */
11142 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11144 int is_q
= extract32(insn
, 30, 1);
11145 int u
= extract32(insn
, 29, 1);
11146 int size
= extract32(insn
, 22, 2);
11147 int opcode
= extract32(insn
, 11, 5);
11148 int rm
= extract32(insn
, 16, 5);
11149 int rn
= extract32(insn
, 5, 5);
11150 int rd
= extract32(insn
, 0, 5);
11155 case 0x13: /* MUL, PMUL */
11156 if (u
&& size
!= 0) {
11157 unallocated_encoding(s
);
11161 case 0x0: /* SHADD, UHADD */
11162 case 0x2: /* SRHADD, URHADD */
11163 case 0x4: /* SHSUB, UHSUB */
11164 case 0xc: /* SMAX, UMAX */
11165 case 0xd: /* SMIN, UMIN */
11166 case 0xe: /* SABD, UABD */
11167 case 0xf: /* SABA, UABA */
11168 case 0x12: /* MLA, MLS */
11170 unallocated_encoding(s
);
11174 case 0x16: /* SQDMULH, SQRDMULH */
11175 if (size
== 0 || size
== 3) {
11176 unallocated_encoding(s
);
11181 if (size
== 3 && !is_q
) {
11182 unallocated_encoding(s
);
11188 if (!fp_access_check(s
)) {
11193 case 0x01: /* SQADD, UQADD */
11195 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11197 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11200 case 0x05: /* SQSUB, UQSUB */
11202 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11204 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11207 case 0x08: /* SSHL, USHL */
11209 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11211 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11214 case 0x0c: /* SMAX, UMAX */
11216 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11218 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11221 case 0x0d: /* SMIN, UMIN */
11223 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11225 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11228 case 0xe: /* SABD, UABD */
11230 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11232 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11235 case 0xf: /* SABA, UABA */
11237 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11239 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11242 case 0x10: /* ADD, SUB */
11244 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11246 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11249 case 0x13: /* MUL, PMUL */
11250 if (!u
) { /* MUL */
11251 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11252 } else { /* PMUL */
11253 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11256 case 0x12: /* MLA, MLS */
11258 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11260 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11264 if (!u
) { /* CMTST */
11265 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11269 cond
= TCG_COND_EQ
;
11271 case 0x06: /* CMGT, CMHI */
11272 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11274 case 0x07: /* CMGE, CMHS */
11275 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11277 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11278 vec_full_reg_offset(s
, rn
),
11279 vec_full_reg_offset(s
, rm
),
11280 is_q
? 16 : 8, vec_full_reg_size(s
));
11286 for (pass
= 0; pass
< 2; pass
++) {
11287 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11288 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11289 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11291 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11292 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11294 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11296 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11298 tcg_temp_free_i64(tcg_res
);
11299 tcg_temp_free_i64(tcg_op1
);
11300 tcg_temp_free_i64(tcg_op2
);
11303 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11304 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11305 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11306 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11307 NeonGenTwoOpFn
*genfn
= NULL
;
11308 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11310 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11311 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11314 case 0x0: /* SHADD, UHADD */
11316 static NeonGenTwoOpFn
* const fns
[3][2] = {
11317 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11318 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11319 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11321 genfn
= fns
[size
][u
];
11324 case 0x2: /* SRHADD, URHADD */
11326 static NeonGenTwoOpFn
* const fns
[3][2] = {
11327 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11328 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11329 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11331 genfn
= fns
[size
][u
];
11334 case 0x4: /* SHSUB, UHSUB */
11336 static NeonGenTwoOpFn
* const fns
[3][2] = {
11337 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11338 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11339 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11341 genfn
= fns
[size
][u
];
11344 case 0x9: /* SQSHL, UQSHL */
11346 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11347 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11348 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11349 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11351 genenvfn
= fns
[size
][u
];
11354 case 0xa: /* SRSHL, URSHL */
11356 static NeonGenTwoOpFn
* const fns
[3][2] = {
11357 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11358 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11359 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11361 genfn
= fns
[size
][u
];
11364 case 0xb: /* SQRSHL, UQRSHL */
11366 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11367 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11368 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11369 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11371 genenvfn
= fns
[size
][u
];
11374 case 0x16: /* SQDMULH, SQRDMULH */
11376 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11377 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11378 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11380 assert(size
== 1 || size
== 2);
11381 genenvfn
= fns
[size
- 1][u
];
11385 g_assert_not_reached();
11389 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11391 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11394 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11396 tcg_temp_free_i32(tcg_res
);
11397 tcg_temp_free_i32(tcg_op1
);
11398 tcg_temp_free_i32(tcg_op2
);
11401 clear_vec_high(s
, is_q
, rd
);
11404 /* AdvSIMD three same
11405 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11406 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11407 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11408 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11410 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11412 int opcode
= extract32(insn
, 11, 5);
11415 case 0x3: /* logic ops */
11416 disas_simd_3same_logic(s
, insn
);
11418 case 0x17: /* ADDP */
11419 case 0x14: /* SMAXP, UMAXP */
11420 case 0x15: /* SMINP, UMINP */
11422 /* Pairwise operations */
11423 int is_q
= extract32(insn
, 30, 1);
11424 int u
= extract32(insn
, 29, 1);
11425 int size
= extract32(insn
, 22, 2);
11426 int rm
= extract32(insn
, 16, 5);
11427 int rn
= extract32(insn
, 5, 5);
11428 int rd
= extract32(insn
, 0, 5);
11429 if (opcode
== 0x17) {
11430 if (u
|| (size
== 3 && !is_q
)) {
11431 unallocated_encoding(s
);
11436 unallocated_encoding(s
);
11440 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11443 case 0x18 ... 0x31:
11444 /* floating point ops, sz[1] and U are part of opcode */
11445 disas_simd_3same_float(s
, insn
);
11448 disas_simd_3same_int(s
, insn
);
11454 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11456 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11457 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11458 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11459 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11461 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11462 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11465 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11467 int opcode
, fpopcode
;
11468 int is_q
, u
, a
, rm
, rn
, rd
;
11469 int datasize
, elements
;
11472 bool pairwise
= false;
11474 if (!dc_isar_feature(aa64_fp16
, s
)) {
11475 unallocated_encoding(s
);
11479 if (!fp_access_check(s
)) {
11483 /* For these floating point ops, the U, a and opcode bits
11484 * together indicate the operation.
11486 opcode
= extract32(insn
, 11, 3);
11487 u
= extract32(insn
, 29, 1);
11488 a
= extract32(insn
, 23, 1);
11489 is_q
= extract32(insn
, 30, 1);
11490 rm
= extract32(insn
, 16, 5);
11491 rn
= extract32(insn
, 5, 5);
11492 rd
= extract32(insn
, 0, 5);
11494 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11495 datasize
= is_q
? 128 : 64;
11496 elements
= datasize
/ 16;
11498 switch (fpopcode
) {
11499 case 0x10: /* FMAXNMP */
11500 case 0x12: /* FADDP */
11501 case 0x16: /* FMAXP */
11502 case 0x18: /* FMINNMP */
11503 case 0x1e: /* FMINP */
11508 fpst
= get_fpstatus_ptr(true);
11511 int maxpass
= is_q
? 8 : 4;
11512 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11513 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11514 TCGv_i32 tcg_res
[8];
11516 for (pass
= 0; pass
< maxpass
; pass
++) {
11517 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11518 int passelt
= (pass
<< 1) & (maxpass
- 1);
11520 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11521 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11522 tcg_res
[pass
] = tcg_temp_new_i32();
11524 switch (fpopcode
) {
11525 case 0x10: /* FMAXNMP */
11526 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11529 case 0x12: /* FADDP */
11530 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11532 case 0x16: /* FMAXP */
11533 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11535 case 0x18: /* FMINNMP */
11536 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11539 case 0x1e: /* FMINP */
11540 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11543 g_assert_not_reached();
11547 for (pass
= 0; pass
< maxpass
; pass
++) {
11548 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11549 tcg_temp_free_i32(tcg_res
[pass
]);
11552 tcg_temp_free_i32(tcg_op1
);
11553 tcg_temp_free_i32(tcg_op2
);
11556 for (pass
= 0; pass
< elements
; pass
++) {
11557 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11558 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11559 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11561 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11562 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11564 switch (fpopcode
) {
11565 case 0x0: /* FMAXNM */
11566 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11568 case 0x1: /* FMLA */
11569 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11570 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11573 case 0x2: /* FADD */
11574 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11576 case 0x3: /* FMULX */
11577 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11579 case 0x4: /* FCMEQ */
11580 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11582 case 0x6: /* FMAX */
11583 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11585 case 0x7: /* FRECPS */
11586 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11588 case 0x8: /* FMINNM */
11589 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11591 case 0x9: /* FMLS */
11592 /* As usual for ARM, separate negation for fused multiply-add */
11593 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11594 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11595 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11598 case 0xa: /* FSUB */
11599 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11601 case 0xe: /* FMIN */
11602 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11604 case 0xf: /* FRSQRTS */
11605 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11607 case 0x13: /* FMUL */
11608 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11610 case 0x14: /* FCMGE */
11611 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11613 case 0x15: /* FACGE */
11614 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11616 case 0x17: /* FDIV */
11617 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11619 case 0x1a: /* FABD */
11620 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11621 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11623 case 0x1c: /* FCMGT */
11624 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11626 case 0x1d: /* FACGT */
11627 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11630 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11631 __func__
, insn
, fpopcode
, s
->pc_curr
);
11632 g_assert_not_reached();
11635 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11636 tcg_temp_free_i32(tcg_res
);
11637 tcg_temp_free_i32(tcg_op1
);
11638 tcg_temp_free_i32(tcg_op2
);
11642 tcg_temp_free_ptr(fpst
);
11644 clear_vec_high(s
, is_q
, rd
);
11647 /* AdvSIMD three same extra
11648 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11649 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11650 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11651 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11653 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11655 int rd
= extract32(insn
, 0, 5);
11656 int rn
= extract32(insn
, 5, 5);
11657 int opcode
= extract32(insn
, 11, 4);
11658 int rm
= extract32(insn
, 16, 5);
11659 int size
= extract32(insn
, 22, 2);
11660 bool u
= extract32(insn
, 29, 1);
11661 bool is_q
= extract32(insn
, 30, 1);
11665 switch (u
* 16 + opcode
) {
11666 case 0x10: /* SQRDMLAH (vector) */
11667 case 0x11: /* SQRDMLSH (vector) */
11668 if (size
!= 1 && size
!= 2) {
11669 unallocated_encoding(s
);
11672 feature
= dc_isar_feature(aa64_rdm
, s
);
11674 case 0x02: /* SDOT (vector) */
11675 case 0x12: /* UDOT (vector) */
11676 if (size
!= MO_32
) {
11677 unallocated_encoding(s
);
11680 feature
= dc_isar_feature(aa64_dp
, s
);
11682 case 0x18: /* FCMLA, #0 */
11683 case 0x19: /* FCMLA, #90 */
11684 case 0x1a: /* FCMLA, #180 */
11685 case 0x1b: /* FCMLA, #270 */
11686 case 0x1c: /* FCADD, #90 */
11687 case 0x1e: /* FCADD, #270 */
11689 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11690 || (size
== 3 && !is_q
)) {
11691 unallocated_encoding(s
);
11694 feature
= dc_isar_feature(aa64_fcma
, s
);
11697 unallocated_encoding(s
);
11701 unallocated_encoding(s
);
11704 if (!fp_access_check(s
)) {
11709 case 0x0: /* SQRDMLAH (vector) */
11710 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
11713 case 0x1: /* SQRDMLSH (vector) */
11714 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
11717 case 0x2: /* SDOT / UDOT */
11718 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11719 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11722 case 0x8: /* FCMLA, #0 */
11723 case 0x9: /* FCMLA, #90 */
11724 case 0xa: /* FCMLA, #180 */
11725 case 0xb: /* FCMLA, #270 */
11726 rot
= extract32(opcode
, 0, 2);
11729 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11730 gen_helper_gvec_fcmlah
);
11733 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11734 gen_helper_gvec_fcmlas
);
11737 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11738 gen_helper_gvec_fcmlad
);
11741 g_assert_not_reached();
11745 case 0xc: /* FCADD, #90 */
11746 case 0xe: /* FCADD, #270 */
11747 rot
= extract32(opcode
, 1, 1);
11750 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11751 gen_helper_gvec_fcaddh
);
11754 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11755 gen_helper_gvec_fcadds
);
11758 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11759 gen_helper_gvec_fcaddd
);
11762 g_assert_not_reached();
11767 g_assert_not_reached();
11771 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11772 int size
, int rn
, int rd
)
11774 /* Handle 2-reg-misc ops which are widening (so each size element
11775 * in the source becomes a 2*size element in the destination.
11776 * The only instruction like this is FCVTL.
11781 /* 32 -> 64 bit fp conversion */
11782 TCGv_i64 tcg_res
[2];
11783 int srcelt
= is_q
? 2 : 0;
11785 for (pass
= 0; pass
< 2; pass
++) {
11786 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11787 tcg_res
[pass
] = tcg_temp_new_i64();
11789 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11790 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11791 tcg_temp_free_i32(tcg_op
);
11793 for (pass
= 0; pass
< 2; pass
++) {
11794 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11795 tcg_temp_free_i64(tcg_res
[pass
]);
11798 /* 16 -> 32 bit fp conversion */
11799 int srcelt
= is_q
? 4 : 0;
11800 TCGv_i32 tcg_res
[4];
11801 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11802 TCGv_i32 ahp
= get_ahp_flag();
11804 for (pass
= 0; pass
< 4; pass
++) {
11805 tcg_res
[pass
] = tcg_temp_new_i32();
11807 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11808 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11811 for (pass
= 0; pass
< 4; pass
++) {
11812 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11813 tcg_temp_free_i32(tcg_res
[pass
]);
11816 tcg_temp_free_ptr(fpst
);
11817 tcg_temp_free_i32(ahp
);
11821 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11822 bool is_q
, int size
, int rn
, int rd
)
11824 int op
= (opcode
<< 1) | u
;
11825 int opsz
= op
+ size
;
11826 int grp_size
= 3 - opsz
;
11827 int dsize
= is_q
? 128 : 64;
11831 unallocated_encoding(s
);
11835 if (!fp_access_check(s
)) {
11840 /* Special case bytes, use bswap op on each group of elements */
11841 int groups
= dsize
/ (8 << grp_size
);
11843 for (i
= 0; i
< groups
; i
++) {
11844 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11846 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11847 switch (grp_size
) {
11849 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11852 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11855 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11858 g_assert_not_reached();
11860 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11861 tcg_temp_free_i64(tcg_tmp
);
11863 clear_vec_high(s
, is_q
, rd
);
11865 int revmask
= (1 << grp_size
) - 1;
11866 int esize
= 8 << size
;
11867 int elements
= dsize
/ esize
;
11868 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11869 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11870 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11872 for (i
= 0; i
< elements
; i
++) {
11873 int e_rev
= (i
& 0xf) ^ revmask
;
11874 int off
= e_rev
* esize
;
11875 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11877 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11878 tcg_rn
, off
- 64, esize
);
11880 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11883 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11884 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11886 tcg_temp_free_i64(tcg_rd_hi
);
11887 tcg_temp_free_i64(tcg_rd
);
11888 tcg_temp_free_i64(tcg_rn
);
11892 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11893 bool is_q
, int size
, int rn
, int rd
)
11895 /* Implement the pairwise operations from 2-misc:
11896 * SADDLP, UADDLP, SADALP, UADALP.
11897 * These all add pairs of elements in the input to produce a
11898 * double-width result element in the output (possibly accumulating).
11900 bool accum
= (opcode
== 0x6);
11901 int maxpass
= is_q
? 2 : 1;
11903 TCGv_i64 tcg_res
[2];
11906 /* 32 + 32 -> 64 op */
11907 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11909 for (pass
= 0; pass
< maxpass
; pass
++) {
11910 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11911 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11913 tcg_res
[pass
] = tcg_temp_new_i64();
11915 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11916 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11917 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11919 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11920 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11923 tcg_temp_free_i64(tcg_op1
);
11924 tcg_temp_free_i64(tcg_op2
);
11927 for (pass
= 0; pass
< maxpass
; pass
++) {
11928 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11929 NeonGenOne64OpFn
*genfn
;
11930 static NeonGenOne64OpFn
* const fns
[2][2] = {
11931 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11932 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11935 genfn
= fns
[size
][u
];
11937 tcg_res
[pass
] = tcg_temp_new_i64();
11939 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11940 genfn(tcg_res
[pass
], tcg_op
);
11943 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11945 gen_helper_neon_addl_u16(tcg_res
[pass
],
11946 tcg_res
[pass
], tcg_op
);
11948 gen_helper_neon_addl_u32(tcg_res
[pass
],
11949 tcg_res
[pass
], tcg_op
);
11952 tcg_temp_free_i64(tcg_op
);
11956 tcg_res
[1] = tcg_const_i64(0);
11958 for (pass
= 0; pass
< 2; pass
++) {
11959 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11960 tcg_temp_free_i64(tcg_res
[pass
]);
11964 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11966 /* Implement SHLL and SHLL2 */
11968 int part
= is_q
? 2 : 0;
11969 TCGv_i64 tcg_res
[2];
11971 for (pass
= 0; pass
< 2; pass
++) {
11972 static NeonGenWidenFn
* const widenfns
[3] = {
11973 gen_helper_neon_widen_u8
,
11974 gen_helper_neon_widen_u16
,
11975 tcg_gen_extu_i32_i64
,
11977 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11978 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11980 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11981 tcg_res
[pass
] = tcg_temp_new_i64();
11982 widenfn(tcg_res
[pass
], tcg_op
);
11983 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11985 tcg_temp_free_i32(tcg_op
);
11988 for (pass
= 0; pass
< 2; pass
++) {
11989 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11990 tcg_temp_free_i64(tcg_res
[pass
]);
11994 /* AdvSIMD two reg misc
11995 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11996 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11997 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11998 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12000 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12002 int size
= extract32(insn
, 22, 2);
12003 int opcode
= extract32(insn
, 12, 5);
12004 bool u
= extract32(insn
, 29, 1);
12005 bool is_q
= extract32(insn
, 30, 1);
12006 int rn
= extract32(insn
, 5, 5);
12007 int rd
= extract32(insn
, 0, 5);
12008 bool need_fpstatus
= false;
12009 bool need_rmode
= false;
12011 TCGv_i32 tcg_rmode
;
12012 TCGv_ptr tcg_fpstatus
;
12015 case 0x0: /* REV64, REV32 */
12016 case 0x1: /* REV16 */
12017 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12019 case 0x5: /* CNT, NOT, RBIT */
12020 if (u
&& size
== 0) {
12023 } else if (u
&& size
== 1) {
12026 } else if (!u
&& size
== 0) {
12030 unallocated_encoding(s
);
12032 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12033 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12035 unallocated_encoding(s
);
12038 if (!fp_access_check(s
)) {
12042 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12044 case 0x4: /* CLS, CLZ */
12046 unallocated_encoding(s
);
12050 case 0x2: /* SADDLP, UADDLP */
12051 case 0x6: /* SADALP, UADALP */
12053 unallocated_encoding(s
);
12056 if (!fp_access_check(s
)) {
12059 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12061 case 0x13: /* SHLL, SHLL2 */
12062 if (u
== 0 || size
== 3) {
12063 unallocated_encoding(s
);
12066 if (!fp_access_check(s
)) {
12069 handle_shll(s
, is_q
, size
, rn
, rd
);
12071 case 0xa: /* CMLT */
12073 unallocated_encoding(s
);
12077 case 0x8: /* CMGT, CMGE */
12078 case 0x9: /* CMEQ, CMLE */
12079 case 0xb: /* ABS, NEG */
12080 if (size
== 3 && !is_q
) {
12081 unallocated_encoding(s
);
12085 case 0x3: /* SUQADD, USQADD */
12086 if (size
== 3 && !is_q
) {
12087 unallocated_encoding(s
);
12090 if (!fp_access_check(s
)) {
12093 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12095 case 0x7: /* SQABS, SQNEG */
12096 if (size
== 3 && !is_q
) {
12097 unallocated_encoding(s
);
12102 case 0x16 ... 0x1f:
12104 /* Floating point: U, size[1] and opcode indicate operation;
12105 * size[0] indicates single or double precision.
12107 int is_double
= extract32(size
, 0, 1);
12108 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12109 size
= is_double
? 3 : 2;
12111 case 0x2f: /* FABS */
12112 case 0x6f: /* FNEG */
12113 if (size
== 3 && !is_q
) {
12114 unallocated_encoding(s
);
12118 case 0x1d: /* SCVTF */
12119 case 0x5d: /* UCVTF */
12121 bool is_signed
= (opcode
== 0x1d) ? true : false;
12122 int elements
= is_double
? 2 : is_q
? 4 : 2;
12123 if (is_double
&& !is_q
) {
12124 unallocated_encoding(s
);
12127 if (!fp_access_check(s
)) {
12130 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12133 case 0x2c: /* FCMGT (zero) */
12134 case 0x2d: /* FCMEQ (zero) */
12135 case 0x2e: /* FCMLT (zero) */
12136 case 0x6c: /* FCMGE (zero) */
12137 case 0x6d: /* FCMLE (zero) */
12138 if (size
== 3 && !is_q
) {
12139 unallocated_encoding(s
);
12142 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12144 case 0x7f: /* FSQRT */
12145 if (size
== 3 && !is_q
) {
12146 unallocated_encoding(s
);
12150 case 0x1a: /* FCVTNS */
12151 case 0x1b: /* FCVTMS */
12152 case 0x3a: /* FCVTPS */
12153 case 0x3b: /* FCVTZS */
12154 case 0x5a: /* FCVTNU */
12155 case 0x5b: /* FCVTMU */
12156 case 0x7a: /* FCVTPU */
12157 case 0x7b: /* FCVTZU */
12158 need_fpstatus
= true;
12160 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12161 if (size
== 3 && !is_q
) {
12162 unallocated_encoding(s
);
12166 case 0x5c: /* FCVTAU */
12167 case 0x1c: /* FCVTAS */
12168 need_fpstatus
= true;
12170 rmode
= FPROUNDING_TIEAWAY
;
12171 if (size
== 3 && !is_q
) {
12172 unallocated_encoding(s
);
12176 case 0x3c: /* URECPE */
12178 unallocated_encoding(s
);
12182 case 0x3d: /* FRECPE */
12183 case 0x7d: /* FRSQRTE */
12184 if (size
== 3 && !is_q
) {
12185 unallocated_encoding(s
);
12188 if (!fp_access_check(s
)) {
12191 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12193 case 0x56: /* FCVTXN, FCVTXN2 */
12195 unallocated_encoding(s
);
12199 case 0x16: /* FCVTN, FCVTN2 */
12200 /* handle_2misc_narrow does a 2*size -> size operation, but these
12201 * instructions encode the source size rather than dest size.
12203 if (!fp_access_check(s
)) {
12206 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12208 case 0x17: /* FCVTL, FCVTL2 */
12209 if (!fp_access_check(s
)) {
12212 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12214 case 0x18: /* FRINTN */
12215 case 0x19: /* FRINTM */
12216 case 0x38: /* FRINTP */
12217 case 0x39: /* FRINTZ */
12219 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12221 case 0x59: /* FRINTX */
12222 case 0x79: /* FRINTI */
12223 need_fpstatus
= true;
12224 if (size
== 3 && !is_q
) {
12225 unallocated_encoding(s
);
12229 case 0x58: /* FRINTA */
12231 rmode
= FPROUNDING_TIEAWAY
;
12232 need_fpstatus
= true;
12233 if (size
== 3 && !is_q
) {
12234 unallocated_encoding(s
);
12238 case 0x7c: /* URSQRTE */
12240 unallocated_encoding(s
);
12244 case 0x1e: /* FRINT32Z */
12245 case 0x1f: /* FRINT64Z */
12247 rmode
= FPROUNDING_ZERO
;
12249 case 0x5e: /* FRINT32X */
12250 case 0x5f: /* FRINT64X */
12251 need_fpstatus
= true;
12252 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12253 unallocated_encoding(s
);
12258 unallocated_encoding(s
);
12264 unallocated_encoding(s
);
12268 if (!fp_access_check(s
)) {
12272 if (need_fpstatus
|| need_rmode
) {
12273 tcg_fpstatus
= get_fpstatus_ptr(false);
12275 tcg_fpstatus
= NULL
;
12278 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12279 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12286 if (u
&& size
== 0) { /* NOT */
12287 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12291 case 0x8: /* CMGT, CMGE */
12293 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12295 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12298 case 0x9: /* CMEQ, CMLE */
12300 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12302 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12305 case 0xa: /* CMLT */
12306 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12309 if (u
) { /* ABS, NEG */
12310 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12312 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12318 /* All 64-bit element operations can be shared with scalar 2misc */
12321 /* Coverity claims (size == 3 && !is_q) has been eliminated
12322 * from all paths leading to here.
12324 tcg_debug_assert(is_q
);
12325 for (pass
= 0; pass
< 2; pass
++) {
12326 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12327 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12329 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12331 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12332 tcg_rmode
, tcg_fpstatus
);
12334 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12336 tcg_temp_free_i64(tcg_res
);
12337 tcg_temp_free_i64(tcg_op
);
12342 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12343 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12344 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12346 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12349 /* Special cases for 32 bit elements */
12351 case 0x4: /* CLS */
12353 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12355 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12358 case 0x7: /* SQABS, SQNEG */
12360 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12362 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12365 case 0x2f: /* FABS */
12366 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12368 case 0x6f: /* FNEG */
12369 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12371 case 0x7f: /* FSQRT */
12372 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12374 case 0x1a: /* FCVTNS */
12375 case 0x1b: /* FCVTMS */
12376 case 0x1c: /* FCVTAS */
12377 case 0x3a: /* FCVTPS */
12378 case 0x3b: /* FCVTZS */
12380 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12381 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12382 tcg_shift
, tcg_fpstatus
);
12383 tcg_temp_free_i32(tcg_shift
);
12386 case 0x5a: /* FCVTNU */
12387 case 0x5b: /* FCVTMU */
12388 case 0x5c: /* FCVTAU */
12389 case 0x7a: /* FCVTPU */
12390 case 0x7b: /* FCVTZU */
12392 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12393 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12394 tcg_shift
, tcg_fpstatus
);
12395 tcg_temp_free_i32(tcg_shift
);
12398 case 0x18: /* FRINTN */
12399 case 0x19: /* FRINTM */
12400 case 0x38: /* FRINTP */
12401 case 0x39: /* FRINTZ */
12402 case 0x58: /* FRINTA */
12403 case 0x79: /* FRINTI */
12404 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12406 case 0x59: /* FRINTX */
12407 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12409 case 0x7c: /* URSQRTE */
12410 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12412 case 0x1e: /* FRINT32Z */
12413 case 0x5e: /* FRINT32X */
12414 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12416 case 0x1f: /* FRINT64Z */
12417 case 0x5f: /* FRINT64X */
12418 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12421 g_assert_not_reached();
12424 /* Use helpers for 8 and 16 bit elements */
12426 case 0x5: /* CNT, RBIT */
12427 /* For these two insns size is part of the opcode specifier
12428 * (handled earlier); they always operate on byte elements.
12431 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12433 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12436 case 0x7: /* SQABS, SQNEG */
12438 NeonGenOneOpEnvFn
*genfn
;
12439 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12440 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12441 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12443 genfn
= fns
[size
][u
];
12444 genfn(tcg_res
, cpu_env
, tcg_op
);
12447 case 0x4: /* CLS, CLZ */
12450 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12452 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12456 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12458 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12463 g_assert_not_reached();
12467 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12469 tcg_temp_free_i32(tcg_res
);
12470 tcg_temp_free_i32(tcg_op
);
12473 clear_vec_high(s
, is_q
, rd
);
12476 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12477 tcg_temp_free_i32(tcg_rmode
);
12479 if (need_fpstatus
) {
12480 tcg_temp_free_ptr(tcg_fpstatus
);
12484 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12486 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12487 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12488 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12489 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12490 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12491 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12493 * This actually covers two groups where scalar access is governed by
12494 * bit 28. A bunch of the instructions (float to integral) only exist
12495 * in the vector form and are un-allocated for the scalar decode. Also
12496 * in the scalar decode Q is always 1.
12498 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12500 int fpop
, opcode
, a
, u
;
12504 bool only_in_vector
= false;
12507 TCGv_i32 tcg_rmode
= NULL
;
12508 TCGv_ptr tcg_fpstatus
= NULL
;
12509 bool need_rmode
= false;
12510 bool need_fpst
= true;
12513 if (!dc_isar_feature(aa64_fp16
, s
)) {
12514 unallocated_encoding(s
);
12518 rd
= extract32(insn
, 0, 5);
12519 rn
= extract32(insn
, 5, 5);
12521 a
= extract32(insn
, 23, 1);
12522 u
= extract32(insn
, 29, 1);
12523 is_scalar
= extract32(insn
, 28, 1);
12524 is_q
= extract32(insn
, 30, 1);
12526 opcode
= extract32(insn
, 12, 5);
12527 fpop
= deposit32(opcode
, 5, 1, a
);
12528 fpop
= deposit32(fpop
, 6, 1, u
);
12530 rd
= extract32(insn
, 0, 5);
12531 rn
= extract32(insn
, 5, 5);
12534 case 0x1d: /* SCVTF */
12535 case 0x5d: /* UCVTF */
12542 elements
= (is_q
? 8 : 4);
12545 if (!fp_access_check(s
)) {
12548 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12552 case 0x2c: /* FCMGT (zero) */
12553 case 0x2d: /* FCMEQ (zero) */
12554 case 0x2e: /* FCMLT (zero) */
12555 case 0x6c: /* FCMGE (zero) */
12556 case 0x6d: /* FCMLE (zero) */
12557 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12559 case 0x3d: /* FRECPE */
12560 case 0x3f: /* FRECPX */
12562 case 0x18: /* FRINTN */
12564 only_in_vector
= true;
12565 rmode
= FPROUNDING_TIEEVEN
;
12567 case 0x19: /* FRINTM */
12569 only_in_vector
= true;
12570 rmode
= FPROUNDING_NEGINF
;
12572 case 0x38: /* FRINTP */
12574 only_in_vector
= true;
12575 rmode
= FPROUNDING_POSINF
;
12577 case 0x39: /* FRINTZ */
12579 only_in_vector
= true;
12580 rmode
= FPROUNDING_ZERO
;
12582 case 0x58: /* FRINTA */
12584 only_in_vector
= true;
12585 rmode
= FPROUNDING_TIEAWAY
;
12587 case 0x59: /* FRINTX */
12588 case 0x79: /* FRINTI */
12589 only_in_vector
= true;
12590 /* current rounding mode */
12592 case 0x1a: /* FCVTNS */
12594 rmode
= FPROUNDING_TIEEVEN
;
12596 case 0x1b: /* FCVTMS */
12598 rmode
= FPROUNDING_NEGINF
;
12600 case 0x1c: /* FCVTAS */
12602 rmode
= FPROUNDING_TIEAWAY
;
12604 case 0x3a: /* FCVTPS */
12606 rmode
= FPROUNDING_POSINF
;
12608 case 0x3b: /* FCVTZS */
12610 rmode
= FPROUNDING_ZERO
;
12612 case 0x5a: /* FCVTNU */
12614 rmode
= FPROUNDING_TIEEVEN
;
12616 case 0x5b: /* FCVTMU */
12618 rmode
= FPROUNDING_NEGINF
;
12620 case 0x5c: /* FCVTAU */
12622 rmode
= FPROUNDING_TIEAWAY
;
12624 case 0x7a: /* FCVTPU */
12626 rmode
= FPROUNDING_POSINF
;
12628 case 0x7b: /* FCVTZU */
12630 rmode
= FPROUNDING_ZERO
;
12632 case 0x2f: /* FABS */
12633 case 0x6f: /* FNEG */
12636 case 0x7d: /* FRSQRTE */
12637 case 0x7f: /* FSQRT (vector) */
12640 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12641 g_assert_not_reached();
12645 /* Check additional constraints for the scalar encoding */
12648 unallocated_encoding(s
);
12651 /* FRINTxx is only in the vector form */
12652 if (only_in_vector
) {
12653 unallocated_encoding(s
);
12658 if (!fp_access_check(s
)) {
12662 if (need_rmode
|| need_fpst
) {
12663 tcg_fpstatus
= get_fpstatus_ptr(true);
12667 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12668 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12672 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12673 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12676 case 0x1a: /* FCVTNS */
12677 case 0x1b: /* FCVTMS */
12678 case 0x1c: /* FCVTAS */
12679 case 0x3a: /* FCVTPS */
12680 case 0x3b: /* FCVTZS */
12681 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12683 case 0x3d: /* FRECPE */
12684 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12686 case 0x3f: /* FRECPX */
12687 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12689 case 0x5a: /* FCVTNU */
12690 case 0x5b: /* FCVTMU */
12691 case 0x5c: /* FCVTAU */
12692 case 0x7a: /* FCVTPU */
12693 case 0x7b: /* FCVTZU */
12694 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12696 case 0x6f: /* FNEG */
12697 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12699 case 0x7d: /* FRSQRTE */
12700 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12703 g_assert_not_reached();
12706 /* limit any sign extension going on */
12707 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12708 write_fp_sreg(s
, rd
, tcg_res
);
12710 tcg_temp_free_i32(tcg_res
);
12711 tcg_temp_free_i32(tcg_op
);
12713 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12714 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12715 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12717 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12720 case 0x1a: /* FCVTNS */
12721 case 0x1b: /* FCVTMS */
12722 case 0x1c: /* FCVTAS */
12723 case 0x3a: /* FCVTPS */
12724 case 0x3b: /* FCVTZS */
12725 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12727 case 0x3d: /* FRECPE */
12728 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12730 case 0x5a: /* FCVTNU */
12731 case 0x5b: /* FCVTMU */
12732 case 0x5c: /* FCVTAU */
12733 case 0x7a: /* FCVTPU */
12734 case 0x7b: /* FCVTZU */
12735 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12737 case 0x18: /* FRINTN */
12738 case 0x19: /* FRINTM */
12739 case 0x38: /* FRINTP */
12740 case 0x39: /* FRINTZ */
12741 case 0x58: /* FRINTA */
12742 case 0x79: /* FRINTI */
12743 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12745 case 0x59: /* FRINTX */
12746 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12748 case 0x2f: /* FABS */
12749 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12751 case 0x6f: /* FNEG */
12752 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12754 case 0x7d: /* FRSQRTE */
12755 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12757 case 0x7f: /* FSQRT */
12758 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12761 g_assert_not_reached();
12764 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12766 tcg_temp_free_i32(tcg_res
);
12767 tcg_temp_free_i32(tcg_op
);
12770 clear_vec_high(s
, is_q
, rd
);
12774 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12775 tcg_temp_free_i32(tcg_rmode
);
12778 if (tcg_fpstatus
) {
12779 tcg_temp_free_ptr(tcg_fpstatus
);
12783 /* AdvSIMD scalar x indexed element
12784 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12785 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12786 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12787 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12788 * AdvSIMD vector x indexed element
12789 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12790 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12791 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12792 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12794 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12796 /* This encoding has two kinds of instruction:
12797 * normal, where we perform elt x idxelt => elt for each
12798 * element in the vector
12799 * long, where we perform elt x idxelt and generate a result of
12800 * double the width of the input element
12801 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12803 bool is_scalar
= extract32(insn
, 28, 1);
12804 bool is_q
= extract32(insn
, 30, 1);
12805 bool u
= extract32(insn
, 29, 1);
12806 int size
= extract32(insn
, 22, 2);
12807 int l
= extract32(insn
, 21, 1);
12808 int m
= extract32(insn
, 20, 1);
12809 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12810 int rm
= extract32(insn
, 16, 4);
12811 int opcode
= extract32(insn
, 12, 4);
12812 int h
= extract32(insn
, 11, 1);
12813 int rn
= extract32(insn
, 5, 5);
12814 int rd
= extract32(insn
, 0, 5);
12815 bool is_long
= false;
12817 bool is_fp16
= false;
12821 switch (16 * u
+ opcode
) {
12822 case 0x08: /* MUL */
12823 case 0x10: /* MLA */
12824 case 0x14: /* MLS */
12826 unallocated_encoding(s
);
12830 case 0x02: /* SMLAL, SMLAL2 */
12831 case 0x12: /* UMLAL, UMLAL2 */
12832 case 0x06: /* SMLSL, SMLSL2 */
12833 case 0x16: /* UMLSL, UMLSL2 */
12834 case 0x0a: /* SMULL, SMULL2 */
12835 case 0x1a: /* UMULL, UMULL2 */
12837 unallocated_encoding(s
);
12842 case 0x03: /* SQDMLAL, SQDMLAL2 */
12843 case 0x07: /* SQDMLSL, SQDMLSL2 */
12844 case 0x0b: /* SQDMULL, SQDMULL2 */
12847 case 0x0c: /* SQDMULH */
12848 case 0x0d: /* SQRDMULH */
12850 case 0x01: /* FMLA */
12851 case 0x05: /* FMLS */
12852 case 0x09: /* FMUL */
12853 case 0x19: /* FMULX */
12856 case 0x1d: /* SQRDMLAH */
12857 case 0x1f: /* SQRDMLSH */
12858 if (!dc_isar_feature(aa64_rdm
, s
)) {
12859 unallocated_encoding(s
);
12863 case 0x0e: /* SDOT */
12864 case 0x1e: /* UDOT */
12865 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12866 unallocated_encoding(s
);
12870 case 0x11: /* FCMLA #0 */
12871 case 0x13: /* FCMLA #90 */
12872 case 0x15: /* FCMLA #180 */
12873 case 0x17: /* FCMLA #270 */
12874 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12875 unallocated_encoding(s
);
12880 case 0x00: /* FMLAL */
12881 case 0x04: /* FMLSL */
12882 case 0x18: /* FMLAL2 */
12883 case 0x1c: /* FMLSL2 */
12884 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12885 unallocated_encoding(s
);
12889 /* is_fp, but we pass cpu_env not fp_status. */
12892 unallocated_encoding(s
);
12897 case 1: /* normal fp */
12898 /* convert insn encoded size to MemOp size */
12900 case 0: /* half-precision */
12904 case MO_32
: /* single precision */
12905 case MO_64
: /* double precision */
12908 unallocated_encoding(s
);
12913 case 2: /* complex fp */
12914 /* Each indexable element is a complex pair. */
12919 unallocated_encoding(s
);
12927 unallocated_encoding(s
);
12932 default: /* integer */
12936 unallocated_encoding(s
);
12941 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12942 unallocated_encoding(s
);
12946 /* Given MemOp size, adjust register and indexing. */
12949 index
= h
<< 2 | l
<< 1 | m
;
12952 index
= h
<< 1 | l
;
12957 unallocated_encoding(s
);
12964 g_assert_not_reached();
12967 if (!fp_access_check(s
)) {
12972 fpst
= get_fpstatus_ptr(is_fp16
);
12977 switch (16 * u
+ opcode
) {
12978 case 0x0e: /* SDOT */
12979 case 0x1e: /* UDOT */
12980 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12981 u
? gen_helper_gvec_udot_idx_b
12982 : gen_helper_gvec_sdot_idx_b
);
12984 case 0x11: /* FCMLA #0 */
12985 case 0x13: /* FCMLA #90 */
12986 case 0x15: /* FCMLA #180 */
12987 case 0x17: /* FCMLA #270 */
12989 int rot
= extract32(insn
, 13, 2);
12990 int data
= (index
<< 2) | rot
;
12991 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12992 vec_full_reg_offset(s
, rn
),
12993 vec_full_reg_offset(s
, rm
), fpst
,
12994 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12996 ? gen_helper_gvec_fcmlas_idx
12997 : gen_helper_gvec_fcmlah_idx
);
12998 tcg_temp_free_ptr(fpst
);
13002 case 0x00: /* FMLAL */
13003 case 0x04: /* FMLSL */
13004 case 0x18: /* FMLAL2 */
13005 case 0x1c: /* FMLSL2 */
13007 int is_s
= extract32(opcode
, 2, 1);
13009 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13010 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13011 vec_full_reg_offset(s
, rn
),
13012 vec_full_reg_offset(s
, rm
), cpu_env
,
13013 is_q
? 16 : 8, vec_full_reg_size(s
),
13014 data
, gen_helper_gvec_fmlal_idx_a64
);
13020 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13023 assert(is_fp
&& is_q
&& !is_long
);
13025 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13027 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13028 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13029 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13031 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13033 switch (16 * u
+ opcode
) {
13034 case 0x05: /* FMLS */
13035 /* As usual for ARM, separate negation for fused multiply-add */
13036 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13038 case 0x01: /* FMLA */
13039 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13040 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13042 case 0x09: /* FMUL */
13043 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13045 case 0x19: /* FMULX */
13046 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13049 g_assert_not_reached();
13052 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13053 tcg_temp_free_i64(tcg_op
);
13054 tcg_temp_free_i64(tcg_res
);
13057 tcg_temp_free_i64(tcg_idx
);
13058 clear_vec_high(s
, !is_scalar
, rd
);
13059 } else if (!is_long
) {
13060 /* 32 bit floating point, or 16 or 32 bit integer.
13061 * For the 16 bit scalar case we use the usual Neon helpers and
13062 * rely on the fact that 0 op 0 == 0 with no side effects.
13064 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13065 int pass
, maxpasses
;
13070 maxpasses
= is_q
? 4 : 2;
13073 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13075 if (size
== 1 && !is_scalar
) {
13076 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13077 * the index into both halves of the 32 bit tcg_idx and then use
13078 * the usual Neon helpers.
13080 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13083 for (pass
= 0; pass
< maxpasses
; pass
++) {
13084 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13085 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13087 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13089 switch (16 * u
+ opcode
) {
13090 case 0x08: /* MUL */
13091 case 0x10: /* MLA */
13092 case 0x14: /* MLS */
13094 static NeonGenTwoOpFn
* const fns
[2][2] = {
13095 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13096 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13098 NeonGenTwoOpFn
*genfn
;
13099 bool is_sub
= opcode
== 0x4;
13102 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13104 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13106 if (opcode
== 0x8) {
13109 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13110 genfn
= fns
[size
- 1][is_sub
];
13111 genfn(tcg_res
, tcg_op
, tcg_res
);
13114 case 0x05: /* FMLS */
13115 case 0x01: /* FMLA */
13116 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13117 is_scalar
? size
: MO_32
);
13120 if (opcode
== 0x5) {
13121 /* As usual for ARM, separate negation for fused
13123 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13126 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13129 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13134 if (opcode
== 0x5) {
13135 /* As usual for ARM, separate negation for
13136 * fused multiply-add */
13137 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13139 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13143 g_assert_not_reached();
13146 case 0x09: /* FMUL */
13150 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13153 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13158 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13161 g_assert_not_reached();
13164 case 0x19: /* FMULX */
13168 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13171 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13176 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13179 g_assert_not_reached();
13182 case 0x0c: /* SQDMULH */
13184 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13187 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13191 case 0x0d: /* SQRDMULH */
13193 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13196 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13200 case 0x1d: /* SQRDMLAH */
13201 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13202 is_scalar
? size
: MO_32
);
13204 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13205 tcg_op
, tcg_idx
, tcg_res
);
13207 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13208 tcg_op
, tcg_idx
, tcg_res
);
13211 case 0x1f: /* SQRDMLSH */
13212 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13213 is_scalar
? size
: MO_32
);
13215 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13216 tcg_op
, tcg_idx
, tcg_res
);
13218 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13219 tcg_op
, tcg_idx
, tcg_res
);
13223 g_assert_not_reached();
13227 write_fp_sreg(s
, rd
, tcg_res
);
13229 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13232 tcg_temp_free_i32(tcg_op
);
13233 tcg_temp_free_i32(tcg_res
);
13236 tcg_temp_free_i32(tcg_idx
);
13237 clear_vec_high(s
, is_q
, rd
);
13239 /* long ops: 16x16->32 or 32x32->64 */
13240 TCGv_i64 tcg_res
[2];
13242 bool satop
= extract32(opcode
, 0, 1);
13243 MemOp memop
= MO_32
;
13250 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13252 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13254 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13255 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13256 TCGv_i64 tcg_passres
;
13262 passelt
= pass
+ (is_q
* 2);
13265 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13267 tcg_res
[pass
] = tcg_temp_new_i64();
13269 if (opcode
== 0xa || opcode
== 0xb) {
13270 /* Non-accumulating ops */
13271 tcg_passres
= tcg_res
[pass
];
13273 tcg_passres
= tcg_temp_new_i64();
13276 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13277 tcg_temp_free_i64(tcg_op
);
13280 /* saturating, doubling */
13281 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13282 tcg_passres
, tcg_passres
);
13285 if (opcode
== 0xa || opcode
== 0xb) {
13289 /* Accumulating op: handle accumulate step */
13290 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13293 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13294 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13296 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13297 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13299 case 0x7: /* SQDMLSL, SQDMLSL2 */
13300 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13302 case 0x3: /* SQDMLAL, SQDMLAL2 */
13303 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13308 g_assert_not_reached();
13310 tcg_temp_free_i64(tcg_passres
);
13312 tcg_temp_free_i64(tcg_idx
);
13314 clear_vec_high(s
, !is_scalar
, rd
);
13316 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13319 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13322 /* The simplest way to handle the 16x16 indexed ops is to
13323 * duplicate the index into both halves of the 32 bit tcg_idx
13324 * and then use the usual Neon helpers.
13326 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13329 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13330 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13331 TCGv_i64 tcg_passres
;
13334 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13336 read_vec_element_i32(s
, tcg_op
, rn
,
13337 pass
+ (is_q
* 2), MO_32
);
13340 tcg_res
[pass
] = tcg_temp_new_i64();
13342 if (opcode
== 0xa || opcode
== 0xb) {
13343 /* Non-accumulating ops */
13344 tcg_passres
= tcg_res
[pass
];
13346 tcg_passres
= tcg_temp_new_i64();
13349 if (memop
& MO_SIGN
) {
13350 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13352 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13355 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13356 tcg_passres
, tcg_passres
);
13358 tcg_temp_free_i32(tcg_op
);
13360 if (opcode
== 0xa || opcode
== 0xb) {
13364 /* Accumulating op: handle accumulate step */
13365 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13368 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13369 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13372 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13373 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13376 case 0x7: /* SQDMLSL, SQDMLSL2 */
13377 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13379 case 0x3: /* SQDMLAL, SQDMLAL2 */
13380 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13385 g_assert_not_reached();
13387 tcg_temp_free_i64(tcg_passres
);
13389 tcg_temp_free_i32(tcg_idx
);
13392 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13397 tcg_res
[1] = tcg_const_i64(0);
13400 for (pass
= 0; pass
< 2; pass
++) {
13401 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13402 tcg_temp_free_i64(tcg_res
[pass
]);
13407 tcg_temp_free_ptr(fpst
);
13412 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13413 * +-----------------+------+-----------+--------+-----+------+------+
13414 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13415 * +-----------------+------+-----------+--------+-----+------+------+
13417 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13419 int size
= extract32(insn
, 22, 2);
13420 int opcode
= extract32(insn
, 12, 5);
13421 int rn
= extract32(insn
, 5, 5);
13422 int rd
= extract32(insn
, 0, 5);
13424 gen_helper_gvec_2
*genfn2
= NULL
;
13425 gen_helper_gvec_3
*genfn3
= NULL
;
13427 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13428 unallocated_encoding(s
);
13433 case 0x4: /* AESE */
13435 genfn3
= gen_helper_crypto_aese
;
13437 case 0x6: /* AESMC */
13439 genfn2
= gen_helper_crypto_aesmc
;
13441 case 0x5: /* AESD */
13443 genfn3
= gen_helper_crypto_aese
;
13445 case 0x7: /* AESIMC */
13447 genfn2
= gen_helper_crypto_aesmc
;
13450 unallocated_encoding(s
);
13454 if (!fp_access_check(s
)) {
13458 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13460 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13464 /* Crypto three-reg SHA
13465 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13466 * +-----------------+------+---+------+---+--------+-----+------+------+
13467 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13468 * +-----------------+------+---+------+---+--------+-----+------+------+
13470 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13472 int size
= extract32(insn
, 22, 2);
13473 int opcode
= extract32(insn
, 12, 3);
13474 int rm
= extract32(insn
, 16, 5);
13475 int rn
= extract32(insn
, 5, 5);
13476 int rd
= extract32(insn
, 0, 5);
13477 gen_helper_gvec_3
*genfn
;
13481 unallocated_encoding(s
);
13486 case 0: /* SHA1C */
13487 genfn
= gen_helper_crypto_sha1c
;
13488 feature
= dc_isar_feature(aa64_sha1
, s
);
13490 case 1: /* SHA1P */
13491 genfn
= gen_helper_crypto_sha1p
;
13492 feature
= dc_isar_feature(aa64_sha1
, s
);
13494 case 2: /* SHA1M */
13495 genfn
= gen_helper_crypto_sha1m
;
13496 feature
= dc_isar_feature(aa64_sha1
, s
);
13498 case 3: /* SHA1SU0 */
13499 genfn
= gen_helper_crypto_sha1su0
;
13500 feature
= dc_isar_feature(aa64_sha1
, s
);
13502 case 4: /* SHA256H */
13503 genfn
= gen_helper_crypto_sha256h
;
13504 feature
= dc_isar_feature(aa64_sha256
, s
);
13506 case 5: /* SHA256H2 */
13507 genfn
= gen_helper_crypto_sha256h2
;
13508 feature
= dc_isar_feature(aa64_sha256
, s
);
13510 case 6: /* SHA256SU1 */
13511 genfn
= gen_helper_crypto_sha256su1
;
13512 feature
= dc_isar_feature(aa64_sha256
, s
);
13515 unallocated_encoding(s
);
13520 unallocated_encoding(s
);
13524 if (!fp_access_check(s
)) {
13527 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
13530 /* Crypto two-reg SHA
13531 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13532 * +-----------------+------+-----------+--------+-----+------+------+
13533 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13534 * +-----------------+------+-----------+--------+-----+------+------+
13536 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13538 int size
= extract32(insn
, 22, 2);
13539 int opcode
= extract32(insn
, 12, 5);
13540 int rn
= extract32(insn
, 5, 5);
13541 int rd
= extract32(insn
, 0, 5);
13542 gen_helper_gvec_2
*genfn
;
13546 unallocated_encoding(s
);
13551 case 0: /* SHA1H */
13552 feature
= dc_isar_feature(aa64_sha1
, s
);
13553 genfn
= gen_helper_crypto_sha1h
;
13555 case 1: /* SHA1SU1 */
13556 feature
= dc_isar_feature(aa64_sha1
, s
);
13557 genfn
= gen_helper_crypto_sha1su1
;
13559 case 2: /* SHA256SU0 */
13560 feature
= dc_isar_feature(aa64_sha256
, s
);
13561 genfn
= gen_helper_crypto_sha256su0
;
13564 unallocated_encoding(s
);
13569 unallocated_encoding(s
);
13573 if (!fp_access_check(s
)) {
13576 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
13579 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
13581 tcg_gen_rotli_i64(d
, m
, 1);
13582 tcg_gen_xor_i64(d
, d
, n
);
13585 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
13587 tcg_gen_rotli_vec(vece
, d
, m
, 1);
13588 tcg_gen_xor_vec(vece
, d
, d
, n
);
13591 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
13592 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
13594 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
13595 static const GVecGen3 op
= {
13596 .fni8
= gen_rax1_i64
,
13597 .fniv
= gen_rax1_vec
,
13598 .opt_opc
= vecop_list
,
13599 .fno
= gen_helper_crypto_rax1
,
13602 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
13605 /* Crypto three-reg SHA512
13606 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13607 * +-----------------------+------+---+---+-----+--------+------+------+
13608 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13609 * +-----------------------+------+---+---+-----+--------+------+------+
13611 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13613 int opcode
= extract32(insn
, 10, 2);
13614 int o
= extract32(insn
, 14, 1);
13615 int rm
= extract32(insn
, 16, 5);
13616 int rn
= extract32(insn
, 5, 5);
13617 int rd
= extract32(insn
, 0, 5);
13619 gen_helper_gvec_3
*oolfn
= NULL
;
13620 GVecGen3Fn
*gvecfn
= NULL
;
13624 case 0: /* SHA512H */
13625 feature
= dc_isar_feature(aa64_sha512
, s
);
13626 oolfn
= gen_helper_crypto_sha512h
;
13628 case 1: /* SHA512H2 */
13629 feature
= dc_isar_feature(aa64_sha512
, s
);
13630 oolfn
= gen_helper_crypto_sha512h2
;
13632 case 2: /* SHA512SU1 */
13633 feature
= dc_isar_feature(aa64_sha512
, s
);
13634 oolfn
= gen_helper_crypto_sha512su1
;
13637 feature
= dc_isar_feature(aa64_sha3
, s
);
13638 gvecfn
= gen_gvec_rax1
;
13641 g_assert_not_reached();
13645 case 0: /* SM3PARTW1 */
13646 feature
= dc_isar_feature(aa64_sm3
, s
);
13647 oolfn
= gen_helper_crypto_sm3partw1
;
13649 case 1: /* SM3PARTW2 */
13650 feature
= dc_isar_feature(aa64_sm3
, s
);
13651 oolfn
= gen_helper_crypto_sm3partw2
;
13653 case 2: /* SM4EKEY */
13654 feature
= dc_isar_feature(aa64_sm4
, s
);
13655 oolfn
= gen_helper_crypto_sm4ekey
;
13658 unallocated_encoding(s
);
13664 unallocated_encoding(s
);
13668 if (!fp_access_check(s
)) {
13673 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
13675 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
13679 /* Crypto two-reg SHA512
13680 * 31 12 11 10 9 5 4 0
13681 * +-----------------------------------------+--------+------+------+
13682 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13683 * +-----------------------------------------+--------+------+------+
13685 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13687 int opcode
= extract32(insn
, 10, 2);
13688 int rn
= extract32(insn
, 5, 5);
13689 int rd
= extract32(insn
, 0, 5);
13693 case 0: /* SHA512SU0 */
13694 feature
= dc_isar_feature(aa64_sha512
, s
);
13697 feature
= dc_isar_feature(aa64_sm4
, s
);
13700 unallocated_encoding(s
);
13705 unallocated_encoding(s
);
13709 if (!fp_access_check(s
)) {
13714 case 0: /* SHA512SU0 */
13715 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
13718 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
13721 g_assert_not_reached();
13725 /* Crypto four-register
13726 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13727 * +-------------------+-----+------+---+------+------+------+
13728 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13729 * +-------------------+-----+------+---+------+------+------+
13731 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13733 int op0
= extract32(insn
, 21, 2);
13734 int rm
= extract32(insn
, 16, 5);
13735 int ra
= extract32(insn
, 10, 5);
13736 int rn
= extract32(insn
, 5, 5);
13737 int rd
= extract32(insn
, 0, 5);
13743 feature
= dc_isar_feature(aa64_sha3
, s
);
13745 case 2: /* SM3SS1 */
13746 feature
= dc_isar_feature(aa64_sm3
, s
);
13749 unallocated_encoding(s
);
13754 unallocated_encoding(s
);
13758 if (!fp_access_check(s
)) {
13763 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13766 tcg_op1
= tcg_temp_new_i64();
13767 tcg_op2
= tcg_temp_new_i64();
13768 tcg_op3
= tcg_temp_new_i64();
13769 tcg_res
[0] = tcg_temp_new_i64();
13770 tcg_res
[1] = tcg_temp_new_i64();
13772 for (pass
= 0; pass
< 2; pass
++) {
13773 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13774 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13775 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13779 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13782 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13784 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13786 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13787 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13789 tcg_temp_free_i64(tcg_op1
);
13790 tcg_temp_free_i64(tcg_op2
);
13791 tcg_temp_free_i64(tcg_op3
);
13792 tcg_temp_free_i64(tcg_res
[0]);
13793 tcg_temp_free_i64(tcg_res
[1]);
13795 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13797 tcg_op1
= tcg_temp_new_i32();
13798 tcg_op2
= tcg_temp_new_i32();
13799 tcg_op3
= tcg_temp_new_i32();
13800 tcg_res
= tcg_temp_new_i32();
13801 tcg_zero
= tcg_const_i32(0);
13803 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13804 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13805 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13807 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13808 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13809 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13810 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13812 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13813 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13814 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13815 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13817 tcg_temp_free_i32(tcg_op1
);
13818 tcg_temp_free_i32(tcg_op2
);
13819 tcg_temp_free_i32(tcg_op3
);
13820 tcg_temp_free_i32(tcg_res
);
13821 tcg_temp_free_i32(tcg_zero
);
13826 * 31 21 20 16 15 10 9 5 4 0
13827 * +-----------------------+------+--------+------+------+
13828 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13829 * +-----------------------+------+--------+------+------+
13831 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13833 int rm
= extract32(insn
, 16, 5);
13834 int imm6
= extract32(insn
, 10, 6);
13835 int rn
= extract32(insn
, 5, 5);
13836 int rd
= extract32(insn
, 0, 5);
13837 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13840 if (!dc_isar_feature(aa64_sha3
, s
)) {
13841 unallocated_encoding(s
);
13845 if (!fp_access_check(s
)) {
13849 tcg_op1
= tcg_temp_new_i64();
13850 tcg_op2
= tcg_temp_new_i64();
13851 tcg_res
[0] = tcg_temp_new_i64();
13852 tcg_res
[1] = tcg_temp_new_i64();
13854 for (pass
= 0; pass
< 2; pass
++) {
13855 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13856 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13858 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13859 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13861 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13862 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13864 tcg_temp_free_i64(tcg_op1
);
13865 tcg_temp_free_i64(tcg_op2
);
13866 tcg_temp_free_i64(tcg_res
[0]);
13867 tcg_temp_free_i64(tcg_res
[1]);
13870 /* Crypto three-reg imm2
13871 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13872 * +-----------------------+------+-----+------+--------+------+------+
13873 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13874 * +-----------------------+------+-----+------+--------+------+------+
13876 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13878 static gen_helper_gvec_3
* const fns
[4] = {
13879 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
13880 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
13882 int opcode
= extract32(insn
, 10, 2);
13883 int imm2
= extract32(insn
, 12, 2);
13884 int rm
= extract32(insn
, 16, 5);
13885 int rn
= extract32(insn
, 5, 5);
13886 int rd
= extract32(insn
, 0, 5);
13888 if (!dc_isar_feature(aa64_sm3
, s
)) {
13889 unallocated_encoding(s
);
13893 if (!fp_access_check(s
)) {
13897 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
13900 /* C3.6 Data processing - SIMD, inc Crypto
13902 * As the decode gets a little complex we are using a table based
13903 * approach for this part of the decode.
13905 static const AArch64DecodeTable data_proc_simd
[] = {
13906 /* pattern , mask , fn */
13907 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13908 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13909 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13910 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13911 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13912 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13913 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13914 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13915 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13916 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13917 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13918 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13919 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13920 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13921 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13922 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13923 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13924 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13925 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13926 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13927 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13928 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13929 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13930 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13931 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13932 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13933 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13934 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13935 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13936 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13937 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13938 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13939 { 0x00000000, 0x00000000, NULL
}
13942 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13944 /* Note that this is called with all non-FP cases from
13945 * table C3-6 so it must UNDEF for entries not specifically
13946 * allocated to instructions in that table.
13948 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13952 unallocated_encoding(s
);
13956 /* C3.6 Data processing - SIMD and floating point */
13957 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13959 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13960 disas_data_proc_fp(s
, insn
);
13962 /* SIMD, including crypto */
13963 disas_data_proc_simd(s
, insn
);
13969 * @env: The cpu environment
13970 * @s: The DisasContext
13972 * Return true if the page is guarded.
13974 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13976 #ifdef CONFIG_USER_ONLY
13977 return false; /* FIXME */
13979 uint64_t addr
= s
->base
.pc_first
;
13980 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13981 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13982 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13985 * We test this immediately after reading an insn, which means
13986 * that any normal page must be in the TLB. The only exception
13987 * would be for executing from flash or device memory, which
13988 * does not retain the TLB entry.
13990 * FIXME: Assume false for those, for now. We could use
13991 * arm_cpu_get_phys_page_attrs_debug to re-read the page
13992 * table entry even for that case.
13994 return (tlb_hit(entry
->addr_code
, addr
) &&
13995 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14000 * btype_destination_ok:
14001 * @insn: The instruction at the branch destination
14002 * @bt: SCTLR_ELx.BT
14003 * @btype: PSTATE.BTYPE, and is non-zero
14005 * On a guarded page, there are a limited number of insns
14006 * that may be present at the branch target:
14007 * - branch target identifiers,
14008 * - paciasp, pacibsp,
14011 * Anything else causes a Branch Target Exception.
14013 * Return true if the branch is compatible, false to raise BTITRAP.
14015 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14017 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14019 switch (extract32(insn
, 5, 7)) {
14020 case 0b011001: /* PACIASP */
14021 case 0b011011: /* PACIBSP */
14023 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14024 * with btype == 3. Otherwise all btype are ok.
14026 return !bt
|| btype
!= 3;
14027 case 0b100000: /* BTI */
14028 /* Not compatible with any btype. */
14030 case 0b100010: /* BTI c */
14031 /* Not compatible with btype == 3 */
14033 case 0b100100: /* BTI j */
14034 /* Not compatible with btype == 2 */
14036 case 0b100110: /* BTI jc */
14037 /* Compatible with any btype. */
14041 switch (insn
& 0xffe0001fu
) {
14042 case 0xd4200000u
: /* BRK */
14043 case 0xd4400000u
: /* HLT */
14044 /* Give priority to the breakpoint exception. */
14051 /* C3.1 A64 instruction index by encoding */
14052 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14056 s
->pc_curr
= s
->base
.pc_next
;
14057 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14059 s
->base
.pc_next
+= 4;
14061 s
->fp_access_checked
= false;
14063 if (dc_isar_feature(aa64_bti
, s
)) {
14064 if (s
->base
.num_insns
== 1) {
14066 * At the first insn of the TB, compute s->guarded_page.
14067 * We delayed computing this until successfully reading
14068 * the first insn of the TB, above. This (mostly) ensures
14069 * that the softmmu tlb entry has been populated, and the
14070 * page table GP bit is available.
14072 * Note that we need to compute this even if btype == 0,
14073 * because this value is used for BR instructions later
14074 * where ENV is not available.
14076 s
->guarded_page
= is_guarded_page(env
, s
);
14078 /* First insn can have btype set to non-zero. */
14079 tcg_debug_assert(s
->btype
>= 0);
14082 * Note that the Branch Target Exception has fairly high
14083 * priority -- below debugging exceptions but above most
14084 * everything else. This allows us to handle this now
14085 * instead of waiting until the insn is otherwise decoded.
14089 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14090 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14091 syn_btitrap(s
->btype
),
14092 default_exception_el(s
));
14096 /* Not the first insn: btype must be 0. */
14097 tcg_debug_assert(s
->btype
== 0);
14101 switch (extract32(insn
, 25, 4)) {
14102 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14103 unallocated_encoding(s
);
14106 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14107 unallocated_encoding(s
);
14110 case 0x8: case 0x9: /* Data processing - immediate */
14111 disas_data_proc_imm(s
, insn
);
14113 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14114 disas_b_exc_sys(s
, insn
);
14119 case 0xe: /* Loads and stores */
14120 disas_ldst(s
, insn
);
14123 case 0xd: /* Data processing - register */
14124 disas_data_proc_reg(s
, insn
);
14127 case 0xf: /* Data processing - SIMD and floating point */
14128 disas_data_proc_simd_fp(s
, insn
);
14131 assert(FALSE
); /* all 15 cases should be handled above */
14135 /* if we allocated any temporaries, free them here */
14139 * After execution of most insns, btype is reset to 0.
14140 * Note that we set btype == -1 when the insn sets btype.
14142 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14147 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14150 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14151 CPUARMState
*env
= cpu
->env_ptr
;
14152 ARMCPU
*arm_cpu
= env_archcpu(env
);
14153 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14154 int bound
, core_mmu_idx
;
14156 dc
->isar
= &arm_cpu
->isar
;
14160 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14161 * there is no secure EL1, so we route exceptions to EL3.
14163 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14164 !arm_el_is_aa64(env
, 3);
14167 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14168 dc
->condexec_mask
= 0;
14169 dc
->condexec_cond
= 0;
14170 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14171 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14172 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14173 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14174 dc
->tcma
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TCMA
);
14175 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14176 #if !defined(CONFIG_USER_ONLY)
14177 dc
->user
= (dc
->current_el
== 0);
14179 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14180 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14181 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14182 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14183 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14184 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14185 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14186 dc
->ata
= FIELD_EX32(tb_flags
, TBFLAG_A64
, ATA
);
14187 dc
->mte_active
[0] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE_ACTIVE
);
14188 dc
->mte_active
[1] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE0_ACTIVE
);
14190 dc
->vec_stride
= 0;
14191 dc
->cp_regs
= arm_cpu
->cp_regs
;
14192 dc
->features
= env
->features
;
14194 /* Single step state. The code-generation logic here is:
14196 * generate code with no special handling for single-stepping (except
14197 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14198 * this happens anyway because those changes are all system register or
14200 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14201 * emit code for one insn
14202 * emit code to clear PSTATE.SS
14203 * emit code to generate software step exception for completed step
14204 * end TB (as usual for having generated an exception)
14205 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14206 * emit code to generate a software step exception
14209 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14210 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14211 dc
->is_ldex
= false;
14212 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14214 /* Bound the number of insns to execute to those left on the page. */
14215 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14217 /* If architectural single step active, limit to 1. */
14218 if (dc
->ss_active
) {
14221 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14223 init_tmp_a64_array(dc
);
14226 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14230 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14232 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14234 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14235 dc
->insn_start
= tcg_last_op();
14238 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14239 const CPUBreakpoint
*bp
)
14241 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14243 if (bp
->flags
& BP_CPU
) {
14244 gen_a64_set_pc_im(dc
->base
.pc_next
);
14245 gen_helper_check_breakpoints(cpu_env
);
14246 /* End the TB early; it likely won't be executed */
14247 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14249 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14250 /* The address covered by the breakpoint must be
14251 included in [tb->pc, tb->pc + tb->size) in order
14252 to for it to be properly cleared -- thus we
14253 increment the PC here so that the logic setting
14254 tb->size below does the right thing. */
14255 dc
->base
.pc_next
+= 4;
14256 dc
->base
.is_jmp
= DISAS_NORETURN
;
14262 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14264 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14265 CPUARMState
*env
= cpu
->env_ptr
;
14267 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14268 /* Singlestep state is Active-pending.
14269 * If we're in this state at the start of a TB then either
14270 * a) we just took an exception to an EL which is being debugged
14271 * and this is the first insn in the exception handler
14272 * b) debug exceptions were masked and we just unmasked them
14273 * without changing EL (eg by clearing PSTATE.D)
14274 * In either case we're going to take a swstep exception in the
14275 * "did not step an insn" case, and so the syndrome ISV and EX
14276 * bits should be zero.
14278 assert(dc
->base
.num_insns
== 1);
14279 gen_swstep_exception(dc
, 0, 0);
14280 dc
->base
.is_jmp
= DISAS_NORETURN
;
14282 disas_a64_insn(env
, dc
);
14285 translator_loop_temp_check(&dc
->base
);
14288 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14290 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14292 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14293 /* Note that this means single stepping WFI doesn't halt the CPU.
14294 * For conditional branch insns this is harmless unreachable code as
14295 * gen_goto_tb() has already handled emitting the debug exception
14296 * (and thus a tb-jump is not possible when singlestepping).
14298 switch (dc
->base
.is_jmp
) {
14300 gen_a64_set_pc_im(dc
->base
.pc_next
);
14304 if (dc
->base
.singlestep_enabled
) {
14305 gen_exception_internal(EXCP_DEBUG
);
14307 gen_step_complete_exception(dc
);
14310 case DISAS_NORETURN
:
14314 switch (dc
->base
.is_jmp
) {
14316 case DISAS_TOO_MANY
:
14317 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14320 case DISAS_UPDATE_EXIT
:
14321 gen_a64_set_pc_im(dc
->base
.pc_next
);
14324 tcg_gen_exit_tb(NULL
, 0);
14326 case DISAS_UPDATE_NOCHAIN
:
14327 gen_a64_set_pc_im(dc
->base
.pc_next
);
14330 tcg_gen_lookup_and_goto_ptr();
14332 case DISAS_NORETURN
:
14336 gen_a64_set_pc_im(dc
->base
.pc_next
);
14337 gen_helper_wfe(cpu_env
);
14340 gen_a64_set_pc_im(dc
->base
.pc_next
);
14341 gen_helper_yield(cpu_env
);
14345 /* This is a special case because we don't want to just halt the CPU
14346 * if trying to debug across a WFI.
14348 TCGv_i32 tmp
= tcg_const_i32(4);
14350 gen_a64_set_pc_im(dc
->base
.pc_next
);
14351 gen_helper_wfi(cpu_env
, tmp
);
14352 tcg_temp_free_i32(tmp
);
14353 /* The helper doesn't necessarily throw an exception, but we
14354 * must go back to the main loop to check for interrupts anyway.
14356 tcg_gen_exit_tb(NULL
, 0);
14363 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14366 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14368 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14369 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14372 const TranslatorOps aarch64_translator_ops
= {
14373 .init_disas_context
= aarch64_tr_init_disas_context
,
14374 .tb_start
= aarch64_tr_tb_start
,
14375 .insn_start
= aarch64_tr_insn_start
,
14376 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14377 .translate_insn
= aarch64_tr_translate_insn
,
14378 .tb_stop
= aarch64_tr_tb_stop
,
14379 .disas_log
= aarch64_tr_disas_log
,