4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void gen_a64_set_pc_im(uint64_t val
)
156 tcg_gen_movi_i64(cpu_pc
, val
);
160 * Handle Top Byte Ignore (TBI) bits.
162 * If address tagging is enabled via the TCR TBI bits:
163 * + for EL2 and EL3 there is only one TBI bit, and if it is set
164 * then the address is zero-extended, clearing bits [63:56]
165 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
166 * and TBI1 controls addressses with bit 55 == 1.
167 * If the appropriate TBI bit is set for the address then
168 * the address is sign-extended from bit 55 into bits [63:56]
170 * Here We have concatenated TBI{1,0} into tbi.
172 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
173 TCGv_i64 src
, int tbi
)
176 /* Load unmodified address */
177 tcg_gen_mov_i64(dst
, src
);
178 } else if (s
->current_el
>= 2) {
179 /* FIXME: ARMv8.1-VHE S2 translation regime. */
180 /* Force tag byte to all zero */
181 tcg_gen_extract_i64(dst
, src
, 0, 56);
183 /* Sign-extend from bit 55. */
184 tcg_gen_sextract_i64(dst
, src
, 0, 56);
187 TCGv_i64 tcg_zero
= tcg_const_i64(0);
190 * The two TBI bits differ.
191 * If tbi0, then !tbi1: only use the extension if positive.
192 * if !tbi0, then tbi1: only use the extension if negative.
194 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
195 dst
, dst
, tcg_zero
, dst
, src
);
196 tcg_temp_free_i64(tcg_zero
);
201 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
204 * If address tagging is enabled for instructions via the TCR TBI bits,
205 * then loading an address into the PC will clear out any tag.
207 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
211 * Return a "clean" address for ADDR according to TBID.
212 * This is always a fresh temporary, as we need to be able to
213 * increment this independently of a dirty write-back address.
215 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
217 TCGv_i64 clean
= new_tmp_a64(s
);
218 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
222 typedef struct DisasCompare64
{
227 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
231 arm_test_cc(&c32
, cc
);
233 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
234 * properly. The NE/EQ comparisons are also fine with this choice. */
235 c64
->cond
= c32
.cond
;
236 c64
->value
= tcg_temp_new_i64();
237 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
242 static void a64_free_cc(DisasCompare64
*c64
)
244 tcg_temp_free_i64(c64
->value
);
247 static void gen_exception_internal(int excp
)
249 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
251 assert(excp_is_internal(excp
));
252 gen_helper_exception_internal(cpu_env
, tcg_excp
);
253 tcg_temp_free_i32(tcg_excp
);
256 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
258 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
259 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
260 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
262 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
264 tcg_temp_free_i32(tcg_el
);
265 tcg_temp_free_i32(tcg_syn
);
266 tcg_temp_free_i32(tcg_excp
);
269 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
271 gen_a64_set_pc_im(s
->pc
- offset
);
272 gen_exception_internal(excp
);
273 s
->base
.is_jmp
= DISAS_NORETURN
;
276 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
277 uint32_t syndrome
, uint32_t target_el
)
279 gen_a64_set_pc_im(s
->pc
- offset
);
280 gen_exception(excp
, syndrome
, target_el
);
281 s
->base
.is_jmp
= DISAS_NORETURN
;
284 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
289 gen_a64_set_pc_im(s
->pc
- offset
);
290 tcg_syn
= tcg_const_i32(syndrome
);
291 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
292 tcg_temp_free_i32(tcg_syn
);
293 s
->base
.is_jmp
= DISAS_NORETURN
;
296 static void gen_step_complete_exception(DisasContext
*s
)
298 /* We just completed step of an insn. Move from Active-not-pending
299 * to Active-pending, and then also take the swstep exception.
300 * This corresponds to making the (IMPDEF) choice to prioritize
301 * swstep exceptions over asynchronous exceptions taken to an exception
302 * level where debug is disabled. This choice has the advantage that
303 * we do not need to maintain internal state corresponding to the
304 * ISV/EX syndrome bits between completion of the step and generation
305 * of the exception, and our syndrome information is always correct.
308 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
309 default_exception_el(s
));
310 s
->base
.is_jmp
= DISAS_NORETURN
;
313 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
315 /* No direct tb linking with singlestep (either QEMU's or the ARM
316 * debug architecture kind) or deterministic io
318 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
319 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
323 #ifndef CONFIG_USER_ONLY
324 /* Only link tbs from inside the same guest page */
325 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
333 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
335 TranslationBlock
*tb
;
338 if (use_goto_tb(s
, n
, dest
)) {
340 gen_a64_set_pc_im(dest
);
341 tcg_gen_exit_tb(tb
, n
);
342 s
->base
.is_jmp
= DISAS_NORETURN
;
344 gen_a64_set_pc_im(dest
);
346 gen_step_complete_exception(s
);
347 } else if (s
->base
.singlestep_enabled
) {
348 gen_exception_internal(EXCP_DEBUG
);
350 tcg_gen_lookup_and_goto_ptr();
351 s
->base
.is_jmp
= DISAS_NORETURN
;
356 void unallocated_encoding(DisasContext
*s
)
358 /* Unallocated and reserved encodings are uncategorized */
359 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
360 default_exception_el(s
));
363 static void init_tmp_a64_array(DisasContext
*s
)
365 #ifdef CONFIG_DEBUG_TCG
366 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
368 s
->tmp_a64_count
= 0;
371 static void free_tmp_a64(DisasContext
*s
)
374 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
375 tcg_temp_free_i64(s
->tmp_a64
[i
]);
377 init_tmp_a64_array(s
);
380 TCGv_i64
new_tmp_a64(DisasContext
*s
)
382 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
383 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
386 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
388 TCGv_i64 t
= new_tmp_a64(s
);
389 tcg_gen_movi_i64(t
, 0);
394 * Register access functions
396 * These functions are used for directly accessing a register in where
397 * changes to the final register value are likely to be made. If you
398 * need to use a register for temporary calculation (e.g. index type
399 * operations) use the read_* form.
401 * B1.2.1 Register mappings
403 * In instruction register encoding 31 can refer to ZR (zero register) or
404 * the SP (stack pointer) depending on context. In QEMU's case we map SP
405 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
406 * This is the point of the _sp forms.
408 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
411 return new_tmp_a64_zero(s
);
417 /* register access for when 31 == SP */
418 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
423 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
424 * representing the register contents. This TCGv is an auto-freed
425 * temporary so it need not be explicitly freed, and may be modified.
427 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
429 TCGv_i64 v
= new_tmp_a64(s
);
432 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
434 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
437 tcg_gen_movi_i64(v
, 0);
442 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
444 TCGv_i64 v
= new_tmp_a64(s
);
446 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
448 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
453 /* Return the offset into CPUARMState of a slice (from
454 * the least significant end) of FP register Qn (ie
456 * (Note that this is not the same mapping as for A32; see cpu.h)
458 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
460 return vec_reg_offset(s
, regno
, 0, size
);
463 /* Offset of the high half of the 128 bit vector Qn */
464 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
466 return vec_reg_offset(s
, regno
, 1, MO_64
);
469 /* Convenience accessors for reading and writing single and double
470 * FP registers. Writing clears the upper parts of the associated
471 * 128 bit vector register, as required by the architecture.
472 * Note that unlike the GP register accessors, the values returned
473 * by the read functions must be manually freed.
475 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
477 TCGv_i64 v
= tcg_temp_new_i64();
479 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
483 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
485 TCGv_i32 v
= tcg_temp_new_i32();
487 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
491 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
493 TCGv_i32 v
= tcg_temp_new_i32();
495 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
499 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
500 * If SVE is not enabled, then there are only 128 bits in the vector.
502 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
504 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
505 unsigned vsz
= vec_full_reg_size(s
);
508 TCGv_i64 tcg_zero
= tcg_const_i64(0);
509 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
510 tcg_temp_free_i64(tcg_zero
);
513 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
517 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
519 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
521 tcg_gen_st_i64(v
, cpu_env
, ofs
);
522 clear_vec_high(s
, false, reg
);
525 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
527 TCGv_i64 tmp
= tcg_temp_new_i64();
529 tcg_gen_extu_i32_i64(tmp
, v
);
530 write_fp_dreg(s
, reg
, tmp
);
531 tcg_temp_free_i64(tmp
);
534 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
536 TCGv_ptr statusptr
= tcg_temp_new_ptr();
539 /* In A64 all instructions (both FP and Neon) use the FPCR; there
540 * is no equivalent of the A32 Neon "standard FPSCR value".
541 * However half-precision operations operate under a different
542 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
545 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
547 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
549 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
553 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
554 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
555 GVecGen2Fn
*gvec_fn
, int vece
)
557 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
558 is_q
? 16 : 8, vec_full_reg_size(s
));
561 /* Expand a 2-operand + immediate AdvSIMD vector operation using
562 * an expander function.
564 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
565 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
567 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
568 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
571 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
572 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
573 GVecGen3Fn
*gvec_fn
, int vece
)
575 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
576 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
579 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
580 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
581 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
583 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
584 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
585 is_q
? 16 : 8, vec_full_reg_size(s
));
588 /* Expand a 2-operand + immediate AdvSIMD vector operation using
591 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
592 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
594 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
595 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
598 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
599 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
600 int rn
, int rm
, const GVecGen3
*gvec_op
)
602 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
603 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
604 vec_full_reg_size(s
), gvec_op
);
607 /* Expand a 3-operand operation using an out-of-line helper. */
608 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
609 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
611 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
612 vec_full_reg_offset(s
, rn
),
613 vec_full_reg_offset(s
, rm
),
614 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
617 /* Expand a 3-operand + env pointer operation using
618 * an out-of-line helper.
620 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
621 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
623 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
624 vec_full_reg_offset(s
, rn
),
625 vec_full_reg_offset(s
, rm
), cpu_env
,
626 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
629 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
630 * an out-of-line helper.
632 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
633 int rm
, bool is_fp16
, int data
,
634 gen_helper_gvec_3_ptr
*fn
)
636 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
637 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
638 vec_full_reg_offset(s
, rn
),
639 vec_full_reg_offset(s
, rm
), fpst
,
640 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
641 tcg_temp_free_ptr(fpst
);
644 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
645 * than the 32 bit equivalent.
647 static inline void gen_set_NZ64(TCGv_i64 result
)
649 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
650 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
653 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
654 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
657 gen_set_NZ64(result
);
659 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
660 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
662 tcg_gen_movi_i32(cpu_CF
, 0);
663 tcg_gen_movi_i32(cpu_VF
, 0);
666 /* dest = T0 + T1; compute C, N, V and Z flags */
667 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
670 TCGv_i64 result
, flag
, tmp
;
671 result
= tcg_temp_new_i64();
672 flag
= tcg_temp_new_i64();
673 tmp
= tcg_temp_new_i64();
675 tcg_gen_movi_i64(tmp
, 0);
676 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
678 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
680 gen_set_NZ64(result
);
682 tcg_gen_xor_i64(flag
, result
, t0
);
683 tcg_gen_xor_i64(tmp
, t0
, t1
);
684 tcg_gen_andc_i64(flag
, flag
, tmp
);
685 tcg_temp_free_i64(tmp
);
686 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
688 tcg_gen_mov_i64(dest
, result
);
689 tcg_temp_free_i64(result
);
690 tcg_temp_free_i64(flag
);
692 /* 32 bit arithmetic */
693 TCGv_i32 t0_32
= tcg_temp_new_i32();
694 TCGv_i32 t1_32
= tcg_temp_new_i32();
695 TCGv_i32 tmp
= tcg_temp_new_i32();
697 tcg_gen_movi_i32(tmp
, 0);
698 tcg_gen_extrl_i64_i32(t0_32
, t0
);
699 tcg_gen_extrl_i64_i32(t1_32
, t1
);
700 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
701 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
702 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
703 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
704 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
705 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
707 tcg_temp_free_i32(tmp
);
708 tcg_temp_free_i32(t0_32
);
709 tcg_temp_free_i32(t1_32
);
713 /* dest = T0 - T1; compute C, N, V and Z flags */
714 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
717 /* 64 bit arithmetic */
718 TCGv_i64 result
, flag
, tmp
;
720 result
= tcg_temp_new_i64();
721 flag
= tcg_temp_new_i64();
722 tcg_gen_sub_i64(result
, t0
, t1
);
724 gen_set_NZ64(result
);
726 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
727 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
729 tcg_gen_xor_i64(flag
, result
, t0
);
730 tmp
= tcg_temp_new_i64();
731 tcg_gen_xor_i64(tmp
, t0
, t1
);
732 tcg_gen_and_i64(flag
, flag
, tmp
);
733 tcg_temp_free_i64(tmp
);
734 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
735 tcg_gen_mov_i64(dest
, result
);
736 tcg_temp_free_i64(flag
);
737 tcg_temp_free_i64(result
);
739 /* 32 bit arithmetic */
740 TCGv_i32 t0_32
= tcg_temp_new_i32();
741 TCGv_i32 t1_32
= tcg_temp_new_i32();
744 tcg_gen_extrl_i64_i32(t0_32
, t0
);
745 tcg_gen_extrl_i64_i32(t1_32
, t1
);
746 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
747 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
748 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
749 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
750 tmp
= tcg_temp_new_i32();
751 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
752 tcg_temp_free_i32(t0_32
);
753 tcg_temp_free_i32(t1_32
);
754 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
755 tcg_temp_free_i32(tmp
);
756 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
760 /* dest = T0 + T1 + CF; do not compute flags. */
761 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
763 TCGv_i64 flag
= tcg_temp_new_i64();
764 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
765 tcg_gen_add_i64(dest
, t0
, t1
);
766 tcg_gen_add_i64(dest
, dest
, flag
);
767 tcg_temp_free_i64(flag
);
770 tcg_gen_ext32u_i64(dest
, dest
);
774 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
775 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
778 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
779 result
= tcg_temp_new_i64();
780 cf_64
= tcg_temp_new_i64();
781 vf_64
= tcg_temp_new_i64();
782 tmp
= tcg_const_i64(0);
784 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
785 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
786 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
787 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
788 gen_set_NZ64(result
);
790 tcg_gen_xor_i64(vf_64
, result
, t0
);
791 tcg_gen_xor_i64(tmp
, t0
, t1
);
792 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
793 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
795 tcg_gen_mov_i64(dest
, result
);
797 tcg_temp_free_i64(tmp
);
798 tcg_temp_free_i64(vf_64
);
799 tcg_temp_free_i64(cf_64
);
800 tcg_temp_free_i64(result
);
802 TCGv_i32 t0_32
, t1_32
, tmp
;
803 t0_32
= tcg_temp_new_i32();
804 t1_32
= tcg_temp_new_i32();
805 tmp
= tcg_const_i32(0);
807 tcg_gen_extrl_i64_i32(t0_32
, t0
);
808 tcg_gen_extrl_i64_i32(t1_32
, t1
);
809 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
810 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
812 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
813 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
814 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
815 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
816 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
818 tcg_temp_free_i32(tmp
);
819 tcg_temp_free_i32(t1_32
);
820 tcg_temp_free_i32(t0_32
);
825 * Load/Store generators
829 * Store from GPR register to memory.
831 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
832 TCGv_i64 tcg_addr
, int size
, int memidx
,
834 unsigned int iss_srt
,
835 bool iss_sf
, bool iss_ar
)
838 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
843 syn
= syn_data_abort_with_iss(0,
849 0, 0, 0, 0, 0, false);
850 disas_set_insn_syndrome(s
, syn
);
854 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
855 TCGv_i64 tcg_addr
, int size
,
857 unsigned int iss_srt
,
858 bool iss_sf
, bool iss_ar
)
860 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
861 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
865 * Load from memory to GPR register
867 static void do_gpr_ld_memidx(DisasContext
*s
,
868 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
869 int size
, bool is_signed
,
870 bool extend
, int memidx
,
871 bool iss_valid
, unsigned int iss_srt
,
872 bool iss_sf
, bool iss_ar
)
874 TCGMemOp memop
= s
->be_data
+ size
;
882 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
884 if (extend
&& is_signed
) {
886 tcg_gen_ext32u_i64(dest
, dest
);
892 syn
= syn_data_abort_with_iss(0,
898 0, 0, 0, 0, 0, false);
899 disas_set_insn_syndrome(s
, syn
);
903 static void do_gpr_ld(DisasContext
*s
,
904 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
905 int size
, bool is_signed
, bool extend
,
906 bool iss_valid
, unsigned int iss_srt
,
907 bool iss_sf
, bool iss_ar
)
909 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
911 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
915 * Store from FP register to memory
917 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
919 /* This writes the bottom N bits of a 128 bit wide vector to memory */
920 TCGv_i64 tmp
= tcg_temp_new_i64();
921 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
923 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
926 bool be
= s
->be_data
== MO_BE
;
927 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
929 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
930 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
932 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
933 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
935 tcg_temp_free_i64(tcg_hiaddr
);
938 tcg_temp_free_i64(tmp
);
942 * Load from memory to FP register
944 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
946 /* This always zero-extends and writes to a full 128 bit wide vector */
947 TCGv_i64 tmplo
= tcg_temp_new_i64();
951 TCGMemOp memop
= s
->be_data
+ size
;
952 tmphi
= tcg_const_i64(0);
953 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
955 bool be
= s
->be_data
== MO_BE
;
958 tmphi
= tcg_temp_new_i64();
959 tcg_hiaddr
= tcg_temp_new_i64();
961 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
962 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
964 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
966 tcg_temp_free_i64(tcg_hiaddr
);
969 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
970 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
972 tcg_temp_free_i64(tmplo
);
973 tcg_temp_free_i64(tmphi
);
975 clear_vec_high(s
, true, destidx
);
979 * Vector load/store helpers.
981 * The principal difference between this and a FP load is that we don't
982 * zero extend as we are filling a partial chunk of the vector register.
983 * These functions don't support 128 bit loads/stores, which would be
984 * normal load/store operations.
986 * The _i32 versions are useful when operating on 32 bit quantities
987 * (eg for floating point single or using Neon helper functions).
990 /* Get value of an element within a vector register */
991 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
992 int element
, TCGMemOp memop
)
994 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
997 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1000 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1003 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1006 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1009 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1016 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1019 g_assert_not_reached();
1023 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1024 int element
, TCGMemOp memop
)
1026 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1029 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1032 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1035 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1038 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1042 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1045 g_assert_not_reached();
1049 /* Set value of an element within a vector register */
1050 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1051 int element
, TCGMemOp memop
)
1053 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1056 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1059 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1062 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1065 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1068 g_assert_not_reached();
1072 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1073 int destidx
, int element
, TCGMemOp memop
)
1075 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1078 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1081 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1084 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1087 g_assert_not_reached();
1091 /* Store from vector register to memory */
1092 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1093 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1095 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1097 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1098 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1100 tcg_temp_free_i64(tcg_tmp
);
1103 /* Load from memory to vector register */
1104 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1105 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1107 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1109 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1110 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1112 tcg_temp_free_i64(tcg_tmp
);
1115 /* Check that FP/Neon access is enabled. If it is, return
1116 * true. If not, emit code to generate an appropriate exception,
1117 * and return false; the caller should not emit any code for
1118 * the instruction. Note that this check must happen after all
1119 * unallocated-encoding checks (otherwise the syndrome information
1120 * for the resulting exception will be incorrect).
1122 static inline bool fp_access_check(DisasContext
*s
)
1124 assert(!s
->fp_access_checked
);
1125 s
->fp_access_checked
= true;
1127 if (!s
->fp_excp_el
) {
1131 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1136 /* Check that SVE access is enabled. If it is, return true.
1137 * If not, emit code to generate an appropriate exception and return false.
1139 bool sve_access_check(DisasContext
*s
)
1141 if (s
->sve_excp_el
) {
1142 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1146 return fp_access_check(s
);
1150 * This utility function is for doing register extension with an
1151 * optional shift. You will likely want to pass a temporary for the
1152 * destination register. See DecodeRegExtend() in the ARM ARM.
1154 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1155 int option
, unsigned int shift
)
1157 int extsize
= extract32(option
, 0, 2);
1158 bool is_signed
= extract32(option
, 2, 1);
1163 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1166 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1169 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1172 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1178 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1181 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1184 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1187 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1193 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1197 static inline void gen_check_sp_alignment(DisasContext
*s
)
1199 /* The AArch64 architecture mandates that (if enabled via PSTATE
1200 * or SCTLR bits) there is a check that SP is 16-aligned on every
1201 * SP-relative load or store (with an exception generated if it is not).
1202 * In line with general QEMU practice regarding misaligned accesses,
1203 * we omit these checks for the sake of guest program performance.
1204 * This function is provided as a hook so we can more easily add these
1205 * checks in future (possibly as a "favour catching guest program bugs
1206 * over speed" user selectable option).
1211 * This provides a simple table based table lookup decoder. It is
1212 * intended to be used when the relevant bits for decode are too
1213 * awkwardly placed and switch/if based logic would be confusing and
1214 * deeply nested. Since it's a linear search through the table, tables
1215 * should be kept small.
1217 * It returns the first handler where insn & mask == pattern, or
1218 * NULL if there is no match.
1219 * The table is terminated by an empty mask (i.e. 0)
1221 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1224 const AArch64DecodeTable
*tptr
= table
;
1226 while (tptr
->mask
) {
1227 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1228 return tptr
->disas_fn
;
1236 * The instruction disassembly implemented here matches
1237 * the instruction encoding classifications in chapter C4
1238 * of the ARM Architecture Reference Manual (DDI0487B_a);
1239 * classification names and decode diagrams here should generally
1240 * match up with those in the manual.
1243 /* Unconditional branch (immediate)
1245 * +----+-----------+-------------------------------------+
1246 * | op | 0 0 1 0 1 | imm26 |
1247 * +----+-----------+-------------------------------------+
1249 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1251 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1253 if (insn
& (1U << 31)) {
1254 /* BL Branch with link */
1255 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1258 /* B Branch / BL Branch with link */
1260 gen_goto_tb(s
, 0, addr
);
1263 /* Compare and branch (immediate)
1264 * 31 30 25 24 23 5 4 0
1265 * +----+-------------+----+---------------------+--------+
1266 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1267 * +----+-------------+----+---------------------+--------+
1269 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1271 unsigned int sf
, op
, rt
;
1273 TCGLabel
*label_match
;
1276 sf
= extract32(insn
, 31, 1);
1277 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1278 rt
= extract32(insn
, 0, 5);
1279 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1281 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1282 label_match
= gen_new_label();
1285 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1286 tcg_cmp
, 0, label_match
);
1288 gen_goto_tb(s
, 0, s
->pc
);
1289 gen_set_label(label_match
);
1290 gen_goto_tb(s
, 1, addr
);
1293 /* Test and branch (immediate)
1294 * 31 30 25 24 23 19 18 5 4 0
1295 * +----+-------------+----+-------+-------------+------+
1296 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1297 * +----+-------------+----+-------+-------------+------+
1299 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1301 unsigned int bit_pos
, op
, rt
;
1303 TCGLabel
*label_match
;
1306 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1307 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1308 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1309 rt
= extract32(insn
, 0, 5);
1311 tcg_cmp
= tcg_temp_new_i64();
1312 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1313 label_match
= gen_new_label();
1316 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1317 tcg_cmp
, 0, label_match
);
1318 tcg_temp_free_i64(tcg_cmp
);
1319 gen_goto_tb(s
, 0, s
->pc
);
1320 gen_set_label(label_match
);
1321 gen_goto_tb(s
, 1, addr
);
1324 /* Conditional branch (immediate)
1325 * 31 25 24 23 5 4 3 0
1326 * +---------------+----+---------------------+----+------+
1327 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1328 * +---------------+----+---------------------+----+------+
1330 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1335 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1336 unallocated_encoding(s
);
1339 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1340 cond
= extract32(insn
, 0, 4);
1344 /* genuinely conditional branches */
1345 TCGLabel
*label_match
= gen_new_label();
1346 arm_gen_test_cc(cond
, label_match
);
1347 gen_goto_tb(s
, 0, s
->pc
);
1348 gen_set_label(label_match
);
1349 gen_goto_tb(s
, 1, addr
);
1351 /* 0xe and 0xf are both "always" conditions */
1352 gen_goto_tb(s
, 0, addr
);
1356 /* HINT instruction group, including various allocated HINTs */
1357 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1358 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1360 unsigned int selector
= crm
<< 3 | op2
;
1363 unallocated_encoding(s
);
1368 case 0b00000: /* NOP */
1370 case 0b00011: /* WFI */
1371 s
->base
.is_jmp
= DISAS_WFI
;
1373 case 0b00001: /* YIELD */
1374 /* When running in MTTCG we don't generate jumps to the yield and
1375 * WFE helpers as it won't affect the scheduling of other vCPUs.
1376 * If we wanted to more completely model WFE/SEV so we don't busy
1377 * spin unnecessarily we would need to do something more involved.
1379 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1380 s
->base
.is_jmp
= DISAS_YIELD
;
1383 case 0b00010: /* WFE */
1384 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1385 s
->base
.is_jmp
= DISAS_WFE
;
1388 case 0b00100: /* SEV */
1389 case 0b00101: /* SEVL */
1390 /* we treat all as NOP at least for now */
1392 case 0b00111: /* XPACLRI */
1393 if (s
->pauth_active
) {
1394 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1397 case 0b01000: /* PACIA1716 */
1398 if (s
->pauth_active
) {
1399 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1402 case 0b01010: /* PACIB1716 */
1403 if (s
->pauth_active
) {
1404 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1407 case 0b01100: /* AUTIA1716 */
1408 if (s
->pauth_active
) {
1409 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1412 case 0b01110: /* AUTIB1716 */
1413 if (s
->pauth_active
) {
1414 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1417 case 0b11000: /* PACIAZ */
1418 if (s
->pauth_active
) {
1419 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1420 new_tmp_a64_zero(s
));
1423 case 0b11001: /* PACIASP */
1424 if (s
->pauth_active
) {
1425 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1428 case 0b11010: /* PACIBZ */
1429 if (s
->pauth_active
) {
1430 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1431 new_tmp_a64_zero(s
));
1434 case 0b11011: /* PACIBSP */
1435 if (s
->pauth_active
) {
1436 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1439 case 0b11100: /* AUTIAZ */
1440 if (s
->pauth_active
) {
1441 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1442 new_tmp_a64_zero(s
));
1445 case 0b11101: /* AUTIASP */
1446 if (s
->pauth_active
) {
1447 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1450 case 0b11110: /* AUTIBZ */
1451 if (s
->pauth_active
) {
1452 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1453 new_tmp_a64_zero(s
));
1456 case 0b11111: /* AUTIBSP */
1457 if (s
->pauth_active
) {
1458 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1462 /* default specified as NOP equivalent */
1467 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1469 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1472 /* CLREX, DSB, DMB, ISB */
1473 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1474 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1479 unallocated_encoding(s
);
1490 case 1: /* MBReqTypes_Reads */
1491 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1493 case 2: /* MBReqTypes_Writes */
1494 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1496 default: /* MBReqTypes_All */
1497 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1503 /* We need to break the TB after this insn to execute
1504 * a self-modified code correctly and also to take
1505 * any pending interrupts immediately.
1508 gen_goto_tb(s
, 0, s
->pc
);
1512 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1513 goto do_unallocated
;
1516 * TODO: There is no speculation barrier opcode for TCG;
1517 * MB and end the TB instead.
1519 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1520 gen_goto_tb(s
, 0, s
->pc
);
1525 unallocated_encoding(s
);
1530 static void gen_xaflag(void)
1532 TCGv_i32 z
= tcg_temp_new_i32();
1534 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1543 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1544 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1547 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1548 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1550 /* (!C & Z) << 31 -> -(Z & ~C) */
1551 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1552 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1555 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1557 tcg_temp_free_i32(z
);
1560 static void gen_axflag(void)
1562 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1563 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1565 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1566 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1568 tcg_gen_movi_i32(cpu_NF
, 0);
1569 tcg_gen_movi_i32(cpu_VF
, 0);
1572 /* MSR (immediate) - move immediate to processor state field */
1573 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1574 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1577 int op
= op1
<< 3 | op2
;
1579 /* End the TB by default, chaining is ok. */
1580 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1583 case 0x00: /* CFINV */
1584 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1585 goto do_unallocated
;
1587 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1588 s
->base
.is_jmp
= DISAS_NEXT
;
1591 case 0x01: /* XAFlag */
1592 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1593 goto do_unallocated
;
1596 s
->base
.is_jmp
= DISAS_NEXT
;
1599 case 0x02: /* AXFlag */
1600 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1601 goto do_unallocated
;
1604 s
->base
.is_jmp
= DISAS_NEXT
;
1607 case 0x05: /* SPSel */
1608 if (s
->current_el
== 0) {
1609 goto do_unallocated
;
1611 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1612 gen_helper_msr_i_spsel(cpu_env
, t1
);
1613 tcg_temp_free_i32(t1
);
1616 case 0x1e: /* DAIFSet */
1617 t1
= tcg_const_i32(crm
);
1618 gen_helper_msr_i_daifset(cpu_env
, t1
);
1619 tcg_temp_free_i32(t1
);
1622 case 0x1f: /* DAIFClear */
1623 t1
= tcg_const_i32(crm
);
1624 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1625 tcg_temp_free_i32(t1
);
1626 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1627 s
->base
.is_jmp
= DISAS_UPDATE
;
1632 unallocated_encoding(s
);
1637 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1639 TCGv_i32 tmp
= tcg_temp_new_i32();
1640 TCGv_i32 nzcv
= tcg_temp_new_i32();
1642 /* build bit 31, N */
1643 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1644 /* build bit 30, Z */
1645 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1646 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1647 /* build bit 29, C */
1648 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1649 /* build bit 28, V */
1650 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1651 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1652 /* generate result */
1653 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1655 tcg_temp_free_i32(nzcv
);
1656 tcg_temp_free_i32(tmp
);
1659 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1661 TCGv_i32 nzcv
= tcg_temp_new_i32();
1663 /* take NZCV from R[t] */
1664 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1667 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1669 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1670 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1672 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1673 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1675 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1676 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1677 tcg_temp_free_i32(nzcv
);
1680 /* MRS - move from system register
1681 * MSR (register) - move to system register
1684 * These are all essentially the same insn in 'read' and 'write'
1685 * versions, with varying op0 fields.
1687 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1688 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1689 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1691 const ARMCPRegInfo
*ri
;
1694 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1695 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1696 crn
, crm
, op0
, op1
, op2
));
1699 /* Unknown register; this might be a guest error or a QEMU
1700 * unimplemented feature.
1702 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1703 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1704 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1705 unallocated_encoding(s
);
1709 /* Check access permissions */
1710 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1711 unallocated_encoding(s
);
1716 /* Emit code to perform further access permissions checks at
1717 * runtime; this may result in an exception.
1720 TCGv_i32 tcg_syn
, tcg_isread
;
1723 gen_a64_set_pc_im(s
->pc
- 4);
1724 tmpptr
= tcg_const_ptr(ri
);
1725 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1726 tcg_syn
= tcg_const_i32(syndrome
);
1727 tcg_isread
= tcg_const_i32(isread
);
1728 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1729 tcg_temp_free_ptr(tmpptr
);
1730 tcg_temp_free_i32(tcg_syn
);
1731 tcg_temp_free_i32(tcg_isread
);
1734 /* Handle special cases first */
1735 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1739 tcg_rt
= cpu_reg(s
, rt
);
1741 gen_get_nzcv(tcg_rt
);
1743 gen_set_nzcv(tcg_rt
);
1746 case ARM_CP_CURRENTEL
:
1747 /* Reads as current EL value from pstate, which is
1748 * guaranteed to be constant by the tb flags.
1750 tcg_rt
= cpu_reg(s
, rt
);
1751 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1754 /* Writes clear the aligned block of memory which rt points into. */
1755 tcg_rt
= cpu_reg(s
, rt
);
1756 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1761 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1763 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1767 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1771 tcg_rt
= cpu_reg(s
, rt
);
1774 if (ri
->type
& ARM_CP_CONST
) {
1775 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1776 } else if (ri
->readfn
) {
1778 tmpptr
= tcg_const_ptr(ri
);
1779 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1780 tcg_temp_free_ptr(tmpptr
);
1782 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1785 if (ri
->type
& ARM_CP_CONST
) {
1786 /* If not forbidden by access permissions, treat as WI */
1788 } else if (ri
->writefn
) {
1790 tmpptr
= tcg_const_ptr(ri
);
1791 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1792 tcg_temp_free_ptr(tmpptr
);
1794 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1798 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1799 /* I/O operations must end the TB here (whether read or write) */
1801 s
->base
.is_jmp
= DISAS_UPDATE
;
1802 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1803 /* We default to ending the TB on a coprocessor register write,
1804 * but allow this to be suppressed by the register definition
1805 * (usually only necessary to work around guest bugs).
1807 s
->base
.is_jmp
= DISAS_UPDATE
;
1812 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1813 * +---------------------+---+-----+-----+-------+-------+-----+------+
1814 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1815 * +---------------------+---+-----+-----+-------+-------+-----+------+
1817 static void disas_system(DisasContext
*s
, uint32_t insn
)
1819 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1820 l
= extract32(insn
, 21, 1);
1821 op0
= extract32(insn
, 19, 2);
1822 op1
= extract32(insn
, 16, 3);
1823 crn
= extract32(insn
, 12, 4);
1824 crm
= extract32(insn
, 8, 4);
1825 op2
= extract32(insn
, 5, 3);
1826 rt
= extract32(insn
, 0, 5);
1829 if (l
|| rt
!= 31) {
1830 unallocated_encoding(s
);
1834 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1835 handle_hint(s
, insn
, op1
, op2
, crm
);
1837 case 3: /* CLREX, DSB, DMB, ISB */
1838 handle_sync(s
, insn
, op1
, op2
, crm
);
1840 case 4: /* MSR (immediate) */
1841 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1844 unallocated_encoding(s
);
1849 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1852 /* Exception generation
1854 * 31 24 23 21 20 5 4 2 1 0
1855 * +-----------------+-----+------------------------+-----+----+
1856 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1857 * +-----------------------+------------------------+----------+
1859 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1861 int opc
= extract32(insn
, 21, 3);
1862 int op2_ll
= extract32(insn
, 0, 5);
1863 int imm16
= extract32(insn
, 5, 16);
1868 /* For SVC, HVC and SMC we advance the single-step state
1869 * machine before taking the exception. This is architecturally
1870 * mandated, to ensure that single-stepping a system call
1871 * instruction works properly.
1876 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1877 default_exception_el(s
));
1880 if (s
->current_el
== 0) {
1881 unallocated_encoding(s
);
1884 /* The pre HVC helper handles cases when HVC gets trapped
1885 * as an undefined insn by runtime configuration.
1887 gen_a64_set_pc_im(s
->pc
- 4);
1888 gen_helper_pre_hvc(cpu_env
);
1890 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1893 if (s
->current_el
== 0) {
1894 unallocated_encoding(s
);
1897 gen_a64_set_pc_im(s
->pc
- 4);
1898 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1899 gen_helper_pre_smc(cpu_env
, tmp
);
1900 tcg_temp_free_i32(tmp
);
1902 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1905 unallocated_encoding(s
);
1911 unallocated_encoding(s
);
1915 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1919 unallocated_encoding(s
);
1922 /* HLT. This has two purposes.
1923 * Architecturally, it is an external halting debug instruction.
1924 * Since QEMU doesn't implement external debug, we treat this as
1925 * it is required for halting debug disabled: it will UNDEF.
1926 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1928 if (semihosting_enabled() && imm16
== 0xf000) {
1929 #ifndef CONFIG_USER_ONLY
1930 /* In system mode, don't allow userspace access to semihosting,
1931 * to provide some semblance of security (and for consistency
1932 * with our 32-bit semihosting).
1934 if (s
->current_el
== 0) {
1935 unsupported_encoding(s
, insn
);
1939 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1941 unsupported_encoding(s
, insn
);
1945 if (op2_ll
< 1 || op2_ll
> 3) {
1946 unallocated_encoding(s
);
1949 /* DCPS1, DCPS2, DCPS3 */
1950 unsupported_encoding(s
, insn
);
1953 unallocated_encoding(s
);
1958 /* Unconditional branch (register)
1959 * 31 25 24 21 20 16 15 10 9 5 4 0
1960 * +---------------+-------+-------+-------+------+-------+
1961 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1962 * +---------------+-------+-------+-------+------+-------+
1964 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1966 unsigned int opc
, op2
, op3
, rn
, op4
;
1967 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
1971 opc
= extract32(insn
, 21, 4);
1972 op2
= extract32(insn
, 16, 5);
1973 op3
= extract32(insn
, 10, 6);
1974 rn
= extract32(insn
, 5, 5);
1975 op4
= extract32(insn
, 0, 5);
1978 goto do_unallocated
;
1990 goto do_unallocated
;
1992 dst
= cpu_reg(s
, rn
);
1997 if (!dc_isar_feature(aa64_pauth
, s
)) {
1998 goto do_unallocated
;
2002 if (rn
!= 0x1f || op4
!= 0x1f) {
2003 goto do_unallocated
;
2006 modifier
= cpu_X
[31];
2008 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2010 goto do_unallocated
;
2012 modifier
= new_tmp_a64_zero(s
);
2014 if (s
->pauth_active
) {
2015 dst
= new_tmp_a64(s
);
2017 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2019 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2022 dst
= cpu_reg(s
, rn
);
2027 goto do_unallocated
;
2029 gen_a64_set_pc(s
, dst
);
2030 /* BLR also needs to load return address */
2032 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2038 if (!dc_isar_feature(aa64_pauth
, s
)) {
2039 goto do_unallocated
;
2041 if ((op3
& ~1) != 2) {
2042 goto do_unallocated
;
2044 btype_mod
= opc
& 1;
2045 if (s
->pauth_active
) {
2046 dst
= new_tmp_a64(s
);
2047 modifier
= cpu_reg_sp(s
, op4
);
2049 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2051 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2054 dst
= cpu_reg(s
, rn
);
2056 gen_a64_set_pc(s
, dst
);
2057 /* BLRAA also needs to load return address */
2059 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2064 if (s
->current_el
== 0) {
2065 goto do_unallocated
;
2070 goto do_unallocated
;
2072 dst
= tcg_temp_new_i64();
2073 tcg_gen_ld_i64(dst
, cpu_env
,
2074 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2077 case 2: /* ERETAA */
2078 case 3: /* ERETAB */
2079 if (!dc_isar_feature(aa64_pauth
, s
)) {
2080 goto do_unallocated
;
2082 if (rn
!= 0x1f || op4
!= 0x1f) {
2083 goto do_unallocated
;
2085 dst
= tcg_temp_new_i64();
2086 tcg_gen_ld_i64(dst
, cpu_env
,
2087 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2088 if (s
->pauth_active
) {
2089 modifier
= cpu_X
[31];
2091 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2093 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2099 goto do_unallocated
;
2101 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2105 gen_helper_exception_return(cpu_env
, dst
);
2106 tcg_temp_free_i64(dst
);
2107 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2110 /* Must exit loop to check un-masked IRQs */
2111 s
->base
.is_jmp
= DISAS_EXIT
;
2115 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2116 goto do_unallocated
;
2118 unsupported_encoding(s
, insn
);
2124 unallocated_encoding(s
);
2128 switch (btype_mod
) {
2130 if (dc_isar_feature(aa64_bti
, s
)) {
2131 /* BR to {x16,x17} or !guard -> 1, else 3. */
2132 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2137 if (dc_isar_feature(aa64_bti
, s
)) {
2138 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2143 default: /* RET or none of the above. */
2144 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2148 s
->base
.is_jmp
= DISAS_JUMP
;
2151 /* Branches, exception generating and system instructions */
2152 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2154 switch (extract32(insn
, 25, 7)) {
2155 case 0x0a: case 0x0b:
2156 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2157 disas_uncond_b_imm(s
, insn
);
2159 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2160 disas_comp_b_imm(s
, insn
);
2162 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2163 disas_test_b_imm(s
, insn
);
2165 case 0x2a: /* Conditional branch (immediate) */
2166 disas_cond_b_imm(s
, insn
);
2168 case 0x6a: /* Exception generation / System */
2169 if (insn
& (1 << 24)) {
2170 if (extract32(insn
, 22, 2) == 0) {
2171 disas_system(s
, insn
);
2173 unallocated_encoding(s
);
2179 case 0x6b: /* Unconditional branch (register) */
2180 disas_uncond_b_reg(s
, insn
);
2183 unallocated_encoding(s
);
2189 * Load/Store exclusive instructions are implemented by remembering
2190 * the value/address loaded, and seeing if these are the same
2191 * when the store is performed. This is not actually the architecturally
2192 * mandated semantics, but it works for typical guest code sequences
2193 * and avoids having to monitor regular stores.
2195 * The store exclusive uses the atomic cmpxchg primitives to avoid
2196 * races in multi-threaded linux-user and when MTTCG softmmu is
2199 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2200 TCGv_i64 addr
, int size
, bool is_pair
)
2202 int idx
= get_mem_index(s
);
2203 TCGMemOp memop
= s
->be_data
;
2205 g_assert(size
<= 3);
2207 g_assert(size
>= 2);
2209 /* The pair must be single-copy atomic for the doubleword. */
2210 memop
|= MO_64
| MO_ALIGN
;
2211 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2212 if (s
->be_data
== MO_LE
) {
2213 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2214 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2216 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2217 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2220 /* The pair must be single-copy atomic for *each* doubleword, not
2221 the entire quadword, however it must be quadword aligned. */
2223 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2224 memop
| MO_ALIGN_16
);
2226 TCGv_i64 addr2
= tcg_temp_new_i64();
2227 tcg_gen_addi_i64(addr2
, addr
, 8);
2228 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2229 tcg_temp_free_i64(addr2
);
2231 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2232 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2235 memop
|= size
| MO_ALIGN
;
2236 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2237 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2239 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2242 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2243 TCGv_i64 addr
, int size
, int is_pair
)
2245 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2246 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2249 * [addr + datasize] = {Rt2};
2255 * env->exclusive_addr = -1;
2257 TCGLabel
*fail_label
= gen_new_label();
2258 TCGLabel
*done_label
= gen_new_label();
2261 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2263 tmp
= tcg_temp_new_i64();
2266 if (s
->be_data
== MO_LE
) {
2267 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2269 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2271 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2272 cpu_exclusive_val
, tmp
,
2274 MO_64
| MO_ALIGN
| s
->be_data
);
2275 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2276 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2277 if (!HAVE_CMPXCHG128
) {
2278 gen_helper_exit_atomic(cpu_env
);
2279 s
->base
.is_jmp
= DISAS_NORETURN
;
2280 } else if (s
->be_data
== MO_LE
) {
2281 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2286 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2291 } else if (s
->be_data
== MO_LE
) {
2292 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2293 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2295 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2296 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2299 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2300 cpu_reg(s
, rt
), get_mem_index(s
),
2301 size
| MO_ALIGN
| s
->be_data
);
2302 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2304 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2305 tcg_temp_free_i64(tmp
);
2306 tcg_gen_br(done_label
);
2308 gen_set_label(fail_label
);
2309 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2310 gen_set_label(done_label
);
2311 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2314 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2317 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2318 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2319 int memidx
= get_mem_index(s
);
2320 TCGv_i64 clean_addr
;
2323 gen_check_sp_alignment(s
);
2325 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2326 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2327 size
| MO_ALIGN
| s
->be_data
);
2330 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2333 TCGv_i64 s1
= cpu_reg(s
, rs
);
2334 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2335 TCGv_i64 t1
= cpu_reg(s
, rt
);
2336 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2337 TCGv_i64 clean_addr
;
2338 int memidx
= get_mem_index(s
);
2341 gen_check_sp_alignment(s
);
2343 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2346 TCGv_i64 cmp
= tcg_temp_new_i64();
2347 TCGv_i64 val
= tcg_temp_new_i64();
2349 if (s
->be_data
== MO_LE
) {
2350 tcg_gen_concat32_i64(val
, t1
, t2
);
2351 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2353 tcg_gen_concat32_i64(val
, t2
, t1
);
2354 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2357 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2358 MO_64
| MO_ALIGN
| s
->be_data
);
2359 tcg_temp_free_i64(val
);
2361 if (s
->be_data
== MO_LE
) {
2362 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2364 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2366 tcg_temp_free_i64(cmp
);
2367 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2368 if (HAVE_CMPXCHG128
) {
2369 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2370 if (s
->be_data
== MO_LE
) {
2371 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2372 clean_addr
, t1
, t2
);
2374 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2375 clean_addr
, t1
, t2
);
2377 tcg_temp_free_i32(tcg_rs
);
2379 gen_helper_exit_atomic(cpu_env
);
2380 s
->base
.is_jmp
= DISAS_NORETURN
;
2383 TCGv_i64 d1
= tcg_temp_new_i64();
2384 TCGv_i64 d2
= tcg_temp_new_i64();
2385 TCGv_i64 a2
= tcg_temp_new_i64();
2386 TCGv_i64 c1
= tcg_temp_new_i64();
2387 TCGv_i64 c2
= tcg_temp_new_i64();
2388 TCGv_i64 zero
= tcg_const_i64(0);
2390 /* Load the two words, in memory order. */
2391 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2392 MO_64
| MO_ALIGN_16
| s
->be_data
);
2393 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2394 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2396 /* Compare the two words, also in memory order. */
2397 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2398 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2399 tcg_gen_and_i64(c2
, c2
, c1
);
2401 /* If compare equal, write back new data, else write back old data. */
2402 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2403 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2404 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2405 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2406 tcg_temp_free_i64(a2
);
2407 tcg_temp_free_i64(c1
);
2408 tcg_temp_free_i64(c2
);
2409 tcg_temp_free_i64(zero
);
2411 /* Write back the data from memory to Rs. */
2412 tcg_gen_mov_i64(s1
, d1
);
2413 tcg_gen_mov_i64(s2
, d2
);
2414 tcg_temp_free_i64(d1
);
2415 tcg_temp_free_i64(d2
);
2419 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2420 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2422 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2424 int opc0
= extract32(opc
, 0, 1);
2428 regsize
= opc0
? 32 : 64;
2430 regsize
= size
== 3 ? 64 : 32;
2432 return regsize
== 64;
2435 /* Load/store exclusive
2437 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2438 * +-----+-------------+----+---+----+------+----+-------+------+------+
2439 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2440 * +-----+-------------+----+---+----+------+----+-------+------+------+
2442 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2443 * L: 0 -> store, 1 -> load
2444 * o2: 0 -> exclusive, 1 -> not
2445 * o1: 0 -> single register, 1 -> register pair
2446 * o0: 1 -> load-acquire/store-release, 0 -> not
2448 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2450 int rt
= extract32(insn
, 0, 5);
2451 int rn
= extract32(insn
, 5, 5);
2452 int rt2
= extract32(insn
, 10, 5);
2453 int rs
= extract32(insn
, 16, 5);
2454 int is_lasr
= extract32(insn
, 15, 1);
2455 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2456 int size
= extract32(insn
, 30, 2);
2457 TCGv_i64 clean_addr
;
2459 switch (o2_L_o1_o0
) {
2460 case 0x0: /* STXR */
2461 case 0x1: /* STLXR */
2463 gen_check_sp_alignment(s
);
2466 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2468 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2469 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2472 case 0x4: /* LDXR */
2473 case 0x5: /* LDAXR */
2475 gen_check_sp_alignment(s
);
2477 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2479 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2481 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2485 case 0x8: /* STLLR */
2486 if (!dc_isar_feature(aa64_lor
, s
)) {
2489 /* StoreLORelease is the same as Store-Release for QEMU. */
2491 case 0x9: /* STLR */
2492 /* Generate ISS for non-exclusive accesses including LASR. */
2494 gen_check_sp_alignment(s
);
2496 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2497 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2498 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2499 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2502 case 0xc: /* LDLAR */
2503 if (!dc_isar_feature(aa64_lor
, s
)) {
2506 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2508 case 0xd: /* LDAR */
2509 /* Generate ISS for non-exclusive accesses including LASR. */
2511 gen_check_sp_alignment(s
);
2513 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2514 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2515 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2516 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2519 case 0x2: case 0x3: /* CASP / STXP */
2520 if (size
& 2) { /* STXP / STLXP */
2522 gen_check_sp_alignment(s
);
2525 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2527 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2528 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2532 && ((rt
| rs
) & 1) == 0
2533 && dc_isar_feature(aa64_atomics
, s
)) {
2535 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2540 case 0x6: case 0x7: /* CASPA / LDXP */
2541 if (size
& 2) { /* LDXP / LDAXP */
2543 gen_check_sp_alignment(s
);
2545 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2547 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2549 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2554 && ((rt
| rs
) & 1) == 0
2555 && dc_isar_feature(aa64_atomics
, s
)) {
2556 /* CASPA / CASPAL */
2557 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2563 case 0xb: /* CASL */
2564 case 0xe: /* CASA */
2565 case 0xf: /* CASAL */
2566 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2567 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2572 unallocated_encoding(s
);
2576 * Load register (literal)
2578 * 31 30 29 27 26 25 24 23 5 4 0
2579 * +-----+-------+---+-----+-------------------+-------+
2580 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2581 * +-----+-------+---+-----+-------------------+-------+
2583 * V: 1 -> vector (simd/fp)
2584 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2585 * 10-> 32 bit signed, 11 -> prefetch
2586 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2588 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2590 int rt
= extract32(insn
, 0, 5);
2591 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2592 bool is_vector
= extract32(insn
, 26, 1);
2593 int opc
= extract32(insn
, 30, 2);
2594 bool is_signed
= false;
2596 TCGv_i64 tcg_rt
, clean_addr
;
2600 unallocated_encoding(s
);
2604 if (!fp_access_check(s
)) {
2609 /* PRFM (literal) : prefetch */
2612 size
= 2 + extract32(opc
, 0, 1);
2613 is_signed
= extract32(opc
, 1, 1);
2616 tcg_rt
= cpu_reg(s
, rt
);
2618 clean_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2620 do_fp_ld(s
, rt
, clean_addr
, size
);
2622 /* Only unsigned 32bit loads target 32bit registers. */
2623 bool iss_sf
= opc
!= 0;
2625 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2626 true, rt
, iss_sf
, false);
2628 tcg_temp_free_i64(clean_addr
);
2632 * LDNP (Load Pair - non-temporal hint)
2633 * LDP (Load Pair - non vector)
2634 * LDPSW (Load Pair Signed Word - non vector)
2635 * STNP (Store Pair - non-temporal hint)
2636 * STP (Store Pair - non vector)
2637 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2638 * LDP (Load Pair of SIMD&FP)
2639 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2640 * STP (Store Pair of SIMD&FP)
2642 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2643 * +-----+-------+---+---+-------+---+-----------------------------+
2644 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2645 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2647 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2649 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2650 * V: 0 -> GPR, 1 -> Vector
2651 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2652 * 10 -> signed offset, 11 -> pre-index
2653 * L: 0 -> Store 1 -> Load
2655 * Rt, Rt2 = GPR or SIMD registers to be stored
2656 * Rn = general purpose register containing address
2657 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2659 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2661 int rt
= extract32(insn
, 0, 5);
2662 int rn
= extract32(insn
, 5, 5);
2663 int rt2
= extract32(insn
, 10, 5);
2664 uint64_t offset
= sextract64(insn
, 15, 7);
2665 int index
= extract32(insn
, 23, 2);
2666 bool is_vector
= extract32(insn
, 26, 1);
2667 bool is_load
= extract32(insn
, 22, 1);
2668 int opc
= extract32(insn
, 30, 2);
2670 bool is_signed
= false;
2671 bool postindex
= false;
2674 TCGv_i64 clean_addr
, dirty_addr
;
2679 unallocated_encoding(s
);
2686 size
= 2 + extract32(opc
, 1, 1);
2687 is_signed
= extract32(opc
, 0, 1);
2688 if (!is_load
&& is_signed
) {
2689 unallocated_encoding(s
);
2695 case 1: /* post-index */
2700 /* signed offset with "non-temporal" hint. Since we don't emulate
2701 * caches we don't care about hints to the cache system about
2702 * data access patterns, and handle this identically to plain
2706 /* There is no non-temporal-hint version of LDPSW */
2707 unallocated_encoding(s
);
2712 case 2: /* signed offset, rn not updated */
2715 case 3: /* pre-index */
2721 if (is_vector
&& !fp_access_check(s
)) {
2728 gen_check_sp_alignment(s
);
2731 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2733 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2735 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2739 do_fp_ld(s
, rt
, clean_addr
, size
);
2741 do_fp_st(s
, rt
, clean_addr
, size
);
2743 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2745 do_fp_ld(s
, rt2
, clean_addr
, size
);
2747 do_fp_st(s
, rt2
, clean_addr
, size
);
2750 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2751 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2754 TCGv_i64 tmp
= tcg_temp_new_i64();
2756 /* Do not modify tcg_rt before recognizing any exception
2757 * from the second load.
2759 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2760 false, 0, false, false);
2761 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2762 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2763 false, 0, false, false);
2765 tcg_gen_mov_i64(tcg_rt
, tmp
);
2766 tcg_temp_free_i64(tmp
);
2768 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2769 false, 0, false, false);
2770 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2771 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2772 false, 0, false, false);
2778 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2780 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2785 * Load/store (immediate post-indexed)
2786 * Load/store (immediate pre-indexed)
2787 * Load/store (unscaled immediate)
2789 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2790 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2791 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2792 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2794 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2796 * V = 0 -> non-vector
2797 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2798 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2800 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2806 int rn
= extract32(insn
, 5, 5);
2807 int imm9
= sextract32(insn
, 12, 9);
2808 int idx
= extract32(insn
, 10, 2);
2809 bool is_signed
= false;
2810 bool is_store
= false;
2811 bool is_extended
= false;
2812 bool is_unpriv
= (idx
== 2);
2813 bool iss_valid
= !is_vector
;
2817 TCGv_i64 clean_addr
, dirty_addr
;
2820 size
|= (opc
& 2) << 1;
2821 if (size
> 4 || is_unpriv
) {
2822 unallocated_encoding(s
);
2825 is_store
= ((opc
& 1) == 0);
2826 if (!fp_access_check(s
)) {
2830 if (size
== 3 && opc
== 2) {
2831 /* PRFM - prefetch */
2833 unallocated_encoding(s
);
2838 if (opc
== 3 && size
> 1) {
2839 unallocated_encoding(s
);
2842 is_store
= (opc
== 0);
2843 is_signed
= extract32(opc
, 1, 1);
2844 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2862 g_assert_not_reached();
2866 gen_check_sp_alignment(s
);
2869 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2871 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2873 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2877 do_fp_st(s
, rt
, clean_addr
, size
);
2879 do_fp_ld(s
, rt
, clean_addr
, size
);
2882 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2883 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2884 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2887 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2888 iss_valid
, rt
, iss_sf
, false);
2890 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2891 is_signed
, is_extended
, memidx
,
2892 iss_valid
, rt
, iss_sf
, false);
2897 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2899 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2901 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2906 * Load/store (register offset)
2908 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2909 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2910 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2911 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2914 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2915 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2917 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2918 * opc<0>: 0 -> store, 1 -> load
2919 * V: 1 -> vector/simd
2920 * opt: extend encoding (see DecodeRegExtend)
2921 * S: if S=1 then scale (essentially index by sizeof(size))
2922 * Rt: register to transfer into/out of
2923 * Rn: address register or SP for base
2924 * Rm: offset register or ZR for offset
2926 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2932 int rn
= extract32(insn
, 5, 5);
2933 int shift
= extract32(insn
, 12, 1);
2934 int rm
= extract32(insn
, 16, 5);
2935 int opt
= extract32(insn
, 13, 3);
2936 bool is_signed
= false;
2937 bool is_store
= false;
2938 bool is_extended
= false;
2940 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2942 if (extract32(opt
, 1, 1) == 0) {
2943 unallocated_encoding(s
);
2948 size
|= (opc
& 2) << 1;
2950 unallocated_encoding(s
);
2953 is_store
= !extract32(opc
, 0, 1);
2954 if (!fp_access_check(s
)) {
2958 if (size
== 3 && opc
== 2) {
2959 /* PRFM - prefetch */
2962 if (opc
== 3 && size
> 1) {
2963 unallocated_encoding(s
);
2966 is_store
= (opc
== 0);
2967 is_signed
= extract32(opc
, 1, 1);
2968 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2972 gen_check_sp_alignment(s
);
2974 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2976 tcg_rm
= read_cpu_reg(s
, rm
, 1);
2977 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
2979 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
2980 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2984 do_fp_st(s
, rt
, clean_addr
, size
);
2986 do_fp_ld(s
, rt
, clean_addr
, size
);
2989 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2990 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2992 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2993 true, rt
, iss_sf
, false);
2995 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
2996 is_signed
, is_extended
,
2997 true, rt
, iss_sf
, false);
3003 * Load/store (unsigned immediate)
3005 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3006 * +----+-------+---+-----+-----+------------+-------+------+
3007 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3008 * +----+-------+---+-----+-----+------------+-------+------+
3011 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3012 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3014 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3015 * opc<0>: 0 -> store, 1 -> load
3016 * Rn: base address register (inc SP)
3017 * Rt: target register
3019 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3025 int rn
= extract32(insn
, 5, 5);
3026 unsigned int imm12
= extract32(insn
, 10, 12);
3027 unsigned int offset
;
3029 TCGv_i64 clean_addr
, dirty_addr
;
3032 bool is_signed
= false;
3033 bool is_extended
= false;
3036 size
|= (opc
& 2) << 1;
3038 unallocated_encoding(s
);
3041 is_store
= !extract32(opc
, 0, 1);
3042 if (!fp_access_check(s
)) {
3046 if (size
== 3 && opc
== 2) {
3047 /* PRFM - prefetch */
3050 if (opc
== 3 && size
> 1) {
3051 unallocated_encoding(s
);
3054 is_store
= (opc
== 0);
3055 is_signed
= extract32(opc
, 1, 1);
3056 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3060 gen_check_sp_alignment(s
);
3062 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3063 offset
= imm12
<< size
;
3064 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3065 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3069 do_fp_st(s
, rt
, clean_addr
, size
);
3071 do_fp_ld(s
, rt
, clean_addr
, size
);
3074 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3075 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3077 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3078 true, rt
, iss_sf
, false);
3080 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3081 true, rt
, iss_sf
, false);
3086 /* Atomic memory operations
3088 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3089 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3090 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3091 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3093 * Rt: the result register
3094 * Rn: base address or SP
3095 * Rs: the source register for the operation
3096 * V: vector flag (always 0 as of v8.3)
3100 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3101 int size
, int rt
, bool is_vector
)
3103 int rs
= extract32(insn
, 16, 5);
3104 int rn
= extract32(insn
, 5, 5);
3105 int o3_opc
= extract32(insn
, 12, 4);
3106 TCGv_i64 tcg_rs
, clean_addr
;
3107 AtomicThreeOpFn
*fn
;
3109 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3110 unallocated_encoding(s
);
3114 case 000: /* LDADD */
3115 fn
= tcg_gen_atomic_fetch_add_i64
;
3117 case 001: /* LDCLR */
3118 fn
= tcg_gen_atomic_fetch_and_i64
;
3120 case 002: /* LDEOR */
3121 fn
= tcg_gen_atomic_fetch_xor_i64
;
3123 case 003: /* LDSET */
3124 fn
= tcg_gen_atomic_fetch_or_i64
;
3126 case 004: /* LDSMAX */
3127 fn
= tcg_gen_atomic_fetch_smax_i64
;
3129 case 005: /* LDSMIN */
3130 fn
= tcg_gen_atomic_fetch_smin_i64
;
3132 case 006: /* LDUMAX */
3133 fn
= tcg_gen_atomic_fetch_umax_i64
;
3135 case 007: /* LDUMIN */
3136 fn
= tcg_gen_atomic_fetch_umin_i64
;
3139 fn
= tcg_gen_atomic_xchg_i64
;
3142 unallocated_encoding(s
);
3147 gen_check_sp_alignment(s
);
3149 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3150 tcg_rs
= read_cpu_reg(s
, rs
, true);
3152 if (o3_opc
== 1) { /* LDCLR */
3153 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3156 /* The tcg atomic primitives are all full barriers. Therefore we
3157 * can ignore the Acquire and Release bits of this instruction.
3159 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3160 s
->be_data
| size
| MO_ALIGN
);
3164 * PAC memory operations
3166 * 31 30 27 26 24 22 21 12 11 10 5 0
3167 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3168 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3169 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3171 * Rt: the result register
3172 * Rn: base address or SP
3173 * V: vector flag (always 0 as of v8.3)
3174 * M: clear for key DA, set for key DB
3175 * W: pre-indexing flag
3178 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3179 int size
, int rt
, bool is_vector
)
3181 int rn
= extract32(insn
, 5, 5);
3182 bool is_wback
= extract32(insn
, 11, 1);
3183 bool use_key_a
= !extract32(insn
, 23, 1);
3185 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3187 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3188 unallocated_encoding(s
);
3193 gen_check_sp_alignment(s
);
3195 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3197 if (s
->pauth_active
) {
3199 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3201 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3205 /* Form the 10-bit signed, scaled offset. */
3206 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3207 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3208 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3210 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3211 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3213 tcg_rt
= cpu_reg(s
, rt
);
3214 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3215 /* extend */ false, /* iss_valid */ !is_wback
,
3216 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3219 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3223 /* Load/store register (all forms) */
3224 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3226 int rt
= extract32(insn
, 0, 5);
3227 int opc
= extract32(insn
, 22, 2);
3228 bool is_vector
= extract32(insn
, 26, 1);
3229 int size
= extract32(insn
, 30, 2);
3231 switch (extract32(insn
, 24, 2)) {
3233 if (extract32(insn
, 21, 1) == 0) {
3234 /* Load/store register (unscaled immediate)
3235 * Load/store immediate pre/post-indexed
3236 * Load/store register unprivileged
3238 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3241 switch (extract32(insn
, 10, 2)) {
3243 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3246 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3249 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3254 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3257 unallocated_encoding(s
);
3260 /* AdvSIMD load/store multiple structures
3262 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3263 * +---+---+---------------+---+-------------+--------+------+------+------+
3264 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3265 * +---+---+---------------+---+-------------+--------+------+------+------+
3267 * AdvSIMD load/store multiple structures (post-indexed)
3269 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3270 * +---+---+---------------+---+---+---------+--------+------+------+------+
3271 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3272 * +---+---+---------------+---+---+---------+--------+------+------+------+
3274 * Rt: first (or only) SIMD&FP register to be transferred
3275 * Rn: base address or SP
3276 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3278 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3280 int rt
= extract32(insn
, 0, 5);
3281 int rn
= extract32(insn
, 5, 5);
3282 int rm
= extract32(insn
, 16, 5);
3283 int size
= extract32(insn
, 10, 2);
3284 int opcode
= extract32(insn
, 12, 4);
3285 bool is_store
= !extract32(insn
, 22, 1);
3286 bool is_postidx
= extract32(insn
, 23, 1);
3287 bool is_q
= extract32(insn
, 30, 1);
3288 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3289 TCGMemOp endian
= s
->be_data
;
3291 int ebytes
; /* bytes per element */
3292 int elements
; /* elements per vector */
3293 int rpt
; /* num iterations */
3294 int selem
; /* structure elements */
3297 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3298 unallocated_encoding(s
);
3302 if (!is_postidx
&& rm
!= 0) {
3303 unallocated_encoding(s
);
3307 /* From the shared decode logic */
3338 unallocated_encoding(s
);
3342 if (size
== 3 && !is_q
&& selem
!= 1) {
3344 unallocated_encoding(s
);
3348 if (!fp_access_check(s
)) {
3353 gen_check_sp_alignment(s
);
3356 /* For our purposes, bytes are always little-endian. */
3361 /* Consecutive little-endian elements from a single register
3362 * can be promoted to a larger little-endian operation.
3364 if (selem
== 1 && endian
== MO_LE
) {
3368 elements
= (is_q
? 16 : 8) / ebytes
;
3370 tcg_rn
= cpu_reg_sp(s
, rn
);
3371 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3372 tcg_ebytes
= tcg_const_i64(ebytes
);
3374 for (r
= 0; r
< rpt
; r
++) {
3376 for (e
= 0; e
< elements
; e
++) {
3378 for (xs
= 0; xs
< selem
; xs
++) {
3379 int tt
= (rt
+ r
+ xs
) % 32;
3381 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3383 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3385 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3389 tcg_temp_free_i64(tcg_ebytes
);
3392 /* For non-quad operations, setting a slice of the low
3393 * 64 bits of the register clears the high 64 bits (in
3394 * the ARM ARM pseudocode this is implicit in the fact
3395 * that 'rval' is a 64 bit wide variable).
3396 * For quad operations, we might still need to zero the
3399 for (r
= 0; r
< rpt
* selem
; r
++) {
3400 int tt
= (rt
+ r
) % 32;
3401 clear_vec_high(s
, is_q
, tt
);
3407 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3409 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3414 /* AdvSIMD load/store single structure
3416 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3417 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3418 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3419 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3421 * AdvSIMD load/store single structure (post-indexed)
3423 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3424 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3425 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3426 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3428 * Rt: first (or only) SIMD&FP register to be transferred
3429 * Rn: base address or SP
3430 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3431 * index = encoded in Q:S:size dependent on size
3433 * lane_size = encoded in R, opc
3434 * transfer width = encoded in opc, S, size
3436 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3438 int rt
= extract32(insn
, 0, 5);
3439 int rn
= extract32(insn
, 5, 5);
3440 int rm
= extract32(insn
, 16, 5);
3441 int size
= extract32(insn
, 10, 2);
3442 int S
= extract32(insn
, 12, 1);
3443 int opc
= extract32(insn
, 13, 3);
3444 int R
= extract32(insn
, 21, 1);
3445 int is_load
= extract32(insn
, 22, 1);
3446 int is_postidx
= extract32(insn
, 23, 1);
3447 int is_q
= extract32(insn
, 30, 1);
3449 int scale
= extract32(opc
, 1, 2);
3450 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3451 bool replicate
= false;
3452 int index
= is_q
<< 3 | S
<< 2 | size
;
3454 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3456 if (extract32(insn
, 31, 1)) {
3457 unallocated_encoding(s
);
3460 if (!is_postidx
&& rm
!= 0) {
3461 unallocated_encoding(s
);
3467 if (!is_load
|| S
) {
3468 unallocated_encoding(s
);
3477 if (extract32(size
, 0, 1)) {
3478 unallocated_encoding(s
);
3484 if (extract32(size
, 1, 1)) {
3485 unallocated_encoding(s
);
3488 if (!extract32(size
, 0, 1)) {
3492 unallocated_encoding(s
);
3500 g_assert_not_reached();
3503 if (!fp_access_check(s
)) {
3507 ebytes
= 1 << scale
;
3510 gen_check_sp_alignment(s
);
3513 tcg_rn
= cpu_reg_sp(s
, rn
);
3514 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3515 tcg_ebytes
= tcg_const_i64(ebytes
);
3517 for (xs
= 0; xs
< selem
; xs
++) {
3519 /* Load and replicate to all elements */
3520 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3522 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3523 get_mem_index(s
), s
->be_data
+ scale
);
3524 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3525 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3527 tcg_temp_free_i64(tcg_tmp
);
3529 /* Load/store one element per register */
3531 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3533 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3536 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3539 tcg_temp_free_i64(tcg_ebytes
);
3543 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3545 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3550 /* Loads and stores */
3551 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3553 switch (extract32(insn
, 24, 6)) {
3554 case 0x08: /* Load/store exclusive */
3555 disas_ldst_excl(s
, insn
);
3557 case 0x18: case 0x1c: /* Load register (literal) */
3558 disas_ld_lit(s
, insn
);
3560 case 0x28: case 0x29:
3561 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3562 disas_ldst_pair(s
, insn
);
3564 case 0x38: case 0x39:
3565 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3566 disas_ldst_reg(s
, insn
);
3568 case 0x0c: /* AdvSIMD load/store multiple structures */
3569 disas_ldst_multiple_struct(s
, insn
);
3571 case 0x0d: /* AdvSIMD load/store single structure */
3572 disas_ldst_single_struct(s
, insn
);
3575 unallocated_encoding(s
);
3580 /* PC-rel. addressing
3581 * 31 30 29 28 24 23 5 4 0
3582 * +----+-------+-----------+-------------------+------+
3583 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3584 * +----+-------+-----------+-------------------+------+
3586 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3588 unsigned int page
, rd
;
3592 page
= extract32(insn
, 31, 1);
3593 /* SignExtend(immhi:immlo) -> offset */
3594 offset
= sextract64(insn
, 5, 19);
3595 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3596 rd
= extract32(insn
, 0, 5);
3600 /* ADRP (page based) */
3605 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3609 * Add/subtract (immediate)
3611 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3612 * +--+--+--+-----------+-----+-------------+-----+-----+
3613 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3614 * +--+--+--+-----------+-----+-------------+-----+-----+
3616 * sf: 0 -> 32bit, 1 -> 64bit
3617 * op: 0 -> add , 1 -> sub
3619 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3621 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3623 int rd
= extract32(insn
, 0, 5);
3624 int rn
= extract32(insn
, 5, 5);
3625 uint64_t imm
= extract32(insn
, 10, 12);
3626 int shift
= extract32(insn
, 22, 2);
3627 bool setflags
= extract32(insn
, 29, 1);
3628 bool sub_op
= extract32(insn
, 30, 1);
3629 bool is_64bit
= extract32(insn
, 31, 1);
3631 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3632 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3633 TCGv_i64 tcg_result
;
3642 unallocated_encoding(s
);
3646 tcg_result
= tcg_temp_new_i64();
3649 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3651 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3654 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3656 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3658 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3660 tcg_temp_free_i64(tcg_imm
);
3664 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3666 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3669 tcg_temp_free_i64(tcg_result
);
3672 /* The input should be a value in the bottom e bits (with higher
3673 * bits zero); returns that value replicated into every element
3674 * of size e in a 64 bit integer.
3676 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3686 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3687 static inline uint64_t bitmask64(unsigned int length
)
3689 assert(length
> 0 && length
<= 64);
3690 return ~0ULL >> (64 - length
);
3693 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3694 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3695 * value (ie should cause a guest UNDEF exception), and true if they are
3696 * valid, in which case the decoded bit pattern is written to result.
3698 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3699 unsigned int imms
, unsigned int immr
)
3702 unsigned e
, levels
, s
, r
;
3705 assert(immn
< 2 && imms
< 64 && immr
< 64);
3707 /* The bit patterns we create here are 64 bit patterns which
3708 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3709 * 64 bits each. Each element contains the same value: a run
3710 * of between 1 and e-1 non-zero bits, rotated within the
3711 * element by between 0 and e-1 bits.
3713 * The element size and run length are encoded into immn (1 bit)
3714 * and imms (6 bits) as follows:
3715 * 64 bit elements: immn = 1, imms = <length of run - 1>
3716 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3717 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3718 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3719 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3720 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3721 * Notice that immn = 0, imms = 11111x is the only combination
3722 * not covered by one of the above options; this is reserved.
3723 * Further, <length of run - 1> all-ones is a reserved pattern.
3725 * In all cases the rotation is by immr % e (and immr is 6 bits).
3728 /* First determine the element size */
3729 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3731 /* This is the immn == 0, imms == 0x11111x case */
3741 /* <length of run - 1> mustn't be all-ones. */
3745 /* Create the value of one element: s+1 set bits rotated
3746 * by r within the element (which is e bits wide)...
3748 mask
= bitmask64(s
+ 1);
3750 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3751 mask
&= bitmask64(e
);
3753 /* ...then replicate the element over the whole 64 bit value */
3754 mask
= bitfield_replicate(mask
, e
);
3759 /* Logical (immediate)
3760 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3761 * +----+-----+-------------+---+------+------+------+------+
3762 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3763 * +----+-----+-------------+---+------+------+------+------+
3765 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3767 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3768 TCGv_i64 tcg_rd
, tcg_rn
;
3770 bool is_and
= false;
3772 sf
= extract32(insn
, 31, 1);
3773 opc
= extract32(insn
, 29, 2);
3774 is_n
= extract32(insn
, 22, 1);
3775 immr
= extract32(insn
, 16, 6);
3776 imms
= extract32(insn
, 10, 6);
3777 rn
= extract32(insn
, 5, 5);
3778 rd
= extract32(insn
, 0, 5);
3781 unallocated_encoding(s
);
3785 if (opc
== 0x3) { /* ANDS */
3786 tcg_rd
= cpu_reg(s
, rd
);
3788 tcg_rd
= cpu_reg_sp(s
, rd
);
3790 tcg_rn
= cpu_reg(s
, rn
);
3792 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3793 /* some immediate field values are reserved */
3794 unallocated_encoding(s
);
3799 wmask
&= 0xffffffff;
3803 case 0x3: /* ANDS */
3805 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3809 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3812 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3815 assert(FALSE
); /* must handle all above */
3819 if (!sf
&& !is_and
) {
3820 /* zero extend final result; we know we can skip this for AND
3821 * since the immediate had the high 32 bits clear.
3823 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3826 if (opc
== 3) { /* ANDS */
3827 gen_logic_CC(sf
, tcg_rd
);
3832 * Move wide (immediate)
3834 * 31 30 29 28 23 22 21 20 5 4 0
3835 * +--+-----+-------------+-----+----------------+------+
3836 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3837 * +--+-----+-------------+-----+----------------+------+
3839 * sf: 0 -> 32 bit, 1 -> 64 bit
3840 * opc: 00 -> N, 10 -> Z, 11 -> K
3841 * hw: shift/16 (0,16, and sf only 32, 48)
3843 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3845 int rd
= extract32(insn
, 0, 5);
3846 uint64_t imm
= extract32(insn
, 5, 16);
3847 int sf
= extract32(insn
, 31, 1);
3848 int opc
= extract32(insn
, 29, 2);
3849 int pos
= extract32(insn
, 21, 2) << 4;
3850 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3853 if (!sf
&& (pos
>= 32)) {
3854 unallocated_encoding(s
);
3868 tcg_gen_movi_i64(tcg_rd
, imm
);
3871 tcg_imm
= tcg_const_i64(imm
);
3872 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3873 tcg_temp_free_i64(tcg_imm
);
3875 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3879 unallocated_encoding(s
);
3885 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3886 * +----+-----+-------------+---+------+------+------+------+
3887 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3888 * +----+-----+-------------+---+------+------+------+------+
3890 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3892 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3893 TCGv_i64 tcg_rd
, tcg_tmp
;
3895 sf
= extract32(insn
, 31, 1);
3896 opc
= extract32(insn
, 29, 2);
3897 n
= extract32(insn
, 22, 1);
3898 ri
= extract32(insn
, 16, 6);
3899 si
= extract32(insn
, 10, 6);
3900 rn
= extract32(insn
, 5, 5);
3901 rd
= extract32(insn
, 0, 5);
3902 bitsize
= sf
? 64 : 32;
3904 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3905 unallocated_encoding(s
);
3909 tcg_rd
= cpu_reg(s
, rd
);
3911 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3912 to be smaller than bitsize, we'll never reference data outside the
3913 low 32-bits anyway. */
3914 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3916 /* Recognize simple(r) extractions. */
3918 /* Wd<s-r:0> = Wn<s:r> */
3919 len
= (si
- ri
) + 1;
3920 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3921 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3923 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3924 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3927 /* opc == 1, BFXIL fall through to deposit */
3928 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
3931 /* Handle the ri > si case with a deposit
3932 * Wd<32+s-r,32-r> = Wn<s:0>
3935 pos
= (bitsize
- ri
) & (bitsize
- 1);
3938 if (opc
== 0 && len
< ri
) {
3939 /* SBFM: sign extend the destination field from len to fill
3940 the balance of the word. Let the deposit below insert all
3941 of those sign bits. */
3942 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3946 if (opc
== 1) { /* BFM, BFXIL */
3947 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3949 /* SBFM or UBFM: We start with zero, and we haven't modified
3950 any bits outside bitsize, therefore the zero-extension
3951 below is unneeded. */
3952 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3957 if (!sf
) { /* zero extend final result */
3958 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3963 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3964 * +----+------+-------------+---+----+------+--------+------+------+
3965 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3966 * +----+------+-------------+---+----+------+--------+------+------+
3968 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3970 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3972 sf
= extract32(insn
, 31, 1);
3973 n
= extract32(insn
, 22, 1);
3974 rm
= extract32(insn
, 16, 5);
3975 imm
= extract32(insn
, 10, 6);
3976 rn
= extract32(insn
, 5, 5);
3977 rd
= extract32(insn
, 0, 5);
3978 op21
= extract32(insn
, 29, 2);
3979 op0
= extract32(insn
, 21, 1);
3980 bitsize
= sf
? 64 : 32;
3982 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
3983 unallocated_encoding(s
);
3985 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
3987 tcg_rd
= cpu_reg(s
, rd
);
3989 if (unlikely(imm
== 0)) {
3990 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
3991 * so an extract from bit 0 is a special case.
3994 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
3996 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
3999 tcg_rm
= cpu_reg(s
, rm
);
4000 tcg_rn
= cpu_reg(s
, rn
);
4003 /* Specialization to ROR happens in EXTRACT2. */
4004 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4006 TCGv_i32 t0
= tcg_temp_new_i32();
4008 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4010 tcg_gen_rotri_i32(t0
, t0
, imm
);
4012 TCGv_i32 t1
= tcg_temp_new_i32();
4013 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4014 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4015 tcg_temp_free_i32(t1
);
4017 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4018 tcg_temp_free_i32(t0
);
4024 /* Data processing - immediate */
4025 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4027 switch (extract32(insn
, 23, 6)) {
4028 case 0x20: case 0x21: /* PC-rel. addressing */
4029 disas_pc_rel_adr(s
, insn
);
4031 case 0x22: case 0x23: /* Add/subtract (immediate) */
4032 disas_add_sub_imm(s
, insn
);
4034 case 0x24: /* Logical (immediate) */
4035 disas_logic_imm(s
, insn
);
4037 case 0x25: /* Move wide (immediate) */
4038 disas_movw_imm(s
, insn
);
4040 case 0x26: /* Bitfield */
4041 disas_bitfield(s
, insn
);
4043 case 0x27: /* Extract */
4044 disas_extract(s
, insn
);
4047 unallocated_encoding(s
);
4052 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4053 * Note that it is the caller's responsibility to ensure that the
4054 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4055 * mandated semantics for out of range shifts.
4057 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4058 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4060 switch (shift_type
) {
4061 case A64_SHIFT_TYPE_LSL
:
4062 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4064 case A64_SHIFT_TYPE_LSR
:
4065 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4067 case A64_SHIFT_TYPE_ASR
:
4069 tcg_gen_ext32s_i64(dst
, src
);
4071 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4073 case A64_SHIFT_TYPE_ROR
:
4075 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4078 t0
= tcg_temp_new_i32();
4079 t1
= tcg_temp_new_i32();
4080 tcg_gen_extrl_i64_i32(t0
, src
);
4081 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4082 tcg_gen_rotr_i32(t0
, t0
, t1
);
4083 tcg_gen_extu_i32_i64(dst
, t0
);
4084 tcg_temp_free_i32(t0
);
4085 tcg_temp_free_i32(t1
);
4089 assert(FALSE
); /* all shift types should be handled */
4093 if (!sf
) { /* zero extend final result */
4094 tcg_gen_ext32u_i64(dst
, dst
);
4098 /* Shift a TCGv src by immediate, put result in dst.
4099 * The shift amount must be in range (this should always be true as the
4100 * relevant instructions will UNDEF on bad shift immediates).
4102 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4103 enum a64_shift_type shift_type
, unsigned int shift_i
)
4105 assert(shift_i
< (sf
? 64 : 32));
4108 tcg_gen_mov_i64(dst
, src
);
4110 TCGv_i64 shift_const
;
4112 shift_const
= tcg_const_i64(shift_i
);
4113 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4114 tcg_temp_free_i64(shift_const
);
4118 /* Logical (shifted register)
4119 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4120 * +----+-----+-----------+-------+---+------+--------+------+------+
4121 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4122 * +----+-----+-----------+-------+---+------+--------+------+------+
4124 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4126 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4127 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4129 sf
= extract32(insn
, 31, 1);
4130 opc
= extract32(insn
, 29, 2);
4131 shift_type
= extract32(insn
, 22, 2);
4132 invert
= extract32(insn
, 21, 1);
4133 rm
= extract32(insn
, 16, 5);
4134 shift_amount
= extract32(insn
, 10, 6);
4135 rn
= extract32(insn
, 5, 5);
4136 rd
= extract32(insn
, 0, 5);
4138 if (!sf
&& (shift_amount
& (1 << 5))) {
4139 unallocated_encoding(s
);
4143 tcg_rd
= cpu_reg(s
, rd
);
4145 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4146 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4147 * register-register MOV and MVN, so it is worth special casing.
4149 tcg_rm
= cpu_reg(s
, rm
);
4151 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4153 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4157 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4159 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4165 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4168 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4171 tcg_rn
= cpu_reg(s
, rn
);
4173 switch (opc
| (invert
<< 2)) {
4176 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4179 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4182 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4186 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4189 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4192 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4200 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4204 gen_logic_CC(sf
, tcg_rd
);
4209 * Add/subtract (extended register)
4211 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4212 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4213 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4214 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4216 * sf: 0 -> 32bit, 1 -> 64bit
4217 * op: 0 -> add , 1 -> sub
4220 * option: extension type (see DecodeRegExtend)
4221 * imm3: optional shift to Rm
4223 * Rd = Rn + LSL(extend(Rm), amount)
4225 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4227 int rd
= extract32(insn
, 0, 5);
4228 int rn
= extract32(insn
, 5, 5);
4229 int imm3
= extract32(insn
, 10, 3);
4230 int option
= extract32(insn
, 13, 3);
4231 int rm
= extract32(insn
, 16, 5);
4232 int opt
= extract32(insn
, 22, 2);
4233 bool setflags
= extract32(insn
, 29, 1);
4234 bool sub_op
= extract32(insn
, 30, 1);
4235 bool sf
= extract32(insn
, 31, 1);
4237 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4239 TCGv_i64 tcg_result
;
4241 if (imm3
> 4 || opt
!= 0) {
4242 unallocated_encoding(s
);
4246 /* non-flag setting ops may use SP */
4248 tcg_rd
= cpu_reg_sp(s
, rd
);
4250 tcg_rd
= cpu_reg(s
, rd
);
4252 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4254 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4255 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4257 tcg_result
= tcg_temp_new_i64();
4261 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4263 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4267 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4269 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4274 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4276 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4279 tcg_temp_free_i64(tcg_result
);
4283 * Add/subtract (shifted register)
4285 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4286 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4287 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4288 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4290 * sf: 0 -> 32bit, 1 -> 64bit
4291 * op: 0 -> add , 1 -> sub
4293 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4294 * imm6: Shift amount to apply to Rm before the add/sub
4296 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4298 int rd
= extract32(insn
, 0, 5);
4299 int rn
= extract32(insn
, 5, 5);
4300 int imm6
= extract32(insn
, 10, 6);
4301 int rm
= extract32(insn
, 16, 5);
4302 int shift_type
= extract32(insn
, 22, 2);
4303 bool setflags
= extract32(insn
, 29, 1);
4304 bool sub_op
= extract32(insn
, 30, 1);
4305 bool sf
= extract32(insn
, 31, 1);
4307 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4308 TCGv_i64 tcg_rn
, tcg_rm
;
4309 TCGv_i64 tcg_result
;
4311 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4312 unallocated_encoding(s
);
4316 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4317 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4319 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4321 tcg_result
= tcg_temp_new_i64();
4325 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4327 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4331 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4333 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4338 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4340 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4343 tcg_temp_free_i64(tcg_result
);
4346 /* Data-processing (3 source)
4348 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4349 * +--+------+-----------+------+------+----+------+------+------+
4350 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4351 * +--+------+-----------+------+------+----+------+------+------+
4353 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4355 int rd
= extract32(insn
, 0, 5);
4356 int rn
= extract32(insn
, 5, 5);
4357 int ra
= extract32(insn
, 10, 5);
4358 int rm
= extract32(insn
, 16, 5);
4359 int op_id
= (extract32(insn
, 29, 3) << 4) |
4360 (extract32(insn
, 21, 3) << 1) |
4361 extract32(insn
, 15, 1);
4362 bool sf
= extract32(insn
, 31, 1);
4363 bool is_sub
= extract32(op_id
, 0, 1);
4364 bool is_high
= extract32(op_id
, 2, 1);
4365 bool is_signed
= false;
4370 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4372 case 0x42: /* SMADDL */
4373 case 0x43: /* SMSUBL */
4374 case 0x44: /* SMULH */
4377 case 0x0: /* MADD (32bit) */
4378 case 0x1: /* MSUB (32bit) */
4379 case 0x40: /* MADD (64bit) */
4380 case 0x41: /* MSUB (64bit) */
4381 case 0x4a: /* UMADDL */
4382 case 0x4b: /* UMSUBL */
4383 case 0x4c: /* UMULH */
4386 unallocated_encoding(s
);
4391 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4392 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4393 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4394 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4397 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4399 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4402 tcg_temp_free_i64(low_bits
);
4406 tcg_op1
= tcg_temp_new_i64();
4407 tcg_op2
= tcg_temp_new_i64();
4408 tcg_tmp
= tcg_temp_new_i64();
4411 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4412 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4415 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4416 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4418 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4419 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4423 if (ra
== 31 && !is_sub
) {
4424 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4425 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4427 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4429 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4431 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4436 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4439 tcg_temp_free_i64(tcg_op1
);
4440 tcg_temp_free_i64(tcg_op2
);
4441 tcg_temp_free_i64(tcg_tmp
);
4444 /* Add/subtract (with carry)
4445 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4446 * +--+--+--+------------------------+------+-------------+------+-----+
4447 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4448 * +--+--+--+------------------------+------+-------------+------+-----+
4451 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4453 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4454 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4456 sf
= extract32(insn
, 31, 1);
4457 op
= extract32(insn
, 30, 1);
4458 setflags
= extract32(insn
, 29, 1);
4459 rm
= extract32(insn
, 16, 5);
4460 rn
= extract32(insn
, 5, 5);
4461 rd
= extract32(insn
, 0, 5);
4463 tcg_rd
= cpu_reg(s
, rd
);
4464 tcg_rn
= cpu_reg(s
, rn
);
4467 tcg_y
= new_tmp_a64(s
);
4468 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4470 tcg_y
= cpu_reg(s
, rm
);
4474 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4476 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4481 * Rotate right into flags
4482 * 31 30 29 21 15 10 5 4 0
4483 * +--+--+--+-----------------+--------+-----------+------+--+------+
4484 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4485 * +--+--+--+-----------------+--------+-----------+------+--+------+
4487 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4489 int mask
= extract32(insn
, 0, 4);
4490 int o2
= extract32(insn
, 4, 1);
4491 int rn
= extract32(insn
, 5, 5);
4492 int imm6
= extract32(insn
, 15, 6);
4493 int sf_op_s
= extract32(insn
, 29, 3);
4497 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4498 unallocated_encoding(s
);
4502 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4503 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4505 nzcv
= tcg_temp_new_i32();
4506 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4508 if (mask
& 8) { /* N */
4509 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4511 if (mask
& 4) { /* Z */
4512 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4513 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4515 if (mask
& 2) { /* C */
4516 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4518 if (mask
& 1) { /* V */
4519 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4522 tcg_temp_free_i32(nzcv
);
4526 * Evaluate into flags
4527 * 31 30 29 21 15 14 10 5 4 0
4528 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4529 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4530 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4532 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4534 int o3_mask
= extract32(insn
, 0, 5);
4535 int rn
= extract32(insn
, 5, 5);
4536 int o2
= extract32(insn
, 15, 6);
4537 int sz
= extract32(insn
, 14, 1);
4538 int sf_op_s
= extract32(insn
, 29, 3);
4542 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4543 !dc_isar_feature(aa64_condm_4
, s
)) {
4544 unallocated_encoding(s
);
4547 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4549 tmp
= tcg_temp_new_i32();
4550 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4551 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4552 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4553 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4554 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4555 tcg_temp_free_i32(tmp
);
4558 /* Conditional compare (immediate / register)
4559 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4560 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4561 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4562 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4565 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4567 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4568 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4569 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4572 if (!extract32(insn
, 29, 1)) {
4573 unallocated_encoding(s
);
4576 if (insn
& (1 << 10 | 1 << 4)) {
4577 unallocated_encoding(s
);
4580 sf
= extract32(insn
, 31, 1);
4581 op
= extract32(insn
, 30, 1);
4582 is_imm
= extract32(insn
, 11, 1);
4583 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4584 cond
= extract32(insn
, 12, 4);
4585 rn
= extract32(insn
, 5, 5);
4586 nzcv
= extract32(insn
, 0, 4);
4588 /* Set T0 = !COND. */
4589 tcg_t0
= tcg_temp_new_i32();
4590 arm_test_cc(&c
, cond
);
4591 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4594 /* Load the arguments for the new comparison. */
4596 tcg_y
= new_tmp_a64(s
);
4597 tcg_gen_movi_i64(tcg_y
, y
);
4599 tcg_y
= cpu_reg(s
, y
);
4601 tcg_rn
= cpu_reg(s
, rn
);
4603 /* Set the flags for the new comparison. */
4604 tcg_tmp
= tcg_temp_new_i64();
4606 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4608 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4610 tcg_temp_free_i64(tcg_tmp
);
4612 /* If COND was false, force the flags to #nzcv. Compute two masks
4613 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4614 * For tcg hosts that support ANDC, we can make do with just T1.
4615 * In either case, allow the tcg optimizer to delete any unused mask.
4617 tcg_t1
= tcg_temp_new_i32();
4618 tcg_t2
= tcg_temp_new_i32();
4619 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4620 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4622 if (nzcv
& 8) { /* N */
4623 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4625 if (TCG_TARGET_HAS_andc_i32
) {
4626 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4628 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4631 if (nzcv
& 4) { /* Z */
4632 if (TCG_TARGET_HAS_andc_i32
) {
4633 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4635 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4638 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4640 if (nzcv
& 2) { /* C */
4641 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4643 if (TCG_TARGET_HAS_andc_i32
) {
4644 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4646 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4649 if (nzcv
& 1) { /* V */
4650 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4652 if (TCG_TARGET_HAS_andc_i32
) {
4653 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4655 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4658 tcg_temp_free_i32(tcg_t0
);
4659 tcg_temp_free_i32(tcg_t1
);
4660 tcg_temp_free_i32(tcg_t2
);
4663 /* Conditional select
4664 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4665 * +----+----+---+-----------------+------+------+-----+------+------+
4666 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4667 * +----+----+---+-----------------+------+------+-----+------+------+
4669 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4671 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4672 TCGv_i64 tcg_rd
, zero
;
4675 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4676 /* S == 1 or op2<1> == 1 */
4677 unallocated_encoding(s
);
4680 sf
= extract32(insn
, 31, 1);
4681 else_inv
= extract32(insn
, 30, 1);
4682 rm
= extract32(insn
, 16, 5);
4683 cond
= extract32(insn
, 12, 4);
4684 else_inc
= extract32(insn
, 10, 1);
4685 rn
= extract32(insn
, 5, 5);
4686 rd
= extract32(insn
, 0, 5);
4688 tcg_rd
= cpu_reg(s
, rd
);
4690 a64_test_cc(&c
, cond
);
4691 zero
= tcg_const_i64(0);
4693 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4695 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4697 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4700 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4701 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4702 if (else_inv
&& else_inc
) {
4703 tcg_gen_neg_i64(t_false
, t_false
);
4704 } else if (else_inv
) {
4705 tcg_gen_not_i64(t_false
, t_false
);
4706 } else if (else_inc
) {
4707 tcg_gen_addi_i64(t_false
, t_false
, 1);
4709 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4712 tcg_temp_free_i64(zero
);
4716 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4720 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4721 unsigned int rn
, unsigned int rd
)
4723 TCGv_i64 tcg_rd
, tcg_rn
;
4724 tcg_rd
= cpu_reg(s
, rd
);
4725 tcg_rn
= cpu_reg(s
, rn
);
4728 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4730 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4731 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4732 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4733 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4734 tcg_temp_free_i32(tcg_tmp32
);
4738 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4739 unsigned int rn
, unsigned int rd
)
4741 TCGv_i64 tcg_rd
, tcg_rn
;
4742 tcg_rd
= cpu_reg(s
, rd
);
4743 tcg_rn
= cpu_reg(s
, rn
);
4746 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4748 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4749 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4750 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4751 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4752 tcg_temp_free_i32(tcg_tmp32
);
4756 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4757 unsigned int rn
, unsigned int rd
)
4759 TCGv_i64 tcg_rd
, tcg_rn
;
4760 tcg_rd
= cpu_reg(s
, rd
);
4761 tcg_rn
= cpu_reg(s
, rn
);
4764 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4766 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4767 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4768 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4769 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4770 tcg_temp_free_i32(tcg_tmp32
);
4774 /* REV with sf==1, opcode==3 ("REV64") */
4775 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4776 unsigned int rn
, unsigned int rd
)
4779 unallocated_encoding(s
);
4782 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4785 /* REV with sf==0, opcode==2
4786 * REV32 (sf==1, opcode==2)
4788 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4789 unsigned int rn
, unsigned int rd
)
4791 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4794 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4795 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4797 /* bswap32_i64 requires zero high word */
4798 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4799 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4800 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4801 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4802 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4804 tcg_temp_free_i64(tcg_tmp
);
4806 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4807 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4811 /* REV16 (opcode==1) */
4812 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4813 unsigned int rn
, unsigned int rd
)
4815 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4816 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4817 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4818 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4820 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4821 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4822 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4823 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4824 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4826 tcg_temp_free_i64(mask
);
4827 tcg_temp_free_i64(tcg_tmp
);
4830 /* Data-processing (1 source)
4831 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4832 * +----+---+---+-----------------+---------+--------+------+------+
4833 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4834 * +----+---+---+-----------------+---------+--------+------+------+
4836 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4838 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4841 if (extract32(insn
, 29, 1)) {
4842 unallocated_encoding(s
);
4846 sf
= extract32(insn
, 31, 1);
4847 opcode
= extract32(insn
, 10, 6);
4848 opcode2
= extract32(insn
, 16, 5);
4849 rn
= extract32(insn
, 5, 5);
4850 rd
= extract32(insn
, 0, 5);
4852 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4854 switch (MAP(sf
, opcode2
, opcode
)) {
4855 case MAP(0, 0x00, 0x00): /* RBIT */
4856 case MAP(1, 0x00, 0x00):
4857 handle_rbit(s
, sf
, rn
, rd
);
4859 case MAP(0, 0x00, 0x01): /* REV16 */
4860 case MAP(1, 0x00, 0x01):
4861 handle_rev16(s
, sf
, rn
, rd
);
4863 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4864 case MAP(1, 0x00, 0x02):
4865 handle_rev32(s
, sf
, rn
, rd
);
4867 case MAP(1, 0x00, 0x03): /* REV64 */
4868 handle_rev64(s
, sf
, rn
, rd
);
4870 case MAP(0, 0x00, 0x04): /* CLZ */
4871 case MAP(1, 0x00, 0x04):
4872 handle_clz(s
, sf
, rn
, rd
);
4874 case MAP(0, 0x00, 0x05): /* CLS */
4875 case MAP(1, 0x00, 0x05):
4876 handle_cls(s
, sf
, rn
, rd
);
4878 case MAP(1, 0x01, 0x00): /* PACIA */
4879 if (s
->pauth_active
) {
4880 tcg_rd
= cpu_reg(s
, rd
);
4881 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4882 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4883 goto do_unallocated
;
4886 case MAP(1, 0x01, 0x01): /* PACIB */
4887 if (s
->pauth_active
) {
4888 tcg_rd
= cpu_reg(s
, rd
);
4889 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4890 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4891 goto do_unallocated
;
4894 case MAP(1, 0x01, 0x02): /* PACDA */
4895 if (s
->pauth_active
) {
4896 tcg_rd
= cpu_reg(s
, rd
);
4897 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4898 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4899 goto do_unallocated
;
4902 case MAP(1, 0x01, 0x03): /* PACDB */
4903 if (s
->pauth_active
) {
4904 tcg_rd
= cpu_reg(s
, rd
);
4905 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4906 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4907 goto do_unallocated
;
4910 case MAP(1, 0x01, 0x04): /* AUTIA */
4911 if (s
->pauth_active
) {
4912 tcg_rd
= cpu_reg(s
, rd
);
4913 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4914 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4915 goto do_unallocated
;
4918 case MAP(1, 0x01, 0x05): /* AUTIB */
4919 if (s
->pauth_active
) {
4920 tcg_rd
= cpu_reg(s
, rd
);
4921 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4922 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4923 goto do_unallocated
;
4926 case MAP(1, 0x01, 0x06): /* AUTDA */
4927 if (s
->pauth_active
) {
4928 tcg_rd
= cpu_reg(s
, rd
);
4929 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4930 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4931 goto do_unallocated
;
4934 case MAP(1, 0x01, 0x07): /* AUTDB */
4935 if (s
->pauth_active
) {
4936 tcg_rd
= cpu_reg(s
, rd
);
4937 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4938 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4939 goto do_unallocated
;
4942 case MAP(1, 0x01, 0x08): /* PACIZA */
4943 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4944 goto do_unallocated
;
4945 } else if (s
->pauth_active
) {
4946 tcg_rd
= cpu_reg(s
, rd
);
4947 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4950 case MAP(1, 0x01, 0x09): /* PACIZB */
4951 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4952 goto do_unallocated
;
4953 } else if (s
->pauth_active
) {
4954 tcg_rd
= cpu_reg(s
, rd
);
4955 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4958 case MAP(1, 0x01, 0x0a): /* PACDZA */
4959 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4960 goto do_unallocated
;
4961 } else if (s
->pauth_active
) {
4962 tcg_rd
= cpu_reg(s
, rd
);
4963 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4966 case MAP(1, 0x01, 0x0b): /* PACDZB */
4967 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4968 goto do_unallocated
;
4969 } else if (s
->pauth_active
) {
4970 tcg_rd
= cpu_reg(s
, rd
);
4971 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4974 case MAP(1, 0x01, 0x0c): /* AUTIZA */
4975 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4976 goto do_unallocated
;
4977 } else if (s
->pauth_active
) {
4978 tcg_rd
= cpu_reg(s
, rd
);
4979 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4982 case MAP(1, 0x01, 0x0d): /* AUTIZB */
4983 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4984 goto do_unallocated
;
4985 } else if (s
->pauth_active
) {
4986 tcg_rd
= cpu_reg(s
, rd
);
4987 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4990 case MAP(1, 0x01, 0x0e): /* AUTDZA */
4991 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4992 goto do_unallocated
;
4993 } else if (s
->pauth_active
) {
4994 tcg_rd
= cpu_reg(s
, rd
);
4995 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4998 case MAP(1, 0x01, 0x0f): /* AUTDZB */
4999 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5000 goto do_unallocated
;
5001 } else if (s
->pauth_active
) {
5002 tcg_rd
= cpu_reg(s
, rd
);
5003 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5006 case MAP(1, 0x01, 0x10): /* XPACI */
5007 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5008 goto do_unallocated
;
5009 } else if (s
->pauth_active
) {
5010 tcg_rd
= cpu_reg(s
, rd
);
5011 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5014 case MAP(1, 0x01, 0x11): /* XPACD */
5015 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5016 goto do_unallocated
;
5017 } else if (s
->pauth_active
) {
5018 tcg_rd
= cpu_reg(s
, rd
);
5019 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5024 unallocated_encoding(s
);
5031 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5032 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5034 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5035 tcg_rd
= cpu_reg(s
, rd
);
5037 if (!sf
&& is_signed
) {
5038 tcg_n
= new_tmp_a64(s
);
5039 tcg_m
= new_tmp_a64(s
);
5040 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5041 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5043 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5044 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5048 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5050 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5053 if (!sf
) { /* zero extend final result */
5054 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5058 /* LSLV, LSRV, ASRV, RORV */
5059 static void handle_shift_reg(DisasContext
*s
,
5060 enum a64_shift_type shift_type
, unsigned int sf
,
5061 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5063 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5064 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5065 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5067 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5068 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5069 tcg_temp_free_i64(tcg_shift
);
5072 /* CRC32[BHWX], CRC32C[BHWX] */
5073 static void handle_crc32(DisasContext
*s
,
5074 unsigned int sf
, unsigned int sz
, bool crc32c
,
5075 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5077 TCGv_i64 tcg_acc
, tcg_val
;
5080 if (!dc_isar_feature(aa64_crc32
, s
)
5081 || (sf
== 1 && sz
!= 3)
5082 || (sf
== 0 && sz
== 3)) {
5083 unallocated_encoding(s
);
5088 tcg_val
= cpu_reg(s
, rm
);
5102 g_assert_not_reached();
5104 tcg_val
= new_tmp_a64(s
);
5105 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5108 tcg_acc
= cpu_reg(s
, rn
);
5109 tcg_bytes
= tcg_const_i32(1 << sz
);
5112 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5114 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5117 tcg_temp_free_i32(tcg_bytes
);
5120 /* Data-processing (2 source)
5121 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5122 * +----+---+---+-----------------+------+--------+------+------+
5123 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5124 * +----+---+---+-----------------+------+--------+------+------+
5126 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5128 unsigned int sf
, rm
, opcode
, rn
, rd
;
5129 sf
= extract32(insn
, 31, 1);
5130 rm
= extract32(insn
, 16, 5);
5131 opcode
= extract32(insn
, 10, 6);
5132 rn
= extract32(insn
, 5, 5);
5133 rd
= extract32(insn
, 0, 5);
5135 if (extract32(insn
, 29, 1)) {
5136 unallocated_encoding(s
);
5142 handle_div(s
, false, sf
, rm
, rn
, rd
);
5145 handle_div(s
, true, sf
, rm
, rn
, rd
);
5148 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5151 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5154 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5157 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5159 case 12: /* PACGA */
5160 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5161 goto do_unallocated
;
5163 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5164 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5173 case 23: /* CRC32 */
5175 int sz
= extract32(opcode
, 0, 2);
5176 bool crc32c
= extract32(opcode
, 2, 1);
5177 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5182 unallocated_encoding(s
);
5188 * Data processing - register
5189 * 31 30 29 28 25 21 20 16 10 0
5190 * +--+---+--+---+-------+-----+-------+-------+---------+
5191 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5192 * +--+---+--+---+-------+-----+-------+-------+---------+
5194 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5196 int op0
= extract32(insn
, 30, 1);
5197 int op1
= extract32(insn
, 28, 1);
5198 int op2
= extract32(insn
, 21, 4);
5199 int op3
= extract32(insn
, 10, 6);
5204 /* Add/sub (extended register) */
5205 disas_add_sub_ext_reg(s
, insn
);
5207 /* Add/sub (shifted register) */
5208 disas_add_sub_reg(s
, insn
);
5211 /* Logical (shifted register) */
5212 disas_logic_reg(s
, insn
);
5220 case 0x00: /* Add/subtract (with carry) */
5221 disas_adc_sbc(s
, insn
);
5224 case 0x01: /* Rotate right into flags */
5226 disas_rotate_right_into_flags(s
, insn
);
5229 case 0x02: /* Evaluate into flags */
5233 disas_evaluate_into_flags(s
, insn
);
5237 goto do_unallocated
;
5241 case 0x2: /* Conditional compare */
5242 disas_cc(s
, insn
); /* both imm and reg forms */
5245 case 0x4: /* Conditional select */
5246 disas_cond_select(s
, insn
);
5249 case 0x6: /* Data-processing */
5250 if (op0
) { /* (1 source) */
5251 disas_data_proc_1src(s
, insn
);
5252 } else { /* (2 source) */
5253 disas_data_proc_2src(s
, insn
);
5256 case 0x8 ... 0xf: /* (3 source) */
5257 disas_data_proc_3src(s
, insn
);
5262 unallocated_encoding(s
);
5267 static void handle_fp_compare(DisasContext
*s
, int size
,
5268 unsigned int rn
, unsigned int rm
,
5269 bool cmp_with_zero
, bool signal_all_nans
)
5271 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5272 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5274 if (size
== MO_64
) {
5275 TCGv_i64 tcg_vn
, tcg_vm
;
5277 tcg_vn
= read_fp_dreg(s
, rn
);
5278 if (cmp_with_zero
) {
5279 tcg_vm
= tcg_const_i64(0);
5281 tcg_vm
= read_fp_dreg(s
, rm
);
5283 if (signal_all_nans
) {
5284 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5286 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5288 tcg_temp_free_i64(tcg_vn
);
5289 tcg_temp_free_i64(tcg_vm
);
5291 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5292 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5294 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5295 if (cmp_with_zero
) {
5296 tcg_gen_movi_i32(tcg_vm
, 0);
5298 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5303 if (signal_all_nans
) {
5304 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5306 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5310 if (signal_all_nans
) {
5311 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5313 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5317 g_assert_not_reached();
5320 tcg_temp_free_i32(tcg_vn
);
5321 tcg_temp_free_i32(tcg_vm
);
5324 tcg_temp_free_ptr(fpst
);
5326 gen_set_nzcv(tcg_flags
);
5328 tcg_temp_free_i64(tcg_flags
);
5331 /* Floating point compare
5332 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5333 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5334 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5335 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5337 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5339 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5342 mos
= extract32(insn
, 29, 3);
5343 type
= extract32(insn
, 22, 2);
5344 rm
= extract32(insn
, 16, 5);
5345 op
= extract32(insn
, 14, 2);
5346 rn
= extract32(insn
, 5, 5);
5347 opc
= extract32(insn
, 3, 2);
5348 op2r
= extract32(insn
, 0, 3);
5350 if (mos
|| op
|| op2r
) {
5351 unallocated_encoding(s
);
5364 if (dc_isar_feature(aa64_fp16
, s
)) {
5369 unallocated_encoding(s
);
5373 if (!fp_access_check(s
)) {
5377 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5380 /* Floating point conditional compare
5381 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5382 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5383 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5384 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5386 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5388 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5390 TCGLabel
*label_continue
= NULL
;
5393 mos
= extract32(insn
, 29, 3);
5394 type
= extract32(insn
, 22, 2);
5395 rm
= extract32(insn
, 16, 5);
5396 cond
= extract32(insn
, 12, 4);
5397 rn
= extract32(insn
, 5, 5);
5398 op
= extract32(insn
, 4, 1);
5399 nzcv
= extract32(insn
, 0, 4);
5402 unallocated_encoding(s
);
5415 if (dc_isar_feature(aa64_fp16
, s
)) {
5420 unallocated_encoding(s
);
5424 if (!fp_access_check(s
)) {
5428 if (cond
< 0x0e) { /* not always */
5429 TCGLabel
*label_match
= gen_new_label();
5430 label_continue
= gen_new_label();
5431 arm_gen_test_cc(cond
, label_match
);
5433 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5434 gen_set_nzcv(tcg_flags
);
5435 tcg_temp_free_i64(tcg_flags
);
5436 tcg_gen_br(label_continue
);
5437 gen_set_label(label_match
);
5440 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5443 gen_set_label(label_continue
);
5447 /* Floating point conditional select
5448 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5449 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5450 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5451 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5453 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5455 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5456 TCGv_i64 t_true
, t_false
, t_zero
;
5460 mos
= extract32(insn
, 29, 3);
5461 type
= extract32(insn
, 22, 2);
5462 rm
= extract32(insn
, 16, 5);
5463 cond
= extract32(insn
, 12, 4);
5464 rn
= extract32(insn
, 5, 5);
5465 rd
= extract32(insn
, 0, 5);
5468 unallocated_encoding(s
);
5481 if (dc_isar_feature(aa64_fp16
, s
)) {
5486 unallocated_encoding(s
);
5490 if (!fp_access_check(s
)) {
5494 /* Zero extend sreg & hreg inputs to 64 bits now. */
5495 t_true
= tcg_temp_new_i64();
5496 t_false
= tcg_temp_new_i64();
5497 read_vec_element(s
, t_true
, rn
, 0, sz
);
5498 read_vec_element(s
, t_false
, rm
, 0, sz
);
5500 a64_test_cc(&c
, cond
);
5501 t_zero
= tcg_const_i64(0);
5502 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5503 tcg_temp_free_i64(t_zero
);
5504 tcg_temp_free_i64(t_false
);
5507 /* Note that sregs & hregs write back zeros to the high bits,
5508 and we've already done the zero-extension. */
5509 write_fp_dreg(s
, rd
, t_true
);
5510 tcg_temp_free_i64(t_true
);
5513 /* Floating-point data-processing (1 source) - half precision */
5514 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5516 TCGv_ptr fpst
= NULL
;
5517 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5518 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5521 case 0x0: /* FMOV */
5522 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5524 case 0x1: /* FABS */
5525 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5527 case 0x2: /* FNEG */
5528 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5530 case 0x3: /* FSQRT */
5531 fpst
= get_fpstatus_ptr(true);
5532 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5534 case 0x8: /* FRINTN */
5535 case 0x9: /* FRINTP */
5536 case 0xa: /* FRINTM */
5537 case 0xb: /* FRINTZ */
5538 case 0xc: /* FRINTA */
5540 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5541 fpst
= get_fpstatus_ptr(true);
5543 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5544 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5546 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5547 tcg_temp_free_i32(tcg_rmode
);
5550 case 0xe: /* FRINTX */
5551 fpst
= get_fpstatus_ptr(true);
5552 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5554 case 0xf: /* FRINTI */
5555 fpst
= get_fpstatus_ptr(true);
5556 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5562 write_fp_sreg(s
, rd
, tcg_res
);
5565 tcg_temp_free_ptr(fpst
);
5567 tcg_temp_free_i32(tcg_op
);
5568 tcg_temp_free_i32(tcg_res
);
5571 /* Floating-point data-processing (1 source) - single precision */
5572 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5574 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5575 TCGv_i32 tcg_op
, tcg_res
;
5579 tcg_op
= read_fp_sreg(s
, rn
);
5580 tcg_res
= tcg_temp_new_i32();
5583 case 0x0: /* FMOV */
5584 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5586 case 0x1: /* FABS */
5587 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5589 case 0x2: /* FNEG */
5590 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5592 case 0x3: /* FSQRT */
5593 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5595 case 0x8: /* FRINTN */
5596 case 0x9: /* FRINTP */
5597 case 0xa: /* FRINTM */
5598 case 0xb: /* FRINTZ */
5599 case 0xc: /* FRINTA */
5600 rmode
= arm_rmode_to_sf(opcode
& 7);
5601 gen_fpst
= gen_helper_rints
;
5603 case 0xe: /* FRINTX */
5604 gen_fpst
= gen_helper_rints_exact
;
5606 case 0xf: /* FRINTI */
5607 gen_fpst
= gen_helper_rints
;
5609 case 0x10: /* FRINT32Z */
5610 rmode
= float_round_to_zero
;
5611 gen_fpst
= gen_helper_frint32_s
;
5613 case 0x11: /* FRINT32X */
5614 gen_fpst
= gen_helper_frint32_s
;
5616 case 0x12: /* FRINT64Z */
5617 rmode
= float_round_to_zero
;
5618 gen_fpst
= gen_helper_frint64_s
;
5620 case 0x13: /* FRINT64X */
5621 gen_fpst
= gen_helper_frint64_s
;
5624 g_assert_not_reached();
5627 fpst
= get_fpstatus_ptr(false);
5629 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5630 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5631 gen_fpst(tcg_res
, tcg_op
, fpst
);
5632 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5633 tcg_temp_free_i32(tcg_rmode
);
5635 gen_fpst(tcg_res
, tcg_op
, fpst
);
5637 tcg_temp_free_ptr(fpst
);
5640 write_fp_sreg(s
, rd
, tcg_res
);
5641 tcg_temp_free_i32(tcg_op
);
5642 tcg_temp_free_i32(tcg_res
);
5645 /* Floating-point data-processing (1 source) - double precision */
5646 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5648 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5649 TCGv_i64 tcg_op
, tcg_res
;
5654 case 0x0: /* FMOV */
5655 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5659 tcg_op
= read_fp_dreg(s
, rn
);
5660 tcg_res
= tcg_temp_new_i64();
5663 case 0x1: /* FABS */
5664 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5666 case 0x2: /* FNEG */
5667 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5669 case 0x3: /* FSQRT */
5670 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5672 case 0x8: /* FRINTN */
5673 case 0x9: /* FRINTP */
5674 case 0xa: /* FRINTM */
5675 case 0xb: /* FRINTZ */
5676 case 0xc: /* FRINTA */
5677 rmode
= arm_rmode_to_sf(opcode
& 7);
5678 gen_fpst
= gen_helper_rintd
;
5680 case 0xe: /* FRINTX */
5681 gen_fpst
= gen_helper_rintd_exact
;
5683 case 0xf: /* FRINTI */
5684 gen_fpst
= gen_helper_rintd
;
5686 case 0x10: /* FRINT32Z */
5687 rmode
= float_round_to_zero
;
5688 gen_fpst
= gen_helper_frint32_d
;
5690 case 0x11: /* FRINT32X */
5691 gen_fpst
= gen_helper_frint32_d
;
5693 case 0x12: /* FRINT64Z */
5694 rmode
= float_round_to_zero
;
5695 gen_fpst
= gen_helper_frint64_d
;
5697 case 0x13: /* FRINT64X */
5698 gen_fpst
= gen_helper_frint64_d
;
5701 g_assert_not_reached();
5704 fpst
= get_fpstatus_ptr(false);
5706 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5707 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5708 gen_fpst(tcg_res
, tcg_op
, fpst
);
5709 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5710 tcg_temp_free_i32(tcg_rmode
);
5712 gen_fpst(tcg_res
, tcg_op
, fpst
);
5714 tcg_temp_free_ptr(fpst
);
5717 write_fp_dreg(s
, rd
, tcg_res
);
5718 tcg_temp_free_i64(tcg_op
);
5719 tcg_temp_free_i64(tcg_res
);
5722 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5723 int rd
, int rn
, int dtype
, int ntype
)
5728 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5730 /* Single to double */
5731 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5732 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5733 write_fp_dreg(s
, rd
, tcg_rd
);
5734 tcg_temp_free_i64(tcg_rd
);
5736 /* Single to half */
5737 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5738 TCGv_i32 ahp
= get_ahp_flag();
5739 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5741 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5742 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5743 write_fp_sreg(s
, rd
, tcg_rd
);
5744 tcg_temp_free_i32(tcg_rd
);
5745 tcg_temp_free_i32(ahp
);
5746 tcg_temp_free_ptr(fpst
);
5748 tcg_temp_free_i32(tcg_rn
);
5753 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5754 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5756 /* Double to single */
5757 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5759 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5760 TCGv_i32 ahp
= get_ahp_flag();
5761 /* Double to half */
5762 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5763 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5764 tcg_temp_free_ptr(fpst
);
5765 tcg_temp_free_i32(ahp
);
5767 write_fp_sreg(s
, rd
, tcg_rd
);
5768 tcg_temp_free_i32(tcg_rd
);
5769 tcg_temp_free_i64(tcg_rn
);
5774 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5775 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5776 TCGv_i32 tcg_ahp
= get_ahp_flag();
5777 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5779 /* Half to single */
5780 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5781 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5782 write_fp_sreg(s
, rd
, tcg_rd
);
5783 tcg_temp_free_ptr(tcg_fpst
);
5784 tcg_temp_free_i32(tcg_ahp
);
5785 tcg_temp_free_i32(tcg_rd
);
5787 /* Half to double */
5788 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5789 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5790 write_fp_dreg(s
, rd
, tcg_rd
);
5791 tcg_temp_free_i64(tcg_rd
);
5793 tcg_temp_free_i32(tcg_rn
);
5801 /* Floating point data-processing (1 source)
5802 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5803 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5804 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5805 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5807 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5809 int mos
= extract32(insn
, 29, 3);
5810 int type
= extract32(insn
, 22, 2);
5811 int opcode
= extract32(insn
, 15, 6);
5812 int rn
= extract32(insn
, 5, 5);
5813 int rd
= extract32(insn
, 0, 5);
5816 unallocated_encoding(s
);
5821 case 0x4: case 0x5: case 0x7:
5823 /* FCVT between half, single and double precision */
5824 int dtype
= extract32(opcode
, 0, 2);
5825 if (type
== 2 || dtype
== type
) {
5826 unallocated_encoding(s
);
5829 if (!fp_access_check(s
)) {
5833 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5837 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
5838 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
5839 unallocated_encoding(s
);
5846 /* 32-to-32 and 64-to-64 ops */
5849 if (!fp_access_check(s
)) {
5852 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5855 if (!fp_access_check(s
)) {
5858 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5861 if (!dc_isar_feature(aa64_fp16
, s
)) {
5862 unallocated_encoding(s
);
5866 if (!fp_access_check(s
)) {
5869 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5872 unallocated_encoding(s
);
5877 unallocated_encoding(s
);
5882 /* Floating-point data-processing (2 source) - single precision */
5883 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5884 int rd
, int rn
, int rm
)
5891 tcg_res
= tcg_temp_new_i32();
5892 fpst
= get_fpstatus_ptr(false);
5893 tcg_op1
= read_fp_sreg(s
, rn
);
5894 tcg_op2
= read_fp_sreg(s
, rm
);
5897 case 0x0: /* FMUL */
5898 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5900 case 0x1: /* FDIV */
5901 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5903 case 0x2: /* FADD */
5904 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5906 case 0x3: /* FSUB */
5907 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5909 case 0x4: /* FMAX */
5910 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5912 case 0x5: /* FMIN */
5913 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5915 case 0x6: /* FMAXNM */
5916 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5918 case 0x7: /* FMINNM */
5919 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5921 case 0x8: /* FNMUL */
5922 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5923 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5927 write_fp_sreg(s
, rd
, tcg_res
);
5929 tcg_temp_free_ptr(fpst
);
5930 tcg_temp_free_i32(tcg_op1
);
5931 tcg_temp_free_i32(tcg_op2
);
5932 tcg_temp_free_i32(tcg_res
);
5935 /* Floating-point data-processing (2 source) - double precision */
5936 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5937 int rd
, int rn
, int rm
)
5944 tcg_res
= tcg_temp_new_i64();
5945 fpst
= get_fpstatus_ptr(false);
5946 tcg_op1
= read_fp_dreg(s
, rn
);
5947 tcg_op2
= read_fp_dreg(s
, rm
);
5950 case 0x0: /* FMUL */
5951 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5953 case 0x1: /* FDIV */
5954 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5956 case 0x2: /* FADD */
5957 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5959 case 0x3: /* FSUB */
5960 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5962 case 0x4: /* FMAX */
5963 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5965 case 0x5: /* FMIN */
5966 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5968 case 0x6: /* FMAXNM */
5969 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5971 case 0x7: /* FMINNM */
5972 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5974 case 0x8: /* FNMUL */
5975 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5976 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5980 write_fp_dreg(s
, rd
, tcg_res
);
5982 tcg_temp_free_ptr(fpst
);
5983 tcg_temp_free_i64(tcg_op1
);
5984 tcg_temp_free_i64(tcg_op2
);
5985 tcg_temp_free_i64(tcg_res
);
5988 /* Floating-point data-processing (2 source) - half precision */
5989 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5990 int rd
, int rn
, int rm
)
5997 tcg_res
= tcg_temp_new_i32();
5998 fpst
= get_fpstatus_ptr(true);
5999 tcg_op1
= read_fp_hreg(s
, rn
);
6000 tcg_op2
= read_fp_hreg(s
, rm
);
6003 case 0x0: /* FMUL */
6004 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6006 case 0x1: /* FDIV */
6007 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6009 case 0x2: /* FADD */
6010 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6012 case 0x3: /* FSUB */
6013 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6015 case 0x4: /* FMAX */
6016 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6018 case 0x5: /* FMIN */
6019 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6021 case 0x6: /* FMAXNM */
6022 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6024 case 0x7: /* FMINNM */
6025 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6027 case 0x8: /* FNMUL */
6028 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6029 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6032 g_assert_not_reached();
6035 write_fp_sreg(s
, rd
, tcg_res
);
6037 tcg_temp_free_ptr(fpst
);
6038 tcg_temp_free_i32(tcg_op1
);
6039 tcg_temp_free_i32(tcg_op2
);
6040 tcg_temp_free_i32(tcg_res
);
6043 /* Floating point data-processing (2 source)
6044 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6045 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6046 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6047 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6049 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6051 int mos
= extract32(insn
, 29, 3);
6052 int type
= extract32(insn
, 22, 2);
6053 int rd
= extract32(insn
, 0, 5);
6054 int rn
= extract32(insn
, 5, 5);
6055 int rm
= extract32(insn
, 16, 5);
6056 int opcode
= extract32(insn
, 12, 4);
6058 if (opcode
> 8 || mos
) {
6059 unallocated_encoding(s
);
6065 if (!fp_access_check(s
)) {
6068 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6071 if (!fp_access_check(s
)) {
6074 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6077 if (!dc_isar_feature(aa64_fp16
, s
)) {
6078 unallocated_encoding(s
);
6081 if (!fp_access_check(s
)) {
6084 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6087 unallocated_encoding(s
);
6091 /* Floating-point data-processing (3 source) - single precision */
6092 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6093 int rd
, int rn
, int rm
, int ra
)
6095 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6096 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6097 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6099 tcg_op1
= read_fp_sreg(s
, rn
);
6100 tcg_op2
= read_fp_sreg(s
, rm
);
6101 tcg_op3
= read_fp_sreg(s
, ra
);
6103 /* These are fused multiply-add, and must be done as one
6104 * floating point operation with no rounding between the
6105 * multiplication and addition steps.
6106 * NB that doing the negations here as separate steps is
6107 * correct : an input NaN should come out with its sign bit
6108 * flipped if it is a negated-input.
6111 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6115 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6118 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6120 write_fp_sreg(s
, rd
, tcg_res
);
6122 tcg_temp_free_ptr(fpst
);
6123 tcg_temp_free_i32(tcg_op1
);
6124 tcg_temp_free_i32(tcg_op2
);
6125 tcg_temp_free_i32(tcg_op3
);
6126 tcg_temp_free_i32(tcg_res
);
6129 /* Floating-point data-processing (3 source) - double precision */
6130 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6131 int rd
, int rn
, int rm
, int ra
)
6133 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6134 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6135 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6137 tcg_op1
= read_fp_dreg(s
, rn
);
6138 tcg_op2
= read_fp_dreg(s
, rm
);
6139 tcg_op3
= read_fp_dreg(s
, ra
);
6141 /* These are fused multiply-add, and must be done as one
6142 * floating point operation with no rounding between the
6143 * multiplication and addition steps.
6144 * NB that doing the negations here as separate steps is
6145 * correct : an input NaN should come out with its sign bit
6146 * flipped if it is a negated-input.
6149 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6153 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6156 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6158 write_fp_dreg(s
, rd
, tcg_res
);
6160 tcg_temp_free_ptr(fpst
);
6161 tcg_temp_free_i64(tcg_op1
);
6162 tcg_temp_free_i64(tcg_op2
);
6163 tcg_temp_free_i64(tcg_op3
);
6164 tcg_temp_free_i64(tcg_res
);
6167 /* Floating-point data-processing (3 source) - half precision */
6168 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6169 int rd
, int rn
, int rm
, int ra
)
6171 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6172 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6173 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6175 tcg_op1
= read_fp_hreg(s
, rn
);
6176 tcg_op2
= read_fp_hreg(s
, rm
);
6177 tcg_op3
= read_fp_hreg(s
, ra
);
6179 /* These are fused multiply-add, and must be done as one
6180 * floating point operation with no rounding between the
6181 * multiplication and addition steps.
6182 * NB that doing the negations here as separate steps is
6183 * correct : an input NaN should come out with its sign bit
6184 * flipped if it is a negated-input.
6187 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6191 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6194 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6196 write_fp_sreg(s
, rd
, tcg_res
);
6198 tcg_temp_free_ptr(fpst
);
6199 tcg_temp_free_i32(tcg_op1
);
6200 tcg_temp_free_i32(tcg_op2
);
6201 tcg_temp_free_i32(tcg_op3
);
6202 tcg_temp_free_i32(tcg_res
);
6205 /* Floating point data-processing (3 source)
6206 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6207 * +---+---+---+-----------+------+----+------+----+------+------+------+
6208 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6209 * +---+---+---+-----------+------+----+------+----+------+------+------+
6211 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6213 int mos
= extract32(insn
, 29, 3);
6214 int type
= extract32(insn
, 22, 2);
6215 int rd
= extract32(insn
, 0, 5);
6216 int rn
= extract32(insn
, 5, 5);
6217 int ra
= extract32(insn
, 10, 5);
6218 int rm
= extract32(insn
, 16, 5);
6219 bool o0
= extract32(insn
, 15, 1);
6220 bool o1
= extract32(insn
, 21, 1);
6223 unallocated_encoding(s
);
6229 if (!fp_access_check(s
)) {
6232 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6235 if (!fp_access_check(s
)) {
6238 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6241 if (!dc_isar_feature(aa64_fp16
, s
)) {
6242 unallocated_encoding(s
);
6245 if (!fp_access_check(s
)) {
6248 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6251 unallocated_encoding(s
);
6255 /* Floating point immediate
6256 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6257 * +---+---+---+-----------+------+---+------------+-------+------+------+
6258 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6259 * +---+---+---+-----------+------+---+------------+-------+------+------+
6261 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6263 int rd
= extract32(insn
, 0, 5);
6264 int imm5
= extract32(insn
, 5, 5);
6265 int imm8
= extract32(insn
, 13, 8);
6266 int type
= extract32(insn
, 22, 2);
6267 int mos
= extract32(insn
, 29, 3);
6273 unallocated_encoding(s
);
6286 if (dc_isar_feature(aa64_fp16
, s
)) {
6291 unallocated_encoding(s
);
6295 if (!fp_access_check(s
)) {
6299 imm
= vfp_expand_imm(sz
, imm8
);
6301 tcg_res
= tcg_const_i64(imm
);
6302 write_fp_dreg(s
, rd
, tcg_res
);
6303 tcg_temp_free_i64(tcg_res
);
6306 /* Handle floating point <=> fixed point conversions. Note that we can
6307 * also deal with fp <=> integer conversions as a special case (scale == 64)
6308 * OPTME: consider handling that special case specially or at least skipping
6309 * the call to scalbn in the helpers for zero shifts.
6311 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6312 bool itof
, int rmode
, int scale
, int sf
, int type
)
6314 bool is_signed
= !(opcode
& 1);
6315 TCGv_ptr tcg_fpstatus
;
6316 TCGv_i32 tcg_shift
, tcg_single
;
6317 TCGv_i64 tcg_double
;
6319 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6321 tcg_shift
= tcg_const_i32(64 - scale
);
6324 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6326 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6329 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6331 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6334 tcg_int
= tcg_extend
;
6338 case 1: /* float64 */
6339 tcg_double
= tcg_temp_new_i64();
6341 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6342 tcg_shift
, tcg_fpstatus
);
6344 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6345 tcg_shift
, tcg_fpstatus
);
6347 write_fp_dreg(s
, rd
, tcg_double
);
6348 tcg_temp_free_i64(tcg_double
);
6351 case 0: /* float32 */
6352 tcg_single
= tcg_temp_new_i32();
6354 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6355 tcg_shift
, tcg_fpstatus
);
6357 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6358 tcg_shift
, tcg_fpstatus
);
6360 write_fp_sreg(s
, rd
, tcg_single
);
6361 tcg_temp_free_i32(tcg_single
);
6364 case 3: /* float16 */
6365 tcg_single
= tcg_temp_new_i32();
6367 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6368 tcg_shift
, tcg_fpstatus
);
6370 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6371 tcg_shift
, tcg_fpstatus
);
6373 write_fp_sreg(s
, rd
, tcg_single
);
6374 tcg_temp_free_i32(tcg_single
);
6378 g_assert_not_reached();
6381 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6384 if (extract32(opcode
, 2, 1)) {
6385 /* There are too many rounding modes to all fit into rmode,
6386 * so FCVTA[US] is a special case.
6388 rmode
= FPROUNDING_TIEAWAY
;
6391 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6393 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6396 case 1: /* float64 */
6397 tcg_double
= read_fp_dreg(s
, rn
);
6400 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6401 tcg_shift
, tcg_fpstatus
);
6403 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6404 tcg_shift
, tcg_fpstatus
);
6408 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6409 tcg_shift
, tcg_fpstatus
);
6411 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6412 tcg_shift
, tcg_fpstatus
);
6416 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6418 tcg_temp_free_i64(tcg_double
);
6421 case 0: /* float32 */
6422 tcg_single
= read_fp_sreg(s
, rn
);
6425 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6426 tcg_shift
, tcg_fpstatus
);
6428 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6429 tcg_shift
, tcg_fpstatus
);
6432 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6434 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6435 tcg_shift
, tcg_fpstatus
);
6437 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6438 tcg_shift
, tcg_fpstatus
);
6440 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6441 tcg_temp_free_i32(tcg_dest
);
6443 tcg_temp_free_i32(tcg_single
);
6446 case 3: /* float16 */
6447 tcg_single
= read_fp_sreg(s
, rn
);
6450 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6451 tcg_shift
, tcg_fpstatus
);
6453 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6454 tcg_shift
, tcg_fpstatus
);
6457 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6459 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6460 tcg_shift
, tcg_fpstatus
);
6462 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6463 tcg_shift
, tcg_fpstatus
);
6465 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6466 tcg_temp_free_i32(tcg_dest
);
6468 tcg_temp_free_i32(tcg_single
);
6472 g_assert_not_reached();
6475 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6476 tcg_temp_free_i32(tcg_rmode
);
6479 tcg_temp_free_ptr(tcg_fpstatus
);
6480 tcg_temp_free_i32(tcg_shift
);
6483 /* Floating point <-> fixed point conversions
6484 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6485 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6486 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6487 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6489 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6491 int rd
= extract32(insn
, 0, 5);
6492 int rn
= extract32(insn
, 5, 5);
6493 int scale
= extract32(insn
, 10, 6);
6494 int opcode
= extract32(insn
, 16, 3);
6495 int rmode
= extract32(insn
, 19, 2);
6496 int type
= extract32(insn
, 22, 2);
6497 bool sbit
= extract32(insn
, 29, 1);
6498 bool sf
= extract32(insn
, 31, 1);
6501 if (sbit
|| (!sf
&& scale
< 32)) {
6502 unallocated_encoding(s
);
6507 case 0: /* float32 */
6508 case 1: /* float64 */
6510 case 3: /* float16 */
6511 if (dc_isar_feature(aa64_fp16
, s
)) {
6516 unallocated_encoding(s
);
6520 switch ((rmode
<< 3) | opcode
) {
6521 case 0x2: /* SCVTF */
6522 case 0x3: /* UCVTF */
6525 case 0x18: /* FCVTZS */
6526 case 0x19: /* FCVTZU */
6530 unallocated_encoding(s
);
6534 if (!fp_access_check(s
)) {
6538 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6541 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6543 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6544 * without conversion.
6548 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6554 tmp
= tcg_temp_new_i64();
6555 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6556 write_fp_dreg(s
, rd
, tmp
);
6557 tcg_temp_free_i64(tmp
);
6561 write_fp_dreg(s
, rd
, tcg_rn
);
6564 /* 64 bit to top half. */
6565 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6566 clear_vec_high(s
, true, rd
);
6570 tmp
= tcg_temp_new_i64();
6571 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6572 write_fp_dreg(s
, rd
, tmp
);
6573 tcg_temp_free_i64(tmp
);
6576 g_assert_not_reached();
6579 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6584 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6588 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6591 /* 64 bits from top half */
6592 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6596 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6599 g_assert_not_reached();
6604 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6606 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6607 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6609 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6611 tcg_temp_free_ptr(fpstatus
);
6613 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6614 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6615 tcg_gen_movi_i32(cpu_CF
, 0);
6616 tcg_gen_movi_i32(cpu_NF
, 0);
6617 tcg_gen_movi_i32(cpu_VF
, 0);
6619 tcg_temp_free_i64(t
);
6622 /* Floating point <-> integer conversions
6623 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6624 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6625 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6626 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6628 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6630 int rd
= extract32(insn
, 0, 5);
6631 int rn
= extract32(insn
, 5, 5);
6632 int opcode
= extract32(insn
, 16, 3);
6633 int rmode
= extract32(insn
, 19, 2);
6634 int type
= extract32(insn
, 22, 2);
6635 bool sbit
= extract32(insn
, 29, 1);
6636 bool sf
= extract32(insn
, 31, 1);
6640 goto do_unallocated
;
6648 case 4: /* FCVTAS */
6649 case 5: /* FCVTAU */
6651 goto do_unallocated
;
6654 case 0: /* FCVT[NPMZ]S */
6655 case 1: /* FCVT[NPMZ]U */
6657 case 0: /* float32 */
6658 case 1: /* float64 */
6660 case 3: /* float16 */
6661 if (!dc_isar_feature(aa64_fp16
, s
)) {
6662 goto do_unallocated
;
6666 goto do_unallocated
;
6668 if (!fp_access_check(s
)) {
6671 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6675 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6676 case 0b01100110: /* FMOV half <-> 32-bit int */
6678 case 0b11100110: /* FMOV half <-> 64-bit int */
6680 if (!dc_isar_feature(aa64_fp16
, s
)) {
6681 goto do_unallocated
;
6684 case 0b00000110: /* FMOV 32-bit */
6686 case 0b10100110: /* FMOV 64-bit */
6688 case 0b11001110: /* FMOV top half of 128-bit */
6690 if (!fp_access_check(s
)) {
6694 handle_fmov(s
, rd
, rn
, type
, itof
);
6697 case 0b00111110: /* FJCVTZS */
6698 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6699 goto do_unallocated
;
6700 } else if (fp_access_check(s
)) {
6701 handle_fjcvtzs(s
, rd
, rn
);
6707 unallocated_encoding(s
);
6714 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6715 * 31 30 29 28 25 24 0
6716 * +---+---+---+---------+-----------------------------+
6717 * | | 0 | | 1 1 1 1 | |
6718 * +---+---+---+---------+-----------------------------+
6720 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6722 if (extract32(insn
, 24, 1)) {
6723 /* Floating point data-processing (3 source) */
6724 disas_fp_3src(s
, insn
);
6725 } else if (extract32(insn
, 21, 1) == 0) {
6726 /* Floating point to fixed point conversions */
6727 disas_fp_fixed_conv(s
, insn
);
6729 switch (extract32(insn
, 10, 2)) {
6731 /* Floating point conditional compare */
6732 disas_fp_ccomp(s
, insn
);
6735 /* Floating point data-processing (2 source) */
6736 disas_fp_2src(s
, insn
);
6739 /* Floating point conditional select */
6740 disas_fp_csel(s
, insn
);
6743 switch (ctz32(extract32(insn
, 12, 4))) {
6744 case 0: /* [15:12] == xxx1 */
6745 /* Floating point immediate */
6746 disas_fp_imm(s
, insn
);
6748 case 1: /* [15:12] == xx10 */
6749 /* Floating point compare */
6750 disas_fp_compare(s
, insn
);
6752 case 2: /* [15:12] == x100 */
6753 /* Floating point data-processing (1 source) */
6754 disas_fp_1src(s
, insn
);
6756 case 3: /* [15:12] == 1000 */
6757 unallocated_encoding(s
);
6759 default: /* [15:12] == 0000 */
6760 /* Floating point <-> integer conversions */
6761 disas_fp_int_conv(s
, insn
);
6769 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6772 /* Extract 64 bits from the middle of two concatenated 64 bit
6773 * vector register slices left:right. The extracted bits start
6774 * at 'pos' bits into the right (least significant) side.
6775 * We return the result in tcg_right, and guarantee not to
6778 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6779 assert(pos
> 0 && pos
< 64);
6781 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6782 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6783 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6785 tcg_temp_free_i64(tcg_tmp
);
6789 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6790 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6791 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6792 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6794 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6796 int is_q
= extract32(insn
, 30, 1);
6797 int op2
= extract32(insn
, 22, 2);
6798 int imm4
= extract32(insn
, 11, 4);
6799 int rm
= extract32(insn
, 16, 5);
6800 int rn
= extract32(insn
, 5, 5);
6801 int rd
= extract32(insn
, 0, 5);
6802 int pos
= imm4
<< 3;
6803 TCGv_i64 tcg_resl
, tcg_resh
;
6805 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6806 unallocated_encoding(s
);
6810 if (!fp_access_check(s
)) {
6814 tcg_resh
= tcg_temp_new_i64();
6815 tcg_resl
= tcg_temp_new_i64();
6817 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6818 * either extracting 128 bits from a 128:128 concatenation, or
6819 * extracting 64 bits from a 64:64 concatenation.
6822 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6824 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6825 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6827 tcg_gen_movi_i64(tcg_resh
, 0);
6834 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6835 EltPosns
*elt
= eltposns
;
6842 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6844 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6847 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6848 tcg_hh
= tcg_temp_new_i64();
6849 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6850 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6851 tcg_temp_free_i64(tcg_hh
);
6855 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6856 tcg_temp_free_i64(tcg_resl
);
6857 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6858 tcg_temp_free_i64(tcg_resh
);
6862 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6863 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6864 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6865 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6867 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6869 int op2
= extract32(insn
, 22, 2);
6870 int is_q
= extract32(insn
, 30, 1);
6871 int rm
= extract32(insn
, 16, 5);
6872 int rn
= extract32(insn
, 5, 5);
6873 int rd
= extract32(insn
, 0, 5);
6874 int is_tblx
= extract32(insn
, 12, 1);
6875 int len
= extract32(insn
, 13, 2);
6876 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6877 TCGv_i32 tcg_regno
, tcg_numregs
;
6880 unallocated_encoding(s
);
6884 if (!fp_access_check(s
)) {
6888 /* This does a table lookup: for every byte element in the input
6889 * we index into a table formed from up to four vector registers,
6890 * and then the output is the result of the lookups. Our helper
6891 * function does the lookup operation for a single 64 bit part of
6894 tcg_resl
= tcg_temp_new_i64();
6895 tcg_resh
= tcg_temp_new_i64();
6898 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6900 tcg_gen_movi_i64(tcg_resl
, 0);
6902 if (is_tblx
&& is_q
) {
6903 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6905 tcg_gen_movi_i64(tcg_resh
, 0);
6908 tcg_idx
= tcg_temp_new_i64();
6909 tcg_regno
= tcg_const_i32(rn
);
6910 tcg_numregs
= tcg_const_i32(len
+ 1);
6911 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6912 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6913 tcg_regno
, tcg_numregs
);
6915 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6916 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6917 tcg_regno
, tcg_numregs
);
6919 tcg_temp_free_i64(tcg_idx
);
6920 tcg_temp_free_i32(tcg_regno
);
6921 tcg_temp_free_i32(tcg_numregs
);
6923 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6924 tcg_temp_free_i64(tcg_resl
);
6925 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6926 tcg_temp_free_i64(tcg_resh
);
6930 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6931 * +---+---+-------------+------+---+------+---+------------------+------+
6932 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6933 * +---+---+-------------+------+---+------+---+------------------+------+
6935 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6937 int rd
= extract32(insn
, 0, 5);
6938 int rn
= extract32(insn
, 5, 5);
6939 int rm
= extract32(insn
, 16, 5);
6940 int size
= extract32(insn
, 22, 2);
6941 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6942 * bit 2 indicates 1 vs 2 variant of the insn.
6944 int opcode
= extract32(insn
, 12, 2);
6945 bool part
= extract32(insn
, 14, 1);
6946 bool is_q
= extract32(insn
, 30, 1);
6947 int esize
= 8 << size
;
6949 int datasize
= is_q
? 128 : 64;
6950 int elements
= datasize
/ esize
;
6951 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6953 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6954 unallocated_encoding(s
);
6958 if (!fp_access_check(s
)) {
6962 tcg_resl
= tcg_const_i64(0);
6963 tcg_resh
= tcg_const_i64(0);
6964 tcg_res
= tcg_temp_new_i64();
6966 for (i
= 0; i
< elements
; i
++) {
6968 case 1: /* UZP1/2 */
6970 int midpoint
= elements
/ 2;
6972 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6974 read_vec_element(s
, tcg_res
, rm
,
6975 2 * (i
- midpoint
) + part
, size
);
6979 case 2: /* TRN1/2 */
6981 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6983 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6986 case 3: /* ZIP1/2 */
6988 int base
= part
* elements
/ 2;
6990 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6992 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6997 g_assert_not_reached();
7002 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7003 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7005 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7006 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7010 tcg_temp_free_i64(tcg_res
);
7012 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7013 tcg_temp_free_i64(tcg_resl
);
7014 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7015 tcg_temp_free_i64(tcg_resh
);
7019 * do_reduction_op helper
7021 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7022 * important for correct NaN propagation that we do these
7023 * operations in exactly the order specified by the pseudocode.
7025 * This is a recursive function, TCG temps should be freed by the
7026 * calling function once it is done with the values.
7028 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7029 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7031 if (esize
== size
) {
7033 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7036 /* We should have one register left here */
7037 assert(ctpop8(vmap
) == 1);
7038 element
= ctz32(vmap
);
7039 assert(element
< 8);
7041 tcg_elem
= tcg_temp_new_i32();
7042 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7045 int bits
= size
/ 2;
7046 int shift
= ctpop8(vmap
) / 2;
7047 int vmap_lo
= (vmap
>> shift
) & vmap
;
7048 int vmap_hi
= (vmap
& ~vmap_lo
);
7049 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7051 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7052 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7053 tcg_res
= tcg_temp_new_i32();
7056 case 0x0c: /* fmaxnmv half-precision */
7057 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7059 case 0x0f: /* fmaxv half-precision */
7060 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7062 case 0x1c: /* fminnmv half-precision */
7063 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7065 case 0x1f: /* fminv half-precision */
7066 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7068 case 0x2c: /* fmaxnmv */
7069 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7071 case 0x2f: /* fmaxv */
7072 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7074 case 0x3c: /* fminnmv */
7075 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7077 case 0x3f: /* fminv */
7078 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7081 g_assert_not_reached();
7084 tcg_temp_free_i32(tcg_hi
);
7085 tcg_temp_free_i32(tcg_lo
);
7090 /* AdvSIMD across lanes
7091 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7092 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7093 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7094 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7096 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7098 int rd
= extract32(insn
, 0, 5);
7099 int rn
= extract32(insn
, 5, 5);
7100 int size
= extract32(insn
, 22, 2);
7101 int opcode
= extract32(insn
, 12, 5);
7102 bool is_q
= extract32(insn
, 30, 1);
7103 bool is_u
= extract32(insn
, 29, 1);
7105 bool is_min
= false;
7109 TCGv_i64 tcg_res
, tcg_elt
;
7112 case 0x1b: /* ADDV */
7114 unallocated_encoding(s
);
7118 case 0x3: /* SADDLV, UADDLV */
7119 case 0xa: /* SMAXV, UMAXV */
7120 case 0x1a: /* SMINV, UMINV */
7121 if (size
== 3 || (size
== 2 && !is_q
)) {
7122 unallocated_encoding(s
);
7126 case 0xc: /* FMAXNMV, FMINNMV */
7127 case 0xf: /* FMAXV, FMINV */
7128 /* Bit 1 of size field encodes min vs max and the actual size
7129 * depends on the encoding of the U bit. If not set (and FP16
7130 * enabled) then we do half-precision float instead of single
7133 is_min
= extract32(size
, 1, 1);
7135 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7137 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7138 unallocated_encoding(s
);
7145 unallocated_encoding(s
);
7149 if (!fp_access_check(s
)) {
7154 elements
= (is_q
? 128 : 64) / esize
;
7156 tcg_res
= tcg_temp_new_i64();
7157 tcg_elt
= tcg_temp_new_i64();
7159 /* These instructions operate across all lanes of a vector
7160 * to produce a single result. We can guarantee that a 64
7161 * bit intermediate is sufficient:
7162 * + for [US]ADDLV the maximum element size is 32 bits, and
7163 * the result type is 64 bits
7164 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7165 * same as the element size, which is 32 bits at most
7166 * For the integer operations we can choose to work at 64
7167 * or 32 bits and truncate at the end; for simplicity
7168 * we use 64 bits always. The floating point
7169 * ops do require 32 bit intermediates, though.
7172 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7174 for (i
= 1; i
< elements
; i
++) {
7175 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7178 case 0x03: /* SADDLV / UADDLV */
7179 case 0x1b: /* ADDV */
7180 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7182 case 0x0a: /* SMAXV / UMAXV */
7184 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7186 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7189 case 0x1a: /* SMINV / UMINV */
7191 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7193 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7197 g_assert_not_reached();
7202 /* Floating point vector reduction ops which work across 32
7203 * bit (single) or 16 bit (half-precision) intermediates.
7204 * Note that correct NaN propagation requires that we do these
7205 * operations in exactly the order specified by the pseudocode.
7207 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7208 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7209 int vmap
= (1 << elements
) - 1;
7210 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7211 (is_q
? 128 : 64), vmap
, fpst
);
7212 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7213 tcg_temp_free_i32(tcg_res32
);
7214 tcg_temp_free_ptr(fpst
);
7217 tcg_temp_free_i64(tcg_elt
);
7219 /* Now truncate the result to the width required for the final output */
7220 if (opcode
== 0x03) {
7221 /* SADDLV, UADDLV: result is 2*esize */
7227 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7230 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7233 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7238 g_assert_not_reached();
7241 write_fp_dreg(s
, rd
, tcg_res
);
7242 tcg_temp_free_i64(tcg_res
);
7245 /* DUP (Element, Vector)
7247 * 31 30 29 21 20 16 15 10 9 5 4 0
7248 * +---+---+-------------------+--------+-------------+------+------+
7249 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7250 * +---+---+-------------------+--------+-------------+------+------+
7252 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7254 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7257 int size
= ctz32(imm5
);
7258 int index
= imm5
>> (size
+ 1);
7260 if (size
> 3 || (size
== 3 && !is_q
)) {
7261 unallocated_encoding(s
);
7265 if (!fp_access_check(s
)) {
7269 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7270 vec_reg_offset(s
, rn
, index
, size
),
7271 is_q
? 16 : 8, vec_full_reg_size(s
));
7274 /* DUP (element, scalar)
7275 * 31 21 20 16 15 10 9 5 4 0
7276 * +-----------------------+--------+-------------+------+------+
7277 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7278 * +-----------------------+--------+-------------+------+------+
7280 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7283 int size
= ctz32(imm5
);
7288 unallocated_encoding(s
);
7292 if (!fp_access_check(s
)) {
7296 index
= imm5
>> (size
+ 1);
7298 /* This instruction just extracts the specified element and
7299 * zero-extends it into the bottom of the destination register.
7301 tmp
= tcg_temp_new_i64();
7302 read_vec_element(s
, tmp
, rn
, index
, size
);
7303 write_fp_dreg(s
, rd
, tmp
);
7304 tcg_temp_free_i64(tmp
);
7309 * 31 30 29 21 20 16 15 10 9 5 4 0
7310 * +---+---+-------------------+--------+-------------+------+------+
7311 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7312 * +---+---+-------------------+--------+-------------+------+------+
7314 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7316 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7319 int size
= ctz32(imm5
);
7320 uint32_t dofs
, oprsz
, maxsz
;
7322 if (size
> 3 || ((size
== 3) && !is_q
)) {
7323 unallocated_encoding(s
);
7327 if (!fp_access_check(s
)) {
7331 dofs
= vec_full_reg_offset(s
, rd
);
7332 oprsz
= is_q
? 16 : 8;
7333 maxsz
= vec_full_reg_size(s
);
7335 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7340 * 31 21 20 16 15 14 11 10 9 5 4 0
7341 * +-----------------------+--------+------------+---+------+------+
7342 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7343 * +-----------------------+--------+------------+---+------+------+
7345 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7346 * index: encoded in imm5<4:size+1>
7348 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7351 int size
= ctz32(imm5
);
7352 int src_index
, dst_index
;
7356 unallocated_encoding(s
);
7360 if (!fp_access_check(s
)) {
7364 dst_index
= extract32(imm5
, 1+size
, 5);
7365 src_index
= extract32(imm4
, size
, 4);
7367 tmp
= tcg_temp_new_i64();
7369 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7370 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7372 tcg_temp_free_i64(tmp
);
7378 * 31 21 20 16 15 10 9 5 4 0
7379 * +-----------------------+--------+-------------+------+------+
7380 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7381 * +-----------------------+--------+-------------+------+------+
7383 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7384 * index: encoded in imm5<4:size+1>
7386 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7388 int size
= ctz32(imm5
);
7392 unallocated_encoding(s
);
7396 if (!fp_access_check(s
)) {
7400 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7401 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7408 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7409 * +---+---+-------------------+--------+-------------+------+------+
7410 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7411 * +---+---+-------------------+--------+-------------+------+------+
7413 * U: unsigned when set
7414 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7416 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7417 int rn
, int rd
, int imm5
)
7419 int size
= ctz32(imm5
);
7423 /* Check for UnallocatedEncodings */
7425 if (size
> 2 || (size
== 2 && !is_q
)) {
7426 unallocated_encoding(s
);
7431 || (size
< 3 && is_q
)
7432 || (size
== 3 && !is_q
)) {
7433 unallocated_encoding(s
);
7438 if (!fp_access_check(s
)) {
7442 element
= extract32(imm5
, 1+size
, 4);
7444 tcg_rd
= cpu_reg(s
, rd
);
7445 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7446 if (is_signed
&& !is_q
) {
7447 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7452 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7453 * +---+---+----+-----------------+------+---+------+---+------+------+
7454 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7455 * +---+---+----+-----------------+------+---+------+---+------+------+
7457 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7459 int rd
= extract32(insn
, 0, 5);
7460 int rn
= extract32(insn
, 5, 5);
7461 int imm4
= extract32(insn
, 11, 4);
7462 int op
= extract32(insn
, 29, 1);
7463 int is_q
= extract32(insn
, 30, 1);
7464 int imm5
= extract32(insn
, 16, 5);
7469 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7471 unallocated_encoding(s
);
7476 /* DUP (element - vector) */
7477 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7481 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7486 handle_simd_insg(s
, rd
, rn
, imm5
);
7488 unallocated_encoding(s
);
7493 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7494 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7497 unallocated_encoding(s
);
7503 /* AdvSIMD modified immediate
7504 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7505 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7506 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7507 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7509 * There are a number of operations that can be carried out here:
7510 * MOVI - move (shifted) imm into register
7511 * MVNI - move inverted (shifted) imm into register
7512 * ORR - bitwise OR of (shifted) imm with register
7513 * BIC - bitwise clear of (shifted) imm with register
7514 * With ARMv8.2 we also have:
7515 * FMOV half-precision
7517 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7519 int rd
= extract32(insn
, 0, 5);
7520 int cmode
= extract32(insn
, 12, 4);
7521 int cmode_3_1
= extract32(cmode
, 1, 3);
7522 int cmode_0
= extract32(cmode
, 0, 1);
7523 int o2
= extract32(insn
, 11, 1);
7524 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7525 bool is_neg
= extract32(insn
, 29, 1);
7526 bool is_q
= extract32(insn
, 30, 1);
7529 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7530 /* Check for FMOV (vector, immediate) - half-precision */
7531 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7532 unallocated_encoding(s
);
7537 if (!fp_access_check(s
)) {
7541 /* See AdvSIMDExpandImm() in ARM ARM */
7542 switch (cmode_3_1
) {
7543 case 0: /* Replicate(Zeros(24):imm8, 2) */
7544 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7545 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7546 case 3: /* Replicate(imm8:Zeros(24), 2) */
7548 int shift
= cmode_3_1
* 8;
7549 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7552 case 4: /* Replicate(Zeros(8):imm8, 4) */
7553 case 5: /* Replicate(imm8:Zeros(8), 4) */
7555 int shift
= (cmode_3_1
& 0x1) * 8;
7556 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7561 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7562 imm
= (abcdefgh
<< 16) | 0xffff;
7564 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7565 imm
= (abcdefgh
<< 8) | 0xff;
7567 imm
= bitfield_replicate(imm
, 32);
7570 if (!cmode_0
&& !is_neg
) {
7571 imm
= bitfield_replicate(abcdefgh
, 8);
7572 } else if (!cmode_0
&& is_neg
) {
7575 for (i
= 0; i
< 8; i
++) {
7576 if ((abcdefgh
) & (1 << i
)) {
7577 imm
|= 0xffULL
<< (i
* 8);
7580 } else if (cmode_0
) {
7582 imm
= (abcdefgh
& 0x3f) << 48;
7583 if (abcdefgh
& 0x80) {
7584 imm
|= 0x8000000000000000ULL
;
7586 if (abcdefgh
& 0x40) {
7587 imm
|= 0x3fc0000000000000ULL
;
7589 imm
|= 0x4000000000000000ULL
;
7593 /* FMOV (vector, immediate) - half-precision */
7594 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7595 /* now duplicate across the lanes */
7596 imm
= bitfield_replicate(imm
, 16);
7598 imm
= (abcdefgh
& 0x3f) << 19;
7599 if (abcdefgh
& 0x80) {
7602 if (abcdefgh
& 0x40) {
7613 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7614 g_assert_not_reached();
7617 if (cmode_3_1
!= 7 && is_neg
) {
7621 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7622 /* MOVI or MVNI, with MVNI negation handled above. */
7623 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7624 vec_full_reg_size(s
), imm
);
7626 /* ORR or BIC, with BIC negation to AND handled above. */
7628 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7630 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7635 /* AdvSIMD scalar copy
7636 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7637 * +-----+----+-----------------+------+---+------+---+------+------+
7638 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7639 * +-----+----+-----------------+------+---+------+---+------+------+
7641 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7643 int rd
= extract32(insn
, 0, 5);
7644 int rn
= extract32(insn
, 5, 5);
7645 int imm4
= extract32(insn
, 11, 4);
7646 int imm5
= extract32(insn
, 16, 5);
7647 int op
= extract32(insn
, 29, 1);
7649 if (op
!= 0 || imm4
!= 0) {
7650 unallocated_encoding(s
);
7654 /* DUP (element, scalar) */
7655 handle_simd_dupes(s
, rd
, rn
, imm5
);
7658 /* AdvSIMD scalar pairwise
7659 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7660 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7661 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7662 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7664 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7666 int u
= extract32(insn
, 29, 1);
7667 int size
= extract32(insn
, 22, 2);
7668 int opcode
= extract32(insn
, 12, 5);
7669 int rn
= extract32(insn
, 5, 5);
7670 int rd
= extract32(insn
, 0, 5);
7673 /* For some ops (the FP ones), size[1] is part of the encoding.
7674 * For ADDP strictly it is not but size[1] is always 1 for valid
7677 opcode
|= (extract32(size
, 1, 1) << 5);
7680 case 0x3b: /* ADDP */
7681 if (u
|| size
!= 3) {
7682 unallocated_encoding(s
);
7685 if (!fp_access_check(s
)) {
7691 case 0xc: /* FMAXNMP */
7692 case 0xd: /* FADDP */
7693 case 0xf: /* FMAXP */
7694 case 0x2c: /* FMINNMP */
7695 case 0x2f: /* FMINP */
7696 /* FP op, size[0] is 32 or 64 bit*/
7698 if (!dc_isar_feature(aa64_fp16
, s
)) {
7699 unallocated_encoding(s
);
7705 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7708 if (!fp_access_check(s
)) {
7712 fpst
= get_fpstatus_ptr(size
== MO_16
);
7715 unallocated_encoding(s
);
7719 if (size
== MO_64
) {
7720 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7721 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7722 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7724 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7725 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7728 case 0x3b: /* ADDP */
7729 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7731 case 0xc: /* FMAXNMP */
7732 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7734 case 0xd: /* FADDP */
7735 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7737 case 0xf: /* FMAXP */
7738 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7740 case 0x2c: /* FMINNMP */
7741 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7743 case 0x2f: /* FMINP */
7744 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7747 g_assert_not_reached();
7750 write_fp_dreg(s
, rd
, tcg_res
);
7752 tcg_temp_free_i64(tcg_op1
);
7753 tcg_temp_free_i64(tcg_op2
);
7754 tcg_temp_free_i64(tcg_res
);
7756 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7757 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7758 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7760 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7761 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7763 if (size
== MO_16
) {
7765 case 0xc: /* FMAXNMP */
7766 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7768 case 0xd: /* FADDP */
7769 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7771 case 0xf: /* FMAXP */
7772 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7774 case 0x2c: /* FMINNMP */
7775 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7777 case 0x2f: /* FMINP */
7778 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7781 g_assert_not_reached();
7785 case 0xc: /* FMAXNMP */
7786 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7788 case 0xd: /* FADDP */
7789 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7791 case 0xf: /* FMAXP */
7792 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7794 case 0x2c: /* FMINNMP */
7795 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7797 case 0x2f: /* FMINP */
7798 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7801 g_assert_not_reached();
7805 write_fp_sreg(s
, rd
, tcg_res
);
7807 tcg_temp_free_i32(tcg_op1
);
7808 tcg_temp_free_i32(tcg_op2
);
7809 tcg_temp_free_i32(tcg_res
);
7813 tcg_temp_free_ptr(fpst
);
7818 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7820 * This code is handles the common shifting code and is used by both
7821 * the vector and scalar code.
7823 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7824 TCGv_i64 tcg_rnd
, bool accumulate
,
7825 bool is_u
, int size
, int shift
)
7827 bool extended_result
= false;
7828 bool round
= tcg_rnd
!= NULL
;
7830 TCGv_i64 tcg_src_hi
;
7832 if (round
&& size
== 3) {
7833 extended_result
= true;
7834 ext_lshift
= 64 - shift
;
7835 tcg_src_hi
= tcg_temp_new_i64();
7836 } else if (shift
== 64) {
7837 if (!accumulate
&& is_u
) {
7838 /* result is zero */
7839 tcg_gen_movi_i64(tcg_res
, 0);
7844 /* Deal with the rounding step */
7846 if (extended_result
) {
7847 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7849 /* take care of sign extending tcg_res */
7850 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7851 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7852 tcg_src
, tcg_src_hi
,
7855 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7859 tcg_temp_free_i64(tcg_zero
);
7861 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7865 /* Now do the shift right */
7866 if (round
&& extended_result
) {
7867 /* extended case, >64 bit precision required */
7868 if (ext_lshift
== 0) {
7869 /* special case, only high bits matter */
7870 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7872 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7873 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7874 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7879 /* essentially shifting in 64 zeros */
7880 tcg_gen_movi_i64(tcg_src
, 0);
7882 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7886 /* effectively extending the sign-bit */
7887 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7889 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7895 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7897 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7900 if (extended_result
) {
7901 tcg_temp_free_i64(tcg_src_hi
);
7905 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7906 static void handle_scalar_simd_shri(DisasContext
*s
,
7907 bool is_u
, int immh
, int immb
,
7908 int opcode
, int rn
, int rd
)
7911 int immhb
= immh
<< 3 | immb
;
7912 int shift
= 2 * (8 << size
) - immhb
;
7913 bool accumulate
= false;
7915 bool insert
= false;
7920 if (!extract32(immh
, 3, 1)) {
7921 unallocated_encoding(s
);
7925 if (!fp_access_check(s
)) {
7930 case 0x02: /* SSRA / USRA (accumulate) */
7933 case 0x04: /* SRSHR / URSHR (rounding) */
7936 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7937 accumulate
= round
= true;
7939 case 0x08: /* SRI */
7945 uint64_t round_const
= 1ULL << (shift
- 1);
7946 tcg_round
= tcg_const_i64(round_const
);
7951 tcg_rn
= read_fp_dreg(s
, rn
);
7952 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7955 /* shift count same as element size is valid but does nothing;
7956 * special case to avoid potential shift by 64.
7958 int esize
= 8 << size
;
7959 if (shift
!= esize
) {
7960 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7961 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7964 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7965 accumulate
, is_u
, size
, shift
);
7968 write_fp_dreg(s
, rd
, tcg_rd
);
7970 tcg_temp_free_i64(tcg_rn
);
7971 tcg_temp_free_i64(tcg_rd
);
7973 tcg_temp_free_i64(tcg_round
);
7977 /* SHL/SLI - Scalar shift left */
7978 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7979 int immh
, int immb
, int opcode
,
7982 int size
= 32 - clz32(immh
) - 1;
7983 int immhb
= immh
<< 3 | immb
;
7984 int shift
= immhb
- (8 << size
);
7985 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7986 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7988 if (!extract32(immh
, 3, 1)) {
7989 unallocated_encoding(s
);
7993 if (!fp_access_check(s
)) {
7997 tcg_rn
= read_fp_dreg(s
, rn
);
7998 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8001 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8003 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8006 write_fp_dreg(s
, rd
, tcg_rd
);
8008 tcg_temp_free_i64(tcg_rn
);
8009 tcg_temp_free_i64(tcg_rd
);
8012 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8013 * (signed/unsigned) narrowing */
8014 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8015 bool is_u_shift
, bool is_u_narrow
,
8016 int immh
, int immb
, int opcode
,
8019 int immhb
= immh
<< 3 | immb
;
8020 int size
= 32 - clz32(immh
) - 1;
8021 int esize
= 8 << size
;
8022 int shift
= (2 * esize
) - immhb
;
8023 int elements
= is_scalar
? 1 : (64 / esize
);
8024 bool round
= extract32(opcode
, 0, 1);
8025 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8026 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8027 TCGv_i32 tcg_rd_narrowed
;
8030 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8031 { gen_helper_neon_narrow_sat_s8
,
8032 gen_helper_neon_unarrow_sat8
},
8033 { gen_helper_neon_narrow_sat_s16
,
8034 gen_helper_neon_unarrow_sat16
},
8035 { gen_helper_neon_narrow_sat_s32
,
8036 gen_helper_neon_unarrow_sat32
},
8039 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8040 gen_helper_neon_narrow_sat_u8
,
8041 gen_helper_neon_narrow_sat_u16
,
8042 gen_helper_neon_narrow_sat_u32
,
8045 NeonGenNarrowEnvFn
*narrowfn
;
8051 if (extract32(immh
, 3, 1)) {
8052 unallocated_encoding(s
);
8056 if (!fp_access_check(s
)) {
8061 narrowfn
= unsigned_narrow_fns
[size
];
8063 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8066 tcg_rn
= tcg_temp_new_i64();
8067 tcg_rd
= tcg_temp_new_i64();
8068 tcg_rd_narrowed
= tcg_temp_new_i32();
8069 tcg_final
= tcg_const_i64(0);
8072 uint64_t round_const
= 1ULL << (shift
- 1);
8073 tcg_round
= tcg_const_i64(round_const
);
8078 for (i
= 0; i
< elements
; i
++) {
8079 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8080 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8081 false, is_u_shift
, size
+1, shift
);
8082 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8083 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8084 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8088 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8090 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8094 tcg_temp_free_i64(tcg_round
);
8096 tcg_temp_free_i64(tcg_rn
);
8097 tcg_temp_free_i64(tcg_rd
);
8098 tcg_temp_free_i32(tcg_rd_narrowed
);
8099 tcg_temp_free_i64(tcg_final
);
8101 clear_vec_high(s
, is_q
, rd
);
8104 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8105 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8106 bool src_unsigned
, bool dst_unsigned
,
8107 int immh
, int immb
, int rn
, int rd
)
8109 int immhb
= immh
<< 3 | immb
;
8110 int size
= 32 - clz32(immh
) - 1;
8111 int shift
= immhb
- (8 << size
);
8115 assert(!(scalar
&& is_q
));
8118 if (!is_q
&& extract32(immh
, 3, 1)) {
8119 unallocated_encoding(s
);
8123 /* Since we use the variable-shift helpers we must
8124 * replicate the shift count into each element of
8125 * the tcg_shift value.
8129 shift
|= shift
<< 8;
8132 shift
|= shift
<< 16;
8138 g_assert_not_reached();
8142 if (!fp_access_check(s
)) {
8147 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8148 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8149 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8150 { NULL
, gen_helper_neon_qshl_u64
},
8152 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8153 int maxpass
= is_q
? 2 : 1;
8155 for (pass
= 0; pass
< maxpass
; pass
++) {
8156 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8158 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8159 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8160 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8162 tcg_temp_free_i64(tcg_op
);
8164 tcg_temp_free_i64(tcg_shift
);
8165 clear_vec_high(s
, is_q
, rd
);
8167 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8168 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8170 { gen_helper_neon_qshl_s8
,
8171 gen_helper_neon_qshl_s16
,
8172 gen_helper_neon_qshl_s32
},
8173 { gen_helper_neon_qshlu_s8
,
8174 gen_helper_neon_qshlu_s16
,
8175 gen_helper_neon_qshlu_s32
}
8177 { NULL
, NULL
, NULL
},
8178 { gen_helper_neon_qshl_u8
,
8179 gen_helper_neon_qshl_u16
,
8180 gen_helper_neon_qshl_u32
}
8183 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8184 TCGMemOp memop
= scalar
? size
: MO_32
;
8185 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8187 for (pass
= 0; pass
< maxpass
; pass
++) {
8188 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8190 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8191 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8195 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8198 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8203 g_assert_not_reached();
8205 write_fp_sreg(s
, rd
, tcg_op
);
8207 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8210 tcg_temp_free_i32(tcg_op
);
8212 tcg_temp_free_i32(tcg_shift
);
8215 clear_vec_high(s
, is_q
, rd
);
8220 /* Common vector code for handling integer to FP conversion */
8221 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8222 int elements
, int is_signed
,
8223 int fracbits
, int size
)
8225 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8226 TCGv_i32 tcg_shift
= NULL
;
8228 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8231 if (fracbits
|| size
== MO_64
) {
8232 tcg_shift
= tcg_const_i32(fracbits
);
8235 if (size
== MO_64
) {
8236 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8237 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8239 for (pass
= 0; pass
< elements
; pass
++) {
8240 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8243 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8244 tcg_shift
, tcg_fpst
);
8246 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8247 tcg_shift
, tcg_fpst
);
8249 if (elements
== 1) {
8250 write_fp_dreg(s
, rd
, tcg_double
);
8252 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8256 tcg_temp_free_i64(tcg_int64
);
8257 tcg_temp_free_i64(tcg_double
);
8260 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8261 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8263 for (pass
= 0; pass
< elements
; pass
++) {
8264 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8270 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8271 tcg_shift
, tcg_fpst
);
8273 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8274 tcg_shift
, tcg_fpst
);
8278 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8280 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8287 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8288 tcg_shift
, tcg_fpst
);
8290 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8291 tcg_shift
, tcg_fpst
);
8295 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8297 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8302 g_assert_not_reached();
8305 if (elements
== 1) {
8306 write_fp_sreg(s
, rd
, tcg_float
);
8308 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8312 tcg_temp_free_i32(tcg_int32
);
8313 tcg_temp_free_i32(tcg_float
);
8316 tcg_temp_free_ptr(tcg_fpst
);
8318 tcg_temp_free_i32(tcg_shift
);
8321 clear_vec_high(s
, elements
<< size
== 16, rd
);
8324 /* UCVTF/SCVTF - Integer to FP conversion */
8325 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8326 bool is_q
, bool is_u
,
8327 int immh
, int immb
, int opcode
,
8330 int size
, elements
, fracbits
;
8331 int immhb
= immh
<< 3 | immb
;
8335 if (!is_scalar
&& !is_q
) {
8336 unallocated_encoding(s
);
8339 } else if (immh
& 4) {
8341 } else if (immh
& 2) {
8343 if (!dc_isar_feature(aa64_fp16
, s
)) {
8344 unallocated_encoding(s
);
8348 /* immh == 0 would be a failure of the decode logic */
8349 g_assert(immh
== 1);
8350 unallocated_encoding(s
);
8357 elements
= (8 << is_q
) >> size
;
8359 fracbits
= (16 << size
) - immhb
;
8361 if (!fp_access_check(s
)) {
8365 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8368 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8369 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8370 bool is_q
, bool is_u
,
8371 int immh
, int immb
, int rn
, int rd
)
8373 int immhb
= immh
<< 3 | immb
;
8374 int pass
, size
, fracbits
;
8375 TCGv_ptr tcg_fpstatus
;
8376 TCGv_i32 tcg_rmode
, tcg_shift
;
8380 if (!is_scalar
&& !is_q
) {
8381 unallocated_encoding(s
);
8384 } else if (immh
& 0x4) {
8386 } else if (immh
& 0x2) {
8388 if (!dc_isar_feature(aa64_fp16
, s
)) {
8389 unallocated_encoding(s
);
8393 /* Should have split out AdvSIMD modified immediate earlier. */
8395 unallocated_encoding(s
);
8399 if (!fp_access_check(s
)) {
8403 assert(!(is_scalar
&& is_q
));
8405 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8406 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8407 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8408 fracbits
= (16 << size
) - immhb
;
8409 tcg_shift
= tcg_const_i32(fracbits
);
8411 if (size
== MO_64
) {
8412 int maxpass
= is_scalar
? 1 : 2;
8414 for (pass
= 0; pass
< maxpass
; pass
++) {
8415 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8417 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8419 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8421 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8423 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8424 tcg_temp_free_i64(tcg_op
);
8426 clear_vec_high(s
, is_q
, rd
);
8428 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8429 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8434 fn
= gen_helper_vfp_touhh
;
8436 fn
= gen_helper_vfp_toshh
;
8441 fn
= gen_helper_vfp_touls
;
8443 fn
= gen_helper_vfp_tosls
;
8447 g_assert_not_reached();
8450 for (pass
= 0; pass
< maxpass
; pass
++) {
8451 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8453 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8454 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8456 write_fp_sreg(s
, rd
, tcg_op
);
8458 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8460 tcg_temp_free_i32(tcg_op
);
8463 clear_vec_high(s
, is_q
, rd
);
8467 tcg_temp_free_ptr(tcg_fpstatus
);
8468 tcg_temp_free_i32(tcg_shift
);
8469 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8470 tcg_temp_free_i32(tcg_rmode
);
8473 /* AdvSIMD scalar shift by immediate
8474 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8475 * +-----+---+-------------+------+------+--------+---+------+------+
8476 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8477 * +-----+---+-------------+------+------+--------+---+------+------+
8479 * This is the scalar version so it works on a fixed sized registers
8481 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8483 int rd
= extract32(insn
, 0, 5);
8484 int rn
= extract32(insn
, 5, 5);
8485 int opcode
= extract32(insn
, 11, 5);
8486 int immb
= extract32(insn
, 16, 3);
8487 int immh
= extract32(insn
, 19, 4);
8488 bool is_u
= extract32(insn
, 29, 1);
8491 unallocated_encoding(s
);
8496 case 0x08: /* SRI */
8498 unallocated_encoding(s
);
8502 case 0x00: /* SSHR / USHR */
8503 case 0x02: /* SSRA / USRA */
8504 case 0x04: /* SRSHR / URSHR */
8505 case 0x06: /* SRSRA / URSRA */
8506 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8508 case 0x0a: /* SHL / SLI */
8509 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8511 case 0x1c: /* SCVTF, UCVTF */
8512 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8515 case 0x10: /* SQSHRUN, SQSHRUN2 */
8516 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8518 unallocated_encoding(s
);
8521 handle_vec_simd_sqshrn(s
, true, false, false, true,
8522 immh
, immb
, opcode
, rn
, rd
);
8524 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8525 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8526 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8527 immh
, immb
, opcode
, rn
, rd
);
8529 case 0xc: /* SQSHLU */
8531 unallocated_encoding(s
);
8534 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8536 case 0xe: /* SQSHL, UQSHL */
8537 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8539 case 0x1f: /* FCVTZS, FCVTZU */
8540 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8543 unallocated_encoding(s
);
8548 /* AdvSIMD scalar three different
8549 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8550 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8551 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8552 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8554 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8556 bool is_u
= extract32(insn
, 29, 1);
8557 int size
= extract32(insn
, 22, 2);
8558 int opcode
= extract32(insn
, 12, 4);
8559 int rm
= extract32(insn
, 16, 5);
8560 int rn
= extract32(insn
, 5, 5);
8561 int rd
= extract32(insn
, 0, 5);
8564 unallocated_encoding(s
);
8569 case 0x9: /* SQDMLAL, SQDMLAL2 */
8570 case 0xb: /* SQDMLSL, SQDMLSL2 */
8571 case 0xd: /* SQDMULL, SQDMULL2 */
8572 if (size
== 0 || size
== 3) {
8573 unallocated_encoding(s
);
8578 unallocated_encoding(s
);
8582 if (!fp_access_check(s
)) {
8587 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8588 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8589 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8591 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8592 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8594 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8595 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8598 case 0xd: /* SQDMULL, SQDMULL2 */
8600 case 0xb: /* SQDMLSL, SQDMLSL2 */
8601 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8603 case 0x9: /* SQDMLAL, SQDMLAL2 */
8604 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8605 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8609 g_assert_not_reached();
8612 write_fp_dreg(s
, rd
, tcg_res
);
8614 tcg_temp_free_i64(tcg_op1
);
8615 tcg_temp_free_i64(tcg_op2
);
8616 tcg_temp_free_i64(tcg_res
);
8618 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8619 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8620 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8622 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8623 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8626 case 0xd: /* SQDMULL, SQDMULL2 */
8628 case 0xb: /* SQDMLSL, SQDMLSL2 */
8629 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8631 case 0x9: /* SQDMLAL, SQDMLAL2 */
8633 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8634 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8635 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8637 tcg_temp_free_i64(tcg_op3
);
8641 g_assert_not_reached();
8644 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8645 write_fp_dreg(s
, rd
, tcg_res
);
8647 tcg_temp_free_i32(tcg_op1
);
8648 tcg_temp_free_i32(tcg_op2
);
8649 tcg_temp_free_i64(tcg_res
);
8653 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8654 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8656 /* Handle 64x64->64 opcodes which are shared between the scalar
8657 * and vector 3-same groups. We cover every opcode where size == 3
8658 * is valid in either the three-reg-same (integer, not pairwise)
8659 * or scalar-three-reg-same groups.
8664 case 0x1: /* SQADD */
8666 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8668 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8671 case 0x5: /* SQSUB */
8673 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8675 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8678 case 0x6: /* CMGT, CMHI */
8679 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8680 * We implement this using setcond (test) and then negating.
8682 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8684 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8685 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8687 case 0x7: /* CMGE, CMHS */
8688 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8690 case 0x11: /* CMTST, CMEQ */
8695 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8697 case 0x8: /* SSHL, USHL */
8699 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8701 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8704 case 0x9: /* SQSHL, UQSHL */
8706 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8708 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8711 case 0xa: /* SRSHL, URSHL */
8713 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8715 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8718 case 0xb: /* SQRSHL, UQRSHL */
8720 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8722 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8725 case 0x10: /* ADD, SUB */
8727 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8729 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8733 g_assert_not_reached();
8737 /* Handle the 3-same-operands float operations; shared by the scalar
8738 * and vector encodings. The caller must filter out any encodings
8739 * not allocated for the encoding it is dealing with.
8741 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8742 int fpopcode
, int rd
, int rn
, int rm
)
8745 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8747 for (pass
= 0; pass
< elements
; pass
++) {
8750 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8751 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8752 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8754 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8755 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8758 case 0x39: /* FMLS */
8759 /* As usual for ARM, separate negation for fused multiply-add */
8760 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8762 case 0x19: /* FMLA */
8763 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8764 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8767 case 0x18: /* FMAXNM */
8768 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8770 case 0x1a: /* FADD */
8771 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8773 case 0x1b: /* FMULX */
8774 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8776 case 0x1c: /* FCMEQ */
8777 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8779 case 0x1e: /* FMAX */
8780 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8782 case 0x1f: /* FRECPS */
8783 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8785 case 0x38: /* FMINNM */
8786 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8788 case 0x3a: /* FSUB */
8789 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8791 case 0x3e: /* FMIN */
8792 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8794 case 0x3f: /* FRSQRTS */
8795 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8797 case 0x5b: /* FMUL */
8798 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8800 case 0x5c: /* FCMGE */
8801 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8803 case 0x5d: /* FACGE */
8804 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8806 case 0x5f: /* FDIV */
8807 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8809 case 0x7a: /* FABD */
8810 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8811 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8813 case 0x7c: /* FCMGT */
8814 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8816 case 0x7d: /* FACGT */
8817 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8820 g_assert_not_reached();
8823 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8825 tcg_temp_free_i64(tcg_res
);
8826 tcg_temp_free_i64(tcg_op1
);
8827 tcg_temp_free_i64(tcg_op2
);
8830 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8831 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8832 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8834 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8835 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8838 case 0x39: /* FMLS */
8839 /* As usual for ARM, separate negation for fused multiply-add */
8840 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8842 case 0x19: /* FMLA */
8843 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8844 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8847 case 0x1a: /* FADD */
8848 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8850 case 0x1b: /* FMULX */
8851 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8853 case 0x1c: /* FCMEQ */
8854 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8856 case 0x1e: /* FMAX */
8857 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8859 case 0x1f: /* FRECPS */
8860 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8862 case 0x18: /* FMAXNM */
8863 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8865 case 0x38: /* FMINNM */
8866 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8868 case 0x3a: /* FSUB */
8869 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8871 case 0x3e: /* FMIN */
8872 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8874 case 0x3f: /* FRSQRTS */
8875 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8877 case 0x5b: /* FMUL */
8878 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8880 case 0x5c: /* FCMGE */
8881 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8883 case 0x5d: /* FACGE */
8884 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8886 case 0x5f: /* FDIV */
8887 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8889 case 0x7a: /* FABD */
8890 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8891 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8893 case 0x7c: /* FCMGT */
8894 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8896 case 0x7d: /* FACGT */
8897 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8900 g_assert_not_reached();
8903 if (elements
== 1) {
8904 /* scalar single so clear high part */
8905 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8907 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8908 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8909 tcg_temp_free_i64(tcg_tmp
);
8911 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8914 tcg_temp_free_i32(tcg_res
);
8915 tcg_temp_free_i32(tcg_op1
);
8916 tcg_temp_free_i32(tcg_op2
);
8920 tcg_temp_free_ptr(fpst
);
8922 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8925 /* AdvSIMD scalar three same
8926 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8927 * +-----+---+-----------+------+---+------+--------+---+------+------+
8928 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8929 * +-----+---+-----------+------+---+------+--------+---+------+------+
8931 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8933 int rd
= extract32(insn
, 0, 5);
8934 int rn
= extract32(insn
, 5, 5);
8935 int opcode
= extract32(insn
, 11, 5);
8936 int rm
= extract32(insn
, 16, 5);
8937 int size
= extract32(insn
, 22, 2);
8938 bool u
= extract32(insn
, 29, 1);
8941 if (opcode
>= 0x18) {
8942 /* Floating point: U, size[1] and opcode indicate operation */
8943 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8945 case 0x1b: /* FMULX */
8946 case 0x1f: /* FRECPS */
8947 case 0x3f: /* FRSQRTS */
8948 case 0x5d: /* FACGE */
8949 case 0x7d: /* FACGT */
8950 case 0x1c: /* FCMEQ */
8951 case 0x5c: /* FCMGE */
8952 case 0x7c: /* FCMGT */
8953 case 0x7a: /* FABD */
8956 unallocated_encoding(s
);
8960 if (!fp_access_check(s
)) {
8964 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8969 case 0x1: /* SQADD, UQADD */
8970 case 0x5: /* SQSUB, UQSUB */
8971 case 0x9: /* SQSHL, UQSHL */
8972 case 0xb: /* SQRSHL, UQRSHL */
8974 case 0x8: /* SSHL, USHL */
8975 case 0xa: /* SRSHL, URSHL */
8976 case 0x6: /* CMGT, CMHI */
8977 case 0x7: /* CMGE, CMHS */
8978 case 0x11: /* CMTST, CMEQ */
8979 case 0x10: /* ADD, SUB (vector) */
8981 unallocated_encoding(s
);
8985 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8986 if (size
!= 1 && size
!= 2) {
8987 unallocated_encoding(s
);
8992 unallocated_encoding(s
);
8996 if (!fp_access_check(s
)) {
9000 tcg_rd
= tcg_temp_new_i64();
9003 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9004 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9006 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9007 tcg_temp_free_i64(tcg_rn
);
9008 tcg_temp_free_i64(tcg_rm
);
9010 /* Do a single operation on the lowest element in the vector.
9011 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9012 * no side effects for all these operations.
9013 * OPTME: special-purpose helpers would avoid doing some
9014 * unnecessary work in the helper for the 8 and 16 bit cases.
9016 NeonGenTwoOpEnvFn
*genenvfn
;
9017 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9018 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9019 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9021 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9022 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9025 case 0x1: /* SQADD, UQADD */
9027 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9028 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9029 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9030 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9032 genenvfn
= fns
[size
][u
];
9035 case 0x5: /* SQSUB, UQSUB */
9037 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9038 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9039 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9040 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9042 genenvfn
= fns
[size
][u
];
9045 case 0x9: /* SQSHL, UQSHL */
9047 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9048 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9049 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9050 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9052 genenvfn
= fns
[size
][u
];
9055 case 0xb: /* SQRSHL, UQRSHL */
9057 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9058 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9059 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9060 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9062 genenvfn
= fns
[size
][u
];
9065 case 0x16: /* SQDMULH, SQRDMULH */
9067 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9068 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9069 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9071 assert(size
== 1 || size
== 2);
9072 genenvfn
= fns
[size
- 1][u
];
9076 g_assert_not_reached();
9079 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9080 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9081 tcg_temp_free_i32(tcg_rd32
);
9082 tcg_temp_free_i32(tcg_rn
);
9083 tcg_temp_free_i32(tcg_rm
);
9086 write_fp_dreg(s
, rd
, tcg_rd
);
9088 tcg_temp_free_i64(tcg_rd
);
9091 /* AdvSIMD scalar three same FP16
9092 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9093 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9094 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9095 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9096 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9097 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9099 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9102 int rd
= extract32(insn
, 0, 5);
9103 int rn
= extract32(insn
, 5, 5);
9104 int opcode
= extract32(insn
, 11, 3);
9105 int rm
= extract32(insn
, 16, 5);
9106 bool u
= extract32(insn
, 29, 1);
9107 bool a
= extract32(insn
, 23, 1);
9108 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9115 case 0x03: /* FMULX */
9116 case 0x04: /* FCMEQ (reg) */
9117 case 0x07: /* FRECPS */
9118 case 0x0f: /* FRSQRTS */
9119 case 0x14: /* FCMGE (reg) */
9120 case 0x15: /* FACGE */
9121 case 0x1a: /* FABD */
9122 case 0x1c: /* FCMGT (reg) */
9123 case 0x1d: /* FACGT */
9126 unallocated_encoding(s
);
9130 if (!dc_isar_feature(aa64_fp16
, s
)) {
9131 unallocated_encoding(s
);
9134 if (!fp_access_check(s
)) {
9138 fpst
= get_fpstatus_ptr(true);
9140 tcg_op1
= read_fp_hreg(s
, rn
);
9141 tcg_op2
= read_fp_hreg(s
, rm
);
9142 tcg_res
= tcg_temp_new_i32();
9145 case 0x03: /* FMULX */
9146 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9148 case 0x04: /* FCMEQ (reg) */
9149 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9151 case 0x07: /* FRECPS */
9152 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9154 case 0x0f: /* FRSQRTS */
9155 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9157 case 0x14: /* FCMGE (reg) */
9158 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9160 case 0x15: /* FACGE */
9161 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9163 case 0x1a: /* FABD */
9164 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9165 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9167 case 0x1c: /* FCMGT (reg) */
9168 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9170 case 0x1d: /* FACGT */
9171 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9174 g_assert_not_reached();
9177 write_fp_sreg(s
, rd
, tcg_res
);
9180 tcg_temp_free_i32(tcg_res
);
9181 tcg_temp_free_i32(tcg_op1
);
9182 tcg_temp_free_i32(tcg_op2
);
9183 tcg_temp_free_ptr(fpst
);
9186 /* AdvSIMD scalar three same extra
9187 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9188 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9189 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9190 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9192 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9195 int rd
= extract32(insn
, 0, 5);
9196 int rn
= extract32(insn
, 5, 5);
9197 int opcode
= extract32(insn
, 11, 4);
9198 int rm
= extract32(insn
, 16, 5);
9199 int size
= extract32(insn
, 22, 2);
9200 bool u
= extract32(insn
, 29, 1);
9201 TCGv_i32 ele1
, ele2
, ele3
;
9205 switch (u
* 16 + opcode
) {
9206 case 0x10: /* SQRDMLAH (vector) */
9207 case 0x11: /* SQRDMLSH (vector) */
9208 if (size
!= 1 && size
!= 2) {
9209 unallocated_encoding(s
);
9212 feature
= dc_isar_feature(aa64_rdm
, s
);
9215 unallocated_encoding(s
);
9219 unallocated_encoding(s
);
9222 if (!fp_access_check(s
)) {
9226 /* Do a single operation on the lowest element in the vector.
9227 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9228 * with no side effects for all these operations.
9229 * OPTME: special-purpose helpers would avoid doing some
9230 * unnecessary work in the helper for the 16 bit cases.
9232 ele1
= tcg_temp_new_i32();
9233 ele2
= tcg_temp_new_i32();
9234 ele3
= tcg_temp_new_i32();
9236 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9237 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9238 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9241 case 0x0: /* SQRDMLAH */
9243 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9245 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9248 case 0x1: /* SQRDMLSH */
9250 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9252 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9256 g_assert_not_reached();
9258 tcg_temp_free_i32(ele1
);
9259 tcg_temp_free_i32(ele2
);
9261 res
= tcg_temp_new_i64();
9262 tcg_gen_extu_i32_i64(res
, ele3
);
9263 tcg_temp_free_i32(ele3
);
9265 write_fp_dreg(s
, rd
, res
);
9266 tcg_temp_free_i64(res
);
9269 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9270 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9271 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9273 /* Handle 64->64 opcodes which are shared between the scalar and
9274 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9275 * is valid in either group and also the double-precision fp ops.
9276 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9282 case 0x4: /* CLS, CLZ */
9284 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9286 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9290 /* This opcode is shared with CNT and RBIT but we have earlier
9291 * enforced that size == 3 if and only if this is the NOT insn.
9293 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9295 case 0x7: /* SQABS, SQNEG */
9297 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9299 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9302 case 0xa: /* CMLT */
9303 /* 64 bit integer comparison against zero, result is
9304 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9309 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9310 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9312 case 0x8: /* CMGT, CMGE */
9313 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9315 case 0x9: /* CMEQ, CMLE */
9316 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9318 case 0xb: /* ABS, NEG */
9320 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9322 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9325 case 0x2f: /* FABS */
9326 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9328 case 0x6f: /* FNEG */
9329 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9331 case 0x7f: /* FSQRT */
9332 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9334 case 0x1a: /* FCVTNS */
9335 case 0x1b: /* FCVTMS */
9336 case 0x1c: /* FCVTAS */
9337 case 0x3a: /* FCVTPS */
9338 case 0x3b: /* FCVTZS */
9340 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9341 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9342 tcg_temp_free_i32(tcg_shift
);
9345 case 0x5a: /* FCVTNU */
9346 case 0x5b: /* FCVTMU */
9347 case 0x5c: /* FCVTAU */
9348 case 0x7a: /* FCVTPU */
9349 case 0x7b: /* FCVTZU */
9351 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9352 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9353 tcg_temp_free_i32(tcg_shift
);
9356 case 0x18: /* FRINTN */
9357 case 0x19: /* FRINTM */
9358 case 0x38: /* FRINTP */
9359 case 0x39: /* FRINTZ */
9360 case 0x58: /* FRINTA */
9361 case 0x79: /* FRINTI */
9362 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9364 case 0x59: /* FRINTX */
9365 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9367 case 0x1e: /* FRINT32Z */
9368 case 0x5e: /* FRINT32X */
9369 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9371 case 0x1f: /* FRINT64Z */
9372 case 0x5f: /* FRINT64X */
9373 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9376 g_assert_not_reached();
9380 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9381 bool is_scalar
, bool is_u
, bool is_q
,
9382 int size
, int rn
, int rd
)
9384 bool is_double
= (size
== MO_64
);
9387 if (!fp_access_check(s
)) {
9391 fpst
= get_fpstatus_ptr(size
== MO_16
);
9394 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9395 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9396 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9397 NeonGenTwoDoubleOPFn
*genfn
;
9402 case 0x2e: /* FCMLT (zero) */
9405 case 0x2c: /* FCMGT (zero) */
9406 genfn
= gen_helper_neon_cgt_f64
;
9408 case 0x2d: /* FCMEQ (zero) */
9409 genfn
= gen_helper_neon_ceq_f64
;
9411 case 0x6d: /* FCMLE (zero) */
9414 case 0x6c: /* FCMGE (zero) */
9415 genfn
= gen_helper_neon_cge_f64
;
9418 g_assert_not_reached();
9421 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9422 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9424 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9426 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9428 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9430 tcg_temp_free_i64(tcg_res
);
9431 tcg_temp_free_i64(tcg_zero
);
9432 tcg_temp_free_i64(tcg_op
);
9434 clear_vec_high(s
, !is_scalar
, rd
);
9436 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9437 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9438 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9439 NeonGenTwoSingleOPFn
*genfn
;
9441 int pass
, maxpasses
;
9443 if (size
== MO_16
) {
9445 case 0x2e: /* FCMLT (zero) */
9448 case 0x2c: /* FCMGT (zero) */
9449 genfn
= gen_helper_advsimd_cgt_f16
;
9451 case 0x2d: /* FCMEQ (zero) */
9452 genfn
= gen_helper_advsimd_ceq_f16
;
9454 case 0x6d: /* FCMLE (zero) */
9457 case 0x6c: /* FCMGE (zero) */
9458 genfn
= gen_helper_advsimd_cge_f16
;
9461 g_assert_not_reached();
9465 case 0x2e: /* FCMLT (zero) */
9468 case 0x2c: /* FCMGT (zero) */
9469 genfn
= gen_helper_neon_cgt_f32
;
9471 case 0x2d: /* FCMEQ (zero) */
9472 genfn
= gen_helper_neon_ceq_f32
;
9474 case 0x6d: /* FCMLE (zero) */
9477 case 0x6c: /* FCMGE (zero) */
9478 genfn
= gen_helper_neon_cge_f32
;
9481 g_assert_not_reached();
9488 int vector_size
= 8 << is_q
;
9489 maxpasses
= vector_size
>> size
;
9492 for (pass
= 0; pass
< maxpasses
; pass
++) {
9493 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9495 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9497 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9500 write_fp_sreg(s
, rd
, tcg_res
);
9502 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9505 tcg_temp_free_i32(tcg_res
);
9506 tcg_temp_free_i32(tcg_zero
);
9507 tcg_temp_free_i32(tcg_op
);
9509 clear_vec_high(s
, is_q
, rd
);
9513 tcg_temp_free_ptr(fpst
);
9516 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9517 bool is_scalar
, bool is_u
, bool is_q
,
9518 int size
, int rn
, int rd
)
9520 bool is_double
= (size
== 3);
9521 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9524 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9525 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9528 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9529 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9531 case 0x3d: /* FRECPE */
9532 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9534 case 0x3f: /* FRECPX */
9535 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9537 case 0x7d: /* FRSQRTE */
9538 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9541 g_assert_not_reached();
9543 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9545 tcg_temp_free_i64(tcg_res
);
9546 tcg_temp_free_i64(tcg_op
);
9547 clear_vec_high(s
, !is_scalar
, rd
);
9549 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9550 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9551 int pass
, maxpasses
;
9556 maxpasses
= is_q
? 4 : 2;
9559 for (pass
= 0; pass
< maxpasses
; pass
++) {
9560 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9563 case 0x3c: /* URECPE */
9564 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9566 case 0x3d: /* FRECPE */
9567 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9569 case 0x3f: /* FRECPX */
9570 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9572 case 0x7d: /* FRSQRTE */
9573 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9576 g_assert_not_reached();
9580 write_fp_sreg(s
, rd
, tcg_res
);
9582 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9585 tcg_temp_free_i32(tcg_res
);
9586 tcg_temp_free_i32(tcg_op
);
9588 clear_vec_high(s
, is_q
, rd
);
9591 tcg_temp_free_ptr(fpst
);
9594 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9595 int opcode
, bool u
, bool is_q
,
9596 int size
, int rn
, int rd
)
9598 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9599 * in the source becomes a size element in the destination).
9602 TCGv_i32 tcg_res
[2];
9603 int destelt
= is_q
? 2 : 0;
9604 int passes
= scalar
? 1 : 2;
9607 tcg_res
[1] = tcg_const_i32(0);
9610 for (pass
= 0; pass
< passes
; pass
++) {
9611 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9612 NeonGenNarrowFn
*genfn
= NULL
;
9613 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9616 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9618 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9620 tcg_res
[pass
] = tcg_temp_new_i32();
9623 case 0x12: /* XTN, SQXTUN */
9625 static NeonGenNarrowFn
* const xtnfns
[3] = {
9626 gen_helper_neon_narrow_u8
,
9627 gen_helper_neon_narrow_u16
,
9628 tcg_gen_extrl_i64_i32
,
9630 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9631 gen_helper_neon_unarrow_sat8
,
9632 gen_helper_neon_unarrow_sat16
,
9633 gen_helper_neon_unarrow_sat32
,
9636 genenvfn
= sqxtunfns
[size
];
9638 genfn
= xtnfns
[size
];
9642 case 0x14: /* SQXTN, UQXTN */
9644 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9645 { gen_helper_neon_narrow_sat_s8
,
9646 gen_helper_neon_narrow_sat_u8
},
9647 { gen_helper_neon_narrow_sat_s16
,
9648 gen_helper_neon_narrow_sat_u16
},
9649 { gen_helper_neon_narrow_sat_s32
,
9650 gen_helper_neon_narrow_sat_u32
},
9652 genenvfn
= fns
[size
][u
];
9655 case 0x16: /* FCVTN, FCVTN2 */
9656 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9658 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9660 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9661 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9662 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9663 TCGv_i32 ahp
= get_ahp_flag();
9665 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9666 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9667 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9668 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9669 tcg_temp_free_i32(tcg_lo
);
9670 tcg_temp_free_i32(tcg_hi
);
9671 tcg_temp_free_ptr(fpst
);
9672 tcg_temp_free_i32(ahp
);
9675 case 0x56: /* FCVTXN, FCVTXN2 */
9676 /* 64 bit to 32 bit float conversion
9677 * with von Neumann rounding (round to odd)
9680 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9683 g_assert_not_reached();
9687 genfn(tcg_res
[pass
], tcg_op
);
9688 } else if (genenvfn
) {
9689 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9692 tcg_temp_free_i64(tcg_op
);
9695 for (pass
= 0; pass
< 2; pass
++) {
9696 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9697 tcg_temp_free_i32(tcg_res
[pass
]);
9699 clear_vec_high(s
, is_q
, rd
);
9702 /* Remaining saturating accumulating ops */
9703 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9704 bool is_q
, int size
, int rn
, int rd
)
9706 bool is_double
= (size
== 3);
9709 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9710 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9713 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9714 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9715 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9717 if (is_u
) { /* USQADD */
9718 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9719 } else { /* SUQADD */
9720 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9722 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9724 tcg_temp_free_i64(tcg_rd
);
9725 tcg_temp_free_i64(tcg_rn
);
9726 clear_vec_high(s
, !is_scalar
, rd
);
9728 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9729 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9730 int pass
, maxpasses
;
9735 maxpasses
= is_q
? 4 : 2;
9738 for (pass
= 0; pass
< maxpasses
; pass
++) {
9740 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9741 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9743 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9744 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9747 if (is_u
) { /* USQADD */
9750 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9753 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9756 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9759 g_assert_not_reached();
9761 } else { /* SUQADD */
9764 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9767 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9770 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9773 g_assert_not_reached();
9778 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9779 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9780 tcg_temp_free_i64(tcg_zero
);
9782 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9784 tcg_temp_free_i32(tcg_rd
);
9785 tcg_temp_free_i32(tcg_rn
);
9786 clear_vec_high(s
, is_q
, rd
);
9790 /* AdvSIMD scalar two reg misc
9791 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9792 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9793 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9794 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9796 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9798 int rd
= extract32(insn
, 0, 5);
9799 int rn
= extract32(insn
, 5, 5);
9800 int opcode
= extract32(insn
, 12, 5);
9801 int size
= extract32(insn
, 22, 2);
9802 bool u
= extract32(insn
, 29, 1);
9803 bool is_fcvt
= false;
9806 TCGv_ptr tcg_fpstatus
;
9809 case 0x3: /* USQADD / SUQADD*/
9810 if (!fp_access_check(s
)) {
9813 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9815 case 0x7: /* SQABS / SQNEG */
9817 case 0xa: /* CMLT */
9819 unallocated_encoding(s
);
9823 case 0x8: /* CMGT, CMGE */
9824 case 0x9: /* CMEQ, CMLE */
9825 case 0xb: /* ABS, NEG */
9827 unallocated_encoding(s
);
9831 case 0x12: /* SQXTUN */
9833 unallocated_encoding(s
);
9837 case 0x14: /* SQXTN, UQXTN */
9839 unallocated_encoding(s
);
9842 if (!fp_access_check(s
)) {
9845 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9850 /* Floating point: U, size[1] and opcode indicate operation;
9851 * size[0] indicates single or double precision.
9853 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9854 size
= extract32(size
, 0, 1) ? 3 : 2;
9856 case 0x2c: /* FCMGT (zero) */
9857 case 0x2d: /* FCMEQ (zero) */
9858 case 0x2e: /* FCMLT (zero) */
9859 case 0x6c: /* FCMGE (zero) */
9860 case 0x6d: /* FCMLE (zero) */
9861 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9863 case 0x1d: /* SCVTF */
9864 case 0x5d: /* UCVTF */
9866 bool is_signed
= (opcode
== 0x1d);
9867 if (!fp_access_check(s
)) {
9870 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9873 case 0x3d: /* FRECPE */
9874 case 0x3f: /* FRECPX */
9875 case 0x7d: /* FRSQRTE */
9876 if (!fp_access_check(s
)) {
9879 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9881 case 0x1a: /* FCVTNS */
9882 case 0x1b: /* FCVTMS */
9883 case 0x3a: /* FCVTPS */
9884 case 0x3b: /* FCVTZS */
9885 case 0x5a: /* FCVTNU */
9886 case 0x5b: /* FCVTMU */
9887 case 0x7a: /* FCVTPU */
9888 case 0x7b: /* FCVTZU */
9890 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9892 case 0x1c: /* FCVTAS */
9893 case 0x5c: /* FCVTAU */
9894 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9896 rmode
= FPROUNDING_TIEAWAY
;
9898 case 0x56: /* FCVTXN, FCVTXN2 */
9900 unallocated_encoding(s
);
9903 if (!fp_access_check(s
)) {
9906 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9909 unallocated_encoding(s
);
9914 unallocated_encoding(s
);
9918 if (!fp_access_check(s
)) {
9923 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9924 tcg_fpstatus
= get_fpstatus_ptr(false);
9925 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9928 tcg_fpstatus
= NULL
;
9932 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9933 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9935 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9936 write_fp_dreg(s
, rd
, tcg_rd
);
9937 tcg_temp_free_i64(tcg_rd
);
9938 tcg_temp_free_i64(tcg_rn
);
9940 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9941 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9943 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9946 case 0x7: /* SQABS, SQNEG */
9948 NeonGenOneOpEnvFn
*genfn
;
9949 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9950 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9951 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9952 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9954 genfn
= fns
[size
][u
];
9955 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9958 case 0x1a: /* FCVTNS */
9959 case 0x1b: /* FCVTMS */
9960 case 0x1c: /* FCVTAS */
9961 case 0x3a: /* FCVTPS */
9962 case 0x3b: /* FCVTZS */
9964 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9965 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9966 tcg_temp_free_i32(tcg_shift
);
9969 case 0x5a: /* FCVTNU */
9970 case 0x5b: /* FCVTMU */
9971 case 0x5c: /* FCVTAU */
9972 case 0x7a: /* FCVTPU */
9973 case 0x7b: /* FCVTZU */
9975 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9976 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9977 tcg_temp_free_i32(tcg_shift
);
9981 g_assert_not_reached();
9984 write_fp_sreg(s
, rd
, tcg_rd
);
9985 tcg_temp_free_i32(tcg_rd
);
9986 tcg_temp_free_i32(tcg_rn
);
9990 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9991 tcg_temp_free_i32(tcg_rmode
);
9992 tcg_temp_free_ptr(tcg_fpstatus
);
9996 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9997 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9998 int immh
, int immb
, int opcode
, int rn
, int rd
)
10000 int size
= 32 - clz32(immh
) - 1;
10001 int immhb
= immh
<< 3 | immb
;
10002 int shift
= 2 * (8 << size
) - immhb
;
10003 bool accumulate
= false;
10004 int dsize
= is_q
? 128 : 64;
10005 int esize
= 8 << size
;
10006 int elements
= dsize
/esize
;
10007 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
10008 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10009 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10010 TCGv_i64 tcg_round
;
10011 uint64_t round_const
;
10014 if (extract32(immh
, 3, 1) && !is_q
) {
10015 unallocated_encoding(s
);
10018 tcg_debug_assert(size
<= 3);
10020 if (!fp_access_check(s
)) {
10025 case 0x02: /* SSRA / USRA (accumulate) */
10027 /* Shift count same as element size produces zero to add. */
10028 if (shift
== 8 << size
) {
10031 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
10033 /* Shift count same as element size produces all sign to add. */
10034 if (shift
== 8 << size
) {
10037 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
10040 case 0x08: /* SRI */
10041 /* Shift count same as element size is valid but does nothing. */
10042 if (shift
== 8 << size
) {
10045 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
10048 case 0x00: /* SSHR / USHR */
10050 if (shift
== 8 << size
) {
10051 /* Shift count the same size as element size produces zero. */
10052 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
10053 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10055 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
10058 /* Shift count the same size as element size produces all sign. */
10059 if (shift
== 8 << size
) {
10062 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10066 case 0x04: /* SRSHR / URSHR (rounding) */
10068 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10072 g_assert_not_reached();
10075 round_const
= 1ULL << (shift
- 1);
10076 tcg_round
= tcg_const_i64(round_const
);
10078 for (i
= 0; i
< elements
; i
++) {
10079 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10081 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10084 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10085 accumulate
, is_u
, size
, shift
);
10087 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10089 tcg_temp_free_i64(tcg_round
);
10092 clear_vec_high(s
, is_q
, rd
);
10095 /* SHL/SLI - Vector shift left */
10096 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10097 int immh
, int immb
, int opcode
, int rn
, int rd
)
10099 int size
= 32 - clz32(immh
) - 1;
10100 int immhb
= immh
<< 3 | immb
;
10101 int shift
= immhb
- (8 << size
);
10103 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10104 assert(size
>= 0 && size
<= 3);
10106 if (extract32(immh
, 3, 1) && !is_q
) {
10107 unallocated_encoding(s
);
10111 if (!fp_access_check(s
)) {
10116 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10118 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10122 /* USHLL/SHLL - Vector shift left with widening */
10123 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10124 int immh
, int immb
, int opcode
, int rn
, int rd
)
10126 int size
= 32 - clz32(immh
) - 1;
10127 int immhb
= immh
<< 3 | immb
;
10128 int shift
= immhb
- (8 << size
);
10130 int esize
= 8 << size
;
10131 int elements
= dsize
/esize
;
10132 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10133 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10137 unallocated_encoding(s
);
10141 if (!fp_access_check(s
)) {
10145 /* For the LL variants the store is larger than the load,
10146 * so if rd == rn we would overwrite parts of our input.
10147 * So load everything right now and use shifts in the main loop.
10149 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10151 for (i
= 0; i
< elements
; i
++) {
10152 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10153 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10154 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10155 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10159 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10160 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10161 int immh
, int immb
, int opcode
, int rn
, int rd
)
10163 int immhb
= immh
<< 3 | immb
;
10164 int size
= 32 - clz32(immh
) - 1;
10166 int esize
= 8 << size
;
10167 int elements
= dsize
/esize
;
10168 int shift
= (2 * esize
) - immhb
;
10169 bool round
= extract32(opcode
, 0, 1);
10170 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10171 TCGv_i64 tcg_round
;
10174 if (extract32(immh
, 3, 1)) {
10175 unallocated_encoding(s
);
10179 if (!fp_access_check(s
)) {
10183 tcg_rn
= tcg_temp_new_i64();
10184 tcg_rd
= tcg_temp_new_i64();
10185 tcg_final
= tcg_temp_new_i64();
10186 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10189 uint64_t round_const
= 1ULL << (shift
- 1);
10190 tcg_round
= tcg_const_i64(round_const
);
10195 for (i
= 0; i
< elements
; i
++) {
10196 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10197 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10198 false, true, size
+1, shift
);
10200 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10204 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10206 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10209 tcg_temp_free_i64(tcg_round
);
10211 tcg_temp_free_i64(tcg_rn
);
10212 tcg_temp_free_i64(tcg_rd
);
10213 tcg_temp_free_i64(tcg_final
);
10215 clear_vec_high(s
, is_q
, rd
);
10219 /* AdvSIMD shift by immediate
10220 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10221 * +---+---+---+-------------+------+------+--------+---+------+------+
10222 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10223 * +---+---+---+-------------+------+------+--------+---+------+------+
10225 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10227 int rd
= extract32(insn
, 0, 5);
10228 int rn
= extract32(insn
, 5, 5);
10229 int opcode
= extract32(insn
, 11, 5);
10230 int immb
= extract32(insn
, 16, 3);
10231 int immh
= extract32(insn
, 19, 4);
10232 bool is_u
= extract32(insn
, 29, 1);
10233 bool is_q
= extract32(insn
, 30, 1);
10236 case 0x08: /* SRI */
10238 unallocated_encoding(s
);
10242 case 0x00: /* SSHR / USHR */
10243 case 0x02: /* SSRA / USRA (accumulate) */
10244 case 0x04: /* SRSHR / URSHR (rounding) */
10245 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10246 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10248 case 0x0a: /* SHL / SLI */
10249 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10251 case 0x10: /* SHRN */
10252 case 0x11: /* RSHRN / SQRSHRUN */
10254 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10257 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10260 case 0x12: /* SQSHRN / UQSHRN */
10261 case 0x13: /* SQRSHRN / UQRSHRN */
10262 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10265 case 0x14: /* SSHLL / USHLL */
10266 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10268 case 0x1c: /* SCVTF / UCVTF */
10269 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10272 case 0xc: /* SQSHLU */
10274 unallocated_encoding(s
);
10277 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10279 case 0xe: /* SQSHL, UQSHL */
10280 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10282 case 0x1f: /* FCVTZS/ FCVTZU */
10283 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10286 unallocated_encoding(s
);
10291 /* Generate code to do a "long" addition or subtraction, ie one done in
10292 * TCGv_i64 on vector lanes twice the width specified by size.
10294 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10295 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10297 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10298 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10299 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10300 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10302 NeonGenTwo64OpFn
*genfn
;
10305 genfn
= fns
[size
][is_sub
];
10306 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10309 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10310 int opcode
, int rd
, int rn
, int rm
)
10312 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10313 TCGv_i64 tcg_res
[2];
10316 tcg_res
[0] = tcg_temp_new_i64();
10317 tcg_res
[1] = tcg_temp_new_i64();
10319 /* Does this op do an adding accumulate, a subtracting accumulate,
10320 * or no accumulate at all?
10338 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10339 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10342 /* size == 2 means two 32x32->64 operations; this is worth special
10343 * casing because we can generally handle it inline.
10346 for (pass
= 0; pass
< 2; pass
++) {
10347 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10348 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10349 TCGv_i64 tcg_passres
;
10350 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10352 int elt
= pass
+ is_q
* 2;
10354 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10355 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10358 tcg_passres
= tcg_res
[pass
];
10360 tcg_passres
= tcg_temp_new_i64();
10364 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10365 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10367 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10368 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10370 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10371 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10373 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10374 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10376 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10377 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10378 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10380 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10381 tcg_temp_free_i64(tcg_tmp1
);
10382 tcg_temp_free_i64(tcg_tmp2
);
10385 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10386 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10387 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10388 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10390 case 9: /* SQDMLAL, SQDMLAL2 */
10391 case 11: /* SQDMLSL, SQDMLSL2 */
10392 case 13: /* SQDMULL, SQDMULL2 */
10393 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10394 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10395 tcg_passres
, tcg_passres
);
10398 g_assert_not_reached();
10401 if (opcode
== 9 || opcode
== 11) {
10402 /* saturating accumulate ops */
10404 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10406 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10407 tcg_res
[pass
], tcg_passres
);
10408 } else if (accop
> 0) {
10409 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10410 } else if (accop
< 0) {
10411 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10415 tcg_temp_free_i64(tcg_passres
);
10418 tcg_temp_free_i64(tcg_op1
);
10419 tcg_temp_free_i64(tcg_op2
);
10422 /* size 0 or 1, generally helper functions */
10423 for (pass
= 0; pass
< 2; pass
++) {
10424 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10425 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10426 TCGv_i64 tcg_passres
;
10427 int elt
= pass
+ is_q
* 2;
10429 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10430 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10433 tcg_passres
= tcg_res
[pass
];
10435 tcg_passres
= tcg_temp_new_i64();
10439 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10440 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10442 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10443 static NeonGenWidenFn
* const widenfns
[2][2] = {
10444 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10445 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10447 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10449 widenfn(tcg_op2_64
, tcg_op2
);
10450 widenfn(tcg_passres
, tcg_op1
);
10451 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10452 tcg_passres
, tcg_op2_64
);
10453 tcg_temp_free_i64(tcg_op2_64
);
10456 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10457 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10460 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10462 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10466 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10468 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10472 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10473 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10474 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10477 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10479 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10483 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10485 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10489 case 9: /* SQDMLAL, SQDMLAL2 */
10490 case 11: /* SQDMLSL, SQDMLSL2 */
10491 case 13: /* SQDMULL, SQDMULL2 */
10493 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10494 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10495 tcg_passres
, tcg_passres
);
10497 case 14: /* PMULL */
10499 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10502 g_assert_not_reached();
10504 tcg_temp_free_i32(tcg_op1
);
10505 tcg_temp_free_i32(tcg_op2
);
10508 if (opcode
== 9 || opcode
== 11) {
10509 /* saturating accumulate ops */
10511 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10513 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10517 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10518 tcg_res
[pass
], tcg_passres
);
10520 tcg_temp_free_i64(tcg_passres
);
10525 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10526 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10527 tcg_temp_free_i64(tcg_res
[0]);
10528 tcg_temp_free_i64(tcg_res
[1]);
10531 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10532 int opcode
, int rd
, int rn
, int rm
)
10534 TCGv_i64 tcg_res
[2];
10535 int part
= is_q
? 2 : 0;
10538 for (pass
= 0; pass
< 2; pass
++) {
10539 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10540 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10541 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10542 static NeonGenWidenFn
* const widenfns
[3][2] = {
10543 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10544 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10545 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10547 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10549 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10550 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10551 widenfn(tcg_op2_wide
, tcg_op2
);
10552 tcg_temp_free_i32(tcg_op2
);
10553 tcg_res
[pass
] = tcg_temp_new_i64();
10554 gen_neon_addl(size
, (opcode
== 3),
10555 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10556 tcg_temp_free_i64(tcg_op1
);
10557 tcg_temp_free_i64(tcg_op2_wide
);
10560 for (pass
= 0; pass
< 2; pass
++) {
10561 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10562 tcg_temp_free_i64(tcg_res
[pass
]);
10566 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10568 tcg_gen_addi_i64(in
, in
, 1U << 31);
10569 tcg_gen_extrh_i64_i32(res
, in
);
10572 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10573 int opcode
, int rd
, int rn
, int rm
)
10575 TCGv_i32 tcg_res
[2];
10576 int part
= is_q
? 2 : 0;
10579 for (pass
= 0; pass
< 2; pass
++) {
10580 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10581 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10582 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10583 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10584 { gen_helper_neon_narrow_high_u8
,
10585 gen_helper_neon_narrow_round_high_u8
},
10586 { gen_helper_neon_narrow_high_u16
,
10587 gen_helper_neon_narrow_round_high_u16
},
10588 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10590 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10592 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10593 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10595 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10597 tcg_temp_free_i64(tcg_op1
);
10598 tcg_temp_free_i64(tcg_op2
);
10600 tcg_res
[pass
] = tcg_temp_new_i32();
10601 gennarrow(tcg_res
[pass
], tcg_wideres
);
10602 tcg_temp_free_i64(tcg_wideres
);
10605 for (pass
= 0; pass
< 2; pass
++) {
10606 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10607 tcg_temp_free_i32(tcg_res
[pass
]);
10609 clear_vec_high(s
, is_q
, rd
);
10612 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10614 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10615 * is the only three-reg-diff instruction which produces a
10616 * 128-bit wide result from a single operation. However since
10617 * it's possible to calculate the two halves more or less
10618 * separately we just use two helper calls.
10620 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10621 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10622 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10624 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10625 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10626 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10627 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10628 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10629 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10631 tcg_temp_free_i64(tcg_op1
);
10632 tcg_temp_free_i64(tcg_op2
);
10633 tcg_temp_free_i64(tcg_res
);
10636 /* AdvSIMD three different
10637 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10638 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10639 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10640 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10642 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10644 /* Instructions in this group fall into three basic classes
10645 * (in each case with the operation working on each element in
10646 * the input vectors):
10647 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10649 * (2) wide 64 x 128 -> 128
10650 * (3) narrowing 128 x 128 -> 64
10651 * Here we do initial decode, catch unallocated cases and
10652 * dispatch to separate functions for each class.
10654 int is_q
= extract32(insn
, 30, 1);
10655 int is_u
= extract32(insn
, 29, 1);
10656 int size
= extract32(insn
, 22, 2);
10657 int opcode
= extract32(insn
, 12, 4);
10658 int rm
= extract32(insn
, 16, 5);
10659 int rn
= extract32(insn
, 5, 5);
10660 int rd
= extract32(insn
, 0, 5);
10663 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10664 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10665 /* 64 x 128 -> 128 */
10667 unallocated_encoding(s
);
10670 if (!fp_access_check(s
)) {
10673 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10675 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10676 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10677 /* 128 x 128 -> 64 */
10679 unallocated_encoding(s
);
10682 if (!fp_access_check(s
)) {
10685 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10687 case 14: /* PMULL, PMULL2 */
10688 if (is_u
|| size
== 1 || size
== 2) {
10689 unallocated_encoding(s
);
10693 if (!dc_isar_feature(aa64_pmull
, s
)) {
10694 unallocated_encoding(s
);
10697 if (!fp_access_check(s
)) {
10700 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10704 case 9: /* SQDMLAL, SQDMLAL2 */
10705 case 11: /* SQDMLSL, SQDMLSL2 */
10706 case 13: /* SQDMULL, SQDMULL2 */
10707 if (is_u
|| size
== 0) {
10708 unallocated_encoding(s
);
10712 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10713 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10714 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10715 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10716 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10717 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10718 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10719 /* 64 x 64 -> 128 */
10721 unallocated_encoding(s
);
10725 if (!fp_access_check(s
)) {
10729 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10732 /* opcode 15 not allocated */
10733 unallocated_encoding(s
);
10738 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10739 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10741 int rd
= extract32(insn
, 0, 5);
10742 int rn
= extract32(insn
, 5, 5);
10743 int rm
= extract32(insn
, 16, 5);
10744 int size
= extract32(insn
, 22, 2);
10745 bool is_u
= extract32(insn
, 29, 1);
10746 bool is_q
= extract32(insn
, 30, 1);
10748 if (!fp_access_check(s
)) {
10752 switch (size
+ 4 * is_u
) {
10754 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10757 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10760 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10763 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10766 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10769 case 5: /* BSL bitwise select */
10770 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10772 case 6: /* BIT, bitwise insert if true */
10773 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10775 case 7: /* BIF, bitwise insert if false */
10776 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10780 g_assert_not_reached();
10784 /* Pairwise op subgroup of C3.6.16.
10786 * This is called directly or via the handle_3same_float for float pairwise
10787 * operations where the opcode and size are calculated differently.
10789 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10790 int size
, int rn
, int rm
, int rd
)
10795 /* Floating point operations need fpst */
10796 if (opcode
>= 0x58) {
10797 fpst
= get_fpstatus_ptr(false);
10802 if (!fp_access_check(s
)) {
10806 /* These operations work on the concatenated rm:rn, with each pair of
10807 * adjacent elements being operated on to produce an element in the result.
10810 TCGv_i64 tcg_res
[2];
10812 for (pass
= 0; pass
< 2; pass
++) {
10813 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10814 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10815 int passreg
= (pass
== 0) ? rn
: rm
;
10817 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10818 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10819 tcg_res
[pass
] = tcg_temp_new_i64();
10822 case 0x17: /* ADDP */
10823 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10825 case 0x58: /* FMAXNMP */
10826 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10828 case 0x5a: /* FADDP */
10829 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10831 case 0x5e: /* FMAXP */
10832 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10834 case 0x78: /* FMINNMP */
10835 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10837 case 0x7e: /* FMINP */
10838 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10841 g_assert_not_reached();
10844 tcg_temp_free_i64(tcg_op1
);
10845 tcg_temp_free_i64(tcg_op2
);
10848 for (pass
= 0; pass
< 2; pass
++) {
10849 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10850 tcg_temp_free_i64(tcg_res
[pass
]);
10853 int maxpass
= is_q
? 4 : 2;
10854 TCGv_i32 tcg_res
[4];
10856 for (pass
= 0; pass
< maxpass
; pass
++) {
10857 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10858 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10859 NeonGenTwoOpFn
*genfn
= NULL
;
10860 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10861 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10863 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10864 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10865 tcg_res
[pass
] = tcg_temp_new_i32();
10868 case 0x17: /* ADDP */
10870 static NeonGenTwoOpFn
* const fns
[3] = {
10871 gen_helper_neon_padd_u8
,
10872 gen_helper_neon_padd_u16
,
10878 case 0x14: /* SMAXP, UMAXP */
10880 static NeonGenTwoOpFn
* const fns
[3][2] = {
10881 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10882 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10883 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10885 genfn
= fns
[size
][u
];
10888 case 0x15: /* SMINP, UMINP */
10890 static NeonGenTwoOpFn
* const fns
[3][2] = {
10891 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10892 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10893 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10895 genfn
= fns
[size
][u
];
10898 /* The FP operations are all on single floats (32 bit) */
10899 case 0x58: /* FMAXNMP */
10900 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10902 case 0x5a: /* FADDP */
10903 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10905 case 0x5e: /* FMAXP */
10906 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10908 case 0x78: /* FMINNMP */
10909 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10911 case 0x7e: /* FMINP */
10912 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10915 g_assert_not_reached();
10918 /* FP ops called directly, otherwise call now */
10920 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10923 tcg_temp_free_i32(tcg_op1
);
10924 tcg_temp_free_i32(tcg_op2
);
10927 for (pass
= 0; pass
< maxpass
; pass
++) {
10928 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10929 tcg_temp_free_i32(tcg_res
[pass
]);
10931 clear_vec_high(s
, is_q
, rd
);
10935 tcg_temp_free_ptr(fpst
);
10939 /* Floating point op subgroup of C3.6.16. */
10940 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10942 /* For floating point ops, the U, size[1] and opcode bits
10943 * together indicate the operation. size[0] indicates single
10946 int fpopcode
= extract32(insn
, 11, 5)
10947 | (extract32(insn
, 23, 1) << 5)
10948 | (extract32(insn
, 29, 1) << 6);
10949 int is_q
= extract32(insn
, 30, 1);
10950 int size
= extract32(insn
, 22, 1);
10951 int rm
= extract32(insn
, 16, 5);
10952 int rn
= extract32(insn
, 5, 5);
10953 int rd
= extract32(insn
, 0, 5);
10955 int datasize
= is_q
? 128 : 64;
10956 int esize
= 32 << size
;
10957 int elements
= datasize
/ esize
;
10959 if (size
== 1 && !is_q
) {
10960 unallocated_encoding(s
);
10964 switch (fpopcode
) {
10965 case 0x58: /* FMAXNMP */
10966 case 0x5a: /* FADDP */
10967 case 0x5e: /* FMAXP */
10968 case 0x78: /* FMINNMP */
10969 case 0x7e: /* FMINP */
10970 if (size
&& !is_q
) {
10971 unallocated_encoding(s
);
10974 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10977 case 0x1b: /* FMULX */
10978 case 0x1f: /* FRECPS */
10979 case 0x3f: /* FRSQRTS */
10980 case 0x5d: /* FACGE */
10981 case 0x7d: /* FACGT */
10982 case 0x19: /* FMLA */
10983 case 0x39: /* FMLS */
10984 case 0x18: /* FMAXNM */
10985 case 0x1a: /* FADD */
10986 case 0x1c: /* FCMEQ */
10987 case 0x1e: /* FMAX */
10988 case 0x38: /* FMINNM */
10989 case 0x3a: /* FSUB */
10990 case 0x3e: /* FMIN */
10991 case 0x5b: /* FMUL */
10992 case 0x5c: /* FCMGE */
10993 case 0x5f: /* FDIV */
10994 case 0x7a: /* FABD */
10995 case 0x7c: /* FCMGT */
10996 if (!fp_access_check(s
)) {
10999 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11002 case 0x1d: /* FMLAL */
11003 case 0x3d: /* FMLSL */
11004 case 0x59: /* FMLAL2 */
11005 case 0x79: /* FMLSL2 */
11006 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11007 unallocated_encoding(s
);
11010 if (fp_access_check(s
)) {
11011 int is_s
= extract32(insn
, 23, 1);
11012 int is_2
= extract32(insn
, 29, 1);
11013 int data
= (is_2
<< 1) | is_s
;
11014 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11015 vec_full_reg_offset(s
, rn
),
11016 vec_full_reg_offset(s
, rm
), cpu_env
,
11017 is_q
? 16 : 8, vec_full_reg_size(s
),
11018 data
, gen_helper_gvec_fmlal_a64
);
11023 unallocated_encoding(s
);
11028 /* Integer op subgroup of C3.6.16. */
11029 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11031 int is_q
= extract32(insn
, 30, 1);
11032 int u
= extract32(insn
, 29, 1);
11033 int size
= extract32(insn
, 22, 2);
11034 int opcode
= extract32(insn
, 11, 5);
11035 int rm
= extract32(insn
, 16, 5);
11036 int rn
= extract32(insn
, 5, 5);
11037 int rd
= extract32(insn
, 0, 5);
11042 case 0x13: /* MUL, PMUL */
11043 if (u
&& size
!= 0) {
11044 unallocated_encoding(s
);
11048 case 0x0: /* SHADD, UHADD */
11049 case 0x2: /* SRHADD, URHADD */
11050 case 0x4: /* SHSUB, UHSUB */
11051 case 0xc: /* SMAX, UMAX */
11052 case 0xd: /* SMIN, UMIN */
11053 case 0xe: /* SABD, UABD */
11054 case 0xf: /* SABA, UABA */
11055 case 0x12: /* MLA, MLS */
11057 unallocated_encoding(s
);
11061 case 0x16: /* SQDMULH, SQRDMULH */
11062 if (size
== 0 || size
== 3) {
11063 unallocated_encoding(s
);
11068 if (size
== 3 && !is_q
) {
11069 unallocated_encoding(s
);
11075 if (!fp_access_check(s
)) {
11080 case 0x01: /* SQADD, UQADD */
11081 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11082 offsetof(CPUARMState
, vfp
.qc
),
11083 vec_full_reg_offset(s
, rn
),
11084 vec_full_reg_offset(s
, rm
),
11085 is_q
? 16 : 8, vec_full_reg_size(s
),
11086 (u
? uqadd_op
: sqadd_op
) + size
);
11088 case 0x05: /* SQSUB, UQSUB */
11089 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11090 offsetof(CPUARMState
, vfp
.qc
),
11091 vec_full_reg_offset(s
, rn
),
11092 vec_full_reg_offset(s
, rm
),
11093 is_q
? 16 : 8, vec_full_reg_size(s
),
11094 (u
? uqsub_op
: sqsub_op
) + size
);
11096 case 0x0c: /* SMAX, UMAX */
11098 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11100 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11103 case 0x0d: /* SMIN, UMIN */
11105 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11107 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11110 case 0x10: /* ADD, SUB */
11112 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11114 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11117 case 0x13: /* MUL, PMUL */
11118 if (!u
) { /* MUL */
11119 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11123 case 0x12: /* MLA, MLS */
11125 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11127 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11131 if (!u
) { /* CMTST */
11132 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11136 cond
= TCG_COND_EQ
;
11138 case 0x06: /* CMGT, CMHI */
11139 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11141 case 0x07: /* CMGE, CMHS */
11142 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11144 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11145 vec_full_reg_offset(s
, rn
),
11146 vec_full_reg_offset(s
, rm
),
11147 is_q
? 16 : 8, vec_full_reg_size(s
));
11153 for (pass
= 0; pass
< 2; pass
++) {
11154 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11155 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11156 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11158 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11159 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11161 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11163 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11165 tcg_temp_free_i64(tcg_res
);
11166 tcg_temp_free_i64(tcg_op1
);
11167 tcg_temp_free_i64(tcg_op2
);
11170 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11171 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11172 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11173 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11174 NeonGenTwoOpFn
*genfn
= NULL
;
11175 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11177 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11178 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11181 case 0x0: /* SHADD, UHADD */
11183 static NeonGenTwoOpFn
* const fns
[3][2] = {
11184 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11185 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11186 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11188 genfn
= fns
[size
][u
];
11191 case 0x2: /* SRHADD, URHADD */
11193 static NeonGenTwoOpFn
* const fns
[3][2] = {
11194 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11195 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11196 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11198 genfn
= fns
[size
][u
];
11201 case 0x4: /* SHSUB, UHSUB */
11203 static NeonGenTwoOpFn
* const fns
[3][2] = {
11204 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11205 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11206 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11208 genfn
= fns
[size
][u
];
11211 case 0x8: /* SSHL, USHL */
11213 static NeonGenTwoOpFn
* const fns
[3][2] = {
11214 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11215 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11216 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11218 genfn
= fns
[size
][u
];
11221 case 0x9: /* SQSHL, UQSHL */
11223 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11224 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11225 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11226 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11228 genenvfn
= fns
[size
][u
];
11231 case 0xa: /* SRSHL, URSHL */
11233 static NeonGenTwoOpFn
* const fns
[3][2] = {
11234 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11235 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11236 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11238 genfn
= fns
[size
][u
];
11241 case 0xb: /* SQRSHL, UQRSHL */
11243 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11244 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11245 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11246 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11248 genenvfn
= fns
[size
][u
];
11251 case 0xe: /* SABD, UABD */
11252 case 0xf: /* SABA, UABA */
11254 static NeonGenTwoOpFn
* const fns
[3][2] = {
11255 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11256 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11257 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11259 genfn
= fns
[size
][u
];
11262 case 0x13: /* MUL, PMUL */
11263 assert(u
); /* PMUL */
11265 genfn
= gen_helper_neon_mul_p8
;
11267 case 0x16: /* SQDMULH, SQRDMULH */
11269 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11270 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11271 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11273 assert(size
== 1 || size
== 2);
11274 genenvfn
= fns
[size
- 1][u
];
11278 g_assert_not_reached();
11282 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11284 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11287 if (opcode
== 0xf) {
11288 /* SABA, UABA: accumulating ops */
11289 static NeonGenTwoOpFn
* const fns
[3] = {
11290 gen_helper_neon_add_u8
,
11291 gen_helper_neon_add_u16
,
11295 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11296 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11299 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11301 tcg_temp_free_i32(tcg_res
);
11302 tcg_temp_free_i32(tcg_op1
);
11303 tcg_temp_free_i32(tcg_op2
);
11306 clear_vec_high(s
, is_q
, rd
);
11309 /* AdvSIMD three same
11310 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11311 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11312 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11313 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11315 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11317 int opcode
= extract32(insn
, 11, 5);
11320 case 0x3: /* logic ops */
11321 disas_simd_3same_logic(s
, insn
);
11323 case 0x17: /* ADDP */
11324 case 0x14: /* SMAXP, UMAXP */
11325 case 0x15: /* SMINP, UMINP */
11327 /* Pairwise operations */
11328 int is_q
= extract32(insn
, 30, 1);
11329 int u
= extract32(insn
, 29, 1);
11330 int size
= extract32(insn
, 22, 2);
11331 int rm
= extract32(insn
, 16, 5);
11332 int rn
= extract32(insn
, 5, 5);
11333 int rd
= extract32(insn
, 0, 5);
11334 if (opcode
== 0x17) {
11335 if (u
|| (size
== 3 && !is_q
)) {
11336 unallocated_encoding(s
);
11341 unallocated_encoding(s
);
11345 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11348 case 0x18 ... 0x31:
11349 /* floating point ops, sz[1] and U are part of opcode */
11350 disas_simd_3same_float(s
, insn
);
11353 disas_simd_3same_int(s
, insn
);
11359 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11361 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11362 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11363 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11364 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11366 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11367 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11370 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11372 int opcode
, fpopcode
;
11373 int is_q
, u
, a
, rm
, rn
, rd
;
11374 int datasize
, elements
;
11377 bool pairwise
= false;
11379 if (!dc_isar_feature(aa64_fp16
, s
)) {
11380 unallocated_encoding(s
);
11384 if (!fp_access_check(s
)) {
11388 /* For these floating point ops, the U, a and opcode bits
11389 * together indicate the operation.
11391 opcode
= extract32(insn
, 11, 3);
11392 u
= extract32(insn
, 29, 1);
11393 a
= extract32(insn
, 23, 1);
11394 is_q
= extract32(insn
, 30, 1);
11395 rm
= extract32(insn
, 16, 5);
11396 rn
= extract32(insn
, 5, 5);
11397 rd
= extract32(insn
, 0, 5);
11399 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11400 datasize
= is_q
? 128 : 64;
11401 elements
= datasize
/ 16;
11403 switch (fpopcode
) {
11404 case 0x10: /* FMAXNMP */
11405 case 0x12: /* FADDP */
11406 case 0x16: /* FMAXP */
11407 case 0x18: /* FMINNMP */
11408 case 0x1e: /* FMINP */
11413 fpst
= get_fpstatus_ptr(true);
11416 int maxpass
= is_q
? 8 : 4;
11417 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11418 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11419 TCGv_i32 tcg_res
[8];
11421 for (pass
= 0; pass
< maxpass
; pass
++) {
11422 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11423 int passelt
= (pass
<< 1) & (maxpass
- 1);
11425 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11426 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11427 tcg_res
[pass
] = tcg_temp_new_i32();
11429 switch (fpopcode
) {
11430 case 0x10: /* FMAXNMP */
11431 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11434 case 0x12: /* FADDP */
11435 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11437 case 0x16: /* FMAXP */
11438 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11440 case 0x18: /* FMINNMP */
11441 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11444 case 0x1e: /* FMINP */
11445 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11448 g_assert_not_reached();
11452 for (pass
= 0; pass
< maxpass
; pass
++) {
11453 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11454 tcg_temp_free_i32(tcg_res
[pass
]);
11457 tcg_temp_free_i32(tcg_op1
);
11458 tcg_temp_free_i32(tcg_op2
);
11461 for (pass
= 0; pass
< elements
; pass
++) {
11462 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11463 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11464 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11466 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11467 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11469 switch (fpopcode
) {
11470 case 0x0: /* FMAXNM */
11471 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11473 case 0x1: /* FMLA */
11474 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11475 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11478 case 0x2: /* FADD */
11479 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11481 case 0x3: /* FMULX */
11482 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11484 case 0x4: /* FCMEQ */
11485 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11487 case 0x6: /* FMAX */
11488 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11490 case 0x7: /* FRECPS */
11491 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11493 case 0x8: /* FMINNM */
11494 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11496 case 0x9: /* FMLS */
11497 /* As usual for ARM, separate negation for fused multiply-add */
11498 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11499 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11500 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11503 case 0xa: /* FSUB */
11504 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11506 case 0xe: /* FMIN */
11507 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11509 case 0xf: /* FRSQRTS */
11510 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11512 case 0x13: /* FMUL */
11513 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11515 case 0x14: /* FCMGE */
11516 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11518 case 0x15: /* FACGE */
11519 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11521 case 0x17: /* FDIV */
11522 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11524 case 0x1a: /* FABD */
11525 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11526 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11528 case 0x1c: /* FCMGT */
11529 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11531 case 0x1d: /* FACGT */
11532 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11535 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11536 __func__
, insn
, fpopcode
, s
->pc
);
11537 g_assert_not_reached();
11540 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11541 tcg_temp_free_i32(tcg_res
);
11542 tcg_temp_free_i32(tcg_op1
);
11543 tcg_temp_free_i32(tcg_op2
);
11547 tcg_temp_free_ptr(fpst
);
11549 clear_vec_high(s
, is_q
, rd
);
11552 /* AdvSIMD three same extra
11553 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11554 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11555 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11556 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11558 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11560 int rd
= extract32(insn
, 0, 5);
11561 int rn
= extract32(insn
, 5, 5);
11562 int opcode
= extract32(insn
, 11, 4);
11563 int rm
= extract32(insn
, 16, 5);
11564 int size
= extract32(insn
, 22, 2);
11565 bool u
= extract32(insn
, 29, 1);
11566 bool is_q
= extract32(insn
, 30, 1);
11570 switch (u
* 16 + opcode
) {
11571 case 0x10: /* SQRDMLAH (vector) */
11572 case 0x11: /* SQRDMLSH (vector) */
11573 if (size
!= 1 && size
!= 2) {
11574 unallocated_encoding(s
);
11577 feature
= dc_isar_feature(aa64_rdm
, s
);
11579 case 0x02: /* SDOT (vector) */
11580 case 0x12: /* UDOT (vector) */
11581 if (size
!= MO_32
) {
11582 unallocated_encoding(s
);
11585 feature
= dc_isar_feature(aa64_dp
, s
);
11587 case 0x18: /* FCMLA, #0 */
11588 case 0x19: /* FCMLA, #90 */
11589 case 0x1a: /* FCMLA, #180 */
11590 case 0x1b: /* FCMLA, #270 */
11591 case 0x1c: /* FCADD, #90 */
11592 case 0x1e: /* FCADD, #270 */
11594 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11595 || (size
== 3 && !is_q
)) {
11596 unallocated_encoding(s
);
11599 feature
= dc_isar_feature(aa64_fcma
, s
);
11602 unallocated_encoding(s
);
11606 unallocated_encoding(s
);
11609 if (!fp_access_check(s
)) {
11614 case 0x0: /* SQRDMLAH (vector) */
11617 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11620 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11623 g_assert_not_reached();
11627 case 0x1: /* SQRDMLSH (vector) */
11630 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11633 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11636 g_assert_not_reached();
11640 case 0x2: /* SDOT / UDOT */
11641 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11642 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11645 case 0x8: /* FCMLA, #0 */
11646 case 0x9: /* FCMLA, #90 */
11647 case 0xa: /* FCMLA, #180 */
11648 case 0xb: /* FCMLA, #270 */
11649 rot
= extract32(opcode
, 0, 2);
11652 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11653 gen_helper_gvec_fcmlah
);
11656 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11657 gen_helper_gvec_fcmlas
);
11660 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11661 gen_helper_gvec_fcmlad
);
11664 g_assert_not_reached();
11668 case 0xc: /* FCADD, #90 */
11669 case 0xe: /* FCADD, #270 */
11670 rot
= extract32(opcode
, 1, 1);
11673 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11674 gen_helper_gvec_fcaddh
);
11677 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11678 gen_helper_gvec_fcadds
);
11681 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11682 gen_helper_gvec_fcaddd
);
11685 g_assert_not_reached();
11690 g_assert_not_reached();
11694 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11695 int size
, int rn
, int rd
)
11697 /* Handle 2-reg-misc ops which are widening (so each size element
11698 * in the source becomes a 2*size element in the destination.
11699 * The only instruction like this is FCVTL.
11704 /* 32 -> 64 bit fp conversion */
11705 TCGv_i64 tcg_res
[2];
11706 int srcelt
= is_q
? 2 : 0;
11708 for (pass
= 0; pass
< 2; pass
++) {
11709 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11710 tcg_res
[pass
] = tcg_temp_new_i64();
11712 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11713 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11714 tcg_temp_free_i32(tcg_op
);
11716 for (pass
= 0; pass
< 2; pass
++) {
11717 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11718 tcg_temp_free_i64(tcg_res
[pass
]);
11721 /* 16 -> 32 bit fp conversion */
11722 int srcelt
= is_q
? 4 : 0;
11723 TCGv_i32 tcg_res
[4];
11724 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11725 TCGv_i32 ahp
= get_ahp_flag();
11727 for (pass
= 0; pass
< 4; pass
++) {
11728 tcg_res
[pass
] = tcg_temp_new_i32();
11730 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11731 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11734 for (pass
= 0; pass
< 4; pass
++) {
11735 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11736 tcg_temp_free_i32(tcg_res
[pass
]);
11739 tcg_temp_free_ptr(fpst
);
11740 tcg_temp_free_i32(ahp
);
11744 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11745 bool is_q
, int size
, int rn
, int rd
)
11747 int op
= (opcode
<< 1) | u
;
11748 int opsz
= op
+ size
;
11749 int grp_size
= 3 - opsz
;
11750 int dsize
= is_q
? 128 : 64;
11754 unallocated_encoding(s
);
11758 if (!fp_access_check(s
)) {
11763 /* Special case bytes, use bswap op on each group of elements */
11764 int groups
= dsize
/ (8 << grp_size
);
11766 for (i
= 0; i
< groups
; i
++) {
11767 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11769 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11770 switch (grp_size
) {
11772 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11775 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11778 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11781 g_assert_not_reached();
11783 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11784 tcg_temp_free_i64(tcg_tmp
);
11786 clear_vec_high(s
, is_q
, rd
);
11788 int revmask
= (1 << grp_size
) - 1;
11789 int esize
= 8 << size
;
11790 int elements
= dsize
/ esize
;
11791 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11792 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11793 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11795 for (i
= 0; i
< elements
; i
++) {
11796 int e_rev
= (i
& 0xf) ^ revmask
;
11797 int off
= e_rev
* esize
;
11798 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11800 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11801 tcg_rn
, off
- 64, esize
);
11803 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11806 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11807 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11809 tcg_temp_free_i64(tcg_rd_hi
);
11810 tcg_temp_free_i64(tcg_rd
);
11811 tcg_temp_free_i64(tcg_rn
);
11815 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11816 bool is_q
, int size
, int rn
, int rd
)
11818 /* Implement the pairwise operations from 2-misc:
11819 * SADDLP, UADDLP, SADALP, UADALP.
11820 * These all add pairs of elements in the input to produce a
11821 * double-width result element in the output (possibly accumulating).
11823 bool accum
= (opcode
== 0x6);
11824 int maxpass
= is_q
? 2 : 1;
11826 TCGv_i64 tcg_res
[2];
11829 /* 32 + 32 -> 64 op */
11830 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11832 for (pass
= 0; pass
< maxpass
; pass
++) {
11833 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11834 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11836 tcg_res
[pass
] = tcg_temp_new_i64();
11838 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11839 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11840 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11842 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11843 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11846 tcg_temp_free_i64(tcg_op1
);
11847 tcg_temp_free_i64(tcg_op2
);
11850 for (pass
= 0; pass
< maxpass
; pass
++) {
11851 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11852 NeonGenOneOpFn
*genfn
;
11853 static NeonGenOneOpFn
* const fns
[2][2] = {
11854 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11855 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11858 genfn
= fns
[size
][u
];
11860 tcg_res
[pass
] = tcg_temp_new_i64();
11862 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11863 genfn(tcg_res
[pass
], tcg_op
);
11866 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11868 gen_helper_neon_addl_u16(tcg_res
[pass
],
11869 tcg_res
[pass
], tcg_op
);
11871 gen_helper_neon_addl_u32(tcg_res
[pass
],
11872 tcg_res
[pass
], tcg_op
);
11875 tcg_temp_free_i64(tcg_op
);
11879 tcg_res
[1] = tcg_const_i64(0);
11881 for (pass
= 0; pass
< 2; pass
++) {
11882 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11883 tcg_temp_free_i64(tcg_res
[pass
]);
11887 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11889 /* Implement SHLL and SHLL2 */
11891 int part
= is_q
? 2 : 0;
11892 TCGv_i64 tcg_res
[2];
11894 for (pass
= 0; pass
< 2; pass
++) {
11895 static NeonGenWidenFn
* const widenfns
[3] = {
11896 gen_helper_neon_widen_u8
,
11897 gen_helper_neon_widen_u16
,
11898 tcg_gen_extu_i32_i64
,
11900 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11901 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11903 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11904 tcg_res
[pass
] = tcg_temp_new_i64();
11905 widenfn(tcg_res
[pass
], tcg_op
);
11906 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11908 tcg_temp_free_i32(tcg_op
);
11911 for (pass
= 0; pass
< 2; pass
++) {
11912 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11913 tcg_temp_free_i64(tcg_res
[pass
]);
11917 /* AdvSIMD two reg misc
11918 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11919 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11920 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11921 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11923 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11925 int size
= extract32(insn
, 22, 2);
11926 int opcode
= extract32(insn
, 12, 5);
11927 bool u
= extract32(insn
, 29, 1);
11928 bool is_q
= extract32(insn
, 30, 1);
11929 int rn
= extract32(insn
, 5, 5);
11930 int rd
= extract32(insn
, 0, 5);
11931 bool need_fpstatus
= false;
11932 bool need_rmode
= false;
11934 TCGv_i32 tcg_rmode
;
11935 TCGv_ptr tcg_fpstatus
;
11938 case 0x0: /* REV64, REV32 */
11939 case 0x1: /* REV16 */
11940 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11942 case 0x5: /* CNT, NOT, RBIT */
11943 if (u
&& size
== 0) {
11946 } else if (u
&& size
== 1) {
11949 } else if (!u
&& size
== 0) {
11953 unallocated_encoding(s
);
11955 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11956 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11958 unallocated_encoding(s
);
11961 if (!fp_access_check(s
)) {
11965 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11967 case 0x4: /* CLS, CLZ */
11969 unallocated_encoding(s
);
11973 case 0x2: /* SADDLP, UADDLP */
11974 case 0x6: /* SADALP, UADALP */
11976 unallocated_encoding(s
);
11979 if (!fp_access_check(s
)) {
11982 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11984 case 0x13: /* SHLL, SHLL2 */
11985 if (u
== 0 || size
== 3) {
11986 unallocated_encoding(s
);
11989 if (!fp_access_check(s
)) {
11992 handle_shll(s
, is_q
, size
, rn
, rd
);
11994 case 0xa: /* CMLT */
11996 unallocated_encoding(s
);
12000 case 0x8: /* CMGT, CMGE */
12001 case 0x9: /* CMEQ, CMLE */
12002 case 0xb: /* ABS, NEG */
12003 if (size
== 3 && !is_q
) {
12004 unallocated_encoding(s
);
12008 case 0x3: /* SUQADD, USQADD */
12009 if (size
== 3 && !is_q
) {
12010 unallocated_encoding(s
);
12013 if (!fp_access_check(s
)) {
12016 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12018 case 0x7: /* SQABS, SQNEG */
12019 if (size
== 3 && !is_q
) {
12020 unallocated_encoding(s
);
12025 case 0x16 ... 0x1f:
12027 /* Floating point: U, size[1] and opcode indicate operation;
12028 * size[0] indicates single or double precision.
12030 int is_double
= extract32(size
, 0, 1);
12031 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12032 size
= is_double
? 3 : 2;
12034 case 0x2f: /* FABS */
12035 case 0x6f: /* FNEG */
12036 if (size
== 3 && !is_q
) {
12037 unallocated_encoding(s
);
12041 case 0x1d: /* SCVTF */
12042 case 0x5d: /* UCVTF */
12044 bool is_signed
= (opcode
== 0x1d) ? true : false;
12045 int elements
= is_double
? 2 : is_q
? 4 : 2;
12046 if (is_double
&& !is_q
) {
12047 unallocated_encoding(s
);
12050 if (!fp_access_check(s
)) {
12053 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12056 case 0x2c: /* FCMGT (zero) */
12057 case 0x2d: /* FCMEQ (zero) */
12058 case 0x2e: /* FCMLT (zero) */
12059 case 0x6c: /* FCMGE (zero) */
12060 case 0x6d: /* FCMLE (zero) */
12061 if (size
== 3 && !is_q
) {
12062 unallocated_encoding(s
);
12065 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12067 case 0x7f: /* FSQRT */
12068 if (size
== 3 && !is_q
) {
12069 unallocated_encoding(s
);
12073 case 0x1a: /* FCVTNS */
12074 case 0x1b: /* FCVTMS */
12075 case 0x3a: /* FCVTPS */
12076 case 0x3b: /* FCVTZS */
12077 case 0x5a: /* FCVTNU */
12078 case 0x5b: /* FCVTMU */
12079 case 0x7a: /* FCVTPU */
12080 case 0x7b: /* FCVTZU */
12081 need_fpstatus
= true;
12083 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12084 if (size
== 3 && !is_q
) {
12085 unallocated_encoding(s
);
12089 case 0x5c: /* FCVTAU */
12090 case 0x1c: /* FCVTAS */
12091 need_fpstatus
= true;
12093 rmode
= FPROUNDING_TIEAWAY
;
12094 if (size
== 3 && !is_q
) {
12095 unallocated_encoding(s
);
12099 case 0x3c: /* URECPE */
12101 unallocated_encoding(s
);
12105 case 0x3d: /* FRECPE */
12106 case 0x7d: /* FRSQRTE */
12107 if (size
== 3 && !is_q
) {
12108 unallocated_encoding(s
);
12111 if (!fp_access_check(s
)) {
12114 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12116 case 0x56: /* FCVTXN, FCVTXN2 */
12118 unallocated_encoding(s
);
12122 case 0x16: /* FCVTN, FCVTN2 */
12123 /* handle_2misc_narrow does a 2*size -> size operation, but these
12124 * instructions encode the source size rather than dest size.
12126 if (!fp_access_check(s
)) {
12129 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12131 case 0x17: /* FCVTL, FCVTL2 */
12132 if (!fp_access_check(s
)) {
12135 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12137 case 0x18: /* FRINTN */
12138 case 0x19: /* FRINTM */
12139 case 0x38: /* FRINTP */
12140 case 0x39: /* FRINTZ */
12142 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12144 case 0x59: /* FRINTX */
12145 case 0x79: /* FRINTI */
12146 need_fpstatus
= true;
12147 if (size
== 3 && !is_q
) {
12148 unallocated_encoding(s
);
12152 case 0x58: /* FRINTA */
12154 rmode
= FPROUNDING_TIEAWAY
;
12155 need_fpstatus
= true;
12156 if (size
== 3 && !is_q
) {
12157 unallocated_encoding(s
);
12161 case 0x7c: /* URSQRTE */
12163 unallocated_encoding(s
);
12166 need_fpstatus
= true;
12168 case 0x1e: /* FRINT32Z */
12169 case 0x1f: /* FRINT64Z */
12171 rmode
= FPROUNDING_ZERO
;
12173 case 0x5e: /* FRINT32X */
12174 case 0x5f: /* FRINT64X */
12175 need_fpstatus
= true;
12176 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12177 unallocated_encoding(s
);
12182 unallocated_encoding(s
);
12188 unallocated_encoding(s
);
12192 if (!fp_access_check(s
)) {
12196 if (need_fpstatus
|| need_rmode
) {
12197 tcg_fpstatus
= get_fpstatus_ptr(false);
12199 tcg_fpstatus
= NULL
;
12202 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12203 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12210 if (u
&& size
== 0) { /* NOT */
12211 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12216 if (u
) { /* ABS, NEG */
12217 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12219 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12225 /* All 64-bit element operations can be shared with scalar 2misc */
12228 /* Coverity claims (size == 3 && !is_q) has been eliminated
12229 * from all paths leading to here.
12231 tcg_debug_assert(is_q
);
12232 for (pass
= 0; pass
< 2; pass
++) {
12233 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12234 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12236 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12238 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12239 tcg_rmode
, tcg_fpstatus
);
12241 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12243 tcg_temp_free_i64(tcg_res
);
12244 tcg_temp_free_i64(tcg_op
);
12249 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12250 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12251 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12254 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12257 /* Special cases for 32 bit elements */
12259 case 0xa: /* CMLT */
12260 /* 32 bit integer comparison against zero, result is
12261 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12264 cond
= TCG_COND_LT
;
12266 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12267 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12269 case 0x8: /* CMGT, CMGE */
12270 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12272 case 0x9: /* CMEQ, CMLE */
12273 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12275 case 0x4: /* CLS */
12277 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12279 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12282 case 0x7: /* SQABS, SQNEG */
12284 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12286 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12289 case 0x2f: /* FABS */
12290 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12292 case 0x6f: /* FNEG */
12293 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12295 case 0x7f: /* FSQRT */
12296 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12298 case 0x1a: /* FCVTNS */
12299 case 0x1b: /* FCVTMS */
12300 case 0x1c: /* FCVTAS */
12301 case 0x3a: /* FCVTPS */
12302 case 0x3b: /* FCVTZS */
12304 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12305 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12306 tcg_shift
, tcg_fpstatus
);
12307 tcg_temp_free_i32(tcg_shift
);
12310 case 0x5a: /* FCVTNU */
12311 case 0x5b: /* FCVTMU */
12312 case 0x5c: /* FCVTAU */
12313 case 0x7a: /* FCVTPU */
12314 case 0x7b: /* FCVTZU */
12316 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12317 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12318 tcg_shift
, tcg_fpstatus
);
12319 tcg_temp_free_i32(tcg_shift
);
12322 case 0x18: /* FRINTN */
12323 case 0x19: /* FRINTM */
12324 case 0x38: /* FRINTP */
12325 case 0x39: /* FRINTZ */
12326 case 0x58: /* FRINTA */
12327 case 0x79: /* FRINTI */
12328 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12330 case 0x59: /* FRINTX */
12331 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12333 case 0x7c: /* URSQRTE */
12334 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12336 case 0x1e: /* FRINT32Z */
12337 case 0x5e: /* FRINT32X */
12338 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12340 case 0x1f: /* FRINT64Z */
12341 case 0x5f: /* FRINT64X */
12342 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12345 g_assert_not_reached();
12348 /* Use helpers for 8 and 16 bit elements */
12350 case 0x5: /* CNT, RBIT */
12351 /* For these two insns size is part of the opcode specifier
12352 * (handled earlier); they always operate on byte elements.
12355 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12357 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12360 case 0x7: /* SQABS, SQNEG */
12362 NeonGenOneOpEnvFn
*genfn
;
12363 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12364 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12365 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12367 genfn
= fns
[size
][u
];
12368 genfn(tcg_res
, cpu_env
, tcg_op
);
12371 case 0x8: /* CMGT, CMGE */
12372 case 0x9: /* CMEQ, CMLE */
12373 case 0xa: /* CMLT */
12375 static NeonGenTwoOpFn
* const fns
[3][2] = {
12376 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12377 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12378 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12380 NeonGenTwoOpFn
*genfn
;
12383 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12385 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12386 comp
= (opcode
- 0x8) * 2 + u
;
12387 /* ...but LE, LT are implemented as reverse GE, GT */
12388 reverse
= (comp
> 2);
12392 genfn
= fns
[comp
][size
];
12394 genfn(tcg_res
, tcg_zero
, tcg_op
);
12396 genfn(tcg_res
, tcg_op
, tcg_zero
);
12398 tcg_temp_free_i32(tcg_zero
);
12401 case 0x4: /* CLS, CLZ */
12404 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12406 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12410 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12412 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12417 g_assert_not_reached();
12421 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12423 tcg_temp_free_i32(tcg_res
);
12424 tcg_temp_free_i32(tcg_op
);
12427 clear_vec_high(s
, is_q
, rd
);
12430 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12431 tcg_temp_free_i32(tcg_rmode
);
12433 if (need_fpstatus
) {
12434 tcg_temp_free_ptr(tcg_fpstatus
);
12438 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12440 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12441 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12442 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12443 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12444 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12445 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12447 * This actually covers two groups where scalar access is governed by
12448 * bit 28. A bunch of the instructions (float to integral) only exist
12449 * in the vector form and are un-allocated for the scalar decode. Also
12450 * in the scalar decode Q is always 1.
12452 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12454 int fpop
, opcode
, a
, u
;
12458 bool only_in_vector
= false;
12461 TCGv_i32 tcg_rmode
= NULL
;
12462 TCGv_ptr tcg_fpstatus
= NULL
;
12463 bool need_rmode
= false;
12464 bool need_fpst
= true;
12467 if (!dc_isar_feature(aa64_fp16
, s
)) {
12468 unallocated_encoding(s
);
12472 rd
= extract32(insn
, 0, 5);
12473 rn
= extract32(insn
, 5, 5);
12475 a
= extract32(insn
, 23, 1);
12476 u
= extract32(insn
, 29, 1);
12477 is_scalar
= extract32(insn
, 28, 1);
12478 is_q
= extract32(insn
, 30, 1);
12480 opcode
= extract32(insn
, 12, 5);
12481 fpop
= deposit32(opcode
, 5, 1, a
);
12482 fpop
= deposit32(fpop
, 6, 1, u
);
12484 rd
= extract32(insn
, 0, 5);
12485 rn
= extract32(insn
, 5, 5);
12488 case 0x1d: /* SCVTF */
12489 case 0x5d: /* UCVTF */
12496 elements
= (is_q
? 8 : 4);
12499 if (!fp_access_check(s
)) {
12502 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12506 case 0x2c: /* FCMGT (zero) */
12507 case 0x2d: /* FCMEQ (zero) */
12508 case 0x2e: /* FCMLT (zero) */
12509 case 0x6c: /* FCMGE (zero) */
12510 case 0x6d: /* FCMLE (zero) */
12511 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12513 case 0x3d: /* FRECPE */
12514 case 0x3f: /* FRECPX */
12516 case 0x18: /* FRINTN */
12518 only_in_vector
= true;
12519 rmode
= FPROUNDING_TIEEVEN
;
12521 case 0x19: /* FRINTM */
12523 only_in_vector
= true;
12524 rmode
= FPROUNDING_NEGINF
;
12526 case 0x38: /* FRINTP */
12528 only_in_vector
= true;
12529 rmode
= FPROUNDING_POSINF
;
12531 case 0x39: /* FRINTZ */
12533 only_in_vector
= true;
12534 rmode
= FPROUNDING_ZERO
;
12536 case 0x58: /* FRINTA */
12538 only_in_vector
= true;
12539 rmode
= FPROUNDING_TIEAWAY
;
12541 case 0x59: /* FRINTX */
12542 case 0x79: /* FRINTI */
12543 only_in_vector
= true;
12544 /* current rounding mode */
12546 case 0x1a: /* FCVTNS */
12548 rmode
= FPROUNDING_TIEEVEN
;
12550 case 0x1b: /* FCVTMS */
12552 rmode
= FPROUNDING_NEGINF
;
12554 case 0x1c: /* FCVTAS */
12556 rmode
= FPROUNDING_TIEAWAY
;
12558 case 0x3a: /* FCVTPS */
12560 rmode
= FPROUNDING_POSINF
;
12562 case 0x3b: /* FCVTZS */
12564 rmode
= FPROUNDING_ZERO
;
12566 case 0x5a: /* FCVTNU */
12568 rmode
= FPROUNDING_TIEEVEN
;
12570 case 0x5b: /* FCVTMU */
12572 rmode
= FPROUNDING_NEGINF
;
12574 case 0x5c: /* FCVTAU */
12576 rmode
= FPROUNDING_TIEAWAY
;
12578 case 0x7a: /* FCVTPU */
12580 rmode
= FPROUNDING_POSINF
;
12582 case 0x7b: /* FCVTZU */
12584 rmode
= FPROUNDING_ZERO
;
12586 case 0x2f: /* FABS */
12587 case 0x6f: /* FNEG */
12590 case 0x7d: /* FRSQRTE */
12591 case 0x7f: /* FSQRT (vector) */
12594 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12595 g_assert_not_reached();
12599 /* Check additional constraints for the scalar encoding */
12602 unallocated_encoding(s
);
12605 /* FRINTxx is only in the vector form */
12606 if (only_in_vector
) {
12607 unallocated_encoding(s
);
12612 if (!fp_access_check(s
)) {
12616 if (need_rmode
|| need_fpst
) {
12617 tcg_fpstatus
= get_fpstatus_ptr(true);
12621 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12622 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12626 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12627 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12630 case 0x1a: /* FCVTNS */
12631 case 0x1b: /* FCVTMS */
12632 case 0x1c: /* FCVTAS */
12633 case 0x3a: /* FCVTPS */
12634 case 0x3b: /* FCVTZS */
12635 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12637 case 0x3d: /* FRECPE */
12638 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12640 case 0x3f: /* FRECPX */
12641 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12643 case 0x5a: /* FCVTNU */
12644 case 0x5b: /* FCVTMU */
12645 case 0x5c: /* FCVTAU */
12646 case 0x7a: /* FCVTPU */
12647 case 0x7b: /* FCVTZU */
12648 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12650 case 0x6f: /* FNEG */
12651 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12653 case 0x7d: /* FRSQRTE */
12654 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12657 g_assert_not_reached();
12660 /* limit any sign extension going on */
12661 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12662 write_fp_sreg(s
, rd
, tcg_res
);
12664 tcg_temp_free_i32(tcg_res
);
12665 tcg_temp_free_i32(tcg_op
);
12667 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12668 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12669 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12671 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12674 case 0x1a: /* FCVTNS */
12675 case 0x1b: /* FCVTMS */
12676 case 0x1c: /* FCVTAS */
12677 case 0x3a: /* FCVTPS */
12678 case 0x3b: /* FCVTZS */
12679 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12681 case 0x3d: /* FRECPE */
12682 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12684 case 0x5a: /* FCVTNU */
12685 case 0x5b: /* FCVTMU */
12686 case 0x5c: /* FCVTAU */
12687 case 0x7a: /* FCVTPU */
12688 case 0x7b: /* FCVTZU */
12689 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12691 case 0x18: /* FRINTN */
12692 case 0x19: /* FRINTM */
12693 case 0x38: /* FRINTP */
12694 case 0x39: /* FRINTZ */
12695 case 0x58: /* FRINTA */
12696 case 0x79: /* FRINTI */
12697 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12699 case 0x59: /* FRINTX */
12700 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12702 case 0x2f: /* FABS */
12703 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12705 case 0x6f: /* FNEG */
12706 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12708 case 0x7d: /* FRSQRTE */
12709 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12711 case 0x7f: /* FSQRT */
12712 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12715 g_assert_not_reached();
12718 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12720 tcg_temp_free_i32(tcg_res
);
12721 tcg_temp_free_i32(tcg_op
);
12724 clear_vec_high(s
, is_q
, rd
);
12728 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12729 tcg_temp_free_i32(tcg_rmode
);
12732 if (tcg_fpstatus
) {
12733 tcg_temp_free_ptr(tcg_fpstatus
);
12737 /* AdvSIMD scalar x indexed element
12738 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12739 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12740 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12741 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12742 * AdvSIMD vector x indexed element
12743 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12744 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12745 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12746 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12748 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12750 /* This encoding has two kinds of instruction:
12751 * normal, where we perform elt x idxelt => elt for each
12752 * element in the vector
12753 * long, where we perform elt x idxelt and generate a result of
12754 * double the width of the input element
12755 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12757 bool is_scalar
= extract32(insn
, 28, 1);
12758 bool is_q
= extract32(insn
, 30, 1);
12759 bool u
= extract32(insn
, 29, 1);
12760 int size
= extract32(insn
, 22, 2);
12761 int l
= extract32(insn
, 21, 1);
12762 int m
= extract32(insn
, 20, 1);
12763 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12764 int rm
= extract32(insn
, 16, 4);
12765 int opcode
= extract32(insn
, 12, 4);
12766 int h
= extract32(insn
, 11, 1);
12767 int rn
= extract32(insn
, 5, 5);
12768 int rd
= extract32(insn
, 0, 5);
12769 bool is_long
= false;
12771 bool is_fp16
= false;
12775 switch (16 * u
+ opcode
) {
12776 case 0x08: /* MUL */
12777 case 0x10: /* MLA */
12778 case 0x14: /* MLS */
12780 unallocated_encoding(s
);
12784 case 0x02: /* SMLAL, SMLAL2 */
12785 case 0x12: /* UMLAL, UMLAL2 */
12786 case 0x06: /* SMLSL, SMLSL2 */
12787 case 0x16: /* UMLSL, UMLSL2 */
12788 case 0x0a: /* SMULL, SMULL2 */
12789 case 0x1a: /* UMULL, UMULL2 */
12791 unallocated_encoding(s
);
12796 case 0x03: /* SQDMLAL, SQDMLAL2 */
12797 case 0x07: /* SQDMLSL, SQDMLSL2 */
12798 case 0x0b: /* SQDMULL, SQDMULL2 */
12801 case 0x0c: /* SQDMULH */
12802 case 0x0d: /* SQRDMULH */
12804 case 0x01: /* FMLA */
12805 case 0x05: /* FMLS */
12806 case 0x09: /* FMUL */
12807 case 0x19: /* FMULX */
12810 case 0x1d: /* SQRDMLAH */
12811 case 0x1f: /* SQRDMLSH */
12812 if (!dc_isar_feature(aa64_rdm
, s
)) {
12813 unallocated_encoding(s
);
12817 case 0x0e: /* SDOT */
12818 case 0x1e: /* UDOT */
12819 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12820 unallocated_encoding(s
);
12824 case 0x11: /* FCMLA #0 */
12825 case 0x13: /* FCMLA #90 */
12826 case 0x15: /* FCMLA #180 */
12827 case 0x17: /* FCMLA #270 */
12828 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12829 unallocated_encoding(s
);
12834 case 0x00: /* FMLAL */
12835 case 0x04: /* FMLSL */
12836 case 0x18: /* FMLAL2 */
12837 case 0x1c: /* FMLSL2 */
12838 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12839 unallocated_encoding(s
);
12843 /* is_fp, but we pass cpu_env not fp_status. */
12846 unallocated_encoding(s
);
12851 case 1: /* normal fp */
12852 /* convert insn encoded size to TCGMemOp size */
12854 case 0: /* half-precision */
12858 case MO_32
: /* single precision */
12859 case MO_64
: /* double precision */
12862 unallocated_encoding(s
);
12867 case 2: /* complex fp */
12868 /* Each indexable element is a complex pair. */
12873 unallocated_encoding(s
);
12881 unallocated_encoding(s
);
12886 default: /* integer */
12890 unallocated_encoding(s
);
12895 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12896 unallocated_encoding(s
);
12900 /* Given TCGMemOp size, adjust register and indexing. */
12903 index
= h
<< 2 | l
<< 1 | m
;
12906 index
= h
<< 1 | l
;
12911 unallocated_encoding(s
);
12918 g_assert_not_reached();
12921 if (!fp_access_check(s
)) {
12926 fpst
= get_fpstatus_ptr(is_fp16
);
12931 switch (16 * u
+ opcode
) {
12932 case 0x0e: /* SDOT */
12933 case 0x1e: /* UDOT */
12934 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12935 u
? gen_helper_gvec_udot_idx_b
12936 : gen_helper_gvec_sdot_idx_b
);
12938 case 0x11: /* FCMLA #0 */
12939 case 0x13: /* FCMLA #90 */
12940 case 0x15: /* FCMLA #180 */
12941 case 0x17: /* FCMLA #270 */
12943 int rot
= extract32(insn
, 13, 2);
12944 int data
= (index
<< 2) | rot
;
12945 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12946 vec_full_reg_offset(s
, rn
),
12947 vec_full_reg_offset(s
, rm
), fpst
,
12948 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12950 ? gen_helper_gvec_fcmlas_idx
12951 : gen_helper_gvec_fcmlah_idx
);
12952 tcg_temp_free_ptr(fpst
);
12956 case 0x00: /* FMLAL */
12957 case 0x04: /* FMLSL */
12958 case 0x18: /* FMLAL2 */
12959 case 0x1c: /* FMLSL2 */
12961 int is_s
= extract32(opcode
, 2, 1);
12963 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
12964 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12965 vec_full_reg_offset(s
, rn
),
12966 vec_full_reg_offset(s
, rm
), cpu_env
,
12967 is_q
? 16 : 8, vec_full_reg_size(s
),
12968 data
, gen_helper_gvec_fmlal_idx_a64
);
12974 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12977 assert(is_fp
&& is_q
&& !is_long
);
12979 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12981 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12982 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12983 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12985 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12987 switch (16 * u
+ opcode
) {
12988 case 0x05: /* FMLS */
12989 /* As usual for ARM, separate negation for fused multiply-add */
12990 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12992 case 0x01: /* FMLA */
12993 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12994 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12996 case 0x09: /* FMUL */
12997 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12999 case 0x19: /* FMULX */
13000 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13003 g_assert_not_reached();
13006 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13007 tcg_temp_free_i64(tcg_op
);
13008 tcg_temp_free_i64(tcg_res
);
13011 tcg_temp_free_i64(tcg_idx
);
13012 clear_vec_high(s
, !is_scalar
, rd
);
13013 } else if (!is_long
) {
13014 /* 32 bit floating point, or 16 or 32 bit integer.
13015 * For the 16 bit scalar case we use the usual Neon helpers and
13016 * rely on the fact that 0 op 0 == 0 with no side effects.
13018 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13019 int pass
, maxpasses
;
13024 maxpasses
= is_q
? 4 : 2;
13027 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13029 if (size
== 1 && !is_scalar
) {
13030 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13031 * the index into both halves of the 32 bit tcg_idx and then use
13032 * the usual Neon helpers.
13034 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13037 for (pass
= 0; pass
< maxpasses
; pass
++) {
13038 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13039 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13041 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13043 switch (16 * u
+ opcode
) {
13044 case 0x08: /* MUL */
13045 case 0x10: /* MLA */
13046 case 0x14: /* MLS */
13048 static NeonGenTwoOpFn
* const fns
[2][2] = {
13049 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13050 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13052 NeonGenTwoOpFn
*genfn
;
13053 bool is_sub
= opcode
== 0x4;
13056 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13058 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13060 if (opcode
== 0x8) {
13063 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13064 genfn
= fns
[size
- 1][is_sub
];
13065 genfn(tcg_res
, tcg_op
, tcg_res
);
13068 case 0x05: /* FMLS */
13069 case 0x01: /* FMLA */
13070 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13071 is_scalar
? size
: MO_32
);
13074 if (opcode
== 0x5) {
13075 /* As usual for ARM, separate negation for fused
13077 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13080 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13083 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13088 if (opcode
== 0x5) {
13089 /* As usual for ARM, separate negation for
13090 * fused multiply-add */
13091 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13093 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13097 g_assert_not_reached();
13100 case 0x09: /* FMUL */
13104 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13107 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13112 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13115 g_assert_not_reached();
13118 case 0x19: /* FMULX */
13122 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13125 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13130 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13133 g_assert_not_reached();
13136 case 0x0c: /* SQDMULH */
13138 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13141 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13145 case 0x0d: /* SQRDMULH */
13147 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13150 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13154 case 0x1d: /* SQRDMLAH */
13155 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13156 is_scalar
? size
: MO_32
);
13158 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13159 tcg_op
, tcg_idx
, tcg_res
);
13161 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13162 tcg_op
, tcg_idx
, tcg_res
);
13165 case 0x1f: /* SQRDMLSH */
13166 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13167 is_scalar
? size
: MO_32
);
13169 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13170 tcg_op
, tcg_idx
, tcg_res
);
13172 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13173 tcg_op
, tcg_idx
, tcg_res
);
13177 g_assert_not_reached();
13181 write_fp_sreg(s
, rd
, tcg_res
);
13183 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13186 tcg_temp_free_i32(tcg_op
);
13187 tcg_temp_free_i32(tcg_res
);
13190 tcg_temp_free_i32(tcg_idx
);
13191 clear_vec_high(s
, is_q
, rd
);
13193 /* long ops: 16x16->32 or 32x32->64 */
13194 TCGv_i64 tcg_res
[2];
13196 bool satop
= extract32(opcode
, 0, 1);
13197 TCGMemOp memop
= MO_32
;
13204 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13206 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13208 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13209 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13210 TCGv_i64 tcg_passres
;
13216 passelt
= pass
+ (is_q
* 2);
13219 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13221 tcg_res
[pass
] = tcg_temp_new_i64();
13223 if (opcode
== 0xa || opcode
== 0xb) {
13224 /* Non-accumulating ops */
13225 tcg_passres
= tcg_res
[pass
];
13227 tcg_passres
= tcg_temp_new_i64();
13230 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13231 tcg_temp_free_i64(tcg_op
);
13234 /* saturating, doubling */
13235 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13236 tcg_passres
, tcg_passres
);
13239 if (opcode
== 0xa || opcode
== 0xb) {
13243 /* Accumulating op: handle accumulate step */
13244 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13247 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13248 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13250 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13251 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13253 case 0x7: /* SQDMLSL, SQDMLSL2 */
13254 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13256 case 0x3: /* SQDMLAL, SQDMLAL2 */
13257 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13262 g_assert_not_reached();
13264 tcg_temp_free_i64(tcg_passres
);
13266 tcg_temp_free_i64(tcg_idx
);
13268 clear_vec_high(s
, !is_scalar
, rd
);
13270 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13273 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13276 /* The simplest way to handle the 16x16 indexed ops is to
13277 * duplicate the index into both halves of the 32 bit tcg_idx
13278 * and then use the usual Neon helpers.
13280 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13283 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13284 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13285 TCGv_i64 tcg_passres
;
13288 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13290 read_vec_element_i32(s
, tcg_op
, rn
,
13291 pass
+ (is_q
* 2), MO_32
);
13294 tcg_res
[pass
] = tcg_temp_new_i64();
13296 if (opcode
== 0xa || opcode
== 0xb) {
13297 /* Non-accumulating ops */
13298 tcg_passres
= tcg_res
[pass
];
13300 tcg_passres
= tcg_temp_new_i64();
13303 if (memop
& MO_SIGN
) {
13304 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13306 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13309 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13310 tcg_passres
, tcg_passres
);
13312 tcg_temp_free_i32(tcg_op
);
13314 if (opcode
== 0xa || opcode
== 0xb) {
13318 /* Accumulating op: handle accumulate step */
13319 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13322 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13323 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13326 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13327 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13330 case 0x7: /* SQDMLSL, SQDMLSL2 */
13331 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13333 case 0x3: /* SQDMLAL, SQDMLAL2 */
13334 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13339 g_assert_not_reached();
13341 tcg_temp_free_i64(tcg_passres
);
13343 tcg_temp_free_i32(tcg_idx
);
13346 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13351 tcg_res
[1] = tcg_const_i64(0);
13354 for (pass
= 0; pass
< 2; pass
++) {
13355 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13356 tcg_temp_free_i64(tcg_res
[pass
]);
13361 tcg_temp_free_ptr(fpst
);
13366 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13367 * +-----------------+------+-----------+--------+-----+------+------+
13368 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13369 * +-----------------+------+-----------+--------+-----+------+------+
13371 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13373 int size
= extract32(insn
, 22, 2);
13374 int opcode
= extract32(insn
, 12, 5);
13375 int rn
= extract32(insn
, 5, 5);
13376 int rd
= extract32(insn
, 0, 5);
13378 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13379 TCGv_i32 tcg_decrypt
;
13380 CryptoThreeOpIntFn
*genfn
;
13382 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13383 unallocated_encoding(s
);
13388 case 0x4: /* AESE */
13390 genfn
= gen_helper_crypto_aese
;
13392 case 0x6: /* AESMC */
13394 genfn
= gen_helper_crypto_aesmc
;
13396 case 0x5: /* AESD */
13398 genfn
= gen_helper_crypto_aese
;
13400 case 0x7: /* AESIMC */
13402 genfn
= gen_helper_crypto_aesmc
;
13405 unallocated_encoding(s
);
13409 if (!fp_access_check(s
)) {
13413 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13414 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13415 tcg_decrypt
= tcg_const_i32(decrypt
);
13417 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13419 tcg_temp_free_ptr(tcg_rd_ptr
);
13420 tcg_temp_free_ptr(tcg_rn_ptr
);
13421 tcg_temp_free_i32(tcg_decrypt
);
13424 /* Crypto three-reg SHA
13425 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13426 * +-----------------+------+---+------+---+--------+-----+------+------+
13427 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13428 * +-----------------+------+---+------+---+--------+-----+------+------+
13430 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13432 int size
= extract32(insn
, 22, 2);
13433 int opcode
= extract32(insn
, 12, 3);
13434 int rm
= extract32(insn
, 16, 5);
13435 int rn
= extract32(insn
, 5, 5);
13436 int rd
= extract32(insn
, 0, 5);
13437 CryptoThreeOpFn
*genfn
;
13438 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13442 unallocated_encoding(s
);
13447 case 0: /* SHA1C */
13448 case 1: /* SHA1P */
13449 case 2: /* SHA1M */
13450 case 3: /* SHA1SU0 */
13452 feature
= dc_isar_feature(aa64_sha1
, s
);
13454 case 4: /* SHA256H */
13455 genfn
= gen_helper_crypto_sha256h
;
13456 feature
= dc_isar_feature(aa64_sha256
, s
);
13458 case 5: /* SHA256H2 */
13459 genfn
= gen_helper_crypto_sha256h2
;
13460 feature
= dc_isar_feature(aa64_sha256
, s
);
13462 case 6: /* SHA256SU1 */
13463 genfn
= gen_helper_crypto_sha256su1
;
13464 feature
= dc_isar_feature(aa64_sha256
, s
);
13467 unallocated_encoding(s
);
13472 unallocated_encoding(s
);
13476 if (!fp_access_check(s
)) {
13480 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13481 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13482 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13485 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13487 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13489 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13490 tcg_rm_ptr
, tcg_opcode
);
13491 tcg_temp_free_i32(tcg_opcode
);
13494 tcg_temp_free_ptr(tcg_rd_ptr
);
13495 tcg_temp_free_ptr(tcg_rn_ptr
);
13496 tcg_temp_free_ptr(tcg_rm_ptr
);
13499 /* Crypto two-reg SHA
13500 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13501 * +-----------------+------+-----------+--------+-----+------+------+
13502 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13503 * +-----------------+------+-----------+--------+-----+------+------+
13505 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13507 int size
= extract32(insn
, 22, 2);
13508 int opcode
= extract32(insn
, 12, 5);
13509 int rn
= extract32(insn
, 5, 5);
13510 int rd
= extract32(insn
, 0, 5);
13511 CryptoTwoOpFn
*genfn
;
13513 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13516 unallocated_encoding(s
);
13521 case 0: /* SHA1H */
13522 feature
= dc_isar_feature(aa64_sha1
, s
);
13523 genfn
= gen_helper_crypto_sha1h
;
13525 case 1: /* SHA1SU1 */
13526 feature
= dc_isar_feature(aa64_sha1
, s
);
13527 genfn
= gen_helper_crypto_sha1su1
;
13529 case 2: /* SHA256SU0 */
13530 feature
= dc_isar_feature(aa64_sha256
, s
);
13531 genfn
= gen_helper_crypto_sha256su0
;
13534 unallocated_encoding(s
);
13539 unallocated_encoding(s
);
13543 if (!fp_access_check(s
)) {
13547 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13548 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13550 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13552 tcg_temp_free_ptr(tcg_rd_ptr
);
13553 tcg_temp_free_ptr(tcg_rn_ptr
);
13556 /* Crypto three-reg SHA512
13557 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13558 * +-----------------------+------+---+---+-----+--------+------+------+
13559 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13560 * +-----------------------+------+---+---+-----+--------+------+------+
13562 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13564 int opcode
= extract32(insn
, 10, 2);
13565 int o
= extract32(insn
, 14, 1);
13566 int rm
= extract32(insn
, 16, 5);
13567 int rn
= extract32(insn
, 5, 5);
13568 int rd
= extract32(insn
, 0, 5);
13570 CryptoThreeOpFn
*genfn
;
13574 case 0: /* SHA512H */
13575 feature
= dc_isar_feature(aa64_sha512
, s
);
13576 genfn
= gen_helper_crypto_sha512h
;
13578 case 1: /* SHA512H2 */
13579 feature
= dc_isar_feature(aa64_sha512
, s
);
13580 genfn
= gen_helper_crypto_sha512h2
;
13582 case 2: /* SHA512SU1 */
13583 feature
= dc_isar_feature(aa64_sha512
, s
);
13584 genfn
= gen_helper_crypto_sha512su1
;
13587 feature
= dc_isar_feature(aa64_sha3
, s
);
13593 case 0: /* SM3PARTW1 */
13594 feature
= dc_isar_feature(aa64_sm3
, s
);
13595 genfn
= gen_helper_crypto_sm3partw1
;
13597 case 1: /* SM3PARTW2 */
13598 feature
= dc_isar_feature(aa64_sm3
, s
);
13599 genfn
= gen_helper_crypto_sm3partw2
;
13601 case 2: /* SM4EKEY */
13602 feature
= dc_isar_feature(aa64_sm4
, s
);
13603 genfn
= gen_helper_crypto_sm4ekey
;
13606 unallocated_encoding(s
);
13612 unallocated_encoding(s
);
13616 if (!fp_access_check(s
)) {
13621 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13623 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13624 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13625 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13627 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13629 tcg_temp_free_ptr(tcg_rd_ptr
);
13630 tcg_temp_free_ptr(tcg_rn_ptr
);
13631 tcg_temp_free_ptr(tcg_rm_ptr
);
13633 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13636 tcg_op1
= tcg_temp_new_i64();
13637 tcg_op2
= tcg_temp_new_i64();
13638 tcg_res
[0] = tcg_temp_new_i64();
13639 tcg_res
[1] = tcg_temp_new_i64();
13641 for (pass
= 0; pass
< 2; pass
++) {
13642 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13643 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13645 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13646 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13648 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13649 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13651 tcg_temp_free_i64(tcg_op1
);
13652 tcg_temp_free_i64(tcg_op2
);
13653 tcg_temp_free_i64(tcg_res
[0]);
13654 tcg_temp_free_i64(tcg_res
[1]);
13658 /* Crypto two-reg SHA512
13659 * 31 12 11 10 9 5 4 0
13660 * +-----------------------------------------+--------+------+------+
13661 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13662 * +-----------------------------------------+--------+------+------+
13664 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13666 int opcode
= extract32(insn
, 10, 2);
13667 int rn
= extract32(insn
, 5, 5);
13668 int rd
= extract32(insn
, 0, 5);
13669 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13671 CryptoTwoOpFn
*genfn
;
13674 case 0: /* SHA512SU0 */
13675 feature
= dc_isar_feature(aa64_sha512
, s
);
13676 genfn
= gen_helper_crypto_sha512su0
;
13679 feature
= dc_isar_feature(aa64_sm4
, s
);
13680 genfn
= gen_helper_crypto_sm4e
;
13683 unallocated_encoding(s
);
13688 unallocated_encoding(s
);
13692 if (!fp_access_check(s
)) {
13696 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13697 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13699 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13701 tcg_temp_free_ptr(tcg_rd_ptr
);
13702 tcg_temp_free_ptr(tcg_rn_ptr
);
13705 /* Crypto four-register
13706 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13707 * +-------------------+-----+------+---+------+------+------+
13708 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13709 * +-------------------+-----+------+---+------+------+------+
13711 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13713 int op0
= extract32(insn
, 21, 2);
13714 int rm
= extract32(insn
, 16, 5);
13715 int ra
= extract32(insn
, 10, 5);
13716 int rn
= extract32(insn
, 5, 5);
13717 int rd
= extract32(insn
, 0, 5);
13723 feature
= dc_isar_feature(aa64_sha3
, s
);
13725 case 2: /* SM3SS1 */
13726 feature
= dc_isar_feature(aa64_sm3
, s
);
13729 unallocated_encoding(s
);
13734 unallocated_encoding(s
);
13738 if (!fp_access_check(s
)) {
13743 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13746 tcg_op1
= tcg_temp_new_i64();
13747 tcg_op2
= tcg_temp_new_i64();
13748 tcg_op3
= tcg_temp_new_i64();
13749 tcg_res
[0] = tcg_temp_new_i64();
13750 tcg_res
[1] = tcg_temp_new_i64();
13752 for (pass
= 0; pass
< 2; pass
++) {
13753 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13754 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13755 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13759 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13762 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13764 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13766 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13767 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13769 tcg_temp_free_i64(tcg_op1
);
13770 tcg_temp_free_i64(tcg_op2
);
13771 tcg_temp_free_i64(tcg_op3
);
13772 tcg_temp_free_i64(tcg_res
[0]);
13773 tcg_temp_free_i64(tcg_res
[1]);
13775 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13777 tcg_op1
= tcg_temp_new_i32();
13778 tcg_op2
= tcg_temp_new_i32();
13779 tcg_op3
= tcg_temp_new_i32();
13780 tcg_res
= tcg_temp_new_i32();
13781 tcg_zero
= tcg_const_i32(0);
13783 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13784 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13785 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13787 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13788 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13789 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13790 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13792 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13793 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13794 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13795 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13797 tcg_temp_free_i32(tcg_op1
);
13798 tcg_temp_free_i32(tcg_op2
);
13799 tcg_temp_free_i32(tcg_op3
);
13800 tcg_temp_free_i32(tcg_res
);
13801 tcg_temp_free_i32(tcg_zero
);
13806 * 31 21 20 16 15 10 9 5 4 0
13807 * +-----------------------+------+--------+------+------+
13808 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13809 * +-----------------------+------+--------+------+------+
13811 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13813 int rm
= extract32(insn
, 16, 5);
13814 int imm6
= extract32(insn
, 10, 6);
13815 int rn
= extract32(insn
, 5, 5);
13816 int rd
= extract32(insn
, 0, 5);
13817 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13820 if (!dc_isar_feature(aa64_sha3
, s
)) {
13821 unallocated_encoding(s
);
13825 if (!fp_access_check(s
)) {
13829 tcg_op1
= tcg_temp_new_i64();
13830 tcg_op2
= tcg_temp_new_i64();
13831 tcg_res
[0] = tcg_temp_new_i64();
13832 tcg_res
[1] = tcg_temp_new_i64();
13834 for (pass
= 0; pass
< 2; pass
++) {
13835 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13836 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13838 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13839 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13841 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13842 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13844 tcg_temp_free_i64(tcg_op1
);
13845 tcg_temp_free_i64(tcg_op2
);
13846 tcg_temp_free_i64(tcg_res
[0]);
13847 tcg_temp_free_i64(tcg_res
[1]);
13850 /* Crypto three-reg imm2
13851 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13852 * +-----------------------+------+-----+------+--------+------+------+
13853 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13854 * +-----------------------+------+-----+------+--------+------+------+
13856 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13858 int opcode
= extract32(insn
, 10, 2);
13859 int imm2
= extract32(insn
, 12, 2);
13860 int rm
= extract32(insn
, 16, 5);
13861 int rn
= extract32(insn
, 5, 5);
13862 int rd
= extract32(insn
, 0, 5);
13863 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13864 TCGv_i32 tcg_imm2
, tcg_opcode
;
13866 if (!dc_isar_feature(aa64_sm3
, s
)) {
13867 unallocated_encoding(s
);
13871 if (!fp_access_check(s
)) {
13875 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13876 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13877 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13878 tcg_imm2
= tcg_const_i32(imm2
);
13879 tcg_opcode
= tcg_const_i32(opcode
);
13881 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13884 tcg_temp_free_ptr(tcg_rd_ptr
);
13885 tcg_temp_free_ptr(tcg_rn_ptr
);
13886 tcg_temp_free_ptr(tcg_rm_ptr
);
13887 tcg_temp_free_i32(tcg_imm2
);
13888 tcg_temp_free_i32(tcg_opcode
);
13891 /* C3.6 Data processing - SIMD, inc Crypto
13893 * As the decode gets a little complex we are using a table based
13894 * approach for this part of the decode.
13896 static const AArch64DecodeTable data_proc_simd
[] = {
13897 /* pattern , mask , fn */
13898 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13899 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13900 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13901 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13902 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13903 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13904 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13905 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13906 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13907 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13908 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13909 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13910 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13911 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13912 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13913 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13914 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13915 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13916 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13917 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13918 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13919 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13920 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13921 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13922 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13923 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13924 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13925 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13926 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13927 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13928 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13929 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13930 { 0x00000000, 0x00000000, NULL
}
13933 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13935 /* Note that this is called with all non-FP cases from
13936 * table C3-6 so it must UNDEF for entries not specifically
13937 * allocated to instructions in that table.
13939 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13943 unallocated_encoding(s
);
13947 /* C3.6 Data processing - SIMD and floating point */
13948 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13950 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13951 disas_data_proc_fp(s
, insn
);
13953 /* SIMD, including crypto */
13954 disas_data_proc_simd(s
, insn
);
13960 * @env: The cpu environment
13961 * @s: The DisasContext
13963 * Return true if the page is guarded.
13965 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13967 #ifdef CONFIG_USER_ONLY
13968 return false; /* FIXME */
13970 uint64_t addr
= s
->base
.pc_first
;
13971 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13972 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13973 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13976 * We test this immediately after reading an insn, which means
13977 * that any normal page must be in the TLB. The only exception
13978 * would be for executing from flash or device memory, which
13979 * does not retain the TLB entry.
13981 * FIXME: Assume false for those, for now. We could use
13982 * arm_cpu_get_phys_page_attrs_debug to re-read the page
13983 * table entry even for that case.
13985 return (tlb_hit(entry
->addr_code
, addr
) &&
13986 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
13991 * btype_destination_ok:
13992 * @insn: The instruction at the branch destination
13993 * @bt: SCTLR_ELx.BT
13994 * @btype: PSTATE.BTYPE, and is non-zero
13996 * On a guarded page, there are a limited number of insns
13997 * that may be present at the branch target:
13998 * - branch target identifiers,
13999 * - paciasp, pacibsp,
14002 * Anything else causes a Branch Target Exception.
14004 * Return true if the branch is compatible, false to raise BTITRAP.
14006 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14008 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14010 switch (extract32(insn
, 5, 7)) {
14011 case 0b011001: /* PACIASP */
14012 case 0b011011: /* PACIBSP */
14014 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14015 * with btype == 3. Otherwise all btype are ok.
14017 return !bt
|| btype
!= 3;
14018 case 0b100000: /* BTI */
14019 /* Not compatible with any btype. */
14021 case 0b100010: /* BTI c */
14022 /* Not compatible with btype == 3 */
14024 case 0b100100: /* BTI j */
14025 /* Not compatible with btype == 2 */
14027 case 0b100110: /* BTI jc */
14028 /* Compatible with any btype. */
14032 switch (insn
& 0xffe0001fu
) {
14033 case 0xd4200000u
: /* BRK */
14034 case 0xd4400000u
: /* HLT */
14035 /* Give priority to the breakpoint exception. */
14042 /* C3.1 A64 instruction index by encoding */
14043 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14047 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
14051 s
->fp_access_checked
= false;
14053 if (dc_isar_feature(aa64_bti
, s
)) {
14054 if (s
->base
.num_insns
== 1) {
14056 * At the first insn of the TB, compute s->guarded_page.
14057 * We delayed computing this until successfully reading
14058 * the first insn of the TB, above. This (mostly) ensures
14059 * that the softmmu tlb entry has been populated, and the
14060 * page table GP bit is available.
14062 * Note that we need to compute this even if btype == 0,
14063 * because this value is used for BR instructions later
14064 * where ENV is not available.
14066 s
->guarded_page
= is_guarded_page(env
, s
);
14068 /* First insn can have btype set to non-zero. */
14069 tcg_debug_assert(s
->btype
>= 0);
14072 * Note that the Branch Target Exception has fairly high
14073 * priority -- below debugging exceptions but above most
14074 * everything else. This allows us to handle this now
14075 * instead of waiting until the insn is otherwise decoded.
14079 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14080 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_btitrap(s
->btype
),
14081 default_exception_el(s
));
14085 /* Not the first insn: btype must be 0. */
14086 tcg_debug_assert(s
->btype
== 0);
14090 switch (extract32(insn
, 25, 4)) {
14091 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14092 unallocated_encoding(s
);
14095 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14096 unallocated_encoding(s
);
14099 case 0x8: case 0x9: /* Data processing - immediate */
14100 disas_data_proc_imm(s
, insn
);
14102 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14103 disas_b_exc_sys(s
, insn
);
14108 case 0xe: /* Loads and stores */
14109 disas_ldst(s
, insn
);
14112 case 0xd: /* Data processing - register */
14113 disas_data_proc_reg(s
, insn
);
14116 case 0xf: /* Data processing - SIMD and floating point */
14117 disas_data_proc_simd_fp(s
, insn
);
14120 assert(FALSE
); /* all 15 cases should be handled above */
14124 /* if we allocated any temporaries, free them here */
14128 * After execution of most insns, btype is reset to 0.
14129 * Note that we set btype == -1 when the insn sets btype.
14131 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14136 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14139 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14140 CPUARMState
*env
= cpu
->env_ptr
;
14141 ARMCPU
*arm_cpu
= env_archcpu(env
);
14142 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14143 int bound
, core_mmu_idx
;
14145 dc
->isar
= &arm_cpu
->isar
;
14146 dc
->pc
= dc
->base
.pc_first
;
14150 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14151 * there is no secure EL1, so we route exceptions to EL3.
14153 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14154 !arm_el_is_aa64(env
, 3);
14157 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14158 dc
->condexec_mask
= 0;
14159 dc
->condexec_cond
= 0;
14160 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14161 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14162 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14163 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14164 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14165 #if !defined(CONFIG_USER_ONLY)
14166 dc
->user
= (dc
->current_el
== 0);
14168 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14169 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14170 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14171 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14172 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14173 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14175 dc
->vec_stride
= 0;
14176 dc
->cp_regs
= arm_cpu
->cp_regs
;
14177 dc
->features
= env
->features
;
14179 /* Single step state. The code-generation logic here is:
14181 * generate code with no special handling for single-stepping (except
14182 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14183 * this happens anyway because those changes are all system register or
14185 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14186 * emit code for one insn
14187 * emit code to clear PSTATE.SS
14188 * emit code to generate software step exception for completed step
14189 * end TB (as usual for having generated an exception)
14190 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14191 * emit code to generate a software step exception
14194 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14195 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14196 dc
->is_ldex
= false;
14197 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
14199 /* Bound the number of insns to execute to those left on the page. */
14200 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14202 /* If architectural single step active, limit to 1. */
14203 if (dc
->ss_active
) {
14206 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14208 init_tmp_a64_array(dc
);
14211 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14215 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14217 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14219 tcg_gen_insn_start(dc
->pc
, 0, 0);
14220 dc
->insn_start
= tcg_last_op();
14223 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14224 const CPUBreakpoint
*bp
)
14226 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14228 if (bp
->flags
& BP_CPU
) {
14229 gen_a64_set_pc_im(dc
->pc
);
14230 gen_helper_check_breakpoints(cpu_env
);
14231 /* End the TB early; it likely won't be executed */
14232 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14234 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
14235 /* The address covered by the breakpoint must be
14236 included in [tb->pc, tb->pc + tb->size) in order
14237 to for it to be properly cleared -- thus we
14238 increment the PC here so that the logic setting
14239 tb->size below does the right thing. */
14241 dc
->base
.is_jmp
= DISAS_NORETURN
;
14247 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14249 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14250 CPUARMState
*env
= cpu
->env_ptr
;
14252 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14253 /* Singlestep state is Active-pending.
14254 * If we're in this state at the start of a TB then either
14255 * a) we just took an exception to an EL which is being debugged
14256 * and this is the first insn in the exception handler
14257 * b) debug exceptions were masked and we just unmasked them
14258 * without changing EL (eg by clearing PSTATE.D)
14259 * In either case we're going to take a swstep exception in the
14260 * "did not step an insn" case, and so the syndrome ISV and EX
14261 * bits should be zero.
14263 assert(dc
->base
.num_insns
== 1);
14264 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
14265 default_exception_el(dc
));
14266 dc
->base
.is_jmp
= DISAS_NORETURN
;
14268 disas_a64_insn(env
, dc
);
14271 dc
->base
.pc_next
= dc
->pc
;
14272 translator_loop_temp_check(&dc
->base
);
14275 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14277 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14279 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14280 /* Note that this means single stepping WFI doesn't halt the CPU.
14281 * For conditional branch insns this is harmless unreachable code as
14282 * gen_goto_tb() has already handled emitting the debug exception
14283 * (and thus a tb-jump is not possible when singlestepping).
14285 switch (dc
->base
.is_jmp
) {
14287 gen_a64_set_pc_im(dc
->pc
);
14291 if (dc
->base
.singlestep_enabled
) {
14292 gen_exception_internal(EXCP_DEBUG
);
14294 gen_step_complete_exception(dc
);
14297 case DISAS_NORETURN
:
14301 switch (dc
->base
.is_jmp
) {
14303 case DISAS_TOO_MANY
:
14304 gen_goto_tb(dc
, 1, dc
->pc
);
14308 gen_a64_set_pc_im(dc
->pc
);
14311 tcg_gen_exit_tb(NULL
, 0);
14314 tcg_gen_lookup_and_goto_ptr();
14316 case DISAS_NORETURN
:
14320 gen_a64_set_pc_im(dc
->pc
);
14321 gen_helper_wfe(cpu_env
);
14324 gen_a64_set_pc_im(dc
->pc
);
14325 gen_helper_yield(cpu_env
);
14329 /* This is a special case because we don't want to just halt the CPU
14330 * if trying to debug across a WFI.
14332 TCGv_i32 tmp
= tcg_const_i32(4);
14334 gen_a64_set_pc_im(dc
->pc
);
14335 gen_helper_wfi(cpu_env
, tmp
);
14336 tcg_temp_free_i32(tmp
);
14337 /* The helper doesn't necessarily throw an exception, but we
14338 * must go back to the main loop to check for interrupts anyway.
14340 tcg_gen_exit_tb(NULL
, 0);
14346 /* Functions above can change dc->pc, so re-align db->pc_next */
14347 dc
->base
.pc_next
= dc
->pc
;
14350 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14353 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14355 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14356 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14359 const TranslatorOps aarch64_translator_ops
= {
14360 .init_disas_context
= aarch64_tr_init_disas_context
,
14361 .tb_start
= aarch64_tr_tb_start
,
14362 .insn_start
= aarch64_tr_insn_start
,
14363 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14364 .translate_insn
= aarch64_tr_translate_insn
,
14365 .tb_stop
= aarch64_tr_tb_stop
,
14366 .disas_log
= aarch64_tr_disas_log
,