4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx
);
128 static void reset_btype(DisasContext
*s
)
131 TCGv_i32 zero
= tcg_const_i32(0);
132 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
133 tcg_temp_free_i32(zero
);
138 static void set_btype(DisasContext
*s
, int val
)
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val
>= 1 && val
<= 3);
145 tcg_val
= tcg_const_i32(val
);
146 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
147 tcg_temp_free_i32(tcg_val
);
151 void gen_a64_set_pc_im(uint64_t val
)
153 tcg_gen_movi_i64(cpu_pc
, val
);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
183 TCGv_i64 tcg_zero
= tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
191 dst
, dst
, tcg_zero
, dst
, src
);
192 tcg_temp_free_i64(tcg_zero
);
197 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
207 * Handle MTE and/or TBI.
209 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
210 * for the tag to be present in the FAR_ELx register. But for user-only
211 * mode we do not have a TLB with which to implement this, so we must
212 * remove the top byte now.
214 * Always return a fresh temporary that we can increment independently
215 * of the write-back address.
218 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
220 TCGv_i64 clean
= new_tmp_a64(s
);
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
224 tcg_gen_mov_i64(clean
, addr
);
229 /* Insert a zero tag into src, with the result at dst. */
230 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
232 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
235 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
236 MMUAccessType acc
, int log2_size
)
238 TCGv_i32 t_acc
= tcg_const_i32(acc
);
239 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
240 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
242 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
243 tcg_temp_free_i32(t_acc
);
244 tcg_temp_free_i32(t_idx
);
245 tcg_temp_free_i32(t_size
);
249 * For MTE, check a single logical or atomic access. This probes a single
250 * address, the exact one specified. The size and alignment of the access
251 * is not relevant to MTE, per se, but watchpoints do require the size,
252 * and we want to recognize those before making any other changes to state.
254 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
255 bool is_write
, bool tag_checked
,
256 int log2_size
, bool is_unpriv
,
259 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
264 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
265 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
266 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
267 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
268 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_size
);
269 tcg_desc
= tcg_const_i32(desc
);
271 ret
= new_tmp_a64(s
);
272 gen_helper_mte_check1(ret
, cpu_env
, tcg_desc
, addr
);
273 tcg_temp_free_i32(tcg_desc
);
277 return clean_data_tbi(s
, addr
);
280 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
281 bool tag_checked
, int log2_size
)
283 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
284 false, get_mem_index(s
));
288 * For MTE, check multiple logical sequential accesses.
290 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
291 bool tag_checked
, int log2_esize
, int total_size
)
293 if (tag_checked
&& s
->mte_active
[0] && total_size
!= (1 << log2_esize
)) {
298 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
299 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
300 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
301 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
302 desc
= FIELD_DP32(desc
, MTEDESC
, ESIZE
, 1 << log2_esize
);
303 desc
= FIELD_DP32(desc
, MTEDESC
, TSIZE
, total_size
);
304 tcg_desc
= tcg_const_i32(desc
);
306 ret
= new_tmp_a64(s
);
307 gen_helper_mte_checkN(ret
, cpu_env
, tcg_desc
, addr
);
308 tcg_temp_free_i32(tcg_desc
);
312 return gen_mte_check1(s
, addr
, is_write
, tag_checked
, log2_esize
);
315 typedef struct DisasCompare64
{
320 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
324 arm_test_cc(&c32
, cc
);
326 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
327 * properly. The NE/EQ comparisons are also fine with this choice. */
328 c64
->cond
= c32
.cond
;
329 c64
->value
= tcg_temp_new_i64();
330 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
335 static void a64_free_cc(DisasCompare64
*c64
)
337 tcg_temp_free_i64(c64
->value
);
340 static void gen_exception_internal(int excp
)
342 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
344 assert(excp_is_internal(excp
));
345 gen_helper_exception_internal(cpu_env
, tcg_excp
);
346 tcg_temp_free_i32(tcg_excp
);
349 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
351 gen_a64_set_pc_im(pc
);
352 gen_exception_internal(excp
);
353 s
->base
.is_jmp
= DISAS_NORETURN
;
356 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
357 uint32_t syndrome
, uint32_t target_el
)
359 gen_a64_set_pc_im(pc
);
360 gen_exception(excp
, syndrome
, target_el
);
361 s
->base
.is_jmp
= DISAS_NORETURN
;
364 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
368 gen_a64_set_pc_im(s
->pc_curr
);
369 tcg_syn
= tcg_const_i32(syndrome
);
370 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
371 tcg_temp_free_i32(tcg_syn
);
372 s
->base
.is_jmp
= DISAS_NORETURN
;
375 static void gen_step_complete_exception(DisasContext
*s
)
377 /* We just completed step of an insn. Move from Active-not-pending
378 * to Active-pending, and then also take the swstep exception.
379 * This corresponds to making the (IMPDEF) choice to prioritize
380 * swstep exceptions over asynchronous exceptions taken to an exception
381 * level where debug is disabled. This choice has the advantage that
382 * we do not need to maintain internal state corresponding to the
383 * ISV/EX syndrome bits between completion of the step and generation
384 * of the exception, and our syndrome information is always correct.
387 gen_swstep_exception(s
, 1, s
->is_ldex
);
388 s
->base
.is_jmp
= DISAS_NORETURN
;
391 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
393 /* No direct tb linking with singlestep (either QEMU's or the ARM
394 * debug architecture kind) or deterministic io
396 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
397 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
401 #ifndef CONFIG_USER_ONLY
402 /* Only link tbs from inside the same guest page */
403 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
411 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
413 TranslationBlock
*tb
;
416 if (use_goto_tb(s
, n
, dest
)) {
418 gen_a64_set_pc_im(dest
);
419 tcg_gen_exit_tb(tb
, n
);
420 s
->base
.is_jmp
= DISAS_NORETURN
;
422 gen_a64_set_pc_im(dest
);
424 gen_step_complete_exception(s
);
425 } else if (s
->base
.singlestep_enabled
) {
426 gen_exception_internal(EXCP_DEBUG
);
428 tcg_gen_lookup_and_goto_ptr();
429 s
->base
.is_jmp
= DISAS_NORETURN
;
434 void unallocated_encoding(DisasContext
*s
)
436 /* Unallocated and reserved encodings are uncategorized */
437 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
438 default_exception_el(s
));
441 static void init_tmp_a64_array(DisasContext
*s
)
443 #ifdef CONFIG_DEBUG_TCG
444 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
446 s
->tmp_a64_count
= 0;
449 static void free_tmp_a64(DisasContext
*s
)
452 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
453 tcg_temp_free_i64(s
->tmp_a64
[i
]);
455 init_tmp_a64_array(s
);
458 TCGv_i64
new_tmp_a64(DisasContext
*s
)
460 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
461 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
464 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
466 TCGv_i64 t
= new_tmp_a64(s
);
467 tcg_gen_movi_i64(t
, 0);
472 * Register access functions
474 * These functions are used for directly accessing a register in where
475 * changes to the final register value are likely to be made. If you
476 * need to use a register for temporary calculation (e.g. index type
477 * operations) use the read_* form.
479 * B1.2.1 Register mappings
481 * In instruction register encoding 31 can refer to ZR (zero register) or
482 * the SP (stack pointer) depending on context. In QEMU's case we map SP
483 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
484 * This is the point of the _sp forms.
486 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
489 return new_tmp_a64_zero(s
);
495 /* register access for when 31 == SP */
496 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
501 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
502 * representing the register contents. This TCGv is an auto-freed
503 * temporary so it need not be explicitly freed, and may be modified.
505 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
507 TCGv_i64 v
= new_tmp_a64(s
);
510 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
512 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
515 tcg_gen_movi_i64(v
, 0);
520 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
522 TCGv_i64 v
= new_tmp_a64(s
);
524 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
526 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
531 /* Return the offset into CPUARMState of a slice (from
532 * the least significant end) of FP register Qn (ie
534 * (Note that this is not the same mapping as for A32; see cpu.h)
536 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
538 return vec_reg_offset(s
, regno
, 0, size
);
541 /* Offset of the high half of the 128 bit vector Qn */
542 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
544 return vec_reg_offset(s
, regno
, 1, MO_64
);
547 /* Convenience accessors for reading and writing single and double
548 * FP registers. Writing clears the upper parts of the associated
549 * 128 bit vector register, as required by the architecture.
550 * Note that unlike the GP register accessors, the values returned
551 * by the read functions must be manually freed.
553 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
555 TCGv_i64 v
= tcg_temp_new_i64();
557 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
561 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
563 TCGv_i32 v
= tcg_temp_new_i32();
565 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
569 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
571 TCGv_i32 v
= tcg_temp_new_i32();
573 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
577 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
578 * If SVE is not enabled, then there are only 128 bits in the vector.
580 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
582 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
583 unsigned vsz
= vec_full_reg_size(s
);
585 /* Nop move, with side effect of clearing the tail. */
586 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
589 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
591 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
593 tcg_gen_st_i64(v
, cpu_env
, ofs
);
594 clear_vec_high(s
, false, reg
);
597 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
599 TCGv_i64 tmp
= tcg_temp_new_i64();
601 tcg_gen_extu_i32_i64(tmp
, v
);
602 write_fp_dreg(s
, reg
, tmp
);
603 tcg_temp_free_i64(tmp
);
606 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
608 TCGv_ptr statusptr
= tcg_temp_new_ptr();
611 /* In A64 all instructions (both FP and Neon) use the FPCR; there
612 * is no equivalent of the A32 Neon "standard FPSCR value".
613 * However half-precision operations operate under a different
614 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
617 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
619 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
621 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
625 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
626 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
627 GVecGen2Fn
*gvec_fn
, int vece
)
629 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
630 is_q
? 16 : 8, vec_full_reg_size(s
));
633 /* Expand a 2-operand + immediate AdvSIMD vector operation using
634 * an expander function.
636 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
637 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
639 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
640 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
643 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
644 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
645 GVecGen3Fn
*gvec_fn
, int vece
)
647 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
648 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
651 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
652 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
653 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
655 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
656 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
657 is_q
? 16 : 8, vec_full_reg_size(s
));
660 /* Expand a 2-operand operation using an out-of-line helper. */
661 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
662 int rn
, int data
, gen_helper_gvec_2
*fn
)
664 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
665 vec_full_reg_offset(s
, rn
),
666 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
669 /* Expand a 3-operand operation using an out-of-line helper. */
670 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
671 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
673 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
674 vec_full_reg_offset(s
, rn
),
675 vec_full_reg_offset(s
, rm
),
676 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
679 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
680 * an out-of-line helper.
682 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
683 int rm
, bool is_fp16
, int data
,
684 gen_helper_gvec_3_ptr
*fn
)
686 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
687 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
688 vec_full_reg_offset(s
, rn
),
689 vec_full_reg_offset(s
, rm
), fpst
,
690 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
691 tcg_temp_free_ptr(fpst
);
694 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
695 * than the 32 bit equivalent.
697 static inline void gen_set_NZ64(TCGv_i64 result
)
699 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
700 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
703 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
704 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
707 gen_set_NZ64(result
);
709 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
710 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
712 tcg_gen_movi_i32(cpu_CF
, 0);
713 tcg_gen_movi_i32(cpu_VF
, 0);
716 /* dest = T0 + T1; compute C, N, V and Z flags */
717 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
720 TCGv_i64 result
, flag
, tmp
;
721 result
= tcg_temp_new_i64();
722 flag
= tcg_temp_new_i64();
723 tmp
= tcg_temp_new_i64();
725 tcg_gen_movi_i64(tmp
, 0);
726 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
728 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
730 gen_set_NZ64(result
);
732 tcg_gen_xor_i64(flag
, result
, t0
);
733 tcg_gen_xor_i64(tmp
, t0
, t1
);
734 tcg_gen_andc_i64(flag
, flag
, tmp
);
735 tcg_temp_free_i64(tmp
);
736 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
738 tcg_gen_mov_i64(dest
, result
);
739 tcg_temp_free_i64(result
);
740 tcg_temp_free_i64(flag
);
742 /* 32 bit arithmetic */
743 TCGv_i32 t0_32
= tcg_temp_new_i32();
744 TCGv_i32 t1_32
= tcg_temp_new_i32();
745 TCGv_i32 tmp
= tcg_temp_new_i32();
747 tcg_gen_movi_i32(tmp
, 0);
748 tcg_gen_extrl_i64_i32(t0_32
, t0
);
749 tcg_gen_extrl_i64_i32(t1_32
, t1
);
750 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
751 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
752 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
753 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
754 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
755 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
757 tcg_temp_free_i32(tmp
);
758 tcg_temp_free_i32(t0_32
);
759 tcg_temp_free_i32(t1_32
);
763 /* dest = T0 - T1; compute C, N, V and Z flags */
764 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
767 /* 64 bit arithmetic */
768 TCGv_i64 result
, flag
, tmp
;
770 result
= tcg_temp_new_i64();
771 flag
= tcg_temp_new_i64();
772 tcg_gen_sub_i64(result
, t0
, t1
);
774 gen_set_NZ64(result
);
776 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
777 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
779 tcg_gen_xor_i64(flag
, result
, t0
);
780 tmp
= tcg_temp_new_i64();
781 tcg_gen_xor_i64(tmp
, t0
, t1
);
782 tcg_gen_and_i64(flag
, flag
, tmp
);
783 tcg_temp_free_i64(tmp
);
784 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
785 tcg_gen_mov_i64(dest
, result
);
786 tcg_temp_free_i64(flag
);
787 tcg_temp_free_i64(result
);
789 /* 32 bit arithmetic */
790 TCGv_i32 t0_32
= tcg_temp_new_i32();
791 TCGv_i32 t1_32
= tcg_temp_new_i32();
794 tcg_gen_extrl_i64_i32(t0_32
, t0
);
795 tcg_gen_extrl_i64_i32(t1_32
, t1
);
796 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
797 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
798 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
799 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
800 tmp
= tcg_temp_new_i32();
801 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
802 tcg_temp_free_i32(t0_32
);
803 tcg_temp_free_i32(t1_32
);
804 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
805 tcg_temp_free_i32(tmp
);
806 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
810 /* dest = T0 + T1 + CF; do not compute flags. */
811 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
813 TCGv_i64 flag
= tcg_temp_new_i64();
814 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
815 tcg_gen_add_i64(dest
, t0
, t1
);
816 tcg_gen_add_i64(dest
, dest
, flag
);
817 tcg_temp_free_i64(flag
);
820 tcg_gen_ext32u_i64(dest
, dest
);
824 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
825 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
828 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
829 result
= tcg_temp_new_i64();
830 cf_64
= tcg_temp_new_i64();
831 vf_64
= tcg_temp_new_i64();
832 tmp
= tcg_const_i64(0);
834 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
835 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
836 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
837 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
838 gen_set_NZ64(result
);
840 tcg_gen_xor_i64(vf_64
, result
, t0
);
841 tcg_gen_xor_i64(tmp
, t0
, t1
);
842 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
843 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
845 tcg_gen_mov_i64(dest
, result
);
847 tcg_temp_free_i64(tmp
);
848 tcg_temp_free_i64(vf_64
);
849 tcg_temp_free_i64(cf_64
);
850 tcg_temp_free_i64(result
);
852 TCGv_i32 t0_32
, t1_32
, tmp
;
853 t0_32
= tcg_temp_new_i32();
854 t1_32
= tcg_temp_new_i32();
855 tmp
= tcg_const_i32(0);
857 tcg_gen_extrl_i64_i32(t0_32
, t0
);
858 tcg_gen_extrl_i64_i32(t1_32
, t1
);
859 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
860 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
862 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
863 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
864 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
865 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
866 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
868 tcg_temp_free_i32(tmp
);
869 tcg_temp_free_i32(t1_32
);
870 tcg_temp_free_i32(t0_32
);
875 * Load/Store generators
879 * Store from GPR register to memory.
881 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
882 TCGv_i64 tcg_addr
, int size
, int memidx
,
884 unsigned int iss_srt
,
885 bool iss_sf
, bool iss_ar
)
888 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
893 syn
= syn_data_abort_with_iss(0,
899 0, 0, 0, 0, 0, false);
900 disas_set_insn_syndrome(s
, syn
);
904 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
905 TCGv_i64 tcg_addr
, int size
,
907 unsigned int iss_srt
,
908 bool iss_sf
, bool iss_ar
)
910 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
911 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
915 * Load from memory to GPR register
917 static void do_gpr_ld_memidx(DisasContext
*s
,
918 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
919 int size
, bool is_signed
,
920 bool extend
, int memidx
,
921 bool iss_valid
, unsigned int iss_srt
,
922 bool iss_sf
, bool iss_ar
)
924 MemOp memop
= s
->be_data
+ size
;
932 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
934 if (extend
&& is_signed
) {
936 tcg_gen_ext32u_i64(dest
, dest
);
942 syn
= syn_data_abort_with_iss(0,
948 0, 0, 0, 0, 0, false);
949 disas_set_insn_syndrome(s
, syn
);
953 static void do_gpr_ld(DisasContext
*s
,
954 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
955 int size
, bool is_signed
, bool extend
,
956 bool iss_valid
, unsigned int iss_srt
,
957 bool iss_sf
, bool iss_ar
)
959 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
961 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
965 * Store from FP register to memory
967 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
969 /* This writes the bottom N bits of a 128 bit wide vector to memory */
970 TCGv_i64 tmp
= tcg_temp_new_i64();
971 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
973 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
976 bool be
= s
->be_data
== MO_BE
;
977 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
979 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
980 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
982 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
983 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
985 tcg_temp_free_i64(tcg_hiaddr
);
988 tcg_temp_free_i64(tmp
);
992 * Load from memory to FP register
994 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
996 /* This always zero-extends and writes to a full 128 bit wide vector */
997 TCGv_i64 tmplo
= tcg_temp_new_i64();
998 TCGv_i64 tmphi
= NULL
;
1001 MemOp memop
= s
->be_data
+ size
;
1002 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1004 bool be
= s
->be_data
== MO_BE
;
1005 TCGv_i64 tcg_hiaddr
;
1007 tmphi
= tcg_temp_new_i64();
1008 tcg_hiaddr
= tcg_temp_new_i64();
1010 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1011 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1013 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1015 tcg_temp_free_i64(tcg_hiaddr
);
1018 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1019 tcg_temp_free_i64(tmplo
);
1022 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1023 tcg_temp_free_i64(tmphi
);
1025 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1029 * Vector load/store helpers.
1031 * The principal difference between this and a FP load is that we don't
1032 * zero extend as we are filling a partial chunk of the vector register.
1033 * These functions don't support 128 bit loads/stores, which would be
1034 * normal load/store operations.
1036 * The _i32 versions are useful when operating on 32 bit quantities
1037 * (eg for floating point single or using Neon helper functions).
1040 /* Get value of an element within a vector register */
1041 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1042 int element
, MemOp memop
)
1044 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1047 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1050 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1053 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1056 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1059 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1062 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1066 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1069 g_assert_not_reached();
1073 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1074 int element
, MemOp memop
)
1076 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1079 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1082 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1085 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1088 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1092 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1095 g_assert_not_reached();
1099 /* Set value of an element within a vector register */
1100 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1101 int element
, MemOp memop
)
1103 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1106 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1109 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1112 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1115 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1118 g_assert_not_reached();
1122 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1123 int destidx
, int element
, MemOp memop
)
1125 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1128 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1131 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1134 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1137 g_assert_not_reached();
1141 /* Store from vector register to memory */
1142 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1143 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1145 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1147 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1148 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1150 tcg_temp_free_i64(tcg_tmp
);
1153 /* Load from memory to vector register */
1154 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1155 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1157 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1159 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1160 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1162 tcg_temp_free_i64(tcg_tmp
);
1165 /* Check that FP/Neon access is enabled. If it is, return
1166 * true. If not, emit code to generate an appropriate exception,
1167 * and return false; the caller should not emit any code for
1168 * the instruction. Note that this check must happen after all
1169 * unallocated-encoding checks (otherwise the syndrome information
1170 * for the resulting exception will be incorrect).
1172 static inline bool fp_access_check(DisasContext
*s
)
1174 assert(!s
->fp_access_checked
);
1175 s
->fp_access_checked
= true;
1177 if (!s
->fp_excp_el
) {
1181 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1182 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1186 /* Check that SVE access is enabled. If it is, return true.
1187 * If not, emit code to generate an appropriate exception and return false.
1189 bool sve_access_check(DisasContext
*s
)
1191 if (s
->sve_excp_el
) {
1192 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1196 return fp_access_check(s
);
1200 * This utility function is for doing register extension with an
1201 * optional shift. You will likely want to pass a temporary for the
1202 * destination register. See DecodeRegExtend() in the ARM ARM.
1204 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1205 int option
, unsigned int shift
)
1207 int extsize
= extract32(option
, 0, 2);
1208 bool is_signed
= extract32(option
, 2, 1);
1213 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1216 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1219 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1222 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1228 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1231 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1234 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1237 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1243 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1247 static inline void gen_check_sp_alignment(DisasContext
*s
)
1249 /* The AArch64 architecture mandates that (if enabled via PSTATE
1250 * or SCTLR bits) there is a check that SP is 16-aligned on every
1251 * SP-relative load or store (with an exception generated if it is not).
1252 * In line with general QEMU practice regarding misaligned accesses,
1253 * we omit these checks for the sake of guest program performance.
1254 * This function is provided as a hook so we can more easily add these
1255 * checks in future (possibly as a "favour catching guest program bugs
1256 * over speed" user selectable option).
1261 * This provides a simple table based table lookup decoder. It is
1262 * intended to be used when the relevant bits for decode are too
1263 * awkwardly placed and switch/if based logic would be confusing and
1264 * deeply nested. Since it's a linear search through the table, tables
1265 * should be kept small.
1267 * It returns the first handler where insn & mask == pattern, or
1268 * NULL if there is no match.
1269 * The table is terminated by an empty mask (i.e. 0)
1271 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1274 const AArch64DecodeTable
*tptr
= table
;
1276 while (tptr
->mask
) {
1277 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1278 return tptr
->disas_fn
;
1286 * The instruction disassembly implemented here matches
1287 * the instruction encoding classifications in chapter C4
1288 * of the ARM Architecture Reference Manual (DDI0487B_a);
1289 * classification names and decode diagrams here should generally
1290 * match up with those in the manual.
1293 /* Unconditional branch (immediate)
1295 * +----+-----------+-------------------------------------+
1296 * | op | 0 0 1 0 1 | imm26 |
1297 * +----+-----------+-------------------------------------+
1299 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1301 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1303 if (insn
& (1U << 31)) {
1304 /* BL Branch with link */
1305 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1308 /* B Branch / BL Branch with link */
1310 gen_goto_tb(s
, 0, addr
);
1313 /* Compare and branch (immediate)
1314 * 31 30 25 24 23 5 4 0
1315 * +----+-------------+----+---------------------+--------+
1316 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1317 * +----+-------------+----+---------------------+--------+
1319 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1321 unsigned int sf
, op
, rt
;
1323 TCGLabel
*label_match
;
1326 sf
= extract32(insn
, 31, 1);
1327 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1328 rt
= extract32(insn
, 0, 5);
1329 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1331 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1332 label_match
= gen_new_label();
1335 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1336 tcg_cmp
, 0, label_match
);
1338 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1339 gen_set_label(label_match
);
1340 gen_goto_tb(s
, 1, addr
);
1343 /* Test and branch (immediate)
1344 * 31 30 25 24 23 19 18 5 4 0
1345 * +----+-------------+----+-------+-------------+------+
1346 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1347 * +----+-------------+----+-------+-------------+------+
1349 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1351 unsigned int bit_pos
, op
, rt
;
1353 TCGLabel
*label_match
;
1356 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1357 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1358 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1359 rt
= extract32(insn
, 0, 5);
1361 tcg_cmp
= tcg_temp_new_i64();
1362 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1363 label_match
= gen_new_label();
1366 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1367 tcg_cmp
, 0, label_match
);
1368 tcg_temp_free_i64(tcg_cmp
);
1369 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1370 gen_set_label(label_match
);
1371 gen_goto_tb(s
, 1, addr
);
1374 /* Conditional branch (immediate)
1375 * 31 25 24 23 5 4 3 0
1376 * +---------------+----+---------------------+----+------+
1377 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1378 * +---------------+----+---------------------+----+------+
1380 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1385 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1386 unallocated_encoding(s
);
1389 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1390 cond
= extract32(insn
, 0, 4);
1394 /* genuinely conditional branches */
1395 TCGLabel
*label_match
= gen_new_label();
1396 arm_gen_test_cc(cond
, label_match
);
1397 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1398 gen_set_label(label_match
);
1399 gen_goto_tb(s
, 1, addr
);
1401 /* 0xe and 0xf are both "always" conditions */
1402 gen_goto_tb(s
, 0, addr
);
1406 /* HINT instruction group, including various allocated HINTs */
1407 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1408 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1410 unsigned int selector
= crm
<< 3 | op2
;
1413 unallocated_encoding(s
);
1418 case 0b00000: /* NOP */
1420 case 0b00011: /* WFI */
1421 s
->base
.is_jmp
= DISAS_WFI
;
1423 case 0b00001: /* YIELD */
1424 /* When running in MTTCG we don't generate jumps to the yield and
1425 * WFE helpers as it won't affect the scheduling of other vCPUs.
1426 * If we wanted to more completely model WFE/SEV so we don't busy
1427 * spin unnecessarily we would need to do something more involved.
1429 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1430 s
->base
.is_jmp
= DISAS_YIELD
;
1433 case 0b00010: /* WFE */
1434 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1435 s
->base
.is_jmp
= DISAS_WFE
;
1438 case 0b00100: /* SEV */
1439 case 0b00101: /* SEVL */
1440 /* we treat all as NOP at least for now */
1442 case 0b00111: /* XPACLRI */
1443 if (s
->pauth_active
) {
1444 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1447 case 0b01000: /* PACIA1716 */
1448 if (s
->pauth_active
) {
1449 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1452 case 0b01010: /* PACIB1716 */
1453 if (s
->pauth_active
) {
1454 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1457 case 0b01100: /* AUTIA1716 */
1458 if (s
->pauth_active
) {
1459 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1462 case 0b01110: /* AUTIB1716 */
1463 if (s
->pauth_active
) {
1464 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1467 case 0b11000: /* PACIAZ */
1468 if (s
->pauth_active
) {
1469 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1470 new_tmp_a64_zero(s
));
1473 case 0b11001: /* PACIASP */
1474 if (s
->pauth_active
) {
1475 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1478 case 0b11010: /* PACIBZ */
1479 if (s
->pauth_active
) {
1480 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1481 new_tmp_a64_zero(s
));
1484 case 0b11011: /* PACIBSP */
1485 if (s
->pauth_active
) {
1486 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1489 case 0b11100: /* AUTIAZ */
1490 if (s
->pauth_active
) {
1491 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1492 new_tmp_a64_zero(s
));
1495 case 0b11101: /* AUTIASP */
1496 if (s
->pauth_active
) {
1497 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1500 case 0b11110: /* AUTIBZ */
1501 if (s
->pauth_active
) {
1502 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1503 new_tmp_a64_zero(s
));
1506 case 0b11111: /* AUTIBSP */
1507 if (s
->pauth_active
) {
1508 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1512 /* default specified as NOP equivalent */
1517 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1519 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1522 /* CLREX, DSB, DMB, ISB */
1523 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1524 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1529 unallocated_encoding(s
);
1540 case 1: /* MBReqTypes_Reads */
1541 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1543 case 2: /* MBReqTypes_Writes */
1544 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1546 default: /* MBReqTypes_All */
1547 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1553 /* We need to break the TB after this insn to execute
1554 * a self-modified code correctly and also to take
1555 * any pending interrupts immediately.
1558 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1562 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1563 goto do_unallocated
;
1566 * TODO: There is no speculation barrier opcode for TCG;
1567 * MB and end the TB instead.
1569 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1570 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1575 unallocated_encoding(s
);
1580 static void gen_xaflag(void)
1582 TCGv_i32 z
= tcg_temp_new_i32();
1584 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1593 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1594 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1597 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1598 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1600 /* (!C & Z) << 31 -> -(Z & ~C) */
1601 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1602 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1605 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1607 tcg_temp_free_i32(z
);
1610 static void gen_axflag(void)
1612 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1613 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1615 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1616 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1618 tcg_gen_movi_i32(cpu_NF
, 0);
1619 tcg_gen_movi_i32(cpu_VF
, 0);
1622 /* MSR (immediate) - move immediate to processor state field */
1623 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1624 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1627 int op
= op1
<< 3 | op2
;
1629 /* End the TB by default, chaining is ok. */
1630 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1633 case 0x00: /* CFINV */
1634 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1635 goto do_unallocated
;
1637 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1638 s
->base
.is_jmp
= DISAS_NEXT
;
1641 case 0x01: /* XAFlag */
1642 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1643 goto do_unallocated
;
1646 s
->base
.is_jmp
= DISAS_NEXT
;
1649 case 0x02: /* AXFlag */
1650 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1651 goto do_unallocated
;
1654 s
->base
.is_jmp
= DISAS_NEXT
;
1657 case 0x03: /* UAO */
1658 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1659 goto do_unallocated
;
1662 set_pstate_bits(PSTATE_UAO
);
1664 clear_pstate_bits(PSTATE_UAO
);
1666 t1
= tcg_const_i32(s
->current_el
);
1667 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1668 tcg_temp_free_i32(t1
);
1671 case 0x04: /* PAN */
1672 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1673 goto do_unallocated
;
1676 set_pstate_bits(PSTATE_PAN
);
1678 clear_pstate_bits(PSTATE_PAN
);
1680 t1
= tcg_const_i32(s
->current_el
);
1681 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1682 tcg_temp_free_i32(t1
);
1685 case 0x05: /* SPSel */
1686 if (s
->current_el
== 0) {
1687 goto do_unallocated
;
1689 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1690 gen_helper_msr_i_spsel(cpu_env
, t1
);
1691 tcg_temp_free_i32(t1
);
1694 case 0x1e: /* DAIFSet */
1695 t1
= tcg_const_i32(crm
);
1696 gen_helper_msr_i_daifset(cpu_env
, t1
);
1697 tcg_temp_free_i32(t1
);
1700 case 0x1f: /* DAIFClear */
1701 t1
= tcg_const_i32(crm
);
1702 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1703 tcg_temp_free_i32(t1
);
1704 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1705 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1708 case 0x1c: /* TCO */
1709 if (dc_isar_feature(aa64_mte
, s
)) {
1710 /* Full MTE is enabled -- set the TCO bit as directed. */
1712 set_pstate_bits(PSTATE_TCO
);
1714 clear_pstate_bits(PSTATE_TCO
);
1716 t1
= tcg_const_i32(s
->current_el
);
1717 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1718 tcg_temp_free_i32(t1
);
1719 /* Many factors, including TCO, go into MTE_ACTIVE. */
1720 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1721 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1722 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1723 s
->base
.is_jmp
= DISAS_NEXT
;
1725 goto do_unallocated
;
1731 unallocated_encoding(s
);
1736 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1738 TCGv_i32 tmp
= tcg_temp_new_i32();
1739 TCGv_i32 nzcv
= tcg_temp_new_i32();
1741 /* build bit 31, N */
1742 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1743 /* build bit 30, Z */
1744 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1745 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1746 /* build bit 29, C */
1747 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1748 /* build bit 28, V */
1749 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1750 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1751 /* generate result */
1752 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1754 tcg_temp_free_i32(nzcv
);
1755 tcg_temp_free_i32(tmp
);
1758 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1760 TCGv_i32 nzcv
= tcg_temp_new_i32();
1762 /* take NZCV from R[t] */
1763 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1766 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1768 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1769 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1771 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1772 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1774 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1775 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1776 tcg_temp_free_i32(nzcv
);
1779 /* MRS - move from system register
1780 * MSR (register) - move to system register
1783 * These are all essentially the same insn in 'read' and 'write'
1784 * versions, with varying op0 fields.
1786 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1787 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1788 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1790 const ARMCPRegInfo
*ri
;
1793 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1794 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1795 crn
, crm
, op0
, op1
, op2
));
1798 /* Unknown register; this might be a guest error or a QEMU
1799 * unimplemented feature.
1801 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1802 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1803 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1804 unallocated_encoding(s
);
1808 /* Check access permissions */
1809 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1810 unallocated_encoding(s
);
1815 /* Emit code to perform further access permissions checks at
1816 * runtime; this may result in an exception.
1819 TCGv_i32 tcg_syn
, tcg_isread
;
1822 gen_a64_set_pc_im(s
->pc_curr
);
1823 tmpptr
= tcg_const_ptr(ri
);
1824 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1825 tcg_syn
= tcg_const_i32(syndrome
);
1826 tcg_isread
= tcg_const_i32(isread
);
1827 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1828 tcg_temp_free_ptr(tmpptr
);
1829 tcg_temp_free_i32(tcg_syn
);
1830 tcg_temp_free_i32(tcg_isread
);
1831 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1833 * The readfn or writefn might raise an exception;
1834 * synchronize the CPU state in case it does.
1836 gen_a64_set_pc_im(s
->pc_curr
);
1839 /* Handle special cases first */
1840 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1844 tcg_rt
= cpu_reg(s
, rt
);
1846 gen_get_nzcv(tcg_rt
);
1848 gen_set_nzcv(tcg_rt
);
1851 case ARM_CP_CURRENTEL
:
1852 /* Reads as current EL value from pstate, which is
1853 * guaranteed to be constant by the tb flags.
1855 tcg_rt
= cpu_reg(s
, rt
);
1856 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1859 /* Writes clear the aligned block of memory which rt points into. */
1860 if (s
->mte_active
[0]) {
1864 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1865 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1866 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1867 t_desc
= tcg_const_i32(desc
);
1869 tcg_rt
= new_tmp_a64(s
);
1870 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1871 tcg_temp_free_i32(t_desc
);
1873 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1875 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1880 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1882 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1886 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1890 tcg_rt
= cpu_reg(s
, rt
);
1893 if (ri
->type
& ARM_CP_CONST
) {
1894 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1895 } else if (ri
->readfn
) {
1897 tmpptr
= tcg_const_ptr(ri
);
1898 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1899 tcg_temp_free_ptr(tmpptr
);
1901 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1904 if (ri
->type
& ARM_CP_CONST
) {
1905 /* If not forbidden by access permissions, treat as WI */
1907 } else if (ri
->writefn
) {
1909 tmpptr
= tcg_const_ptr(ri
);
1910 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1911 tcg_temp_free_ptr(tmpptr
);
1913 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1917 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1918 /* I/O operations must end the TB here (whether read or write) */
1919 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1921 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1923 * A write to any coprocessor regiser that ends a TB
1924 * must rebuild the hflags for the next TB.
1926 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1927 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1928 tcg_temp_free_i32(tcg_el
);
1930 * We default to ending the TB on a coprocessor register write,
1931 * but allow this to be suppressed by the register definition
1932 * (usually only necessary to work around guest bugs).
1934 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1939 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1940 * +---------------------+---+-----+-----+-------+-------+-----+------+
1941 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1942 * +---------------------+---+-----+-----+-------+-------+-----+------+
1944 static void disas_system(DisasContext
*s
, uint32_t insn
)
1946 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1947 l
= extract32(insn
, 21, 1);
1948 op0
= extract32(insn
, 19, 2);
1949 op1
= extract32(insn
, 16, 3);
1950 crn
= extract32(insn
, 12, 4);
1951 crm
= extract32(insn
, 8, 4);
1952 op2
= extract32(insn
, 5, 3);
1953 rt
= extract32(insn
, 0, 5);
1956 if (l
|| rt
!= 31) {
1957 unallocated_encoding(s
);
1961 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1962 handle_hint(s
, insn
, op1
, op2
, crm
);
1964 case 3: /* CLREX, DSB, DMB, ISB */
1965 handle_sync(s
, insn
, op1
, op2
, crm
);
1967 case 4: /* MSR (immediate) */
1968 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1971 unallocated_encoding(s
);
1976 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1979 /* Exception generation
1981 * 31 24 23 21 20 5 4 2 1 0
1982 * +-----------------+-----+------------------------+-----+----+
1983 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1984 * +-----------------------+------------------------+----------+
1986 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1988 int opc
= extract32(insn
, 21, 3);
1989 int op2_ll
= extract32(insn
, 0, 5);
1990 int imm16
= extract32(insn
, 5, 16);
1995 /* For SVC, HVC and SMC we advance the single-step state
1996 * machine before taking the exception. This is architecturally
1997 * mandated, to ensure that single-stepping a system call
1998 * instruction works properly.
2003 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2004 syn_aa64_svc(imm16
), default_exception_el(s
));
2007 if (s
->current_el
== 0) {
2008 unallocated_encoding(s
);
2011 /* The pre HVC helper handles cases when HVC gets trapped
2012 * as an undefined insn by runtime configuration.
2014 gen_a64_set_pc_im(s
->pc_curr
);
2015 gen_helper_pre_hvc(cpu_env
);
2017 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2018 syn_aa64_hvc(imm16
), 2);
2021 if (s
->current_el
== 0) {
2022 unallocated_encoding(s
);
2025 gen_a64_set_pc_im(s
->pc_curr
);
2026 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2027 gen_helper_pre_smc(cpu_env
, tmp
);
2028 tcg_temp_free_i32(tmp
);
2030 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2031 syn_aa64_smc(imm16
), 3);
2034 unallocated_encoding(s
);
2040 unallocated_encoding(s
);
2044 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2048 unallocated_encoding(s
);
2051 /* HLT. This has two purposes.
2052 * Architecturally, it is an external halting debug instruction.
2053 * Since QEMU doesn't implement external debug, we treat this as
2054 * it is required for halting debug disabled: it will UNDEF.
2055 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2057 if (semihosting_enabled() && imm16
== 0xf000) {
2058 #ifndef CONFIG_USER_ONLY
2059 /* In system mode, don't allow userspace access to semihosting,
2060 * to provide some semblance of security (and for consistency
2061 * with our 32-bit semihosting).
2063 if (s
->current_el
== 0) {
2064 unsupported_encoding(s
, insn
);
2068 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2070 unsupported_encoding(s
, insn
);
2074 if (op2_ll
< 1 || op2_ll
> 3) {
2075 unallocated_encoding(s
);
2078 /* DCPS1, DCPS2, DCPS3 */
2079 unsupported_encoding(s
, insn
);
2082 unallocated_encoding(s
);
2087 /* Unconditional branch (register)
2088 * 31 25 24 21 20 16 15 10 9 5 4 0
2089 * +---------------+-------+-------+-------+------+-------+
2090 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2091 * +---------------+-------+-------+-------+------+-------+
2093 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2095 unsigned int opc
, op2
, op3
, rn
, op4
;
2096 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2100 opc
= extract32(insn
, 21, 4);
2101 op2
= extract32(insn
, 16, 5);
2102 op3
= extract32(insn
, 10, 6);
2103 rn
= extract32(insn
, 5, 5);
2104 op4
= extract32(insn
, 0, 5);
2107 goto do_unallocated
;
2119 goto do_unallocated
;
2121 dst
= cpu_reg(s
, rn
);
2126 if (!dc_isar_feature(aa64_pauth
, s
)) {
2127 goto do_unallocated
;
2131 if (rn
!= 0x1f || op4
!= 0x1f) {
2132 goto do_unallocated
;
2135 modifier
= cpu_X
[31];
2137 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2139 goto do_unallocated
;
2141 modifier
= new_tmp_a64_zero(s
);
2143 if (s
->pauth_active
) {
2144 dst
= new_tmp_a64(s
);
2146 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2148 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2151 dst
= cpu_reg(s
, rn
);
2156 goto do_unallocated
;
2158 gen_a64_set_pc(s
, dst
);
2159 /* BLR also needs to load return address */
2161 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2167 if (!dc_isar_feature(aa64_pauth
, s
)) {
2168 goto do_unallocated
;
2170 if ((op3
& ~1) != 2) {
2171 goto do_unallocated
;
2173 btype_mod
= opc
& 1;
2174 if (s
->pauth_active
) {
2175 dst
= new_tmp_a64(s
);
2176 modifier
= cpu_reg_sp(s
, op4
);
2178 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2180 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2183 dst
= cpu_reg(s
, rn
);
2185 gen_a64_set_pc(s
, dst
);
2186 /* BLRAA also needs to load return address */
2188 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2193 if (s
->current_el
== 0) {
2194 goto do_unallocated
;
2199 goto do_unallocated
;
2201 dst
= tcg_temp_new_i64();
2202 tcg_gen_ld_i64(dst
, cpu_env
,
2203 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2206 case 2: /* ERETAA */
2207 case 3: /* ERETAB */
2208 if (!dc_isar_feature(aa64_pauth
, s
)) {
2209 goto do_unallocated
;
2211 if (rn
!= 0x1f || op4
!= 0x1f) {
2212 goto do_unallocated
;
2214 dst
= tcg_temp_new_i64();
2215 tcg_gen_ld_i64(dst
, cpu_env
,
2216 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2217 if (s
->pauth_active
) {
2218 modifier
= cpu_X
[31];
2220 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2222 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2228 goto do_unallocated
;
2230 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2234 gen_helper_exception_return(cpu_env
, dst
);
2235 tcg_temp_free_i64(dst
);
2236 /* Must exit loop to check un-masked IRQs */
2237 s
->base
.is_jmp
= DISAS_EXIT
;
2241 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2242 goto do_unallocated
;
2244 unsupported_encoding(s
, insn
);
2250 unallocated_encoding(s
);
2254 switch (btype_mod
) {
2256 if (dc_isar_feature(aa64_bti
, s
)) {
2257 /* BR to {x16,x17} or !guard -> 1, else 3. */
2258 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2263 if (dc_isar_feature(aa64_bti
, s
)) {
2264 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2269 default: /* RET or none of the above. */
2270 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2274 s
->base
.is_jmp
= DISAS_JUMP
;
2277 /* Branches, exception generating and system instructions */
2278 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2280 switch (extract32(insn
, 25, 7)) {
2281 case 0x0a: case 0x0b:
2282 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2283 disas_uncond_b_imm(s
, insn
);
2285 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2286 disas_comp_b_imm(s
, insn
);
2288 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2289 disas_test_b_imm(s
, insn
);
2291 case 0x2a: /* Conditional branch (immediate) */
2292 disas_cond_b_imm(s
, insn
);
2294 case 0x6a: /* Exception generation / System */
2295 if (insn
& (1 << 24)) {
2296 if (extract32(insn
, 22, 2) == 0) {
2297 disas_system(s
, insn
);
2299 unallocated_encoding(s
);
2305 case 0x6b: /* Unconditional branch (register) */
2306 disas_uncond_b_reg(s
, insn
);
2309 unallocated_encoding(s
);
2315 * Load/Store exclusive instructions are implemented by remembering
2316 * the value/address loaded, and seeing if these are the same
2317 * when the store is performed. This is not actually the architecturally
2318 * mandated semantics, but it works for typical guest code sequences
2319 * and avoids having to monitor regular stores.
2321 * The store exclusive uses the atomic cmpxchg primitives to avoid
2322 * races in multi-threaded linux-user and when MTTCG softmmu is
2325 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2326 TCGv_i64 addr
, int size
, bool is_pair
)
2328 int idx
= get_mem_index(s
);
2329 MemOp memop
= s
->be_data
;
2331 g_assert(size
<= 3);
2333 g_assert(size
>= 2);
2335 /* The pair must be single-copy atomic for the doubleword. */
2336 memop
|= MO_64
| MO_ALIGN
;
2337 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2338 if (s
->be_data
== MO_LE
) {
2339 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2340 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2342 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2343 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2346 /* The pair must be single-copy atomic for *each* doubleword, not
2347 the entire quadword, however it must be quadword aligned. */
2349 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2350 memop
| MO_ALIGN_16
);
2352 TCGv_i64 addr2
= tcg_temp_new_i64();
2353 tcg_gen_addi_i64(addr2
, addr
, 8);
2354 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2355 tcg_temp_free_i64(addr2
);
2357 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2358 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2361 memop
|= size
| MO_ALIGN
;
2362 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2363 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2365 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2368 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2369 TCGv_i64 addr
, int size
, int is_pair
)
2371 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2372 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2375 * [addr + datasize] = {Rt2};
2381 * env->exclusive_addr = -1;
2383 TCGLabel
*fail_label
= gen_new_label();
2384 TCGLabel
*done_label
= gen_new_label();
2387 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2389 tmp
= tcg_temp_new_i64();
2392 if (s
->be_data
== MO_LE
) {
2393 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2395 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2397 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2398 cpu_exclusive_val
, tmp
,
2400 MO_64
| MO_ALIGN
| s
->be_data
);
2401 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2402 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2403 if (!HAVE_CMPXCHG128
) {
2404 gen_helper_exit_atomic(cpu_env
);
2405 s
->base
.is_jmp
= DISAS_NORETURN
;
2406 } else if (s
->be_data
== MO_LE
) {
2407 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2412 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2417 } else if (s
->be_data
== MO_LE
) {
2418 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2419 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2421 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2422 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2425 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2426 cpu_reg(s
, rt
), get_mem_index(s
),
2427 size
| MO_ALIGN
| s
->be_data
);
2428 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2430 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2431 tcg_temp_free_i64(tmp
);
2432 tcg_gen_br(done_label
);
2434 gen_set_label(fail_label
);
2435 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2436 gen_set_label(done_label
);
2437 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2440 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2443 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2444 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2445 int memidx
= get_mem_index(s
);
2446 TCGv_i64 clean_addr
;
2449 gen_check_sp_alignment(s
);
2451 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2452 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2453 size
| MO_ALIGN
| s
->be_data
);
2456 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2459 TCGv_i64 s1
= cpu_reg(s
, rs
);
2460 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2461 TCGv_i64 t1
= cpu_reg(s
, rt
);
2462 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2463 TCGv_i64 clean_addr
;
2464 int memidx
= get_mem_index(s
);
2467 gen_check_sp_alignment(s
);
2470 /* This is a single atomic access, despite the "pair". */
2471 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2474 TCGv_i64 cmp
= tcg_temp_new_i64();
2475 TCGv_i64 val
= tcg_temp_new_i64();
2477 if (s
->be_data
== MO_LE
) {
2478 tcg_gen_concat32_i64(val
, t1
, t2
);
2479 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2481 tcg_gen_concat32_i64(val
, t2
, t1
);
2482 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2485 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2486 MO_64
| MO_ALIGN
| s
->be_data
);
2487 tcg_temp_free_i64(val
);
2489 if (s
->be_data
== MO_LE
) {
2490 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2492 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2494 tcg_temp_free_i64(cmp
);
2495 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2496 if (HAVE_CMPXCHG128
) {
2497 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2498 if (s
->be_data
== MO_LE
) {
2499 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2500 clean_addr
, t1
, t2
);
2502 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2503 clean_addr
, t1
, t2
);
2505 tcg_temp_free_i32(tcg_rs
);
2507 gen_helper_exit_atomic(cpu_env
);
2508 s
->base
.is_jmp
= DISAS_NORETURN
;
2511 TCGv_i64 d1
= tcg_temp_new_i64();
2512 TCGv_i64 d2
= tcg_temp_new_i64();
2513 TCGv_i64 a2
= tcg_temp_new_i64();
2514 TCGv_i64 c1
= tcg_temp_new_i64();
2515 TCGv_i64 c2
= tcg_temp_new_i64();
2516 TCGv_i64 zero
= tcg_const_i64(0);
2518 /* Load the two words, in memory order. */
2519 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2520 MO_64
| MO_ALIGN_16
| s
->be_data
);
2521 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2522 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2524 /* Compare the two words, also in memory order. */
2525 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2526 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2527 tcg_gen_and_i64(c2
, c2
, c1
);
2529 /* If compare equal, write back new data, else write back old data. */
2530 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2531 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2532 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2533 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2534 tcg_temp_free_i64(a2
);
2535 tcg_temp_free_i64(c1
);
2536 tcg_temp_free_i64(c2
);
2537 tcg_temp_free_i64(zero
);
2539 /* Write back the data from memory to Rs. */
2540 tcg_gen_mov_i64(s1
, d1
);
2541 tcg_gen_mov_i64(s2
, d2
);
2542 tcg_temp_free_i64(d1
);
2543 tcg_temp_free_i64(d2
);
2547 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2548 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2550 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2552 int opc0
= extract32(opc
, 0, 1);
2556 regsize
= opc0
? 32 : 64;
2558 regsize
= size
== 3 ? 64 : 32;
2560 return regsize
== 64;
2563 /* Load/store exclusive
2565 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2566 * +-----+-------------+----+---+----+------+----+-------+------+------+
2567 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2568 * +-----+-------------+----+---+----+------+----+-------+------+------+
2570 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2571 * L: 0 -> store, 1 -> load
2572 * o2: 0 -> exclusive, 1 -> not
2573 * o1: 0 -> single register, 1 -> register pair
2574 * o0: 1 -> load-acquire/store-release, 0 -> not
2576 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2578 int rt
= extract32(insn
, 0, 5);
2579 int rn
= extract32(insn
, 5, 5);
2580 int rt2
= extract32(insn
, 10, 5);
2581 int rs
= extract32(insn
, 16, 5);
2582 int is_lasr
= extract32(insn
, 15, 1);
2583 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2584 int size
= extract32(insn
, 30, 2);
2585 TCGv_i64 clean_addr
;
2587 switch (o2_L_o1_o0
) {
2588 case 0x0: /* STXR */
2589 case 0x1: /* STLXR */
2591 gen_check_sp_alignment(s
);
2594 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2596 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2597 true, rn
!= 31, size
);
2598 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2601 case 0x4: /* LDXR */
2602 case 0x5: /* LDAXR */
2604 gen_check_sp_alignment(s
);
2606 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2607 false, rn
!= 31, size
);
2609 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2611 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2615 case 0x8: /* STLLR */
2616 if (!dc_isar_feature(aa64_lor
, s
)) {
2619 /* StoreLORelease is the same as Store-Release for QEMU. */
2621 case 0x9: /* STLR */
2622 /* Generate ISS for non-exclusive accesses including LASR. */
2624 gen_check_sp_alignment(s
);
2626 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2627 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2628 true, rn
!= 31, size
);
2629 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2630 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2633 case 0xc: /* LDLAR */
2634 if (!dc_isar_feature(aa64_lor
, s
)) {
2637 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2639 case 0xd: /* LDAR */
2640 /* Generate ISS for non-exclusive accesses including LASR. */
2642 gen_check_sp_alignment(s
);
2644 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2645 false, rn
!= 31, size
);
2646 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2647 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2648 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2651 case 0x2: case 0x3: /* CASP / STXP */
2652 if (size
& 2) { /* STXP / STLXP */
2654 gen_check_sp_alignment(s
);
2657 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2659 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2660 true, rn
!= 31, size
);
2661 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2665 && ((rt
| rs
) & 1) == 0
2666 && dc_isar_feature(aa64_atomics
, s
)) {
2668 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2673 case 0x6: case 0x7: /* CASPA / LDXP */
2674 if (size
& 2) { /* LDXP / LDAXP */
2676 gen_check_sp_alignment(s
);
2678 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2679 false, rn
!= 31, size
);
2681 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2683 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2688 && ((rt
| rs
) & 1) == 0
2689 && dc_isar_feature(aa64_atomics
, s
)) {
2690 /* CASPA / CASPAL */
2691 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2697 case 0xb: /* CASL */
2698 case 0xe: /* CASA */
2699 case 0xf: /* CASAL */
2700 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2701 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2706 unallocated_encoding(s
);
2710 * Load register (literal)
2712 * 31 30 29 27 26 25 24 23 5 4 0
2713 * +-----+-------+---+-----+-------------------+-------+
2714 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2715 * +-----+-------+---+-----+-------------------+-------+
2717 * V: 1 -> vector (simd/fp)
2718 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2719 * 10-> 32 bit signed, 11 -> prefetch
2720 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2722 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2724 int rt
= extract32(insn
, 0, 5);
2725 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2726 bool is_vector
= extract32(insn
, 26, 1);
2727 int opc
= extract32(insn
, 30, 2);
2728 bool is_signed
= false;
2730 TCGv_i64 tcg_rt
, clean_addr
;
2734 unallocated_encoding(s
);
2738 if (!fp_access_check(s
)) {
2743 /* PRFM (literal) : prefetch */
2746 size
= 2 + extract32(opc
, 0, 1);
2747 is_signed
= extract32(opc
, 1, 1);
2750 tcg_rt
= cpu_reg(s
, rt
);
2752 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2754 do_fp_ld(s
, rt
, clean_addr
, size
);
2756 /* Only unsigned 32bit loads target 32bit registers. */
2757 bool iss_sf
= opc
!= 0;
2759 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2760 true, rt
, iss_sf
, false);
2762 tcg_temp_free_i64(clean_addr
);
2766 * LDNP (Load Pair - non-temporal hint)
2767 * LDP (Load Pair - non vector)
2768 * LDPSW (Load Pair Signed Word - non vector)
2769 * STNP (Store Pair - non-temporal hint)
2770 * STP (Store Pair - non vector)
2771 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2772 * LDP (Load Pair of SIMD&FP)
2773 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2774 * STP (Store Pair of SIMD&FP)
2776 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2777 * +-----+-------+---+---+-------+---+-----------------------------+
2778 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2779 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2781 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2783 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2784 * V: 0 -> GPR, 1 -> Vector
2785 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2786 * 10 -> signed offset, 11 -> pre-index
2787 * L: 0 -> Store 1 -> Load
2789 * Rt, Rt2 = GPR or SIMD registers to be stored
2790 * Rn = general purpose register containing address
2791 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2793 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2795 int rt
= extract32(insn
, 0, 5);
2796 int rn
= extract32(insn
, 5, 5);
2797 int rt2
= extract32(insn
, 10, 5);
2798 uint64_t offset
= sextract64(insn
, 15, 7);
2799 int index
= extract32(insn
, 23, 2);
2800 bool is_vector
= extract32(insn
, 26, 1);
2801 bool is_load
= extract32(insn
, 22, 1);
2802 int opc
= extract32(insn
, 30, 2);
2804 bool is_signed
= false;
2805 bool postindex
= false;
2807 bool set_tag
= false;
2809 TCGv_i64 clean_addr
, dirty_addr
;
2814 unallocated_encoding(s
);
2820 } else if (opc
== 1 && !is_load
) {
2822 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2823 unallocated_encoding(s
);
2829 size
= 2 + extract32(opc
, 1, 1);
2830 is_signed
= extract32(opc
, 0, 1);
2831 if (!is_load
&& is_signed
) {
2832 unallocated_encoding(s
);
2838 case 1: /* post-index */
2843 /* signed offset with "non-temporal" hint. Since we don't emulate
2844 * caches we don't care about hints to the cache system about
2845 * data access patterns, and handle this identically to plain
2849 /* There is no non-temporal-hint version of LDPSW */
2850 unallocated_encoding(s
);
2855 case 2: /* signed offset, rn not updated */
2858 case 3: /* pre-index */
2864 if (is_vector
&& !fp_access_check(s
)) {
2868 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2871 gen_check_sp_alignment(s
);
2874 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2876 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2882 * TODO: We could rely on the stores below, at least for
2883 * system mode, if we arrange to add MO_ALIGN_16.
2885 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2886 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2887 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2889 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2893 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2894 (wback
|| rn
!= 31) && !set_tag
,
2899 do_fp_ld(s
, rt
, clean_addr
, size
);
2901 do_fp_st(s
, rt
, clean_addr
, size
);
2903 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2905 do_fp_ld(s
, rt2
, clean_addr
, size
);
2907 do_fp_st(s
, rt2
, clean_addr
, size
);
2910 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2911 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2914 TCGv_i64 tmp
= tcg_temp_new_i64();
2916 /* Do not modify tcg_rt before recognizing any exception
2917 * from the second load.
2919 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2920 false, 0, false, false);
2921 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2922 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2923 false, 0, false, false);
2925 tcg_gen_mov_i64(tcg_rt
, tmp
);
2926 tcg_temp_free_i64(tmp
);
2928 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2929 false, 0, false, false);
2930 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2931 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2932 false, 0, false, false);
2938 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2940 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2945 * Load/store (immediate post-indexed)
2946 * Load/store (immediate pre-indexed)
2947 * Load/store (unscaled immediate)
2949 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2950 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2951 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2952 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2954 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2956 * V = 0 -> non-vector
2957 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2958 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2960 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2966 int rn
= extract32(insn
, 5, 5);
2967 int imm9
= sextract32(insn
, 12, 9);
2968 int idx
= extract32(insn
, 10, 2);
2969 bool is_signed
= false;
2970 bool is_store
= false;
2971 bool is_extended
= false;
2972 bool is_unpriv
= (idx
== 2);
2973 bool iss_valid
= !is_vector
;
2978 TCGv_i64 clean_addr
, dirty_addr
;
2981 size
|= (opc
& 2) << 1;
2982 if (size
> 4 || is_unpriv
) {
2983 unallocated_encoding(s
);
2986 is_store
= ((opc
& 1) == 0);
2987 if (!fp_access_check(s
)) {
2991 if (size
== 3 && opc
== 2) {
2992 /* PRFM - prefetch */
2994 unallocated_encoding(s
);
2999 if (opc
== 3 && size
> 1) {
3000 unallocated_encoding(s
);
3003 is_store
= (opc
== 0);
3004 is_signed
= extract32(opc
, 1, 1);
3005 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3023 g_assert_not_reached();
3027 gen_check_sp_alignment(s
);
3030 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3032 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3035 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3036 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3037 writeback
|| rn
!= 31,
3038 size
, is_unpriv
, memidx
);
3042 do_fp_st(s
, rt
, clean_addr
, size
);
3044 do_fp_ld(s
, rt
, clean_addr
, size
);
3047 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3048 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3051 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3052 iss_valid
, rt
, iss_sf
, false);
3054 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
3055 is_signed
, is_extended
, memidx
,
3056 iss_valid
, rt
, iss_sf
, false);
3061 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3063 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3065 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3070 * Load/store (register offset)
3072 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3073 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3074 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3075 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3078 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3079 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3081 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3082 * opc<0>: 0 -> store, 1 -> load
3083 * V: 1 -> vector/simd
3084 * opt: extend encoding (see DecodeRegExtend)
3085 * S: if S=1 then scale (essentially index by sizeof(size))
3086 * Rt: register to transfer into/out of
3087 * Rn: address register or SP for base
3088 * Rm: offset register or ZR for offset
3090 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3096 int rn
= extract32(insn
, 5, 5);
3097 int shift
= extract32(insn
, 12, 1);
3098 int rm
= extract32(insn
, 16, 5);
3099 int opt
= extract32(insn
, 13, 3);
3100 bool is_signed
= false;
3101 bool is_store
= false;
3102 bool is_extended
= false;
3104 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3106 if (extract32(opt
, 1, 1) == 0) {
3107 unallocated_encoding(s
);
3112 size
|= (opc
& 2) << 1;
3114 unallocated_encoding(s
);
3117 is_store
= !extract32(opc
, 0, 1);
3118 if (!fp_access_check(s
)) {
3122 if (size
== 3 && opc
== 2) {
3123 /* PRFM - prefetch */
3126 if (opc
== 3 && size
> 1) {
3127 unallocated_encoding(s
);
3130 is_store
= (opc
== 0);
3131 is_signed
= extract32(opc
, 1, 1);
3132 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3136 gen_check_sp_alignment(s
);
3138 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3140 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3141 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3143 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3144 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3148 do_fp_st(s
, rt
, clean_addr
, size
);
3150 do_fp_ld(s
, rt
, clean_addr
, size
);
3153 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3154 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3156 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3157 true, rt
, iss_sf
, false);
3159 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3160 is_signed
, is_extended
,
3161 true, rt
, iss_sf
, false);
3167 * Load/store (unsigned immediate)
3169 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3170 * +----+-------+---+-----+-----+------------+-------+------+
3171 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3172 * +----+-------+---+-----+-----+------------+-------+------+
3175 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3176 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3178 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3179 * opc<0>: 0 -> store, 1 -> load
3180 * Rn: base address register (inc SP)
3181 * Rt: target register
3183 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3189 int rn
= extract32(insn
, 5, 5);
3190 unsigned int imm12
= extract32(insn
, 10, 12);
3191 unsigned int offset
;
3193 TCGv_i64 clean_addr
, dirty_addr
;
3196 bool is_signed
= false;
3197 bool is_extended
= false;
3200 size
|= (opc
& 2) << 1;
3202 unallocated_encoding(s
);
3205 is_store
= !extract32(opc
, 0, 1);
3206 if (!fp_access_check(s
)) {
3210 if (size
== 3 && opc
== 2) {
3211 /* PRFM - prefetch */
3214 if (opc
== 3 && size
> 1) {
3215 unallocated_encoding(s
);
3218 is_store
= (opc
== 0);
3219 is_signed
= extract32(opc
, 1, 1);
3220 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3224 gen_check_sp_alignment(s
);
3226 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3227 offset
= imm12
<< size
;
3228 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3229 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3233 do_fp_st(s
, rt
, clean_addr
, size
);
3235 do_fp_ld(s
, rt
, clean_addr
, size
);
3238 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3239 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3241 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3242 true, rt
, iss_sf
, false);
3244 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3245 true, rt
, iss_sf
, false);
3250 /* Atomic memory operations
3252 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3253 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3254 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3255 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3257 * Rt: the result register
3258 * Rn: base address or SP
3259 * Rs: the source register for the operation
3260 * V: vector flag (always 0 as of v8.3)
3264 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3265 int size
, int rt
, bool is_vector
)
3267 int rs
= extract32(insn
, 16, 5);
3268 int rn
= extract32(insn
, 5, 5);
3269 int o3_opc
= extract32(insn
, 12, 4);
3270 bool r
= extract32(insn
, 22, 1);
3271 bool a
= extract32(insn
, 23, 1);
3272 TCGv_i64 tcg_rs
, clean_addr
;
3273 AtomicThreeOpFn
*fn
;
3275 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3276 unallocated_encoding(s
);
3280 case 000: /* LDADD */
3281 fn
= tcg_gen_atomic_fetch_add_i64
;
3283 case 001: /* LDCLR */
3284 fn
= tcg_gen_atomic_fetch_and_i64
;
3286 case 002: /* LDEOR */
3287 fn
= tcg_gen_atomic_fetch_xor_i64
;
3289 case 003: /* LDSET */
3290 fn
= tcg_gen_atomic_fetch_or_i64
;
3292 case 004: /* LDSMAX */
3293 fn
= tcg_gen_atomic_fetch_smax_i64
;
3295 case 005: /* LDSMIN */
3296 fn
= tcg_gen_atomic_fetch_smin_i64
;
3298 case 006: /* LDUMAX */
3299 fn
= tcg_gen_atomic_fetch_umax_i64
;
3301 case 007: /* LDUMIN */
3302 fn
= tcg_gen_atomic_fetch_umin_i64
;
3305 fn
= tcg_gen_atomic_xchg_i64
;
3307 case 014: /* LDAPR, LDAPRH, LDAPRB */
3308 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3309 rs
!= 31 || a
!= 1 || r
!= 0) {
3310 unallocated_encoding(s
);
3315 unallocated_encoding(s
);
3320 gen_check_sp_alignment(s
);
3322 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3324 if (o3_opc
== 014) {
3326 * LDAPR* are a special case because they are a simple load, not a
3327 * fetch-and-do-something op.
3328 * The architectural consistency requirements here are weaker than
3329 * full load-acquire (we only need "load-acquire processor consistent"),
3330 * but we choose to implement them as full LDAQ.
3332 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3333 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3334 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3338 tcg_rs
= read_cpu_reg(s
, rs
, true);
3340 if (o3_opc
== 1) { /* LDCLR */
3341 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3344 /* The tcg atomic primitives are all full barriers. Therefore we
3345 * can ignore the Acquire and Release bits of this instruction.
3347 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3348 s
->be_data
| size
| MO_ALIGN
);
3352 * PAC memory operations
3354 * 31 30 27 26 24 22 21 12 11 10 5 0
3355 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3356 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3357 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3359 * Rt: the result register
3360 * Rn: base address or SP
3361 * V: vector flag (always 0 as of v8.3)
3362 * M: clear for key DA, set for key DB
3363 * W: pre-indexing flag
3366 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3367 int size
, int rt
, bool is_vector
)
3369 int rn
= extract32(insn
, 5, 5);
3370 bool is_wback
= extract32(insn
, 11, 1);
3371 bool use_key_a
= !extract32(insn
, 23, 1);
3373 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3375 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3376 unallocated_encoding(s
);
3381 gen_check_sp_alignment(s
);
3383 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3385 if (s
->pauth_active
) {
3387 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3389 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3393 /* Form the 10-bit signed, scaled offset. */
3394 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3395 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3396 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3398 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3399 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3400 is_wback
|| rn
!= 31, size
);
3402 tcg_rt
= cpu_reg(s
, rt
);
3403 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3404 /* extend */ false, /* iss_valid */ !is_wback
,
3405 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3408 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3413 * LDAPR/STLR (unscaled immediate)
3415 * 31 30 24 22 21 12 10 5 0
3416 * +------+-------------+-----+---+--------+-----+----+-----+
3417 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3418 * +------+-------------+-----+---+--------+-----+----+-----+
3420 * Rt: source or destination register
3422 * imm9: unscaled immediate offset
3423 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3424 * size: size of load/store
3426 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3428 int rt
= extract32(insn
, 0, 5);
3429 int rn
= extract32(insn
, 5, 5);
3430 int offset
= sextract32(insn
, 12, 9);
3431 int opc
= extract32(insn
, 22, 2);
3432 int size
= extract32(insn
, 30, 2);
3433 TCGv_i64 clean_addr
, dirty_addr
;
3434 bool is_store
= false;
3435 bool is_signed
= false;
3436 bool extend
= false;
3439 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3440 unallocated_encoding(s
);
3445 case 0: /* STLURB */
3448 case 1: /* LDAPUR* */
3450 case 2: /* LDAPURS* 64-bit variant */
3452 unallocated_encoding(s
);
3457 case 3: /* LDAPURS* 32-bit variant */
3459 unallocated_encoding(s
);
3463 extend
= true; /* zero-extend 32->64 after signed load */
3466 g_assert_not_reached();
3469 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3472 gen_check_sp_alignment(s
);
3475 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3476 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3477 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3480 /* Store-Release semantics */
3481 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3482 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3485 * Load-AcquirePC semantics; we implement as the slightly more
3486 * restrictive Load-Acquire.
3488 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3489 true, rt
, iss_sf
, true);
3490 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3494 /* Load/store register (all forms) */
3495 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3497 int rt
= extract32(insn
, 0, 5);
3498 int opc
= extract32(insn
, 22, 2);
3499 bool is_vector
= extract32(insn
, 26, 1);
3500 int size
= extract32(insn
, 30, 2);
3502 switch (extract32(insn
, 24, 2)) {
3504 if (extract32(insn
, 21, 1) == 0) {
3505 /* Load/store register (unscaled immediate)
3506 * Load/store immediate pre/post-indexed
3507 * Load/store register unprivileged
3509 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3512 switch (extract32(insn
, 10, 2)) {
3514 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3517 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3520 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3525 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3528 unallocated_encoding(s
);
3531 /* AdvSIMD load/store multiple structures
3533 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3534 * +---+---+---------------+---+-------------+--------+------+------+------+
3535 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3536 * +---+---+---------------+---+-------------+--------+------+------+------+
3538 * AdvSIMD load/store multiple structures (post-indexed)
3540 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3541 * +---+---+---------------+---+---+---------+--------+------+------+------+
3542 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3543 * +---+---+---------------+---+---+---------+--------+------+------+------+
3545 * Rt: first (or only) SIMD&FP register to be transferred
3546 * Rn: base address or SP
3547 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3549 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3551 int rt
= extract32(insn
, 0, 5);
3552 int rn
= extract32(insn
, 5, 5);
3553 int rm
= extract32(insn
, 16, 5);
3554 int size
= extract32(insn
, 10, 2);
3555 int opcode
= extract32(insn
, 12, 4);
3556 bool is_store
= !extract32(insn
, 22, 1);
3557 bool is_postidx
= extract32(insn
, 23, 1);
3558 bool is_q
= extract32(insn
, 30, 1);
3559 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3560 MemOp endian
= s
->be_data
;
3562 int total
; /* total bytes */
3563 int elements
; /* elements per vector */
3564 int rpt
; /* num iterations */
3565 int selem
; /* structure elements */
3568 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3569 unallocated_encoding(s
);
3573 if (!is_postidx
&& rm
!= 0) {
3574 unallocated_encoding(s
);
3578 /* From the shared decode logic */
3609 unallocated_encoding(s
);
3613 if (size
== 3 && !is_q
&& selem
!= 1) {
3615 unallocated_encoding(s
);
3619 if (!fp_access_check(s
)) {
3624 gen_check_sp_alignment(s
);
3627 /* For our purposes, bytes are always little-endian. */
3632 total
= rpt
* selem
* (is_q
? 16 : 8);
3633 tcg_rn
= cpu_reg_sp(s
, rn
);
3636 * Issue the MTE check vs the logical repeat count, before we
3637 * promote consecutive little-endian elements below.
3639 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3643 * Consecutive little-endian elements from a single register
3644 * can be promoted to a larger little-endian operation.
3646 if (selem
== 1 && endian
== MO_LE
) {
3649 elements
= (is_q
? 16 : 8) >> size
;
3651 tcg_ebytes
= tcg_const_i64(1 << size
);
3652 for (r
= 0; r
< rpt
; r
++) {
3654 for (e
= 0; e
< elements
; e
++) {
3656 for (xs
= 0; xs
< selem
; xs
++) {
3657 int tt
= (rt
+ r
+ xs
) % 32;
3659 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3661 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3663 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3667 tcg_temp_free_i64(tcg_ebytes
);
3670 /* For non-quad operations, setting a slice of the low
3671 * 64 bits of the register clears the high 64 bits (in
3672 * the ARM ARM pseudocode this is implicit in the fact
3673 * that 'rval' is a 64 bit wide variable).
3674 * For quad operations, we might still need to zero the
3677 for (r
= 0; r
< rpt
* selem
; r
++) {
3678 int tt
= (rt
+ r
) % 32;
3679 clear_vec_high(s
, is_q
, tt
);
3685 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3687 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3692 /* AdvSIMD load/store single structure
3694 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3695 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3696 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3697 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3699 * AdvSIMD load/store single structure (post-indexed)
3701 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3702 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3703 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3704 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3706 * Rt: first (or only) SIMD&FP register to be transferred
3707 * Rn: base address or SP
3708 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3709 * index = encoded in Q:S:size dependent on size
3711 * lane_size = encoded in R, opc
3712 * transfer width = encoded in opc, S, size
3714 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3716 int rt
= extract32(insn
, 0, 5);
3717 int rn
= extract32(insn
, 5, 5);
3718 int rm
= extract32(insn
, 16, 5);
3719 int size
= extract32(insn
, 10, 2);
3720 int S
= extract32(insn
, 12, 1);
3721 int opc
= extract32(insn
, 13, 3);
3722 int R
= extract32(insn
, 21, 1);
3723 int is_load
= extract32(insn
, 22, 1);
3724 int is_postidx
= extract32(insn
, 23, 1);
3725 int is_q
= extract32(insn
, 30, 1);
3727 int scale
= extract32(opc
, 1, 2);
3728 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3729 bool replicate
= false;
3730 int index
= is_q
<< 3 | S
<< 2 | size
;
3732 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3734 if (extract32(insn
, 31, 1)) {
3735 unallocated_encoding(s
);
3738 if (!is_postidx
&& rm
!= 0) {
3739 unallocated_encoding(s
);
3745 if (!is_load
|| S
) {
3746 unallocated_encoding(s
);
3755 if (extract32(size
, 0, 1)) {
3756 unallocated_encoding(s
);
3762 if (extract32(size
, 1, 1)) {
3763 unallocated_encoding(s
);
3766 if (!extract32(size
, 0, 1)) {
3770 unallocated_encoding(s
);
3778 g_assert_not_reached();
3781 if (!fp_access_check(s
)) {
3786 gen_check_sp_alignment(s
);
3789 total
= selem
<< scale
;
3790 tcg_rn
= cpu_reg_sp(s
, rn
);
3792 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3795 tcg_ebytes
= tcg_const_i64(1 << scale
);
3796 for (xs
= 0; xs
< selem
; xs
++) {
3798 /* Load and replicate to all elements */
3799 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3801 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3802 get_mem_index(s
), s
->be_data
+ scale
);
3803 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3804 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3806 tcg_temp_free_i64(tcg_tmp
);
3808 /* Load/store one element per register */
3810 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3812 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3815 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3818 tcg_temp_free_i64(tcg_ebytes
);
3822 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3824 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3830 * Load/Store memory tags
3832 * 31 30 29 24 22 21 12 10 5 0
3833 * +-----+-------------+-----+---+------+-----+------+------+
3834 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3835 * +-----+-------------+-----+---+------+-----+------+------+
3837 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3839 int rt
= extract32(insn
, 0, 5);
3840 int rn
= extract32(insn
, 5, 5);
3841 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3842 int op2
= extract32(insn
, 10, 2);
3843 int op1
= extract32(insn
, 22, 2);
3844 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3846 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3848 /* We checked insn bits [29:24,21] in the caller. */
3849 if (extract32(insn
, 30, 2) != 3) {
3850 goto do_unallocated
;
3854 * @index is a tri-state variable which has 3 states:
3855 * < 0 : post-index, writeback
3856 * = 0 : signed offset
3857 * > 0 : pre-index, writeback
3866 if (s
->current_el
== 0 || offset
!= 0) {
3867 goto do_unallocated
;
3869 is_mult
= is_zero
= true;
3889 if (s
->current_el
== 0 || offset
!= 0) {
3890 goto do_unallocated
;
3898 is_pair
= is_zero
= true;
3902 if (s
->current_el
== 0 || offset
!= 0) {
3903 goto do_unallocated
;
3905 is_mult
= is_load
= true;
3911 unallocated_encoding(s
);
3916 ? !dc_isar_feature(aa64_mte
, s
)
3917 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
3918 goto do_unallocated
;
3922 gen_check_sp_alignment(s
);
3925 addr
= read_cpu_reg_sp(s
, rn
, true);
3927 /* pre-index or signed offset */
3928 tcg_gen_addi_i64(addr
, addr
, offset
);
3932 tcg_rt
= cpu_reg(s
, rt
);
3935 int size
= 4 << s
->dcz_blocksize
;
3938 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
3941 * The non-tags portion of STZGM is mostly like DC_ZVA,
3942 * except the alignment happens before the access.
3944 clean_addr
= clean_data_tbi(s
, addr
);
3945 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
3946 gen_helper_dc_zva(cpu_env
, clean_addr
);
3947 } else if (s
->ata
) {
3949 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
3951 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
3954 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
3955 int size
= 4 << GMID_EL1_BS
;
3957 clean_addr
= clean_data_tbi(s
, addr
);
3958 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
3959 gen_probe_access(s
, clean_addr
, acc
, size
);
3962 /* The result tags are zeros. */
3963 tcg_gen_movi_i64(tcg_rt
, 0);
3970 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
3971 tcg_rt
= cpu_reg(s
, rt
);
3973 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
3975 clean_addr
= clean_data_tbi(s
, addr
);
3976 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
3977 gen_address_with_allocation_tag0(tcg_rt
, addr
);
3980 tcg_rt
= cpu_reg_sp(s
, rt
);
3983 * For STG and ST2G, we need to check alignment and probe memory.
3984 * TODO: For STZG and STZ2G, we could rely on the stores below,
3985 * at least for system mode; user-only won't enforce alignment.
3988 gen_helper_st2g_stub(cpu_env
, addr
);
3990 gen_helper_stg_stub(cpu_env
, addr
);
3992 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
3994 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
3996 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4000 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4002 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4008 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4009 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4010 int mem_index
= get_mem_index(s
);
4011 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4013 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4014 MO_Q
| MO_ALIGN_16
);
4015 for (i
= 8; i
< n
; i
+= 8) {
4016 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4017 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_Q
);
4019 tcg_temp_free_i64(tcg_zero
);
4023 /* pre-index or post-index */
4026 tcg_gen_addi_i64(addr
, addr
, offset
);
4028 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4032 /* Loads and stores */
4033 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4035 switch (extract32(insn
, 24, 6)) {
4036 case 0x08: /* Load/store exclusive */
4037 disas_ldst_excl(s
, insn
);
4039 case 0x18: case 0x1c: /* Load register (literal) */
4040 disas_ld_lit(s
, insn
);
4042 case 0x28: case 0x29:
4043 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4044 disas_ldst_pair(s
, insn
);
4046 case 0x38: case 0x39:
4047 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4048 disas_ldst_reg(s
, insn
);
4050 case 0x0c: /* AdvSIMD load/store multiple structures */
4051 disas_ldst_multiple_struct(s
, insn
);
4053 case 0x0d: /* AdvSIMD load/store single structure */
4054 disas_ldst_single_struct(s
, insn
);
4057 if (extract32(insn
, 21, 1) != 0) {
4058 disas_ldst_tag(s
, insn
);
4059 } else if (extract32(insn
, 10, 2) == 0) {
4060 disas_ldst_ldapr_stlr(s
, insn
);
4062 unallocated_encoding(s
);
4066 unallocated_encoding(s
);
4071 /* PC-rel. addressing
4072 * 31 30 29 28 24 23 5 4 0
4073 * +----+-------+-----------+-------------------+------+
4074 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4075 * +----+-------+-----------+-------------------+------+
4077 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4079 unsigned int page
, rd
;
4083 page
= extract32(insn
, 31, 1);
4084 /* SignExtend(immhi:immlo) -> offset */
4085 offset
= sextract64(insn
, 5, 19);
4086 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4087 rd
= extract32(insn
, 0, 5);
4091 /* ADRP (page based) */
4096 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4100 * Add/subtract (immediate)
4102 * 31 30 29 28 23 22 21 10 9 5 4 0
4103 * +--+--+--+-------------+--+-------------+-----+-----+
4104 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4105 * +--+--+--+-------------+--+-------------+-----+-----+
4107 * sf: 0 -> 32bit, 1 -> 64bit
4108 * op: 0 -> add , 1 -> sub
4110 * sh: 1 -> LSL imm by 12
4112 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4114 int rd
= extract32(insn
, 0, 5);
4115 int rn
= extract32(insn
, 5, 5);
4116 uint64_t imm
= extract32(insn
, 10, 12);
4117 bool shift
= extract32(insn
, 22, 1);
4118 bool setflags
= extract32(insn
, 29, 1);
4119 bool sub_op
= extract32(insn
, 30, 1);
4120 bool is_64bit
= extract32(insn
, 31, 1);
4122 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4123 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4124 TCGv_i64 tcg_result
;
4130 tcg_result
= tcg_temp_new_i64();
4133 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4135 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4138 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4140 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4142 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4144 tcg_temp_free_i64(tcg_imm
);
4148 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4150 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4153 tcg_temp_free_i64(tcg_result
);
4157 * Add/subtract (immediate, with tags)
4159 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4160 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4161 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4162 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4164 * op: 0 -> add, 1 -> sub
4166 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4168 int rd
= extract32(insn
, 0, 5);
4169 int rn
= extract32(insn
, 5, 5);
4170 int uimm4
= extract32(insn
, 10, 4);
4171 int uimm6
= extract32(insn
, 16, 6);
4172 bool sub_op
= extract32(insn
, 30, 1);
4173 TCGv_i64 tcg_rn
, tcg_rd
;
4176 /* Test all of sf=1, S=0, o2=0, o3=0. */
4177 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4178 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4179 unallocated_encoding(s
);
4183 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4188 tcg_rn
= cpu_reg_sp(s
, rn
);
4189 tcg_rd
= cpu_reg_sp(s
, rd
);
4192 TCGv_i32 offset
= tcg_const_i32(imm
);
4193 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4195 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4196 tcg_temp_free_i32(tag_offset
);
4197 tcg_temp_free_i32(offset
);
4199 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4200 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4204 /* The input should be a value in the bottom e bits (with higher
4205 * bits zero); returns that value replicated into every element
4206 * of size e in a 64 bit integer.
4208 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4218 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4219 static inline uint64_t bitmask64(unsigned int length
)
4221 assert(length
> 0 && length
<= 64);
4222 return ~0ULL >> (64 - length
);
4225 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4226 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4227 * value (ie should cause a guest UNDEF exception), and true if they are
4228 * valid, in which case the decoded bit pattern is written to result.
4230 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4231 unsigned int imms
, unsigned int immr
)
4234 unsigned e
, levels
, s
, r
;
4237 assert(immn
< 2 && imms
< 64 && immr
< 64);
4239 /* The bit patterns we create here are 64 bit patterns which
4240 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4241 * 64 bits each. Each element contains the same value: a run
4242 * of between 1 and e-1 non-zero bits, rotated within the
4243 * element by between 0 and e-1 bits.
4245 * The element size and run length are encoded into immn (1 bit)
4246 * and imms (6 bits) as follows:
4247 * 64 bit elements: immn = 1, imms = <length of run - 1>
4248 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4249 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4250 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4251 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4252 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4253 * Notice that immn = 0, imms = 11111x is the only combination
4254 * not covered by one of the above options; this is reserved.
4255 * Further, <length of run - 1> all-ones is a reserved pattern.
4257 * In all cases the rotation is by immr % e (and immr is 6 bits).
4260 /* First determine the element size */
4261 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4263 /* This is the immn == 0, imms == 0x11111x case */
4273 /* <length of run - 1> mustn't be all-ones. */
4277 /* Create the value of one element: s+1 set bits rotated
4278 * by r within the element (which is e bits wide)...
4280 mask
= bitmask64(s
+ 1);
4282 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4283 mask
&= bitmask64(e
);
4285 /* ...then replicate the element over the whole 64 bit value */
4286 mask
= bitfield_replicate(mask
, e
);
4291 /* Logical (immediate)
4292 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4293 * +----+-----+-------------+---+------+------+------+------+
4294 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4295 * +----+-----+-------------+---+------+------+------+------+
4297 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4299 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4300 TCGv_i64 tcg_rd
, tcg_rn
;
4302 bool is_and
= false;
4304 sf
= extract32(insn
, 31, 1);
4305 opc
= extract32(insn
, 29, 2);
4306 is_n
= extract32(insn
, 22, 1);
4307 immr
= extract32(insn
, 16, 6);
4308 imms
= extract32(insn
, 10, 6);
4309 rn
= extract32(insn
, 5, 5);
4310 rd
= extract32(insn
, 0, 5);
4313 unallocated_encoding(s
);
4317 if (opc
== 0x3) { /* ANDS */
4318 tcg_rd
= cpu_reg(s
, rd
);
4320 tcg_rd
= cpu_reg_sp(s
, rd
);
4322 tcg_rn
= cpu_reg(s
, rn
);
4324 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4325 /* some immediate field values are reserved */
4326 unallocated_encoding(s
);
4331 wmask
&= 0xffffffff;
4335 case 0x3: /* ANDS */
4337 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4341 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4344 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4347 assert(FALSE
); /* must handle all above */
4351 if (!sf
&& !is_and
) {
4352 /* zero extend final result; we know we can skip this for AND
4353 * since the immediate had the high 32 bits clear.
4355 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4358 if (opc
== 3) { /* ANDS */
4359 gen_logic_CC(sf
, tcg_rd
);
4364 * Move wide (immediate)
4366 * 31 30 29 28 23 22 21 20 5 4 0
4367 * +--+-----+-------------+-----+----------------+------+
4368 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4369 * +--+-----+-------------+-----+----------------+------+
4371 * sf: 0 -> 32 bit, 1 -> 64 bit
4372 * opc: 00 -> N, 10 -> Z, 11 -> K
4373 * hw: shift/16 (0,16, and sf only 32, 48)
4375 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4377 int rd
= extract32(insn
, 0, 5);
4378 uint64_t imm
= extract32(insn
, 5, 16);
4379 int sf
= extract32(insn
, 31, 1);
4380 int opc
= extract32(insn
, 29, 2);
4381 int pos
= extract32(insn
, 21, 2) << 4;
4382 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4385 if (!sf
&& (pos
>= 32)) {
4386 unallocated_encoding(s
);
4400 tcg_gen_movi_i64(tcg_rd
, imm
);
4403 tcg_imm
= tcg_const_i64(imm
);
4404 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4405 tcg_temp_free_i64(tcg_imm
);
4407 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4411 unallocated_encoding(s
);
4417 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4418 * +----+-----+-------------+---+------+------+------+------+
4419 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4420 * +----+-----+-------------+---+------+------+------+------+
4422 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4424 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4425 TCGv_i64 tcg_rd
, tcg_tmp
;
4427 sf
= extract32(insn
, 31, 1);
4428 opc
= extract32(insn
, 29, 2);
4429 n
= extract32(insn
, 22, 1);
4430 ri
= extract32(insn
, 16, 6);
4431 si
= extract32(insn
, 10, 6);
4432 rn
= extract32(insn
, 5, 5);
4433 rd
= extract32(insn
, 0, 5);
4434 bitsize
= sf
? 64 : 32;
4436 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4437 unallocated_encoding(s
);
4441 tcg_rd
= cpu_reg(s
, rd
);
4443 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4444 to be smaller than bitsize, we'll never reference data outside the
4445 low 32-bits anyway. */
4446 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4448 /* Recognize simple(r) extractions. */
4450 /* Wd<s-r:0> = Wn<s:r> */
4451 len
= (si
- ri
) + 1;
4452 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4453 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4455 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4456 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4459 /* opc == 1, BFXIL fall through to deposit */
4460 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4463 /* Handle the ri > si case with a deposit
4464 * Wd<32+s-r,32-r> = Wn<s:0>
4467 pos
= (bitsize
- ri
) & (bitsize
- 1);
4470 if (opc
== 0 && len
< ri
) {
4471 /* SBFM: sign extend the destination field from len to fill
4472 the balance of the word. Let the deposit below insert all
4473 of those sign bits. */
4474 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4478 if (opc
== 1) { /* BFM, BFXIL */
4479 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4481 /* SBFM or UBFM: We start with zero, and we haven't modified
4482 any bits outside bitsize, therefore the zero-extension
4483 below is unneeded. */
4484 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4489 if (!sf
) { /* zero extend final result */
4490 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4495 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4496 * +----+------+-------------+---+----+------+--------+------+------+
4497 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4498 * +----+------+-------------+---+----+------+--------+------+------+
4500 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4502 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4504 sf
= extract32(insn
, 31, 1);
4505 n
= extract32(insn
, 22, 1);
4506 rm
= extract32(insn
, 16, 5);
4507 imm
= extract32(insn
, 10, 6);
4508 rn
= extract32(insn
, 5, 5);
4509 rd
= extract32(insn
, 0, 5);
4510 op21
= extract32(insn
, 29, 2);
4511 op0
= extract32(insn
, 21, 1);
4512 bitsize
= sf
? 64 : 32;
4514 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4515 unallocated_encoding(s
);
4517 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4519 tcg_rd
= cpu_reg(s
, rd
);
4521 if (unlikely(imm
== 0)) {
4522 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4523 * so an extract from bit 0 is a special case.
4526 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4528 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4531 tcg_rm
= cpu_reg(s
, rm
);
4532 tcg_rn
= cpu_reg(s
, rn
);
4535 /* Specialization to ROR happens in EXTRACT2. */
4536 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4538 TCGv_i32 t0
= tcg_temp_new_i32();
4540 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4542 tcg_gen_rotri_i32(t0
, t0
, imm
);
4544 TCGv_i32 t1
= tcg_temp_new_i32();
4545 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4546 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4547 tcg_temp_free_i32(t1
);
4549 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4550 tcg_temp_free_i32(t0
);
4556 /* Data processing - immediate */
4557 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4559 switch (extract32(insn
, 23, 6)) {
4560 case 0x20: case 0x21: /* PC-rel. addressing */
4561 disas_pc_rel_adr(s
, insn
);
4563 case 0x22: /* Add/subtract (immediate) */
4564 disas_add_sub_imm(s
, insn
);
4566 case 0x23: /* Add/subtract (immediate, with tags) */
4567 disas_add_sub_imm_with_tags(s
, insn
);
4569 case 0x24: /* Logical (immediate) */
4570 disas_logic_imm(s
, insn
);
4572 case 0x25: /* Move wide (immediate) */
4573 disas_movw_imm(s
, insn
);
4575 case 0x26: /* Bitfield */
4576 disas_bitfield(s
, insn
);
4578 case 0x27: /* Extract */
4579 disas_extract(s
, insn
);
4582 unallocated_encoding(s
);
4587 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4588 * Note that it is the caller's responsibility to ensure that the
4589 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4590 * mandated semantics for out of range shifts.
4592 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4593 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4595 switch (shift_type
) {
4596 case A64_SHIFT_TYPE_LSL
:
4597 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4599 case A64_SHIFT_TYPE_LSR
:
4600 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4602 case A64_SHIFT_TYPE_ASR
:
4604 tcg_gen_ext32s_i64(dst
, src
);
4606 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4608 case A64_SHIFT_TYPE_ROR
:
4610 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4613 t0
= tcg_temp_new_i32();
4614 t1
= tcg_temp_new_i32();
4615 tcg_gen_extrl_i64_i32(t0
, src
);
4616 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4617 tcg_gen_rotr_i32(t0
, t0
, t1
);
4618 tcg_gen_extu_i32_i64(dst
, t0
);
4619 tcg_temp_free_i32(t0
);
4620 tcg_temp_free_i32(t1
);
4624 assert(FALSE
); /* all shift types should be handled */
4628 if (!sf
) { /* zero extend final result */
4629 tcg_gen_ext32u_i64(dst
, dst
);
4633 /* Shift a TCGv src by immediate, put result in dst.
4634 * The shift amount must be in range (this should always be true as the
4635 * relevant instructions will UNDEF on bad shift immediates).
4637 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4638 enum a64_shift_type shift_type
, unsigned int shift_i
)
4640 assert(shift_i
< (sf
? 64 : 32));
4643 tcg_gen_mov_i64(dst
, src
);
4645 TCGv_i64 shift_const
;
4647 shift_const
= tcg_const_i64(shift_i
);
4648 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4649 tcg_temp_free_i64(shift_const
);
4653 /* Logical (shifted register)
4654 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4655 * +----+-----+-----------+-------+---+------+--------+------+------+
4656 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4657 * +----+-----+-----------+-------+---+------+--------+------+------+
4659 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4661 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4662 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4664 sf
= extract32(insn
, 31, 1);
4665 opc
= extract32(insn
, 29, 2);
4666 shift_type
= extract32(insn
, 22, 2);
4667 invert
= extract32(insn
, 21, 1);
4668 rm
= extract32(insn
, 16, 5);
4669 shift_amount
= extract32(insn
, 10, 6);
4670 rn
= extract32(insn
, 5, 5);
4671 rd
= extract32(insn
, 0, 5);
4673 if (!sf
&& (shift_amount
& (1 << 5))) {
4674 unallocated_encoding(s
);
4678 tcg_rd
= cpu_reg(s
, rd
);
4680 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4681 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4682 * register-register MOV and MVN, so it is worth special casing.
4684 tcg_rm
= cpu_reg(s
, rm
);
4686 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4688 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4692 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4694 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4700 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4703 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4706 tcg_rn
= cpu_reg(s
, rn
);
4708 switch (opc
| (invert
<< 2)) {
4711 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4714 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4717 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4721 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4724 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4727 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4735 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4739 gen_logic_CC(sf
, tcg_rd
);
4744 * Add/subtract (extended register)
4746 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4747 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4748 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4749 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4751 * sf: 0 -> 32bit, 1 -> 64bit
4752 * op: 0 -> add , 1 -> sub
4755 * option: extension type (see DecodeRegExtend)
4756 * imm3: optional shift to Rm
4758 * Rd = Rn + LSL(extend(Rm), amount)
4760 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4762 int rd
= extract32(insn
, 0, 5);
4763 int rn
= extract32(insn
, 5, 5);
4764 int imm3
= extract32(insn
, 10, 3);
4765 int option
= extract32(insn
, 13, 3);
4766 int rm
= extract32(insn
, 16, 5);
4767 int opt
= extract32(insn
, 22, 2);
4768 bool setflags
= extract32(insn
, 29, 1);
4769 bool sub_op
= extract32(insn
, 30, 1);
4770 bool sf
= extract32(insn
, 31, 1);
4772 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4774 TCGv_i64 tcg_result
;
4776 if (imm3
> 4 || opt
!= 0) {
4777 unallocated_encoding(s
);
4781 /* non-flag setting ops may use SP */
4783 tcg_rd
= cpu_reg_sp(s
, rd
);
4785 tcg_rd
= cpu_reg(s
, rd
);
4787 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4789 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4790 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4792 tcg_result
= tcg_temp_new_i64();
4796 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4798 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4802 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4804 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4809 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4811 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4814 tcg_temp_free_i64(tcg_result
);
4818 * Add/subtract (shifted register)
4820 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4821 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4822 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4823 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4825 * sf: 0 -> 32bit, 1 -> 64bit
4826 * op: 0 -> add , 1 -> sub
4828 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4829 * imm6: Shift amount to apply to Rm before the add/sub
4831 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4833 int rd
= extract32(insn
, 0, 5);
4834 int rn
= extract32(insn
, 5, 5);
4835 int imm6
= extract32(insn
, 10, 6);
4836 int rm
= extract32(insn
, 16, 5);
4837 int shift_type
= extract32(insn
, 22, 2);
4838 bool setflags
= extract32(insn
, 29, 1);
4839 bool sub_op
= extract32(insn
, 30, 1);
4840 bool sf
= extract32(insn
, 31, 1);
4842 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4843 TCGv_i64 tcg_rn
, tcg_rm
;
4844 TCGv_i64 tcg_result
;
4846 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4847 unallocated_encoding(s
);
4851 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4852 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4854 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4856 tcg_result
= tcg_temp_new_i64();
4860 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4862 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4866 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4868 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4873 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4875 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4878 tcg_temp_free_i64(tcg_result
);
4881 /* Data-processing (3 source)
4883 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4884 * +--+------+-----------+------+------+----+------+------+------+
4885 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4886 * +--+------+-----------+------+------+----+------+------+------+
4888 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4890 int rd
= extract32(insn
, 0, 5);
4891 int rn
= extract32(insn
, 5, 5);
4892 int ra
= extract32(insn
, 10, 5);
4893 int rm
= extract32(insn
, 16, 5);
4894 int op_id
= (extract32(insn
, 29, 3) << 4) |
4895 (extract32(insn
, 21, 3) << 1) |
4896 extract32(insn
, 15, 1);
4897 bool sf
= extract32(insn
, 31, 1);
4898 bool is_sub
= extract32(op_id
, 0, 1);
4899 bool is_high
= extract32(op_id
, 2, 1);
4900 bool is_signed
= false;
4905 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4907 case 0x42: /* SMADDL */
4908 case 0x43: /* SMSUBL */
4909 case 0x44: /* SMULH */
4912 case 0x0: /* MADD (32bit) */
4913 case 0x1: /* MSUB (32bit) */
4914 case 0x40: /* MADD (64bit) */
4915 case 0x41: /* MSUB (64bit) */
4916 case 0x4a: /* UMADDL */
4917 case 0x4b: /* UMSUBL */
4918 case 0x4c: /* UMULH */
4921 unallocated_encoding(s
);
4926 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4927 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4928 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4929 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4932 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4934 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4937 tcg_temp_free_i64(low_bits
);
4941 tcg_op1
= tcg_temp_new_i64();
4942 tcg_op2
= tcg_temp_new_i64();
4943 tcg_tmp
= tcg_temp_new_i64();
4946 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4947 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4950 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4951 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4953 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4954 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4958 if (ra
== 31 && !is_sub
) {
4959 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4960 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4962 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4964 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4966 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4971 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4974 tcg_temp_free_i64(tcg_op1
);
4975 tcg_temp_free_i64(tcg_op2
);
4976 tcg_temp_free_i64(tcg_tmp
);
4979 /* Add/subtract (with carry)
4980 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4981 * +--+--+--+------------------------+------+-------------+------+-----+
4982 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4983 * +--+--+--+------------------------+------+-------------+------+-----+
4986 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4988 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4989 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4991 sf
= extract32(insn
, 31, 1);
4992 op
= extract32(insn
, 30, 1);
4993 setflags
= extract32(insn
, 29, 1);
4994 rm
= extract32(insn
, 16, 5);
4995 rn
= extract32(insn
, 5, 5);
4996 rd
= extract32(insn
, 0, 5);
4998 tcg_rd
= cpu_reg(s
, rd
);
4999 tcg_rn
= cpu_reg(s
, rn
);
5002 tcg_y
= new_tmp_a64(s
);
5003 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5005 tcg_y
= cpu_reg(s
, rm
);
5009 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5011 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5016 * Rotate right into flags
5017 * 31 30 29 21 15 10 5 4 0
5018 * +--+--+--+-----------------+--------+-----------+------+--+------+
5019 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5020 * +--+--+--+-----------------+--------+-----------+------+--+------+
5022 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5024 int mask
= extract32(insn
, 0, 4);
5025 int o2
= extract32(insn
, 4, 1);
5026 int rn
= extract32(insn
, 5, 5);
5027 int imm6
= extract32(insn
, 15, 6);
5028 int sf_op_s
= extract32(insn
, 29, 3);
5032 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5033 unallocated_encoding(s
);
5037 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5038 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5040 nzcv
= tcg_temp_new_i32();
5041 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5043 if (mask
& 8) { /* N */
5044 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5046 if (mask
& 4) { /* Z */
5047 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5048 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5050 if (mask
& 2) { /* C */
5051 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5053 if (mask
& 1) { /* V */
5054 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5057 tcg_temp_free_i32(nzcv
);
5061 * Evaluate into flags
5062 * 31 30 29 21 15 14 10 5 4 0
5063 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5064 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5065 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5067 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5069 int o3_mask
= extract32(insn
, 0, 5);
5070 int rn
= extract32(insn
, 5, 5);
5071 int o2
= extract32(insn
, 15, 6);
5072 int sz
= extract32(insn
, 14, 1);
5073 int sf_op_s
= extract32(insn
, 29, 3);
5077 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5078 !dc_isar_feature(aa64_condm_4
, s
)) {
5079 unallocated_encoding(s
);
5082 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5084 tmp
= tcg_temp_new_i32();
5085 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5086 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5087 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5088 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5089 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5090 tcg_temp_free_i32(tmp
);
5093 /* Conditional compare (immediate / register)
5094 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5095 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5096 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5097 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5100 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5102 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5103 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5104 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5107 if (!extract32(insn
, 29, 1)) {
5108 unallocated_encoding(s
);
5111 if (insn
& (1 << 10 | 1 << 4)) {
5112 unallocated_encoding(s
);
5115 sf
= extract32(insn
, 31, 1);
5116 op
= extract32(insn
, 30, 1);
5117 is_imm
= extract32(insn
, 11, 1);
5118 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5119 cond
= extract32(insn
, 12, 4);
5120 rn
= extract32(insn
, 5, 5);
5121 nzcv
= extract32(insn
, 0, 4);
5123 /* Set T0 = !COND. */
5124 tcg_t0
= tcg_temp_new_i32();
5125 arm_test_cc(&c
, cond
);
5126 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5129 /* Load the arguments for the new comparison. */
5131 tcg_y
= new_tmp_a64(s
);
5132 tcg_gen_movi_i64(tcg_y
, y
);
5134 tcg_y
= cpu_reg(s
, y
);
5136 tcg_rn
= cpu_reg(s
, rn
);
5138 /* Set the flags for the new comparison. */
5139 tcg_tmp
= tcg_temp_new_i64();
5141 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5143 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5145 tcg_temp_free_i64(tcg_tmp
);
5147 /* If COND was false, force the flags to #nzcv. Compute two masks
5148 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5149 * For tcg hosts that support ANDC, we can make do with just T1.
5150 * In either case, allow the tcg optimizer to delete any unused mask.
5152 tcg_t1
= tcg_temp_new_i32();
5153 tcg_t2
= tcg_temp_new_i32();
5154 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5155 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5157 if (nzcv
& 8) { /* N */
5158 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5160 if (TCG_TARGET_HAS_andc_i32
) {
5161 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5163 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5166 if (nzcv
& 4) { /* Z */
5167 if (TCG_TARGET_HAS_andc_i32
) {
5168 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5170 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5173 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5175 if (nzcv
& 2) { /* C */
5176 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5178 if (TCG_TARGET_HAS_andc_i32
) {
5179 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5181 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5184 if (nzcv
& 1) { /* V */
5185 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5187 if (TCG_TARGET_HAS_andc_i32
) {
5188 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5190 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5193 tcg_temp_free_i32(tcg_t0
);
5194 tcg_temp_free_i32(tcg_t1
);
5195 tcg_temp_free_i32(tcg_t2
);
5198 /* Conditional select
5199 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5200 * +----+----+---+-----------------+------+------+-----+------+------+
5201 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5202 * +----+----+---+-----------------+------+------+-----+------+------+
5204 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5206 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5207 TCGv_i64 tcg_rd
, zero
;
5210 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5211 /* S == 1 or op2<1> == 1 */
5212 unallocated_encoding(s
);
5215 sf
= extract32(insn
, 31, 1);
5216 else_inv
= extract32(insn
, 30, 1);
5217 rm
= extract32(insn
, 16, 5);
5218 cond
= extract32(insn
, 12, 4);
5219 else_inc
= extract32(insn
, 10, 1);
5220 rn
= extract32(insn
, 5, 5);
5221 rd
= extract32(insn
, 0, 5);
5223 tcg_rd
= cpu_reg(s
, rd
);
5225 a64_test_cc(&c
, cond
);
5226 zero
= tcg_const_i64(0);
5228 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5230 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5232 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5235 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5236 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5237 if (else_inv
&& else_inc
) {
5238 tcg_gen_neg_i64(t_false
, t_false
);
5239 } else if (else_inv
) {
5240 tcg_gen_not_i64(t_false
, t_false
);
5241 } else if (else_inc
) {
5242 tcg_gen_addi_i64(t_false
, t_false
, 1);
5244 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5247 tcg_temp_free_i64(zero
);
5251 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5255 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5256 unsigned int rn
, unsigned int rd
)
5258 TCGv_i64 tcg_rd
, tcg_rn
;
5259 tcg_rd
= cpu_reg(s
, rd
);
5260 tcg_rn
= cpu_reg(s
, rn
);
5263 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5265 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5266 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5267 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5268 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5269 tcg_temp_free_i32(tcg_tmp32
);
5273 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5274 unsigned int rn
, unsigned int rd
)
5276 TCGv_i64 tcg_rd
, tcg_rn
;
5277 tcg_rd
= cpu_reg(s
, rd
);
5278 tcg_rn
= cpu_reg(s
, rn
);
5281 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5283 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5284 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5285 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5286 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5287 tcg_temp_free_i32(tcg_tmp32
);
5291 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5292 unsigned int rn
, unsigned int rd
)
5294 TCGv_i64 tcg_rd
, tcg_rn
;
5295 tcg_rd
= cpu_reg(s
, rd
);
5296 tcg_rn
= cpu_reg(s
, rn
);
5299 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5301 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5302 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5303 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5304 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5305 tcg_temp_free_i32(tcg_tmp32
);
5309 /* REV with sf==1, opcode==3 ("REV64") */
5310 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5311 unsigned int rn
, unsigned int rd
)
5314 unallocated_encoding(s
);
5317 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5320 /* REV with sf==0, opcode==2
5321 * REV32 (sf==1, opcode==2)
5323 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5324 unsigned int rn
, unsigned int rd
)
5326 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5329 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5330 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5332 /* bswap32_i64 requires zero high word */
5333 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
5334 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
5335 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
5336 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
5337 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5339 tcg_temp_free_i64(tcg_tmp
);
5341 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
5342 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
5346 /* REV16 (opcode==1) */
5347 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5348 unsigned int rn
, unsigned int rd
)
5350 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5351 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5352 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5353 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5355 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5356 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5357 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5358 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5359 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5361 tcg_temp_free_i64(mask
);
5362 tcg_temp_free_i64(tcg_tmp
);
5365 /* Data-processing (1 source)
5366 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5367 * +----+---+---+-----------------+---------+--------+------+------+
5368 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5369 * +----+---+---+-----------------+---------+--------+------+------+
5371 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5373 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5376 if (extract32(insn
, 29, 1)) {
5377 unallocated_encoding(s
);
5381 sf
= extract32(insn
, 31, 1);
5382 opcode
= extract32(insn
, 10, 6);
5383 opcode2
= extract32(insn
, 16, 5);
5384 rn
= extract32(insn
, 5, 5);
5385 rd
= extract32(insn
, 0, 5);
5387 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5389 switch (MAP(sf
, opcode2
, opcode
)) {
5390 case MAP(0, 0x00, 0x00): /* RBIT */
5391 case MAP(1, 0x00, 0x00):
5392 handle_rbit(s
, sf
, rn
, rd
);
5394 case MAP(0, 0x00, 0x01): /* REV16 */
5395 case MAP(1, 0x00, 0x01):
5396 handle_rev16(s
, sf
, rn
, rd
);
5398 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5399 case MAP(1, 0x00, 0x02):
5400 handle_rev32(s
, sf
, rn
, rd
);
5402 case MAP(1, 0x00, 0x03): /* REV64 */
5403 handle_rev64(s
, sf
, rn
, rd
);
5405 case MAP(0, 0x00, 0x04): /* CLZ */
5406 case MAP(1, 0x00, 0x04):
5407 handle_clz(s
, sf
, rn
, rd
);
5409 case MAP(0, 0x00, 0x05): /* CLS */
5410 case MAP(1, 0x00, 0x05):
5411 handle_cls(s
, sf
, rn
, rd
);
5413 case MAP(1, 0x01, 0x00): /* PACIA */
5414 if (s
->pauth_active
) {
5415 tcg_rd
= cpu_reg(s
, rd
);
5416 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5417 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5418 goto do_unallocated
;
5421 case MAP(1, 0x01, 0x01): /* PACIB */
5422 if (s
->pauth_active
) {
5423 tcg_rd
= cpu_reg(s
, rd
);
5424 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5425 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5426 goto do_unallocated
;
5429 case MAP(1, 0x01, 0x02): /* PACDA */
5430 if (s
->pauth_active
) {
5431 tcg_rd
= cpu_reg(s
, rd
);
5432 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5433 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5434 goto do_unallocated
;
5437 case MAP(1, 0x01, 0x03): /* PACDB */
5438 if (s
->pauth_active
) {
5439 tcg_rd
= cpu_reg(s
, rd
);
5440 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5441 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5442 goto do_unallocated
;
5445 case MAP(1, 0x01, 0x04): /* AUTIA */
5446 if (s
->pauth_active
) {
5447 tcg_rd
= cpu_reg(s
, rd
);
5448 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5449 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5450 goto do_unallocated
;
5453 case MAP(1, 0x01, 0x05): /* AUTIB */
5454 if (s
->pauth_active
) {
5455 tcg_rd
= cpu_reg(s
, rd
);
5456 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5457 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5458 goto do_unallocated
;
5461 case MAP(1, 0x01, 0x06): /* AUTDA */
5462 if (s
->pauth_active
) {
5463 tcg_rd
= cpu_reg(s
, rd
);
5464 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5465 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5466 goto do_unallocated
;
5469 case MAP(1, 0x01, 0x07): /* AUTDB */
5470 if (s
->pauth_active
) {
5471 tcg_rd
= cpu_reg(s
, rd
);
5472 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5473 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5474 goto do_unallocated
;
5477 case MAP(1, 0x01, 0x08): /* PACIZA */
5478 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5479 goto do_unallocated
;
5480 } else if (s
->pauth_active
) {
5481 tcg_rd
= cpu_reg(s
, rd
);
5482 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5485 case MAP(1, 0x01, 0x09): /* PACIZB */
5486 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5487 goto do_unallocated
;
5488 } else if (s
->pauth_active
) {
5489 tcg_rd
= cpu_reg(s
, rd
);
5490 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5493 case MAP(1, 0x01, 0x0a): /* PACDZA */
5494 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5495 goto do_unallocated
;
5496 } else if (s
->pauth_active
) {
5497 tcg_rd
= cpu_reg(s
, rd
);
5498 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5501 case MAP(1, 0x01, 0x0b): /* PACDZB */
5502 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5503 goto do_unallocated
;
5504 } else if (s
->pauth_active
) {
5505 tcg_rd
= cpu_reg(s
, rd
);
5506 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5509 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5510 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5511 goto do_unallocated
;
5512 } else if (s
->pauth_active
) {
5513 tcg_rd
= cpu_reg(s
, rd
);
5514 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5517 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5518 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5519 goto do_unallocated
;
5520 } else if (s
->pauth_active
) {
5521 tcg_rd
= cpu_reg(s
, rd
);
5522 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5525 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5526 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5527 goto do_unallocated
;
5528 } else if (s
->pauth_active
) {
5529 tcg_rd
= cpu_reg(s
, rd
);
5530 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5533 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5534 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5535 goto do_unallocated
;
5536 } else if (s
->pauth_active
) {
5537 tcg_rd
= cpu_reg(s
, rd
);
5538 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5541 case MAP(1, 0x01, 0x10): /* XPACI */
5542 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5543 goto do_unallocated
;
5544 } else if (s
->pauth_active
) {
5545 tcg_rd
= cpu_reg(s
, rd
);
5546 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5549 case MAP(1, 0x01, 0x11): /* XPACD */
5550 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5551 goto do_unallocated
;
5552 } else if (s
->pauth_active
) {
5553 tcg_rd
= cpu_reg(s
, rd
);
5554 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5559 unallocated_encoding(s
);
5566 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5567 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5569 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5570 tcg_rd
= cpu_reg(s
, rd
);
5572 if (!sf
&& is_signed
) {
5573 tcg_n
= new_tmp_a64(s
);
5574 tcg_m
= new_tmp_a64(s
);
5575 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5576 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5578 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5579 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5583 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5585 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5588 if (!sf
) { /* zero extend final result */
5589 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5593 /* LSLV, LSRV, ASRV, RORV */
5594 static void handle_shift_reg(DisasContext
*s
,
5595 enum a64_shift_type shift_type
, unsigned int sf
,
5596 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5598 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5599 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5600 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5602 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5603 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5604 tcg_temp_free_i64(tcg_shift
);
5607 /* CRC32[BHWX], CRC32C[BHWX] */
5608 static void handle_crc32(DisasContext
*s
,
5609 unsigned int sf
, unsigned int sz
, bool crc32c
,
5610 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5612 TCGv_i64 tcg_acc
, tcg_val
;
5615 if (!dc_isar_feature(aa64_crc32
, s
)
5616 || (sf
== 1 && sz
!= 3)
5617 || (sf
== 0 && sz
== 3)) {
5618 unallocated_encoding(s
);
5623 tcg_val
= cpu_reg(s
, rm
);
5637 g_assert_not_reached();
5639 tcg_val
= new_tmp_a64(s
);
5640 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5643 tcg_acc
= cpu_reg(s
, rn
);
5644 tcg_bytes
= tcg_const_i32(1 << sz
);
5647 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5649 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5652 tcg_temp_free_i32(tcg_bytes
);
5655 /* Data-processing (2 source)
5656 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5657 * +----+---+---+-----------------+------+--------+------+------+
5658 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5659 * +----+---+---+-----------------+------+--------+------+------+
5661 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5663 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5664 sf
= extract32(insn
, 31, 1);
5665 setflag
= extract32(insn
, 29, 1);
5666 rm
= extract32(insn
, 16, 5);
5667 opcode
= extract32(insn
, 10, 6);
5668 rn
= extract32(insn
, 5, 5);
5669 rd
= extract32(insn
, 0, 5);
5671 if (setflag
&& opcode
!= 0) {
5672 unallocated_encoding(s
);
5677 case 0: /* SUBP(S) */
5678 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5679 goto do_unallocated
;
5681 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5683 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5684 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5685 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5686 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5687 tcg_d
= cpu_reg(s
, rd
);
5690 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5692 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5697 handle_div(s
, false, sf
, rm
, rn
, rd
);
5700 handle_div(s
, true, sf
, rm
, rn
, rd
);
5703 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5704 goto do_unallocated
;
5707 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5708 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5710 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5715 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5716 goto do_unallocated
;
5718 TCGv_i64 t1
= tcg_const_i64(1);
5719 TCGv_i64 t2
= tcg_temp_new_i64();
5721 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5722 tcg_gen_shl_i64(t1
, t1
, t2
);
5723 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5725 tcg_temp_free_i64(t1
);
5726 tcg_temp_free_i64(t2
);
5730 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5733 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5736 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5739 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5741 case 12: /* PACGA */
5742 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5743 goto do_unallocated
;
5745 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5746 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5755 case 23: /* CRC32 */
5757 int sz
= extract32(opcode
, 0, 2);
5758 bool crc32c
= extract32(opcode
, 2, 1);
5759 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5764 unallocated_encoding(s
);
5770 * Data processing - register
5771 * 31 30 29 28 25 21 20 16 10 0
5772 * +--+---+--+---+-------+-----+-------+-------+---------+
5773 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5774 * +--+---+--+---+-------+-----+-------+-------+---------+
5776 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5778 int op0
= extract32(insn
, 30, 1);
5779 int op1
= extract32(insn
, 28, 1);
5780 int op2
= extract32(insn
, 21, 4);
5781 int op3
= extract32(insn
, 10, 6);
5786 /* Add/sub (extended register) */
5787 disas_add_sub_ext_reg(s
, insn
);
5789 /* Add/sub (shifted register) */
5790 disas_add_sub_reg(s
, insn
);
5793 /* Logical (shifted register) */
5794 disas_logic_reg(s
, insn
);
5802 case 0x00: /* Add/subtract (with carry) */
5803 disas_adc_sbc(s
, insn
);
5806 case 0x01: /* Rotate right into flags */
5808 disas_rotate_right_into_flags(s
, insn
);
5811 case 0x02: /* Evaluate into flags */
5815 disas_evaluate_into_flags(s
, insn
);
5819 goto do_unallocated
;
5823 case 0x2: /* Conditional compare */
5824 disas_cc(s
, insn
); /* both imm and reg forms */
5827 case 0x4: /* Conditional select */
5828 disas_cond_select(s
, insn
);
5831 case 0x6: /* Data-processing */
5832 if (op0
) { /* (1 source) */
5833 disas_data_proc_1src(s
, insn
);
5834 } else { /* (2 source) */
5835 disas_data_proc_2src(s
, insn
);
5838 case 0x8 ... 0xf: /* (3 source) */
5839 disas_data_proc_3src(s
, insn
);
5844 unallocated_encoding(s
);
5849 static void handle_fp_compare(DisasContext
*s
, int size
,
5850 unsigned int rn
, unsigned int rm
,
5851 bool cmp_with_zero
, bool signal_all_nans
)
5853 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5854 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5856 if (size
== MO_64
) {
5857 TCGv_i64 tcg_vn
, tcg_vm
;
5859 tcg_vn
= read_fp_dreg(s
, rn
);
5860 if (cmp_with_zero
) {
5861 tcg_vm
= tcg_const_i64(0);
5863 tcg_vm
= read_fp_dreg(s
, rm
);
5865 if (signal_all_nans
) {
5866 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5868 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5870 tcg_temp_free_i64(tcg_vn
);
5871 tcg_temp_free_i64(tcg_vm
);
5873 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5874 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5876 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5877 if (cmp_with_zero
) {
5878 tcg_gen_movi_i32(tcg_vm
, 0);
5880 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5885 if (signal_all_nans
) {
5886 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5888 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5892 if (signal_all_nans
) {
5893 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5895 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5899 g_assert_not_reached();
5902 tcg_temp_free_i32(tcg_vn
);
5903 tcg_temp_free_i32(tcg_vm
);
5906 tcg_temp_free_ptr(fpst
);
5908 gen_set_nzcv(tcg_flags
);
5910 tcg_temp_free_i64(tcg_flags
);
5913 /* Floating point compare
5914 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5915 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5916 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5917 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5919 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5921 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5924 mos
= extract32(insn
, 29, 3);
5925 type
= extract32(insn
, 22, 2);
5926 rm
= extract32(insn
, 16, 5);
5927 op
= extract32(insn
, 14, 2);
5928 rn
= extract32(insn
, 5, 5);
5929 opc
= extract32(insn
, 3, 2);
5930 op2r
= extract32(insn
, 0, 3);
5932 if (mos
|| op
|| op2r
) {
5933 unallocated_encoding(s
);
5946 if (dc_isar_feature(aa64_fp16
, s
)) {
5951 unallocated_encoding(s
);
5955 if (!fp_access_check(s
)) {
5959 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5962 /* Floating point conditional compare
5963 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5964 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5965 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5966 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5968 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5970 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5972 TCGLabel
*label_continue
= NULL
;
5975 mos
= extract32(insn
, 29, 3);
5976 type
= extract32(insn
, 22, 2);
5977 rm
= extract32(insn
, 16, 5);
5978 cond
= extract32(insn
, 12, 4);
5979 rn
= extract32(insn
, 5, 5);
5980 op
= extract32(insn
, 4, 1);
5981 nzcv
= extract32(insn
, 0, 4);
5984 unallocated_encoding(s
);
5997 if (dc_isar_feature(aa64_fp16
, s
)) {
6002 unallocated_encoding(s
);
6006 if (!fp_access_check(s
)) {
6010 if (cond
< 0x0e) { /* not always */
6011 TCGLabel
*label_match
= gen_new_label();
6012 label_continue
= gen_new_label();
6013 arm_gen_test_cc(cond
, label_match
);
6015 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6016 gen_set_nzcv(tcg_flags
);
6017 tcg_temp_free_i64(tcg_flags
);
6018 tcg_gen_br(label_continue
);
6019 gen_set_label(label_match
);
6022 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6025 gen_set_label(label_continue
);
6029 /* Floating point conditional select
6030 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6031 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6032 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6033 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6035 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6037 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6038 TCGv_i64 t_true
, t_false
, t_zero
;
6042 mos
= extract32(insn
, 29, 3);
6043 type
= extract32(insn
, 22, 2);
6044 rm
= extract32(insn
, 16, 5);
6045 cond
= extract32(insn
, 12, 4);
6046 rn
= extract32(insn
, 5, 5);
6047 rd
= extract32(insn
, 0, 5);
6050 unallocated_encoding(s
);
6063 if (dc_isar_feature(aa64_fp16
, s
)) {
6068 unallocated_encoding(s
);
6072 if (!fp_access_check(s
)) {
6076 /* Zero extend sreg & hreg inputs to 64 bits now. */
6077 t_true
= tcg_temp_new_i64();
6078 t_false
= tcg_temp_new_i64();
6079 read_vec_element(s
, t_true
, rn
, 0, sz
);
6080 read_vec_element(s
, t_false
, rm
, 0, sz
);
6082 a64_test_cc(&c
, cond
);
6083 t_zero
= tcg_const_i64(0);
6084 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6085 tcg_temp_free_i64(t_zero
);
6086 tcg_temp_free_i64(t_false
);
6089 /* Note that sregs & hregs write back zeros to the high bits,
6090 and we've already done the zero-extension. */
6091 write_fp_dreg(s
, rd
, t_true
);
6092 tcg_temp_free_i64(t_true
);
6095 /* Floating-point data-processing (1 source) - half precision */
6096 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6098 TCGv_ptr fpst
= NULL
;
6099 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6100 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6103 case 0x0: /* FMOV */
6104 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6106 case 0x1: /* FABS */
6107 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6109 case 0x2: /* FNEG */
6110 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6112 case 0x3: /* FSQRT */
6113 fpst
= get_fpstatus_ptr(true);
6114 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6116 case 0x8: /* FRINTN */
6117 case 0x9: /* FRINTP */
6118 case 0xa: /* FRINTM */
6119 case 0xb: /* FRINTZ */
6120 case 0xc: /* FRINTA */
6122 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6123 fpst
= get_fpstatus_ptr(true);
6125 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6126 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6128 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6129 tcg_temp_free_i32(tcg_rmode
);
6132 case 0xe: /* FRINTX */
6133 fpst
= get_fpstatus_ptr(true);
6134 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6136 case 0xf: /* FRINTI */
6137 fpst
= get_fpstatus_ptr(true);
6138 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6144 write_fp_sreg(s
, rd
, tcg_res
);
6147 tcg_temp_free_ptr(fpst
);
6149 tcg_temp_free_i32(tcg_op
);
6150 tcg_temp_free_i32(tcg_res
);
6153 /* Floating-point data-processing (1 source) - single precision */
6154 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6156 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6157 TCGv_i32 tcg_op
, tcg_res
;
6161 tcg_op
= read_fp_sreg(s
, rn
);
6162 tcg_res
= tcg_temp_new_i32();
6165 case 0x0: /* FMOV */
6166 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6168 case 0x1: /* FABS */
6169 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6171 case 0x2: /* FNEG */
6172 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6174 case 0x3: /* FSQRT */
6175 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6177 case 0x8: /* FRINTN */
6178 case 0x9: /* FRINTP */
6179 case 0xa: /* FRINTM */
6180 case 0xb: /* FRINTZ */
6181 case 0xc: /* FRINTA */
6182 rmode
= arm_rmode_to_sf(opcode
& 7);
6183 gen_fpst
= gen_helper_rints
;
6185 case 0xe: /* FRINTX */
6186 gen_fpst
= gen_helper_rints_exact
;
6188 case 0xf: /* FRINTI */
6189 gen_fpst
= gen_helper_rints
;
6191 case 0x10: /* FRINT32Z */
6192 rmode
= float_round_to_zero
;
6193 gen_fpst
= gen_helper_frint32_s
;
6195 case 0x11: /* FRINT32X */
6196 gen_fpst
= gen_helper_frint32_s
;
6198 case 0x12: /* FRINT64Z */
6199 rmode
= float_round_to_zero
;
6200 gen_fpst
= gen_helper_frint64_s
;
6202 case 0x13: /* FRINT64X */
6203 gen_fpst
= gen_helper_frint64_s
;
6206 g_assert_not_reached();
6209 fpst
= get_fpstatus_ptr(false);
6211 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6212 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6213 gen_fpst(tcg_res
, tcg_op
, fpst
);
6214 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6215 tcg_temp_free_i32(tcg_rmode
);
6217 gen_fpst(tcg_res
, tcg_op
, fpst
);
6219 tcg_temp_free_ptr(fpst
);
6222 write_fp_sreg(s
, rd
, tcg_res
);
6223 tcg_temp_free_i32(tcg_op
);
6224 tcg_temp_free_i32(tcg_res
);
6227 /* Floating-point data-processing (1 source) - double precision */
6228 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6230 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6231 TCGv_i64 tcg_op
, tcg_res
;
6236 case 0x0: /* FMOV */
6237 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6241 tcg_op
= read_fp_dreg(s
, rn
);
6242 tcg_res
= tcg_temp_new_i64();
6245 case 0x1: /* FABS */
6246 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6248 case 0x2: /* FNEG */
6249 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6251 case 0x3: /* FSQRT */
6252 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6254 case 0x8: /* FRINTN */
6255 case 0x9: /* FRINTP */
6256 case 0xa: /* FRINTM */
6257 case 0xb: /* FRINTZ */
6258 case 0xc: /* FRINTA */
6259 rmode
= arm_rmode_to_sf(opcode
& 7);
6260 gen_fpst
= gen_helper_rintd
;
6262 case 0xe: /* FRINTX */
6263 gen_fpst
= gen_helper_rintd_exact
;
6265 case 0xf: /* FRINTI */
6266 gen_fpst
= gen_helper_rintd
;
6268 case 0x10: /* FRINT32Z */
6269 rmode
= float_round_to_zero
;
6270 gen_fpst
= gen_helper_frint32_d
;
6272 case 0x11: /* FRINT32X */
6273 gen_fpst
= gen_helper_frint32_d
;
6275 case 0x12: /* FRINT64Z */
6276 rmode
= float_round_to_zero
;
6277 gen_fpst
= gen_helper_frint64_d
;
6279 case 0x13: /* FRINT64X */
6280 gen_fpst
= gen_helper_frint64_d
;
6283 g_assert_not_reached();
6286 fpst
= get_fpstatus_ptr(false);
6288 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6289 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6290 gen_fpst(tcg_res
, tcg_op
, fpst
);
6291 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6292 tcg_temp_free_i32(tcg_rmode
);
6294 gen_fpst(tcg_res
, tcg_op
, fpst
);
6296 tcg_temp_free_ptr(fpst
);
6299 write_fp_dreg(s
, rd
, tcg_res
);
6300 tcg_temp_free_i64(tcg_op
);
6301 tcg_temp_free_i64(tcg_res
);
6304 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6305 int rd
, int rn
, int dtype
, int ntype
)
6310 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6312 /* Single to double */
6313 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6314 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6315 write_fp_dreg(s
, rd
, tcg_rd
);
6316 tcg_temp_free_i64(tcg_rd
);
6318 /* Single to half */
6319 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6320 TCGv_i32 ahp
= get_ahp_flag();
6321 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6323 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6324 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6325 write_fp_sreg(s
, rd
, tcg_rd
);
6326 tcg_temp_free_i32(tcg_rd
);
6327 tcg_temp_free_i32(ahp
);
6328 tcg_temp_free_ptr(fpst
);
6330 tcg_temp_free_i32(tcg_rn
);
6335 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6336 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6338 /* Double to single */
6339 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6341 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6342 TCGv_i32 ahp
= get_ahp_flag();
6343 /* Double to half */
6344 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6345 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6346 tcg_temp_free_ptr(fpst
);
6347 tcg_temp_free_i32(ahp
);
6349 write_fp_sreg(s
, rd
, tcg_rd
);
6350 tcg_temp_free_i32(tcg_rd
);
6351 tcg_temp_free_i64(tcg_rn
);
6356 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6357 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
6358 TCGv_i32 tcg_ahp
= get_ahp_flag();
6359 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6361 /* Half to single */
6362 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6363 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6364 write_fp_sreg(s
, rd
, tcg_rd
);
6365 tcg_temp_free_i32(tcg_rd
);
6367 /* Half to double */
6368 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6369 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6370 write_fp_dreg(s
, rd
, tcg_rd
);
6371 tcg_temp_free_i64(tcg_rd
);
6373 tcg_temp_free_i32(tcg_rn
);
6374 tcg_temp_free_ptr(tcg_fpst
);
6375 tcg_temp_free_i32(tcg_ahp
);
6383 /* Floating point data-processing (1 source)
6384 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6385 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6386 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6387 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6389 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6391 int mos
= extract32(insn
, 29, 3);
6392 int type
= extract32(insn
, 22, 2);
6393 int opcode
= extract32(insn
, 15, 6);
6394 int rn
= extract32(insn
, 5, 5);
6395 int rd
= extract32(insn
, 0, 5);
6398 unallocated_encoding(s
);
6403 case 0x4: case 0x5: case 0x7:
6405 /* FCVT between half, single and double precision */
6406 int dtype
= extract32(opcode
, 0, 2);
6407 if (type
== 2 || dtype
== type
) {
6408 unallocated_encoding(s
);
6411 if (!fp_access_check(s
)) {
6415 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6419 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6420 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6421 unallocated_encoding(s
);
6428 /* 32-to-32 and 64-to-64 ops */
6431 if (!fp_access_check(s
)) {
6434 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6437 if (!fp_access_check(s
)) {
6440 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6443 if (!dc_isar_feature(aa64_fp16
, s
)) {
6444 unallocated_encoding(s
);
6448 if (!fp_access_check(s
)) {
6451 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6454 unallocated_encoding(s
);
6459 unallocated_encoding(s
);
6464 /* Floating-point data-processing (2 source) - single precision */
6465 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6466 int rd
, int rn
, int rm
)
6473 tcg_res
= tcg_temp_new_i32();
6474 fpst
= get_fpstatus_ptr(false);
6475 tcg_op1
= read_fp_sreg(s
, rn
);
6476 tcg_op2
= read_fp_sreg(s
, rm
);
6479 case 0x0: /* FMUL */
6480 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6482 case 0x1: /* FDIV */
6483 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6485 case 0x2: /* FADD */
6486 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6488 case 0x3: /* FSUB */
6489 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6491 case 0x4: /* FMAX */
6492 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6494 case 0x5: /* FMIN */
6495 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6497 case 0x6: /* FMAXNM */
6498 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6500 case 0x7: /* FMINNM */
6501 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6503 case 0x8: /* FNMUL */
6504 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6505 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6509 write_fp_sreg(s
, rd
, tcg_res
);
6511 tcg_temp_free_ptr(fpst
);
6512 tcg_temp_free_i32(tcg_op1
);
6513 tcg_temp_free_i32(tcg_op2
);
6514 tcg_temp_free_i32(tcg_res
);
6517 /* Floating-point data-processing (2 source) - double precision */
6518 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6519 int rd
, int rn
, int rm
)
6526 tcg_res
= tcg_temp_new_i64();
6527 fpst
= get_fpstatus_ptr(false);
6528 tcg_op1
= read_fp_dreg(s
, rn
);
6529 tcg_op2
= read_fp_dreg(s
, rm
);
6532 case 0x0: /* FMUL */
6533 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6535 case 0x1: /* FDIV */
6536 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6538 case 0x2: /* FADD */
6539 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6541 case 0x3: /* FSUB */
6542 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6544 case 0x4: /* FMAX */
6545 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6547 case 0x5: /* FMIN */
6548 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6550 case 0x6: /* FMAXNM */
6551 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6553 case 0x7: /* FMINNM */
6554 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6556 case 0x8: /* FNMUL */
6557 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6558 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6562 write_fp_dreg(s
, rd
, tcg_res
);
6564 tcg_temp_free_ptr(fpst
);
6565 tcg_temp_free_i64(tcg_op1
);
6566 tcg_temp_free_i64(tcg_op2
);
6567 tcg_temp_free_i64(tcg_res
);
6570 /* Floating-point data-processing (2 source) - half precision */
6571 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6572 int rd
, int rn
, int rm
)
6579 tcg_res
= tcg_temp_new_i32();
6580 fpst
= get_fpstatus_ptr(true);
6581 tcg_op1
= read_fp_hreg(s
, rn
);
6582 tcg_op2
= read_fp_hreg(s
, rm
);
6585 case 0x0: /* FMUL */
6586 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6588 case 0x1: /* FDIV */
6589 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6591 case 0x2: /* FADD */
6592 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6594 case 0x3: /* FSUB */
6595 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6597 case 0x4: /* FMAX */
6598 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6600 case 0x5: /* FMIN */
6601 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6603 case 0x6: /* FMAXNM */
6604 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6606 case 0x7: /* FMINNM */
6607 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6609 case 0x8: /* FNMUL */
6610 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6611 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6614 g_assert_not_reached();
6617 write_fp_sreg(s
, rd
, tcg_res
);
6619 tcg_temp_free_ptr(fpst
);
6620 tcg_temp_free_i32(tcg_op1
);
6621 tcg_temp_free_i32(tcg_op2
);
6622 tcg_temp_free_i32(tcg_res
);
6625 /* Floating point data-processing (2 source)
6626 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6627 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6628 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6629 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6631 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6633 int mos
= extract32(insn
, 29, 3);
6634 int type
= extract32(insn
, 22, 2);
6635 int rd
= extract32(insn
, 0, 5);
6636 int rn
= extract32(insn
, 5, 5);
6637 int rm
= extract32(insn
, 16, 5);
6638 int opcode
= extract32(insn
, 12, 4);
6640 if (opcode
> 8 || mos
) {
6641 unallocated_encoding(s
);
6647 if (!fp_access_check(s
)) {
6650 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6653 if (!fp_access_check(s
)) {
6656 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6659 if (!dc_isar_feature(aa64_fp16
, s
)) {
6660 unallocated_encoding(s
);
6663 if (!fp_access_check(s
)) {
6666 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6669 unallocated_encoding(s
);
6673 /* Floating-point data-processing (3 source) - single precision */
6674 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6675 int rd
, int rn
, int rm
, int ra
)
6677 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6678 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6679 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6681 tcg_op1
= read_fp_sreg(s
, rn
);
6682 tcg_op2
= read_fp_sreg(s
, rm
);
6683 tcg_op3
= read_fp_sreg(s
, ra
);
6685 /* These are fused multiply-add, and must be done as one
6686 * floating point operation with no rounding between the
6687 * multiplication and addition steps.
6688 * NB that doing the negations here as separate steps is
6689 * correct : an input NaN should come out with its sign bit
6690 * flipped if it is a negated-input.
6693 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6697 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6700 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6702 write_fp_sreg(s
, rd
, tcg_res
);
6704 tcg_temp_free_ptr(fpst
);
6705 tcg_temp_free_i32(tcg_op1
);
6706 tcg_temp_free_i32(tcg_op2
);
6707 tcg_temp_free_i32(tcg_op3
);
6708 tcg_temp_free_i32(tcg_res
);
6711 /* Floating-point data-processing (3 source) - double precision */
6712 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6713 int rd
, int rn
, int rm
, int ra
)
6715 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6716 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6717 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6719 tcg_op1
= read_fp_dreg(s
, rn
);
6720 tcg_op2
= read_fp_dreg(s
, rm
);
6721 tcg_op3
= read_fp_dreg(s
, ra
);
6723 /* These are fused multiply-add, and must be done as one
6724 * floating point operation with no rounding between the
6725 * multiplication and addition steps.
6726 * NB that doing the negations here as separate steps is
6727 * correct : an input NaN should come out with its sign bit
6728 * flipped if it is a negated-input.
6731 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6735 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6738 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6740 write_fp_dreg(s
, rd
, tcg_res
);
6742 tcg_temp_free_ptr(fpst
);
6743 tcg_temp_free_i64(tcg_op1
);
6744 tcg_temp_free_i64(tcg_op2
);
6745 tcg_temp_free_i64(tcg_op3
);
6746 tcg_temp_free_i64(tcg_res
);
6749 /* Floating-point data-processing (3 source) - half precision */
6750 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6751 int rd
, int rn
, int rm
, int ra
)
6753 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6754 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6755 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6757 tcg_op1
= read_fp_hreg(s
, rn
);
6758 tcg_op2
= read_fp_hreg(s
, rm
);
6759 tcg_op3
= read_fp_hreg(s
, ra
);
6761 /* These are fused multiply-add, and must be done as one
6762 * floating point operation with no rounding between the
6763 * multiplication and addition steps.
6764 * NB that doing the negations here as separate steps is
6765 * correct : an input NaN should come out with its sign bit
6766 * flipped if it is a negated-input.
6769 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6773 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6776 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6778 write_fp_sreg(s
, rd
, tcg_res
);
6780 tcg_temp_free_ptr(fpst
);
6781 tcg_temp_free_i32(tcg_op1
);
6782 tcg_temp_free_i32(tcg_op2
);
6783 tcg_temp_free_i32(tcg_op3
);
6784 tcg_temp_free_i32(tcg_res
);
6787 /* Floating point data-processing (3 source)
6788 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6789 * +---+---+---+-----------+------+----+------+----+------+------+------+
6790 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6791 * +---+---+---+-----------+------+----+------+----+------+------+------+
6793 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6795 int mos
= extract32(insn
, 29, 3);
6796 int type
= extract32(insn
, 22, 2);
6797 int rd
= extract32(insn
, 0, 5);
6798 int rn
= extract32(insn
, 5, 5);
6799 int ra
= extract32(insn
, 10, 5);
6800 int rm
= extract32(insn
, 16, 5);
6801 bool o0
= extract32(insn
, 15, 1);
6802 bool o1
= extract32(insn
, 21, 1);
6805 unallocated_encoding(s
);
6811 if (!fp_access_check(s
)) {
6814 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6817 if (!fp_access_check(s
)) {
6820 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6823 if (!dc_isar_feature(aa64_fp16
, s
)) {
6824 unallocated_encoding(s
);
6827 if (!fp_access_check(s
)) {
6830 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6833 unallocated_encoding(s
);
6837 /* Floating point immediate
6838 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6839 * +---+---+---+-----------+------+---+------------+-------+------+------+
6840 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6841 * +---+---+---+-----------+------+---+------------+-------+------+------+
6843 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6845 int rd
= extract32(insn
, 0, 5);
6846 int imm5
= extract32(insn
, 5, 5);
6847 int imm8
= extract32(insn
, 13, 8);
6848 int type
= extract32(insn
, 22, 2);
6849 int mos
= extract32(insn
, 29, 3);
6855 unallocated_encoding(s
);
6868 if (dc_isar_feature(aa64_fp16
, s
)) {
6873 unallocated_encoding(s
);
6877 if (!fp_access_check(s
)) {
6881 imm
= vfp_expand_imm(sz
, imm8
);
6883 tcg_res
= tcg_const_i64(imm
);
6884 write_fp_dreg(s
, rd
, tcg_res
);
6885 tcg_temp_free_i64(tcg_res
);
6888 /* Handle floating point <=> fixed point conversions. Note that we can
6889 * also deal with fp <=> integer conversions as a special case (scale == 64)
6890 * OPTME: consider handling that special case specially or at least skipping
6891 * the call to scalbn in the helpers for zero shifts.
6893 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6894 bool itof
, int rmode
, int scale
, int sf
, int type
)
6896 bool is_signed
= !(opcode
& 1);
6897 TCGv_ptr tcg_fpstatus
;
6898 TCGv_i32 tcg_shift
, tcg_single
;
6899 TCGv_i64 tcg_double
;
6901 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6903 tcg_shift
= tcg_const_i32(64 - scale
);
6906 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6908 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6911 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6913 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6916 tcg_int
= tcg_extend
;
6920 case 1: /* float64 */
6921 tcg_double
= tcg_temp_new_i64();
6923 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6924 tcg_shift
, tcg_fpstatus
);
6926 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6927 tcg_shift
, tcg_fpstatus
);
6929 write_fp_dreg(s
, rd
, tcg_double
);
6930 tcg_temp_free_i64(tcg_double
);
6933 case 0: /* float32 */
6934 tcg_single
= tcg_temp_new_i32();
6936 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6937 tcg_shift
, tcg_fpstatus
);
6939 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6940 tcg_shift
, tcg_fpstatus
);
6942 write_fp_sreg(s
, rd
, tcg_single
);
6943 tcg_temp_free_i32(tcg_single
);
6946 case 3: /* float16 */
6947 tcg_single
= tcg_temp_new_i32();
6949 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6950 tcg_shift
, tcg_fpstatus
);
6952 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6953 tcg_shift
, tcg_fpstatus
);
6955 write_fp_sreg(s
, rd
, tcg_single
);
6956 tcg_temp_free_i32(tcg_single
);
6960 g_assert_not_reached();
6963 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6966 if (extract32(opcode
, 2, 1)) {
6967 /* There are too many rounding modes to all fit into rmode,
6968 * so FCVTA[US] is a special case.
6970 rmode
= FPROUNDING_TIEAWAY
;
6973 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6975 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6978 case 1: /* float64 */
6979 tcg_double
= read_fp_dreg(s
, rn
);
6982 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6983 tcg_shift
, tcg_fpstatus
);
6985 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6986 tcg_shift
, tcg_fpstatus
);
6990 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6991 tcg_shift
, tcg_fpstatus
);
6993 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6994 tcg_shift
, tcg_fpstatus
);
6998 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7000 tcg_temp_free_i64(tcg_double
);
7003 case 0: /* float32 */
7004 tcg_single
= read_fp_sreg(s
, rn
);
7007 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7008 tcg_shift
, tcg_fpstatus
);
7010 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7011 tcg_shift
, tcg_fpstatus
);
7014 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7016 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7017 tcg_shift
, tcg_fpstatus
);
7019 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7020 tcg_shift
, tcg_fpstatus
);
7022 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7023 tcg_temp_free_i32(tcg_dest
);
7025 tcg_temp_free_i32(tcg_single
);
7028 case 3: /* float16 */
7029 tcg_single
= read_fp_sreg(s
, rn
);
7032 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7033 tcg_shift
, tcg_fpstatus
);
7035 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7036 tcg_shift
, tcg_fpstatus
);
7039 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7041 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7042 tcg_shift
, tcg_fpstatus
);
7044 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7045 tcg_shift
, tcg_fpstatus
);
7047 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7048 tcg_temp_free_i32(tcg_dest
);
7050 tcg_temp_free_i32(tcg_single
);
7054 g_assert_not_reached();
7057 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7058 tcg_temp_free_i32(tcg_rmode
);
7061 tcg_temp_free_ptr(tcg_fpstatus
);
7062 tcg_temp_free_i32(tcg_shift
);
7065 /* Floating point <-> fixed point conversions
7066 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7067 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7068 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7069 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7071 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7073 int rd
= extract32(insn
, 0, 5);
7074 int rn
= extract32(insn
, 5, 5);
7075 int scale
= extract32(insn
, 10, 6);
7076 int opcode
= extract32(insn
, 16, 3);
7077 int rmode
= extract32(insn
, 19, 2);
7078 int type
= extract32(insn
, 22, 2);
7079 bool sbit
= extract32(insn
, 29, 1);
7080 bool sf
= extract32(insn
, 31, 1);
7083 if (sbit
|| (!sf
&& scale
< 32)) {
7084 unallocated_encoding(s
);
7089 case 0: /* float32 */
7090 case 1: /* float64 */
7092 case 3: /* float16 */
7093 if (dc_isar_feature(aa64_fp16
, s
)) {
7098 unallocated_encoding(s
);
7102 switch ((rmode
<< 3) | opcode
) {
7103 case 0x2: /* SCVTF */
7104 case 0x3: /* UCVTF */
7107 case 0x18: /* FCVTZS */
7108 case 0x19: /* FCVTZU */
7112 unallocated_encoding(s
);
7116 if (!fp_access_check(s
)) {
7120 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7123 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7125 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7126 * without conversion.
7130 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7136 tmp
= tcg_temp_new_i64();
7137 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7138 write_fp_dreg(s
, rd
, tmp
);
7139 tcg_temp_free_i64(tmp
);
7143 write_fp_dreg(s
, rd
, tcg_rn
);
7146 /* 64 bit to top half. */
7147 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7148 clear_vec_high(s
, true, rd
);
7152 tmp
= tcg_temp_new_i64();
7153 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7154 write_fp_dreg(s
, rd
, tmp
);
7155 tcg_temp_free_i64(tmp
);
7158 g_assert_not_reached();
7161 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7166 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7170 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7173 /* 64 bits from top half */
7174 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7178 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7181 g_assert_not_reached();
7186 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7188 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7189 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
7191 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7193 tcg_temp_free_ptr(fpstatus
);
7195 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7196 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7197 tcg_gen_movi_i32(cpu_CF
, 0);
7198 tcg_gen_movi_i32(cpu_NF
, 0);
7199 tcg_gen_movi_i32(cpu_VF
, 0);
7201 tcg_temp_free_i64(t
);
7204 /* Floating point <-> integer conversions
7205 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7206 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7207 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7208 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7210 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7212 int rd
= extract32(insn
, 0, 5);
7213 int rn
= extract32(insn
, 5, 5);
7214 int opcode
= extract32(insn
, 16, 3);
7215 int rmode
= extract32(insn
, 19, 2);
7216 int type
= extract32(insn
, 22, 2);
7217 bool sbit
= extract32(insn
, 29, 1);
7218 bool sf
= extract32(insn
, 31, 1);
7222 goto do_unallocated
;
7230 case 4: /* FCVTAS */
7231 case 5: /* FCVTAU */
7233 goto do_unallocated
;
7236 case 0: /* FCVT[NPMZ]S */
7237 case 1: /* FCVT[NPMZ]U */
7239 case 0: /* float32 */
7240 case 1: /* float64 */
7242 case 3: /* float16 */
7243 if (!dc_isar_feature(aa64_fp16
, s
)) {
7244 goto do_unallocated
;
7248 goto do_unallocated
;
7250 if (!fp_access_check(s
)) {
7253 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7257 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7258 case 0b01100110: /* FMOV half <-> 32-bit int */
7260 case 0b11100110: /* FMOV half <-> 64-bit int */
7262 if (!dc_isar_feature(aa64_fp16
, s
)) {
7263 goto do_unallocated
;
7266 case 0b00000110: /* FMOV 32-bit */
7268 case 0b10100110: /* FMOV 64-bit */
7270 case 0b11001110: /* FMOV top half of 128-bit */
7272 if (!fp_access_check(s
)) {
7276 handle_fmov(s
, rd
, rn
, type
, itof
);
7279 case 0b00111110: /* FJCVTZS */
7280 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7281 goto do_unallocated
;
7282 } else if (fp_access_check(s
)) {
7283 handle_fjcvtzs(s
, rd
, rn
);
7289 unallocated_encoding(s
);
7296 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7297 * 31 30 29 28 25 24 0
7298 * +---+---+---+---------+-----------------------------+
7299 * | | 0 | | 1 1 1 1 | |
7300 * +---+---+---+---------+-----------------------------+
7302 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7304 if (extract32(insn
, 24, 1)) {
7305 /* Floating point data-processing (3 source) */
7306 disas_fp_3src(s
, insn
);
7307 } else if (extract32(insn
, 21, 1) == 0) {
7308 /* Floating point to fixed point conversions */
7309 disas_fp_fixed_conv(s
, insn
);
7311 switch (extract32(insn
, 10, 2)) {
7313 /* Floating point conditional compare */
7314 disas_fp_ccomp(s
, insn
);
7317 /* Floating point data-processing (2 source) */
7318 disas_fp_2src(s
, insn
);
7321 /* Floating point conditional select */
7322 disas_fp_csel(s
, insn
);
7325 switch (ctz32(extract32(insn
, 12, 4))) {
7326 case 0: /* [15:12] == xxx1 */
7327 /* Floating point immediate */
7328 disas_fp_imm(s
, insn
);
7330 case 1: /* [15:12] == xx10 */
7331 /* Floating point compare */
7332 disas_fp_compare(s
, insn
);
7334 case 2: /* [15:12] == x100 */
7335 /* Floating point data-processing (1 source) */
7336 disas_fp_1src(s
, insn
);
7338 case 3: /* [15:12] == 1000 */
7339 unallocated_encoding(s
);
7341 default: /* [15:12] == 0000 */
7342 /* Floating point <-> integer conversions */
7343 disas_fp_int_conv(s
, insn
);
7351 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7354 /* Extract 64 bits from the middle of two concatenated 64 bit
7355 * vector register slices left:right. The extracted bits start
7356 * at 'pos' bits into the right (least significant) side.
7357 * We return the result in tcg_right, and guarantee not to
7360 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7361 assert(pos
> 0 && pos
< 64);
7363 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7364 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7365 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7367 tcg_temp_free_i64(tcg_tmp
);
7371 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7372 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7373 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7374 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7376 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7378 int is_q
= extract32(insn
, 30, 1);
7379 int op2
= extract32(insn
, 22, 2);
7380 int imm4
= extract32(insn
, 11, 4);
7381 int rm
= extract32(insn
, 16, 5);
7382 int rn
= extract32(insn
, 5, 5);
7383 int rd
= extract32(insn
, 0, 5);
7384 int pos
= imm4
<< 3;
7385 TCGv_i64 tcg_resl
, tcg_resh
;
7387 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7388 unallocated_encoding(s
);
7392 if (!fp_access_check(s
)) {
7396 tcg_resh
= tcg_temp_new_i64();
7397 tcg_resl
= tcg_temp_new_i64();
7399 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7400 * either extracting 128 bits from a 128:128 concatenation, or
7401 * extracting 64 bits from a 64:64 concatenation.
7404 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7406 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7407 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7415 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7416 EltPosns
*elt
= eltposns
;
7423 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7425 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7428 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7429 tcg_hh
= tcg_temp_new_i64();
7430 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7431 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7432 tcg_temp_free_i64(tcg_hh
);
7436 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7437 tcg_temp_free_i64(tcg_resl
);
7439 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7441 tcg_temp_free_i64(tcg_resh
);
7442 clear_vec_high(s
, is_q
, rd
);
7446 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7447 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7448 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7449 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7451 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7453 int op2
= extract32(insn
, 22, 2);
7454 int is_q
= extract32(insn
, 30, 1);
7455 int rm
= extract32(insn
, 16, 5);
7456 int rn
= extract32(insn
, 5, 5);
7457 int rd
= extract32(insn
, 0, 5);
7458 int is_tblx
= extract32(insn
, 12, 1);
7459 int len
= extract32(insn
, 13, 2);
7460 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7461 TCGv_i32 tcg_regno
, tcg_numregs
;
7464 unallocated_encoding(s
);
7468 if (!fp_access_check(s
)) {
7472 /* This does a table lookup: for every byte element in the input
7473 * we index into a table formed from up to four vector registers,
7474 * and then the output is the result of the lookups. Our helper
7475 * function does the lookup operation for a single 64 bit part of
7478 tcg_resl
= tcg_temp_new_i64();
7482 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7484 tcg_gen_movi_i64(tcg_resl
, 0);
7488 tcg_resh
= tcg_temp_new_i64();
7490 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7492 tcg_gen_movi_i64(tcg_resh
, 0);
7496 tcg_idx
= tcg_temp_new_i64();
7497 tcg_regno
= tcg_const_i32(rn
);
7498 tcg_numregs
= tcg_const_i32(len
+ 1);
7499 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7500 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7501 tcg_regno
, tcg_numregs
);
7503 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7504 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7505 tcg_regno
, tcg_numregs
);
7507 tcg_temp_free_i64(tcg_idx
);
7508 tcg_temp_free_i32(tcg_regno
);
7509 tcg_temp_free_i32(tcg_numregs
);
7511 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7512 tcg_temp_free_i64(tcg_resl
);
7515 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7516 tcg_temp_free_i64(tcg_resh
);
7518 clear_vec_high(s
, is_q
, rd
);
7522 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7523 * +---+---+-------------+------+---+------+---+------------------+------+
7524 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7525 * +---+---+-------------+------+---+------+---+------------------+------+
7527 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7529 int rd
= extract32(insn
, 0, 5);
7530 int rn
= extract32(insn
, 5, 5);
7531 int rm
= extract32(insn
, 16, 5);
7532 int size
= extract32(insn
, 22, 2);
7533 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7534 * bit 2 indicates 1 vs 2 variant of the insn.
7536 int opcode
= extract32(insn
, 12, 2);
7537 bool part
= extract32(insn
, 14, 1);
7538 bool is_q
= extract32(insn
, 30, 1);
7539 int esize
= 8 << size
;
7541 int datasize
= is_q
? 128 : 64;
7542 int elements
= datasize
/ esize
;
7543 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7545 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7546 unallocated_encoding(s
);
7550 if (!fp_access_check(s
)) {
7554 tcg_resl
= tcg_const_i64(0);
7555 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7556 tcg_res
= tcg_temp_new_i64();
7558 for (i
= 0; i
< elements
; i
++) {
7560 case 1: /* UZP1/2 */
7562 int midpoint
= elements
/ 2;
7564 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7566 read_vec_element(s
, tcg_res
, rm
,
7567 2 * (i
- midpoint
) + part
, size
);
7571 case 2: /* TRN1/2 */
7573 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7575 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7578 case 3: /* ZIP1/2 */
7580 int base
= part
* elements
/ 2;
7582 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7584 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7589 g_assert_not_reached();
7594 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7595 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7597 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7598 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7602 tcg_temp_free_i64(tcg_res
);
7604 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7605 tcg_temp_free_i64(tcg_resl
);
7608 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7609 tcg_temp_free_i64(tcg_resh
);
7611 clear_vec_high(s
, is_q
, rd
);
7615 * do_reduction_op helper
7617 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7618 * important for correct NaN propagation that we do these
7619 * operations in exactly the order specified by the pseudocode.
7621 * This is a recursive function, TCG temps should be freed by the
7622 * calling function once it is done with the values.
7624 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7625 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7627 if (esize
== size
) {
7629 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7632 /* We should have one register left here */
7633 assert(ctpop8(vmap
) == 1);
7634 element
= ctz32(vmap
);
7635 assert(element
< 8);
7637 tcg_elem
= tcg_temp_new_i32();
7638 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7641 int bits
= size
/ 2;
7642 int shift
= ctpop8(vmap
) / 2;
7643 int vmap_lo
= (vmap
>> shift
) & vmap
;
7644 int vmap_hi
= (vmap
& ~vmap_lo
);
7645 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7647 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7648 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7649 tcg_res
= tcg_temp_new_i32();
7652 case 0x0c: /* fmaxnmv half-precision */
7653 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7655 case 0x0f: /* fmaxv half-precision */
7656 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7658 case 0x1c: /* fminnmv half-precision */
7659 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7661 case 0x1f: /* fminv half-precision */
7662 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7664 case 0x2c: /* fmaxnmv */
7665 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7667 case 0x2f: /* fmaxv */
7668 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7670 case 0x3c: /* fminnmv */
7671 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7673 case 0x3f: /* fminv */
7674 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7677 g_assert_not_reached();
7680 tcg_temp_free_i32(tcg_hi
);
7681 tcg_temp_free_i32(tcg_lo
);
7686 /* AdvSIMD across lanes
7687 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7688 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7689 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7690 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7692 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7694 int rd
= extract32(insn
, 0, 5);
7695 int rn
= extract32(insn
, 5, 5);
7696 int size
= extract32(insn
, 22, 2);
7697 int opcode
= extract32(insn
, 12, 5);
7698 bool is_q
= extract32(insn
, 30, 1);
7699 bool is_u
= extract32(insn
, 29, 1);
7701 bool is_min
= false;
7705 TCGv_i64 tcg_res
, tcg_elt
;
7708 case 0x1b: /* ADDV */
7710 unallocated_encoding(s
);
7714 case 0x3: /* SADDLV, UADDLV */
7715 case 0xa: /* SMAXV, UMAXV */
7716 case 0x1a: /* SMINV, UMINV */
7717 if (size
== 3 || (size
== 2 && !is_q
)) {
7718 unallocated_encoding(s
);
7722 case 0xc: /* FMAXNMV, FMINNMV */
7723 case 0xf: /* FMAXV, FMINV */
7724 /* Bit 1 of size field encodes min vs max and the actual size
7725 * depends on the encoding of the U bit. If not set (and FP16
7726 * enabled) then we do half-precision float instead of single
7729 is_min
= extract32(size
, 1, 1);
7731 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7733 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7734 unallocated_encoding(s
);
7741 unallocated_encoding(s
);
7745 if (!fp_access_check(s
)) {
7750 elements
= (is_q
? 128 : 64) / esize
;
7752 tcg_res
= tcg_temp_new_i64();
7753 tcg_elt
= tcg_temp_new_i64();
7755 /* These instructions operate across all lanes of a vector
7756 * to produce a single result. We can guarantee that a 64
7757 * bit intermediate is sufficient:
7758 * + for [US]ADDLV the maximum element size is 32 bits, and
7759 * the result type is 64 bits
7760 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7761 * same as the element size, which is 32 bits at most
7762 * For the integer operations we can choose to work at 64
7763 * or 32 bits and truncate at the end; for simplicity
7764 * we use 64 bits always. The floating point
7765 * ops do require 32 bit intermediates, though.
7768 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7770 for (i
= 1; i
< elements
; i
++) {
7771 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7774 case 0x03: /* SADDLV / UADDLV */
7775 case 0x1b: /* ADDV */
7776 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7778 case 0x0a: /* SMAXV / UMAXV */
7780 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7782 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7785 case 0x1a: /* SMINV / UMINV */
7787 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7789 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7793 g_assert_not_reached();
7798 /* Floating point vector reduction ops which work across 32
7799 * bit (single) or 16 bit (half-precision) intermediates.
7800 * Note that correct NaN propagation requires that we do these
7801 * operations in exactly the order specified by the pseudocode.
7803 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7804 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7805 int vmap
= (1 << elements
) - 1;
7806 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7807 (is_q
? 128 : 64), vmap
, fpst
);
7808 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7809 tcg_temp_free_i32(tcg_res32
);
7810 tcg_temp_free_ptr(fpst
);
7813 tcg_temp_free_i64(tcg_elt
);
7815 /* Now truncate the result to the width required for the final output */
7816 if (opcode
== 0x03) {
7817 /* SADDLV, UADDLV: result is 2*esize */
7823 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7826 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7829 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7834 g_assert_not_reached();
7837 write_fp_dreg(s
, rd
, tcg_res
);
7838 tcg_temp_free_i64(tcg_res
);
7841 /* DUP (Element, Vector)
7843 * 31 30 29 21 20 16 15 10 9 5 4 0
7844 * +---+---+-------------------+--------+-------------+------+------+
7845 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7846 * +---+---+-------------------+--------+-------------+------+------+
7848 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7850 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7853 int size
= ctz32(imm5
);
7856 if (size
> 3 || (size
== 3 && !is_q
)) {
7857 unallocated_encoding(s
);
7861 if (!fp_access_check(s
)) {
7865 index
= imm5
>> (size
+ 1);
7866 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7867 vec_reg_offset(s
, rn
, index
, size
),
7868 is_q
? 16 : 8, vec_full_reg_size(s
));
7871 /* DUP (element, scalar)
7872 * 31 21 20 16 15 10 9 5 4 0
7873 * +-----------------------+--------+-------------+------+------+
7874 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7875 * +-----------------------+--------+-------------+------+------+
7877 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7880 int size
= ctz32(imm5
);
7885 unallocated_encoding(s
);
7889 if (!fp_access_check(s
)) {
7893 index
= imm5
>> (size
+ 1);
7895 /* This instruction just extracts the specified element and
7896 * zero-extends it into the bottom of the destination register.
7898 tmp
= tcg_temp_new_i64();
7899 read_vec_element(s
, tmp
, rn
, index
, size
);
7900 write_fp_dreg(s
, rd
, tmp
);
7901 tcg_temp_free_i64(tmp
);
7906 * 31 30 29 21 20 16 15 10 9 5 4 0
7907 * +---+---+-------------------+--------+-------------+------+------+
7908 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7909 * +---+---+-------------------+--------+-------------+------+------+
7911 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7913 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7916 int size
= ctz32(imm5
);
7917 uint32_t dofs
, oprsz
, maxsz
;
7919 if (size
> 3 || ((size
== 3) && !is_q
)) {
7920 unallocated_encoding(s
);
7924 if (!fp_access_check(s
)) {
7928 dofs
= vec_full_reg_offset(s
, rd
);
7929 oprsz
= is_q
? 16 : 8;
7930 maxsz
= vec_full_reg_size(s
);
7932 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7937 * 31 21 20 16 15 14 11 10 9 5 4 0
7938 * +-----------------------+--------+------------+---+------+------+
7939 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7940 * +-----------------------+--------+------------+---+------+------+
7942 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7943 * index: encoded in imm5<4:size+1>
7945 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7948 int size
= ctz32(imm5
);
7949 int src_index
, dst_index
;
7953 unallocated_encoding(s
);
7957 if (!fp_access_check(s
)) {
7961 dst_index
= extract32(imm5
, 1+size
, 5);
7962 src_index
= extract32(imm4
, size
, 4);
7964 tmp
= tcg_temp_new_i64();
7966 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7967 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7969 tcg_temp_free_i64(tmp
);
7971 /* INS is considered a 128-bit write for SVE. */
7972 clear_vec_high(s
, true, rd
);
7978 * 31 21 20 16 15 10 9 5 4 0
7979 * +-----------------------+--------+-------------+------+------+
7980 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7981 * +-----------------------+--------+-------------+------+------+
7983 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7984 * index: encoded in imm5<4:size+1>
7986 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7988 int size
= ctz32(imm5
);
7992 unallocated_encoding(s
);
7996 if (!fp_access_check(s
)) {
8000 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8001 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8003 /* INS is considered a 128-bit write for SVE. */
8004 clear_vec_high(s
, true, rd
);
8011 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8012 * +---+---+-------------------+--------+-------------+------+------+
8013 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8014 * +---+---+-------------------+--------+-------------+------+------+
8016 * U: unsigned when set
8017 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8019 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8020 int rn
, int rd
, int imm5
)
8022 int size
= ctz32(imm5
);
8026 /* Check for UnallocatedEncodings */
8028 if (size
> 2 || (size
== 2 && !is_q
)) {
8029 unallocated_encoding(s
);
8034 || (size
< 3 && is_q
)
8035 || (size
== 3 && !is_q
)) {
8036 unallocated_encoding(s
);
8041 if (!fp_access_check(s
)) {
8045 element
= extract32(imm5
, 1+size
, 4);
8047 tcg_rd
= cpu_reg(s
, rd
);
8048 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8049 if (is_signed
&& !is_q
) {
8050 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8055 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8056 * +---+---+----+-----------------+------+---+------+---+------+------+
8057 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8058 * +---+---+----+-----------------+------+---+------+---+------+------+
8060 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8062 int rd
= extract32(insn
, 0, 5);
8063 int rn
= extract32(insn
, 5, 5);
8064 int imm4
= extract32(insn
, 11, 4);
8065 int op
= extract32(insn
, 29, 1);
8066 int is_q
= extract32(insn
, 30, 1);
8067 int imm5
= extract32(insn
, 16, 5);
8072 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8074 unallocated_encoding(s
);
8079 /* DUP (element - vector) */
8080 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8084 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8089 handle_simd_insg(s
, rd
, rn
, imm5
);
8091 unallocated_encoding(s
);
8096 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8097 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8100 unallocated_encoding(s
);
8106 /* AdvSIMD modified immediate
8107 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8108 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8109 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8110 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8112 * There are a number of operations that can be carried out here:
8113 * MOVI - move (shifted) imm into register
8114 * MVNI - move inverted (shifted) imm into register
8115 * ORR - bitwise OR of (shifted) imm with register
8116 * BIC - bitwise clear of (shifted) imm with register
8117 * With ARMv8.2 we also have:
8118 * FMOV half-precision
8120 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8122 int rd
= extract32(insn
, 0, 5);
8123 int cmode
= extract32(insn
, 12, 4);
8124 int cmode_3_1
= extract32(cmode
, 1, 3);
8125 int cmode_0
= extract32(cmode
, 0, 1);
8126 int o2
= extract32(insn
, 11, 1);
8127 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8128 bool is_neg
= extract32(insn
, 29, 1);
8129 bool is_q
= extract32(insn
, 30, 1);
8132 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8133 /* Check for FMOV (vector, immediate) - half-precision */
8134 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8135 unallocated_encoding(s
);
8140 if (!fp_access_check(s
)) {
8144 /* See AdvSIMDExpandImm() in ARM ARM */
8145 switch (cmode_3_1
) {
8146 case 0: /* Replicate(Zeros(24):imm8, 2) */
8147 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
8148 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
8149 case 3: /* Replicate(imm8:Zeros(24), 2) */
8151 int shift
= cmode_3_1
* 8;
8152 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
8155 case 4: /* Replicate(Zeros(8):imm8, 4) */
8156 case 5: /* Replicate(imm8:Zeros(8), 4) */
8158 int shift
= (cmode_3_1
& 0x1) * 8;
8159 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
8164 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
8165 imm
= (abcdefgh
<< 16) | 0xffff;
8167 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
8168 imm
= (abcdefgh
<< 8) | 0xff;
8170 imm
= bitfield_replicate(imm
, 32);
8173 if (!cmode_0
&& !is_neg
) {
8174 imm
= bitfield_replicate(abcdefgh
, 8);
8175 } else if (!cmode_0
&& is_neg
) {
8178 for (i
= 0; i
< 8; i
++) {
8179 if ((abcdefgh
) & (1 << i
)) {
8180 imm
|= 0xffULL
<< (i
* 8);
8183 } else if (cmode_0
) {
8185 imm
= (abcdefgh
& 0x3f) << 48;
8186 if (abcdefgh
& 0x80) {
8187 imm
|= 0x8000000000000000ULL
;
8189 if (abcdefgh
& 0x40) {
8190 imm
|= 0x3fc0000000000000ULL
;
8192 imm
|= 0x4000000000000000ULL
;
8196 /* FMOV (vector, immediate) - half-precision */
8197 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8198 /* now duplicate across the lanes */
8199 imm
= bitfield_replicate(imm
, 16);
8201 imm
= (abcdefgh
& 0x3f) << 19;
8202 if (abcdefgh
& 0x80) {
8205 if (abcdefgh
& 0x40) {
8216 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
8217 g_assert_not_reached();
8220 if (cmode_3_1
!= 7 && is_neg
) {
8224 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8225 /* MOVI or MVNI, with MVNI negation handled above. */
8226 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8227 vec_full_reg_size(s
), imm
);
8229 /* ORR or BIC, with BIC negation to AND handled above. */
8231 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8233 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8238 /* AdvSIMD scalar copy
8239 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8240 * +-----+----+-----------------+------+---+------+---+------+------+
8241 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8242 * +-----+----+-----------------+------+---+------+---+------+------+
8244 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8246 int rd
= extract32(insn
, 0, 5);
8247 int rn
= extract32(insn
, 5, 5);
8248 int imm4
= extract32(insn
, 11, 4);
8249 int imm5
= extract32(insn
, 16, 5);
8250 int op
= extract32(insn
, 29, 1);
8252 if (op
!= 0 || imm4
!= 0) {
8253 unallocated_encoding(s
);
8257 /* DUP (element, scalar) */
8258 handle_simd_dupes(s
, rd
, rn
, imm5
);
8261 /* AdvSIMD scalar pairwise
8262 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8263 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8264 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8265 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8267 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8269 int u
= extract32(insn
, 29, 1);
8270 int size
= extract32(insn
, 22, 2);
8271 int opcode
= extract32(insn
, 12, 5);
8272 int rn
= extract32(insn
, 5, 5);
8273 int rd
= extract32(insn
, 0, 5);
8276 /* For some ops (the FP ones), size[1] is part of the encoding.
8277 * For ADDP strictly it is not but size[1] is always 1 for valid
8280 opcode
|= (extract32(size
, 1, 1) << 5);
8283 case 0x3b: /* ADDP */
8284 if (u
|| size
!= 3) {
8285 unallocated_encoding(s
);
8288 if (!fp_access_check(s
)) {
8294 case 0xc: /* FMAXNMP */
8295 case 0xd: /* FADDP */
8296 case 0xf: /* FMAXP */
8297 case 0x2c: /* FMINNMP */
8298 case 0x2f: /* FMINP */
8299 /* FP op, size[0] is 32 or 64 bit*/
8301 if (!dc_isar_feature(aa64_fp16
, s
)) {
8302 unallocated_encoding(s
);
8308 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8311 if (!fp_access_check(s
)) {
8315 fpst
= get_fpstatus_ptr(size
== MO_16
);
8318 unallocated_encoding(s
);
8322 if (size
== MO_64
) {
8323 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8324 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8325 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8327 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8328 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8331 case 0x3b: /* ADDP */
8332 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8334 case 0xc: /* FMAXNMP */
8335 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8337 case 0xd: /* FADDP */
8338 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8340 case 0xf: /* FMAXP */
8341 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8343 case 0x2c: /* FMINNMP */
8344 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8346 case 0x2f: /* FMINP */
8347 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8350 g_assert_not_reached();
8353 write_fp_dreg(s
, rd
, tcg_res
);
8355 tcg_temp_free_i64(tcg_op1
);
8356 tcg_temp_free_i64(tcg_op2
);
8357 tcg_temp_free_i64(tcg_res
);
8359 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8360 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8361 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8363 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8364 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8366 if (size
== MO_16
) {
8368 case 0xc: /* FMAXNMP */
8369 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8371 case 0xd: /* FADDP */
8372 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8374 case 0xf: /* FMAXP */
8375 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8377 case 0x2c: /* FMINNMP */
8378 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8380 case 0x2f: /* FMINP */
8381 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8384 g_assert_not_reached();
8388 case 0xc: /* FMAXNMP */
8389 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8391 case 0xd: /* FADDP */
8392 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8394 case 0xf: /* FMAXP */
8395 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8397 case 0x2c: /* FMINNMP */
8398 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8400 case 0x2f: /* FMINP */
8401 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8404 g_assert_not_reached();
8408 write_fp_sreg(s
, rd
, tcg_res
);
8410 tcg_temp_free_i32(tcg_op1
);
8411 tcg_temp_free_i32(tcg_op2
);
8412 tcg_temp_free_i32(tcg_res
);
8416 tcg_temp_free_ptr(fpst
);
8421 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8423 * This code is handles the common shifting code and is used by both
8424 * the vector and scalar code.
8426 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8427 TCGv_i64 tcg_rnd
, bool accumulate
,
8428 bool is_u
, int size
, int shift
)
8430 bool extended_result
= false;
8431 bool round
= tcg_rnd
!= NULL
;
8433 TCGv_i64 tcg_src_hi
;
8435 if (round
&& size
== 3) {
8436 extended_result
= true;
8437 ext_lshift
= 64 - shift
;
8438 tcg_src_hi
= tcg_temp_new_i64();
8439 } else if (shift
== 64) {
8440 if (!accumulate
&& is_u
) {
8441 /* result is zero */
8442 tcg_gen_movi_i64(tcg_res
, 0);
8447 /* Deal with the rounding step */
8449 if (extended_result
) {
8450 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8452 /* take care of sign extending tcg_res */
8453 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8454 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8455 tcg_src
, tcg_src_hi
,
8458 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8462 tcg_temp_free_i64(tcg_zero
);
8464 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8468 /* Now do the shift right */
8469 if (round
&& extended_result
) {
8470 /* extended case, >64 bit precision required */
8471 if (ext_lshift
== 0) {
8472 /* special case, only high bits matter */
8473 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8475 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8476 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8477 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8482 /* essentially shifting in 64 zeros */
8483 tcg_gen_movi_i64(tcg_src
, 0);
8485 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8489 /* effectively extending the sign-bit */
8490 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8492 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8498 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8500 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8503 if (extended_result
) {
8504 tcg_temp_free_i64(tcg_src_hi
);
8508 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8509 static void handle_scalar_simd_shri(DisasContext
*s
,
8510 bool is_u
, int immh
, int immb
,
8511 int opcode
, int rn
, int rd
)
8514 int immhb
= immh
<< 3 | immb
;
8515 int shift
= 2 * (8 << size
) - immhb
;
8516 bool accumulate
= false;
8518 bool insert
= false;
8523 if (!extract32(immh
, 3, 1)) {
8524 unallocated_encoding(s
);
8528 if (!fp_access_check(s
)) {
8533 case 0x02: /* SSRA / USRA (accumulate) */
8536 case 0x04: /* SRSHR / URSHR (rounding) */
8539 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8540 accumulate
= round
= true;
8542 case 0x08: /* SRI */
8548 uint64_t round_const
= 1ULL << (shift
- 1);
8549 tcg_round
= tcg_const_i64(round_const
);
8554 tcg_rn
= read_fp_dreg(s
, rn
);
8555 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8558 /* shift count same as element size is valid but does nothing;
8559 * special case to avoid potential shift by 64.
8561 int esize
= 8 << size
;
8562 if (shift
!= esize
) {
8563 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8564 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8567 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8568 accumulate
, is_u
, size
, shift
);
8571 write_fp_dreg(s
, rd
, tcg_rd
);
8573 tcg_temp_free_i64(tcg_rn
);
8574 tcg_temp_free_i64(tcg_rd
);
8576 tcg_temp_free_i64(tcg_round
);
8580 /* SHL/SLI - Scalar shift left */
8581 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8582 int immh
, int immb
, int opcode
,
8585 int size
= 32 - clz32(immh
) - 1;
8586 int immhb
= immh
<< 3 | immb
;
8587 int shift
= immhb
- (8 << size
);
8588 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8589 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8591 if (!extract32(immh
, 3, 1)) {
8592 unallocated_encoding(s
);
8596 if (!fp_access_check(s
)) {
8600 tcg_rn
= read_fp_dreg(s
, rn
);
8601 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8604 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8606 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8609 write_fp_dreg(s
, rd
, tcg_rd
);
8611 tcg_temp_free_i64(tcg_rn
);
8612 tcg_temp_free_i64(tcg_rd
);
8615 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8616 * (signed/unsigned) narrowing */
8617 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8618 bool is_u_shift
, bool is_u_narrow
,
8619 int immh
, int immb
, int opcode
,
8622 int immhb
= immh
<< 3 | immb
;
8623 int size
= 32 - clz32(immh
) - 1;
8624 int esize
= 8 << size
;
8625 int shift
= (2 * esize
) - immhb
;
8626 int elements
= is_scalar
? 1 : (64 / esize
);
8627 bool round
= extract32(opcode
, 0, 1);
8628 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8629 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8630 TCGv_i32 tcg_rd_narrowed
;
8633 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8634 { gen_helper_neon_narrow_sat_s8
,
8635 gen_helper_neon_unarrow_sat8
},
8636 { gen_helper_neon_narrow_sat_s16
,
8637 gen_helper_neon_unarrow_sat16
},
8638 { gen_helper_neon_narrow_sat_s32
,
8639 gen_helper_neon_unarrow_sat32
},
8642 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8643 gen_helper_neon_narrow_sat_u8
,
8644 gen_helper_neon_narrow_sat_u16
,
8645 gen_helper_neon_narrow_sat_u32
,
8648 NeonGenNarrowEnvFn
*narrowfn
;
8654 if (extract32(immh
, 3, 1)) {
8655 unallocated_encoding(s
);
8659 if (!fp_access_check(s
)) {
8664 narrowfn
= unsigned_narrow_fns
[size
];
8666 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8669 tcg_rn
= tcg_temp_new_i64();
8670 tcg_rd
= tcg_temp_new_i64();
8671 tcg_rd_narrowed
= tcg_temp_new_i32();
8672 tcg_final
= tcg_const_i64(0);
8675 uint64_t round_const
= 1ULL << (shift
- 1);
8676 tcg_round
= tcg_const_i64(round_const
);
8681 for (i
= 0; i
< elements
; i
++) {
8682 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8683 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8684 false, is_u_shift
, size
+1, shift
);
8685 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8686 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8687 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8691 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8693 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8697 tcg_temp_free_i64(tcg_round
);
8699 tcg_temp_free_i64(tcg_rn
);
8700 tcg_temp_free_i64(tcg_rd
);
8701 tcg_temp_free_i32(tcg_rd_narrowed
);
8702 tcg_temp_free_i64(tcg_final
);
8704 clear_vec_high(s
, is_q
, rd
);
8707 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8708 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8709 bool src_unsigned
, bool dst_unsigned
,
8710 int immh
, int immb
, int rn
, int rd
)
8712 int immhb
= immh
<< 3 | immb
;
8713 int size
= 32 - clz32(immh
) - 1;
8714 int shift
= immhb
- (8 << size
);
8718 assert(!(scalar
&& is_q
));
8721 if (!is_q
&& extract32(immh
, 3, 1)) {
8722 unallocated_encoding(s
);
8726 /* Since we use the variable-shift helpers we must
8727 * replicate the shift count into each element of
8728 * the tcg_shift value.
8732 shift
|= shift
<< 8;
8735 shift
|= shift
<< 16;
8741 g_assert_not_reached();
8745 if (!fp_access_check(s
)) {
8750 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8751 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8752 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8753 { NULL
, gen_helper_neon_qshl_u64
},
8755 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8756 int maxpass
= is_q
? 2 : 1;
8758 for (pass
= 0; pass
< maxpass
; pass
++) {
8759 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8761 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8762 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8763 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8765 tcg_temp_free_i64(tcg_op
);
8767 tcg_temp_free_i64(tcg_shift
);
8768 clear_vec_high(s
, is_q
, rd
);
8770 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8771 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8773 { gen_helper_neon_qshl_s8
,
8774 gen_helper_neon_qshl_s16
,
8775 gen_helper_neon_qshl_s32
},
8776 { gen_helper_neon_qshlu_s8
,
8777 gen_helper_neon_qshlu_s16
,
8778 gen_helper_neon_qshlu_s32
}
8780 { NULL
, NULL
, NULL
},
8781 { gen_helper_neon_qshl_u8
,
8782 gen_helper_neon_qshl_u16
,
8783 gen_helper_neon_qshl_u32
}
8786 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8787 MemOp memop
= scalar
? size
: MO_32
;
8788 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8790 for (pass
= 0; pass
< maxpass
; pass
++) {
8791 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8793 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8794 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8798 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8801 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8806 g_assert_not_reached();
8808 write_fp_sreg(s
, rd
, tcg_op
);
8810 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8813 tcg_temp_free_i32(tcg_op
);
8815 tcg_temp_free_i32(tcg_shift
);
8818 clear_vec_high(s
, is_q
, rd
);
8823 /* Common vector code for handling integer to FP conversion */
8824 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8825 int elements
, int is_signed
,
8826 int fracbits
, int size
)
8828 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8829 TCGv_i32 tcg_shift
= NULL
;
8831 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8834 if (fracbits
|| size
== MO_64
) {
8835 tcg_shift
= tcg_const_i32(fracbits
);
8838 if (size
== MO_64
) {
8839 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8840 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8842 for (pass
= 0; pass
< elements
; pass
++) {
8843 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8846 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8847 tcg_shift
, tcg_fpst
);
8849 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8850 tcg_shift
, tcg_fpst
);
8852 if (elements
== 1) {
8853 write_fp_dreg(s
, rd
, tcg_double
);
8855 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8859 tcg_temp_free_i64(tcg_int64
);
8860 tcg_temp_free_i64(tcg_double
);
8863 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8864 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8866 for (pass
= 0; pass
< elements
; pass
++) {
8867 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8873 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8874 tcg_shift
, tcg_fpst
);
8876 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8877 tcg_shift
, tcg_fpst
);
8881 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8883 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8890 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8891 tcg_shift
, tcg_fpst
);
8893 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8894 tcg_shift
, tcg_fpst
);
8898 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8900 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8905 g_assert_not_reached();
8908 if (elements
== 1) {
8909 write_fp_sreg(s
, rd
, tcg_float
);
8911 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8915 tcg_temp_free_i32(tcg_int32
);
8916 tcg_temp_free_i32(tcg_float
);
8919 tcg_temp_free_ptr(tcg_fpst
);
8921 tcg_temp_free_i32(tcg_shift
);
8924 clear_vec_high(s
, elements
<< size
== 16, rd
);
8927 /* UCVTF/SCVTF - Integer to FP conversion */
8928 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8929 bool is_q
, bool is_u
,
8930 int immh
, int immb
, int opcode
,
8933 int size
, elements
, fracbits
;
8934 int immhb
= immh
<< 3 | immb
;
8938 if (!is_scalar
&& !is_q
) {
8939 unallocated_encoding(s
);
8942 } else if (immh
& 4) {
8944 } else if (immh
& 2) {
8946 if (!dc_isar_feature(aa64_fp16
, s
)) {
8947 unallocated_encoding(s
);
8951 /* immh == 0 would be a failure of the decode logic */
8952 g_assert(immh
== 1);
8953 unallocated_encoding(s
);
8960 elements
= (8 << is_q
) >> size
;
8962 fracbits
= (16 << size
) - immhb
;
8964 if (!fp_access_check(s
)) {
8968 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8971 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8972 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8973 bool is_q
, bool is_u
,
8974 int immh
, int immb
, int rn
, int rd
)
8976 int immhb
= immh
<< 3 | immb
;
8977 int pass
, size
, fracbits
;
8978 TCGv_ptr tcg_fpstatus
;
8979 TCGv_i32 tcg_rmode
, tcg_shift
;
8983 if (!is_scalar
&& !is_q
) {
8984 unallocated_encoding(s
);
8987 } else if (immh
& 0x4) {
8989 } else if (immh
& 0x2) {
8991 if (!dc_isar_feature(aa64_fp16
, s
)) {
8992 unallocated_encoding(s
);
8996 /* Should have split out AdvSIMD modified immediate earlier. */
8998 unallocated_encoding(s
);
9002 if (!fp_access_check(s
)) {
9006 assert(!(is_scalar
&& is_q
));
9008 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
9009 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
9010 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9011 fracbits
= (16 << size
) - immhb
;
9012 tcg_shift
= tcg_const_i32(fracbits
);
9014 if (size
== MO_64
) {
9015 int maxpass
= is_scalar
? 1 : 2;
9017 for (pass
= 0; pass
< maxpass
; pass
++) {
9018 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9020 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9022 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9024 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9026 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9027 tcg_temp_free_i64(tcg_op
);
9029 clear_vec_high(s
, is_q
, rd
);
9031 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9032 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9037 fn
= gen_helper_vfp_touhh
;
9039 fn
= gen_helper_vfp_toshh
;
9044 fn
= gen_helper_vfp_touls
;
9046 fn
= gen_helper_vfp_tosls
;
9050 g_assert_not_reached();
9053 for (pass
= 0; pass
< maxpass
; pass
++) {
9054 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9056 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9057 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9059 write_fp_sreg(s
, rd
, tcg_op
);
9061 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9063 tcg_temp_free_i32(tcg_op
);
9066 clear_vec_high(s
, is_q
, rd
);
9070 tcg_temp_free_ptr(tcg_fpstatus
);
9071 tcg_temp_free_i32(tcg_shift
);
9072 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9073 tcg_temp_free_i32(tcg_rmode
);
9076 /* AdvSIMD scalar shift by immediate
9077 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9078 * +-----+---+-------------+------+------+--------+---+------+------+
9079 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9080 * +-----+---+-------------+------+------+--------+---+------+------+
9082 * This is the scalar version so it works on a fixed sized registers
9084 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9086 int rd
= extract32(insn
, 0, 5);
9087 int rn
= extract32(insn
, 5, 5);
9088 int opcode
= extract32(insn
, 11, 5);
9089 int immb
= extract32(insn
, 16, 3);
9090 int immh
= extract32(insn
, 19, 4);
9091 bool is_u
= extract32(insn
, 29, 1);
9094 unallocated_encoding(s
);
9099 case 0x08: /* SRI */
9101 unallocated_encoding(s
);
9105 case 0x00: /* SSHR / USHR */
9106 case 0x02: /* SSRA / USRA */
9107 case 0x04: /* SRSHR / URSHR */
9108 case 0x06: /* SRSRA / URSRA */
9109 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9111 case 0x0a: /* SHL / SLI */
9112 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9114 case 0x1c: /* SCVTF, UCVTF */
9115 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9118 case 0x10: /* SQSHRUN, SQSHRUN2 */
9119 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9121 unallocated_encoding(s
);
9124 handle_vec_simd_sqshrn(s
, true, false, false, true,
9125 immh
, immb
, opcode
, rn
, rd
);
9127 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9128 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9129 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9130 immh
, immb
, opcode
, rn
, rd
);
9132 case 0xc: /* SQSHLU */
9134 unallocated_encoding(s
);
9137 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9139 case 0xe: /* SQSHL, UQSHL */
9140 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9142 case 0x1f: /* FCVTZS, FCVTZU */
9143 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9146 unallocated_encoding(s
);
9151 /* AdvSIMD scalar three different
9152 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9153 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9154 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9155 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9157 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9159 bool is_u
= extract32(insn
, 29, 1);
9160 int size
= extract32(insn
, 22, 2);
9161 int opcode
= extract32(insn
, 12, 4);
9162 int rm
= extract32(insn
, 16, 5);
9163 int rn
= extract32(insn
, 5, 5);
9164 int rd
= extract32(insn
, 0, 5);
9167 unallocated_encoding(s
);
9172 case 0x9: /* SQDMLAL, SQDMLAL2 */
9173 case 0xb: /* SQDMLSL, SQDMLSL2 */
9174 case 0xd: /* SQDMULL, SQDMULL2 */
9175 if (size
== 0 || size
== 3) {
9176 unallocated_encoding(s
);
9181 unallocated_encoding(s
);
9185 if (!fp_access_check(s
)) {
9190 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9191 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9192 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9194 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9195 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9197 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9198 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9201 case 0xd: /* SQDMULL, SQDMULL2 */
9203 case 0xb: /* SQDMLSL, SQDMLSL2 */
9204 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9206 case 0x9: /* SQDMLAL, SQDMLAL2 */
9207 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9208 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9212 g_assert_not_reached();
9215 write_fp_dreg(s
, rd
, tcg_res
);
9217 tcg_temp_free_i64(tcg_op1
);
9218 tcg_temp_free_i64(tcg_op2
);
9219 tcg_temp_free_i64(tcg_res
);
9221 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9222 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9223 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9225 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9226 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9229 case 0xd: /* SQDMULL, SQDMULL2 */
9231 case 0xb: /* SQDMLSL, SQDMLSL2 */
9232 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9234 case 0x9: /* SQDMLAL, SQDMLAL2 */
9236 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9237 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9238 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9240 tcg_temp_free_i64(tcg_op3
);
9244 g_assert_not_reached();
9247 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9248 write_fp_dreg(s
, rd
, tcg_res
);
9250 tcg_temp_free_i32(tcg_op1
);
9251 tcg_temp_free_i32(tcg_op2
);
9252 tcg_temp_free_i64(tcg_res
);
9256 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9257 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9259 /* Handle 64x64->64 opcodes which are shared between the scalar
9260 * and vector 3-same groups. We cover every opcode where size == 3
9261 * is valid in either the three-reg-same (integer, not pairwise)
9262 * or scalar-three-reg-same groups.
9267 case 0x1: /* SQADD */
9269 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9271 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9274 case 0x5: /* SQSUB */
9276 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9278 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9281 case 0x6: /* CMGT, CMHI */
9282 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9283 * We implement this using setcond (test) and then negating.
9285 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9287 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9288 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9290 case 0x7: /* CMGE, CMHS */
9291 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9293 case 0x11: /* CMTST, CMEQ */
9298 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9300 case 0x8: /* SSHL, USHL */
9302 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9304 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9307 case 0x9: /* SQSHL, UQSHL */
9309 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9311 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9314 case 0xa: /* SRSHL, URSHL */
9316 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9318 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9321 case 0xb: /* SQRSHL, UQRSHL */
9323 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9325 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9328 case 0x10: /* ADD, SUB */
9330 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9332 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9336 g_assert_not_reached();
9340 /* Handle the 3-same-operands float operations; shared by the scalar
9341 * and vector encodings. The caller must filter out any encodings
9342 * not allocated for the encoding it is dealing with.
9344 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9345 int fpopcode
, int rd
, int rn
, int rm
)
9348 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9350 for (pass
= 0; pass
< elements
; pass
++) {
9353 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9354 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9355 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9357 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9358 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9361 case 0x39: /* FMLS */
9362 /* As usual for ARM, separate negation for fused multiply-add */
9363 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9365 case 0x19: /* FMLA */
9366 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9367 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9370 case 0x18: /* FMAXNM */
9371 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9373 case 0x1a: /* FADD */
9374 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9376 case 0x1b: /* FMULX */
9377 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9379 case 0x1c: /* FCMEQ */
9380 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9382 case 0x1e: /* FMAX */
9383 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9385 case 0x1f: /* FRECPS */
9386 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9388 case 0x38: /* FMINNM */
9389 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9391 case 0x3a: /* FSUB */
9392 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9394 case 0x3e: /* FMIN */
9395 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9397 case 0x3f: /* FRSQRTS */
9398 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9400 case 0x5b: /* FMUL */
9401 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9403 case 0x5c: /* FCMGE */
9404 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9406 case 0x5d: /* FACGE */
9407 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9409 case 0x5f: /* FDIV */
9410 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9412 case 0x7a: /* FABD */
9413 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9414 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9416 case 0x7c: /* FCMGT */
9417 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9419 case 0x7d: /* FACGT */
9420 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9423 g_assert_not_reached();
9426 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9428 tcg_temp_free_i64(tcg_res
);
9429 tcg_temp_free_i64(tcg_op1
);
9430 tcg_temp_free_i64(tcg_op2
);
9433 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9434 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9435 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9437 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9438 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9441 case 0x39: /* FMLS */
9442 /* As usual for ARM, separate negation for fused multiply-add */
9443 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9445 case 0x19: /* FMLA */
9446 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9447 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9450 case 0x1a: /* FADD */
9451 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9453 case 0x1b: /* FMULX */
9454 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9456 case 0x1c: /* FCMEQ */
9457 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9459 case 0x1e: /* FMAX */
9460 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9462 case 0x1f: /* FRECPS */
9463 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9465 case 0x18: /* FMAXNM */
9466 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9468 case 0x38: /* FMINNM */
9469 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9471 case 0x3a: /* FSUB */
9472 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9474 case 0x3e: /* FMIN */
9475 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9477 case 0x3f: /* FRSQRTS */
9478 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9480 case 0x5b: /* FMUL */
9481 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9483 case 0x5c: /* FCMGE */
9484 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9486 case 0x5d: /* FACGE */
9487 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9489 case 0x5f: /* FDIV */
9490 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9492 case 0x7a: /* FABD */
9493 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9494 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9496 case 0x7c: /* FCMGT */
9497 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9499 case 0x7d: /* FACGT */
9500 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9503 g_assert_not_reached();
9506 if (elements
== 1) {
9507 /* scalar single so clear high part */
9508 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9510 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9511 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9512 tcg_temp_free_i64(tcg_tmp
);
9514 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9517 tcg_temp_free_i32(tcg_res
);
9518 tcg_temp_free_i32(tcg_op1
);
9519 tcg_temp_free_i32(tcg_op2
);
9523 tcg_temp_free_ptr(fpst
);
9525 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9528 /* AdvSIMD scalar three same
9529 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9530 * +-----+---+-----------+------+---+------+--------+---+------+------+
9531 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9532 * +-----+---+-----------+------+---+------+--------+---+------+------+
9534 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9536 int rd
= extract32(insn
, 0, 5);
9537 int rn
= extract32(insn
, 5, 5);
9538 int opcode
= extract32(insn
, 11, 5);
9539 int rm
= extract32(insn
, 16, 5);
9540 int size
= extract32(insn
, 22, 2);
9541 bool u
= extract32(insn
, 29, 1);
9544 if (opcode
>= 0x18) {
9545 /* Floating point: U, size[1] and opcode indicate operation */
9546 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9548 case 0x1b: /* FMULX */
9549 case 0x1f: /* FRECPS */
9550 case 0x3f: /* FRSQRTS */
9551 case 0x5d: /* FACGE */
9552 case 0x7d: /* FACGT */
9553 case 0x1c: /* FCMEQ */
9554 case 0x5c: /* FCMGE */
9555 case 0x7c: /* FCMGT */
9556 case 0x7a: /* FABD */
9559 unallocated_encoding(s
);
9563 if (!fp_access_check(s
)) {
9567 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9572 case 0x1: /* SQADD, UQADD */
9573 case 0x5: /* SQSUB, UQSUB */
9574 case 0x9: /* SQSHL, UQSHL */
9575 case 0xb: /* SQRSHL, UQRSHL */
9577 case 0x8: /* SSHL, USHL */
9578 case 0xa: /* SRSHL, URSHL */
9579 case 0x6: /* CMGT, CMHI */
9580 case 0x7: /* CMGE, CMHS */
9581 case 0x11: /* CMTST, CMEQ */
9582 case 0x10: /* ADD, SUB (vector) */
9584 unallocated_encoding(s
);
9588 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9589 if (size
!= 1 && size
!= 2) {
9590 unallocated_encoding(s
);
9595 unallocated_encoding(s
);
9599 if (!fp_access_check(s
)) {
9603 tcg_rd
= tcg_temp_new_i64();
9606 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9607 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9609 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9610 tcg_temp_free_i64(tcg_rn
);
9611 tcg_temp_free_i64(tcg_rm
);
9613 /* Do a single operation on the lowest element in the vector.
9614 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9615 * no side effects for all these operations.
9616 * OPTME: special-purpose helpers would avoid doing some
9617 * unnecessary work in the helper for the 8 and 16 bit cases.
9619 NeonGenTwoOpEnvFn
*genenvfn
;
9620 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9621 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9622 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9624 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9625 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9628 case 0x1: /* SQADD, UQADD */
9630 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9631 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9632 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9633 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9635 genenvfn
= fns
[size
][u
];
9638 case 0x5: /* SQSUB, UQSUB */
9640 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9641 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9642 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9643 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9645 genenvfn
= fns
[size
][u
];
9648 case 0x9: /* SQSHL, UQSHL */
9650 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9651 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9652 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9653 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9655 genenvfn
= fns
[size
][u
];
9658 case 0xb: /* SQRSHL, UQRSHL */
9660 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9661 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9662 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9663 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9665 genenvfn
= fns
[size
][u
];
9668 case 0x16: /* SQDMULH, SQRDMULH */
9670 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9671 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9672 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9674 assert(size
== 1 || size
== 2);
9675 genenvfn
= fns
[size
- 1][u
];
9679 g_assert_not_reached();
9682 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9683 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9684 tcg_temp_free_i32(tcg_rd32
);
9685 tcg_temp_free_i32(tcg_rn
);
9686 tcg_temp_free_i32(tcg_rm
);
9689 write_fp_dreg(s
, rd
, tcg_rd
);
9691 tcg_temp_free_i64(tcg_rd
);
9694 /* AdvSIMD scalar three same FP16
9695 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9696 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9697 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9698 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9699 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9700 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9702 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9705 int rd
= extract32(insn
, 0, 5);
9706 int rn
= extract32(insn
, 5, 5);
9707 int opcode
= extract32(insn
, 11, 3);
9708 int rm
= extract32(insn
, 16, 5);
9709 bool u
= extract32(insn
, 29, 1);
9710 bool a
= extract32(insn
, 23, 1);
9711 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9718 case 0x03: /* FMULX */
9719 case 0x04: /* FCMEQ (reg) */
9720 case 0x07: /* FRECPS */
9721 case 0x0f: /* FRSQRTS */
9722 case 0x14: /* FCMGE (reg) */
9723 case 0x15: /* FACGE */
9724 case 0x1a: /* FABD */
9725 case 0x1c: /* FCMGT (reg) */
9726 case 0x1d: /* FACGT */
9729 unallocated_encoding(s
);
9733 if (!dc_isar_feature(aa64_fp16
, s
)) {
9734 unallocated_encoding(s
);
9737 if (!fp_access_check(s
)) {
9741 fpst
= get_fpstatus_ptr(true);
9743 tcg_op1
= read_fp_hreg(s
, rn
);
9744 tcg_op2
= read_fp_hreg(s
, rm
);
9745 tcg_res
= tcg_temp_new_i32();
9748 case 0x03: /* FMULX */
9749 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9751 case 0x04: /* FCMEQ (reg) */
9752 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9754 case 0x07: /* FRECPS */
9755 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9757 case 0x0f: /* FRSQRTS */
9758 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9760 case 0x14: /* FCMGE (reg) */
9761 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9763 case 0x15: /* FACGE */
9764 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9766 case 0x1a: /* FABD */
9767 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9768 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9770 case 0x1c: /* FCMGT (reg) */
9771 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9773 case 0x1d: /* FACGT */
9774 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9777 g_assert_not_reached();
9780 write_fp_sreg(s
, rd
, tcg_res
);
9783 tcg_temp_free_i32(tcg_res
);
9784 tcg_temp_free_i32(tcg_op1
);
9785 tcg_temp_free_i32(tcg_op2
);
9786 tcg_temp_free_ptr(fpst
);
9789 /* AdvSIMD scalar three same extra
9790 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9791 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9792 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9793 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9795 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9798 int rd
= extract32(insn
, 0, 5);
9799 int rn
= extract32(insn
, 5, 5);
9800 int opcode
= extract32(insn
, 11, 4);
9801 int rm
= extract32(insn
, 16, 5);
9802 int size
= extract32(insn
, 22, 2);
9803 bool u
= extract32(insn
, 29, 1);
9804 TCGv_i32 ele1
, ele2
, ele3
;
9808 switch (u
* 16 + opcode
) {
9809 case 0x10: /* SQRDMLAH (vector) */
9810 case 0x11: /* SQRDMLSH (vector) */
9811 if (size
!= 1 && size
!= 2) {
9812 unallocated_encoding(s
);
9815 feature
= dc_isar_feature(aa64_rdm
, s
);
9818 unallocated_encoding(s
);
9822 unallocated_encoding(s
);
9825 if (!fp_access_check(s
)) {
9829 /* Do a single operation on the lowest element in the vector.
9830 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9831 * with no side effects for all these operations.
9832 * OPTME: special-purpose helpers would avoid doing some
9833 * unnecessary work in the helper for the 16 bit cases.
9835 ele1
= tcg_temp_new_i32();
9836 ele2
= tcg_temp_new_i32();
9837 ele3
= tcg_temp_new_i32();
9839 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9840 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9841 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9844 case 0x0: /* SQRDMLAH */
9846 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9848 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9851 case 0x1: /* SQRDMLSH */
9853 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9855 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9859 g_assert_not_reached();
9861 tcg_temp_free_i32(ele1
);
9862 tcg_temp_free_i32(ele2
);
9864 res
= tcg_temp_new_i64();
9865 tcg_gen_extu_i32_i64(res
, ele3
);
9866 tcg_temp_free_i32(ele3
);
9868 write_fp_dreg(s
, rd
, res
);
9869 tcg_temp_free_i64(res
);
9872 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9873 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9874 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9876 /* Handle 64->64 opcodes which are shared between the scalar and
9877 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9878 * is valid in either group and also the double-precision fp ops.
9879 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9885 case 0x4: /* CLS, CLZ */
9887 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9889 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9893 /* This opcode is shared with CNT and RBIT but we have earlier
9894 * enforced that size == 3 if and only if this is the NOT insn.
9896 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9898 case 0x7: /* SQABS, SQNEG */
9900 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9902 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9905 case 0xa: /* CMLT */
9906 /* 64 bit integer comparison against zero, result is
9907 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9912 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9913 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9915 case 0x8: /* CMGT, CMGE */
9916 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9918 case 0x9: /* CMEQ, CMLE */
9919 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9921 case 0xb: /* ABS, NEG */
9923 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9925 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9928 case 0x2f: /* FABS */
9929 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9931 case 0x6f: /* FNEG */
9932 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9934 case 0x7f: /* FSQRT */
9935 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9937 case 0x1a: /* FCVTNS */
9938 case 0x1b: /* FCVTMS */
9939 case 0x1c: /* FCVTAS */
9940 case 0x3a: /* FCVTPS */
9941 case 0x3b: /* FCVTZS */
9943 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9944 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9945 tcg_temp_free_i32(tcg_shift
);
9948 case 0x5a: /* FCVTNU */
9949 case 0x5b: /* FCVTMU */
9950 case 0x5c: /* FCVTAU */
9951 case 0x7a: /* FCVTPU */
9952 case 0x7b: /* FCVTZU */
9954 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9955 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9956 tcg_temp_free_i32(tcg_shift
);
9959 case 0x18: /* FRINTN */
9960 case 0x19: /* FRINTM */
9961 case 0x38: /* FRINTP */
9962 case 0x39: /* FRINTZ */
9963 case 0x58: /* FRINTA */
9964 case 0x79: /* FRINTI */
9965 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9967 case 0x59: /* FRINTX */
9968 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9970 case 0x1e: /* FRINT32Z */
9971 case 0x5e: /* FRINT32X */
9972 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9974 case 0x1f: /* FRINT64Z */
9975 case 0x5f: /* FRINT64X */
9976 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9979 g_assert_not_reached();
9983 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9984 bool is_scalar
, bool is_u
, bool is_q
,
9985 int size
, int rn
, int rd
)
9987 bool is_double
= (size
== MO_64
);
9990 if (!fp_access_check(s
)) {
9994 fpst
= get_fpstatus_ptr(size
== MO_16
);
9997 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9998 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9999 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10000 NeonGenTwoDoubleOpFn
*genfn
;
10005 case 0x2e: /* FCMLT (zero) */
10008 case 0x2c: /* FCMGT (zero) */
10009 genfn
= gen_helper_neon_cgt_f64
;
10011 case 0x2d: /* FCMEQ (zero) */
10012 genfn
= gen_helper_neon_ceq_f64
;
10014 case 0x6d: /* FCMLE (zero) */
10017 case 0x6c: /* FCMGE (zero) */
10018 genfn
= gen_helper_neon_cge_f64
;
10021 g_assert_not_reached();
10024 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10025 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10027 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10029 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10031 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10033 tcg_temp_free_i64(tcg_res
);
10034 tcg_temp_free_i64(tcg_zero
);
10035 tcg_temp_free_i64(tcg_op
);
10037 clear_vec_high(s
, !is_scalar
, rd
);
10039 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10040 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10041 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10042 NeonGenTwoSingleOpFn
*genfn
;
10044 int pass
, maxpasses
;
10046 if (size
== MO_16
) {
10048 case 0x2e: /* FCMLT (zero) */
10051 case 0x2c: /* FCMGT (zero) */
10052 genfn
= gen_helper_advsimd_cgt_f16
;
10054 case 0x2d: /* FCMEQ (zero) */
10055 genfn
= gen_helper_advsimd_ceq_f16
;
10057 case 0x6d: /* FCMLE (zero) */
10060 case 0x6c: /* FCMGE (zero) */
10061 genfn
= gen_helper_advsimd_cge_f16
;
10064 g_assert_not_reached();
10068 case 0x2e: /* FCMLT (zero) */
10071 case 0x2c: /* FCMGT (zero) */
10072 genfn
= gen_helper_neon_cgt_f32
;
10074 case 0x2d: /* FCMEQ (zero) */
10075 genfn
= gen_helper_neon_ceq_f32
;
10077 case 0x6d: /* FCMLE (zero) */
10080 case 0x6c: /* FCMGE (zero) */
10081 genfn
= gen_helper_neon_cge_f32
;
10084 g_assert_not_reached();
10091 int vector_size
= 8 << is_q
;
10092 maxpasses
= vector_size
>> size
;
10095 for (pass
= 0; pass
< maxpasses
; pass
++) {
10096 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10098 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10100 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10103 write_fp_sreg(s
, rd
, tcg_res
);
10105 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10108 tcg_temp_free_i32(tcg_res
);
10109 tcg_temp_free_i32(tcg_zero
);
10110 tcg_temp_free_i32(tcg_op
);
10112 clear_vec_high(s
, is_q
, rd
);
10116 tcg_temp_free_ptr(fpst
);
10119 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10120 bool is_scalar
, bool is_u
, bool is_q
,
10121 int size
, int rn
, int rd
)
10123 bool is_double
= (size
== 3);
10124 TCGv_ptr fpst
= get_fpstatus_ptr(false);
10127 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10128 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10131 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10132 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10134 case 0x3d: /* FRECPE */
10135 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10137 case 0x3f: /* FRECPX */
10138 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10140 case 0x7d: /* FRSQRTE */
10141 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10144 g_assert_not_reached();
10146 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10148 tcg_temp_free_i64(tcg_res
);
10149 tcg_temp_free_i64(tcg_op
);
10150 clear_vec_high(s
, !is_scalar
, rd
);
10152 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10153 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10154 int pass
, maxpasses
;
10159 maxpasses
= is_q
? 4 : 2;
10162 for (pass
= 0; pass
< maxpasses
; pass
++) {
10163 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10166 case 0x3c: /* URECPE */
10167 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10169 case 0x3d: /* FRECPE */
10170 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10172 case 0x3f: /* FRECPX */
10173 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10175 case 0x7d: /* FRSQRTE */
10176 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10179 g_assert_not_reached();
10183 write_fp_sreg(s
, rd
, tcg_res
);
10185 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10188 tcg_temp_free_i32(tcg_res
);
10189 tcg_temp_free_i32(tcg_op
);
10191 clear_vec_high(s
, is_q
, rd
);
10194 tcg_temp_free_ptr(fpst
);
10197 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10198 int opcode
, bool u
, bool is_q
,
10199 int size
, int rn
, int rd
)
10201 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10202 * in the source becomes a size element in the destination).
10205 TCGv_i32 tcg_res
[2];
10206 int destelt
= is_q
? 2 : 0;
10207 int passes
= scalar
? 1 : 2;
10210 tcg_res
[1] = tcg_const_i32(0);
10213 for (pass
= 0; pass
< passes
; pass
++) {
10214 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10215 NeonGenNarrowFn
*genfn
= NULL
;
10216 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10219 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10221 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10223 tcg_res
[pass
] = tcg_temp_new_i32();
10226 case 0x12: /* XTN, SQXTUN */
10228 static NeonGenNarrowFn
* const xtnfns
[3] = {
10229 gen_helper_neon_narrow_u8
,
10230 gen_helper_neon_narrow_u16
,
10231 tcg_gen_extrl_i64_i32
,
10233 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10234 gen_helper_neon_unarrow_sat8
,
10235 gen_helper_neon_unarrow_sat16
,
10236 gen_helper_neon_unarrow_sat32
,
10239 genenvfn
= sqxtunfns
[size
];
10241 genfn
= xtnfns
[size
];
10245 case 0x14: /* SQXTN, UQXTN */
10247 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10248 { gen_helper_neon_narrow_sat_s8
,
10249 gen_helper_neon_narrow_sat_u8
},
10250 { gen_helper_neon_narrow_sat_s16
,
10251 gen_helper_neon_narrow_sat_u16
},
10252 { gen_helper_neon_narrow_sat_s32
,
10253 gen_helper_neon_narrow_sat_u32
},
10255 genenvfn
= fns
[size
][u
];
10258 case 0x16: /* FCVTN, FCVTN2 */
10259 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10261 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10263 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10264 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10265 TCGv_ptr fpst
= get_fpstatus_ptr(false);
10266 TCGv_i32 ahp
= get_ahp_flag();
10268 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10269 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10270 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10271 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10272 tcg_temp_free_i32(tcg_lo
);
10273 tcg_temp_free_i32(tcg_hi
);
10274 tcg_temp_free_ptr(fpst
);
10275 tcg_temp_free_i32(ahp
);
10278 case 0x56: /* FCVTXN, FCVTXN2 */
10279 /* 64 bit to 32 bit float conversion
10280 * with von Neumann rounding (round to odd)
10283 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10286 g_assert_not_reached();
10290 genfn(tcg_res
[pass
], tcg_op
);
10291 } else if (genenvfn
) {
10292 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10295 tcg_temp_free_i64(tcg_op
);
10298 for (pass
= 0; pass
< 2; pass
++) {
10299 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10300 tcg_temp_free_i32(tcg_res
[pass
]);
10302 clear_vec_high(s
, is_q
, rd
);
10305 /* Remaining saturating accumulating ops */
10306 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10307 bool is_q
, int size
, int rn
, int rd
)
10309 bool is_double
= (size
== 3);
10312 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10313 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10316 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10317 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10318 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10320 if (is_u
) { /* USQADD */
10321 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10322 } else { /* SUQADD */
10323 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10325 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10327 tcg_temp_free_i64(tcg_rd
);
10328 tcg_temp_free_i64(tcg_rn
);
10329 clear_vec_high(s
, !is_scalar
, rd
);
10331 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10332 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10333 int pass
, maxpasses
;
10338 maxpasses
= is_q
? 4 : 2;
10341 for (pass
= 0; pass
< maxpasses
; pass
++) {
10343 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10344 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10346 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10347 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10350 if (is_u
) { /* USQADD */
10353 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10356 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10359 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10362 g_assert_not_reached();
10364 } else { /* SUQADD */
10367 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10370 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10373 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10376 g_assert_not_reached();
10381 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10382 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10383 tcg_temp_free_i64(tcg_zero
);
10385 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10387 tcg_temp_free_i32(tcg_rd
);
10388 tcg_temp_free_i32(tcg_rn
);
10389 clear_vec_high(s
, is_q
, rd
);
10393 /* AdvSIMD scalar two reg misc
10394 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10395 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10396 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10397 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10399 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10401 int rd
= extract32(insn
, 0, 5);
10402 int rn
= extract32(insn
, 5, 5);
10403 int opcode
= extract32(insn
, 12, 5);
10404 int size
= extract32(insn
, 22, 2);
10405 bool u
= extract32(insn
, 29, 1);
10406 bool is_fcvt
= false;
10408 TCGv_i32 tcg_rmode
;
10409 TCGv_ptr tcg_fpstatus
;
10412 case 0x3: /* USQADD / SUQADD*/
10413 if (!fp_access_check(s
)) {
10416 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10418 case 0x7: /* SQABS / SQNEG */
10420 case 0xa: /* CMLT */
10422 unallocated_encoding(s
);
10426 case 0x8: /* CMGT, CMGE */
10427 case 0x9: /* CMEQ, CMLE */
10428 case 0xb: /* ABS, NEG */
10430 unallocated_encoding(s
);
10434 case 0x12: /* SQXTUN */
10436 unallocated_encoding(s
);
10440 case 0x14: /* SQXTN, UQXTN */
10442 unallocated_encoding(s
);
10445 if (!fp_access_check(s
)) {
10448 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10451 case 0x16 ... 0x1d:
10453 /* Floating point: U, size[1] and opcode indicate operation;
10454 * size[0] indicates single or double precision.
10456 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10457 size
= extract32(size
, 0, 1) ? 3 : 2;
10459 case 0x2c: /* FCMGT (zero) */
10460 case 0x2d: /* FCMEQ (zero) */
10461 case 0x2e: /* FCMLT (zero) */
10462 case 0x6c: /* FCMGE (zero) */
10463 case 0x6d: /* FCMLE (zero) */
10464 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10466 case 0x1d: /* SCVTF */
10467 case 0x5d: /* UCVTF */
10469 bool is_signed
= (opcode
== 0x1d);
10470 if (!fp_access_check(s
)) {
10473 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10476 case 0x3d: /* FRECPE */
10477 case 0x3f: /* FRECPX */
10478 case 0x7d: /* FRSQRTE */
10479 if (!fp_access_check(s
)) {
10482 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10484 case 0x1a: /* FCVTNS */
10485 case 0x1b: /* FCVTMS */
10486 case 0x3a: /* FCVTPS */
10487 case 0x3b: /* FCVTZS */
10488 case 0x5a: /* FCVTNU */
10489 case 0x5b: /* FCVTMU */
10490 case 0x7a: /* FCVTPU */
10491 case 0x7b: /* FCVTZU */
10493 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10495 case 0x1c: /* FCVTAS */
10496 case 0x5c: /* FCVTAU */
10497 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10499 rmode
= FPROUNDING_TIEAWAY
;
10501 case 0x56: /* FCVTXN, FCVTXN2 */
10503 unallocated_encoding(s
);
10506 if (!fp_access_check(s
)) {
10509 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10512 unallocated_encoding(s
);
10517 unallocated_encoding(s
);
10521 if (!fp_access_check(s
)) {
10526 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10527 tcg_fpstatus
= get_fpstatus_ptr(false);
10528 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10531 tcg_fpstatus
= NULL
;
10535 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10536 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10538 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10539 write_fp_dreg(s
, rd
, tcg_rd
);
10540 tcg_temp_free_i64(tcg_rd
);
10541 tcg_temp_free_i64(tcg_rn
);
10543 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10544 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10546 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10549 case 0x7: /* SQABS, SQNEG */
10551 NeonGenOneOpEnvFn
*genfn
;
10552 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10553 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10554 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10555 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10557 genfn
= fns
[size
][u
];
10558 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10561 case 0x1a: /* FCVTNS */
10562 case 0x1b: /* FCVTMS */
10563 case 0x1c: /* FCVTAS */
10564 case 0x3a: /* FCVTPS */
10565 case 0x3b: /* FCVTZS */
10567 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10568 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10569 tcg_temp_free_i32(tcg_shift
);
10572 case 0x5a: /* FCVTNU */
10573 case 0x5b: /* FCVTMU */
10574 case 0x5c: /* FCVTAU */
10575 case 0x7a: /* FCVTPU */
10576 case 0x7b: /* FCVTZU */
10578 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10579 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10580 tcg_temp_free_i32(tcg_shift
);
10584 g_assert_not_reached();
10587 write_fp_sreg(s
, rd
, tcg_rd
);
10588 tcg_temp_free_i32(tcg_rd
);
10589 tcg_temp_free_i32(tcg_rn
);
10593 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10594 tcg_temp_free_i32(tcg_rmode
);
10595 tcg_temp_free_ptr(tcg_fpstatus
);
10599 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10600 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10601 int immh
, int immb
, int opcode
, int rn
, int rd
)
10603 int size
= 32 - clz32(immh
) - 1;
10604 int immhb
= immh
<< 3 | immb
;
10605 int shift
= 2 * (8 << size
) - immhb
;
10606 GVecGen2iFn
*gvec_fn
;
10608 if (extract32(immh
, 3, 1) && !is_q
) {
10609 unallocated_encoding(s
);
10612 tcg_debug_assert(size
<= 3);
10614 if (!fp_access_check(s
)) {
10619 case 0x02: /* SSRA / USRA (accumulate) */
10620 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10623 case 0x08: /* SRI */
10624 gvec_fn
= gen_gvec_sri
;
10627 case 0x00: /* SSHR / USHR */
10629 if (shift
== 8 << size
) {
10630 /* Shift count the same size as element size produces zero. */
10631 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10632 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10635 gvec_fn
= tcg_gen_gvec_shri
;
10637 /* Shift count the same size as element size produces all sign. */
10638 if (shift
== 8 << size
) {
10641 gvec_fn
= tcg_gen_gvec_sari
;
10645 case 0x04: /* SRSHR / URSHR (rounding) */
10646 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10649 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10650 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10654 g_assert_not_reached();
10657 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10660 /* SHL/SLI - Vector shift left */
10661 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10662 int immh
, int immb
, int opcode
, int rn
, int rd
)
10664 int size
= 32 - clz32(immh
) - 1;
10665 int immhb
= immh
<< 3 | immb
;
10666 int shift
= immhb
- (8 << size
);
10668 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10669 assert(size
>= 0 && size
<= 3);
10671 if (extract32(immh
, 3, 1) && !is_q
) {
10672 unallocated_encoding(s
);
10676 if (!fp_access_check(s
)) {
10681 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10683 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10687 /* USHLL/SHLL - Vector shift left with widening */
10688 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10689 int immh
, int immb
, int opcode
, int rn
, int rd
)
10691 int size
= 32 - clz32(immh
) - 1;
10692 int immhb
= immh
<< 3 | immb
;
10693 int shift
= immhb
- (8 << size
);
10695 int esize
= 8 << size
;
10696 int elements
= dsize
/esize
;
10697 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10698 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10702 unallocated_encoding(s
);
10706 if (!fp_access_check(s
)) {
10710 /* For the LL variants the store is larger than the load,
10711 * so if rd == rn we would overwrite parts of our input.
10712 * So load everything right now and use shifts in the main loop.
10714 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10716 for (i
= 0; i
< elements
; i
++) {
10717 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10718 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10719 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10720 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10724 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10725 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10726 int immh
, int immb
, int opcode
, int rn
, int rd
)
10728 int immhb
= immh
<< 3 | immb
;
10729 int size
= 32 - clz32(immh
) - 1;
10731 int esize
= 8 << size
;
10732 int elements
= dsize
/esize
;
10733 int shift
= (2 * esize
) - immhb
;
10734 bool round
= extract32(opcode
, 0, 1);
10735 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10736 TCGv_i64 tcg_round
;
10739 if (extract32(immh
, 3, 1)) {
10740 unallocated_encoding(s
);
10744 if (!fp_access_check(s
)) {
10748 tcg_rn
= tcg_temp_new_i64();
10749 tcg_rd
= tcg_temp_new_i64();
10750 tcg_final
= tcg_temp_new_i64();
10751 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10754 uint64_t round_const
= 1ULL << (shift
- 1);
10755 tcg_round
= tcg_const_i64(round_const
);
10760 for (i
= 0; i
< elements
; i
++) {
10761 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10762 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10763 false, true, size
+1, shift
);
10765 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10769 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10771 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10774 tcg_temp_free_i64(tcg_round
);
10776 tcg_temp_free_i64(tcg_rn
);
10777 tcg_temp_free_i64(tcg_rd
);
10778 tcg_temp_free_i64(tcg_final
);
10780 clear_vec_high(s
, is_q
, rd
);
10784 /* AdvSIMD shift by immediate
10785 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10786 * +---+---+---+-------------+------+------+--------+---+------+------+
10787 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10788 * +---+---+---+-------------+------+------+--------+---+------+------+
10790 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10792 int rd
= extract32(insn
, 0, 5);
10793 int rn
= extract32(insn
, 5, 5);
10794 int opcode
= extract32(insn
, 11, 5);
10795 int immb
= extract32(insn
, 16, 3);
10796 int immh
= extract32(insn
, 19, 4);
10797 bool is_u
= extract32(insn
, 29, 1);
10798 bool is_q
= extract32(insn
, 30, 1);
10800 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10804 case 0x08: /* SRI */
10806 unallocated_encoding(s
);
10810 case 0x00: /* SSHR / USHR */
10811 case 0x02: /* SSRA / USRA (accumulate) */
10812 case 0x04: /* SRSHR / URSHR (rounding) */
10813 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10814 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10816 case 0x0a: /* SHL / SLI */
10817 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10819 case 0x10: /* SHRN */
10820 case 0x11: /* RSHRN / SQRSHRUN */
10822 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10825 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10828 case 0x12: /* SQSHRN / UQSHRN */
10829 case 0x13: /* SQRSHRN / UQRSHRN */
10830 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10833 case 0x14: /* SSHLL / USHLL */
10834 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10836 case 0x1c: /* SCVTF / UCVTF */
10837 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10840 case 0xc: /* SQSHLU */
10842 unallocated_encoding(s
);
10845 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10847 case 0xe: /* SQSHL, UQSHL */
10848 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10850 case 0x1f: /* FCVTZS/ FCVTZU */
10851 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10854 unallocated_encoding(s
);
10859 /* Generate code to do a "long" addition or subtraction, ie one done in
10860 * TCGv_i64 on vector lanes twice the width specified by size.
10862 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10863 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10865 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10866 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10867 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10868 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10870 NeonGenTwo64OpFn
*genfn
;
10873 genfn
= fns
[size
][is_sub
];
10874 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10877 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10878 int opcode
, int rd
, int rn
, int rm
)
10880 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10881 TCGv_i64 tcg_res
[2];
10884 tcg_res
[0] = tcg_temp_new_i64();
10885 tcg_res
[1] = tcg_temp_new_i64();
10887 /* Does this op do an adding accumulate, a subtracting accumulate,
10888 * or no accumulate at all?
10906 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10907 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10910 /* size == 2 means two 32x32->64 operations; this is worth special
10911 * casing because we can generally handle it inline.
10914 for (pass
= 0; pass
< 2; pass
++) {
10915 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10916 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10917 TCGv_i64 tcg_passres
;
10918 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10920 int elt
= pass
+ is_q
* 2;
10922 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10923 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10926 tcg_passres
= tcg_res
[pass
];
10928 tcg_passres
= tcg_temp_new_i64();
10932 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10933 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10935 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10936 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10938 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10939 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10941 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10942 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10944 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10945 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10946 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10948 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10949 tcg_temp_free_i64(tcg_tmp1
);
10950 tcg_temp_free_i64(tcg_tmp2
);
10953 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10954 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10955 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10956 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10958 case 9: /* SQDMLAL, SQDMLAL2 */
10959 case 11: /* SQDMLSL, SQDMLSL2 */
10960 case 13: /* SQDMULL, SQDMULL2 */
10961 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10962 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10963 tcg_passres
, tcg_passres
);
10966 g_assert_not_reached();
10969 if (opcode
== 9 || opcode
== 11) {
10970 /* saturating accumulate ops */
10972 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10974 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10975 tcg_res
[pass
], tcg_passres
);
10976 } else if (accop
> 0) {
10977 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10978 } else if (accop
< 0) {
10979 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10983 tcg_temp_free_i64(tcg_passres
);
10986 tcg_temp_free_i64(tcg_op1
);
10987 tcg_temp_free_i64(tcg_op2
);
10990 /* size 0 or 1, generally helper functions */
10991 for (pass
= 0; pass
< 2; pass
++) {
10992 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10993 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10994 TCGv_i64 tcg_passres
;
10995 int elt
= pass
+ is_q
* 2;
10997 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10998 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
11001 tcg_passres
= tcg_res
[pass
];
11003 tcg_passres
= tcg_temp_new_i64();
11007 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11008 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11010 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
11011 static NeonGenWidenFn
* const widenfns
[2][2] = {
11012 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11013 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11015 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11017 widenfn(tcg_op2_64
, tcg_op2
);
11018 widenfn(tcg_passres
, tcg_op1
);
11019 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11020 tcg_passres
, tcg_op2_64
);
11021 tcg_temp_free_i64(tcg_op2_64
);
11024 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11025 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11028 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11030 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11034 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11036 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11040 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11041 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11042 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11045 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11047 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11051 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11053 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11057 case 9: /* SQDMLAL, SQDMLAL2 */
11058 case 11: /* SQDMLSL, SQDMLSL2 */
11059 case 13: /* SQDMULL, SQDMULL2 */
11061 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11062 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11063 tcg_passres
, tcg_passres
);
11066 g_assert_not_reached();
11068 tcg_temp_free_i32(tcg_op1
);
11069 tcg_temp_free_i32(tcg_op2
);
11072 if (opcode
== 9 || opcode
== 11) {
11073 /* saturating accumulate ops */
11075 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11077 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11081 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11082 tcg_res
[pass
], tcg_passres
);
11084 tcg_temp_free_i64(tcg_passres
);
11089 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11090 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11091 tcg_temp_free_i64(tcg_res
[0]);
11092 tcg_temp_free_i64(tcg_res
[1]);
11095 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11096 int opcode
, int rd
, int rn
, int rm
)
11098 TCGv_i64 tcg_res
[2];
11099 int part
= is_q
? 2 : 0;
11102 for (pass
= 0; pass
< 2; pass
++) {
11103 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11104 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11105 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11106 static NeonGenWidenFn
* const widenfns
[3][2] = {
11107 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11108 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11109 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11111 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11113 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11114 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11115 widenfn(tcg_op2_wide
, tcg_op2
);
11116 tcg_temp_free_i32(tcg_op2
);
11117 tcg_res
[pass
] = tcg_temp_new_i64();
11118 gen_neon_addl(size
, (opcode
== 3),
11119 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11120 tcg_temp_free_i64(tcg_op1
);
11121 tcg_temp_free_i64(tcg_op2_wide
);
11124 for (pass
= 0; pass
< 2; pass
++) {
11125 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11126 tcg_temp_free_i64(tcg_res
[pass
]);
11130 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11132 tcg_gen_addi_i64(in
, in
, 1U << 31);
11133 tcg_gen_extrh_i64_i32(res
, in
);
11136 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11137 int opcode
, int rd
, int rn
, int rm
)
11139 TCGv_i32 tcg_res
[2];
11140 int part
= is_q
? 2 : 0;
11143 for (pass
= 0; pass
< 2; pass
++) {
11144 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11145 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11146 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11147 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11148 { gen_helper_neon_narrow_high_u8
,
11149 gen_helper_neon_narrow_round_high_u8
},
11150 { gen_helper_neon_narrow_high_u16
,
11151 gen_helper_neon_narrow_round_high_u16
},
11152 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11154 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11156 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11157 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11159 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11161 tcg_temp_free_i64(tcg_op1
);
11162 tcg_temp_free_i64(tcg_op2
);
11164 tcg_res
[pass
] = tcg_temp_new_i32();
11165 gennarrow(tcg_res
[pass
], tcg_wideres
);
11166 tcg_temp_free_i64(tcg_wideres
);
11169 for (pass
= 0; pass
< 2; pass
++) {
11170 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11171 tcg_temp_free_i32(tcg_res
[pass
]);
11173 clear_vec_high(s
, is_q
, rd
);
11176 /* AdvSIMD three different
11177 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11178 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11179 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11180 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11182 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11184 /* Instructions in this group fall into three basic classes
11185 * (in each case with the operation working on each element in
11186 * the input vectors):
11187 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11189 * (2) wide 64 x 128 -> 128
11190 * (3) narrowing 128 x 128 -> 64
11191 * Here we do initial decode, catch unallocated cases and
11192 * dispatch to separate functions for each class.
11194 int is_q
= extract32(insn
, 30, 1);
11195 int is_u
= extract32(insn
, 29, 1);
11196 int size
= extract32(insn
, 22, 2);
11197 int opcode
= extract32(insn
, 12, 4);
11198 int rm
= extract32(insn
, 16, 5);
11199 int rn
= extract32(insn
, 5, 5);
11200 int rd
= extract32(insn
, 0, 5);
11203 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11204 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11205 /* 64 x 128 -> 128 */
11207 unallocated_encoding(s
);
11210 if (!fp_access_check(s
)) {
11213 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11215 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11216 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11217 /* 128 x 128 -> 64 */
11219 unallocated_encoding(s
);
11222 if (!fp_access_check(s
)) {
11225 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11227 case 14: /* PMULL, PMULL2 */
11229 unallocated_encoding(s
);
11233 case 0: /* PMULL.P8 */
11234 if (!fp_access_check(s
)) {
11237 /* The Q field specifies lo/hi half input for this insn. */
11238 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11239 gen_helper_neon_pmull_h
);
11242 case 3: /* PMULL.P64 */
11243 if (!dc_isar_feature(aa64_pmull
, s
)) {
11244 unallocated_encoding(s
);
11247 if (!fp_access_check(s
)) {
11250 /* The Q field specifies lo/hi half input for this insn. */
11251 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11252 gen_helper_gvec_pmull_q
);
11256 unallocated_encoding(s
);
11260 case 9: /* SQDMLAL, SQDMLAL2 */
11261 case 11: /* SQDMLSL, SQDMLSL2 */
11262 case 13: /* SQDMULL, SQDMULL2 */
11263 if (is_u
|| size
== 0) {
11264 unallocated_encoding(s
);
11268 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11269 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11270 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11271 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11272 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11273 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11274 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11275 /* 64 x 64 -> 128 */
11277 unallocated_encoding(s
);
11280 if (!fp_access_check(s
)) {
11284 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11287 /* opcode 15 not allocated */
11288 unallocated_encoding(s
);
11293 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11294 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11296 int rd
= extract32(insn
, 0, 5);
11297 int rn
= extract32(insn
, 5, 5);
11298 int rm
= extract32(insn
, 16, 5);
11299 int size
= extract32(insn
, 22, 2);
11300 bool is_u
= extract32(insn
, 29, 1);
11301 bool is_q
= extract32(insn
, 30, 1);
11303 if (!fp_access_check(s
)) {
11307 switch (size
+ 4 * is_u
) {
11309 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11312 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11315 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11318 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11321 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11324 case 5: /* BSL bitwise select */
11325 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11327 case 6: /* BIT, bitwise insert if true */
11328 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11330 case 7: /* BIF, bitwise insert if false */
11331 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11335 g_assert_not_reached();
11339 /* Pairwise op subgroup of C3.6.16.
11341 * This is called directly or via the handle_3same_float for float pairwise
11342 * operations where the opcode and size are calculated differently.
11344 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11345 int size
, int rn
, int rm
, int rd
)
11350 /* Floating point operations need fpst */
11351 if (opcode
>= 0x58) {
11352 fpst
= get_fpstatus_ptr(false);
11357 if (!fp_access_check(s
)) {
11361 /* These operations work on the concatenated rm:rn, with each pair of
11362 * adjacent elements being operated on to produce an element in the result.
11365 TCGv_i64 tcg_res
[2];
11367 for (pass
= 0; pass
< 2; pass
++) {
11368 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11369 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11370 int passreg
= (pass
== 0) ? rn
: rm
;
11372 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11373 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11374 tcg_res
[pass
] = tcg_temp_new_i64();
11377 case 0x17: /* ADDP */
11378 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11380 case 0x58: /* FMAXNMP */
11381 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11383 case 0x5a: /* FADDP */
11384 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11386 case 0x5e: /* FMAXP */
11387 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11389 case 0x78: /* FMINNMP */
11390 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11392 case 0x7e: /* FMINP */
11393 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11396 g_assert_not_reached();
11399 tcg_temp_free_i64(tcg_op1
);
11400 tcg_temp_free_i64(tcg_op2
);
11403 for (pass
= 0; pass
< 2; pass
++) {
11404 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11405 tcg_temp_free_i64(tcg_res
[pass
]);
11408 int maxpass
= is_q
? 4 : 2;
11409 TCGv_i32 tcg_res
[4];
11411 for (pass
= 0; pass
< maxpass
; pass
++) {
11412 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11413 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11414 NeonGenTwoOpFn
*genfn
= NULL
;
11415 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11416 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11418 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11419 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11420 tcg_res
[pass
] = tcg_temp_new_i32();
11423 case 0x17: /* ADDP */
11425 static NeonGenTwoOpFn
* const fns
[3] = {
11426 gen_helper_neon_padd_u8
,
11427 gen_helper_neon_padd_u16
,
11433 case 0x14: /* SMAXP, UMAXP */
11435 static NeonGenTwoOpFn
* const fns
[3][2] = {
11436 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11437 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11438 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11440 genfn
= fns
[size
][u
];
11443 case 0x15: /* SMINP, UMINP */
11445 static NeonGenTwoOpFn
* const fns
[3][2] = {
11446 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11447 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11448 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11450 genfn
= fns
[size
][u
];
11453 /* The FP operations are all on single floats (32 bit) */
11454 case 0x58: /* FMAXNMP */
11455 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11457 case 0x5a: /* FADDP */
11458 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11460 case 0x5e: /* FMAXP */
11461 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11463 case 0x78: /* FMINNMP */
11464 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11466 case 0x7e: /* FMINP */
11467 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11470 g_assert_not_reached();
11473 /* FP ops called directly, otherwise call now */
11475 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11478 tcg_temp_free_i32(tcg_op1
);
11479 tcg_temp_free_i32(tcg_op2
);
11482 for (pass
= 0; pass
< maxpass
; pass
++) {
11483 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11484 tcg_temp_free_i32(tcg_res
[pass
]);
11486 clear_vec_high(s
, is_q
, rd
);
11490 tcg_temp_free_ptr(fpst
);
11494 /* Floating point op subgroup of C3.6.16. */
11495 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11497 /* For floating point ops, the U, size[1] and opcode bits
11498 * together indicate the operation. size[0] indicates single
11501 int fpopcode
= extract32(insn
, 11, 5)
11502 | (extract32(insn
, 23, 1) << 5)
11503 | (extract32(insn
, 29, 1) << 6);
11504 int is_q
= extract32(insn
, 30, 1);
11505 int size
= extract32(insn
, 22, 1);
11506 int rm
= extract32(insn
, 16, 5);
11507 int rn
= extract32(insn
, 5, 5);
11508 int rd
= extract32(insn
, 0, 5);
11510 int datasize
= is_q
? 128 : 64;
11511 int esize
= 32 << size
;
11512 int elements
= datasize
/ esize
;
11514 if (size
== 1 && !is_q
) {
11515 unallocated_encoding(s
);
11519 switch (fpopcode
) {
11520 case 0x58: /* FMAXNMP */
11521 case 0x5a: /* FADDP */
11522 case 0x5e: /* FMAXP */
11523 case 0x78: /* FMINNMP */
11524 case 0x7e: /* FMINP */
11525 if (size
&& !is_q
) {
11526 unallocated_encoding(s
);
11529 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11532 case 0x1b: /* FMULX */
11533 case 0x1f: /* FRECPS */
11534 case 0x3f: /* FRSQRTS */
11535 case 0x5d: /* FACGE */
11536 case 0x7d: /* FACGT */
11537 case 0x19: /* FMLA */
11538 case 0x39: /* FMLS */
11539 case 0x18: /* FMAXNM */
11540 case 0x1a: /* FADD */
11541 case 0x1c: /* FCMEQ */
11542 case 0x1e: /* FMAX */
11543 case 0x38: /* FMINNM */
11544 case 0x3a: /* FSUB */
11545 case 0x3e: /* FMIN */
11546 case 0x5b: /* FMUL */
11547 case 0x5c: /* FCMGE */
11548 case 0x5f: /* FDIV */
11549 case 0x7a: /* FABD */
11550 case 0x7c: /* FCMGT */
11551 if (!fp_access_check(s
)) {
11554 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11557 case 0x1d: /* FMLAL */
11558 case 0x3d: /* FMLSL */
11559 case 0x59: /* FMLAL2 */
11560 case 0x79: /* FMLSL2 */
11561 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11562 unallocated_encoding(s
);
11565 if (fp_access_check(s
)) {
11566 int is_s
= extract32(insn
, 23, 1);
11567 int is_2
= extract32(insn
, 29, 1);
11568 int data
= (is_2
<< 1) | is_s
;
11569 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11570 vec_full_reg_offset(s
, rn
),
11571 vec_full_reg_offset(s
, rm
), cpu_env
,
11572 is_q
? 16 : 8, vec_full_reg_size(s
),
11573 data
, gen_helper_gvec_fmlal_a64
);
11578 unallocated_encoding(s
);
11583 /* Integer op subgroup of C3.6.16. */
11584 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11586 int is_q
= extract32(insn
, 30, 1);
11587 int u
= extract32(insn
, 29, 1);
11588 int size
= extract32(insn
, 22, 2);
11589 int opcode
= extract32(insn
, 11, 5);
11590 int rm
= extract32(insn
, 16, 5);
11591 int rn
= extract32(insn
, 5, 5);
11592 int rd
= extract32(insn
, 0, 5);
11597 case 0x13: /* MUL, PMUL */
11598 if (u
&& size
!= 0) {
11599 unallocated_encoding(s
);
11603 case 0x0: /* SHADD, UHADD */
11604 case 0x2: /* SRHADD, URHADD */
11605 case 0x4: /* SHSUB, UHSUB */
11606 case 0xc: /* SMAX, UMAX */
11607 case 0xd: /* SMIN, UMIN */
11608 case 0xe: /* SABD, UABD */
11609 case 0xf: /* SABA, UABA */
11610 case 0x12: /* MLA, MLS */
11612 unallocated_encoding(s
);
11616 case 0x16: /* SQDMULH, SQRDMULH */
11617 if (size
== 0 || size
== 3) {
11618 unallocated_encoding(s
);
11623 if (size
== 3 && !is_q
) {
11624 unallocated_encoding(s
);
11630 if (!fp_access_check(s
)) {
11635 case 0x01: /* SQADD, UQADD */
11637 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11639 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11642 case 0x05: /* SQSUB, UQSUB */
11644 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11646 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11649 case 0x08: /* SSHL, USHL */
11651 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11653 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11656 case 0x0c: /* SMAX, UMAX */
11658 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11660 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11663 case 0x0d: /* SMIN, UMIN */
11665 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11667 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11670 case 0xe: /* SABD, UABD */
11672 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11674 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11677 case 0xf: /* SABA, UABA */
11679 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11681 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11684 case 0x10: /* ADD, SUB */
11686 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11688 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11691 case 0x13: /* MUL, PMUL */
11692 if (!u
) { /* MUL */
11693 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11694 } else { /* PMUL */
11695 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11698 case 0x12: /* MLA, MLS */
11700 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11702 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11706 if (!u
) { /* CMTST */
11707 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11711 cond
= TCG_COND_EQ
;
11713 case 0x06: /* CMGT, CMHI */
11714 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11716 case 0x07: /* CMGE, CMHS */
11717 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11719 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11720 vec_full_reg_offset(s
, rn
),
11721 vec_full_reg_offset(s
, rm
),
11722 is_q
? 16 : 8, vec_full_reg_size(s
));
11728 for (pass
= 0; pass
< 2; pass
++) {
11729 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11730 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11731 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11733 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11734 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11736 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11738 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11740 tcg_temp_free_i64(tcg_res
);
11741 tcg_temp_free_i64(tcg_op1
);
11742 tcg_temp_free_i64(tcg_op2
);
11745 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11746 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11747 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11748 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11749 NeonGenTwoOpFn
*genfn
= NULL
;
11750 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11752 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11753 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11756 case 0x0: /* SHADD, UHADD */
11758 static NeonGenTwoOpFn
* const fns
[3][2] = {
11759 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11760 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11761 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11763 genfn
= fns
[size
][u
];
11766 case 0x2: /* SRHADD, URHADD */
11768 static NeonGenTwoOpFn
* const fns
[3][2] = {
11769 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11770 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11771 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11773 genfn
= fns
[size
][u
];
11776 case 0x4: /* SHSUB, UHSUB */
11778 static NeonGenTwoOpFn
* const fns
[3][2] = {
11779 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11780 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11781 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11783 genfn
= fns
[size
][u
];
11786 case 0x9: /* SQSHL, UQSHL */
11788 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11789 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11790 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11791 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11793 genenvfn
= fns
[size
][u
];
11796 case 0xa: /* SRSHL, URSHL */
11798 static NeonGenTwoOpFn
* const fns
[3][2] = {
11799 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11800 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11801 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11803 genfn
= fns
[size
][u
];
11806 case 0xb: /* SQRSHL, UQRSHL */
11808 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11809 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11810 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11811 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11813 genenvfn
= fns
[size
][u
];
11816 case 0x16: /* SQDMULH, SQRDMULH */
11818 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11819 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11820 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11822 assert(size
== 1 || size
== 2);
11823 genenvfn
= fns
[size
- 1][u
];
11827 g_assert_not_reached();
11831 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11833 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11836 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11838 tcg_temp_free_i32(tcg_res
);
11839 tcg_temp_free_i32(tcg_op1
);
11840 tcg_temp_free_i32(tcg_op2
);
11843 clear_vec_high(s
, is_q
, rd
);
11846 /* AdvSIMD three same
11847 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11848 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11849 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11850 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11852 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11854 int opcode
= extract32(insn
, 11, 5);
11857 case 0x3: /* logic ops */
11858 disas_simd_3same_logic(s
, insn
);
11860 case 0x17: /* ADDP */
11861 case 0x14: /* SMAXP, UMAXP */
11862 case 0x15: /* SMINP, UMINP */
11864 /* Pairwise operations */
11865 int is_q
= extract32(insn
, 30, 1);
11866 int u
= extract32(insn
, 29, 1);
11867 int size
= extract32(insn
, 22, 2);
11868 int rm
= extract32(insn
, 16, 5);
11869 int rn
= extract32(insn
, 5, 5);
11870 int rd
= extract32(insn
, 0, 5);
11871 if (opcode
== 0x17) {
11872 if (u
|| (size
== 3 && !is_q
)) {
11873 unallocated_encoding(s
);
11878 unallocated_encoding(s
);
11882 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11885 case 0x18 ... 0x31:
11886 /* floating point ops, sz[1] and U are part of opcode */
11887 disas_simd_3same_float(s
, insn
);
11890 disas_simd_3same_int(s
, insn
);
11896 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11898 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11899 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11900 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11901 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11903 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11904 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11907 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11909 int opcode
, fpopcode
;
11910 int is_q
, u
, a
, rm
, rn
, rd
;
11911 int datasize
, elements
;
11914 bool pairwise
= false;
11916 if (!dc_isar_feature(aa64_fp16
, s
)) {
11917 unallocated_encoding(s
);
11921 if (!fp_access_check(s
)) {
11925 /* For these floating point ops, the U, a and opcode bits
11926 * together indicate the operation.
11928 opcode
= extract32(insn
, 11, 3);
11929 u
= extract32(insn
, 29, 1);
11930 a
= extract32(insn
, 23, 1);
11931 is_q
= extract32(insn
, 30, 1);
11932 rm
= extract32(insn
, 16, 5);
11933 rn
= extract32(insn
, 5, 5);
11934 rd
= extract32(insn
, 0, 5);
11936 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11937 datasize
= is_q
? 128 : 64;
11938 elements
= datasize
/ 16;
11940 switch (fpopcode
) {
11941 case 0x10: /* FMAXNMP */
11942 case 0x12: /* FADDP */
11943 case 0x16: /* FMAXP */
11944 case 0x18: /* FMINNMP */
11945 case 0x1e: /* FMINP */
11950 fpst
= get_fpstatus_ptr(true);
11953 int maxpass
= is_q
? 8 : 4;
11954 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11955 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11956 TCGv_i32 tcg_res
[8];
11958 for (pass
= 0; pass
< maxpass
; pass
++) {
11959 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11960 int passelt
= (pass
<< 1) & (maxpass
- 1);
11962 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11963 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11964 tcg_res
[pass
] = tcg_temp_new_i32();
11966 switch (fpopcode
) {
11967 case 0x10: /* FMAXNMP */
11968 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11971 case 0x12: /* FADDP */
11972 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11974 case 0x16: /* FMAXP */
11975 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11977 case 0x18: /* FMINNMP */
11978 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11981 case 0x1e: /* FMINP */
11982 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11985 g_assert_not_reached();
11989 for (pass
= 0; pass
< maxpass
; pass
++) {
11990 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11991 tcg_temp_free_i32(tcg_res
[pass
]);
11994 tcg_temp_free_i32(tcg_op1
);
11995 tcg_temp_free_i32(tcg_op2
);
11998 for (pass
= 0; pass
< elements
; pass
++) {
11999 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12000 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12001 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12003 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12004 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12006 switch (fpopcode
) {
12007 case 0x0: /* FMAXNM */
12008 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12010 case 0x1: /* FMLA */
12011 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12012 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12015 case 0x2: /* FADD */
12016 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12018 case 0x3: /* FMULX */
12019 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12021 case 0x4: /* FCMEQ */
12022 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12024 case 0x6: /* FMAX */
12025 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12027 case 0x7: /* FRECPS */
12028 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12030 case 0x8: /* FMINNM */
12031 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12033 case 0x9: /* FMLS */
12034 /* As usual for ARM, separate negation for fused multiply-add */
12035 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12036 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12037 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12040 case 0xa: /* FSUB */
12041 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12043 case 0xe: /* FMIN */
12044 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12046 case 0xf: /* FRSQRTS */
12047 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12049 case 0x13: /* FMUL */
12050 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12052 case 0x14: /* FCMGE */
12053 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12055 case 0x15: /* FACGE */
12056 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12058 case 0x17: /* FDIV */
12059 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12061 case 0x1a: /* FABD */
12062 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12063 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12065 case 0x1c: /* FCMGT */
12066 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12068 case 0x1d: /* FACGT */
12069 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12072 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
12073 __func__
, insn
, fpopcode
, s
->pc_curr
);
12074 g_assert_not_reached();
12077 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12078 tcg_temp_free_i32(tcg_res
);
12079 tcg_temp_free_i32(tcg_op1
);
12080 tcg_temp_free_i32(tcg_op2
);
12084 tcg_temp_free_ptr(fpst
);
12086 clear_vec_high(s
, is_q
, rd
);
12089 /* AdvSIMD three same extra
12090 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12091 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12092 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12093 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12095 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12097 int rd
= extract32(insn
, 0, 5);
12098 int rn
= extract32(insn
, 5, 5);
12099 int opcode
= extract32(insn
, 11, 4);
12100 int rm
= extract32(insn
, 16, 5);
12101 int size
= extract32(insn
, 22, 2);
12102 bool u
= extract32(insn
, 29, 1);
12103 bool is_q
= extract32(insn
, 30, 1);
12107 switch (u
* 16 + opcode
) {
12108 case 0x10: /* SQRDMLAH (vector) */
12109 case 0x11: /* SQRDMLSH (vector) */
12110 if (size
!= 1 && size
!= 2) {
12111 unallocated_encoding(s
);
12114 feature
= dc_isar_feature(aa64_rdm
, s
);
12116 case 0x02: /* SDOT (vector) */
12117 case 0x12: /* UDOT (vector) */
12118 if (size
!= MO_32
) {
12119 unallocated_encoding(s
);
12122 feature
= dc_isar_feature(aa64_dp
, s
);
12124 case 0x18: /* FCMLA, #0 */
12125 case 0x19: /* FCMLA, #90 */
12126 case 0x1a: /* FCMLA, #180 */
12127 case 0x1b: /* FCMLA, #270 */
12128 case 0x1c: /* FCADD, #90 */
12129 case 0x1e: /* FCADD, #270 */
12131 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12132 || (size
== 3 && !is_q
)) {
12133 unallocated_encoding(s
);
12136 feature
= dc_isar_feature(aa64_fcma
, s
);
12139 unallocated_encoding(s
);
12143 unallocated_encoding(s
);
12146 if (!fp_access_check(s
)) {
12151 case 0x0: /* SQRDMLAH (vector) */
12152 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12155 case 0x1: /* SQRDMLSH (vector) */
12156 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12159 case 0x2: /* SDOT / UDOT */
12160 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
12161 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12164 case 0x8: /* FCMLA, #0 */
12165 case 0x9: /* FCMLA, #90 */
12166 case 0xa: /* FCMLA, #180 */
12167 case 0xb: /* FCMLA, #270 */
12168 rot
= extract32(opcode
, 0, 2);
12171 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
12172 gen_helper_gvec_fcmlah
);
12175 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12176 gen_helper_gvec_fcmlas
);
12179 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
12180 gen_helper_gvec_fcmlad
);
12183 g_assert_not_reached();
12187 case 0xc: /* FCADD, #90 */
12188 case 0xe: /* FCADD, #270 */
12189 rot
= extract32(opcode
, 1, 1);
12192 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12193 gen_helper_gvec_fcaddh
);
12196 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12197 gen_helper_gvec_fcadds
);
12200 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12201 gen_helper_gvec_fcaddd
);
12204 g_assert_not_reached();
12209 g_assert_not_reached();
12213 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12214 int size
, int rn
, int rd
)
12216 /* Handle 2-reg-misc ops which are widening (so each size element
12217 * in the source becomes a 2*size element in the destination.
12218 * The only instruction like this is FCVTL.
12223 /* 32 -> 64 bit fp conversion */
12224 TCGv_i64 tcg_res
[2];
12225 int srcelt
= is_q
? 2 : 0;
12227 for (pass
= 0; pass
< 2; pass
++) {
12228 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12229 tcg_res
[pass
] = tcg_temp_new_i64();
12231 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12232 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12233 tcg_temp_free_i32(tcg_op
);
12235 for (pass
= 0; pass
< 2; pass
++) {
12236 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12237 tcg_temp_free_i64(tcg_res
[pass
]);
12240 /* 16 -> 32 bit fp conversion */
12241 int srcelt
= is_q
? 4 : 0;
12242 TCGv_i32 tcg_res
[4];
12243 TCGv_ptr fpst
= get_fpstatus_ptr(false);
12244 TCGv_i32 ahp
= get_ahp_flag();
12246 for (pass
= 0; pass
< 4; pass
++) {
12247 tcg_res
[pass
] = tcg_temp_new_i32();
12249 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12250 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12253 for (pass
= 0; pass
< 4; pass
++) {
12254 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12255 tcg_temp_free_i32(tcg_res
[pass
]);
12258 tcg_temp_free_ptr(fpst
);
12259 tcg_temp_free_i32(ahp
);
12263 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12264 bool is_q
, int size
, int rn
, int rd
)
12266 int op
= (opcode
<< 1) | u
;
12267 int opsz
= op
+ size
;
12268 int grp_size
= 3 - opsz
;
12269 int dsize
= is_q
? 128 : 64;
12273 unallocated_encoding(s
);
12277 if (!fp_access_check(s
)) {
12282 /* Special case bytes, use bswap op on each group of elements */
12283 int groups
= dsize
/ (8 << grp_size
);
12285 for (i
= 0; i
< groups
; i
++) {
12286 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12288 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12289 switch (grp_size
) {
12291 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
12294 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
12297 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12300 g_assert_not_reached();
12302 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12303 tcg_temp_free_i64(tcg_tmp
);
12305 clear_vec_high(s
, is_q
, rd
);
12307 int revmask
= (1 << grp_size
) - 1;
12308 int esize
= 8 << size
;
12309 int elements
= dsize
/ esize
;
12310 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12311 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12312 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12314 for (i
= 0; i
< elements
; i
++) {
12315 int e_rev
= (i
& 0xf) ^ revmask
;
12316 int off
= e_rev
* esize
;
12317 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12319 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12320 tcg_rn
, off
- 64, esize
);
12322 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12325 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12326 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12328 tcg_temp_free_i64(tcg_rd_hi
);
12329 tcg_temp_free_i64(tcg_rd
);
12330 tcg_temp_free_i64(tcg_rn
);
12334 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12335 bool is_q
, int size
, int rn
, int rd
)
12337 /* Implement the pairwise operations from 2-misc:
12338 * SADDLP, UADDLP, SADALP, UADALP.
12339 * These all add pairs of elements in the input to produce a
12340 * double-width result element in the output (possibly accumulating).
12342 bool accum
= (opcode
== 0x6);
12343 int maxpass
= is_q
? 2 : 1;
12345 TCGv_i64 tcg_res
[2];
12348 /* 32 + 32 -> 64 op */
12349 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12351 for (pass
= 0; pass
< maxpass
; pass
++) {
12352 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12353 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12355 tcg_res
[pass
] = tcg_temp_new_i64();
12357 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12358 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12359 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12361 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12362 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12365 tcg_temp_free_i64(tcg_op1
);
12366 tcg_temp_free_i64(tcg_op2
);
12369 for (pass
= 0; pass
< maxpass
; pass
++) {
12370 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12371 NeonGenOne64OpFn
*genfn
;
12372 static NeonGenOne64OpFn
* const fns
[2][2] = {
12373 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12374 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12377 genfn
= fns
[size
][u
];
12379 tcg_res
[pass
] = tcg_temp_new_i64();
12381 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12382 genfn(tcg_res
[pass
], tcg_op
);
12385 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12387 gen_helper_neon_addl_u16(tcg_res
[pass
],
12388 tcg_res
[pass
], tcg_op
);
12390 gen_helper_neon_addl_u32(tcg_res
[pass
],
12391 tcg_res
[pass
], tcg_op
);
12394 tcg_temp_free_i64(tcg_op
);
12398 tcg_res
[1] = tcg_const_i64(0);
12400 for (pass
= 0; pass
< 2; pass
++) {
12401 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12402 tcg_temp_free_i64(tcg_res
[pass
]);
12406 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12408 /* Implement SHLL and SHLL2 */
12410 int part
= is_q
? 2 : 0;
12411 TCGv_i64 tcg_res
[2];
12413 for (pass
= 0; pass
< 2; pass
++) {
12414 static NeonGenWidenFn
* const widenfns
[3] = {
12415 gen_helper_neon_widen_u8
,
12416 gen_helper_neon_widen_u16
,
12417 tcg_gen_extu_i32_i64
,
12419 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12420 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12422 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12423 tcg_res
[pass
] = tcg_temp_new_i64();
12424 widenfn(tcg_res
[pass
], tcg_op
);
12425 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12427 tcg_temp_free_i32(tcg_op
);
12430 for (pass
= 0; pass
< 2; pass
++) {
12431 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12432 tcg_temp_free_i64(tcg_res
[pass
]);
12436 /* AdvSIMD two reg misc
12437 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12438 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12439 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12440 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12442 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12444 int size
= extract32(insn
, 22, 2);
12445 int opcode
= extract32(insn
, 12, 5);
12446 bool u
= extract32(insn
, 29, 1);
12447 bool is_q
= extract32(insn
, 30, 1);
12448 int rn
= extract32(insn
, 5, 5);
12449 int rd
= extract32(insn
, 0, 5);
12450 bool need_fpstatus
= false;
12451 bool need_rmode
= false;
12453 TCGv_i32 tcg_rmode
;
12454 TCGv_ptr tcg_fpstatus
;
12457 case 0x0: /* REV64, REV32 */
12458 case 0x1: /* REV16 */
12459 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12461 case 0x5: /* CNT, NOT, RBIT */
12462 if (u
&& size
== 0) {
12465 } else if (u
&& size
== 1) {
12468 } else if (!u
&& size
== 0) {
12472 unallocated_encoding(s
);
12474 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12475 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12477 unallocated_encoding(s
);
12480 if (!fp_access_check(s
)) {
12484 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12486 case 0x4: /* CLS, CLZ */
12488 unallocated_encoding(s
);
12492 case 0x2: /* SADDLP, UADDLP */
12493 case 0x6: /* SADALP, UADALP */
12495 unallocated_encoding(s
);
12498 if (!fp_access_check(s
)) {
12501 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12503 case 0x13: /* SHLL, SHLL2 */
12504 if (u
== 0 || size
== 3) {
12505 unallocated_encoding(s
);
12508 if (!fp_access_check(s
)) {
12511 handle_shll(s
, is_q
, size
, rn
, rd
);
12513 case 0xa: /* CMLT */
12515 unallocated_encoding(s
);
12519 case 0x8: /* CMGT, CMGE */
12520 case 0x9: /* CMEQ, CMLE */
12521 case 0xb: /* ABS, NEG */
12522 if (size
== 3 && !is_q
) {
12523 unallocated_encoding(s
);
12527 case 0x3: /* SUQADD, USQADD */
12528 if (size
== 3 && !is_q
) {
12529 unallocated_encoding(s
);
12532 if (!fp_access_check(s
)) {
12535 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12537 case 0x7: /* SQABS, SQNEG */
12538 if (size
== 3 && !is_q
) {
12539 unallocated_encoding(s
);
12544 case 0x16 ... 0x1f:
12546 /* Floating point: U, size[1] and opcode indicate operation;
12547 * size[0] indicates single or double precision.
12549 int is_double
= extract32(size
, 0, 1);
12550 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12551 size
= is_double
? 3 : 2;
12553 case 0x2f: /* FABS */
12554 case 0x6f: /* FNEG */
12555 if (size
== 3 && !is_q
) {
12556 unallocated_encoding(s
);
12560 case 0x1d: /* SCVTF */
12561 case 0x5d: /* UCVTF */
12563 bool is_signed
= (opcode
== 0x1d) ? true : false;
12564 int elements
= is_double
? 2 : is_q
? 4 : 2;
12565 if (is_double
&& !is_q
) {
12566 unallocated_encoding(s
);
12569 if (!fp_access_check(s
)) {
12572 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12575 case 0x2c: /* FCMGT (zero) */
12576 case 0x2d: /* FCMEQ (zero) */
12577 case 0x2e: /* FCMLT (zero) */
12578 case 0x6c: /* FCMGE (zero) */
12579 case 0x6d: /* FCMLE (zero) */
12580 if (size
== 3 && !is_q
) {
12581 unallocated_encoding(s
);
12584 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12586 case 0x7f: /* FSQRT */
12587 if (size
== 3 && !is_q
) {
12588 unallocated_encoding(s
);
12592 case 0x1a: /* FCVTNS */
12593 case 0x1b: /* FCVTMS */
12594 case 0x3a: /* FCVTPS */
12595 case 0x3b: /* FCVTZS */
12596 case 0x5a: /* FCVTNU */
12597 case 0x5b: /* FCVTMU */
12598 case 0x7a: /* FCVTPU */
12599 case 0x7b: /* FCVTZU */
12600 need_fpstatus
= true;
12602 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12603 if (size
== 3 && !is_q
) {
12604 unallocated_encoding(s
);
12608 case 0x5c: /* FCVTAU */
12609 case 0x1c: /* FCVTAS */
12610 need_fpstatus
= true;
12612 rmode
= FPROUNDING_TIEAWAY
;
12613 if (size
== 3 && !is_q
) {
12614 unallocated_encoding(s
);
12618 case 0x3c: /* URECPE */
12620 unallocated_encoding(s
);
12624 case 0x3d: /* FRECPE */
12625 case 0x7d: /* FRSQRTE */
12626 if (size
== 3 && !is_q
) {
12627 unallocated_encoding(s
);
12630 if (!fp_access_check(s
)) {
12633 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12635 case 0x56: /* FCVTXN, FCVTXN2 */
12637 unallocated_encoding(s
);
12641 case 0x16: /* FCVTN, FCVTN2 */
12642 /* handle_2misc_narrow does a 2*size -> size operation, but these
12643 * instructions encode the source size rather than dest size.
12645 if (!fp_access_check(s
)) {
12648 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12650 case 0x17: /* FCVTL, FCVTL2 */
12651 if (!fp_access_check(s
)) {
12654 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12656 case 0x18: /* FRINTN */
12657 case 0x19: /* FRINTM */
12658 case 0x38: /* FRINTP */
12659 case 0x39: /* FRINTZ */
12661 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12663 case 0x59: /* FRINTX */
12664 case 0x79: /* FRINTI */
12665 need_fpstatus
= true;
12666 if (size
== 3 && !is_q
) {
12667 unallocated_encoding(s
);
12671 case 0x58: /* FRINTA */
12673 rmode
= FPROUNDING_TIEAWAY
;
12674 need_fpstatus
= true;
12675 if (size
== 3 && !is_q
) {
12676 unallocated_encoding(s
);
12680 case 0x7c: /* URSQRTE */
12682 unallocated_encoding(s
);
12686 case 0x1e: /* FRINT32Z */
12687 case 0x1f: /* FRINT64Z */
12689 rmode
= FPROUNDING_ZERO
;
12691 case 0x5e: /* FRINT32X */
12692 case 0x5f: /* FRINT64X */
12693 need_fpstatus
= true;
12694 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12695 unallocated_encoding(s
);
12700 unallocated_encoding(s
);
12706 unallocated_encoding(s
);
12710 if (!fp_access_check(s
)) {
12714 if (need_fpstatus
|| need_rmode
) {
12715 tcg_fpstatus
= get_fpstatus_ptr(false);
12717 tcg_fpstatus
= NULL
;
12720 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12721 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12728 if (u
&& size
== 0) { /* NOT */
12729 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12733 case 0x8: /* CMGT, CMGE */
12735 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12737 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12740 case 0x9: /* CMEQ, CMLE */
12742 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12744 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12747 case 0xa: /* CMLT */
12748 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12751 if (u
) { /* ABS, NEG */
12752 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12754 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12760 /* All 64-bit element operations can be shared with scalar 2misc */
12763 /* Coverity claims (size == 3 && !is_q) has been eliminated
12764 * from all paths leading to here.
12766 tcg_debug_assert(is_q
);
12767 for (pass
= 0; pass
< 2; pass
++) {
12768 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12769 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12771 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12773 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12774 tcg_rmode
, tcg_fpstatus
);
12776 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12778 tcg_temp_free_i64(tcg_res
);
12779 tcg_temp_free_i64(tcg_op
);
12784 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12785 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12786 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12788 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12791 /* Special cases for 32 bit elements */
12793 case 0x4: /* CLS */
12795 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12797 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12800 case 0x7: /* SQABS, SQNEG */
12802 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12804 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12807 case 0x2f: /* FABS */
12808 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12810 case 0x6f: /* FNEG */
12811 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12813 case 0x7f: /* FSQRT */
12814 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12816 case 0x1a: /* FCVTNS */
12817 case 0x1b: /* FCVTMS */
12818 case 0x1c: /* FCVTAS */
12819 case 0x3a: /* FCVTPS */
12820 case 0x3b: /* FCVTZS */
12822 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12823 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12824 tcg_shift
, tcg_fpstatus
);
12825 tcg_temp_free_i32(tcg_shift
);
12828 case 0x5a: /* FCVTNU */
12829 case 0x5b: /* FCVTMU */
12830 case 0x5c: /* FCVTAU */
12831 case 0x7a: /* FCVTPU */
12832 case 0x7b: /* FCVTZU */
12834 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12835 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12836 tcg_shift
, tcg_fpstatus
);
12837 tcg_temp_free_i32(tcg_shift
);
12840 case 0x18: /* FRINTN */
12841 case 0x19: /* FRINTM */
12842 case 0x38: /* FRINTP */
12843 case 0x39: /* FRINTZ */
12844 case 0x58: /* FRINTA */
12845 case 0x79: /* FRINTI */
12846 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12848 case 0x59: /* FRINTX */
12849 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12851 case 0x7c: /* URSQRTE */
12852 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12854 case 0x1e: /* FRINT32Z */
12855 case 0x5e: /* FRINT32X */
12856 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12858 case 0x1f: /* FRINT64Z */
12859 case 0x5f: /* FRINT64X */
12860 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12863 g_assert_not_reached();
12866 /* Use helpers for 8 and 16 bit elements */
12868 case 0x5: /* CNT, RBIT */
12869 /* For these two insns size is part of the opcode specifier
12870 * (handled earlier); they always operate on byte elements.
12873 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12875 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12878 case 0x7: /* SQABS, SQNEG */
12880 NeonGenOneOpEnvFn
*genfn
;
12881 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12882 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12883 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12885 genfn
= fns
[size
][u
];
12886 genfn(tcg_res
, cpu_env
, tcg_op
);
12889 case 0x4: /* CLS, CLZ */
12892 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12894 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12898 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12900 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12905 g_assert_not_reached();
12909 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12911 tcg_temp_free_i32(tcg_res
);
12912 tcg_temp_free_i32(tcg_op
);
12915 clear_vec_high(s
, is_q
, rd
);
12918 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12919 tcg_temp_free_i32(tcg_rmode
);
12921 if (need_fpstatus
) {
12922 tcg_temp_free_ptr(tcg_fpstatus
);
12926 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12928 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12929 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12930 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12931 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12932 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12933 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12935 * This actually covers two groups where scalar access is governed by
12936 * bit 28. A bunch of the instructions (float to integral) only exist
12937 * in the vector form and are un-allocated for the scalar decode. Also
12938 * in the scalar decode Q is always 1.
12940 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12942 int fpop
, opcode
, a
, u
;
12946 bool only_in_vector
= false;
12949 TCGv_i32 tcg_rmode
= NULL
;
12950 TCGv_ptr tcg_fpstatus
= NULL
;
12951 bool need_rmode
= false;
12952 bool need_fpst
= true;
12955 if (!dc_isar_feature(aa64_fp16
, s
)) {
12956 unallocated_encoding(s
);
12960 rd
= extract32(insn
, 0, 5);
12961 rn
= extract32(insn
, 5, 5);
12963 a
= extract32(insn
, 23, 1);
12964 u
= extract32(insn
, 29, 1);
12965 is_scalar
= extract32(insn
, 28, 1);
12966 is_q
= extract32(insn
, 30, 1);
12968 opcode
= extract32(insn
, 12, 5);
12969 fpop
= deposit32(opcode
, 5, 1, a
);
12970 fpop
= deposit32(fpop
, 6, 1, u
);
12972 rd
= extract32(insn
, 0, 5);
12973 rn
= extract32(insn
, 5, 5);
12976 case 0x1d: /* SCVTF */
12977 case 0x5d: /* UCVTF */
12984 elements
= (is_q
? 8 : 4);
12987 if (!fp_access_check(s
)) {
12990 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12994 case 0x2c: /* FCMGT (zero) */
12995 case 0x2d: /* FCMEQ (zero) */
12996 case 0x2e: /* FCMLT (zero) */
12997 case 0x6c: /* FCMGE (zero) */
12998 case 0x6d: /* FCMLE (zero) */
12999 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13001 case 0x3d: /* FRECPE */
13002 case 0x3f: /* FRECPX */
13004 case 0x18: /* FRINTN */
13006 only_in_vector
= true;
13007 rmode
= FPROUNDING_TIEEVEN
;
13009 case 0x19: /* FRINTM */
13011 only_in_vector
= true;
13012 rmode
= FPROUNDING_NEGINF
;
13014 case 0x38: /* FRINTP */
13016 only_in_vector
= true;
13017 rmode
= FPROUNDING_POSINF
;
13019 case 0x39: /* FRINTZ */
13021 only_in_vector
= true;
13022 rmode
= FPROUNDING_ZERO
;
13024 case 0x58: /* FRINTA */
13026 only_in_vector
= true;
13027 rmode
= FPROUNDING_TIEAWAY
;
13029 case 0x59: /* FRINTX */
13030 case 0x79: /* FRINTI */
13031 only_in_vector
= true;
13032 /* current rounding mode */
13034 case 0x1a: /* FCVTNS */
13036 rmode
= FPROUNDING_TIEEVEN
;
13038 case 0x1b: /* FCVTMS */
13040 rmode
= FPROUNDING_NEGINF
;
13042 case 0x1c: /* FCVTAS */
13044 rmode
= FPROUNDING_TIEAWAY
;
13046 case 0x3a: /* FCVTPS */
13048 rmode
= FPROUNDING_POSINF
;
13050 case 0x3b: /* FCVTZS */
13052 rmode
= FPROUNDING_ZERO
;
13054 case 0x5a: /* FCVTNU */
13056 rmode
= FPROUNDING_TIEEVEN
;
13058 case 0x5b: /* FCVTMU */
13060 rmode
= FPROUNDING_NEGINF
;
13062 case 0x5c: /* FCVTAU */
13064 rmode
= FPROUNDING_TIEAWAY
;
13066 case 0x7a: /* FCVTPU */
13068 rmode
= FPROUNDING_POSINF
;
13070 case 0x7b: /* FCVTZU */
13072 rmode
= FPROUNDING_ZERO
;
13074 case 0x2f: /* FABS */
13075 case 0x6f: /* FNEG */
13078 case 0x7d: /* FRSQRTE */
13079 case 0x7f: /* FSQRT (vector) */
13082 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
13083 g_assert_not_reached();
13087 /* Check additional constraints for the scalar encoding */
13090 unallocated_encoding(s
);
13093 /* FRINTxx is only in the vector form */
13094 if (only_in_vector
) {
13095 unallocated_encoding(s
);
13100 if (!fp_access_check(s
)) {
13104 if (need_rmode
|| need_fpst
) {
13105 tcg_fpstatus
= get_fpstatus_ptr(true);
13109 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13110 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13114 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13115 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13118 case 0x1a: /* FCVTNS */
13119 case 0x1b: /* FCVTMS */
13120 case 0x1c: /* FCVTAS */
13121 case 0x3a: /* FCVTPS */
13122 case 0x3b: /* FCVTZS */
13123 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13125 case 0x3d: /* FRECPE */
13126 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13128 case 0x3f: /* FRECPX */
13129 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13131 case 0x5a: /* FCVTNU */
13132 case 0x5b: /* FCVTMU */
13133 case 0x5c: /* FCVTAU */
13134 case 0x7a: /* FCVTPU */
13135 case 0x7b: /* FCVTZU */
13136 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13138 case 0x6f: /* FNEG */
13139 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13141 case 0x7d: /* FRSQRTE */
13142 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13145 g_assert_not_reached();
13148 /* limit any sign extension going on */
13149 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13150 write_fp_sreg(s
, rd
, tcg_res
);
13152 tcg_temp_free_i32(tcg_res
);
13153 tcg_temp_free_i32(tcg_op
);
13155 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13156 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13157 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13159 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13162 case 0x1a: /* FCVTNS */
13163 case 0x1b: /* FCVTMS */
13164 case 0x1c: /* FCVTAS */
13165 case 0x3a: /* FCVTPS */
13166 case 0x3b: /* FCVTZS */
13167 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13169 case 0x3d: /* FRECPE */
13170 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13172 case 0x5a: /* FCVTNU */
13173 case 0x5b: /* FCVTMU */
13174 case 0x5c: /* FCVTAU */
13175 case 0x7a: /* FCVTPU */
13176 case 0x7b: /* FCVTZU */
13177 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13179 case 0x18: /* FRINTN */
13180 case 0x19: /* FRINTM */
13181 case 0x38: /* FRINTP */
13182 case 0x39: /* FRINTZ */
13183 case 0x58: /* FRINTA */
13184 case 0x79: /* FRINTI */
13185 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13187 case 0x59: /* FRINTX */
13188 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13190 case 0x2f: /* FABS */
13191 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13193 case 0x6f: /* FNEG */
13194 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13196 case 0x7d: /* FRSQRTE */
13197 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13199 case 0x7f: /* FSQRT */
13200 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13203 g_assert_not_reached();
13206 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13208 tcg_temp_free_i32(tcg_res
);
13209 tcg_temp_free_i32(tcg_op
);
13212 clear_vec_high(s
, is_q
, rd
);
13216 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13217 tcg_temp_free_i32(tcg_rmode
);
13220 if (tcg_fpstatus
) {
13221 tcg_temp_free_ptr(tcg_fpstatus
);
13225 /* AdvSIMD scalar x indexed element
13226 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13227 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13228 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13229 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13230 * AdvSIMD vector x indexed element
13231 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13232 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13233 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13234 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13236 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13238 /* This encoding has two kinds of instruction:
13239 * normal, where we perform elt x idxelt => elt for each
13240 * element in the vector
13241 * long, where we perform elt x idxelt and generate a result of
13242 * double the width of the input element
13243 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13245 bool is_scalar
= extract32(insn
, 28, 1);
13246 bool is_q
= extract32(insn
, 30, 1);
13247 bool u
= extract32(insn
, 29, 1);
13248 int size
= extract32(insn
, 22, 2);
13249 int l
= extract32(insn
, 21, 1);
13250 int m
= extract32(insn
, 20, 1);
13251 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13252 int rm
= extract32(insn
, 16, 4);
13253 int opcode
= extract32(insn
, 12, 4);
13254 int h
= extract32(insn
, 11, 1);
13255 int rn
= extract32(insn
, 5, 5);
13256 int rd
= extract32(insn
, 0, 5);
13257 bool is_long
= false;
13259 bool is_fp16
= false;
13263 switch (16 * u
+ opcode
) {
13264 case 0x08: /* MUL */
13265 case 0x10: /* MLA */
13266 case 0x14: /* MLS */
13268 unallocated_encoding(s
);
13272 case 0x02: /* SMLAL, SMLAL2 */
13273 case 0x12: /* UMLAL, UMLAL2 */
13274 case 0x06: /* SMLSL, SMLSL2 */
13275 case 0x16: /* UMLSL, UMLSL2 */
13276 case 0x0a: /* SMULL, SMULL2 */
13277 case 0x1a: /* UMULL, UMULL2 */
13279 unallocated_encoding(s
);
13284 case 0x03: /* SQDMLAL, SQDMLAL2 */
13285 case 0x07: /* SQDMLSL, SQDMLSL2 */
13286 case 0x0b: /* SQDMULL, SQDMULL2 */
13289 case 0x0c: /* SQDMULH */
13290 case 0x0d: /* SQRDMULH */
13292 case 0x01: /* FMLA */
13293 case 0x05: /* FMLS */
13294 case 0x09: /* FMUL */
13295 case 0x19: /* FMULX */
13298 case 0x1d: /* SQRDMLAH */
13299 case 0x1f: /* SQRDMLSH */
13300 if (!dc_isar_feature(aa64_rdm
, s
)) {
13301 unallocated_encoding(s
);
13305 case 0x0e: /* SDOT */
13306 case 0x1e: /* UDOT */
13307 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13308 unallocated_encoding(s
);
13312 case 0x11: /* FCMLA #0 */
13313 case 0x13: /* FCMLA #90 */
13314 case 0x15: /* FCMLA #180 */
13315 case 0x17: /* FCMLA #270 */
13316 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13317 unallocated_encoding(s
);
13322 case 0x00: /* FMLAL */
13323 case 0x04: /* FMLSL */
13324 case 0x18: /* FMLAL2 */
13325 case 0x1c: /* FMLSL2 */
13326 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13327 unallocated_encoding(s
);
13331 /* is_fp, but we pass cpu_env not fp_status. */
13334 unallocated_encoding(s
);
13339 case 1: /* normal fp */
13340 /* convert insn encoded size to MemOp size */
13342 case 0: /* half-precision */
13346 case MO_32
: /* single precision */
13347 case MO_64
: /* double precision */
13350 unallocated_encoding(s
);
13355 case 2: /* complex fp */
13356 /* Each indexable element is a complex pair. */
13361 unallocated_encoding(s
);
13369 unallocated_encoding(s
);
13374 default: /* integer */
13378 unallocated_encoding(s
);
13383 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13384 unallocated_encoding(s
);
13388 /* Given MemOp size, adjust register and indexing. */
13391 index
= h
<< 2 | l
<< 1 | m
;
13394 index
= h
<< 1 | l
;
13399 unallocated_encoding(s
);
13406 g_assert_not_reached();
13409 if (!fp_access_check(s
)) {
13414 fpst
= get_fpstatus_ptr(is_fp16
);
13419 switch (16 * u
+ opcode
) {
13420 case 0x0e: /* SDOT */
13421 case 0x1e: /* UDOT */
13422 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13423 u
? gen_helper_gvec_udot_idx_b
13424 : gen_helper_gvec_sdot_idx_b
);
13426 case 0x11: /* FCMLA #0 */
13427 case 0x13: /* FCMLA #90 */
13428 case 0x15: /* FCMLA #180 */
13429 case 0x17: /* FCMLA #270 */
13431 int rot
= extract32(insn
, 13, 2);
13432 int data
= (index
<< 2) | rot
;
13433 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13434 vec_full_reg_offset(s
, rn
),
13435 vec_full_reg_offset(s
, rm
), fpst
,
13436 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13438 ? gen_helper_gvec_fcmlas_idx
13439 : gen_helper_gvec_fcmlah_idx
);
13440 tcg_temp_free_ptr(fpst
);
13444 case 0x00: /* FMLAL */
13445 case 0x04: /* FMLSL */
13446 case 0x18: /* FMLAL2 */
13447 case 0x1c: /* FMLSL2 */
13449 int is_s
= extract32(opcode
, 2, 1);
13451 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13452 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13453 vec_full_reg_offset(s
, rn
),
13454 vec_full_reg_offset(s
, rm
), cpu_env
,
13455 is_q
? 16 : 8, vec_full_reg_size(s
),
13456 data
, gen_helper_gvec_fmlal_idx_a64
);
13462 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13465 assert(is_fp
&& is_q
&& !is_long
);
13467 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13469 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13470 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13471 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13473 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13475 switch (16 * u
+ opcode
) {
13476 case 0x05: /* FMLS */
13477 /* As usual for ARM, separate negation for fused multiply-add */
13478 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13480 case 0x01: /* FMLA */
13481 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13482 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13484 case 0x09: /* FMUL */
13485 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13487 case 0x19: /* FMULX */
13488 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13491 g_assert_not_reached();
13494 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13495 tcg_temp_free_i64(tcg_op
);
13496 tcg_temp_free_i64(tcg_res
);
13499 tcg_temp_free_i64(tcg_idx
);
13500 clear_vec_high(s
, !is_scalar
, rd
);
13501 } else if (!is_long
) {
13502 /* 32 bit floating point, or 16 or 32 bit integer.
13503 * For the 16 bit scalar case we use the usual Neon helpers and
13504 * rely on the fact that 0 op 0 == 0 with no side effects.
13506 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13507 int pass
, maxpasses
;
13512 maxpasses
= is_q
? 4 : 2;
13515 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13517 if (size
== 1 && !is_scalar
) {
13518 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13519 * the index into both halves of the 32 bit tcg_idx and then use
13520 * the usual Neon helpers.
13522 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13525 for (pass
= 0; pass
< maxpasses
; pass
++) {
13526 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13527 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13529 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13531 switch (16 * u
+ opcode
) {
13532 case 0x08: /* MUL */
13533 case 0x10: /* MLA */
13534 case 0x14: /* MLS */
13536 static NeonGenTwoOpFn
* const fns
[2][2] = {
13537 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13538 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13540 NeonGenTwoOpFn
*genfn
;
13541 bool is_sub
= opcode
== 0x4;
13544 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13546 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13548 if (opcode
== 0x8) {
13551 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13552 genfn
= fns
[size
- 1][is_sub
];
13553 genfn(tcg_res
, tcg_op
, tcg_res
);
13556 case 0x05: /* FMLS */
13557 case 0x01: /* FMLA */
13558 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13559 is_scalar
? size
: MO_32
);
13562 if (opcode
== 0x5) {
13563 /* As usual for ARM, separate negation for fused
13565 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13568 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13571 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13576 if (opcode
== 0x5) {
13577 /* As usual for ARM, separate negation for
13578 * fused multiply-add */
13579 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13581 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13585 g_assert_not_reached();
13588 case 0x09: /* FMUL */
13592 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13595 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13600 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13603 g_assert_not_reached();
13606 case 0x19: /* FMULX */
13610 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13613 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13618 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13621 g_assert_not_reached();
13624 case 0x0c: /* SQDMULH */
13626 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13629 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13633 case 0x0d: /* SQRDMULH */
13635 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13638 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13642 case 0x1d: /* SQRDMLAH */
13643 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13644 is_scalar
? size
: MO_32
);
13646 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13647 tcg_op
, tcg_idx
, tcg_res
);
13649 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13650 tcg_op
, tcg_idx
, tcg_res
);
13653 case 0x1f: /* SQRDMLSH */
13654 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13655 is_scalar
? size
: MO_32
);
13657 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13658 tcg_op
, tcg_idx
, tcg_res
);
13660 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13661 tcg_op
, tcg_idx
, tcg_res
);
13665 g_assert_not_reached();
13669 write_fp_sreg(s
, rd
, tcg_res
);
13671 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13674 tcg_temp_free_i32(tcg_op
);
13675 tcg_temp_free_i32(tcg_res
);
13678 tcg_temp_free_i32(tcg_idx
);
13679 clear_vec_high(s
, is_q
, rd
);
13681 /* long ops: 16x16->32 or 32x32->64 */
13682 TCGv_i64 tcg_res
[2];
13684 bool satop
= extract32(opcode
, 0, 1);
13685 MemOp memop
= MO_32
;
13692 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13694 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13696 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13697 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13698 TCGv_i64 tcg_passres
;
13704 passelt
= pass
+ (is_q
* 2);
13707 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13709 tcg_res
[pass
] = tcg_temp_new_i64();
13711 if (opcode
== 0xa || opcode
== 0xb) {
13712 /* Non-accumulating ops */
13713 tcg_passres
= tcg_res
[pass
];
13715 tcg_passres
= tcg_temp_new_i64();
13718 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13719 tcg_temp_free_i64(tcg_op
);
13722 /* saturating, doubling */
13723 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13724 tcg_passres
, tcg_passres
);
13727 if (opcode
== 0xa || opcode
== 0xb) {
13731 /* Accumulating op: handle accumulate step */
13732 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13735 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13736 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13738 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13739 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13741 case 0x7: /* SQDMLSL, SQDMLSL2 */
13742 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13744 case 0x3: /* SQDMLAL, SQDMLAL2 */
13745 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13750 g_assert_not_reached();
13752 tcg_temp_free_i64(tcg_passres
);
13754 tcg_temp_free_i64(tcg_idx
);
13756 clear_vec_high(s
, !is_scalar
, rd
);
13758 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13761 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13764 /* The simplest way to handle the 16x16 indexed ops is to
13765 * duplicate the index into both halves of the 32 bit tcg_idx
13766 * and then use the usual Neon helpers.
13768 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13771 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13772 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13773 TCGv_i64 tcg_passres
;
13776 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13778 read_vec_element_i32(s
, tcg_op
, rn
,
13779 pass
+ (is_q
* 2), MO_32
);
13782 tcg_res
[pass
] = tcg_temp_new_i64();
13784 if (opcode
== 0xa || opcode
== 0xb) {
13785 /* Non-accumulating ops */
13786 tcg_passres
= tcg_res
[pass
];
13788 tcg_passres
= tcg_temp_new_i64();
13791 if (memop
& MO_SIGN
) {
13792 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13794 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13797 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13798 tcg_passres
, tcg_passres
);
13800 tcg_temp_free_i32(tcg_op
);
13802 if (opcode
== 0xa || opcode
== 0xb) {
13806 /* Accumulating op: handle accumulate step */
13807 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13810 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13811 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13814 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13815 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13818 case 0x7: /* SQDMLSL, SQDMLSL2 */
13819 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13821 case 0x3: /* SQDMLAL, SQDMLAL2 */
13822 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13827 g_assert_not_reached();
13829 tcg_temp_free_i64(tcg_passres
);
13831 tcg_temp_free_i32(tcg_idx
);
13834 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13839 tcg_res
[1] = tcg_const_i64(0);
13842 for (pass
= 0; pass
< 2; pass
++) {
13843 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13844 tcg_temp_free_i64(tcg_res
[pass
]);
13849 tcg_temp_free_ptr(fpst
);
13854 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13855 * +-----------------+------+-----------+--------+-----+------+------+
13856 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13857 * +-----------------+------+-----------+--------+-----+------+------+
13859 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13861 int size
= extract32(insn
, 22, 2);
13862 int opcode
= extract32(insn
, 12, 5);
13863 int rn
= extract32(insn
, 5, 5);
13864 int rd
= extract32(insn
, 0, 5);
13866 gen_helper_gvec_2
*genfn2
= NULL
;
13867 gen_helper_gvec_3
*genfn3
= NULL
;
13869 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13870 unallocated_encoding(s
);
13875 case 0x4: /* AESE */
13877 genfn3
= gen_helper_crypto_aese
;
13879 case 0x6: /* AESMC */
13881 genfn2
= gen_helper_crypto_aesmc
;
13883 case 0x5: /* AESD */
13885 genfn3
= gen_helper_crypto_aese
;
13887 case 0x7: /* AESIMC */
13889 genfn2
= gen_helper_crypto_aesmc
;
13892 unallocated_encoding(s
);
13896 if (!fp_access_check(s
)) {
13900 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13902 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13906 /* Crypto three-reg SHA
13907 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13908 * +-----------------+------+---+------+---+--------+-----+------+------+
13909 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13910 * +-----------------+------+---+------+---+--------+-----+------+------+
13912 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13914 int size
= extract32(insn
, 22, 2);
13915 int opcode
= extract32(insn
, 12, 3);
13916 int rm
= extract32(insn
, 16, 5);
13917 int rn
= extract32(insn
, 5, 5);
13918 int rd
= extract32(insn
, 0, 5);
13919 gen_helper_gvec_3
*genfn
;
13923 unallocated_encoding(s
);
13928 case 0: /* SHA1C */
13929 genfn
= gen_helper_crypto_sha1c
;
13930 feature
= dc_isar_feature(aa64_sha1
, s
);
13932 case 1: /* SHA1P */
13933 genfn
= gen_helper_crypto_sha1p
;
13934 feature
= dc_isar_feature(aa64_sha1
, s
);
13936 case 2: /* SHA1M */
13937 genfn
= gen_helper_crypto_sha1m
;
13938 feature
= dc_isar_feature(aa64_sha1
, s
);
13940 case 3: /* SHA1SU0 */
13941 genfn
= gen_helper_crypto_sha1su0
;
13942 feature
= dc_isar_feature(aa64_sha1
, s
);
13944 case 4: /* SHA256H */
13945 genfn
= gen_helper_crypto_sha256h
;
13946 feature
= dc_isar_feature(aa64_sha256
, s
);
13948 case 5: /* SHA256H2 */
13949 genfn
= gen_helper_crypto_sha256h2
;
13950 feature
= dc_isar_feature(aa64_sha256
, s
);
13952 case 6: /* SHA256SU1 */
13953 genfn
= gen_helper_crypto_sha256su1
;
13954 feature
= dc_isar_feature(aa64_sha256
, s
);
13957 unallocated_encoding(s
);
13962 unallocated_encoding(s
);
13966 if (!fp_access_check(s
)) {
13969 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
13972 /* Crypto two-reg SHA
13973 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13974 * +-----------------+------+-----------+--------+-----+------+------+
13975 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13976 * +-----------------+------+-----------+--------+-----+------+------+
13978 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13980 int size
= extract32(insn
, 22, 2);
13981 int opcode
= extract32(insn
, 12, 5);
13982 int rn
= extract32(insn
, 5, 5);
13983 int rd
= extract32(insn
, 0, 5);
13984 gen_helper_gvec_2
*genfn
;
13988 unallocated_encoding(s
);
13993 case 0: /* SHA1H */
13994 feature
= dc_isar_feature(aa64_sha1
, s
);
13995 genfn
= gen_helper_crypto_sha1h
;
13997 case 1: /* SHA1SU1 */
13998 feature
= dc_isar_feature(aa64_sha1
, s
);
13999 genfn
= gen_helper_crypto_sha1su1
;
14001 case 2: /* SHA256SU0 */
14002 feature
= dc_isar_feature(aa64_sha256
, s
);
14003 genfn
= gen_helper_crypto_sha256su0
;
14006 unallocated_encoding(s
);
14011 unallocated_encoding(s
);
14015 if (!fp_access_check(s
)) {
14018 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14021 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14023 tcg_gen_rotli_i64(d
, m
, 1);
14024 tcg_gen_xor_i64(d
, d
, n
);
14027 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14029 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14030 tcg_gen_xor_vec(vece
, d
, d
, n
);
14033 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14034 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14036 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14037 static const GVecGen3 op
= {
14038 .fni8
= gen_rax1_i64
,
14039 .fniv
= gen_rax1_vec
,
14040 .opt_opc
= vecop_list
,
14041 .fno
= gen_helper_crypto_rax1
,
14044 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14047 /* Crypto three-reg SHA512
14048 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14049 * +-----------------------+------+---+---+-----+--------+------+------+
14050 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14051 * +-----------------------+------+---+---+-----+--------+------+------+
14053 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14055 int opcode
= extract32(insn
, 10, 2);
14056 int o
= extract32(insn
, 14, 1);
14057 int rm
= extract32(insn
, 16, 5);
14058 int rn
= extract32(insn
, 5, 5);
14059 int rd
= extract32(insn
, 0, 5);
14061 gen_helper_gvec_3
*oolfn
= NULL
;
14062 GVecGen3Fn
*gvecfn
= NULL
;
14066 case 0: /* SHA512H */
14067 feature
= dc_isar_feature(aa64_sha512
, s
);
14068 oolfn
= gen_helper_crypto_sha512h
;
14070 case 1: /* SHA512H2 */
14071 feature
= dc_isar_feature(aa64_sha512
, s
);
14072 oolfn
= gen_helper_crypto_sha512h2
;
14074 case 2: /* SHA512SU1 */
14075 feature
= dc_isar_feature(aa64_sha512
, s
);
14076 oolfn
= gen_helper_crypto_sha512su1
;
14079 feature
= dc_isar_feature(aa64_sha3
, s
);
14080 gvecfn
= gen_gvec_rax1
;
14083 g_assert_not_reached();
14087 case 0: /* SM3PARTW1 */
14088 feature
= dc_isar_feature(aa64_sm3
, s
);
14089 oolfn
= gen_helper_crypto_sm3partw1
;
14091 case 1: /* SM3PARTW2 */
14092 feature
= dc_isar_feature(aa64_sm3
, s
);
14093 oolfn
= gen_helper_crypto_sm3partw2
;
14095 case 2: /* SM4EKEY */
14096 feature
= dc_isar_feature(aa64_sm4
, s
);
14097 oolfn
= gen_helper_crypto_sm4ekey
;
14100 unallocated_encoding(s
);
14106 unallocated_encoding(s
);
14110 if (!fp_access_check(s
)) {
14115 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14117 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14121 /* Crypto two-reg SHA512
14122 * 31 12 11 10 9 5 4 0
14123 * +-----------------------------------------+--------+------+------+
14124 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14125 * +-----------------------------------------+--------+------+------+
14127 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14129 int opcode
= extract32(insn
, 10, 2);
14130 int rn
= extract32(insn
, 5, 5);
14131 int rd
= extract32(insn
, 0, 5);
14135 case 0: /* SHA512SU0 */
14136 feature
= dc_isar_feature(aa64_sha512
, s
);
14139 feature
= dc_isar_feature(aa64_sm4
, s
);
14142 unallocated_encoding(s
);
14147 unallocated_encoding(s
);
14151 if (!fp_access_check(s
)) {
14156 case 0: /* SHA512SU0 */
14157 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14160 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14163 g_assert_not_reached();
14167 /* Crypto four-register
14168 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14169 * +-------------------+-----+------+---+------+------+------+
14170 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14171 * +-------------------+-----+------+---+------+------+------+
14173 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14175 int op0
= extract32(insn
, 21, 2);
14176 int rm
= extract32(insn
, 16, 5);
14177 int ra
= extract32(insn
, 10, 5);
14178 int rn
= extract32(insn
, 5, 5);
14179 int rd
= extract32(insn
, 0, 5);
14185 feature
= dc_isar_feature(aa64_sha3
, s
);
14187 case 2: /* SM3SS1 */
14188 feature
= dc_isar_feature(aa64_sm3
, s
);
14191 unallocated_encoding(s
);
14196 unallocated_encoding(s
);
14200 if (!fp_access_check(s
)) {
14205 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14208 tcg_op1
= tcg_temp_new_i64();
14209 tcg_op2
= tcg_temp_new_i64();
14210 tcg_op3
= tcg_temp_new_i64();
14211 tcg_res
[0] = tcg_temp_new_i64();
14212 tcg_res
[1] = tcg_temp_new_i64();
14214 for (pass
= 0; pass
< 2; pass
++) {
14215 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14216 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14217 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14221 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14224 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14226 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14228 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14229 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14231 tcg_temp_free_i64(tcg_op1
);
14232 tcg_temp_free_i64(tcg_op2
);
14233 tcg_temp_free_i64(tcg_op3
);
14234 tcg_temp_free_i64(tcg_res
[0]);
14235 tcg_temp_free_i64(tcg_res
[1]);
14237 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14239 tcg_op1
= tcg_temp_new_i32();
14240 tcg_op2
= tcg_temp_new_i32();
14241 tcg_op3
= tcg_temp_new_i32();
14242 tcg_res
= tcg_temp_new_i32();
14243 tcg_zero
= tcg_const_i32(0);
14245 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14246 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14247 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14249 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14250 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14251 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14252 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14254 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14255 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14256 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14257 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14259 tcg_temp_free_i32(tcg_op1
);
14260 tcg_temp_free_i32(tcg_op2
);
14261 tcg_temp_free_i32(tcg_op3
);
14262 tcg_temp_free_i32(tcg_res
);
14263 tcg_temp_free_i32(tcg_zero
);
14268 * 31 21 20 16 15 10 9 5 4 0
14269 * +-----------------------+------+--------+------+------+
14270 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14271 * +-----------------------+------+--------+------+------+
14273 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14275 int rm
= extract32(insn
, 16, 5);
14276 int imm6
= extract32(insn
, 10, 6);
14277 int rn
= extract32(insn
, 5, 5);
14278 int rd
= extract32(insn
, 0, 5);
14279 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
14282 if (!dc_isar_feature(aa64_sha3
, s
)) {
14283 unallocated_encoding(s
);
14287 if (!fp_access_check(s
)) {
14291 tcg_op1
= tcg_temp_new_i64();
14292 tcg_op2
= tcg_temp_new_i64();
14293 tcg_res
[0] = tcg_temp_new_i64();
14294 tcg_res
[1] = tcg_temp_new_i64();
14296 for (pass
= 0; pass
< 2; pass
++) {
14297 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14298 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14300 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
14301 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
14303 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14304 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14306 tcg_temp_free_i64(tcg_op1
);
14307 tcg_temp_free_i64(tcg_op2
);
14308 tcg_temp_free_i64(tcg_res
[0]);
14309 tcg_temp_free_i64(tcg_res
[1]);
14312 /* Crypto three-reg imm2
14313 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14314 * +-----------------------+------+-----+------+--------+------+------+
14315 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14316 * +-----------------------+------+-----+------+--------+------+------+
14318 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14320 static gen_helper_gvec_3
* const fns
[4] = {
14321 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14322 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14324 int opcode
= extract32(insn
, 10, 2);
14325 int imm2
= extract32(insn
, 12, 2);
14326 int rm
= extract32(insn
, 16, 5);
14327 int rn
= extract32(insn
, 5, 5);
14328 int rd
= extract32(insn
, 0, 5);
14330 if (!dc_isar_feature(aa64_sm3
, s
)) {
14331 unallocated_encoding(s
);
14335 if (!fp_access_check(s
)) {
14339 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14342 /* C3.6 Data processing - SIMD, inc Crypto
14344 * As the decode gets a little complex we are using a table based
14345 * approach for this part of the decode.
14347 static const AArch64DecodeTable data_proc_simd
[] = {
14348 /* pattern , mask , fn */
14349 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14350 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14351 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14352 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14353 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14354 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14355 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14356 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14357 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14358 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14359 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14360 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14361 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14362 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14363 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14364 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14365 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14366 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14367 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14368 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14369 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14370 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14371 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14372 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14373 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14374 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14375 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14376 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14377 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14378 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14379 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14380 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14381 { 0x00000000, 0x00000000, NULL
}
14384 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14386 /* Note that this is called with all non-FP cases from
14387 * table C3-6 so it must UNDEF for entries not specifically
14388 * allocated to instructions in that table.
14390 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14394 unallocated_encoding(s
);
14398 /* C3.6 Data processing - SIMD and floating point */
14399 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14401 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14402 disas_data_proc_fp(s
, insn
);
14404 /* SIMD, including crypto */
14405 disas_data_proc_simd(s
, insn
);
14411 * @env: The cpu environment
14412 * @s: The DisasContext
14414 * Return true if the page is guarded.
14416 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14418 #ifdef CONFIG_USER_ONLY
14419 return false; /* FIXME */
14421 uint64_t addr
= s
->base
.pc_first
;
14422 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14423 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14424 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14427 * We test this immediately after reading an insn, which means
14428 * that any normal page must be in the TLB. The only exception
14429 * would be for executing from flash or device memory, which
14430 * does not retain the TLB entry.
14432 * FIXME: Assume false for those, for now. We could use
14433 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14434 * table entry even for that case.
14436 return (tlb_hit(entry
->addr_code
, addr
) &&
14437 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14442 * btype_destination_ok:
14443 * @insn: The instruction at the branch destination
14444 * @bt: SCTLR_ELx.BT
14445 * @btype: PSTATE.BTYPE, and is non-zero
14447 * On a guarded page, there are a limited number of insns
14448 * that may be present at the branch target:
14449 * - branch target identifiers,
14450 * - paciasp, pacibsp,
14453 * Anything else causes a Branch Target Exception.
14455 * Return true if the branch is compatible, false to raise BTITRAP.
14457 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14459 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14461 switch (extract32(insn
, 5, 7)) {
14462 case 0b011001: /* PACIASP */
14463 case 0b011011: /* PACIBSP */
14465 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14466 * with btype == 3. Otherwise all btype are ok.
14468 return !bt
|| btype
!= 3;
14469 case 0b100000: /* BTI */
14470 /* Not compatible with any btype. */
14472 case 0b100010: /* BTI c */
14473 /* Not compatible with btype == 3 */
14475 case 0b100100: /* BTI j */
14476 /* Not compatible with btype == 2 */
14478 case 0b100110: /* BTI jc */
14479 /* Compatible with any btype. */
14483 switch (insn
& 0xffe0001fu
) {
14484 case 0xd4200000u
: /* BRK */
14485 case 0xd4400000u
: /* HLT */
14486 /* Give priority to the breakpoint exception. */
14493 /* C3.1 A64 instruction index by encoding */
14494 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14498 s
->pc_curr
= s
->base
.pc_next
;
14499 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14501 s
->base
.pc_next
+= 4;
14503 s
->fp_access_checked
= false;
14505 if (dc_isar_feature(aa64_bti
, s
)) {
14506 if (s
->base
.num_insns
== 1) {
14508 * At the first insn of the TB, compute s->guarded_page.
14509 * We delayed computing this until successfully reading
14510 * the first insn of the TB, above. This (mostly) ensures
14511 * that the softmmu tlb entry has been populated, and the
14512 * page table GP bit is available.
14514 * Note that we need to compute this even if btype == 0,
14515 * because this value is used for BR instructions later
14516 * where ENV is not available.
14518 s
->guarded_page
= is_guarded_page(env
, s
);
14520 /* First insn can have btype set to non-zero. */
14521 tcg_debug_assert(s
->btype
>= 0);
14524 * Note that the Branch Target Exception has fairly high
14525 * priority -- below debugging exceptions but above most
14526 * everything else. This allows us to handle this now
14527 * instead of waiting until the insn is otherwise decoded.
14531 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14532 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14533 syn_btitrap(s
->btype
),
14534 default_exception_el(s
));
14538 /* Not the first insn: btype must be 0. */
14539 tcg_debug_assert(s
->btype
== 0);
14543 switch (extract32(insn
, 25, 4)) {
14544 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14545 unallocated_encoding(s
);
14548 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14549 unallocated_encoding(s
);
14552 case 0x8: case 0x9: /* Data processing - immediate */
14553 disas_data_proc_imm(s
, insn
);
14555 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14556 disas_b_exc_sys(s
, insn
);
14561 case 0xe: /* Loads and stores */
14562 disas_ldst(s
, insn
);
14565 case 0xd: /* Data processing - register */
14566 disas_data_proc_reg(s
, insn
);
14569 case 0xf: /* Data processing - SIMD and floating point */
14570 disas_data_proc_simd_fp(s
, insn
);
14573 assert(FALSE
); /* all 15 cases should be handled above */
14577 /* if we allocated any temporaries, free them here */
14581 * After execution of most insns, btype is reset to 0.
14582 * Note that we set btype == -1 when the insn sets btype.
14584 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14589 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14592 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14593 CPUARMState
*env
= cpu
->env_ptr
;
14594 ARMCPU
*arm_cpu
= env_archcpu(env
);
14595 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14596 int bound
, core_mmu_idx
;
14598 dc
->isar
= &arm_cpu
->isar
;
14602 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14603 * there is no secure EL1, so we route exceptions to EL3.
14605 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14606 !arm_el_is_aa64(env
, 3);
14609 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14610 dc
->condexec_mask
= 0;
14611 dc
->condexec_cond
= 0;
14612 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14613 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14614 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14615 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14616 dc
->tcma
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TCMA
);
14617 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14618 #if !defined(CONFIG_USER_ONLY)
14619 dc
->user
= (dc
->current_el
== 0);
14621 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14622 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14623 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14624 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14625 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14626 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14627 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14628 dc
->ata
= FIELD_EX32(tb_flags
, TBFLAG_A64
, ATA
);
14629 dc
->mte_active
[0] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE_ACTIVE
);
14630 dc
->mte_active
[1] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE0_ACTIVE
);
14632 dc
->vec_stride
= 0;
14633 dc
->cp_regs
= arm_cpu
->cp_regs
;
14634 dc
->features
= env
->features
;
14635 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14637 /* Single step state. The code-generation logic here is:
14639 * generate code with no special handling for single-stepping (except
14640 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14641 * this happens anyway because those changes are all system register or
14643 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14644 * emit code for one insn
14645 * emit code to clear PSTATE.SS
14646 * emit code to generate software step exception for completed step
14647 * end TB (as usual for having generated an exception)
14648 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14649 * emit code to generate a software step exception
14652 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14653 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14654 dc
->is_ldex
= false;
14655 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14657 /* Bound the number of insns to execute to those left on the page. */
14658 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14660 /* If architectural single step active, limit to 1. */
14661 if (dc
->ss_active
) {
14664 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14666 init_tmp_a64_array(dc
);
14669 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14673 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14675 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14677 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14678 dc
->insn_start
= tcg_last_op();
14681 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14682 const CPUBreakpoint
*bp
)
14684 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14686 if (bp
->flags
& BP_CPU
) {
14687 gen_a64_set_pc_im(dc
->base
.pc_next
);
14688 gen_helper_check_breakpoints(cpu_env
);
14689 /* End the TB early; it likely won't be executed */
14690 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14692 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14693 /* The address covered by the breakpoint must be
14694 included in [tb->pc, tb->pc + tb->size) in order
14695 to for it to be properly cleared -- thus we
14696 increment the PC here so that the logic setting
14697 tb->size below does the right thing. */
14698 dc
->base
.pc_next
+= 4;
14699 dc
->base
.is_jmp
= DISAS_NORETURN
;
14705 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14707 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14708 CPUARMState
*env
= cpu
->env_ptr
;
14710 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14711 /* Singlestep state is Active-pending.
14712 * If we're in this state at the start of a TB then either
14713 * a) we just took an exception to an EL which is being debugged
14714 * and this is the first insn in the exception handler
14715 * b) debug exceptions were masked and we just unmasked them
14716 * without changing EL (eg by clearing PSTATE.D)
14717 * In either case we're going to take a swstep exception in the
14718 * "did not step an insn" case, and so the syndrome ISV and EX
14719 * bits should be zero.
14721 assert(dc
->base
.num_insns
== 1);
14722 gen_swstep_exception(dc
, 0, 0);
14723 dc
->base
.is_jmp
= DISAS_NORETURN
;
14725 disas_a64_insn(env
, dc
);
14728 translator_loop_temp_check(&dc
->base
);
14731 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14733 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14735 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14736 /* Note that this means single stepping WFI doesn't halt the CPU.
14737 * For conditional branch insns this is harmless unreachable code as
14738 * gen_goto_tb() has already handled emitting the debug exception
14739 * (and thus a tb-jump is not possible when singlestepping).
14741 switch (dc
->base
.is_jmp
) {
14743 gen_a64_set_pc_im(dc
->base
.pc_next
);
14747 if (dc
->base
.singlestep_enabled
) {
14748 gen_exception_internal(EXCP_DEBUG
);
14750 gen_step_complete_exception(dc
);
14753 case DISAS_NORETURN
:
14757 switch (dc
->base
.is_jmp
) {
14759 case DISAS_TOO_MANY
:
14760 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14763 case DISAS_UPDATE_EXIT
:
14764 gen_a64_set_pc_im(dc
->base
.pc_next
);
14767 tcg_gen_exit_tb(NULL
, 0);
14769 case DISAS_UPDATE_NOCHAIN
:
14770 gen_a64_set_pc_im(dc
->base
.pc_next
);
14773 tcg_gen_lookup_and_goto_ptr();
14775 case DISAS_NORETURN
:
14779 gen_a64_set_pc_im(dc
->base
.pc_next
);
14780 gen_helper_wfe(cpu_env
);
14783 gen_a64_set_pc_im(dc
->base
.pc_next
);
14784 gen_helper_yield(cpu_env
);
14788 /* This is a special case because we don't want to just halt the CPU
14789 * if trying to debug across a WFI.
14791 TCGv_i32 tmp
= tcg_const_i32(4);
14793 gen_a64_set_pc_im(dc
->base
.pc_next
);
14794 gen_helper_wfi(cpu_env
, tmp
);
14795 tcg_temp_free_i32(tmp
);
14796 /* The helper doesn't necessarily throw an exception, but we
14797 * must go back to the main loop to check for interrupts anyway.
14799 tcg_gen_exit_tb(NULL
, 0);
14806 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14809 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14811 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14812 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14815 const TranslatorOps aarch64_translator_ops
= {
14816 .init_disas_context
= aarch64_tr_init_disas_context
,
14817 .tb_start
= aarch64_tr_tb_start
,
14818 .insn_start
= aarch64_tr_insn_start
,
14819 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14820 .translate_insn
= aarch64_tr_translate_insn
,
14821 .tb_stop
= aarch64_tr_tb_stop
,
14822 .disas_log
= aarch64_tr_disas_log
,