4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
155 fprintf_function cpu_fprintf
, int flags
)
157 ARMCPU
*cpu
= ARM_CPU(cs
);
158 CPUARMState
*env
= &cpu
->env
;
159 uint32_t psr
= pstate_read(env
);
161 int el
= arm_current_el(env
);
162 const char *ns_status
;
164 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
165 for (i
= 0; i
< 32; i
++) {
167 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
169 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
170 (i
+ 2) % 3 ? " " : "\n");
174 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
175 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
179 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
181 psr
& PSTATE_N
? 'N' : '-',
182 psr
& PSTATE_Z
? 'Z' : '-',
183 psr
& PSTATE_C
? 'C' : '-',
184 psr
& PSTATE_V
? 'V' : '-',
187 psr
& PSTATE_SP
? 'h' : 't');
189 if (cpu_isar_feature(aa64_bti
, cpu
)) {
190 cpu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
192 if (!(flags
& CPU_DUMP_FPU
)) {
193 cpu_fprintf(f
, "\n");
196 if (fp_exception_el(env
, el
) != 0) {
197 cpu_fprintf(f
, " FPU disabled\n");
200 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
201 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
203 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
204 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
206 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
208 if (i
== FFR_PRED_NUM
) {
209 cpu_fprintf(f
, "FFR=");
210 /* It's last, so end the line. */
213 cpu_fprintf(f
, "P%02d=", i
);
226 /* More than one quadword per predicate. */
231 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
233 if (j
* 4 + 4 <= zcr_len
+ 1) {
236 digits
= (zcr_len
% 4 + 1) * 4;
238 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
239 env
->vfp
.pregs
[i
].p
[j
],
240 j
? ":" : eol
? "\n" : " ");
244 for (i
= 0; i
< 32; i
++) {
246 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
247 i
, env
->vfp
.zregs
[i
].d
[1],
248 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
249 } else if (zcr_len
== 1) {
250 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
251 ":%016" PRIx64
":%016" PRIx64
"\n",
252 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
253 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
255 for (j
= zcr_len
; j
>= 0; j
--) {
256 bool odd
= (zcr_len
- j
) % 2 != 0;
258 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
261 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
263 cpu_fprintf(f
, " [%x]=", j
);
266 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
267 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
268 env
->vfp
.zregs
[i
].d
[j
* 2],
269 odd
|| j
== 0 ? "\n" : ":");
274 for (i
= 0; i
< 32; i
++) {
275 uint64_t *q
= aa64_vfp_qreg(env
, i
);
276 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
277 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
282 void gen_a64_set_pc_im(uint64_t val
)
284 tcg_gen_movi_i64(cpu_pc
, val
);
288 * Handle Top Byte Ignore (TBI) bits.
290 * If address tagging is enabled via the TCR TBI bits:
291 * + for EL2 and EL3 there is only one TBI bit, and if it is set
292 * then the address is zero-extended, clearing bits [63:56]
293 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
294 * and TBI1 controls addressses with bit 55 == 1.
295 * If the appropriate TBI bit is set for the address then
296 * the address is sign-extended from bit 55 into bits [63:56]
298 * Here We have concatenated TBI{1,0} into tbi.
300 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
301 TCGv_i64 src
, int tbi
)
304 /* Load unmodified address */
305 tcg_gen_mov_i64(dst
, src
);
306 } else if (s
->current_el
>= 2) {
307 /* FIXME: ARMv8.1-VHE S2 translation regime. */
308 /* Force tag byte to all zero */
309 tcg_gen_extract_i64(dst
, src
, 0, 56);
311 /* Sign-extend from bit 55. */
312 tcg_gen_sextract_i64(dst
, src
, 0, 56);
315 TCGv_i64 tcg_zero
= tcg_const_i64(0);
318 * The two TBI bits differ.
319 * If tbi0, then !tbi1: only use the extension if positive.
320 * if !tbi0, then tbi1: only use the extension if negative.
322 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
323 dst
, dst
, tcg_zero
, dst
, src
);
324 tcg_temp_free_i64(tcg_zero
);
329 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
332 * If address tagging is enabled for instructions via the TCR TBI bits,
333 * then loading an address into the PC will clear out any tag.
335 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
339 * Return a "clean" address for ADDR according to TBID.
340 * This is always a fresh temporary, as we need to be able to
341 * increment this independently of a dirty write-back address.
343 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
345 TCGv_i64 clean
= new_tmp_a64(s
);
346 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
350 typedef struct DisasCompare64
{
355 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
359 arm_test_cc(&c32
, cc
);
361 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
362 * properly. The NE/EQ comparisons are also fine with this choice. */
363 c64
->cond
= c32
.cond
;
364 c64
->value
= tcg_temp_new_i64();
365 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
370 static void a64_free_cc(DisasCompare64
*c64
)
372 tcg_temp_free_i64(c64
->value
);
375 static void gen_exception_internal(int excp
)
377 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
379 assert(excp_is_internal(excp
));
380 gen_helper_exception_internal(cpu_env
, tcg_excp
);
381 tcg_temp_free_i32(tcg_excp
);
384 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
386 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
387 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
388 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
390 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
392 tcg_temp_free_i32(tcg_el
);
393 tcg_temp_free_i32(tcg_syn
);
394 tcg_temp_free_i32(tcg_excp
);
397 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
399 gen_a64_set_pc_im(s
->pc
- offset
);
400 gen_exception_internal(excp
);
401 s
->base
.is_jmp
= DISAS_NORETURN
;
404 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
405 uint32_t syndrome
, uint32_t target_el
)
407 gen_a64_set_pc_im(s
->pc
- offset
);
408 gen_exception(excp
, syndrome
, target_el
);
409 s
->base
.is_jmp
= DISAS_NORETURN
;
412 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
417 gen_a64_set_pc_im(s
->pc
- offset
);
418 tcg_syn
= tcg_const_i32(syndrome
);
419 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
420 tcg_temp_free_i32(tcg_syn
);
421 s
->base
.is_jmp
= DISAS_NORETURN
;
424 static void gen_ss_advance(DisasContext
*s
)
426 /* If the singlestep state is Active-not-pending, advance to
431 gen_helper_clear_pstate_ss(cpu_env
);
435 static void gen_step_complete_exception(DisasContext
*s
)
437 /* We just completed step of an insn. Move from Active-not-pending
438 * to Active-pending, and then also take the swstep exception.
439 * This corresponds to making the (IMPDEF) choice to prioritize
440 * swstep exceptions over asynchronous exceptions taken to an exception
441 * level where debug is disabled. This choice has the advantage that
442 * we do not need to maintain internal state corresponding to the
443 * ISV/EX syndrome bits between completion of the step and generation
444 * of the exception, and our syndrome information is always correct.
447 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
448 default_exception_el(s
));
449 s
->base
.is_jmp
= DISAS_NORETURN
;
452 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
454 /* No direct tb linking with singlestep (either QEMU's or the ARM
455 * debug architecture kind) or deterministic io
457 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
458 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
462 #ifndef CONFIG_USER_ONLY
463 /* Only link tbs from inside the same guest page */
464 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
472 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
474 TranslationBlock
*tb
;
477 if (use_goto_tb(s
, n
, dest
)) {
479 gen_a64_set_pc_im(dest
);
480 tcg_gen_exit_tb(tb
, n
);
481 s
->base
.is_jmp
= DISAS_NORETURN
;
483 gen_a64_set_pc_im(dest
);
485 gen_step_complete_exception(s
);
486 } else if (s
->base
.singlestep_enabled
) {
487 gen_exception_internal(EXCP_DEBUG
);
489 tcg_gen_lookup_and_goto_ptr();
490 s
->base
.is_jmp
= DISAS_NORETURN
;
495 void unallocated_encoding(DisasContext
*s
)
497 /* Unallocated and reserved encodings are uncategorized */
498 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
499 default_exception_el(s
));
502 static void init_tmp_a64_array(DisasContext
*s
)
504 #ifdef CONFIG_DEBUG_TCG
505 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
507 s
->tmp_a64_count
= 0;
510 static void free_tmp_a64(DisasContext
*s
)
513 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
514 tcg_temp_free_i64(s
->tmp_a64
[i
]);
516 init_tmp_a64_array(s
);
519 TCGv_i64
new_tmp_a64(DisasContext
*s
)
521 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
522 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
525 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
527 TCGv_i64 t
= new_tmp_a64(s
);
528 tcg_gen_movi_i64(t
, 0);
533 * Register access functions
535 * These functions are used for directly accessing a register in where
536 * changes to the final register value are likely to be made. If you
537 * need to use a register for temporary calculation (e.g. index type
538 * operations) use the read_* form.
540 * B1.2.1 Register mappings
542 * In instruction register encoding 31 can refer to ZR (zero register) or
543 * the SP (stack pointer) depending on context. In QEMU's case we map SP
544 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
545 * This is the point of the _sp forms.
547 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
550 return new_tmp_a64_zero(s
);
556 /* register access for when 31 == SP */
557 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
562 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
563 * representing the register contents. This TCGv is an auto-freed
564 * temporary so it need not be explicitly freed, and may be modified.
566 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
568 TCGv_i64 v
= new_tmp_a64(s
);
571 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
573 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
576 tcg_gen_movi_i64(v
, 0);
581 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
583 TCGv_i64 v
= new_tmp_a64(s
);
585 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
587 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
592 /* Return the offset into CPUARMState of a slice (from
593 * the least significant end) of FP register Qn (ie
595 * (Note that this is not the same mapping as for A32; see cpu.h)
597 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
599 return vec_reg_offset(s
, regno
, 0, size
);
602 /* Offset of the high half of the 128 bit vector Qn */
603 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
605 return vec_reg_offset(s
, regno
, 1, MO_64
);
608 /* Convenience accessors for reading and writing single and double
609 * FP registers. Writing clears the upper parts of the associated
610 * 128 bit vector register, as required by the architecture.
611 * Note that unlike the GP register accessors, the values returned
612 * by the read functions must be manually freed.
614 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
616 TCGv_i64 v
= tcg_temp_new_i64();
618 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
622 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
624 TCGv_i32 v
= tcg_temp_new_i32();
626 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
630 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
632 TCGv_i32 v
= tcg_temp_new_i32();
634 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
638 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
639 * If SVE is not enabled, then there are only 128 bits in the vector.
641 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
643 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
644 unsigned vsz
= vec_full_reg_size(s
);
647 TCGv_i64 tcg_zero
= tcg_const_i64(0);
648 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
649 tcg_temp_free_i64(tcg_zero
);
652 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
656 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
658 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
660 tcg_gen_st_i64(v
, cpu_env
, ofs
);
661 clear_vec_high(s
, false, reg
);
664 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
666 TCGv_i64 tmp
= tcg_temp_new_i64();
668 tcg_gen_extu_i32_i64(tmp
, v
);
669 write_fp_dreg(s
, reg
, tmp
);
670 tcg_temp_free_i64(tmp
);
673 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
675 TCGv_ptr statusptr
= tcg_temp_new_ptr();
678 /* In A64 all instructions (both FP and Neon) use the FPCR; there
679 * is no equivalent of the A32 Neon "standard FPSCR value".
680 * However half-precision operations operate under a different
681 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
684 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
686 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
688 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
692 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
693 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
694 GVecGen2Fn
*gvec_fn
, int vece
)
696 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
697 is_q
? 16 : 8, vec_full_reg_size(s
));
700 /* Expand a 2-operand + immediate AdvSIMD vector operation using
701 * an expander function.
703 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
704 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
706 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
707 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
710 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
711 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
712 GVecGen3Fn
*gvec_fn
, int vece
)
714 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
715 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
718 /* Expand a 2-operand + immediate AdvSIMD vector operation using
721 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
722 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
724 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
725 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
728 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
729 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
730 int rn
, int rm
, const GVecGen3
*gvec_op
)
732 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
733 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
734 vec_full_reg_size(s
), gvec_op
);
737 /* Expand a 3-operand operation using an out-of-line helper. */
738 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
739 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
741 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
742 vec_full_reg_offset(s
, rn
),
743 vec_full_reg_offset(s
, rm
),
744 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
747 /* Expand a 3-operand + env pointer operation using
748 * an out-of-line helper.
750 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
751 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
753 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
754 vec_full_reg_offset(s
, rn
),
755 vec_full_reg_offset(s
, rm
), cpu_env
,
756 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
759 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
760 * an out-of-line helper.
762 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
763 int rm
, bool is_fp16
, int data
,
764 gen_helper_gvec_3_ptr
*fn
)
766 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
767 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
768 vec_full_reg_offset(s
, rn
),
769 vec_full_reg_offset(s
, rm
), fpst
,
770 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
771 tcg_temp_free_ptr(fpst
);
774 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
775 * than the 32 bit equivalent.
777 static inline void gen_set_NZ64(TCGv_i64 result
)
779 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
780 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
783 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
784 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
787 gen_set_NZ64(result
);
789 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
790 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
792 tcg_gen_movi_i32(cpu_CF
, 0);
793 tcg_gen_movi_i32(cpu_VF
, 0);
796 /* dest = T0 + T1; compute C, N, V and Z flags */
797 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
800 TCGv_i64 result
, flag
, tmp
;
801 result
= tcg_temp_new_i64();
802 flag
= tcg_temp_new_i64();
803 tmp
= tcg_temp_new_i64();
805 tcg_gen_movi_i64(tmp
, 0);
806 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
808 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
810 gen_set_NZ64(result
);
812 tcg_gen_xor_i64(flag
, result
, t0
);
813 tcg_gen_xor_i64(tmp
, t0
, t1
);
814 tcg_gen_andc_i64(flag
, flag
, tmp
);
815 tcg_temp_free_i64(tmp
);
816 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
818 tcg_gen_mov_i64(dest
, result
);
819 tcg_temp_free_i64(result
);
820 tcg_temp_free_i64(flag
);
822 /* 32 bit arithmetic */
823 TCGv_i32 t0_32
= tcg_temp_new_i32();
824 TCGv_i32 t1_32
= tcg_temp_new_i32();
825 TCGv_i32 tmp
= tcg_temp_new_i32();
827 tcg_gen_movi_i32(tmp
, 0);
828 tcg_gen_extrl_i64_i32(t0_32
, t0
);
829 tcg_gen_extrl_i64_i32(t1_32
, t1
);
830 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
831 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
832 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
833 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
834 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
835 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
837 tcg_temp_free_i32(tmp
);
838 tcg_temp_free_i32(t0_32
);
839 tcg_temp_free_i32(t1_32
);
843 /* dest = T0 - T1; compute C, N, V and Z flags */
844 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
847 /* 64 bit arithmetic */
848 TCGv_i64 result
, flag
, tmp
;
850 result
= tcg_temp_new_i64();
851 flag
= tcg_temp_new_i64();
852 tcg_gen_sub_i64(result
, t0
, t1
);
854 gen_set_NZ64(result
);
856 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
857 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
859 tcg_gen_xor_i64(flag
, result
, t0
);
860 tmp
= tcg_temp_new_i64();
861 tcg_gen_xor_i64(tmp
, t0
, t1
);
862 tcg_gen_and_i64(flag
, flag
, tmp
);
863 tcg_temp_free_i64(tmp
);
864 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
865 tcg_gen_mov_i64(dest
, result
);
866 tcg_temp_free_i64(flag
);
867 tcg_temp_free_i64(result
);
869 /* 32 bit arithmetic */
870 TCGv_i32 t0_32
= tcg_temp_new_i32();
871 TCGv_i32 t1_32
= tcg_temp_new_i32();
874 tcg_gen_extrl_i64_i32(t0_32
, t0
);
875 tcg_gen_extrl_i64_i32(t1_32
, t1
);
876 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
877 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
878 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
879 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
880 tmp
= tcg_temp_new_i32();
881 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
882 tcg_temp_free_i32(t0_32
);
883 tcg_temp_free_i32(t1_32
);
884 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
885 tcg_temp_free_i32(tmp
);
886 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
890 /* dest = T0 + T1 + CF; do not compute flags. */
891 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
893 TCGv_i64 flag
= tcg_temp_new_i64();
894 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
895 tcg_gen_add_i64(dest
, t0
, t1
);
896 tcg_gen_add_i64(dest
, dest
, flag
);
897 tcg_temp_free_i64(flag
);
900 tcg_gen_ext32u_i64(dest
, dest
);
904 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
905 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
908 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
909 result
= tcg_temp_new_i64();
910 cf_64
= tcg_temp_new_i64();
911 vf_64
= tcg_temp_new_i64();
912 tmp
= tcg_const_i64(0);
914 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
915 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
916 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
917 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
918 gen_set_NZ64(result
);
920 tcg_gen_xor_i64(vf_64
, result
, t0
);
921 tcg_gen_xor_i64(tmp
, t0
, t1
);
922 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
923 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
925 tcg_gen_mov_i64(dest
, result
);
927 tcg_temp_free_i64(tmp
);
928 tcg_temp_free_i64(vf_64
);
929 tcg_temp_free_i64(cf_64
);
930 tcg_temp_free_i64(result
);
932 TCGv_i32 t0_32
, t1_32
, tmp
;
933 t0_32
= tcg_temp_new_i32();
934 t1_32
= tcg_temp_new_i32();
935 tmp
= tcg_const_i32(0);
937 tcg_gen_extrl_i64_i32(t0_32
, t0
);
938 tcg_gen_extrl_i64_i32(t1_32
, t1
);
939 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
940 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
942 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
943 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
944 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
945 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
946 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
948 tcg_temp_free_i32(tmp
);
949 tcg_temp_free_i32(t1_32
);
950 tcg_temp_free_i32(t0_32
);
955 * Load/Store generators
959 * Store from GPR register to memory.
961 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
962 TCGv_i64 tcg_addr
, int size
, int memidx
,
964 unsigned int iss_srt
,
965 bool iss_sf
, bool iss_ar
)
968 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
973 syn
= syn_data_abort_with_iss(0,
979 0, 0, 0, 0, 0, false);
980 disas_set_insn_syndrome(s
, syn
);
984 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
985 TCGv_i64 tcg_addr
, int size
,
987 unsigned int iss_srt
,
988 bool iss_sf
, bool iss_ar
)
990 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
991 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
995 * Load from memory to GPR register
997 static void do_gpr_ld_memidx(DisasContext
*s
,
998 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
999 int size
, bool is_signed
,
1000 bool extend
, int memidx
,
1001 bool iss_valid
, unsigned int iss_srt
,
1002 bool iss_sf
, bool iss_ar
)
1004 TCGMemOp memop
= s
->be_data
+ size
;
1006 g_assert(size
<= 3);
1012 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
1014 if (extend
&& is_signed
) {
1016 tcg_gen_ext32u_i64(dest
, dest
);
1022 syn
= syn_data_abort_with_iss(0,
1028 0, 0, 0, 0, 0, false);
1029 disas_set_insn_syndrome(s
, syn
);
1033 static void do_gpr_ld(DisasContext
*s
,
1034 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1035 int size
, bool is_signed
, bool extend
,
1036 bool iss_valid
, unsigned int iss_srt
,
1037 bool iss_sf
, bool iss_ar
)
1039 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1041 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1045 * Store from FP register to memory
1047 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1049 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1050 TCGv_i64 tmp
= tcg_temp_new_i64();
1051 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1053 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1056 bool be
= s
->be_data
== MO_BE
;
1057 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1059 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1060 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1062 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1063 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1065 tcg_temp_free_i64(tcg_hiaddr
);
1068 tcg_temp_free_i64(tmp
);
1072 * Load from memory to FP register
1074 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1076 /* This always zero-extends and writes to a full 128 bit wide vector */
1077 TCGv_i64 tmplo
= tcg_temp_new_i64();
1081 TCGMemOp memop
= s
->be_data
+ size
;
1082 tmphi
= tcg_const_i64(0);
1083 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1085 bool be
= s
->be_data
== MO_BE
;
1086 TCGv_i64 tcg_hiaddr
;
1088 tmphi
= tcg_temp_new_i64();
1089 tcg_hiaddr
= tcg_temp_new_i64();
1091 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1092 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1094 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1096 tcg_temp_free_i64(tcg_hiaddr
);
1099 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1100 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1102 tcg_temp_free_i64(tmplo
);
1103 tcg_temp_free_i64(tmphi
);
1105 clear_vec_high(s
, true, destidx
);
1109 * Vector load/store helpers.
1111 * The principal difference between this and a FP load is that we don't
1112 * zero extend as we are filling a partial chunk of the vector register.
1113 * These functions don't support 128 bit loads/stores, which would be
1114 * normal load/store operations.
1116 * The _i32 versions are useful when operating on 32 bit quantities
1117 * (eg for floating point single or using Neon helper functions).
1120 /* Get value of an element within a vector register */
1121 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1122 int element
, TCGMemOp memop
)
1124 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1127 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1130 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1133 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1136 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1139 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1142 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1146 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1149 g_assert_not_reached();
1153 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1154 int element
, TCGMemOp memop
)
1156 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1159 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1162 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1165 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1168 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1172 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1175 g_assert_not_reached();
1179 /* Set value of an element within a vector register */
1180 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1181 int element
, TCGMemOp memop
)
1183 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1186 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1189 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1192 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1195 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1198 g_assert_not_reached();
1202 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1203 int destidx
, int element
, TCGMemOp memop
)
1205 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1208 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1211 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1214 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1217 g_assert_not_reached();
1221 /* Store from vector register to memory */
1222 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1223 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1225 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1227 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1228 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1230 tcg_temp_free_i64(tcg_tmp
);
1233 /* Load from memory to vector register */
1234 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1235 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1237 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1239 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1240 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1242 tcg_temp_free_i64(tcg_tmp
);
1245 /* Check that FP/Neon access is enabled. If it is, return
1246 * true. If not, emit code to generate an appropriate exception,
1247 * and return false; the caller should not emit any code for
1248 * the instruction. Note that this check must happen after all
1249 * unallocated-encoding checks (otherwise the syndrome information
1250 * for the resulting exception will be incorrect).
1252 static inline bool fp_access_check(DisasContext
*s
)
1254 assert(!s
->fp_access_checked
);
1255 s
->fp_access_checked
= true;
1257 if (!s
->fp_excp_el
) {
1261 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1266 /* Check that SVE access is enabled. If it is, return true.
1267 * If not, emit code to generate an appropriate exception and return false.
1269 bool sve_access_check(DisasContext
*s
)
1271 if (s
->sve_excp_el
) {
1272 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1276 return fp_access_check(s
);
1280 * This utility function is for doing register extension with an
1281 * optional shift. You will likely want to pass a temporary for the
1282 * destination register. See DecodeRegExtend() in the ARM ARM.
1284 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1285 int option
, unsigned int shift
)
1287 int extsize
= extract32(option
, 0, 2);
1288 bool is_signed
= extract32(option
, 2, 1);
1293 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1296 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1299 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1302 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1308 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1311 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1314 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1317 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1323 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1327 static inline void gen_check_sp_alignment(DisasContext
*s
)
1329 /* The AArch64 architecture mandates that (if enabled via PSTATE
1330 * or SCTLR bits) there is a check that SP is 16-aligned on every
1331 * SP-relative load or store (with an exception generated if it is not).
1332 * In line with general QEMU practice regarding misaligned accesses,
1333 * we omit these checks for the sake of guest program performance.
1334 * This function is provided as a hook so we can more easily add these
1335 * checks in future (possibly as a "favour catching guest program bugs
1336 * over speed" user selectable option).
1341 * This provides a simple table based table lookup decoder. It is
1342 * intended to be used when the relevant bits for decode are too
1343 * awkwardly placed and switch/if based logic would be confusing and
1344 * deeply nested. Since it's a linear search through the table, tables
1345 * should be kept small.
1347 * It returns the first handler where insn & mask == pattern, or
1348 * NULL if there is no match.
1349 * The table is terminated by an empty mask (i.e. 0)
1351 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1354 const AArch64DecodeTable
*tptr
= table
;
1356 while (tptr
->mask
) {
1357 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1358 return tptr
->disas_fn
;
1366 * The instruction disassembly implemented here matches
1367 * the instruction encoding classifications in chapter C4
1368 * of the ARM Architecture Reference Manual (DDI0487B_a);
1369 * classification names and decode diagrams here should generally
1370 * match up with those in the manual.
1373 /* Unconditional branch (immediate)
1375 * +----+-----------+-------------------------------------+
1376 * | op | 0 0 1 0 1 | imm26 |
1377 * +----+-----------+-------------------------------------+
1379 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1381 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1383 if (insn
& (1U << 31)) {
1384 /* BL Branch with link */
1385 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1388 /* B Branch / BL Branch with link */
1390 gen_goto_tb(s
, 0, addr
);
1393 /* Compare and branch (immediate)
1394 * 31 30 25 24 23 5 4 0
1395 * +----+-------------+----+---------------------+--------+
1396 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1397 * +----+-------------+----+---------------------+--------+
1399 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1401 unsigned int sf
, op
, rt
;
1403 TCGLabel
*label_match
;
1406 sf
= extract32(insn
, 31, 1);
1407 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1408 rt
= extract32(insn
, 0, 5);
1409 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1411 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1412 label_match
= gen_new_label();
1415 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1416 tcg_cmp
, 0, label_match
);
1418 gen_goto_tb(s
, 0, s
->pc
);
1419 gen_set_label(label_match
);
1420 gen_goto_tb(s
, 1, addr
);
1423 /* Test and branch (immediate)
1424 * 31 30 25 24 23 19 18 5 4 0
1425 * +----+-------------+----+-------+-------------+------+
1426 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1427 * +----+-------------+----+-------+-------------+------+
1429 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1431 unsigned int bit_pos
, op
, rt
;
1433 TCGLabel
*label_match
;
1436 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1437 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1438 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1439 rt
= extract32(insn
, 0, 5);
1441 tcg_cmp
= tcg_temp_new_i64();
1442 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1443 label_match
= gen_new_label();
1446 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1447 tcg_cmp
, 0, label_match
);
1448 tcg_temp_free_i64(tcg_cmp
);
1449 gen_goto_tb(s
, 0, s
->pc
);
1450 gen_set_label(label_match
);
1451 gen_goto_tb(s
, 1, addr
);
1454 /* Conditional branch (immediate)
1455 * 31 25 24 23 5 4 3 0
1456 * +---------------+----+---------------------+----+------+
1457 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1458 * +---------------+----+---------------------+----+------+
1460 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1465 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1466 unallocated_encoding(s
);
1469 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1470 cond
= extract32(insn
, 0, 4);
1474 /* genuinely conditional branches */
1475 TCGLabel
*label_match
= gen_new_label();
1476 arm_gen_test_cc(cond
, label_match
);
1477 gen_goto_tb(s
, 0, s
->pc
);
1478 gen_set_label(label_match
);
1479 gen_goto_tb(s
, 1, addr
);
1481 /* 0xe and 0xf are both "always" conditions */
1482 gen_goto_tb(s
, 0, addr
);
1486 /* HINT instruction group, including various allocated HINTs */
1487 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1488 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1490 unsigned int selector
= crm
<< 3 | op2
;
1493 unallocated_encoding(s
);
1498 case 0b00000: /* NOP */
1500 case 0b00011: /* WFI */
1501 s
->base
.is_jmp
= DISAS_WFI
;
1503 case 0b00001: /* YIELD */
1504 /* When running in MTTCG we don't generate jumps to the yield and
1505 * WFE helpers as it won't affect the scheduling of other vCPUs.
1506 * If we wanted to more completely model WFE/SEV so we don't busy
1507 * spin unnecessarily we would need to do something more involved.
1509 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1510 s
->base
.is_jmp
= DISAS_YIELD
;
1513 case 0b00010: /* WFE */
1514 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1515 s
->base
.is_jmp
= DISAS_WFE
;
1518 case 0b00100: /* SEV */
1519 case 0b00101: /* SEVL */
1520 /* we treat all as NOP at least for now */
1522 case 0b00111: /* XPACLRI */
1523 if (s
->pauth_active
) {
1524 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1527 case 0b01000: /* PACIA1716 */
1528 if (s
->pauth_active
) {
1529 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1532 case 0b01010: /* PACIB1716 */
1533 if (s
->pauth_active
) {
1534 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1537 case 0b01100: /* AUTIA1716 */
1538 if (s
->pauth_active
) {
1539 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1542 case 0b01110: /* AUTIB1716 */
1543 if (s
->pauth_active
) {
1544 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1547 case 0b11000: /* PACIAZ */
1548 if (s
->pauth_active
) {
1549 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1550 new_tmp_a64_zero(s
));
1553 case 0b11001: /* PACIASP */
1554 if (s
->pauth_active
) {
1555 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1558 case 0b11010: /* PACIBZ */
1559 if (s
->pauth_active
) {
1560 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1561 new_tmp_a64_zero(s
));
1564 case 0b11011: /* PACIBSP */
1565 if (s
->pauth_active
) {
1566 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1569 case 0b11100: /* AUTIAZ */
1570 if (s
->pauth_active
) {
1571 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1572 new_tmp_a64_zero(s
));
1575 case 0b11101: /* AUTIASP */
1576 if (s
->pauth_active
) {
1577 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1580 case 0b11110: /* AUTIBZ */
1581 if (s
->pauth_active
) {
1582 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1583 new_tmp_a64_zero(s
));
1586 case 0b11111: /* AUTIBSP */
1587 if (s
->pauth_active
) {
1588 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1592 /* default specified as NOP equivalent */
1597 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1599 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1602 /* CLREX, DSB, DMB, ISB */
1603 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1604 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1609 unallocated_encoding(s
);
1620 case 1: /* MBReqTypes_Reads */
1621 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1623 case 2: /* MBReqTypes_Writes */
1624 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1626 default: /* MBReqTypes_All */
1627 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1633 /* We need to break the TB after this insn to execute
1634 * a self-modified code correctly and also to take
1635 * any pending interrupts immediately.
1638 gen_goto_tb(s
, 0, s
->pc
);
1641 unallocated_encoding(s
);
1646 /* MSR (immediate) - move immediate to processor state field */
1647 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1648 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1650 int op
= op1
<< 3 | op2
;
1652 case 0x05: /* SPSel */
1653 if (s
->current_el
== 0) {
1654 unallocated_encoding(s
);
1658 case 0x1e: /* DAIFSet */
1659 case 0x1f: /* DAIFClear */
1661 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1662 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1663 gen_a64_set_pc_im(s
->pc
- 4);
1664 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1665 tcg_temp_free_i32(tcg_imm
);
1666 tcg_temp_free_i32(tcg_op
);
1667 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1668 gen_a64_set_pc_im(s
->pc
);
1669 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1673 unallocated_encoding(s
);
1678 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1680 TCGv_i32 tmp
= tcg_temp_new_i32();
1681 TCGv_i32 nzcv
= tcg_temp_new_i32();
1683 /* build bit 31, N */
1684 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1685 /* build bit 30, Z */
1686 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1687 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1688 /* build bit 29, C */
1689 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1690 /* build bit 28, V */
1691 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1692 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1693 /* generate result */
1694 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1696 tcg_temp_free_i32(nzcv
);
1697 tcg_temp_free_i32(tmp
);
1700 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1703 TCGv_i32 nzcv
= tcg_temp_new_i32();
1705 /* take NZCV from R[t] */
1706 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1709 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1711 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1712 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1714 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1715 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1717 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1718 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1719 tcg_temp_free_i32(nzcv
);
1722 /* MRS - move from system register
1723 * MSR (register) - move to system register
1726 * These are all essentially the same insn in 'read' and 'write'
1727 * versions, with varying op0 fields.
1729 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1730 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1731 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1733 const ARMCPRegInfo
*ri
;
1736 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1737 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1738 crn
, crm
, op0
, op1
, op2
));
1741 /* Unknown register; this might be a guest error or a QEMU
1742 * unimplemented feature.
1744 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1745 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1746 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1747 unallocated_encoding(s
);
1751 /* Check access permissions */
1752 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1753 unallocated_encoding(s
);
1758 /* Emit code to perform further access permissions checks at
1759 * runtime; this may result in an exception.
1762 TCGv_i32 tcg_syn
, tcg_isread
;
1765 gen_a64_set_pc_im(s
->pc
- 4);
1766 tmpptr
= tcg_const_ptr(ri
);
1767 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1768 tcg_syn
= tcg_const_i32(syndrome
);
1769 tcg_isread
= tcg_const_i32(isread
);
1770 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1771 tcg_temp_free_ptr(tmpptr
);
1772 tcg_temp_free_i32(tcg_syn
);
1773 tcg_temp_free_i32(tcg_isread
);
1776 /* Handle special cases first */
1777 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1781 tcg_rt
= cpu_reg(s
, rt
);
1783 gen_get_nzcv(tcg_rt
);
1785 gen_set_nzcv(tcg_rt
);
1788 case ARM_CP_CURRENTEL
:
1789 /* Reads as current EL value from pstate, which is
1790 * guaranteed to be constant by the tb flags.
1792 tcg_rt
= cpu_reg(s
, rt
);
1793 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1796 /* Writes clear the aligned block of memory which rt points into. */
1797 tcg_rt
= cpu_reg(s
, rt
);
1798 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1803 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1805 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1809 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1813 tcg_rt
= cpu_reg(s
, rt
);
1816 if (ri
->type
& ARM_CP_CONST
) {
1817 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1818 } else if (ri
->readfn
) {
1820 tmpptr
= tcg_const_ptr(ri
);
1821 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1822 tcg_temp_free_ptr(tmpptr
);
1824 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1827 if (ri
->type
& ARM_CP_CONST
) {
1828 /* If not forbidden by access permissions, treat as WI */
1830 } else if (ri
->writefn
) {
1832 tmpptr
= tcg_const_ptr(ri
);
1833 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1834 tcg_temp_free_ptr(tmpptr
);
1836 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1840 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1841 /* I/O operations must end the TB here (whether read or write) */
1843 s
->base
.is_jmp
= DISAS_UPDATE
;
1844 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1845 /* We default to ending the TB on a coprocessor register write,
1846 * but allow this to be suppressed by the register definition
1847 * (usually only necessary to work around guest bugs).
1849 s
->base
.is_jmp
= DISAS_UPDATE
;
1854 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1855 * +---------------------+---+-----+-----+-------+-------+-----+------+
1856 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1857 * +---------------------+---+-----+-----+-------+-------+-----+------+
1859 static void disas_system(DisasContext
*s
, uint32_t insn
)
1861 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1862 l
= extract32(insn
, 21, 1);
1863 op0
= extract32(insn
, 19, 2);
1864 op1
= extract32(insn
, 16, 3);
1865 crn
= extract32(insn
, 12, 4);
1866 crm
= extract32(insn
, 8, 4);
1867 op2
= extract32(insn
, 5, 3);
1868 rt
= extract32(insn
, 0, 5);
1871 if (l
|| rt
!= 31) {
1872 unallocated_encoding(s
);
1876 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1877 handle_hint(s
, insn
, op1
, op2
, crm
);
1879 case 3: /* CLREX, DSB, DMB, ISB */
1880 handle_sync(s
, insn
, op1
, op2
, crm
);
1882 case 4: /* MSR (immediate) */
1883 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1886 unallocated_encoding(s
);
1891 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1894 /* Exception generation
1896 * 31 24 23 21 20 5 4 2 1 0
1897 * +-----------------+-----+------------------------+-----+----+
1898 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1899 * +-----------------------+------------------------+----------+
1901 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1903 int opc
= extract32(insn
, 21, 3);
1904 int op2_ll
= extract32(insn
, 0, 5);
1905 int imm16
= extract32(insn
, 5, 16);
1910 /* For SVC, HVC and SMC we advance the single-step state
1911 * machine before taking the exception. This is architecturally
1912 * mandated, to ensure that single-stepping a system call
1913 * instruction works properly.
1918 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1919 default_exception_el(s
));
1922 if (s
->current_el
== 0) {
1923 unallocated_encoding(s
);
1926 /* The pre HVC helper handles cases when HVC gets trapped
1927 * as an undefined insn by runtime configuration.
1929 gen_a64_set_pc_im(s
->pc
- 4);
1930 gen_helper_pre_hvc(cpu_env
);
1932 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1935 if (s
->current_el
== 0) {
1936 unallocated_encoding(s
);
1939 gen_a64_set_pc_im(s
->pc
- 4);
1940 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1941 gen_helper_pre_smc(cpu_env
, tmp
);
1942 tcg_temp_free_i32(tmp
);
1944 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1947 unallocated_encoding(s
);
1953 unallocated_encoding(s
);
1957 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1961 unallocated_encoding(s
);
1964 /* HLT. This has two purposes.
1965 * Architecturally, it is an external halting debug instruction.
1966 * Since QEMU doesn't implement external debug, we treat this as
1967 * it is required for halting debug disabled: it will UNDEF.
1968 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1970 if (semihosting_enabled() && imm16
== 0xf000) {
1971 #ifndef CONFIG_USER_ONLY
1972 /* In system mode, don't allow userspace access to semihosting,
1973 * to provide some semblance of security (and for consistency
1974 * with our 32-bit semihosting).
1976 if (s
->current_el
== 0) {
1977 unsupported_encoding(s
, insn
);
1981 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1983 unsupported_encoding(s
, insn
);
1987 if (op2_ll
< 1 || op2_ll
> 3) {
1988 unallocated_encoding(s
);
1991 /* DCPS1, DCPS2, DCPS3 */
1992 unsupported_encoding(s
, insn
);
1995 unallocated_encoding(s
);
2000 /* Unconditional branch (register)
2001 * 31 25 24 21 20 16 15 10 9 5 4 0
2002 * +---------------+-------+-------+-------+------+-------+
2003 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2004 * +---------------+-------+-------+-------+------+-------+
2006 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2008 unsigned int opc
, op2
, op3
, rn
, op4
;
2009 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2013 opc
= extract32(insn
, 21, 4);
2014 op2
= extract32(insn
, 16, 5);
2015 op3
= extract32(insn
, 10, 6);
2016 rn
= extract32(insn
, 5, 5);
2017 op4
= extract32(insn
, 0, 5);
2020 goto do_unallocated
;
2032 goto do_unallocated
;
2034 dst
= cpu_reg(s
, rn
);
2039 if (!dc_isar_feature(aa64_pauth
, s
)) {
2040 goto do_unallocated
;
2044 if (rn
!= 0x1f || op4
!= 0x1f) {
2045 goto do_unallocated
;
2048 modifier
= cpu_X
[31];
2050 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2052 goto do_unallocated
;
2054 modifier
= new_tmp_a64_zero(s
);
2056 if (s
->pauth_active
) {
2057 dst
= new_tmp_a64(s
);
2059 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2061 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2064 dst
= cpu_reg(s
, rn
);
2069 goto do_unallocated
;
2071 gen_a64_set_pc(s
, dst
);
2072 /* BLR also needs to load return address */
2074 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2080 if (!dc_isar_feature(aa64_pauth
, s
)) {
2081 goto do_unallocated
;
2083 if ((op3
& ~1) != 2) {
2084 goto do_unallocated
;
2086 btype_mod
= opc
& 1;
2087 if (s
->pauth_active
) {
2088 dst
= new_tmp_a64(s
);
2089 modifier
= cpu_reg_sp(s
, op4
);
2091 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2093 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2096 dst
= cpu_reg(s
, rn
);
2098 gen_a64_set_pc(s
, dst
);
2099 /* BLRAA also needs to load return address */
2101 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2106 if (s
->current_el
== 0) {
2107 goto do_unallocated
;
2112 goto do_unallocated
;
2114 dst
= tcg_temp_new_i64();
2115 tcg_gen_ld_i64(dst
, cpu_env
,
2116 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2119 case 2: /* ERETAA */
2120 case 3: /* ERETAB */
2121 if (!dc_isar_feature(aa64_pauth
, s
)) {
2122 goto do_unallocated
;
2124 if (rn
!= 0x1f || op4
!= 0x1f) {
2125 goto do_unallocated
;
2127 dst
= tcg_temp_new_i64();
2128 tcg_gen_ld_i64(dst
, cpu_env
,
2129 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2130 if (s
->pauth_active
) {
2131 modifier
= cpu_X
[31];
2133 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2135 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2141 goto do_unallocated
;
2143 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2147 gen_helper_exception_return(cpu_env
, dst
);
2148 tcg_temp_free_i64(dst
);
2149 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2152 /* Must exit loop to check un-masked IRQs */
2153 s
->base
.is_jmp
= DISAS_EXIT
;
2157 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2158 goto do_unallocated
;
2160 unsupported_encoding(s
, insn
);
2166 unallocated_encoding(s
);
2170 switch (btype_mod
) {
2172 if (dc_isar_feature(aa64_bti
, s
)) {
2173 /* BR to {x16,x17} or !guard -> 1, else 3. */
2174 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2179 if (dc_isar_feature(aa64_bti
, s
)) {
2180 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2185 default: /* RET or none of the above. */
2186 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2190 s
->base
.is_jmp
= DISAS_JUMP
;
2193 /* Branches, exception generating and system instructions */
2194 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2196 switch (extract32(insn
, 25, 7)) {
2197 case 0x0a: case 0x0b:
2198 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2199 disas_uncond_b_imm(s
, insn
);
2201 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2202 disas_comp_b_imm(s
, insn
);
2204 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2205 disas_test_b_imm(s
, insn
);
2207 case 0x2a: /* Conditional branch (immediate) */
2208 disas_cond_b_imm(s
, insn
);
2210 case 0x6a: /* Exception generation / System */
2211 if (insn
& (1 << 24)) {
2212 if (extract32(insn
, 22, 2) == 0) {
2213 disas_system(s
, insn
);
2215 unallocated_encoding(s
);
2221 case 0x6b: /* Unconditional branch (register) */
2222 disas_uncond_b_reg(s
, insn
);
2225 unallocated_encoding(s
);
2231 * Load/Store exclusive instructions are implemented by remembering
2232 * the value/address loaded, and seeing if these are the same
2233 * when the store is performed. This is not actually the architecturally
2234 * mandated semantics, but it works for typical guest code sequences
2235 * and avoids having to monitor regular stores.
2237 * The store exclusive uses the atomic cmpxchg primitives to avoid
2238 * races in multi-threaded linux-user and when MTTCG softmmu is
2241 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2242 TCGv_i64 addr
, int size
, bool is_pair
)
2244 int idx
= get_mem_index(s
);
2245 TCGMemOp memop
= s
->be_data
;
2247 g_assert(size
<= 3);
2249 g_assert(size
>= 2);
2251 /* The pair must be single-copy atomic for the doubleword. */
2252 memop
|= MO_64
| MO_ALIGN
;
2253 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2254 if (s
->be_data
== MO_LE
) {
2255 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2256 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2258 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2259 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2262 /* The pair must be single-copy atomic for *each* doubleword, not
2263 the entire quadword, however it must be quadword aligned. */
2265 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2266 memop
| MO_ALIGN_16
);
2268 TCGv_i64 addr2
= tcg_temp_new_i64();
2269 tcg_gen_addi_i64(addr2
, addr
, 8);
2270 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2271 tcg_temp_free_i64(addr2
);
2273 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2274 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2277 memop
|= size
| MO_ALIGN
;
2278 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2279 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2281 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2284 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2285 TCGv_i64 addr
, int size
, int is_pair
)
2287 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2288 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2291 * [addr + datasize] = {Rt2};
2297 * env->exclusive_addr = -1;
2299 TCGLabel
*fail_label
= gen_new_label();
2300 TCGLabel
*done_label
= gen_new_label();
2303 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2305 tmp
= tcg_temp_new_i64();
2308 if (s
->be_data
== MO_LE
) {
2309 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2311 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2313 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2314 cpu_exclusive_val
, tmp
,
2316 MO_64
| MO_ALIGN
| s
->be_data
);
2317 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2318 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2319 if (!HAVE_CMPXCHG128
) {
2320 gen_helper_exit_atomic(cpu_env
);
2321 s
->base
.is_jmp
= DISAS_NORETURN
;
2322 } else if (s
->be_data
== MO_LE
) {
2323 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2328 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2333 } else if (s
->be_data
== MO_LE
) {
2334 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2335 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2337 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2338 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2341 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2342 cpu_reg(s
, rt
), get_mem_index(s
),
2343 size
| MO_ALIGN
| s
->be_data
);
2344 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2346 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2347 tcg_temp_free_i64(tmp
);
2348 tcg_gen_br(done_label
);
2350 gen_set_label(fail_label
);
2351 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2352 gen_set_label(done_label
);
2353 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2356 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2359 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2360 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2361 int memidx
= get_mem_index(s
);
2362 TCGv_i64 clean_addr
;
2365 gen_check_sp_alignment(s
);
2367 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2368 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2369 size
| MO_ALIGN
| s
->be_data
);
2372 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2375 TCGv_i64 s1
= cpu_reg(s
, rs
);
2376 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2377 TCGv_i64 t1
= cpu_reg(s
, rt
);
2378 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2379 TCGv_i64 clean_addr
;
2380 int memidx
= get_mem_index(s
);
2383 gen_check_sp_alignment(s
);
2385 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2388 TCGv_i64 cmp
= tcg_temp_new_i64();
2389 TCGv_i64 val
= tcg_temp_new_i64();
2391 if (s
->be_data
== MO_LE
) {
2392 tcg_gen_concat32_i64(val
, t1
, t2
);
2393 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2395 tcg_gen_concat32_i64(val
, t2
, t1
);
2396 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2399 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2400 MO_64
| MO_ALIGN
| s
->be_data
);
2401 tcg_temp_free_i64(val
);
2403 if (s
->be_data
== MO_LE
) {
2404 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2406 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2408 tcg_temp_free_i64(cmp
);
2409 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2410 if (HAVE_CMPXCHG128
) {
2411 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2412 if (s
->be_data
== MO_LE
) {
2413 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2414 clean_addr
, t1
, t2
);
2416 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2417 clean_addr
, t1
, t2
);
2419 tcg_temp_free_i32(tcg_rs
);
2421 gen_helper_exit_atomic(cpu_env
);
2422 s
->base
.is_jmp
= DISAS_NORETURN
;
2425 TCGv_i64 d1
= tcg_temp_new_i64();
2426 TCGv_i64 d2
= tcg_temp_new_i64();
2427 TCGv_i64 a2
= tcg_temp_new_i64();
2428 TCGv_i64 c1
= tcg_temp_new_i64();
2429 TCGv_i64 c2
= tcg_temp_new_i64();
2430 TCGv_i64 zero
= tcg_const_i64(0);
2432 /* Load the two words, in memory order. */
2433 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2434 MO_64
| MO_ALIGN_16
| s
->be_data
);
2435 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2436 tcg_gen_qemu_ld_i64(d2
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2438 /* Compare the two words, also in memory order. */
2439 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2440 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2441 tcg_gen_and_i64(c2
, c2
, c1
);
2443 /* If compare equal, write back new data, else write back old data. */
2444 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2445 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2446 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2447 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2448 tcg_temp_free_i64(a2
);
2449 tcg_temp_free_i64(c1
);
2450 tcg_temp_free_i64(c2
);
2451 tcg_temp_free_i64(zero
);
2453 /* Write back the data from memory to Rs. */
2454 tcg_gen_mov_i64(s1
, d1
);
2455 tcg_gen_mov_i64(s2
, d2
);
2456 tcg_temp_free_i64(d1
);
2457 tcg_temp_free_i64(d2
);
2461 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2462 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2464 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2466 int opc0
= extract32(opc
, 0, 1);
2470 regsize
= opc0
? 32 : 64;
2472 regsize
= size
== 3 ? 64 : 32;
2474 return regsize
== 64;
2477 /* Load/store exclusive
2479 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2480 * +-----+-------------+----+---+----+------+----+-------+------+------+
2481 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2482 * +-----+-------------+----+---+----+------+----+-------+------+------+
2484 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2485 * L: 0 -> store, 1 -> load
2486 * o2: 0 -> exclusive, 1 -> not
2487 * o1: 0 -> single register, 1 -> register pair
2488 * o0: 1 -> load-acquire/store-release, 0 -> not
2490 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2492 int rt
= extract32(insn
, 0, 5);
2493 int rn
= extract32(insn
, 5, 5);
2494 int rt2
= extract32(insn
, 10, 5);
2495 int rs
= extract32(insn
, 16, 5);
2496 int is_lasr
= extract32(insn
, 15, 1);
2497 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2498 int size
= extract32(insn
, 30, 2);
2499 TCGv_i64 clean_addr
;
2501 switch (o2_L_o1_o0
) {
2502 case 0x0: /* STXR */
2503 case 0x1: /* STLXR */
2505 gen_check_sp_alignment(s
);
2508 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2510 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2511 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2514 case 0x4: /* LDXR */
2515 case 0x5: /* LDAXR */
2517 gen_check_sp_alignment(s
);
2519 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2521 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2523 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2527 case 0x8: /* STLLR */
2528 if (!dc_isar_feature(aa64_lor
, s
)) {
2531 /* StoreLORelease is the same as Store-Release for QEMU. */
2533 case 0x9: /* STLR */
2534 /* Generate ISS for non-exclusive accesses including LASR. */
2536 gen_check_sp_alignment(s
);
2538 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2539 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2540 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2541 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2544 case 0xc: /* LDLAR */
2545 if (!dc_isar_feature(aa64_lor
, s
)) {
2548 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2550 case 0xd: /* LDAR */
2551 /* Generate ISS for non-exclusive accesses including LASR. */
2553 gen_check_sp_alignment(s
);
2555 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2556 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2557 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2558 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2561 case 0x2: case 0x3: /* CASP / STXP */
2562 if (size
& 2) { /* STXP / STLXP */
2564 gen_check_sp_alignment(s
);
2567 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2569 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2570 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2574 && ((rt
| rs
) & 1) == 0
2575 && dc_isar_feature(aa64_atomics
, s
)) {
2577 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2582 case 0x6: case 0x7: /* CASPA / LDXP */
2583 if (size
& 2) { /* LDXP / LDAXP */
2585 gen_check_sp_alignment(s
);
2587 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2589 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2591 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2596 && ((rt
| rs
) & 1) == 0
2597 && dc_isar_feature(aa64_atomics
, s
)) {
2598 /* CASPA / CASPAL */
2599 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2605 case 0xb: /* CASL */
2606 case 0xe: /* CASA */
2607 case 0xf: /* CASAL */
2608 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2609 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2614 unallocated_encoding(s
);
2618 * Load register (literal)
2620 * 31 30 29 27 26 25 24 23 5 4 0
2621 * +-----+-------+---+-----+-------------------+-------+
2622 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2623 * +-----+-------+---+-----+-------------------+-------+
2625 * V: 1 -> vector (simd/fp)
2626 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2627 * 10-> 32 bit signed, 11 -> prefetch
2628 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2630 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2632 int rt
= extract32(insn
, 0, 5);
2633 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2634 bool is_vector
= extract32(insn
, 26, 1);
2635 int opc
= extract32(insn
, 30, 2);
2636 bool is_signed
= false;
2638 TCGv_i64 tcg_rt
, clean_addr
;
2642 unallocated_encoding(s
);
2646 if (!fp_access_check(s
)) {
2651 /* PRFM (literal) : prefetch */
2654 size
= 2 + extract32(opc
, 0, 1);
2655 is_signed
= extract32(opc
, 1, 1);
2658 tcg_rt
= cpu_reg(s
, rt
);
2660 clean_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2662 do_fp_ld(s
, rt
, clean_addr
, size
);
2664 /* Only unsigned 32bit loads target 32bit registers. */
2665 bool iss_sf
= opc
!= 0;
2667 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2668 true, rt
, iss_sf
, false);
2670 tcg_temp_free_i64(clean_addr
);
2674 * LDNP (Load Pair - non-temporal hint)
2675 * LDP (Load Pair - non vector)
2676 * LDPSW (Load Pair Signed Word - non vector)
2677 * STNP (Store Pair - non-temporal hint)
2678 * STP (Store Pair - non vector)
2679 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2680 * LDP (Load Pair of SIMD&FP)
2681 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2682 * STP (Store Pair of SIMD&FP)
2684 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2685 * +-----+-------+---+---+-------+---+-----------------------------+
2686 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2687 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2689 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2691 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2692 * V: 0 -> GPR, 1 -> Vector
2693 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2694 * 10 -> signed offset, 11 -> pre-index
2695 * L: 0 -> Store 1 -> Load
2697 * Rt, Rt2 = GPR or SIMD registers to be stored
2698 * Rn = general purpose register containing address
2699 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2701 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2703 int rt
= extract32(insn
, 0, 5);
2704 int rn
= extract32(insn
, 5, 5);
2705 int rt2
= extract32(insn
, 10, 5);
2706 uint64_t offset
= sextract64(insn
, 15, 7);
2707 int index
= extract32(insn
, 23, 2);
2708 bool is_vector
= extract32(insn
, 26, 1);
2709 bool is_load
= extract32(insn
, 22, 1);
2710 int opc
= extract32(insn
, 30, 2);
2712 bool is_signed
= false;
2713 bool postindex
= false;
2716 TCGv_i64 clean_addr
, dirty_addr
;
2721 unallocated_encoding(s
);
2728 size
= 2 + extract32(opc
, 1, 1);
2729 is_signed
= extract32(opc
, 0, 1);
2730 if (!is_load
&& is_signed
) {
2731 unallocated_encoding(s
);
2737 case 1: /* post-index */
2742 /* signed offset with "non-temporal" hint. Since we don't emulate
2743 * caches we don't care about hints to the cache system about
2744 * data access patterns, and handle this identically to plain
2748 /* There is no non-temporal-hint version of LDPSW */
2749 unallocated_encoding(s
);
2754 case 2: /* signed offset, rn not updated */
2757 case 3: /* pre-index */
2763 if (is_vector
&& !fp_access_check(s
)) {
2770 gen_check_sp_alignment(s
);
2773 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2775 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2777 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2781 do_fp_ld(s
, rt
, clean_addr
, size
);
2783 do_fp_st(s
, rt
, clean_addr
, size
);
2785 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2787 do_fp_ld(s
, rt2
, clean_addr
, size
);
2789 do_fp_st(s
, rt2
, clean_addr
, size
);
2792 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2793 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2796 TCGv_i64 tmp
= tcg_temp_new_i64();
2798 /* Do not modify tcg_rt before recognizing any exception
2799 * from the second load.
2801 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2802 false, 0, false, false);
2803 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2804 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2805 false, 0, false, false);
2807 tcg_gen_mov_i64(tcg_rt
, tmp
);
2808 tcg_temp_free_i64(tmp
);
2810 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2811 false, 0, false, false);
2812 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2813 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2814 false, 0, false, false);
2820 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2822 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2827 * Load/store (immediate post-indexed)
2828 * Load/store (immediate pre-indexed)
2829 * Load/store (unscaled immediate)
2831 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2832 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2833 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2834 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2836 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2838 * V = 0 -> non-vector
2839 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2840 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2842 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2848 int rn
= extract32(insn
, 5, 5);
2849 int imm9
= sextract32(insn
, 12, 9);
2850 int idx
= extract32(insn
, 10, 2);
2851 bool is_signed
= false;
2852 bool is_store
= false;
2853 bool is_extended
= false;
2854 bool is_unpriv
= (idx
== 2);
2855 bool iss_valid
= !is_vector
;
2859 TCGv_i64 clean_addr
, dirty_addr
;
2862 size
|= (opc
& 2) << 1;
2863 if (size
> 4 || is_unpriv
) {
2864 unallocated_encoding(s
);
2867 is_store
= ((opc
& 1) == 0);
2868 if (!fp_access_check(s
)) {
2872 if (size
== 3 && opc
== 2) {
2873 /* PRFM - prefetch */
2875 unallocated_encoding(s
);
2880 if (opc
== 3 && size
> 1) {
2881 unallocated_encoding(s
);
2884 is_store
= (opc
== 0);
2885 is_signed
= extract32(opc
, 1, 1);
2886 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2904 g_assert_not_reached();
2908 gen_check_sp_alignment(s
);
2911 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2913 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2915 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2919 do_fp_st(s
, rt
, clean_addr
, size
);
2921 do_fp_ld(s
, rt
, clean_addr
, size
);
2924 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2925 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2926 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2929 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2930 iss_valid
, rt
, iss_sf
, false);
2932 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2933 is_signed
, is_extended
, memidx
,
2934 iss_valid
, rt
, iss_sf
, false);
2939 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2941 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2943 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2948 * Load/store (register offset)
2950 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2951 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2952 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2953 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2956 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2957 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2959 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2960 * opc<0>: 0 -> store, 1 -> load
2961 * V: 1 -> vector/simd
2962 * opt: extend encoding (see DecodeRegExtend)
2963 * S: if S=1 then scale (essentially index by sizeof(size))
2964 * Rt: register to transfer into/out of
2965 * Rn: address register or SP for base
2966 * Rm: offset register or ZR for offset
2968 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2974 int rn
= extract32(insn
, 5, 5);
2975 int shift
= extract32(insn
, 12, 1);
2976 int rm
= extract32(insn
, 16, 5);
2977 int opt
= extract32(insn
, 13, 3);
2978 bool is_signed
= false;
2979 bool is_store
= false;
2980 bool is_extended
= false;
2982 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2984 if (extract32(opt
, 1, 1) == 0) {
2985 unallocated_encoding(s
);
2990 size
|= (opc
& 2) << 1;
2992 unallocated_encoding(s
);
2995 is_store
= !extract32(opc
, 0, 1);
2996 if (!fp_access_check(s
)) {
3000 if (size
== 3 && opc
== 2) {
3001 /* PRFM - prefetch */
3004 if (opc
== 3 && size
> 1) {
3005 unallocated_encoding(s
);
3008 is_store
= (opc
== 0);
3009 is_signed
= extract32(opc
, 1, 1);
3010 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3014 gen_check_sp_alignment(s
);
3016 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3018 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3019 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3021 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3022 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3026 do_fp_st(s
, rt
, clean_addr
, size
);
3028 do_fp_ld(s
, rt
, clean_addr
, size
);
3031 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3032 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3034 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3035 true, rt
, iss_sf
, false);
3037 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3038 is_signed
, is_extended
,
3039 true, rt
, iss_sf
, false);
3045 * Load/store (unsigned immediate)
3047 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3048 * +----+-------+---+-----+-----+------------+-------+------+
3049 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3050 * +----+-------+---+-----+-----+------------+-------+------+
3053 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3054 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3056 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3057 * opc<0>: 0 -> store, 1 -> load
3058 * Rn: base address register (inc SP)
3059 * Rt: target register
3061 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3067 int rn
= extract32(insn
, 5, 5);
3068 unsigned int imm12
= extract32(insn
, 10, 12);
3069 unsigned int offset
;
3071 TCGv_i64 clean_addr
, dirty_addr
;
3074 bool is_signed
= false;
3075 bool is_extended
= false;
3078 size
|= (opc
& 2) << 1;
3080 unallocated_encoding(s
);
3083 is_store
= !extract32(opc
, 0, 1);
3084 if (!fp_access_check(s
)) {
3088 if (size
== 3 && opc
== 2) {
3089 /* PRFM - prefetch */
3092 if (opc
== 3 && size
> 1) {
3093 unallocated_encoding(s
);
3096 is_store
= (opc
== 0);
3097 is_signed
= extract32(opc
, 1, 1);
3098 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3102 gen_check_sp_alignment(s
);
3104 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3105 offset
= imm12
<< size
;
3106 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3107 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3111 do_fp_st(s
, rt
, clean_addr
, size
);
3113 do_fp_ld(s
, rt
, clean_addr
, size
);
3116 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3117 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3119 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3120 true, rt
, iss_sf
, false);
3122 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3123 true, rt
, iss_sf
, false);
3128 /* Atomic memory operations
3130 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3131 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3132 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3133 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3135 * Rt: the result register
3136 * Rn: base address or SP
3137 * Rs: the source register for the operation
3138 * V: vector flag (always 0 as of v8.3)
3142 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3143 int size
, int rt
, bool is_vector
)
3145 int rs
= extract32(insn
, 16, 5);
3146 int rn
= extract32(insn
, 5, 5);
3147 int o3_opc
= extract32(insn
, 12, 4);
3148 TCGv_i64 tcg_rs
, clean_addr
;
3149 AtomicThreeOpFn
*fn
;
3151 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3152 unallocated_encoding(s
);
3156 case 000: /* LDADD */
3157 fn
= tcg_gen_atomic_fetch_add_i64
;
3159 case 001: /* LDCLR */
3160 fn
= tcg_gen_atomic_fetch_and_i64
;
3162 case 002: /* LDEOR */
3163 fn
= tcg_gen_atomic_fetch_xor_i64
;
3165 case 003: /* LDSET */
3166 fn
= tcg_gen_atomic_fetch_or_i64
;
3168 case 004: /* LDSMAX */
3169 fn
= tcg_gen_atomic_fetch_smax_i64
;
3171 case 005: /* LDSMIN */
3172 fn
= tcg_gen_atomic_fetch_smin_i64
;
3174 case 006: /* LDUMAX */
3175 fn
= tcg_gen_atomic_fetch_umax_i64
;
3177 case 007: /* LDUMIN */
3178 fn
= tcg_gen_atomic_fetch_umin_i64
;
3181 fn
= tcg_gen_atomic_xchg_i64
;
3184 unallocated_encoding(s
);
3189 gen_check_sp_alignment(s
);
3191 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3192 tcg_rs
= read_cpu_reg(s
, rs
, true);
3194 if (o3_opc
== 1) { /* LDCLR */
3195 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3198 /* The tcg atomic primitives are all full barriers. Therefore we
3199 * can ignore the Acquire and Release bits of this instruction.
3201 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3202 s
->be_data
| size
| MO_ALIGN
);
3206 * PAC memory operations
3208 * 31 30 27 26 24 22 21 12 11 10 5 0
3209 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3210 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3211 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3213 * Rt: the result register
3214 * Rn: base address or SP
3215 * V: vector flag (always 0 as of v8.3)
3216 * M: clear for key DA, set for key DB
3217 * W: pre-indexing flag
3220 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3221 int size
, int rt
, bool is_vector
)
3223 int rn
= extract32(insn
, 5, 5);
3224 bool is_wback
= extract32(insn
, 11, 1);
3225 bool use_key_a
= !extract32(insn
, 23, 1);
3227 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3229 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3230 unallocated_encoding(s
);
3235 gen_check_sp_alignment(s
);
3237 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3239 if (s
->pauth_active
) {
3241 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3243 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3247 /* Form the 10-bit signed, scaled offset. */
3248 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3249 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3250 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3252 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3253 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3255 tcg_rt
= cpu_reg(s
, rt
);
3256 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3257 /* extend */ false, /* iss_valid */ !is_wback
,
3258 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3261 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3265 /* Load/store register (all forms) */
3266 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3268 int rt
= extract32(insn
, 0, 5);
3269 int opc
= extract32(insn
, 22, 2);
3270 bool is_vector
= extract32(insn
, 26, 1);
3271 int size
= extract32(insn
, 30, 2);
3273 switch (extract32(insn
, 24, 2)) {
3275 if (extract32(insn
, 21, 1) == 0) {
3276 /* Load/store register (unscaled immediate)
3277 * Load/store immediate pre/post-indexed
3278 * Load/store register unprivileged
3280 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3283 switch (extract32(insn
, 10, 2)) {
3285 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3288 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3291 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3296 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3299 unallocated_encoding(s
);
3302 /* AdvSIMD load/store multiple structures
3304 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3305 * +---+---+---------------+---+-------------+--------+------+------+------+
3306 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3307 * +---+---+---------------+---+-------------+--------+------+------+------+
3309 * AdvSIMD load/store multiple structures (post-indexed)
3311 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3312 * +---+---+---------------+---+---+---------+--------+------+------+------+
3313 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3314 * +---+---+---------------+---+---+---------+--------+------+------+------+
3316 * Rt: first (or only) SIMD&FP register to be transferred
3317 * Rn: base address or SP
3318 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3320 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3322 int rt
= extract32(insn
, 0, 5);
3323 int rn
= extract32(insn
, 5, 5);
3324 int rm
= extract32(insn
, 16, 5);
3325 int size
= extract32(insn
, 10, 2);
3326 int opcode
= extract32(insn
, 12, 4);
3327 bool is_store
= !extract32(insn
, 22, 1);
3328 bool is_postidx
= extract32(insn
, 23, 1);
3329 bool is_q
= extract32(insn
, 30, 1);
3330 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3331 TCGMemOp endian
= s
->be_data
;
3333 int ebytes
; /* bytes per element */
3334 int elements
; /* elements per vector */
3335 int rpt
; /* num iterations */
3336 int selem
; /* structure elements */
3339 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3340 unallocated_encoding(s
);
3344 if (!is_postidx
&& rm
!= 0) {
3345 unallocated_encoding(s
);
3349 /* From the shared decode logic */
3380 unallocated_encoding(s
);
3384 if (size
== 3 && !is_q
&& selem
!= 1) {
3386 unallocated_encoding(s
);
3390 if (!fp_access_check(s
)) {
3395 gen_check_sp_alignment(s
);
3398 /* For our purposes, bytes are always little-endian. */
3403 /* Consecutive little-endian elements from a single register
3404 * can be promoted to a larger little-endian operation.
3406 if (selem
== 1 && endian
== MO_LE
) {
3410 elements
= (is_q
? 16 : 8) / ebytes
;
3412 tcg_rn
= cpu_reg_sp(s
, rn
);
3413 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3414 tcg_ebytes
= tcg_const_i64(ebytes
);
3416 for (r
= 0; r
< rpt
; r
++) {
3418 for (e
= 0; e
< elements
; e
++) {
3420 for (xs
= 0; xs
< selem
; xs
++) {
3421 int tt
= (rt
+ r
+ xs
) % 32;
3423 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3425 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3427 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3431 tcg_temp_free_i64(tcg_ebytes
);
3434 /* For non-quad operations, setting a slice of the low
3435 * 64 bits of the register clears the high 64 bits (in
3436 * the ARM ARM pseudocode this is implicit in the fact
3437 * that 'rval' is a 64 bit wide variable).
3438 * For quad operations, we might still need to zero the
3441 for (r
= 0; r
< rpt
* selem
; r
++) {
3442 int tt
= (rt
+ r
) % 32;
3443 clear_vec_high(s
, is_q
, tt
);
3449 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3451 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3456 /* AdvSIMD load/store single structure
3458 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3459 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3460 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3461 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3463 * AdvSIMD load/store single structure (post-indexed)
3465 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3466 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3467 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3468 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3470 * Rt: first (or only) SIMD&FP register to be transferred
3471 * Rn: base address or SP
3472 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3473 * index = encoded in Q:S:size dependent on size
3475 * lane_size = encoded in R, opc
3476 * transfer width = encoded in opc, S, size
3478 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3480 int rt
= extract32(insn
, 0, 5);
3481 int rn
= extract32(insn
, 5, 5);
3482 int rm
= extract32(insn
, 16, 5);
3483 int size
= extract32(insn
, 10, 2);
3484 int S
= extract32(insn
, 12, 1);
3485 int opc
= extract32(insn
, 13, 3);
3486 int R
= extract32(insn
, 21, 1);
3487 int is_load
= extract32(insn
, 22, 1);
3488 int is_postidx
= extract32(insn
, 23, 1);
3489 int is_q
= extract32(insn
, 30, 1);
3491 int scale
= extract32(opc
, 1, 2);
3492 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3493 bool replicate
= false;
3494 int index
= is_q
<< 3 | S
<< 2 | size
;
3496 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3498 if (extract32(insn
, 31, 1)) {
3499 unallocated_encoding(s
);
3502 if (!is_postidx
&& rm
!= 0) {
3503 unallocated_encoding(s
);
3509 if (!is_load
|| S
) {
3510 unallocated_encoding(s
);
3519 if (extract32(size
, 0, 1)) {
3520 unallocated_encoding(s
);
3526 if (extract32(size
, 1, 1)) {
3527 unallocated_encoding(s
);
3530 if (!extract32(size
, 0, 1)) {
3534 unallocated_encoding(s
);
3542 g_assert_not_reached();
3545 if (!fp_access_check(s
)) {
3549 ebytes
= 1 << scale
;
3552 gen_check_sp_alignment(s
);
3555 tcg_rn
= cpu_reg_sp(s
, rn
);
3556 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3557 tcg_ebytes
= tcg_const_i64(ebytes
);
3559 for (xs
= 0; xs
< selem
; xs
++) {
3561 /* Load and replicate to all elements */
3562 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3564 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3565 get_mem_index(s
), s
->be_data
+ scale
);
3566 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3567 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3569 tcg_temp_free_i64(tcg_tmp
);
3571 /* Load/store one element per register */
3573 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3575 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3578 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3581 tcg_temp_free_i64(tcg_ebytes
);
3585 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3587 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3592 /* Loads and stores */
3593 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3595 switch (extract32(insn
, 24, 6)) {
3596 case 0x08: /* Load/store exclusive */
3597 disas_ldst_excl(s
, insn
);
3599 case 0x18: case 0x1c: /* Load register (literal) */
3600 disas_ld_lit(s
, insn
);
3602 case 0x28: case 0x29:
3603 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3604 disas_ldst_pair(s
, insn
);
3606 case 0x38: case 0x39:
3607 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3608 disas_ldst_reg(s
, insn
);
3610 case 0x0c: /* AdvSIMD load/store multiple structures */
3611 disas_ldst_multiple_struct(s
, insn
);
3613 case 0x0d: /* AdvSIMD load/store single structure */
3614 disas_ldst_single_struct(s
, insn
);
3617 unallocated_encoding(s
);
3622 /* PC-rel. addressing
3623 * 31 30 29 28 24 23 5 4 0
3624 * +----+-------+-----------+-------------------+------+
3625 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3626 * +----+-------+-----------+-------------------+------+
3628 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3630 unsigned int page
, rd
;
3634 page
= extract32(insn
, 31, 1);
3635 /* SignExtend(immhi:immlo) -> offset */
3636 offset
= sextract64(insn
, 5, 19);
3637 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3638 rd
= extract32(insn
, 0, 5);
3642 /* ADRP (page based) */
3647 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3651 * Add/subtract (immediate)
3653 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3654 * +--+--+--+-----------+-----+-------------+-----+-----+
3655 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3656 * +--+--+--+-----------+-----+-------------+-----+-----+
3658 * sf: 0 -> 32bit, 1 -> 64bit
3659 * op: 0 -> add , 1 -> sub
3661 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3663 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3665 int rd
= extract32(insn
, 0, 5);
3666 int rn
= extract32(insn
, 5, 5);
3667 uint64_t imm
= extract32(insn
, 10, 12);
3668 int shift
= extract32(insn
, 22, 2);
3669 bool setflags
= extract32(insn
, 29, 1);
3670 bool sub_op
= extract32(insn
, 30, 1);
3671 bool is_64bit
= extract32(insn
, 31, 1);
3673 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3674 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3675 TCGv_i64 tcg_result
;
3684 unallocated_encoding(s
);
3688 tcg_result
= tcg_temp_new_i64();
3691 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3693 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3696 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3698 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3700 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3702 tcg_temp_free_i64(tcg_imm
);
3706 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3708 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3711 tcg_temp_free_i64(tcg_result
);
3714 /* The input should be a value in the bottom e bits (with higher
3715 * bits zero); returns that value replicated into every element
3716 * of size e in a 64 bit integer.
3718 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3728 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3729 static inline uint64_t bitmask64(unsigned int length
)
3731 assert(length
> 0 && length
<= 64);
3732 return ~0ULL >> (64 - length
);
3735 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3736 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3737 * value (ie should cause a guest UNDEF exception), and true if they are
3738 * valid, in which case the decoded bit pattern is written to result.
3740 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3741 unsigned int imms
, unsigned int immr
)
3744 unsigned e
, levels
, s
, r
;
3747 assert(immn
< 2 && imms
< 64 && immr
< 64);
3749 /* The bit patterns we create here are 64 bit patterns which
3750 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3751 * 64 bits each. Each element contains the same value: a run
3752 * of between 1 and e-1 non-zero bits, rotated within the
3753 * element by between 0 and e-1 bits.
3755 * The element size and run length are encoded into immn (1 bit)
3756 * and imms (6 bits) as follows:
3757 * 64 bit elements: immn = 1, imms = <length of run - 1>
3758 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3759 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3760 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3761 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3762 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3763 * Notice that immn = 0, imms = 11111x is the only combination
3764 * not covered by one of the above options; this is reserved.
3765 * Further, <length of run - 1> all-ones is a reserved pattern.
3767 * In all cases the rotation is by immr % e (and immr is 6 bits).
3770 /* First determine the element size */
3771 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3773 /* This is the immn == 0, imms == 0x11111x case */
3783 /* <length of run - 1> mustn't be all-ones. */
3787 /* Create the value of one element: s+1 set bits rotated
3788 * by r within the element (which is e bits wide)...
3790 mask
= bitmask64(s
+ 1);
3792 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3793 mask
&= bitmask64(e
);
3795 /* ...then replicate the element over the whole 64 bit value */
3796 mask
= bitfield_replicate(mask
, e
);
3801 /* Logical (immediate)
3802 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3803 * +----+-----+-------------+---+------+------+------+------+
3804 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3805 * +----+-----+-------------+---+------+------+------+------+
3807 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3809 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3810 TCGv_i64 tcg_rd
, tcg_rn
;
3812 bool is_and
= false;
3814 sf
= extract32(insn
, 31, 1);
3815 opc
= extract32(insn
, 29, 2);
3816 is_n
= extract32(insn
, 22, 1);
3817 immr
= extract32(insn
, 16, 6);
3818 imms
= extract32(insn
, 10, 6);
3819 rn
= extract32(insn
, 5, 5);
3820 rd
= extract32(insn
, 0, 5);
3823 unallocated_encoding(s
);
3827 if (opc
== 0x3) { /* ANDS */
3828 tcg_rd
= cpu_reg(s
, rd
);
3830 tcg_rd
= cpu_reg_sp(s
, rd
);
3832 tcg_rn
= cpu_reg(s
, rn
);
3834 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3835 /* some immediate field values are reserved */
3836 unallocated_encoding(s
);
3841 wmask
&= 0xffffffff;
3845 case 0x3: /* ANDS */
3847 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3851 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3854 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3857 assert(FALSE
); /* must handle all above */
3861 if (!sf
&& !is_and
) {
3862 /* zero extend final result; we know we can skip this for AND
3863 * since the immediate had the high 32 bits clear.
3865 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3868 if (opc
== 3) { /* ANDS */
3869 gen_logic_CC(sf
, tcg_rd
);
3874 * Move wide (immediate)
3876 * 31 30 29 28 23 22 21 20 5 4 0
3877 * +--+-----+-------------+-----+----------------+------+
3878 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3879 * +--+-----+-------------+-----+----------------+------+
3881 * sf: 0 -> 32 bit, 1 -> 64 bit
3882 * opc: 00 -> N, 10 -> Z, 11 -> K
3883 * hw: shift/16 (0,16, and sf only 32, 48)
3885 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3887 int rd
= extract32(insn
, 0, 5);
3888 uint64_t imm
= extract32(insn
, 5, 16);
3889 int sf
= extract32(insn
, 31, 1);
3890 int opc
= extract32(insn
, 29, 2);
3891 int pos
= extract32(insn
, 21, 2) << 4;
3892 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3895 if (!sf
&& (pos
>= 32)) {
3896 unallocated_encoding(s
);
3910 tcg_gen_movi_i64(tcg_rd
, imm
);
3913 tcg_imm
= tcg_const_i64(imm
);
3914 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3915 tcg_temp_free_i64(tcg_imm
);
3917 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3921 unallocated_encoding(s
);
3927 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3928 * +----+-----+-------------+---+------+------+------+------+
3929 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3930 * +----+-----+-------------+---+------+------+------+------+
3932 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3934 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3935 TCGv_i64 tcg_rd
, tcg_tmp
;
3937 sf
= extract32(insn
, 31, 1);
3938 opc
= extract32(insn
, 29, 2);
3939 n
= extract32(insn
, 22, 1);
3940 ri
= extract32(insn
, 16, 6);
3941 si
= extract32(insn
, 10, 6);
3942 rn
= extract32(insn
, 5, 5);
3943 rd
= extract32(insn
, 0, 5);
3944 bitsize
= sf
? 64 : 32;
3946 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3947 unallocated_encoding(s
);
3951 tcg_rd
= cpu_reg(s
, rd
);
3953 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3954 to be smaller than bitsize, we'll never reference data outside the
3955 low 32-bits anyway. */
3956 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3958 /* Recognize simple(r) extractions. */
3960 /* Wd<s-r:0> = Wn<s:r> */
3961 len
= (si
- ri
) + 1;
3962 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3963 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3965 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3966 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3969 /* opc == 1, BXFIL fall through to deposit */
3970 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3973 /* Handle the ri > si case with a deposit
3974 * Wd<32+s-r,32-r> = Wn<s:0>
3977 pos
= (bitsize
- ri
) & (bitsize
- 1);
3980 if (opc
== 0 && len
< ri
) {
3981 /* SBFM: sign extend the destination field from len to fill
3982 the balance of the word. Let the deposit below insert all
3983 of those sign bits. */
3984 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3988 if (opc
== 1) { /* BFM, BXFIL */
3989 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3991 /* SBFM or UBFM: We start with zero, and we haven't modified
3992 any bits outside bitsize, therefore the zero-extension
3993 below is unneeded. */
3994 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3999 if (!sf
) { /* zero extend final result */
4000 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4005 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4006 * +----+------+-------------+---+----+------+--------+------+------+
4007 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4008 * +----+------+-------------+---+----+------+--------+------+------+
4010 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4012 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4014 sf
= extract32(insn
, 31, 1);
4015 n
= extract32(insn
, 22, 1);
4016 rm
= extract32(insn
, 16, 5);
4017 imm
= extract32(insn
, 10, 6);
4018 rn
= extract32(insn
, 5, 5);
4019 rd
= extract32(insn
, 0, 5);
4020 op21
= extract32(insn
, 29, 2);
4021 op0
= extract32(insn
, 21, 1);
4022 bitsize
= sf
? 64 : 32;
4024 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4025 unallocated_encoding(s
);
4027 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4029 tcg_rd
= cpu_reg(s
, rd
);
4031 if (unlikely(imm
== 0)) {
4032 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4033 * so an extract from bit 0 is a special case.
4036 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4038 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4040 } else if (rm
== rn
) { /* ROR */
4041 tcg_rm
= cpu_reg(s
, rm
);
4043 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
4045 TCGv_i32 tmp
= tcg_temp_new_i32();
4046 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
4047 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
4048 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
4049 tcg_temp_free_i32(tmp
);
4052 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4053 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4054 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
4055 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
4056 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
4058 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4064 /* Data processing - immediate */
4065 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4067 switch (extract32(insn
, 23, 6)) {
4068 case 0x20: case 0x21: /* PC-rel. addressing */
4069 disas_pc_rel_adr(s
, insn
);
4071 case 0x22: case 0x23: /* Add/subtract (immediate) */
4072 disas_add_sub_imm(s
, insn
);
4074 case 0x24: /* Logical (immediate) */
4075 disas_logic_imm(s
, insn
);
4077 case 0x25: /* Move wide (immediate) */
4078 disas_movw_imm(s
, insn
);
4080 case 0x26: /* Bitfield */
4081 disas_bitfield(s
, insn
);
4083 case 0x27: /* Extract */
4084 disas_extract(s
, insn
);
4087 unallocated_encoding(s
);
4092 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4093 * Note that it is the caller's responsibility to ensure that the
4094 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4095 * mandated semantics for out of range shifts.
4097 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4098 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4100 switch (shift_type
) {
4101 case A64_SHIFT_TYPE_LSL
:
4102 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4104 case A64_SHIFT_TYPE_LSR
:
4105 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4107 case A64_SHIFT_TYPE_ASR
:
4109 tcg_gen_ext32s_i64(dst
, src
);
4111 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4113 case A64_SHIFT_TYPE_ROR
:
4115 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4118 t0
= tcg_temp_new_i32();
4119 t1
= tcg_temp_new_i32();
4120 tcg_gen_extrl_i64_i32(t0
, src
);
4121 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4122 tcg_gen_rotr_i32(t0
, t0
, t1
);
4123 tcg_gen_extu_i32_i64(dst
, t0
);
4124 tcg_temp_free_i32(t0
);
4125 tcg_temp_free_i32(t1
);
4129 assert(FALSE
); /* all shift types should be handled */
4133 if (!sf
) { /* zero extend final result */
4134 tcg_gen_ext32u_i64(dst
, dst
);
4138 /* Shift a TCGv src by immediate, put result in dst.
4139 * The shift amount must be in range (this should always be true as the
4140 * relevant instructions will UNDEF on bad shift immediates).
4142 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4143 enum a64_shift_type shift_type
, unsigned int shift_i
)
4145 assert(shift_i
< (sf
? 64 : 32));
4148 tcg_gen_mov_i64(dst
, src
);
4150 TCGv_i64 shift_const
;
4152 shift_const
= tcg_const_i64(shift_i
);
4153 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4154 tcg_temp_free_i64(shift_const
);
4158 /* Logical (shifted register)
4159 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4160 * +----+-----+-----------+-------+---+------+--------+------+------+
4161 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4162 * +----+-----+-----------+-------+---+------+--------+------+------+
4164 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4166 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4167 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4169 sf
= extract32(insn
, 31, 1);
4170 opc
= extract32(insn
, 29, 2);
4171 shift_type
= extract32(insn
, 22, 2);
4172 invert
= extract32(insn
, 21, 1);
4173 rm
= extract32(insn
, 16, 5);
4174 shift_amount
= extract32(insn
, 10, 6);
4175 rn
= extract32(insn
, 5, 5);
4176 rd
= extract32(insn
, 0, 5);
4178 if (!sf
&& (shift_amount
& (1 << 5))) {
4179 unallocated_encoding(s
);
4183 tcg_rd
= cpu_reg(s
, rd
);
4185 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4186 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4187 * register-register MOV and MVN, so it is worth special casing.
4189 tcg_rm
= cpu_reg(s
, rm
);
4191 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4193 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4197 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4199 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4205 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4208 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4211 tcg_rn
= cpu_reg(s
, rn
);
4213 switch (opc
| (invert
<< 2)) {
4216 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4219 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4222 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4226 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4229 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4232 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4240 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4244 gen_logic_CC(sf
, tcg_rd
);
4249 * Add/subtract (extended register)
4251 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4252 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4253 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4254 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4256 * sf: 0 -> 32bit, 1 -> 64bit
4257 * op: 0 -> add , 1 -> sub
4260 * option: extension type (see DecodeRegExtend)
4261 * imm3: optional shift to Rm
4263 * Rd = Rn + LSL(extend(Rm), amount)
4265 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4267 int rd
= extract32(insn
, 0, 5);
4268 int rn
= extract32(insn
, 5, 5);
4269 int imm3
= extract32(insn
, 10, 3);
4270 int option
= extract32(insn
, 13, 3);
4271 int rm
= extract32(insn
, 16, 5);
4272 int opt
= extract32(insn
, 22, 2);
4273 bool setflags
= extract32(insn
, 29, 1);
4274 bool sub_op
= extract32(insn
, 30, 1);
4275 bool sf
= extract32(insn
, 31, 1);
4277 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4279 TCGv_i64 tcg_result
;
4281 if (imm3
> 4 || opt
!= 0) {
4282 unallocated_encoding(s
);
4286 /* non-flag setting ops may use SP */
4288 tcg_rd
= cpu_reg_sp(s
, rd
);
4290 tcg_rd
= cpu_reg(s
, rd
);
4292 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4294 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4295 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4297 tcg_result
= tcg_temp_new_i64();
4301 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4303 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4307 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4309 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4314 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4316 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4319 tcg_temp_free_i64(tcg_result
);
4323 * Add/subtract (shifted register)
4325 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4326 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4327 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4328 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4330 * sf: 0 -> 32bit, 1 -> 64bit
4331 * op: 0 -> add , 1 -> sub
4333 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4334 * imm6: Shift amount to apply to Rm before the add/sub
4336 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4338 int rd
= extract32(insn
, 0, 5);
4339 int rn
= extract32(insn
, 5, 5);
4340 int imm6
= extract32(insn
, 10, 6);
4341 int rm
= extract32(insn
, 16, 5);
4342 int shift_type
= extract32(insn
, 22, 2);
4343 bool setflags
= extract32(insn
, 29, 1);
4344 bool sub_op
= extract32(insn
, 30, 1);
4345 bool sf
= extract32(insn
, 31, 1);
4347 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4348 TCGv_i64 tcg_rn
, tcg_rm
;
4349 TCGv_i64 tcg_result
;
4351 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4352 unallocated_encoding(s
);
4356 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4357 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4359 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4361 tcg_result
= tcg_temp_new_i64();
4365 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4367 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4371 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4373 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4378 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4380 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4383 tcg_temp_free_i64(tcg_result
);
4386 /* Data-processing (3 source)
4388 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4389 * +--+------+-----------+------+------+----+------+------+------+
4390 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4391 * +--+------+-----------+------+------+----+------+------+------+
4393 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4395 int rd
= extract32(insn
, 0, 5);
4396 int rn
= extract32(insn
, 5, 5);
4397 int ra
= extract32(insn
, 10, 5);
4398 int rm
= extract32(insn
, 16, 5);
4399 int op_id
= (extract32(insn
, 29, 3) << 4) |
4400 (extract32(insn
, 21, 3) << 1) |
4401 extract32(insn
, 15, 1);
4402 bool sf
= extract32(insn
, 31, 1);
4403 bool is_sub
= extract32(op_id
, 0, 1);
4404 bool is_high
= extract32(op_id
, 2, 1);
4405 bool is_signed
= false;
4410 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4412 case 0x42: /* SMADDL */
4413 case 0x43: /* SMSUBL */
4414 case 0x44: /* SMULH */
4417 case 0x0: /* MADD (32bit) */
4418 case 0x1: /* MSUB (32bit) */
4419 case 0x40: /* MADD (64bit) */
4420 case 0x41: /* MSUB (64bit) */
4421 case 0x4a: /* UMADDL */
4422 case 0x4b: /* UMSUBL */
4423 case 0x4c: /* UMULH */
4426 unallocated_encoding(s
);
4431 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4432 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4433 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4434 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4437 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4439 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4442 tcg_temp_free_i64(low_bits
);
4446 tcg_op1
= tcg_temp_new_i64();
4447 tcg_op2
= tcg_temp_new_i64();
4448 tcg_tmp
= tcg_temp_new_i64();
4451 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4452 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4455 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4456 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4458 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4459 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4463 if (ra
== 31 && !is_sub
) {
4464 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4465 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4467 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4469 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4471 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4476 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4479 tcg_temp_free_i64(tcg_op1
);
4480 tcg_temp_free_i64(tcg_op2
);
4481 tcg_temp_free_i64(tcg_tmp
);
4484 /* Add/subtract (with carry)
4485 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4486 * +--+--+--+------------------------+------+---------+------+-----+
4487 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4488 * +--+--+--+------------------------+------+---------+------+-----+
4492 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4494 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4495 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4497 if (extract32(insn
, 10, 6) != 0) {
4498 unallocated_encoding(s
);
4502 sf
= extract32(insn
, 31, 1);
4503 op
= extract32(insn
, 30, 1);
4504 setflags
= extract32(insn
, 29, 1);
4505 rm
= extract32(insn
, 16, 5);
4506 rn
= extract32(insn
, 5, 5);
4507 rd
= extract32(insn
, 0, 5);
4509 tcg_rd
= cpu_reg(s
, rd
);
4510 tcg_rn
= cpu_reg(s
, rn
);
4513 tcg_y
= new_tmp_a64(s
);
4514 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4516 tcg_y
= cpu_reg(s
, rm
);
4520 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4522 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4526 /* Conditional compare (immediate / register)
4527 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4528 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4529 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4530 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4533 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4535 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4536 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4537 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4540 if (!extract32(insn
, 29, 1)) {
4541 unallocated_encoding(s
);
4544 if (insn
& (1 << 10 | 1 << 4)) {
4545 unallocated_encoding(s
);
4548 sf
= extract32(insn
, 31, 1);
4549 op
= extract32(insn
, 30, 1);
4550 is_imm
= extract32(insn
, 11, 1);
4551 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4552 cond
= extract32(insn
, 12, 4);
4553 rn
= extract32(insn
, 5, 5);
4554 nzcv
= extract32(insn
, 0, 4);
4556 /* Set T0 = !COND. */
4557 tcg_t0
= tcg_temp_new_i32();
4558 arm_test_cc(&c
, cond
);
4559 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4562 /* Load the arguments for the new comparison. */
4564 tcg_y
= new_tmp_a64(s
);
4565 tcg_gen_movi_i64(tcg_y
, y
);
4567 tcg_y
= cpu_reg(s
, y
);
4569 tcg_rn
= cpu_reg(s
, rn
);
4571 /* Set the flags for the new comparison. */
4572 tcg_tmp
= tcg_temp_new_i64();
4574 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4576 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4578 tcg_temp_free_i64(tcg_tmp
);
4580 /* If COND was false, force the flags to #nzcv. Compute two masks
4581 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4582 * For tcg hosts that support ANDC, we can make do with just T1.
4583 * In either case, allow the tcg optimizer to delete any unused mask.
4585 tcg_t1
= tcg_temp_new_i32();
4586 tcg_t2
= tcg_temp_new_i32();
4587 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4588 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4590 if (nzcv
& 8) { /* N */
4591 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4593 if (TCG_TARGET_HAS_andc_i32
) {
4594 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4596 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4599 if (nzcv
& 4) { /* Z */
4600 if (TCG_TARGET_HAS_andc_i32
) {
4601 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4603 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4606 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4608 if (nzcv
& 2) { /* C */
4609 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4611 if (TCG_TARGET_HAS_andc_i32
) {
4612 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4614 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4617 if (nzcv
& 1) { /* V */
4618 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4620 if (TCG_TARGET_HAS_andc_i32
) {
4621 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4623 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4626 tcg_temp_free_i32(tcg_t0
);
4627 tcg_temp_free_i32(tcg_t1
);
4628 tcg_temp_free_i32(tcg_t2
);
4631 /* Conditional select
4632 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4633 * +----+----+---+-----------------+------+------+-----+------+------+
4634 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4635 * +----+----+---+-----------------+------+------+-----+------+------+
4637 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4639 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4640 TCGv_i64 tcg_rd
, zero
;
4643 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4644 /* S == 1 or op2<1> == 1 */
4645 unallocated_encoding(s
);
4648 sf
= extract32(insn
, 31, 1);
4649 else_inv
= extract32(insn
, 30, 1);
4650 rm
= extract32(insn
, 16, 5);
4651 cond
= extract32(insn
, 12, 4);
4652 else_inc
= extract32(insn
, 10, 1);
4653 rn
= extract32(insn
, 5, 5);
4654 rd
= extract32(insn
, 0, 5);
4656 tcg_rd
= cpu_reg(s
, rd
);
4658 a64_test_cc(&c
, cond
);
4659 zero
= tcg_const_i64(0);
4661 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4663 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4665 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4668 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4669 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4670 if (else_inv
&& else_inc
) {
4671 tcg_gen_neg_i64(t_false
, t_false
);
4672 } else if (else_inv
) {
4673 tcg_gen_not_i64(t_false
, t_false
);
4674 } else if (else_inc
) {
4675 tcg_gen_addi_i64(t_false
, t_false
, 1);
4677 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4680 tcg_temp_free_i64(zero
);
4684 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4688 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4689 unsigned int rn
, unsigned int rd
)
4691 TCGv_i64 tcg_rd
, tcg_rn
;
4692 tcg_rd
= cpu_reg(s
, rd
);
4693 tcg_rn
= cpu_reg(s
, rn
);
4696 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4698 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4699 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4700 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4701 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4702 tcg_temp_free_i32(tcg_tmp32
);
4706 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4707 unsigned int rn
, unsigned int rd
)
4709 TCGv_i64 tcg_rd
, tcg_rn
;
4710 tcg_rd
= cpu_reg(s
, rd
);
4711 tcg_rn
= cpu_reg(s
, rn
);
4714 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4716 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4717 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4718 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4719 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4720 tcg_temp_free_i32(tcg_tmp32
);
4724 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4725 unsigned int rn
, unsigned int rd
)
4727 TCGv_i64 tcg_rd
, tcg_rn
;
4728 tcg_rd
= cpu_reg(s
, rd
);
4729 tcg_rn
= cpu_reg(s
, rn
);
4732 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4734 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4735 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4736 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4737 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4738 tcg_temp_free_i32(tcg_tmp32
);
4742 /* REV with sf==1, opcode==3 ("REV64") */
4743 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4744 unsigned int rn
, unsigned int rd
)
4747 unallocated_encoding(s
);
4750 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4753 /* REV with sf==0, opcode==2
4754 * REV32 (sf==1, opcode==2)
4756 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4757 unsigned int rn
, unsigned int rd
)
4759 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4762 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4763 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4765 /* bswap32_i64 requires zero high word */
4766 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4767 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4768 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4769 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4770 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4772 tcg_temp_free_i64(tcg_tmp
);
4774 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4775 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4779 /* REV16 (opcode==1) */
4780 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4781 unsigned int rn
, unsigned int rd
)
4783 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4784 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4785 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4786 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4788 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4789 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4790 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4791 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4792 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4794 tcg_temp_free_i64(mask
);
4795 tcg_temp_free_i64(tcg_tmp
);
4798 /* Data-processing (1 source)
4799 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4800 * +----+---+---+-----------------+---------+--------+------+------+
4801 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4802 * +----+---+---+-----------------+---------+--------+------+------+
4804 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4806 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4809 if (extract32(insn
, 29, 1)) {
4810 unallocated_encoding(s
);
4814 sf
= extract32(insn
, 31, 1);
4815 opcode
= extract32(insn
, 10, 6);
4816 opcode2
= extract32(insn
, 16, 5);
4817 rn
= extract32(insn
, 5, 5);
4818 rd
= extract32(insn
, 0, 5);
4820 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4822 switch (MAP(sf
, opcode2
, opcode
)) {
4823 case MAP(0, 0x00, 0x00): /* RBIT */
4824 case MAP(1, 0x00, 0x00):
4825 handle_rbit(s
, sf
, rn
, rd
);
4827 case MAP(0, 0x00, 0x01): /* REV16 */
4828 case MAP(1, 0x00, 0x01):
4829 handle_rev16(s
, sf
, rn
, rd
);
4831 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4832 case MAP(1, 0x00, 0x02):
4833 handle_rev32(s
, sf
, rn
, rd
);
4835 case MAP(1, 0x00, 0x03): /* REV64 */
4836 handle_rev64(s
, sf
, rn
, rd
);
4838 case MAP(0, 0x00, 0x04): /* CLZ */
4839 case MAP(1, 0x00, 0x04):
4840 handle_clz(s
, sf
, rn
, rd
);
4842 case MAP(0, 0x00, 0x05): /* CLS */
4843 case MAP(1, 0x00, 0x05):
4844 handle_cls(s
, sf
, rn
, rd
);
4846 case MAP(1, 0x01, 0x00): /* PACIA */
4847 if (s
->pauth_active
) {
4848 tcg_rd
= cpu_reg(s
, rd
);
4849 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4850 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4851 goto do_unallocated
;
4854 case MAP(1, 0x01, 0x01): /* PACIB */
4855 if (s
->pauth_active
) {
4856 tcg_rd
= cpu_reg(s
, rd
);
4857 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4858 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4859 goto do_unallocated
;
4862 case MAP(1, 0x01, 0x02): /* PACDA */
4863 if (s
->pauth_active
) {
4864 tcg_rd
= cpu_reg(s
, rd
);
4865 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4866 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4867 goto do_unallocated
;
4870 case MAP(1, 0x01, 0x03): /* PACDB */
4871 if (s
->pauth_active
) {
4872 tcg_rd
= cpu_reg(s
, rd
);
4873 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4874 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4875 goto do_unallocated
;
4878 case MAP(1, 0x01, 0x04): /* AUTIA */
4879 if (s
->pauth_active
) {
4880 tcg_rd
= cpu_reg(s
, rd
);
4881 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4882 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4883 goto do_unallocated
;
4886 case MAP(1, 0x01, 0x05): /* AUTIB */
4887 if (s
->pauth_active
) {
4888 tcg_rd
= cpu_reg(s
, rd
);
4889 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4890 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4891 goto do_unallocated
;
4894 case MAP(1, 0x01, 0x06): /* AUTDA */
4895 if (s
->pauth_active
) {
4896 tcg_rd
= cpu_reg(s
, rd
);
4897 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4898 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4899 goto do_unallocated
;
4902 case MAP(1, 0x01, 0x07): /* AUTDB */
4903 if (s
->pauth_active
) {
4904 tcg_rd
= cpu_reg(s
, rd
);
4905 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4906 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4907 goto do_unallocated
;
4910 case MAP(1, 0x01, 0x08): /* PACIZA */
4911 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4912 goto do_unallocated
;
4913 } else if (s
->pauth_active
) {
4914 tcg_rd
= cpu_reg(s
, rd
);
4915 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4918 case MAP(1, 0x01, 0x09): /* PACIZB */
4919 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4920 goto do_unallocated
;
4921 } else if (s
->pauth_active
) {
4922 tcg_rd
= cpu_reg(s
, rd
);
4923 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4926 case MAP(1, 0x01, 0x0a): /* PACDZA */
4927 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4928 goto do_unallocated
;
4929 } else if (s
->pauth_active
) {
4930 tcg_rd
= cpu_reg(s
, rd
);
4931 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4934 case MAP(1, 0x01, 0x0b): /* PACDZB */
4935 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4936 goto do_unallocated
;
4937 } else if (s
->pauth_active
) {
4938 tcg_rd
= cpu_reg(s
, rd
);
4939 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4942 case MAP(1, 0x01, 0x0c): /* AUTIZA */
4943 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4944 goto do_unallocated
;
4945 } else if (s
->pauth_active
) {
4946 tcg_rd
= cpu_reg(s
, rd
);
4947 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4950 case MAP(1, 0x01, 0x0d): /* AUTIZB */
4951 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4952 goto do_unallocated
;
4953 } else if (s
->pauth_active
) {
4954 tcg_rd
= cpu_reg(s
, rd
);
4955 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4958 case MAP(1, 0x01, 0x0e): /* AUTDZA */
4959 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4960 goto do_unallocated
;
4961 } else if (s
->pauth_active
) {
4962 tcg_rd
= cpu_reg(s
, rd
);
4963 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4966 case MAP(1, 0x01, 0x0f): /* AUTDZB */
4967 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4968 goto do_unallocated
;
4969 } else if (s
->pauth_active
) {
4970 tcg_rd
= cpu_reg(s
, rd
);
4971 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4974 case MAP(1, 0x01, 0x10): /* XPACI */
4975 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4976 goto do_unallocated
;
4977 } else if (s
->pauth_active
) {
4978 tcg_rd
= cpu_reg(s
, rd
);
4979 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
4982 case MAP(1, 0x01, 0x11): /* XPACD */
4983 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4984 goto do_unallocated
;
4985 } else if (s
->pauth_active
) {
4986 tcg_rd
= cpu_reg(s
, rd
);
4987 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
4992 unallocated_encoding(s
);
4999 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5000 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5002 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5003 tcg_rd
= cpu_reg(s
, rd
);
5005 if (!sf
&& is_signed
) {
5006 tcg_n
= new_tmp_a64(s
);
5007 tcg_m
= new_tmp_a64(s
);
5008 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5009 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5011 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5012 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5016 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5018 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5021 if (!sf
) { /* zero extend final result */
5022 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5026 /* LSLV, LSRV, ASRV, RORV */
5027 static void handle_shift_reg(DisasContext
*s
,
5028 enum a64_shift_type shift_type
, unsigned int sf
,
5029 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5031 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5032 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5033 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5035 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5036 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5037 tcg_temp_free_i64(tcg_shift
);
5040 /* CRC32[BHWX], CRC32C[BHWX] */
5041 static void handle_crc32(DisasContext
*s
,
5042 unsigned int sf
, unsigned int sz
, bool crc32c
,
5043 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5045 TCGv_i64 tcg_acc
, tcg_val
;
5048 if (!dc_isar_feature(aa64_crc32
, s
)
5049 || (sf
== 1 && sz
!= 3)
5050 || (sf
== 0 && sz
== 3)) {
5051 unallocated_encoding(s
);
5056 tcg_val
= cpu_reg(s
, rm
);
5070 g_assert_not_reached();
5072 tcg_val
= new_tmp_a64(s
);
5073 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5076 tcg_acc
= cpu_reg(s
, rn
);
5077 tcg_bytes
= tcg_const_i32(1 << sz
);
5080 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5082 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5085 tcg_temp_free_i32(tcg_bytes
);
5088 /* Data-processing (2 source)
5089 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5090 * +----+---+---+-----------------+------+--------+------+------+
5091 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5092 * +----+---+---+-----------------+------+--------+------+------+
5094 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5096 unsigned int sf
, rm
, opcode
, rn
, rd
;
5097 sf
= extract32(insn
, 31, 1);
5098 rm
= extract32(insn
, 16, 5);
5099 opcode
= extract32(insn
, 10, 6);
5100 rn
= extract32(insn
, 5, 5);
5101 rd
= extract32(insn
, 0, 5);
5103 if (extract32(insn
, 29, 1)) {
5104 unallocated_encoding(s
);
5110 handle_div(s
, false, sf
, rm
, rn
, rd
);
5113 handle_div(s
, true, sf
, rm
, rn
, rd
);
5116 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5119 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5122 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5125 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5127 case 12: /* PACGA */
5128 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5129 goto do_unallocated
;
5131 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5132 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5141 case 23: /* CRC32 */
5143 int sz
= extract32(opcode
, 0, 2);
5144 bool crc32c
= extract32(opcode
, 2, 1);
5145 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5150 unallocated_encoding(s
);
5155 /* Data processing - register */
5156 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5158 switch (extract32(insn
, 24, 5)) {
5159 case 0x0a: /* Logical (shifted register) */
5160 disas_logic_reg(s
, insn
);
5162 case 0x0b: /* Add/subtract */
5163 if (insn
& (1 << 21)) { /* (extended register) */
5164 disas_add_sub_ext_reg(s
, insn
);
5166 disas_add_sub_reg(s
, insn
);
5169 case 0x1b: /* Data-processing (3 source) */
5170 disas_data_proc_3src(s
, insn
);
5173 switch (extract32(insn
, 21, 3)) {
5174 case 0x0: /* Add/subtract (with carry) */
5175 disas_adc_sbc(s
, insn
);
5177 case 0x2: /* Conditional compare */
5178 disas_cc(s
, insn
); /* both imm and reg forms */
5180 case 0x4: /* Conditional select */
5181 disas_cond_select(s
, insn
);
5183 case 0x6: /* Data-processing */
5184 if (insn
& (1 << 30)) { /* (1 source) */
5185 disas_data_proc_1src(s
, insn
);
5186 } else { /* (2 source) */
5187 disas_data_proc_2src(s
, insn
);
5191 unallocated_encoding(s
);
5196 unallocated_encoding(s
);
5201 static void handle_fp_compare(DisasContext
*s
, int size
,
5202 unsigned int rn
, unsigned int rm
,
5203 bool cmp_with_zero
, bool signal_all_nans
)
5205 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5206 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5208 if (size
== MO_64
) {
5209 TCGv_i64 tcg_vn
, tcg_vm
;
5211 tcg_vn
= read_fp_dreg(s
, rn
);
5212 if (cmp_with_zero
) {
5213 tcg_vm
= tcg_const_i64(0);
5215 tcg_vm
= read_fp_dreg(s
, rm
);
5217 if (signal_all_nans
) {
5218 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5220 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5222 tcg_temp_free_i64(tcg_vn
);
5223 tcg_temp_free_i64(tcg_vm
);
5225 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5226 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5228 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5229 if (cmp_with_zero
) {
5230 tcg_gen_movi_i32(tcg_vm
, 0);
5232 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5237 if (signal_all_nans
) {
5238 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5240 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5244 if (signal_all_nans
) {
5245 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5247 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5251 g_assert_not_reached();
5254 tcg_temp_free_i32(tcg_vn
);
5255 tcg_temp_free_i32(tcg_vm
);
5258 tcg_temp_free_ptr(fpst
);
5260 gen_set_nzcv(tcg_flags
);
5262 tcg_temp_free_i64(tcg_flags
);
5265 /* Floating point compare
5266 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5267 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5268 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5269 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5271 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5273 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5276 mos
= extract32(insn
, 29, 3);
5277 type
= extract32(insn
, 22, 2);
5278 rm
= extract32(insn
, 16, 5);
5279 op
= extract32(insn
, 14, 2);
5280 rn
= extract32(insn
, 5, 5);
5281 opc
= extract32(insn
, 3, 2);
5282 op2r
= extract32(insn
, 0, 3);
5284 if (mos
|| op
|| op2r
) {
5285 unallocated_encoding(s
);
5298 if (dc_isar_feature(aa64_fp16
, s
)) {
5303 unallocated_encoding(s
);
5307 if (!fp_access_check(s
)) {
5311 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5314 /* Floating point conditional compare
5315 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5316 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5317 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5318 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5320 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5322 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5324 TCGLabel
*label_continue
= NULL
;
5327 mos
= extract32(insn
, 29, 3);
5328 type
= extract32(insn
, 22, 2);
5329 rm
= extract32(insn
, 16, 5);
5330 cond
= extract32(insn
, 12, 4);
5331 rn
= extract32(insn
, 5, 5);
5332 op
= extract32(insn
, 4, 1);
5333 nzcv
= extract32(insn
, 0, 4);
5336 unallocated_encoding(s
);
5349 if (dc_isar_feature(aa64_fp16
, s
)) {
5354 unallocated_encoding(s
);
5358 if (!fp_access_check(s
)) {
5362 if (cond
< 0x0e) { /* not always */
5363 TCGLabel
*label_match
= gen_new_label();
5364 label_continue
= gen_new_label();
5365 arm_gen_test_cc(cond
, label_match
);
5367 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5368 gen_set_nzcv(tcg_flags
);
5369 tcg_temp_free_i64(tcg_flags
);
5370 tcg_gen_br(label_continue
);
5371 gen_set_label(label_match
);
5374 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5377 gen_set_label(label_continue
);
5381 /* Floating point conditional select
5382 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5383 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5384 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5385 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5387 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5389 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5390 TCGv_i64 t_true
, t_false
, t_zero
;
5394 mos
= extract32(insn
, 29, 3);
5395 type
= extract32(insn
, 22, 2);
5396 rm
= extract32(insn
, 16, 5);
5397 cond
= extract32(insn
, 12, 4);
5398 rn
= extract32(insn
, 5, 5);
5399 rd
= extract32(insn
, 0, 5);
5402 unallocated_encoding(s
);
5415 if (dc_isar_feature(aa64_fp16
, s
)) {
5420 unallocated_encoding(s
);
5424 if (!fp_access_check(s
)) {
5428 /* Zero extend sreg & hreg inputs to 64 bits now. */
5429 t_true
= tcg_temp_new_i64();
5430 t_false
= tcg_temp_new_i64();
5431 read_vec_element(s
, t_true
, rn
, 0, sz
);
5432 read_vec_element(s
, t_false
, rm
, 0, sz
);
5434 a64_test_cc(&c
, cond
);
5435 t_zero
= tcg_const_i64(0);
5436 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5437 tcg_temp_free_i64(t_zero
);
5438 tcg_temp_free_i64(t_false
);
5441 /* Note that sregs & hregs write back zeros to the high bits,
5442 and we've already done the zero-extension. */
5443 write_fp_dreg(s
, rd
, t_true
);
5444 tcg_temp_free_i64(t_true
);
5447 /* Floating-point data-processing (1 source) - half precision */
5448 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5450 TCGv_ptr fpst
= NULL
;
5451 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5452 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5455 case 0x0: /* FMOV */
5456 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5458 case 0x1: /* FABS */
5459 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5461 case 0x2: /* FNEG */
5462 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5464 case 0x3: /* FSQRT */
5465 fpst
= get_fpstatus_ptr(true);
5466 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5468 case 0x8: /* FRINTN */
5469 case 0x9: /* FRINTP */
5470 case 0xa: /* FRINTM */
5471 case 0xb: /* FRINTZ */
5472 case 0xc: /* FRINTA */
5474 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5475 fpst
= get_fpstatus_ptr(true);
5477 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5478 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5480 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5481 tcg_temp_free_i32(tcg_rmode
);
5484 case 0xe: /* FRINTX */
5485 fpst
= get_fpstatus_ptr(true);
5486 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5488 case 0xf: /* FRINTI */
5489 fpst
= get_fpstatus_ptr(true);
5490 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5496 write_fp_sreg(s
, rd
, tcg_res
);
5499 tcg_temp_free_ptr(fpst
);
5501 tcg_temp_free_i32(tcg_op
);
5502 tcg_temp_free_i32(tcg_res
);
5505 /* Floating-point data-processing (1 source) - single precision */
5506 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5512 fpst
= get_fpstatus_ptr(false);
5513 tcg_op
= read_fp_sreg(s
, rn
);
5514 tcg_res
= tcg_temp_new_i32();
5517 case 0x0: /* FMOV */
5518 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5520 case 0x1: /* FABS */
5521 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5523 case 0x2: /* FNEG */
5524 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5526 case 0x3: /* FSQRT */
5527 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5529 case 0x8: /* FRINTN */
5530 case 0x9: /* FRINTP */
5531 case 0xa: /* FRINTM */
5532 case 0xb: /* FRINTZ */
5533 case 0xc: /* FRINTA */
5535 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5537 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5538 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5540 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5541 tcg_temp_free_i32(tcg_rmode
);
5544 case 0xe: /* FRINTX */
5545 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5547 case 0xf: /* FRINTI */
5548 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5554 write_fp_sreg(s
, rd
, tcg_res
);
5556 tcg_temp_free_ptr(fpst
);
5557 tcg_temp_free_i32(tcg_op
);
5558 tcg_temp_free_i32(tcg_res
);
5561 /* Floating-point data-processing (1 source) - double precision */
5562 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5569 case 0x0: /* FMOV */
5570 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5574 fpst
= get_fpstatus_ptr(false);
5575 tcg_op
= read_fp_dreg(s
, rn
);
5576 tcg_res
= tcg_temp_new_i64();
5579 case 0x1: /* FABS */
5580 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5582 case 0x2: /* FNEG */
5583 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5585 case 0x3: /* FSQRT */
5586 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5588 case 0x8: /* FRINTN */
5589 case 0x9: /* FRINTP */
5590 case 0xa: /* FRINTM */
5591 case 0xb: /* FRINTZ */
5592 case 0xc: /* FRINTA */
5594 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5596 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5597 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5599 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5600 tcg_temp_free_i32(tcg_rmode
);
5603 case 0xe: /* FRINTX */
5604 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5606 case 0xf: /* FRINTI */
5607 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5613 write_fp_dreg(s
, rd
, tcg_res
);
5615 tcg_temp_free_ptr(fpst
);
5616 tcg_temp_free_i64(tcg_op
);
5617 tcg_temp_free_i64(tcg_res
);
5620 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5621 int rd
, int rn
, int dtype
, int ntype
)
5626 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5628 /* Single to double */
5629 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5630 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5631 write_fp_dreg(s
, rd
, tcg_rd
);
5632 tcg_temp_free_i64(tcg_rd
);
5634 /* Single to half */
5635 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5636 TCGv_i32 ahp
= get_ahp_flag();
5637 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5639 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5640 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5641 write_fp_sreg(s
, rd
, tcg_rd
);
5642 tcg_temp_free_i32(tcg_rd
);
5643 tcg_temp_free_i32(ahp
);
5644 tcg_temp_free_ptr(fpst
);
5646 tcg_temp_free_i32(tcg_rn
);
5651 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5652 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5654 /* Double to single */
5655 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5657 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5658 TCGv_i32 ahp
= get_ahp_flag();
5659 /* Double to half */
5660 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5661 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5662 tcg_temp_free_ptr(fpst
);
5663 tcg_temp_free_i32(ahp
);
5665 write_fp_sreg(s
, rd
, tcg_rd
);
5666 tcg_temp_free_i32(tcg_rd
);
5667 tcg_temp_free_i64(tcg_rn
);
5672 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5673 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5674 TCGv_i32 tcg_ahp
= get_ahp_flag();
5675 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5677 /* Half to single */
5678 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5679 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5680 write_fp_sreg(s
, rd
, tcg_rd
);
5681 tcg_temp_free_ptr(tcg_fpst
);
5682 tcg_temp_free_i32(tcg_ahp
);
5683 tcg_temp_free_i32(tcg_rd
);
5685 /* Half to double */
5686 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5687 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5688 write_fp_dreg(s
, rd
, tcg_rd
);
5689 tcg_temp_free_i64(tcg_rd
);
5691 tcg_temp_free_i32(tcg_rn
);
5699 /* Floating point data-processing (1 source)
5700 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5701 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5702 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5703 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5705 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5707 int mos
= extract32(insn
, 29, 3);
5708 int type
= extract32(insn
, 22, 2);
5709 int opcode
= extract32(insn
, 15, 6);
5710 int rn
= extract32(insn
, 5, 5);
5711 int rd
= extract32(insn
, 0, 5);
5714 unallocated_encoding(s
);
5719 case 0x4: case 0x5: case 0x7:
5721 /* FCVT between half, single and double precision */
5722 int dtype
= extract32(opcode
, 0, 2);
5723 if (type
== 2 || dtype
== type
) {
5724 unallocated_encoding(s
);
5727 if (!fp_access_check(s
)) {
5731 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5737 /* 32-to-32 and 64-to-64 ops */
5740 if (!fp_access_check(s
)) {
5744 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5747 if (!fp_access_check(s
)) {
5751 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5754 if (!dc_isar_feature(aa64_fp16
, s
)) {
5755 unallocated_encoding(s
);
5759 if (!fp_access_check(s
)) {
5763 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5766 unallocated_encoding(s
);
5770 unallocated_encoding(s
);
5775 /* Floating-point data-processing (2 source) - single precision */
5776 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5777 int rd
, int rn
, int rm
)
5784 tcg_res
= tcg_temp_new_i32();
5785 fpst
= get_fpstatus_ptr(false);
5786 tcg_op1
= read_fp_sreg(s
, rn
);
5787 tcg_op2
= read_fp_sreg(s
, rm
);
5790 case 0x0: /* FMUL */
5791 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5793 case 0x1: /* FDIV */
5794 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5796 case 0x2: /* FADD */
5797 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5799 case 0x3: /* FSUB */
5800 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5802 case 0x4: /* FMAX */
5803 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5805 case 0x5: /* FMIN */
5806 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5808 case 0x6: /* FMAXNM */
5809 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5811 case 0x7: /* FMINNM */
5812 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5814 case 0x8: /* FNMUL */
5815 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5816 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5820 write_fp_sreg(s
, rd
, tcg_res
);
5822 tcg_temp_free_ptr(fpst
);
5823 tcg_temp_free_i32(tcg_op1
);
5824 tcg_temp_free_i32(tcg_op2
);
5825 tcg_temp_free_i32(tcg_res
);
5828 /* Floating-point data-processing (2 source) - double precision */
5829 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5830 int rd
, int rn
, int rm
)
5837 tcg_res
= tcg_temp_new_i64();
5838 fpst
= get_fpstatus_ptr(false);
5839 tcg_op1
= read_fp_dreg(s
, rn
);
5840 tcg_op2
= read_fp_dreg(s
, rm
);
5843 case 0x0: /* FMUL */
5844 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5846 case 0x1: /* FDIV */
5847 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5849 case 0x2: /* FADD */
5850 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5852 case 0x3: /* FSUB */
5853 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5855 case 0x4: /* FMAX */
5856 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5858 case 0x5: /* FMIN */
5859 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5861 case 0x6: /* FMAXNM */
5862 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5864 case 0x7: /* FMINNM */
5865 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5867 case 0x8: /* FNMUL */
5868 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5869 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5873 write_fp_dreg(s
, rd
, tcg_res
);
5875 tcg_temp_free_ptr(fpst
);
5876 tcg_temp_free_i64(tcg_op1
);
5877 tcg_temp_free_i64(tcg_op2
);
5878 tcg_temp_free_i64(tcg_res
);
5881 /* Floating-point data-processing (2 source) - half precision */
5882 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5883 int rd
, int rn
, int rm
)
5890 tcg_res
= tcg_temp_new_i32();
5891 fpst
= get_fpstatus_ptr(true);
5892 tcg_op1
= read_fp_hreg(s
, rn
);
5893 tcg_op2
= read_fp_hreg(s
, rm
);
5896 case 0x0: /* FMUL */
5897 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5899 case 0x1: /* FDIV */
5900 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5902 case 0x2: /* FADD */
5903 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5905 case 0x3: /* FSUB */
5906 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5908 case 0x4: /* FMAX */
5909 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5911 case 0x5: /* FMIN */
5912 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5914 case 0x6: /* FMAXNM */
5915 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5917 case 0x7: /* FMINNM */
5918 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5920 case 0x8: /* FNMUL */
5921 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5922 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5925 g_assert_not_reached();
5928 write_fp_sreg(s
, rd
, tcg_res
);
5930 tcg_temp_free_ptr(fpst
);
5931 tcg_temp_free_i32(tcg_op1
);
5932 tcg_temp_free_i32(tcg_op2
);
5933 tcg_temp_free_i32(tcg_res
);
5936 /* Floating point data-processing (2 source)
5937 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5938 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5939 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5940 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5942 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5944 int mos
= extract32(insn
, 29, 3);
5945 int type
= extract32(insn
, 22, 2);
5946 int rd
= extract32(insn
, 0, 5);
5947 int rn
= extract32(insn
, 5, 5);
5948 int rm
= extract32(insn
, 16, 5);
5949 int opcode
= extract32(insn
, 12, 4);
5951 if (opcode
> 8 || mos
) {
5952 unallocated_encoding(s
);
5958 if (!fp_access_check(s
)) {
5961 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5964 if (!fp_access_check(s
)) {
5967 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5970 if (!dc_isar_feature(aa64_fp16
, s
)) {
5971 unallocated_encoding(s
);
5974 if (!fp_access_check(s
)) {
5977 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5980 unallocated_encoding(s
);
5984 /* Floating-point data-processing (3 source) - single precision */
5985 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5986 int rd
, int rn
, int rm
, int ra
)
5988 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5989 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5990 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5992 tcg_op1
= read_fp_sreg(s
, rn
);
5993 tcg_op2
= read_fp_sreg(s
, rm
);
5994 tcg_op3
= read_fp_sreg(s
, ra
);
5996 /* These are fused multiply-add, and must be done as one
5997 * floating point operation with no rounding between the
5998 * multiplication and addition steps.
5999 * NB that doing the negations here as separate steps is
6000 * correct : an input NaN should come out with its sign bit
6001 * flipped if it is a negated-input.
6004 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6008 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6011 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6013 write_fp_sreg(s
, rd
, tcg_res
);
6015 tcg_temp_free_ptr(fpst
);
6016 tcg_temp_free_i32(tcg_op1
);
6017 tcg_temp_free_i32(tcg_op2
);
6018 tcg_temp_free_i32(tcg_op3
);
6019 tcg_temp_free_i32(tcg_res
);
6022 /* Floating-point data-processing (3 source) - double precision */
6023 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6024 int rd
, int rn
, int rm
, int ra
)
6026 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6027 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6028 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6030 tcg_op1
= read_fp_dreg(s
, rn
);
6031 tcg_op2
= read_fp_dreg(s
, rm
);
6032 tcg_op3
= read_fp_dreg(s
, ra
);
6034 /* These are fused multiply-add, and must be done as one
6035 * floating point operation with no rounding between the
6036 * multiplication and addition steps.
6037 * NB that doing the negations here as separate steps is
6038 * correct : an input NaN should come out with its sign bit
6039 * flipped if it is a negated-input.
6042 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6046 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6049 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6051 write_fp_dreg(s
, rd
, tcg_res
);
6053 tcg_temp_free_ptr(fpst
);
6054 tcg_temp_free_i64(tcg_op1
);
6055 tcg_temp_free_i64(tcg_op2
);
6056 tcg_temp_free_i64(tcg_op3
);
6057 tcg_temp_free_i64(tcg_res
);
6060 /* Floating-point data-processing (3 source) - half precision */
6061 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6062 int rd
, int rn
, int rm
, int ra
)
6064 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6065 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6066 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6068 tcg_op1
= read_fp_hreg(s
, rn
);
6069 tcg_op2
= read_fp_hreg(s
, rm
);
6070 tcg_op3
= read_fp_hreg(s
, ra
);
6072 /* These are fused multiply-add, and must be done as one
6073 * floating point operation with no rounding between the
6074 * multiplication and addition steps.
6075 * NB that doing the negations here as separate steps is
6076 * correct : an input NaN should come out with its sign bit
6077 * flipped if it is a negated-input.
6080 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6084 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6087 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6089 write_fp_sreg(s
, rd
, tcg_res
);
6091 tcg_temp_free_ptr(fpst
);
6092 tcg_temp_free_i32(tcg_op1
);
6093 tcg_temp_free_i32(tcg_op2
);
6094 tcg_temp_free_i32(tcg_op3
);
6095 tcg_temp_free_i32(tcg_res
);
6098 /* Floating point data-processing (3 source)
6099 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6100 * +---+---+---+-----------+------+----+------+----+------+------+------+
6101 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6102 * +---+---+---+-----------+------+----+------+----+------+------+------+
6104 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6106 int mos
= extract32(insn
, 29, 3);
6107 int type
= extract32(insn
, 22, 2);
6108 int rd
= extract32(insn
, 0, 5);
6109 int rn
= extract32(insn
, 5, 5);
6110 int ra
= extract32(insn
, 10, 5);
6111 int rm
= extract32(insn
, 16, 5);
6112 bool o0
= extract32(insn
, 15, 1);
6113 bool o1
= extract32(insn
, 21, 1);
6116 unallocated_encoding(s
);
6122 if (!fp_access_check(s
)) {
6125 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6128 if (!fp_access_check(s
)) {
6131 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6134 if (!dc_isar_feature(aa64_fp16
, s
)) {
6135 unallocated_encoding(s
);
6138 if (!fp_access_check(s
)) {
6141 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6144 unallocated_encoding(s
);
6148 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
6149 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
6150 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
6152 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
6158 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6159 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
6160 extract32(imm8
, 0, 6);
6164 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6165 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
6166 (extract32(imm8
, 0, 6) << 3);
6170 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6171 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
6172 (extract32(imm8
, 0, 6) << 6);
6175 g_assert_not_reached();
6180 /* Floating point immediate
6181 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6182 * +---+---+---+-----------+------+---+------------+-------+------+------+
6183 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6184 * +---+---+---+-----------+------+---+------------+-------+------+------+
6186 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6188 int rd
= extract32(insn
, 0, 5);
6189 int imm5
= extract32(insn
, 5, 5);
6190 int imm8
= extract32(insn
, 13, 8);
6191 int type
= extract32(insn
, 22, 2);
6192 int mos
= extract32(insn
, 29, 3);
6198 unallocated_encoding(s
);
6211 if (dc_isar_feature(aa64_fp16
, s
)) {
6216 unallocated_encoding(s
);
6220 if (!fp_access_check(s
)) {
6224 imm
= vfp_expand_imm(sz
, imm8
);
6226 tcg_res
= tcg_const_i64(imm
);
6227 write_fp_dreg(s
, rd
, tcg_res
);
6228 tcg_temp_free_i64(tcg_res
);
6231 /* Handle floating point <=> fixed point conversions. Note that we can
6232 * also deal with fp <=> integer conversions as a special case (scale == 64)
6233 * OPTME: consider handling that special case specially or at least skipping
6234 * the call to scalbn in the helpers for zero shifts.
6236 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6237 bool itof
, int rmode
, int scale
, int sf
, int type
)
6239 bool is_signed
= !(opcode
& 1);
6240 TCGv_ptr tcg_fpstatus
;
6241 TCGv_i32 tcg_shift
, tcg_single
;
6242 TCGv_i64 tcg_double
;
6244 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6246 tcg_shift
= tcg_const_i32(64 - scale
);
6249 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6251 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6254 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6256 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6259 tcg_int
= tcg_extend
;
6263 case 1: /* float64 */
6264 tcg_double
= tcg_temp_new_i64();
6266 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6267 tcg_shift
, tcg_fpstatus
);
6269 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6270 tcg_shift
, tcg_fpstatus
);
6272 write_fp_dreg(s
, rd
, tcg_double
);
6273 tcg_temp_free_i64(tcg_double
);
6276 case 0: /* float32 */
6277 tcg_single
= tcg_temp_new_i32();
6279 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6280 tcg_shift
, tcg_fpstatus
);
6282 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6283 tcg_shift
, tcg_fpstatus
);
6285 write_fp_sreg(s
, rd
, tcg_single
);
6286 tcg_temp_free_i32(tcg_single
);
6289 case 3: /* float16 */
6290 tcg_single
= tcg_temp_new_i32();
6292 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6293 tcg_shift
, tcg_fpstatus
);
6295 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6296 tcg_shift
, tcg_fpstatus
);
6298 write_fp_sreg(s
, rd
, tcg_single
);
6299 tcg_temp_free_i32(tcg_single
);
6303 g_assert_not_reached();
6306 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6309 if (extract32(opcode
, 2, 1)) {
6310 /* There are too many rounding modes to all fit into rmode,
6311 * so FCVTA[US] is a special case.
6313 rmode
= FPROUNDING_TIEAWAY
;
6316 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6318 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6321 case 1: /* float64 */
6322 tcg_double
= read_fp_dreg(s
, rn
);
6325 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6326 tcg_shift
, tcg_fpstatus
);
6328 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6329 tcg_shift
, tcg_fpstatus
);
6333 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6334 tcg_shift
, tcg_fpstatus
);
6336 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6337 tcg_shift
, tcg_fpstatus
);
6341 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6343 tcg_temp_free_i64(tcg_double
);
6346 case 0: /* float32 */
6347 tcg_single
= read_fp_sreg(s
, rn
);
6350 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6351 tcg_shift
, tcg_fpstatus
);
6353 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6354 tcg_shift
, tcg_fpstatus
);
6357 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6359 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6360 tcg_shift
, tcg_fpstatus
);
6362 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6363 tcg_shift
, tcg_fpstatus
);
6365 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6366 tcg_temp_free_i32(tcg_dest
);
6368 tcg_temp_free_i32(tcg_single
);
6371 case 3: /* float16 */
6372 tcg_single
= read_fp_sreg(s
, rn
);
6375 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6376 tcg_shift
, tcg_fpstatus
);
6378 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6379 tcg_shift
, tcg_fpstatus
);
6382 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6384 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6385 tcg_shift
, tcg_fpstatus
);
6387 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6388 tcg_shift
, tcg_fpstatus
);
6390 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6391 tcg_temp_free_i32(tcg_dest
);
6393 tcg_temp_free_i32(tcg_single
);
6397 g_assert_not_reached();
6400 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6401 tcg_temp_free_i32(tcg_rmode
);
6404 tcg_temp_free_ptr(tcg_fpstatus
);
6405 tcg_temp_free_i32(tcg_shift
);
6408 /* Floating point <-> fixed point conversions
6409 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6410 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6411 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6412 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6414 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6416 int rd
= extract32(insn
, 0, 5);
6417 int rn
= extract32(insn
, 5, 5);
6418 int scale
= extract32(insn
, 10, 6);
6419 int opcode
= extract32(insn
, 16, 3);
6420 int rmode
= extract32(insn
, 19, 2);
6421 int type
= extract32(insn
, 22, 2);
6422 bool sbit
= extract32(insn
, 29, 1);
6423 bool sf
= extract32(insn
, 31, 1);
6426 if (sbit
|| (!sf
&& scale
< 32)) {
6427 unallocated_encoding(s
);
6432 case 0: /* float32 */
6433 case 1: /* float64 */
6435 case 3: /* float16 */
6436 if (dc_isar_feature(aa64_fp16
, s
)) {
6441 unallocated_encoding(s
);
6445 switch ((rmode
<< 3) | opcode
) {
6446 case 0x2: /* SCVTF */
6447 case 0x3: /* UCVTF */
6450 case 0x18: /* FCVTZS */
6451 case 0x19: /* FCVTZU */
6455 unallocated_encoding(s
);
6459 if (!fp_access_check(s
)) {
6463 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6466 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6468 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6469 * without conversion.
6473 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6479 tmp
= tcg_temp_new_i64();
6480 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6481 write_fp_dreg(s
, rd
, tmp
);
6482 tcg_temp_free_i64(tmp
);
6486 write_fp_dreg(s
, rd
, tcg_rn
);
6489 /* 64 bit to top half. */
6490 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6491 clear_vec_high(s
, true, rd
);
6495 tmp
= tcg_temp_new_i64();
6496 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6497 write_fp_dreg(s
, rd
, tmp
);
6498 tcg_temp_free_i64(tmp
);
6501 g_assert_not_reached();
6504 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6509 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6513 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6516 /* 64 bits from top half */
6517 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6521 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6524 g_assert_not_reached();
6529 /* Floating point <-> integer conversions
6530 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6531 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6532 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6533 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6535 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6537 int rd
= extract32(insn
, 0, 5);
6538 int rn
= extract32(insn
, 5, 5);
6539 int opcode
= extract32(insn
, 16, 3);
6540 int rmode
= extract32(insn
, 19, 2);
6541 int type
= extract32(insn
, 22, 2);
6542 bool sbit
= extract32(insn
, 29, 1);
6543 bool sf
= extract32(insn
, 31, 1);
6546 unallocated_encoding(s
);
6552 bool itof
= opcode
& 1;
6555 unallocated_encoding(s
);
6559 switch (sf
<< 3 | type
<< 1 | rmode
) {
6560 case 0x0: /* 32 bit */
6561 case 0xa: /* 64 bit */
6562 case 0xd: /* 64 bit to top half of quad */
6564 case 0x6: /* 16-bit float, 32-bit int */
6565 case 0xe: /* 16-bit float, 64-bit int */
6566 if (dc_isar_feature(aa64_fp16
, s
)) {
6571 /* all other sf/type/rmode combinations are invalid */
6572 unallocated_encoding(s
);
6576 if (!fp_access_check(s
)) {
6579 handle_fmov(s
, rd
, rn
, type
, itof
);
6581 /* actual FP conversions */
6582 bool itof
= extract32(opcode
, 1, 1);
6584 if (rmode
!= 0 && opcode
> 1) {
6585 unallocated_encoding(s
);
6589 case 0: /* float32 */
6590 case 1: /* float64 */
6592 case 3: /* float16 */
6593 if (dc_isar_feature(aa64_fp16
, s
)) {
6598 unallocated_encoding(s
);
6602 if (!fp_access_check(s
)) {
6605 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6609 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6610 * 31 30 29 28 25 24 0
6611 * +---+---+---+---------+-----------------------------+
6612 * | | 0 | | 1 1 1 1 | |
6613 * +---+---+---+---------+-----------------------------+
6615 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6617 if (extract32(insn
, 24, 1)) {
6618 /* Floating point data-processing (3 source) */
6619 disas_fp_3src(s
, insn
);
6620 } else if (extract32(insn
, 21, 1) == 0) {
6621 /* Floating point to fixed point conversions */
6622 disas_fp_fixed_conv(s
, insn
);
6624 switch (extract32(insn
, 10, 2)) {
6626 /* Floating point conditional compare */
6627 disas_fp_ccomp(s
, insn
);
6630 /* Floating point data-processing (2 source) */
6631 disas_fp_2src(s
, insn
);
6634 /* Floating point conditional select */
6635 disas_fp_csel(s
, insn
);
6638 switch (ctz32(extract32(insn
, 12, 4))) {
6639 case 0: /* [15:12] == xxx1 */
6640 /* Floating point immediate */
6641 disas_fp_imm(s
, insn
);
6643 case 1: /* [15:12] == xx10 */
6644 /* Floating point compare */
6645 disas_fp_compare(s
, insn
);
6647 case 2: /* [15:12] == x100 */
6648 /* Floating point data-processing (1 source) */
6649 disas_fp_1src(s
, insn
);
6651 case 3: /* [15:12] == 1000 */
6652 unallocated_encoding(s
);
6654 default: /* [15:12] == 0000 */
6655 /* Floating point <-> integer conversions */
6656 disas_fp_int_conv(s
, insn
);
6664 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6667 /* Extract 64 bits from the middle of two concatenated 64 bit
6668 * vector register slices left:right. The extracted bits start
6669 * at 'pos' bits into the right (least significant) side.
6670 * We return the result in tcg_right, and guarantee not to
6673 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6674 assert(pos
> 0 && pos
< 64);
6676 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6677 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6678 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6680 tcg_temp_free_i64(tcg_tmp
);
6684 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6685 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6686 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6687 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6689 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6691 int is_q
= extract32(insn
, 30, 1);
6692 int op2
= extract32(insn
, 22, 2);
6693 int imm4
= extract32(insn
, 11, 4);
6694 int rm
= extract32(insn
, 16, 5);
6695 int rn
= extract32(insn
, 5, 5);
6696 int rd
= extract32(insn
, 0, 5);
6697 int pos
= imm4
<< 3;
6698 TCGv_i64 tcg_resl
, tcg_resh
;
6700 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6701 unallocated_encoding(s
);
6705 if (!fp_access_check(s
)) {
6709 tcg_resh
= tcg_temp_new_i64();
6710 tcg_resl
= tcg_temp_new_i64();
6712 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6713 * either extracting 128 bits from a 128:128 concatenation, or
6714 * extracting 64 bits from a 64:64 concatenation.
6717 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6719 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6720 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6722 tcg_gen_movi_i64(tcg_resh
, 0);
6729 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6730 EltPosns
*elt
= eltposns
;
6737 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6739 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6742 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6743 tcg_hh
= tcg_temp_new_i64();
6744 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6745 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6746 tcg_temp_free_i64(tcg_hh
);
6750 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6751 tcg_temp_free_i64(tcg_resl
);
6752 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6753 tcg_temp_free_i64(tcg_resh
);
6757 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6758 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6759 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6760 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6762 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6764 int op2
= extract32(insn
, 22, 2);
6765 int is_q
= extract32(insn
, 30, 1);
6766 int rm
= extract32(insn
, 16, 5);
6767 int rn
= extract32(insn
, 5, 5);
6768 int rd
= extract32(insn
, 0, 5);
6769 int is_tblx
= extract32(insn
, 12, 1);
6770 int len
= extract32(insn
, 13, 2);
6771 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6772 TCGv_i32 tcg_regno
, tcg_numregs
;
6775 unallocated_encoding(s
);
6779 if (!fp_access_check(s
)) {
6783 /* This does a table lookup: for every byte element in the input
6784 * we index into a table formed from up to four vector registers,
6785 * and then the output is the result of the lookups. Our helper
6786 * function does the lookup operation for a single 64 bit part of
6789 tcg_resl
= tcg_temp_new_i64();
6790 tcg_resh
= tcg_temp_new_i64();
6793 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6795 tcg_gen_movi_i64(tcg_resl
, 0);
6797 if (is_tblx
&& is_q
) {
6798 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6800 tcg_gen_movi_i64(tcg_resh
, 0);
6803 tcg_idx
= tcg_temp_new_i64();
6804 tcg_regno
= tcg_const_i32(rn
);
6805 tcg_numregs
= tcg_const_i32(len
+ 1);
6806 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6807 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6808 tcg_regno
, tcg_numregs
);
6810 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6811 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6812 tcg_regno
, tcg_numregs
);
6814 tcg_temp_free_i64(tcg_idx
);
6815 tcg_temp_free_i32(tcg_regno
);
6816 tcg_temp_free_i32(tcg_numregs
);
6818 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6819 tcg_temp_free_i64(tcg_resl
);
6820 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6821 tcg_temp_free_i64(tcg_resh
);
6825 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6826 * +---+---+-------------+------+---+------+---+------------------+------+
6827 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6828 * +---+---+-------------+------+---+------+---+------------------+------+
6830 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6832 int rd
= extract32(insn
, 0, 5);
6833 int rn
= extract32(insn
, 5, 5);
6834 int rm
= extract32(insn
, 16, 5);
6835 int size
= extract32(insn
, 22, 2);
6836 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6837 * bit 2 indicates 1 vs 2 variant of the insn.
6839 int opcode
= extract32(insn
, 12, 2);
6840 bool part
= extract32(insn
, 14, 1);
6841 bool is_q
= extract32(insn
, 30, 1);
6842 int esize
= 8 << size
;
6844 int datasize
= is_q
? 128 : 64;
6845 int elements
= datasize
/ esize
;
6846 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6848 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6849 unallocated_encoding(s
);
6853 if (!fp_access_check(s
)) {
6857 tcg_resl
= tcg_const_i64(0);
6858 tcg_resh
= tcg_const_i64(0);
6859 tcg_res
= tcg_temp_new_i64();
6861 for (i
= 0; i
< elements
; i
++) {
6863 case 1: /* UZP1/2 */
6865 int midpoint
= elements
/ 2;
6867 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6869 read_vec_element(s
, tcg_res
, rm
,
6870 2 * (i
- midpoint
) + part
, size
);
6874 case 2: /* TRN1/2 */
6876 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6878 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6881 case 3: /* ZIP1/2 */
6883 int base
= part
* elements
/ 2;
6885 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6887 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6892 g_assert_not_reached();
6897 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6898 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6900 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6901 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6905 tcg_temp_free_i64(tcg_res
);
6907 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6908 tcg_temp_free_i64(tcg_resl
);
6909 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6910 tcg_temp_free_i64(tcg_resh
);
6914 * do_reduction_op helper
6916 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6917 * important for correct NaN propagation that we do these
6918 * operations in exactly the order specified by the pseudocode.
6920 * This is a recursive function, TCG temps should be freed by the
6921 * calling function once it is done with the values.
6923 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6924 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6926 if (esize
== size
) {
6928 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6931 /* We should have one register left here */
6932 assert(ctpop8(vmap
) == 1);
6933 element
= ctz32(vmap
);
6934 assert(element
< 8);
6936 tcg_elem
= tcg_temp_new_i32();
6937 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6940 int bits
= size
/ 2;
6941 int shift
= ctpop8(vmap
) / 2;
6942 int vmap_lo
= (vmap
>> shift
) & vmap
;
6943 int vmap_hi
= (vmap
& ~vmap_lo
);
6944 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6946 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6947 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6948 tcg_res
= tcg_temp_new_i32();
6951 case 0x0c: /* fmaxnmv half-precision */
6952 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6954 case 0x0f: /* fmaxv half-precision */
6955 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6957 case 0x1c: /* fminnmv half-precision */
6958 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6960 case 0x1f: /* fminv half-precision */
6961 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6963 case 0x2c: /* fmaxnmv */
6964 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6966 case 0x2f: /* fmaxv */
6967 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6969 case 0x3c: /* fminnmv */
6970 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6972 case 0x3f: /* fminv */
6973 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6976 g_assert_not_reached();
6979 tcg_temp_free_i32(tcg_hi
);
6980 tcg_temp_free_i32(tcg_lo
);
6985 /* AdvSIMD across lanes
6986 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6987 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6988 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6989 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6991 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6993 int rd
= extract32(insn
, 0, 5);
6994 int rn
= extract32(insn
, 5, 5);
6995 int size
= extract32(insn
, 22, 2);
6996 int opcode
= extract32(insn
, 12, 5);
6997 bool is_q
= extract32(insn
, 30, 1);
6998 bool is_u
= extract32(insn
, 29, 1);
7000 bool is_min
= false;
7004 TCGv_i64 tcg_res
, tcg_elt
;
7007 case 0x1b: /* ADDV */
7009 unallocated_encoding(s
);
7013 case 0x3: /* SADDLV, UADDLV */
7014 case 0xa: /* SMAXV, UMAXV */
7015 case 0x1a: /* SMINV, UMINV */
7016 if (size
== 3 || (size
== 2 && !is_q
)) {
7017 unallocated_encoding(s
);
7021 case 0xc: /* FMAXNMV, FMINNMV */
7022 case 0xf: /* FMAXV, FMINV */
7023 /* Bit 1 of size field encodes min vs max and the actual size
7024 * depends on the encoding of the U bit. If not set (and FP16
7025 * enabled) then we do half-precision float instead of single
7028 is_min
= extract32(size
, 1, 1);
7030 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7032 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7033 unallocated_encoding(s
);
7040 unallocated_encoding(s
);
7044 if (!fp_access_check(s
)) {
7049 elements
= (is_q
? 128 : 64) / esize
;
7051 tcg_res
= tcg_temp_new_i64();
7052 tcg_elt
= tcg_temp_new_i64();
7054 /* These instructions operate across all lanes of a vector
7055 * to produce a single result. We can guarantee that a 64
7056 * bit intermediate is sufficient:
7057 * + for [US]ADDLV the maximum element size is 32 bits, and
7058 * the result type is 64 bits
7059 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7060 * same as the element size, which is 32 bits at most
7061 * For the integer operations we can choose to work at 64
7062 * or 32 bits and truncate at the end; for simplicity
7063 * we use 64 bits always. The floating point
7064 * ops do require 32 bit intermediates, though.
7067 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7069 for (i
= 1; i
< elements
; i
++) {
7070 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7073 case 0x03: /* SADDLV / UADDLV */
7074 case 0x1b: /* ADDV */
7075 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7077 case 0x0a: /* SMAXV / UMAXV */
7079 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7081 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7084 case 0x1a: /* SMINV / UMINV */
7086 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7088 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7092 g_assert_not_reached();
7097 /* Floating point vector reduction ops which work across 32
7098 * bit (single) or 16 bit (half-precision) intermediates.
7099 * Note that correct NaN propagation requires that we do these
7100 * operations in exactly the order specified by the pseudocode.
7102 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7103 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7104 int vmap
= (1 << elements
) - 1;
7105 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7106 (is_q
? 128 : 64), vmap
, fpst
);
7107 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7108 tcg_temp_free_i32(tcg_res32
);
7109 tcg_temp_free_ptr(fpst
);
7112 tcg_temp_free_i64(tcg_elt
);
7114 /* Now truncate the result to the width required for the final output */
7115 if (opcode
== 0x03) {
7116 /* SADDLV, UADDLV: result is 2*esize */
7122 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7125 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7128 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7133 g_assert_not_reached();
7136 write_fp_dreg(s
, rd
, tcg_res
);
7137 tcg_temp_free_i64(tcg_res
);
7140 /* DUP (Element, Vector)
7142 * 31 30 29 21 20 16 15 10 9 5 4 0
7143 * +---+---+-------------------+--------+-------------+------+------+
7144 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7145 * +---+---+-------------------+--------+-------------+------+------+
7147 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7149 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7152 int size
= ctz32(imm5
);
7153 int index
= imm5
>> (size
+ 1);
7155 if (size
> 3 || (size
== 3 && !is_q
)) {
7156 unallocated_encoding(s
);
7160 if (!fp_access_check(s
)) {
7164 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7165 vec_reg_offset(s
, rn
, index
, size
),
7166 is_q
? 16 : 8, vec_full_reg_size(s
));
7169 /* DUP (element, scalar)
7170 * 31 21 20 16 15 10 9 5 4 0
7171 * +-----------------------+--------+-------------+------+------+
7172 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7173 * +-----------------------+--------+-------------+------+------+
7175 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7178 int size
= ctz32(imm5
);
7183 unallocated_encoding(s
);
7187 if (!fp_access_check(s
)) {
7191 index
= imm5
>> (size
+ 1);
7193 /* This instruction just extracts the specified element and
7194 * zero-extends it into the bottom of the destination register.
7196 tmp
= tcg_temp_new_i64();
7197 read_vec_element(s
, tmp
, rn
, index
, size
);
7198 write_fp_dreg(s
, rd
, tmp
);
7199 tcg_temp_free_i64(tmp
);
7204 * 31 30 29 21 20 16 15 10 9 5 4 0
7205 * +---+---+-------------------+--------+-------------+------+------+
7206 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7207 * +---+---+-------------------+--------+-------------+------+------+
7209 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7211 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7214 int size
= ctz32(imm5
);
7215 uint32_t dofs
, oprsz
, maxsz
;
7217 if (size
> 3 || ((size
== 3) && !is_q
)) {
7218 unallocated_encoding(s
);
7222 if (!fp_access_check(s
)) {
7226 dofs
= vec_full_reg_offset(s
, rd
);
7227 oprsz
= is_q
? 16 : 8;
7228 maxsz
= vec_full_reg_size(s
);
7230 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7235 * 31 21 20 16 15 14 11 10 9 5 4 0
7236 * +-----------------------+--------+------------+---+------+------+
7237 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7238 * +-----------------------+--------+------------+---+------+------+
7240 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7241 * index: encoded in imm5<4:size+1>
7243 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7246 int size
= ctz32(imm5
);
7247 int src_index
, dst_index
;
7251 unallocated_encoding(s
);
7255 if (!fp_access_check(s
)) {
7259 dst_index
= extract32(imm5
, 1+size
, 5);
7260 src_index
= extract32(imm4
, size
, 4);
7262 tmp
= tcg_temp_new_i64();
7264 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7265 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7267 tcg_temp_free_i64(tmp
);
7273 * 31 21 20 16 15 10 9 5 4 0
7274 * +-----------------------+--------+-------------+------+------+
7275 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7276 * +-----------------------+--------+-------------+------+------+
7278 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7279 * index: encoded in imm5<4:size+1>
7281 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7283 int size
= ctz32(imm5
);
7287 unallocated_encoding(s
);
7291 if (!fp_access_check(s
)) {
7295 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7296 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7303 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7304 * +---+---+-------------------+--------+-------------+------+------+
7305 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7306 * +---+---+-------------------+--------+-------------+------+------+
7308 * U: unsigned when set
7309 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7311 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7312 int rn
, int rd
, int imm5
)
7314 int size
= ctz32(imm5
);
7318 /* Check for UnallocatedEncodings */
7320 if (size
> 2 || (size
== 2 && !is_q
)) {
7321 unallocated_encoding(s
);
7326 || (size
< 3 && is_q
)
7327 || (size
== 3 && !is_q
)) {
7328 unallocated_encoding(s
);
7333 if (!fp_access_check(s
)) {
7337 element
= extract32(imm5
, 1+size
, 4);
7339 tcg_rd
= cpu_reg(s
, rd
);
7340 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7341 if (is_signed
&& !is_q
) {
7342 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7347 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7348 * +---+---+----+-----------------+------+---+------+---+------+------+
7349 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7350 * +---+---+----+-----------------+------+---+------+---+------+------+
7352 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7354 int rd
= extract32(insn
, 0, 5);
7355 int rn
= extract32(insn
, 5, 5);
7356 int imm4
= extract32(insn
, 11, 4);
7357 int op
= extract32(insn
, 29, 1);
7358 int is_q
= extract32(insn
, 30, 1);
7359 int imm5
= extract32(insn
, 16, 5);
7364 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7366 unallocated_encoding(s
);
7371 /* DUP (element - vector) */
7372 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7376 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7381 handle_simd_insg(s
, rd
, rn
, imm5
);
7383 unallocated_encoding(s
);
7388 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7389 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7392 unallocated_encoding(s
);
7398 /* AdvSIMD modified immediate
7399 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7400 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7401 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7402 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7404 * There are a number of operations that can be carried out here:
7405 * MOVI - move (shifted) imm into register
7406 * MVNI - move inverted (shifted) imm into register
7407 * ORR - bitwise OR of (shifted) imm with register
7408 * BIC - bitwise clear of (shifted) imm with register
7409 * With ARMv8.2 we also have:
7410 * FMOV half-precision
7412 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7414 int rd
= extract32(insn
, 0, 5);
7415 int cmode
= extract32(insn
, 12, 4);
7416 int cmode_3_1
= extract32(cmode
, 1, 3);
7417 int cmode_0
= extract32(cmode
, 0, 1);
7418 int o2
= extract32(insn
, 11, 1);
7419 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7420 bool is_neg
= extract32(insn
, 29, 1);
7421 bool is_q
= extract32(insn
, 30, 1);
7424 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7425 /* Check for FMOV (vector, immediate) - half-precision */
7426 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7427 unallocated_encoding(s
);
7432 if (!fp_access_check(s
)) {
7436 /* See AdvSIMDExpandImm() in ARM ARM */
7437 switch (cmode_3_1
) {
7438 case 0: /* Replicate(Zeros(24):imm8, 2) */
7439 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7440 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7441 case 3: /* Replicate(imm8:Zeros(24), 2) */
7443 int shift
= cmode_3_1
* 8;
7444 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7447 case 4: /* Replicate(Zeros(8):imm8, 4) */
7448 case 5: /* Replicate(imm8:Zeros(8), 4) */
7450 int shift
= (cmode_3_1
& 0x1) * 8;
7451 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7456 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7457 imm
= (abcdefgh
<< 16) | 0xffff;
7459 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7460 imm
= (abcdefgh
<< 8) | 0xff;
7462 imm
= bitfield_replicate(imm
, 32);
7465 if (!cmode_0
&& !is_neg
) {
7466 imm
= bitfield_replicate(abcdefgh
, 8);
7467 } else if (!cmode_0
&& is_neg
) {
7470 for (i
= 0; i
< 8; i
++) {
7471 if ((abcdefgh
) & (1 << i
)) {
7472 imm
|= 0xffULL
<< (i
* 8);
7475 } else if (cmode_0
) {
7477 imm
= (abcdefgh
& 0x3f) << 48;
7478 if (abcdefgh
& 0x80) {
7479 imm
|= 0x8000000000000000ULL
;
7481 if (abcdefgh
& 0x40) {
7482 imm
|= 0x3fc0000000000000ULL
;
7484 imm
|= 0x4000000000000000ULL
;
7488 /* FMOV (vector, immediate) - half-precision */
7489 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7490 /* now duplicate across the lanes */
7491 imm
= bitfield_replicate(imm
, 16);
7493 imm
= (abcdefgh
& 0x3f) << 19;
7494 if (abcdefgh
& 0x80) {
7497 if (abcdefgh
& 0x40) {
7508 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7509 g_assert_not_reached();
7512 if (cmode_3_1
!= 7 && is_neg
) {
7516 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7517 /* MOVI or MVNI, with MVNI negation handled above. */
7518 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7519 vec_full_reg_size(s
), imm
);
7521 /* ORR or BIC, with BIC negation to AND handled above. */
7523 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7525 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7530 /* AdvSIMD scalar copy
7531 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7532 * +-----+----+-----------------+------+---+------+---+------+------+
7533 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7534 * +-----+----+-----------------+------+---+------+---+------+------+
7536 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7538 int rd
= extract32(insn
, 0, 5);
7539 int rn
= extract32(insn
, 5, 5);
7540 int imm4
= extract32(insn
, 11, 4);
7541 int imm5
= extract32(insn
, 16, 5);
7542 int op
= extract32(insn
, 29, 1);
7544 if (op
!= 0 || imm4
!= 0) {
7545 unallocated_encoding(s
);
7549 /* DUP (element, scalar) */
7550 handle_simd_dupes(s
, rd
, rn
, imm5
);
7553 /* AdvSIMD scalar pairwise
7554 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7555 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7556 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7557 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7559 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7561 int u
= extract32(insn
, 29, 1);
7562 int size
= extract32(insn
, 22, 2);
7563 int opcode
= extract32(insn
, 12, 5);
7564 int rn
= extract32(insn
, 5, 5);
7565 int rd
= extract32(insn
, 0, 5);
7568 /* For some ops (the FP ones), size[1] is part of the encoding.
7569 * For ADDP strictly it is not but size[1] is always 1 for valid
7572 opcode
|= (extract32(size
, 1, 1) << 5);
7575 case 0x3b: /* ADDP */
7576 if (u
|| size
!= 3) {
7577 unallocated_encoding(s
);
7580 if (!fp_access_check(s
)) {
7586 case 0xc: /* FMAXNMP */
7587 case 0xd: /* FADDP */
7588 case 0xf: /* FMAXP */
7589 case 0x2c: /* FMINNMP */
7590 case 0x2f: /* FMINP */
7591 /* FP op, size[0] is 32 or 64 bit*/
7593 if (!dc_isar_feature(aa64_fp16
, s
)) {
7594 unallocated_encoding(s
);
7600 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7603 if (!fp_access_check(s
)) {
7607 fpst
= get_fpstatus_ptr(size
== MO_16
);
7610 unallocated_encoding(s
);
7614 if (size
== MO_64
) {
7615 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7616 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7617 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7619 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7620 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7623 case 0x3b: /* ADDP */
7624 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7626 case 0xc: /* FMAXNMP */
7627 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7629 case 0xd: /* FADDP */
7630 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7632 case 0xf: /* FMAXP */
7633 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7635 case 0x2c: /* FMINNMP */
7636 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7638 case 0x2f: /* FMINP */
7639 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7642 g_assert_not_reached();
7645 write_fp_dreg(s
, rd
, tcg_res
);
7647 tcg_temp_free_i64(tcg_op1
);
7648 tcg_temp_free_i64(tcg_op2
);
7649 tcg_temp_free_i64(tcg_res
);
7651 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7652 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7653 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7655 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7656 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7658 if (size
== MO_16
) {
7660 case 0xc: /* FMAXNMP */
7661 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7663 case 0xd: /* FADDP */
7664 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7666 case 0xf: /* FMAXP */
7667 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7669 case 0x2c: /* FMINNMP */
7670 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7672 case 0x2f: /* FMINP */
7673 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7676 g_assert_not_reached();
7680 case 0xc: /* FMAXNMP */
7681 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7683 case 0xd: /* FADDP */
7684 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7686 case 0xf: /* FMAXP */
7687 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7689 case 0x2c: /* FMINNMP */
7690 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7692 case 0x2f: /* FMINP */
7693 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7696 g_assert_not_reached();
7700 write_fp_sreg(s
, rd
, tcg_res
);
7702 tcg_temp_free_i32(tcg_op1
);
7703 tcg_temp_free_i32(tcg_op2
);
7704 tcg_temp_free_i32(tcg_res
);
7708 tcg_temp_free_ptr(fpst
);
7713 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7715 * This code is handles the common shifting code and is used by both
7716 * the vector and scalar code.
7718 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7719 TCGv_i64 tcg_rnd
, bool accumulate
,
7720 bool is_u
, int size
, int shift
)
7722 bool extended_result
= false;
7723 bool round
= tcg_rnd
!= NULL
;
7725 TCGv_i64 tcg_src_hi
;
7727 if (round
&& size
== 3) {
7728 extended_result
= true;
7729 ext_lshift
= 64 - shift
;
7730 tcg_src_hi
= tcg_temp_new_i64();
7731 } else if (shift
== 64) {
7732 if (!accumulate
&& is_u
) {
7733 /* result is zero */
7734 tcg_gen_movi_i64(tcg_res
, 0);
7739 /* Deal with the rounding step */
7741 if (extended_result
) {
7742 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7744 /* take care of sign extending tcg_res */
7745 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7746 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7747 tcg_src
, tcg_src_hi
,
7750 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7754 tcg_temp_free_i64(tcg_zero
);
7756 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7760 /* Now do the shift right */
7761 if (round
&& extended_result
) {
7762 /* extended case, >64 bit precision required */
7763 if (ext_lshift
== 0) {
7764 /* special case, only high bits matter */
7765 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7767 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7768 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7769 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7774 /* essentially shifting in 64 zeros */
7775 tcg_gen_movi_i64(tcg_src
, 0);
7777 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7781 /* effectively extending the sign-bit */
7782 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7784 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7790 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7792 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7795 if (extended_result
) {
7796 tcg_temp_free_i64(tcg_src_hi
);
7800 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7801 static void handle_scalar_simd_shri(DisasContext
*s
,
7802 bool is_u
, int immh
, int immb
,
7803 int opcode
, int rn
, int rd
)
7806 int immhb
= immh
<< 3 | immb
;
7807 int shift
= 2 * (8 << size
) - immhb
;
7808 bool accumulate
= false;
7810 bool insert
= false;
7815 if (!extract32(immh
, 3, 1)) {
7816 unallocated_encoding(s
);
7820 if (!fp_access_check(s
)) {
7825 case 0x02: /* SSRA / USRA (accumulate) */
7828 case 0x04: /* SRSHR / URSHR (rounding) */
7831 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7832 accumulate
= round
= true;
7834 case 0x08: /* SRI */
7840 uint64_t round_const
= 1ULL << (shift
- 1);
7841 tcg_round
= tcg_const_i64(round_const
);
7846 tcg_rn
= read_fp_dreg(s
, rn
);
7847 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7850 /* shift count same as element size is valid but does nothing;
7851 * special case to avoid potential shift by 64.
7853 int esize
= 8 << size
;
7854 if (shift
!= esize
) {
7855 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7856 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7859 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7860 accumulate
, is_u
, size
, shift
);
7863 write_fp_dreg(s
, rd
, tcg_rd
);
7865 tcg_temp_free_i64(tcg_rn
);
7866 tcg_temp_free_i64(tcg_rd
);
7868 tcg_temp_free_i64(tcg_round
);
7872 /* SHL/SLI - Scalar shift left */
7873 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7874 int immh
, int immb
, int opcode
,
7877 int size
= 32 - clz32(immh
) - 1;
7878 int immhb
= immh
<< 3 | immb
;
7879 int shift
= immhb
- (8 << size
);
7880 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7881 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7883 if (!extract32(immh
, 3, 1)) {
7884 unallocated_encoding(s
);
7888 if (!fp_access_check(s
)) {
7892 tcg_rn
= read_fp_dreg(s
, rn
);
7893 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7896 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7898 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7901 write_fp_dreg(s
, rd
, tcg_rd
);
7903 tcg_temp_free_i64(tcg_rn
);
7904 tcg_temp_free_i64(tcg_rd
);
7907 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7908 * (signed/unsigned) narrowing */
7909 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7910 bool is_u_shift
, bool is_u_narrow
,
7911 int immh
, int immb
, int opcode
,
7914 int immhb
= immh
<< 3 | immb
;
7915 int size
= 32 - clz32(immh
) - 1;
7916 int esize
= 8 << size
;
7917 int shift
= (2 * esize
) - immhb
;
7918 int elements
= is_scalar
? 1 : (64 / esize
);
7919 bool round
= extract32(opcode
, 0, 1);
7920 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7921 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7922 TCGv_i32 tcg_rd_narrowed
;
7925 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7926 { gen_helper_neon_narrow_sat_s8
,
7927 gen_helper_neon_unarrow_sat8
},
7928 { gen_helper_neon_narrow_sat_s16
,
7929 gen_helper_neon_unarrow_sat16
},
7930 { gen_helper_neon_narrow_sat_s32
,
7931 gen_helper_neon_unarrow_sat32
},
7934 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7935 gen_helper_neon_narrow_sat_u8
,
7936 gen_helper_neon_narrow_sat_u16
,
7937 gen_helper_neon_narrow_sat_u32
,
7940 NeonGenNarrowEnvFn
*narrowfn
;
7946 if (extract32(immh
, 3, 1)) {
7947 unallocated_encoding(s
);
7951 if (!fp_access_check(s
)) {
7956 narrowfn
= unsigned_narrow_fns
[size
];
7958 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7961 tcg_rn
= tcg_temp_new_i64();
7962 tcg_rd
= tcg_temp_new_i64();
7963 tcg_rd_narrowed
= tcg_temp_new_i32();
7964 tcg_final
= tcg_const_i64(0);
7967 uint64_t round_const
= 1ULL << (shift
- 1);
7968 tcg_round
= tcg_const_i64(round_const
);
7973 for (i
= 0; i
< elements
; i
++) {
7974 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7975 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7976 false, is_u_shift
, size
+1, shift
);
7977 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7978 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7979 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7983 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7985 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7989 tcg_temp_free_i64(tcg_round
);
7991 tcg_temp_free_i64(tcg_rn
);
7992 tcg_temp_free_i64(tcg_rd
);
7993 tcg_temp_free_i32(tcg_rd_narrowed
);
7994 tcg_temp_free_i64(tcg_final
);
7996 clear_vec_high(s
, is_q
, rd
);
7999 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8000 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8001 bool src_unsigned
, bool dst_unsigned
,
8002 int immh
, int immb
, int rn
, int rd
)
8004 int immhb
= immh
<< 3 | immb
;
8005 int size
= 32 - clz32(immh
) - 1;
8006 int shift
= immhb
- (8 << size
);
8010 assert(!(scalar
&& is_q
));
8013 if (!is_q
&& extract32(immh
, 3, 1)) {
8014 unallocated_encoding(s
);
8018 /* Since we use the variable-shift helpers we must
8019 * replicate the shift count into each element of
8020 * the tcg_shift value.
8024 shift
|= shift
<< 8;
8027 shift
|= shift
<< 16;
8033 g_assert_not_reached();
8037 if (!fp_access_check(s
)) {
8042 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8043 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8044 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8045 { NULL
, gen_helper_neon_qshl_u64
},
8047 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8048 int maxpass
= is_q
? 2 : 1;
8050 for (pass
= 0; pass
< maxpass
; pass
++) {
8051 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8053 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8054 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8055 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8057 tcg_temp_free_i64(tcg_op
);
8059 tcg_temp_free_i64(tcg_shift
);
8060 clear_vec_high(s
, is_q
, rd
);
8062 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8063 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8065 { gen_helper_neon_qshl_s8
,
8066 gen_helper_neon_qshl_s16
,
8067 gen_helper_neon_qshl_s32
},
8068 { gen_helper_neon_qshlu_s8
,
8069 gen_helper_neon_qshlu_s16
,
8070 gen_helper_neon_qshlu_s32
}
8072 { NULL
, NULL
, NULL
},
8073 { gen_helper_neon_qshl_u8
,
8074 gen_helper_neon_qshl_u16
,
8075 gen_helper_neon_qshl_u32
}
8078 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8079 TCGMemOp memop
= scalar
? size
: MO_32
;
8080 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8082 for (pass
= 0; pass
< maxpass
; pass
++) {
8083 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8085 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8086 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8090 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8093 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8098 g_assert_not_reached();
8100 write_fp_sreg(s
, rd
, tcg_op
);
8102 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8105 tcg_temp_free_i32(tcg_op
);
8107 tcg_temp_free_i32(tcg_shift
);
8110 clear_vec_high(s
, is_q
, rd
);
8115 /* Common vector code for handling integer to FP conversion */
8116 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8117 int elements
, int is_signed
,
8118 int fracbits
, int size
)
8120 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8121 TCGv_i32 tcg_shift
= NULL
;
8123 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8126 if (fracbits
|| size
== MO_64
) {
8127 tcg_shift
= tcg_const_i32(fracbits
);
8130 if (size
== MO_64
) {
8131 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8132 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8134 for (pass
= 0; pass
< elements
; pass
++) {
8135 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8138 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8139 tcg_shift
, tcg_fpst
);
8141 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8142 tcg_shift
, tcg_fpst
);
8144 if (elements
== 1) {
8145 write_fp_dreg(s
, rd
, tcg_double
);
8147 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8151 tcg_temp_free_i64(tcg_int64
);
8152 tcg_temp_free_i64(tcg_double
);
8155 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8156 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8158 for (pass
= 0; pass
< elements
; pass
++) {
8159 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8165 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8166 tcg_shift
, tcg_fpst
);
8168 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8169 tcg_shift
, tcg_fpst
);
8173 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8175 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8182 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8183 tcg_shift
, tcg_fpst
);
8185 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8186 tcg_shift
, tcg_fpst
);
8190 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8192 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8197 g_assert_not_reached();
8200 if (elements
== 1) {
8201 write_fp_sreg(s
, rd
, tcg_float
);
8203 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8207 tcg_temp_free_i32(tcg_int32
);
8208 tcg_temp_free_i32(tcg_float
);
8211 tcg_temp_free_ptr(tcg_fpst
);
8213 tcg_temp_free_i32(tcg_shift
);
8216 clear_vec_high(s
, elements
<< size
== 16, rd
);
8219 /* UCVTF/SCVTF - Integer to FP conversion */
8220 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8221 bool is_q
, bool is_u
,
8222 int immh
, int immb
, int opcode
,
8225 int size
, elements
, fracbits
;
8226 int immhb
= immh
<< 3 | immb
;
8230 if (!is_scalar
&& !is_q
) {
8231 unallocated_encoding(s
);
8234 } else if (immh
& 4) {
8236 } else if (immh
& 2) {
8238 if (!dc_isar_feature(aa64_fp16
, s
)) {
8239 unallocated_encoding(s
);
8243 /* immh == 0 would be a failure of the decode logic */
8244 g_assert(immh
== 1);
8245 unallocated_encoding(s
);
8252 elements
= (8 << is_q
) >> size
;
8254 fracbits
= (16 << size
) - immhb
;
8256 if (!fp_access_check(s
)) {
8260 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8263 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8264 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8265 bool is_q
, bool is_u
,
8266 int immh
, int immb
, int rn
, int rd
)
8268 int immhb
= immh
<< 3 | immb
;
8269 int pass
, size
, fracbits
;
8270 TCGv_ptr tcg_fpstatus
;
8271 TCGv_i32 tcg_rmode
, tcg_shift
;
8275 if (!is_scalar
&& !is_q
) {
8276 unallocated_encoding(s
);
8279 } else if (immh
& 0x4) {
8281 } else if (immh
& 0x2) {
8283 if (!dc_isar_feature(aa64_fp16
, s
)) {
8284 unallocated_encoding(s
);
8288 /* Should have split out AdvSIMD modified immediate earlier. */
8290 unallocated_encoding(s
);
8294 if (!fp_access_check(s
)) {
8298 assert(!(is_scalar
&& is_q
));
8300 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8301 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8302 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8303 fracbits
= (16 << size
) - immhb
;
8304 tcg_shift
= tcg_const_i32(fracbits
);
8306 if (size
== MO_64
) {
8307 int maxpass
= is_scalar
? 1 : 2;
8309 for (pass
= 0; pass
< maxpass
; pass
++) {
8310 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8312 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8314 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8316 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8318 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8319 tcg_temp_free_i64(tcg_op
);
8321 clear_vec_high(s
, is_q
, rd
);
8323 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8324 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8329 fn
= gen_helper_vfp_touhh
;
8331 fn
= gen_helper_vfp_toshh
;
8336 fn
= gen_helper_vfp_touls
;
8338 fn
= gen_helper_vfp_tosls
;
8342 g_assert_not_reached();
8345 for (pass
= 0; pass
< maxpass
; pass
++) {
8346 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8348 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8349 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8351 write_fp_sreg(s
, rd
, tcg_op
);
8353 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8355 tcg_temp_free_i32(tcg_op
);
8358 clear_vec_high(s
, is_q
, rd
);
8362 tcg_temp_free_ptr(tcg_fpstatus
);
8363 tcg_temp_free_i32(tcg_shift
);
8364 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8365 tcg_temp_free_i32(tcg_rmode
);
8368 /* AdvSIMD scalar shift by immediate
8369 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8370 * +-----+---+-------------+------+------+--------+---+------+------+
8371 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8372 * +-----+---+-------------+------+------+--------+---+------+------+
8374 * This is the scalar version so it works on a fixed sized registers
8376 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8378 int rd
= extract32(insn
, 0, 5);
8379 int rn
= extract32(insn
, 5, 5);
8380 int opcode
= extract32(insn
, 11, 5);
8381 int immb
= extract32(insn
, 16, 3);
8382 int immh
= extract32(insn
, 19, 4);
8383 bool is_u
= extract32(insn
, 29, 1);
8386 unallocated_encoding(s
);
8391 case 0x08: /* SRI */
8393 unallocated_encoding(s
);
8397 case 0x00: /* SSHR / USHR */
8398 case 0x02: /* SSRA / USRA */
8399 case 0x04: /* SRSHR / URSHR */
8400 case 0x06: /* SRSRA / URSRA */
8401 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8403 case 0x0a: /* SHL / SLI */
8404 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8406 case 0x1c: /* SCVTF, UCVTF */
8407 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8410 case 0x10: /* SQSHRUN, SQSHRUN2 */
8411 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8413 unallocated_encoding(s
);
8416 handle_vec_simd_sqshrn(s
, true, false, false, true,
8417 immh
, immb
, opcode
, rn
, rd
);
8419 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8420 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8421 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8422 immh
, immb
, opcode
, rn
, rd
);
8424 case 0xc: /* SQSHLU */
8426 unallocated_encoding(s
);
8429 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8431 case 0xe: /* SQSHL, UQSHL */
8432 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8434 case 0x1f: /* FCVTZS, FCVTZU */
8435 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8438 unallocated_encoding(s
);
8443 /* AdvSIMD scalar three different
8444 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8445 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8446 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8447 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8449 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8451 bool is_u
= extract32(insn
, 29, 1);
8452 int size
= extract32(insn
, 22, 2);
8453 int opcode
= extract32(insn
, 12, 4);
8454 int rm
= extract32(insn
, 16, 5);
8455 int rn
= extract32(insn
, 5, 5);
8456 int rd
= extract32(insn
, 0, 5);
8459 unallocated_encoding(s
);
8464 case 0x9: /* SQDMLAL, SQDMLAL2 */
8465 case 0xb: /* SQDMLSL, SQDMLSL2 */
8466 case 0xd: /* SQDMULL, SQDMULL2 */
8467 if (size
== 0 || size
== 3) {
8468 unallocated_encoding(s
);
8473 unallocated_encoding(s
);
8477 if (!fp_access_check(s
)) {
8482 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8483 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8484 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8486 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8487 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8489 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8490 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8493 case 0xd: /* SQDMULL, SQDMULL2 */
8495 case 0xb: /* SQDMLSL, SQDMLSL2 */
8496 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8498 case 0x9: /* SQDMLAL, SQDMLAL2 */
8499 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8500 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8504 g_assert_not_reached();
8507 write_fp_dreg(s
, rd
, tcg_res
);
8509 tcg_temp_free_i64(tcg_op1
);
8510 tcg_temp_free_i64(tcg_op2
);
8511 tcg_temp_free_i64(tcg_res
);
8513 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8514 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8515 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8517 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8518 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8521 case 0xd: /* SQDMULL, SQDMULL2 */
8523 case 0xb: /* SQDMLSL, SQDMLSL2 */
8524 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8526 case 0x9: /* SQDMLAL, SQDMLAL2 */
8528 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8529 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8530 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8532 tcg_temp_free_i64(tcg_op3
);
8536 g_assert_not_reached();
8539 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8540 write_fp_dreg(s
, rd
, tcg_res
);
8542 tcg_temp_free_i32(tcg_op1
);
8543 tcg_temp_free_i32(tcg_op2
);
8544 tcg_temp_free_i64(tcg_res
);
8548 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8549 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8551 /* Handle 64x64->64 opcodes which are shared between the scalar
8552 * and vector 3-same groups. We cover every opcode where size == 3
8553 * is valid in either the three-reg-same (integer, not pairwise)
8554 * or scalar-three-reg-same groups.
8559 case 0x1: /* SQADD */
8561 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8563 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8566 case 0x5: /* SQSUB */
8568 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8570 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8573 case 0x6: /* CMGT, CMHI */
8574 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8575 * We implement this using setcond (test) and then negating.
8577 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8579 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8580 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8582 case 0x7: /* CMGE, CMHS */
8583 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8585 case 0x11: /* CMTST, CMEQ */
8590 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8592 case 0x8: /* SSHL, USHL */
8594 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8596 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8599 case 0x9: /* SQSHL, UQSHL */
8601 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8603 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8606 case 0xa: /* SRSHL, URSHL */
8608 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8610 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8613 case 0xb: /* SQRSHL, UQRSHL */
8615 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8617 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8620 case 0x10: /* ADD, SUB */
8622 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8624 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8628 g_assert_not_reached();
8632 /* Handle the 3-same-operands float operations; shared by the scalar
8633 * and vector encodings. The caller must filter out any encodings
8634 * not allocated for the encoding it is dealing with.
8636 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8637 int fpopcode
, int rd
, int rn
, int rm
)
8640 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8642 for (pass
= 0; pass
< elements
; pass
++) {
8645 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8646 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8647 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8649 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8650 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8653 case 0x39: /* FMLS */
8654 /* As usual for ARM, separate negation for fused multiply-add */
8655 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8657 case 0x19: /* FMLA */
8658 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8659 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8662 case 0x18: /* FMAXNM */
8663 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8665 case 0x1a: /* FADD */
8666 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8668 case 0x1b: /* FMULX */
8669 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8671 case 0x1c: /* FCMEQ */
8672 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8674 case 0x1e: /* FMAX */
8675 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8677 case 0x1f: /* FRECPS */
8678 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8680 case 0x38: /* FMINNM */
8681 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8683 case 0x3a: /* FSUB */
8684 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8686 case 0x3e: /* FMIN */
8687 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8689 case 0x3f: /* FRSQRTS */
8690 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8692 case 0x5b: /* FMUL */
8693 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8695 case 0x5c: /* FCMGE */
8696 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8698 case 0x5d: /* FACGE */
8699 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8701 case 0x5f: /* FDIV */
8702 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8704 case 0x7a: /* FABD */
8705 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8706 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8708 case 0x7c: /* FCMGT */
8709 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8711 case 0x7d: /* FACGT */
8712 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8715 g_assert_not_reached();
8718 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8720 tcg_temp_free_i64(tcg_res
);
8721 tcg_temp_free_i64(tcg_op1
);
8722 tcg_temp_free_i64(tcg_op2
);
8725 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8726 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8727 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8729 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8730 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8733 case 0x39: /* FMLS */
8734 /* As usual for ARM, separate negation for fused multiply-add */
8735 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8737 case 0x19: /* FMLA */
8738 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8739 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8742 case 0x1a: /* FADD */
8743 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8745 case 0x1b: /* FMULX */
8746 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8748 case 0x1c: /* FCMEQ */
8749 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8751 case 0x1e: /* FMAX */
8752 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8754 case 0x1f: /* FRECPS */
8755 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8757 case 0x18: /* FMAXNM */
8758 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8760 case 0x38: /* FMINNM */
8761 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8763 case 0x3a: /* FSUB */
8764 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8766 case 0x3e: /* FMIN */
8767 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8769 case 0x3f: /* FRSQRTS */
8770 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8772 case 0x5b: /* FMUL */
8773 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8775 case 0x5c: /* FCMGE */
8776 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8778 case 0x5d: /* FACGE */
8779 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8781 case 0x5f: /* FDIV */
8782 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8784 case 0x7a: /* FABD */
8785 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8786 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8788 case 0x7c: /* FCMGT */
8789 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8791 case 0x7d: /* FACGT */
8792 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8795 g_assert_not_reached();
8798 if (elements
== 1) {
8799 /* scalar single so clear high part */
8800 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8802 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8803 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8804 tcg_temp_free_i64(tcg_tmp
);
8806 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8809 tcg_temp_free_i32(tcg_res
);
8810 tcg_temp_free_i32(tcg_op1
);
8811 tcg_temp_free_i32(tcg_op2
);
8815 tcg_temp_free_ptr(fpst
);
8817 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8820 /* AdvSIMD scalar three same
8821 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8822 * +-----+---+-----------+------+---+------+--------+---+------+------+
8823 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8824 * +-----+---+-----------+------+---+------+--------+---+------+------+
8826 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8828 int rd
= extract32(insn
, 0, 5);
8829 int rn
= extract32(insn
, 5, 5);
8830 int opcode
= extract32(insn
, 11, 5);
8831 int rm
= extract32(insn
, 16, 5);
8832 int size
= extract32(insn
, 22, 2);
8833 bool u
= extract32(insn
, 29, 1);
8836 if (opcode
>= 0x18) {
8837 /* Floating point: U, size[1] and opcode indicate operation */
8838 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8840 case 0x1b: /* FMULX */
8841 case 0x1f: /* FRECPS */
8842 case 0x3f: /* FRSQRTS */
8843 case 0x5d: /* FACGE */
8844 case 0x7d: /* FACGT */
8845 case 0x1c: /* FCMEQ */
8846 case 0x5c: /* FCMGE */
8847 case 0x7c: /* FCMGT */
8848 case 0x7a: /* FABD */
8851 unallocated_encoding(s
);
8855 if (!fp_access_check(s
)) {
8859 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8864 case 0x1: /* SQADD, UQADD */
8865 case 0x5: /* SQSUB, UQSUB */
8866 case 0x9: /* SQSHL, UQSHL */
8867 case 0xb: /* SQRSHL, UQRSHL */
8869 case 0x8: /* SSHL, USHL */
8870 case 0xa: /* SRSHL, URSHL */
8871 case 0x6: /* CMGT, CMHI */
8872 case 0x7: /* CMGE, CMHS */
8873 case 0x11: /* CMTST, CMEQ */
8874 case 0x10: /* ADD, SUB (vector) */
8876 unallocated_encoding(s
);
8880 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8881 if (size
!= 1 && size
!= 2) {
8882 unallocated_encoding(s
);
8887 unallocated_encoding(s
);
8891 if (!fp_access_check(s
)) {
8895 tcg_rd
= tcg_temp_new_i64();
8898 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8899 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8901 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8902 tcg_temp_free_i64(tcg_rn
);
8903 tcg_temp_free_i64(tcg_rm
);
8905 /* Do a single operation on the lowest element in the vector.
8906 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8907 * no side effects for all these operations.
8908 * OPTME: special-purpose helpers would avoid doing some
8909 * unnecessary work in the helper for the 8 and 16 bit cases.
8911 NeonGenTwoOpEnvFn
*genenvfn
;
8912 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8913 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8914 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8916 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8917 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8920 case 0x1: /* SQADD, UQADD */
8922 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8923 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8924 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8925 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8927 genenvfn
= fns
[size
][u
];
8930 case 0x5: /* SQSUB, UQSUB */
8932 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8933 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8934 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8935 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8937 genenvfn
= fns
[size
][u
];
8940 case 0x9: /* SQSHL, UQSHL */
8942 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8943 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8944 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8945 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8947 genenvfn
= fns
[size
][u
];
8950 case 0xb: /* SQRSHL, UQRSHL */
8952 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8953 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8954 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8955 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8957 genenvfn
= fns
[size
][u
];
8960 case 0x16: /* SQDMULH, SQRDMULH */
8962 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8963 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8964 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8966 assert(size
== 1 || size
== 2);
8967 genenvfn
= fns
[size
- 1][u
];
8971 g_assert_not_reached();
8974 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8975 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8976 tcg_temp_free_i32(tcg_rd32
);
8977 tcg_temp_free_i32(tcg_rn
);
8978 tcg_temp_free_i32(tcg_rm
);
8981 write_fp_dreg(s
, rd
, tcg_rd
);
8983 tcg_temp_free_i64(tcg_rd
);
8986 /* AdvSIMD scalar three same FP16
8987 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8988 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8989 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8990 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8991 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8992 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8994 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8997 int rd
= extract32(insn
, 0, 5);
8998 int rn
= extract32(insn
, 5, 5);
8999 int opcode
= extract32(insn
, 11, 3);
9000 int rm
= extract32(insn
, 16, 5);
9001 bool u
= extract32(insn
, 29, 1);
9002 bool a
= extract32(insn
, 23, 1);
9003 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9010 case 0x03: /* FMULX */
9011 case 0x04: /* FCMEQ (reg) */
9012 case 0x07: /* FRECPS */
9013 case 0x0f: /* FRSQRTS */
9014 case 0x14: /* FCMGE (reg) */
9015 case 0x15: /* FACGE */
9016 case 0x1a: /* FABD */
9017 case 0x1c: /* FCMGT (reg) */
9018 case 0x1d: /* FACGT */
9021 unallocated_encoding(s
);
9025 if (!dc_isar_feature(aa64_fp16
, s
)) {
9026 unallocated_encoding(s
);
9029 if (!fp_access_check(s
)) {
9033 fpst
= get_fpstatus_ptr(true);
9035 tcg_op1
= read_fp_hreg(s
, rn
);
9036 tcg_op2
= read_fp_hreg(s
, rm
);
9037 tcg_res
= tcg_temp_new_i32();
9040 case 0x03: /* FMULX */
9041 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9043 case 0x04: /* FCMEQ (reg) */
9044 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9046 case 0x07: /* FRECPS */
9047 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9049 case 0x0f: /* FRSQRTS */
9050 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9052 case 0x14: /* FCMGE (reg) */
9053 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9055 case 0x15: /* FACGE */
9056 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9058 case 0x1a: /* FABD */
9059 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9060 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9062 case 0x1c: /* FCMGT (reg) */
9063 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9065 case 0x1d: /* FACGT */
9066 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9069 g_assert_not_reached();
9072 write_fp_sreg(s
, rd
, tcg_res
);
9075 tcg_temp_free_i32(tcg_res
);
9076 tcg_temp_free_i32(tcg_op1
);
9077 tcg_temp_free_i32(tcg_op2
);
9078 tcg_temp_free_ptr(fpst
);
9081 /* AdvSIMD scalar three same extra
9082 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9083 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9084 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9085 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9087 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9090 int rd
= extract32(insn
, 0, 5);
9091 int rn
= extract32(insn
, 5, 5);
9092 int opcode
= extract32(insn
, 11, 4);
9093 int rm
= extract32(insn
, 16, 5);
9094 int size
= extract32(insn
, 22, 2);
9095 bool u
= extract32(insn
, 29, 1);
9096 TCGv_i32 ele1
, ele2
, ele3
;
9100 switch (u
* 16 + opcode
) {
9101 case 0x10: /* SQRDMLAH (vector) */
9102 case 0x11: /* SQRDMLSH (vector) */
9103 if (size
!= 1 && size
!= 2) {
9104 unallocated_encoding(s
);
9107 feature
= dc_isar_feature(aa64_rdm
, s
);
9110 unallocated_encoding(s
);
9114 unallocated_encoding(s
);
9117 if (!fp_access_check(s
)) {
9121 /* Do a single operation on the lowest element in the vector.
9122 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9123 * with no side effects for all these operations.
9124 * OPTME: special-purpose helpers would avoid doing some
9125 * unnecessary work in the helper for the 16 bit cases.
9127 ele1
= tcg_temp_new_i32();
9128 ele2
= tcg_temp_new_i32();
9129 ele3
= tcg_temp_new_i32();
9131 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9132 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9133 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9136 case 0x0: /* SQRDMLAH */
9138 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9140 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9143 case 0x1: /* SQRDMLSH */
9145 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9147 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9151 g_assert_not_reached();
9153 tcg_temp_free_i32(ele1
);
9154 tcg_temp_free_i32(ele2
);
9156 res
= tcg_temp_new_i64();
9157 tcg_gen_extu_i32_i64(res
, ele3
);
9158 tcg_temp_free_i32(ele3
);
9160 write_fp_dreg(s
, rd
, res
);
9161 tcg_temp_free_i64(res
);
9164 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9165 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9166 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9168 /* Handle 64->64 opcodes which are shared between the scalar and
9169 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9170 * is valid in either group and also the double-precision fp ops.
9171 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9177 case 0x4: /* CLS, CLZ */
9179 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9181 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9185 /* This opcode is shared with CNT and RBIT but we have earlier
9186 * enforced that size == 3 if and only if this is the NOT insn.
9188 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9190 case 0x7: /* SQABS, SQNEG */
9192 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9194 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9197 case 0xa: /* CMLT */
9198 /* 64 bit integer comparison against zero, result is
9199 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9204 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9205 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9207 case 0x8: /* CMGT, CMGE */
9208 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9210 case 0x9: /* CMEQ, CMLE */
9211 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9213 case 0xb: /* ABS, NEG */
9215 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9217 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9218 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9219 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
9221 tcg_temp_free_i64(tcg_zero
);
9224 case 0x2f: /* FABS */
9225 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9227 case 0x6f: /* FNEG */
9228 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9230 case 0x7f: /* FSQRT */
9231 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9233 case 0x1a: /* FCVTNS */
9234 case 0x1b: /* FCVTMS */
9235 case 0x1c: /* FCVTAS */
9236 case 0x3a: /* FCVTPS */
9237 case 0x3b: /* FCVTZS */
9239 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9240 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9241 tcg_temp_free_i32(tcg_shift
);
9244 case 0x5a: /* FCVTNU */
9245 case 0x5b: /* FCVTMU */
9246 case 0x5c: /* FCVTAU */
9247 case 0x7a: /* FCVTPU */
9248 case 0x7b: /* FCVTZU */
9250 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9251 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9252 tcg_temp_free_i32(tcg_shift
);
9255 case 0x18: /* FRINTN */
9256 case 0x19: /* FRINTM */
9257 case 0x38: /* FRINTP */
9258 case 0x39: /* FRINTZ */
9259 case 0x58: /* FRINTA */
9260 case 0x79: /* FRINTI */
9261 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9263 case 0x59: /* FRINTX */
9264 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9267 g_assert_not_reached();
9271 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9272 bool is_scalar
, bool is_u
, bool is_q
,
9273 int size
, int rn
, int rd
)
9275 bool is_double
= (size
== MO_64
);
9278 if (!fp_access_check(s
)) {
9282 fpst
= get_fpstatus_ptr(size
== MO_16
);
9285 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9286 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9287 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9288 NeonGenTwoDoubleOPFn
*genfn
;
9293 case 0x2e: /* FCMLT (zero) */
9296 case 0x2c: /* FCMGT (zero) */
9297 genfn
= gen_helper_neon_cgt_f64
;
9299 case 0x2d: /* FCMEQ (zero) */
9300 genfn
= gen_helper_neon_ceq_f64
;
9302 case 0x6d: /* FCMLE (zero) */
9305 case 0x6c: /* FCMGE (zero) */
9306 genfn
= gen_helper_neon_cge_f64
;
9309 g_assert_not_reached();
9312 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9313 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9315 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9317 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9319 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9321 tcg_temp_free_i64(tcg_res
);
9322 tcg_temp_free_i64(tcg_zero
);
9323 tcg_temp_free_i64(tcg_op
);
9325 clear_vec_high(s
, !is_scalar
, rd
);
9327 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9328 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9329 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9330 NeonGenTwoSingleOPFn
*genfn
;
9332 int pass
, maxpasses
;
9334 if (size
== MO_16
) {
9336 case 0x2e: /* FCMLT (zero) */
9339 case 0x2c: /* FCMGT (zero) */
9340 genfn
= gen_helper_advsimd_cgt_f16
;
9342 case 0x2d: /* FCMEQ (zero) */
9343 genfn
= gen_helper_advsimd_ceq_f16
;
9345 case 0x6d: /* FCMLE (zero) */
9348 case 0x6c: /* FCMGE (zero) */
9349 genfn
= gen_helper_advsimd_cge_f16
;
9352 g_assert_not_reached();
9356 case 0x2e: /* FCMLT (zero) */
9359 case 0x2c: /* FCMGT (zero) */
9360 genfn
= gen_helper_neon_cgt_f32
;
9362 case 0x2d: /* FCMEQ (zero) */
9363 genfn
= gen_helper_neon_ceq_f32
;
9365 case 0x6d: /* FCMLE (zero) */
9368 case 0x6c: /* FCMGE (zero) */
9369 genfn
= gen_helper_neon_cge_f32
;
9372 g_assert_not_reached();
9379 int vector_size
= 8 << is_q
;
9380 maxpasses
= vector_size
>> size
;
9383 for (pass
= 0; pass
< maxpasses
; pass
++) {
9384 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9386 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9388 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9391 write_fp_sreg(s
, rd
, tcg_res
);
9393 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9396 tcg_temp_free_i32(tcg_res
);
9397 tcg_temp_free_i32(tcg_zero
);
9398 tcg_temp_free_i32(tcg_op
);
9400 clear_vec_high(s
, is_q
, rd
);
9404 tcg_temp_free_ptr(fpst
);
9407 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9408 bool is_scalar
, bool is_u
, bool is_q
,
9409 int size
, int rn
, int rd
)
9411 bool is_double
= (size
== 3);
9412 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9415 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9416 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9419 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9420 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9422 case 0x3d: /* FRECPE */
9423 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9425 case 0x3f: /* FRECPX */
9426 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9428 case 0x7d: /* FRSQRTE */
9429 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9432 g_assert_not_reached();
9434 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9436 tcg_temp_free_i64(tcg_res
);
9437 tcg_temp_free_i64(tcg_op
);
9438 clear_vec_high(s
, !is_scalar
, rd
);
9440 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9441 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9442 int pass
, maxpasses
;
9447 maxpasses
= is_q
? 4 : 2;
9450 for (pass
= 0; pass
< maxpasses
; pass
++) {
9451 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9454 case 0x3c: /* URECPE */
9455 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9457 case 0x3d: /* FRECPE */
9458 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9460 case 0x3f: /* FRECPX */
9461 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9463 case 0x7d: /* FRSQRTE */
9464 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9467 g_assert_not_reached();
9471 write_fp_sreg(s
, rd
, tcg_res
);
9473 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9476 tcg_temp_free_i32(tcg_res
);
9477 tcg_temp_free_i32(tcg_op
);
9479 clear_vec_high(s
, is_q
, rd
);
9482 tcg_temp_free_ptr(fpst
);
9485 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9486 int opcode
, bool u
, bool is_q
,
9487 int size
, int rn
, int rd
)
9489 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9490 * in the source becomes a size element in the destination).
9493 TCGv_i32 tcg_res
[2];
9494 int destelt
= is_q
? 2 : 0;
9495 int passes
= scalar
? 1 : 2;
9498 tcg_res
[1] = tcg_const_i32(0);
9501 for (pass
= 0; pass
< passes
; pass
++) {
9502 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9503 NeonGenNarrowFn
*genfn
= NULL
;
9504 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9507 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9509 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9511 tcg_res
[pass
] = tcg_temp_new_i32();
9514 case 0x12: /* XTN, SQXTUN */
9516 static NeonGenNarrowFn
* const xtnfns
[3] = {
9517 gen_helper_neon_narrow_u8
,
9518 gen_helper_neon_narrow_u16
,
9519 tcg_gen_extrl_i64_i32
,
9521 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9522 gen_helper_neon_unarrow_sat8
,
9523 gen_helper_neon_unarrow_sat16
,
9524 gen_helper_neon_unarrow_sat32
,
9527 genenvfn
= sqxtunfns
[size
];
9529 genfn
= xtnfns
[size
];
9533 case 0x14: /* SQXTN, UQXTN */
9535 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9536 { gen_helper_neon_narrow_sat_s8
,
9537 gen_helper_neon_narrow_sat_u8
},
9538 { gen_helper_neon_narrow_sat_s16
,
9539 gen_helper_neon_narrow_sat_u16
},
9540 { gen_helper_neon_narrow_sat_s32
,
9541 gen_helper_neon_narrow_sat_u32
},
9543 genenvfn
= fns
[size
][u
];
9546 case 0x16: /* FCVTN, FCVTN2 */
9547 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9549 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9551 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9552 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9553 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9554 TCGv_i32 ahp
= get_ahp_flag();
9556 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9557 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9558 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9559 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9560 tcg_temp_free_i32(tcg_lo
);
9561 tcg_temp_free_i32(tcg_hi
);
9562 tcg_temp_free_ptr(fpst
);
9563 tcg_temp_free_i32(ahp
);
9566 case 0x56: /* FCVTXN, FCVTXN2 */
9567 /* 64 bit to 32 bit float conversion
9568 * with von Neumann rounding (round to odd)
9571 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9574 g_assert_not_reached();
9578 genfn(tcg_res
[pass
], tcg_op
);
9579 } else if (genenvfn
) {
9580 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9583 tcg_temp_free_i64(tcg_op
);
9586 for (pass
= 0; pass
< 2; pass
++) {
9587 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9588 tcg_temp_free_i32(tcg_res
[pass
]);
9590 clear_vec_high(s
, is_q
, rd
);
9593 /* Remaining saturating accumulating ops */
9594 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9595 bool is_q
, int size
, int rn
, int rd
)
9597 bool is_double
= (size
== 3);
9600 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9601 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9604 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9605 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9606 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9608 if (is_u
) { /* USQADD */
9609 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9610 } else { /* SUQADD */
9611 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9613 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9615 tcg_temp_free_i64(tcg_rd
);
9616 tcg_temp_free_i64(tcg_rn
);
9617 clear_vec_high(s
, !is_scalar
, rd
);
9619 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9620 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9621 int pass
, maxpasses
;
9626 maxpasses
= is_q
? 4 : 2;
9629 for (pass
= 0; pass
< maxpasses
; pass
++) {
9631 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9632 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9634 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9635 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9638 if (is_u
) { /* USQADD */
9641 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9644 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9647 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9650 g_assert_not_reached();
9652 } else { /* SUQADD */
9655 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9658 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9661 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9664 g_assert_not_reached();
9669 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9670 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9671 tcg_temp_free_i64(tcg_zero
);
9673 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9675 tcg_temp_free_i32(tcg_rd
);
9676 tcg_temp_free_i32(tcg_rn
);
9677 clear_vec_high(s
, is_q
, rd
);
9681 /* AdvSIMD scalar two reg misc
9682 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9683 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9684 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9685 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9687 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9689 int rd
= extract32(insn
, 0, 5);
9690 int rn
= extract32(insn
, 5, 5);
9691 int opcode
= extract32(insn
, 12, 5);
9692 int size
= extract32(insn
, 22, 2);
9693 bool u
= extract32(insn
, 29, 1);
9694 bool is_fcvt
= false;
9697 TCGv_ptr tcg_fpstatus
;
9700 case 0x3: /* USQADD / SUQADD*/
9701 if (!fp_access_check(s
)) {
9704 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9706 case 0x7: /* SQABS / SQNEG */
9708 case 0xa: /* CMLT */
9710 unallocated_encoding(s
);
9714 case 0x8: /* CMGT, CMGE */
9715 case 0x9: /* CMEQ, CMLE */
9716 case 0xb: /* ABS, NEG */
9718 unallocated_encoding(s
);
9722 case 0x12: /* SQXTUN */
9724 unallocated_encoding(s
);
9728 case 0x14: /* SQXTN, UQXTN */
9730 unallocated_encoding(s
);
9733 if (!fp_access_check(s
)) {
9736 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9741 /* Floating point: U, size[1] and opcode indicate operation;
9742 * size[0] indicates single or double precision.
9744 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9745 size
= extract32(size
, 0, 1) ? 3 : 2;
9747 case 0x2c: /* FCMGT (zero) */
9748 case 0x2d: /* FCMEQ (zero) */
9749 case 0x2e: /* FCMLT (zero) */
9750 case 0x6c: /* FCMGE (zero) */
9751 case 0x6d: /* FCMLE (zero) */
9752 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9754 case 0x1d: /* SCVTF */
9755 case 0x5d: /* UCVTF */
9757 bool is_signed
= (opcode
== 0x1d);
9758 if (!fp_access_check(s
)) {
9761 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9764 case 0x3d: /* FRECPE */
9765 case 0x3f: /* FRECPX */
9766 case 0x7d: /* FRSQRTE */
9767 if (!fp_access_check(s
)) {
9770 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9772 case 0x1a: /* FCVTNS */
9773 case 0x1b: /* FCVTMS */
9774 case 0x3a: /* FCVTPS */
9775 case 0x3b: /* FCVTZS */
9776 case 0x5a: /* FCVTNU */
9777 case 0x5b: /* FCVTMU */
9778 case 0x7a: /* FCVTPU */
9779 case 0x7b: /* FCVTZU */
9781 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9783 case 0x1c: /* FCVTAS */
9784 case 0x5c: /* FCVTAU */
9785 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9787 rmode
= FPROUNDING_TIEAWAY
;
9789 case 0x56: /* FCVTXN, FCVTXN2 */
9791 unallocated_encoding(s
);
9794 if (!fp_access_check(s
)) {
9797 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9800 unallocated_encoding(s
);
9805 unallocated_encoding(s
);
9809 if (!fp_access_check(s
)) {
9814 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9815 tcg_fpstatus
= get_fpstatus_ptr(false);
9816 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9819 tcg_fpstatus
= NULL
;
9823 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9824 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9826 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9827 write_fp_dreg(s
, rd
, tcg_rd
);
9828 tcg_temp_free_i64(tcg_rd
);
9829 tcg_temp_free_i64(tcg_rn
);
9831 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9832 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9834 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9837 case 0x7: /* SQABS, SQNEG */
9839 NeonGenOneOpEnvFn
*genfn
;
9840 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9841 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9842 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9843 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9845 genfn
= fns
[size
][u
];
9846 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9849 case 0x1a: /* FCVTNS */
9850 case 0x1b: /* FCVTMS */
9851 case 0x1c: /* FCVTAS */
9852 case 0x3a: /* FCVTPS */
9853 case 0x3b: /* FCVTZS */
9855 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9856 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9857 tcg_temp_free_i32(tcg_shift
);
9860 case 0x5a: /* FCVTNU */
9861 case 0x5b: /* FCVTMU */
9862 case 0x5c: /* FCVTAU */
9863 case 0x7a: /* FCVTPU */
9864 case 0x7b: /* FCVTZU */
9866 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9867 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9868 tcg_temp_free_i32(tcg_shift
);
9872 g_assert_not_reached();
9875 write_fp_sreg(s
, rd
, tcg_rd
);
9876 tcg_temp_free_i32(tcg_rd
);
9877 tcg_temp_free_i32(tcg_rn
);
9881 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9882 tcg_temp_free_i32(tcg_rmode
);
9883 tcg_temp_free_ptr(tcg_fpstatus
);
9887 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9888 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9889 int immh
, int immb
, int opcode
, int rn
, int rd
)
9891 int size
= 32 - clz32(immh
) - 1;
9892 int immhb
= immh
<< 3 | immb
;
9893 int shift
= 2 * (8 << size
) - immhb
;
9894 bool accumulate
= false;
9895 int dsize
= is_q
? 128 : 64;
9896 int esize
= 8 << size
;
9897 int elements
= dsize
/esize
;
9898 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9899 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9900 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9902 uint64_t round_const
;
9905 if (extract32(immh
, 3, 1) && !is_q
) {
9906 unallocated_encoding(s
);
9909 tcg_debug_assert(size
<= 3);
9911 if (!fp_access_check(s
)) {
9916 case 0x02: /* SSRA / USRA (accumulate) */
9918 /* Shift count same as element size produces zero to add. */
9919 if (shift
== 8 << size
) {
9922 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9924 /* Shift count same as element size produces all sign to add. */
9925 if (shift
== 8 << size
) {
9928 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9931 case 0x08: /* SRI */
9932 /* Shift count same as element size is valid but does nothing. */
9933 if (shift
== 8 << size
) {
9936 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9939 case 0x00: /* SSHR / USHR */
9941 if (shift
== 8 << size
) {
9942 /* Shift count the same size as element size produces zero. */
9943 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9944 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9946 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9949 /* Shift count the same size as element size produces all sign. */
9950 if (shift
== 8 << size
) {
9953 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9957 case 0x04: /* SRSHR / URSHR (rounding) */
9959 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9963 g_assert_not_reached();
9966 round_const
= 1ULL << (shift
- 1);
9967 tcg_round
= tcg_const_i64(round_const
);
9969 for (i
= 0; i
< elements
; i
++) {
9970 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9972 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9975 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9976 accumulate
, is_u
, size
, shift
);
9978 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9980 tcg_temp_free_i64(tcg_round
);
9983 clear_vec_high(s
, is_q
, rd
);
9986 /* SHL/SLI - Vector shift left */
9987 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9988 int immh
, int immb
, int opcode
, int rn
, int rd
)
9990 int size
= 32 - clz32(immh
) - 1;
9991 int immhb
= immh
<< 3 | immb
;
9992 int shift
= immhb
- (8 << size
);
9994 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
9995 assert(size
>= 0 && size
<= 3);
9997 if (extract32(immh
, 3, 1) && !is_q
) {
9998 unallocated_encoding(s
);
10002 if (!fp_access_check(s
)) {
10007 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10009 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10013 /* USHLL/SHLL - Vector shift left with widening */
10014 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10015 int immh
, int immb
, int opcode
, int rn
, int rd
)
10017 int size
= 32 - clz32(immh
) - 1;
10018 int immhb
= immh
<< 3 | immb
;
10019 int shift
= immhb
- (8 << size
);
10021 int esize
= 8 << size
;
10022 int elements
= dsize
/esize
;
10023 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10024 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10028 unallocated_encoding(s
);
10032 if (!fp_access_check(s
)) {
10036 /* For the LL variants the store is larger than the load,
10037 * so if rd == rn we would overwrite parts of our input.
10038 * So load everything right now and use shifts in the main loop.
10040 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10042 for (i
= 0; i
< elements
; i
++) {
10043 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10044 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10045 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10046 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10050 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10051 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10052 int immh
, int immb
, int opcode
, int rn
, int rd
)
10054 int immhb
= immh
<< 3 | immb
;
10055 int size
= 32 - clz32(immh
) - 1;
10057 int esize
= 8 << size
;
10058 int elements
= dsize
/esize
;
10059 int shift
= (2 * esize
) - immhb
;
10060 bool round
= extract32(opcode
, 0, 1);
10061 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10062 TCGv_i64 tcg_round
;
10065 if (extract32(immh
, 3, 1)) {
10066 unallocated_encoding(s
);
10070 if (!fp_access_check(s
)) {
10074 tcg_rn
= tcg_temp_new_i64();
10075 tcg_rd
= tcg_temp_new_i64();
10076 tcg_final
= tcg_temp_new_i64();
10077 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10080 uint64_t round_const
= 1ULL << (shift
- 1);
10081 tcg_round
= tcg_const_i64(round_const
);
10086 for (i
= 0; i
< elements
; i
++) {
10087 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10088 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10089 false, true, size
+1, shift
);
10091 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10095 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10097 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10100 tcg_temp_free_i64(tcg_round
);
10102 tcg_temp_free_i64(tcg_rn
);
10103 tcg_temp_free_i64(tcg_rd
);
10104 tcg_temp_free_i64(tcg_final
);
10106 clear_vec_high(s
, is_q
, rd
);
10110 /* AdvSIMD shift by immediate
10111 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10112 * +---+---+---+-------------+------+------+--------+---+------+------+
10113 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10114 * +---+---+---+-------------+------+------+--------+---+------+------+
10116 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10118 int rd
= extract32(insn
, 0, 5);
10119 int rn
= extract32(insn
, 5, 5);
10120 int opcode
= extract32(insn
, 11, 5);
10121 int immb
= extract32(insn
, 16, 3);
10122 int immh
= extract32(insn
, 19, 4);
10123 bool is_u
= extract32(insn
, 29, 1);
10124 bool is_q
= extract32(insn
, 30, 1);
10127 case 0x08: /* SRI */
10129 unallocated_encoding(s
);
10133 case 0x00: /* SSHR / USHR */
10134 case 0x02: /* SSRA / USRA (accumulate) */
10135 case 0x04: /* SRSHR / URSHR (rounding) */
10136 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10137 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10139 case 0x0a: /* SHL / SLI */
10140 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10142 case 0x10: /* SHRN */
10143 case 0x11: /* RSHRN / SQRSHRUN */
10145 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10148 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10151 case 0x12: /* SQSHRN / UQSHRN */
10152 case 0x13: /* SQRSHRN / UQRSHRN */
10153 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10156 case 0x14: /* SSHLL / USHLL */
10157 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10159 case 0x1c: /* SCVTF / UCVTF */
10160 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10163 case 0xc: /* SQSHLU */
10165 unallocated_encoding(s
);
10168 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10170 case 0xe: /* SQSHL, UQSHL */
10171 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10173 case 0x1f: /* FCVTZS/ FCVTZU */
10174 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10177 unallocated_encoding(s
);
10182 /* Generate code to do a "long" addition or subtraction, ie one done in
10183 * TCGv_i64 on vector lanes twice the width specified by size.
10185 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10186 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10188 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10189 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10190 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10191 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10193 NeonGenTwo64OpFn
*genfn
;
10196 genfn
= fns
[size
][is_sub
];
10197 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10200 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10201 int opcode
, int rd
, int rn
, int rm
)
10203 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10204 TCGv_i64 tcg_res
[2];
10207 tcg_res
[0] = tcg_temp_new_i64();
10208 tcg_res
[1] = tcg_temp_new_i64();
10210 /* Does this op do an adding accumulate, a subtracting accumulate,
10211 * or no accumulate at all?
10229 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10230 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10233 /* size == 2 means two 32x32->64 operations; this is worth special
10234 * casing because we can generally handle it inline.
10237 for (pass
= 0; pass
< 2; pass
++) {
10238 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10239 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10240 TCGv_i64 tcg_passres
;
10241 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10243 int elt
= pass
+ is_q
* 2;
10245 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10246 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10249 tcg_passres
= tcg_res
[pass
];
10251 tcg_passres
= tcg_temp_new_i64();
10255 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10256 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10258 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10259 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10261 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10262 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10264 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10265 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10267 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10268 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10269 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10271 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10272 tcg_temp_free_i64(tcg_tmp1
);
10273 tcg_temp_free_i64(tcg_tmp2
);
10276 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10277 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10278 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10279 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10281 case 9: /* SQDMLAL, SQDMLAL2 */
10282 case 11: /* SQDMLSL, SQDMLSL2 */
10283 case 13: /* SQDMULL, SQDMULL2 */
10284 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10285 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10286 tcg_passres
, tcg_passres
);
10289 g_assert_not_reached();
10292 if (opcode
== 9 || opcode
== 11) {
10293 /* saturating accumulate ops */
10295 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10297 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10298 tcg_res
[pass
], tcg_passres
);
10299 } else if (accop
> 0) {
10300 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10301 } else if (accop
< 0) {
10302 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10306 tcg_temp_free_i64(tcg_passres
);
10309 tcg_temp_free_i64(tcg_op1
);
10310 tcg_temp_free_i64(tcg_op2
);
10313 /* size 0 or 1, generally helper functions */
10314 for (pass
= 0; pass
< 2; pass
++) {
10315 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10316 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10317 TCGv_i64 tcg_passres
;
10318 int elt
= pass
+ is_q
* 2;
10320 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10321 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10324 tcg_passres
= tcg_res
[pass
];
10326 tcg_passres
= tcg_temp_new_i64();
10330 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10331 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10333 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10334 static NeonGenWidenFn
* const widenfns
[2][2] = {
10335 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10336 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10338 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10340 widenfn(tcg_op2_64
, tcg_op2
);
10341 widenfn(tcg_passres
, tcg_op1
);
10342 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10343 tcg_passres
, tcg_op2_64
);
10344 tcg_temp_free_i64(tcg_op2_64
);
10347 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10348 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10351 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10353 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10357 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10359 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10363 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10364 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10365 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10368 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10370 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10374 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10376 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10380 case 9: /* SQDMLAL, SQDMLAL2 */
10381 case 11: /* SQDMLSL, SQDMLSL2 */
10382 case 13: /* SQDMULL, SQDMULL2 */
10384 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10385 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10386 tcg_passres
, tcg_passres
);
10388 case 14: /* PMULL */
10390 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10393 g_assert_not_reached();
10395 tcg_temp_free_i32(tcg_op1
);
10396 tcg_temp_free_i32(tcg_op2
);
10399 if (opcode
== 9 || opcode
== 11) {
10400 /* saturating accumulate ops */
10402 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10404 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10408 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10409 tcg_res
[pass
], tcg_passres
);
10411 tcg_temp_free_i64(tcg_passres
);
10416 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10417 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10418 tcg_temp_free_i64(tcg_res
[0]);
10419 tcg_temp_free_i64(tcg_res
[1]);
10422 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10423 int opcode
, int rd
, int rn
, int rm
)
10425 TCGv_i64 tcg_res
[2];
10426 int part
= is_q
? 2 : 0;
10429 for (pass
= 0; pass
< 2; pass
++) {
10430 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10431 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10432 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10433 static NeonGenWidenFn
* const widenfns
[3][2] = {
10434 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10435 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10436 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10438 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10440 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10441 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10442 widenfn(tcg_op2_wide
, tcg_op2
);
10443 tcg_temp_free_i32(tcg_op2
);
10444 tcg_res
[pass
] = tcg_temp_new_i64();
10445 gen_neon_addl(size
, (opcode
== 3),
10446 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10447 tcg_temp_free_i64(tcg_op1
);
10448 tcg_temp_free_i64(tcg_op2_wide
);
10451 for (pass
= 0; pass
< 2; pass
++) {
10452 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10453 tcg_temp_free_i64(tcg_res
[pass
]);
10457 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10459 tcg_gen_addi_i64(in
, in
, 1U << 31);
10460 tcg_gen_extrh_i64_i32(res
, in
);
10463 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10464 int opcode
, int rd
, int rn
, int rm
)
10466 TCGv_i32 tcg_res
[2];
10467 int part
= is_q
? 2 : 0;
10470 for (pass
= 0; pass
< 2; pass
++) {
10471 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10472 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10473 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10474 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10475 { gen_helper_neon_narrow_high_u8
,
10476 gen_helper_neon_narrow_round_high_u8
},
10477 { gen_helper_neon_narrow_high_u16
,
10478 gen_helper_neon_narrow_round_high_u16
},
10479 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10481 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10483 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10484 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10486 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10488 tcg_temp_free_i64(tcg_op1
);
10489 tcg_temp_free_i64(tcg_op2
);
10491 tcg_res
[pass
] = tcg_temp_new_i32();
10492 gennarrow(tcg_res
[pass
], tcg_wideres
);
10493 tcg_temp_free_i64(tcg_wideres
);
10496 for (pass
= 0; pass
< 2; pass
++) {
10497 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10498 tcg_temp_free_i32(tcg_res
[pass
]);
10500 clear_vec_high(s
, is_q
, rd
);
10503 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10505 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10506 * is the only three-reg-diff instruction which produces a
10507 * 128-bit wide result from a single operation. However since
10508 * it's possible to calculate the two halves more or less
10509 * separately we just use two helper calls.
10511 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10512 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10513 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10515 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10516 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10517 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10518 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10519 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10520 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10522 tcg_temp_free_i64(tcg_op1
);
10523 tcg_temp_free_i64(tcg_op2
);
10524 tcg_temp_free_i64(tcg_res
);
10527 /* AdvSIMD three different
10528 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10529 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10530 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10531 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10533 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10535 /* Instructions in this group fall into three basic classes
10536 * (in each case with the operation working on each element in
10537 * the input vectors):
10538 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10540 * (2) wide 64 x 128 -> 128
10541 * (3) narrowing 128 x 128 -> 64
10542 * Here we do initial decode, catch unallocated cases and
10543 * dispatch to separate functions for each class.
10545 int is_q
= extract32(insn
, 30, 1);
10546 int is_u
= extract32(insn
, 29, 1);
10547 int size
= extract32(insn
, 22, 2);
10548 int opcode
= extract32(insn
, 12, 4);
10549 int rm
= extract32(insn
, 16, 5);
10550 int rn
= extract32(insn
, 5, 5);
10551 int rd
= extract32(insn
, 0, 5);
10554 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10555 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10556 /* 64 x 128 -> 128 */
10558 unallocated_encoding(s
);
10561 if (!fp_access_check(s
)) {
10564 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10566 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10567 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10568 /* 128 x 128 -> 64 */
10570 unallocated_encoding(s
);
10573 if (!fp_access_check(s
)) {
10576 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10578 case 14: /* PMULL, PMULL2 */
10579 if (is_u
|| size
== 1 || size
== 2) {
10580 unallocated_encoding(s
);
10584 if (!dc_isar_feature(aa64_pmull
, s
)) {
10585 unallocated_encoding(s
);
10588 if (!fp_access_check(s
)) {
10591 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10595 case 9: /* SQDMLAL, SQDMLAL2 */
10596 case 11: /* SQDMLSL, SQDMLSL2 */
10597 case 13: /* SQDMULL, SQDMULL2 */
10598 if (is_u
|| size
== 0) {
10599 unallocated_encoding(s
);
10603 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10604 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10605 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10606 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10607 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10608 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10609 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10610 /* 64 x 64 -> 128 */
10612 unallocated_encoding(s
);
10616 if (!fp_access_check(s
)) {
10620 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10623 /* opcode 15 not allocated */
10624 unallocated_encoding(s
);
10629 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10630 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10632 int rd
= extract32(insn
, 0, 5);
10633 int rn
= extract32(insn
, 5, 5);
10634 int rm
= extract32(insn
, 16, 5);
10635 int size
= extract32(insn
, 22, 2);
10636 bool is_u
= extract32(insn
, 29, 1);
10637 bool is_q
= extract32(insn
, 30, 1);
10639 if (!fp_access_check(s
)) {
10643 switch (size
+ 4 * is_u
) {
10645 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10648 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10651 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10654 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10657 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10660 case 5: /* BSL bitwise select */
10661 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10663 case 6: /* BIT, bitwise insert if true */
10664 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10666 case 7: /* BIF, bitwise insert if false */
10667 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10671 g_assert_not_reached();
10675 /* Pairwise op subgroup of C3.6.16.
10677 * This is called directly or via the handle_3same_float for float pairwise
10678 * operations where the opcode and size are calculated differently.
10680 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10681 int size
, int rn
, int rm
, int rd
)
10686 /* Floating point operations need fpst */
10687 if (opcode
>= 0x58) {
10688 fpst
= get_fpstatus_ptr(false);
10693 if (!fp_access_check(s
)) {
10697 /* These operations work on the concatenated rm:rn, with each pair of
10698 * adjacent elements being operated on to produce an element in the result.
10701 TCGv_i64 tcg_res
[2];
10703 for (pass
= 0; pass
< 2; pass
++) {
10704 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10705 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10706 int passreg
= (pass
== 0) ? rn
: rm
;
10708 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10709 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10710 tcg_res
[pass
] = tcg_temp_new_i64();
10713 case 0x17: /* ADDP */
10714 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10716 case 0x58: /* FMAXNMP */
10717 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10719 case 0x5a: /* FADDP */
10720 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10722 case 0x5e: /* FMAXP */
10723 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10725 case 0x78: /* FMINNMP */
10726 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10728 case 0x7e: /* FMINP */
10729 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10732 g_assert_not_reached();
10735 tcg_temp_free_i64(tcg_op1
);
10736 tcg_temp_free_i64(tcg_op2
);
10739 for (pass
= 0; pass
< 2; pass
++) {
10740 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10741 tcg_temp_free_i64(tcg_res
[pass
]);
10744 int maxpass
= is_q
? 4 : 2;
10745 TCGv_i32 tcg_res
[4];
10747 for (pass
= 0; pass
< maxpass
; pass
++) {
10748 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10749 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10750 NeonGenTwoOpFn
*genfn
= NULL
;
10751 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10752 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10754 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10755 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10756 tcg_res
[pass
] = tcg_temp_new_i32();
10759 case 0x17: /* ADDP */
10761 static NeonGenTwoOpFn
* const fns
[3] = {
10762 gen_helper_neon_padd_u8
,
10763 gen_helper_neon_padd_u16
,
10769 case 0x14: /* SMAXP, UMAXP */
10771 static NeonGenTwoOpFn
* const fns
[3][2] = {
10772 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10773 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10774 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10776 genfn
= fns
[size
][u
];
10779 case 0x15: /* SMINP, UMINP */
10781 static NeonGenTwoOpFn
* const fns
[3][2] = {
10782 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10783 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10784 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10786 genfn
= fns
[size
][u
];
10789 /* The FP operations are all on single floats (32 bit) */
10790 case 0x58: /* FMAXNMP */
10791 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10793 case 0x5a: /* FADDP */
10794 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10796 case 0x5e: /* FMAXP */
10797 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10799 case 0x78: /* FMINNMP */
10800 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10802 case 0x7e: /* FMINP */
10803 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10806 g_assert_not_reached();
10809 /* FP ops called directly, otherwise call now */
10811 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10814 tcg_temp_free_i32(tcg_op1
);
10815 tcg_temp_free_i32(tcg_op2
);
10818 for (pass
= 0; pass
< maxpass
; pass
++) {
10819 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10820 tcg_temp_free_i32(tcg_res
[pass
]);
10822 clear_vec_high(s
, is_q
, rd
);
10826 tcg_temp_free_ptr(fpst
);
10830 /* Floating point op subgroup of C3.6.16. */
10831 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10833 /* For floating point ops, the U, size[1] and opcode bits
10834 * together indicate the operation. size[0] indicates single
10837 int fpopcode
= extract32(insn
, 11, 5)
10838 | (extract32(insn
, 23, 1) << 5)
10839 | (extract32(insn
, 29, 1) << 6);
10840 int is_q
= extract32(insn
, 30, 1);
10841 int size
= extract32(insn
, 22, 1);
10842 int rm
= extract32(insn
, 16, 5);
10843 int rn
= extract32(insn
, 5, 5);
10844 int rd
= extract32(insn
, 0, 5);
10846 int datasize
= is_q
? 128 : 64;
10847 int esize
= 32 << size
;
10848 int elements
= datasize
/ esize
;
10850 if (size
== 1 && !is_q
) {
10851 unallocated_encoding(s
);
10855 switch (fpopcode
) {
10856 case 0x58: /* FMAXNMP */
10857 case 0x5a: /* FADDP */
10858 case 0x5e: /* FMAXP */
10859 case 0x78: /* FMINNMP */
10860 case 0x7e: /* FMINP */
10861 if (size
&& !is_q
) {
10862 unallocated_encoding(s
);
10865 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10868 case 0x1b: /* FMULX */
10869 case 0x1f: /* FRECPS */
10870 case 0x3f: /* FRSQRTS */
10871 case 0x5d: /* FACGE */
10872 case 0x7d: /* FACGT */
10873 case 0x19: /* FMLA */
10874 case 0x39: /* FMLS */
10875 case 0x18: /* FMAXNM */
10876 case 0x1a: /* FADD */
10877 case 0x1c: /* FCMEQ */
10878 case 0x1e: /* FMAX */
10879 case 0x38: /* FMINNM */
10880 case 0x3a: /* FSUB */
10881 case 0x3e: /* FMIN */
10882 case 0x5b: /* FMUL */
10883 case 0x5c: /* FCMGE */
10884 case 0x5f: /* FDIV */
10885 case 0x7a: /* FABD */
10886 case 0x7c: /* FCMGT */
10887 if (!fp_access_check(s
)) {
10891 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10894 unallocated_encoding(s
);
10899 /* Integer op subgroup of C3.6.16. */
10900 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10902 int is_q
= extract32(insn
, 30, 1);
10903 int u
= extract32(insn
, 29, 1);
10904 int size
= extract32(insn
, 22, 2);
10905 int opcode
= extract32(insn
, 11, 5);
10906 int rm
= extract32(insn
, 16, 5);
10907 int rn
= extract32(insn
, 5, 5);
10908 int rd
= extract32(insn
, 0, 5);
10913 case 0x13: /* MUL, PMUL */
10914 if (u
&& size
!= 0) {
10915 unallocated_encoding(s
);
10919 case 0x0: /* SHADD, UHADD */
10920 case 0x2: /* SRHADD, URHADD */
10921 case 0x4: /* SHSUB, UHSUB */
10922 case 0xc: /* SMAX, UMAX */
10923 case 0xd: /* SMIN, UMIN */
10924 case 0xe: /* SABD, UABD */
10925 case 0xf: /* SABA, UABA */
10926 case 0x12: /* MLA, MLS */
10928 unallocated_encoding(s
);
10932 case 0x16: /* SQDMULH, SQRDMULH */
10933 if (size
== 0 || size
== 3) {
10934 unallocated_encoding(s
);
10939 if (size
== 3 && !is_q
) {
10940 unallocated_encoding(s
);
10946 if (!fp_access_check(s
)) {
10951 case 0x10: /* ADD, SUB */
10953 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10955 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10958 case 0x13: /* MUL, PMUL */
10959 if (!u
) { /* MUL */
10960 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10964 case 0x12: /* MLA, MLS */
10966 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10968 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10972 if (!u
) { /* CMTST */
10973 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10977 cond
= TCG_COND_EQ
;
10979 case 0x06: /* CMGT, CMHI */
10980 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10982 case 0x07: /* CMGE, CMHS */
10983 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10985 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10986 vec_full_reg_offset(s
, rn
),
10987 vec_full_reg_offset(s
, rm
),
10988 is_q
? 16 : 8, vec_full_reg_size(s
));
10994 for (pass
= 0; pass
< 2; pass
++) {
10995 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10996 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10997 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10999 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11000 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11002 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11004 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11006 tcg_temp_free_i64(tcg_res
);
11007 tcg_temp_free_i64(tcg_op1
);
11008 tcg_temp_free_i64(tcg_op2
);
11011 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11012 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11013 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11014 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11015 NeonGenTwoOpFn
*genfn
= NULL
;
11016 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11018 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11019 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11022 case 0x0: /* SHADD, UHADD */
11024 static NeonGenTwoOpFn
* const fns
[3][2] = {
11025 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11026 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11027 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11029 genfn
= fns
[size
][u
];
11032 case 0x1: /* SQADD, UQADD */
11034 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11035 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
11036 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
11037 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
11039 genenvfn
= fns
[size
][u
];
11042 case 0x2: /* SRHADD, URHADD */
11044 static NeonGenTwoOpFn
* const fns
[3][2] = {
11045 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11046 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11047 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11049 genfn
= fns
[size
][u
];
11052 case 0x4: /* SHSUB, UHSUB */
11054 static NeonGenTwoOpFn
* const fns
[3][2] = {
11055 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11056 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11057 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11059 genfn
= fns
[size
][u
];
11062 case 0x5: /* SQSUB, UQSUB */
11064 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11065 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
11066 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
11067 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
11069 genenvfn
= fns
[size
][u
];
11072 case 0x8: /* SSHL, USHL */
11074 static NeonGenTwoOpFn
* const fns
[3][2] = {
11075 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11076 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11077 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11079 genfn
= fns
[size
][u
];
11082 case 0x9: /* SQSHL, UQSHL */
11084 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11085 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11086 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11087 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11089 genenvfn
= fns
[size
][u
];
11092 case 0xa: /* SRSHL, URSHL */
11094 static NeonGenTwoOpFn
* const fns
[3][2] = {
11095 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11096 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11097 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11099 genfn
= fns
[size
][u
];
11102 case 0xb: /* SQRSHL, UQRSHL */
11104 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11105 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11106 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11107 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11109 genenvfn
= fns
[size
][u
];
11112 case 0xc: /* SMAX, UMAX */
11114 static NeonGenTwoOpFn
* const fns
[3][2] = {
11115 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
11116 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
11117 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11119 genfn
= fns
[size
][u
];
11123 case 0xd: /* SMIN, UMIN */
11125 static NeonGenTwoOpFn
* const fns
[3][2] = {
11126 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
11127 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
11128 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11130 genfn
= fns
[size
][u
];
11133 case 0xe: /* SABD, UABD */
11134 case 0xf: /* SABA, UABA */
11136 static NeonGenTwoOpFn
* const fns
[3][2] = {
11137 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11138 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11139 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11141 genfn
= fns
[size
][u
];
11144 case 0x13: /* MUL, PMUL */
11145 assert(u
); /* PMUL */
11147 genfn
= gen_helper_neon_mul_p8
;
11149 case 0x16: /* SQDMULH, SQRDMULH */
11151 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11152 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11153 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11155 assert(size
== 1 || size
== 2);
11156 genenvfn
= fns
[size
- 1][u
];
11160 g_assert_not_reached();
11164 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11166 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11169 if (opcode
== 0xf) {
11170 /* SABA, UABA: accumulating ops */
11171 static NeonGenTwoOpFn
* const fns
[3] = {
11172 gen_helper_neon_add_u8
,
11173 gen_helper_neon_add_u16
,
11177 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11178 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11181 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11183 tcg_temp_free_i32(tcg_res
);
11184 tcg_temp_free_i32(tcg_op1
);
11185 tcg_temp_free_i32(tcg_op2
);
11188 clear_vec_high(s
, is_q
, rd
);
11191 /* AdvSIMD three same
11192 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11193 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11194 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11195 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11197 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11199 int opcode
= extract32(insn
, 11, 5);
11202 case 0x3: /* logic ops */
11203 disas_simd_3same_logic(s
, insn
);
11205 case 0x17: /* ADDP */
11206 case 0x14: /* SMAXP, UMAXP */
11207 case 0x15: /* SMINP, UMINP */
11209 /* Pairwise operations */
11210 int is_q
= extract32(insn
, 30, 1);
11211 int u
= extract32(insn
, 29, 1);
11212 int size
= extract32(insn
, 22, 2);
11213 int rm
= extract32(insn
, 16, 5);
11214 int rn
= extract32(insn
, 5, 5);
11215 int rd
= extract32(insn
, 0, 5);
11216 if (opcode
== 0x17) {
11217 if (u
|| (size
== 3 && !is_q
)) {
11218 unallocated_encoding(s
);
11223 unallocated_encoding(s
);
11227 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11230 case 0x18 ... 0x31:
11231 /* floating point ops, sz[1] and U are part of opcode */
11232 disas_simd_3same_float(s
, insn
);
11235 disas_simd_3same_int(s
, insn
);
11241 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11243 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11244 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11245 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11246 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11248 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11249 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11252 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11254 int opcode
, fpopcode
;
11255 int is_q
, u
, a
, rm
, rn
, rd
;
11256 int datasize
, elements
;
11259 bool pairwise
= false;
11261 if (!dc_isar_feature(aa64_fp16
, s
)) {
11262 unallocated_encoding(s
);
11266 if (!fp_access_check(s
)) {
11270 /* For these floating point ops, the U, a and opcode bits
11271 * together indicate the operation.
11273 opcode
= extract32(insn
, 11, 3);
11274 u
= extract32(insn
, 29, 1);
11275 a
= extract32(insn
, 23, 1);
11276 is_q
= extract32(insn
, 30, 1);
11277 rm
= extract32(insn
, 16, 5);
11278 rn
= extract32(insn
, 5, 5);
11279 rd
= extract32(insn
, 0, 5);
11281 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11282 datasize
= is_q
? 128 : 64;
11283 elements
= datasize
/ 16;
11285 switch (fpopcode
) {
11286 case 0x10: /* FMAXNMP */
11287 case 0x12: /* FADDP */
11288 case 0x16: /* FMAXP */
11289 case 0x18: /* FMINNMP */
11290 case 0x1e: /* FMINP */
11295 fpst
= get_fpstatus_ptr(true);
11298 int maxpass
= is_q
? 8 : 4;
11299 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11300 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11301 TCGv_i32 tcg_res
[8];
11303 for (pass
= 0; pass
< maxpass
; pass
++) {
11304 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11305 int passelt
= (pass
<< 1) & (maxpass
- 1);
11307 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11308 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11309 tcg_res
[pass
] = tcg_temp_new_i32();
11311 switch (fpopcode
) {
11312 case 0x10: /* FMAXNMP */
11313 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11316 case 0x12: /* FADDP */
11317 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11319 case 0x16: /* FMAXP */
11320 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11322 case 0x18: /* FMINNMP */
11323 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11326 case 0x1e: /* FMINP */
11327 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11330 g_assert_not_reached();
11334 for (pass
= 0; pass
< maxpass
; pass
++) {
11335 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11336 tcg_temp_free_i32(tcg_res
[pass
]);
11339 tcg_temp_free_i32(tcg_op1
);
11340 tcg_temp_free_i32(tcg_op2
);
11343 for (pass
= 0; pass
< elements
; pass
++) {
11344 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11345 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11346 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11348 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11349 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11351 switch (fpopcode
) {
11352 case 0x0: /* FMAXNM */
11353 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11355 case 0x1: /* FMLA */
11356 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11357 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11360 case 0x2: /* FADD */
11361 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11363 case 0x3: /* FMULX */
11364 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11366 case 0x4: /* FCMEQ */
11367 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11369 case 0x6: /* FMAX */
11370 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11372 case 0x7: /* FRECPS */
11373 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11375 case 0x8: /* FMINNM */
11376 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11378 case 0x9: /* FMLS */
11379 /* As usual for ARM, separate negation for fused multiply-add */
11380 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11381 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11382 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11385 case 0xa: /* FSUB */
11386 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11388 case 0xe: /* FMIN */
11389 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11391 case 0xf: /* FRSQRTS */
11392 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11394 case 0x13: /* FMUL */
11395 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11397 case 0x14: /* FCMGE */
11398 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11400 case 0x15: /* FACGE */
11401 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11403 case 0x17: /* FDIV */
11404 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11406 case 0x1a: /* FABD */
11407 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11408 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11410 case 0x1c: /* FCMGT */
11411 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11413 case 0x1d: /* FACGT */
11414 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11417 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11418 __func__
, insn
, fpopcode
, s
->pc
);
11419 g_assert_not_reached();
11422 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11423 tcg_temp_free_i32(tcg_res
);
11424 tcg_temp_free_i32(tcg_op1
);
11425 tcg_temp_free_i32(tcg_op2
);
11429 tcg_temp_free_ptr(fpst
);
11431 clear_vec_high(s
, is_q
, rd
);
11434 /* AdvSIMD three same extra
11435 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11436 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11437 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11438 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11440 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11442 int rd
= extract32(insn
, 0, 5);
11443 int rn
= extract32(insn
, 5, 5);
11444 int opcode
= extract32(insn
, 11, 4);
11445 int rm
= extract32(insn
, 16, 5);
11446 int size
= extract32(insn
, 22, 2);
11447 bool u
= extract32(insn
, 29, 1);
11448 bool is_q
= extract32(insn
, 30, 1);
11452 switch (u
* 16 + opcode
) {
11453 case 0x10: /* SQRDMLAH (vector) */
11454 case 0x11: /* SQRDMLSH (vector) */
11455 if (size
!= 1 && size
!= 2) {
11456 unallocated_encoding(s
);
11459 feature
= dc_isar_feature(aa64_rdm
, s
);
11461 case 0x02: /* SDOT (vector) */
11462 case 0x12: /* UDOT (vector) */
11463 if (size
!= MO_32
) {
11464 unallocated_encoding(s
);
11467 feature
= dc_isar_feature(aa64_dp
, s
);
11469 case 0x18: /* FCMLA, #0 */
11470 case 0x19: /* FCMLA, #90 */
11471 case 0x1a: /* FCMLA, #180 */
11472 case 0x1b: /* FCMLA, #270 */
11473 case 0x1c: /* FCADD, #90 */
11474 case 0x1e: /* FCADD, #270 */
11476 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11477 || (size
== 3 && !is_q
)) {
11478 unallocated_encoding(s
);
11481 feature
= dc_isar_feature(aa64_fcma
, s
);
11484 unallocated_encoding(s
);
11488 unallocated_encoding(s
);
11491 if (!fp_access_check(s
)) {
11496 case 0x0: /* SQRDMLAH (vector) */
11499 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11502 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11505 g_assert_not_reached();
11509 case 0x1: /* SQRDMLSH (vector) */
11512 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11515 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11518 g_assert_not_reached();
11522 case 0x2: /* SDOT / UDOT */
11523 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11524 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11527 case 0x8: /* FCMLA, #0 */
11528 case 0x9: /* FCMLA, #90 */
11529 case 0xa: /* FCMLA, #180 */
11530 case 0xb: /* FCMLA, #270 */
11531 rot
= extract32(opcode
, 0, 2);
11534 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11535 gen_helper_gvec_fcmlah
);
11538 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11539 gen_helper_gvec_fcmlas
);
11542 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11543 gen_helper_gvec_fcmlad
);
11546 g_assert_not_reached();
11550 case 0xc: /* FCADD, #90 */
11551 case 0xe: /* FCADD, #270 */
11552 rot
= extract32(opcode
, 1, 1);
11555 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11556 gen_helper_gvec_fcaddh
);
11559 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11560 gen_helper_gvec_fcadds
);
11563 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11564 gen_helper_gvec_fcaddd
);
11567 g_assert_not_reached();
11572 g_assert_not_reached();
11576 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11577 int size
, int rn
, int rd
)
11579 /* Handle 2-reg-misc ops which are widening (so each size element
11580 * in the source becomes a 2*size element in the destination.
11581 * The only instruction like this is FCVTL.
11586 /* 32 -> 64 bit fp conversion */
11587 TCGv_i64 tcg_res
[2];
11588 int srcelt
= is_q
? 2 : 0;
11590 for (pass
= 0; pass
< 2; pass
++) {
11591 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11592 tcg_res
[pass
] = tcg_temp_new_i64();
11594 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11595 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11596 tcg_temp_free_i32(tcg_op
);
11598 for (pass
= 0; pass
< 2; pass
++) {
11599 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11600 tcg_temp_free_i64(tcg_res
[pass
]);
11603 /* 16 -> 32 bit fp conversion */
11604 int srcelt
= is_q
? 4 : 0;
11605 TCGv_i32 tcg_res
[4];
11606 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11607 TCGv_i32 ahp
= get_ahp_flag();
11609 for (pass
= 0; pass
< 4; pass
++) {
11610 tcg_res
[pass
] = tcg_temp_new_i32();
11612 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11613 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11616 for (pass
= 0; pass
< 4; pass
++) {
11617 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11618 tcg_temp_free_i32(tcg_res
[pass
]);
11621 tcg_temp_free_ptr(fpst
);
11622 tcg_temp_free_i32(ahp
);
11626 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11627 bool is_q
, int size
, int rn
, int rd
)
11629 int op
= (opcode
<< 1) | u
;
11630 int opsz
= op
+ size
;
11631 int grp_size
= 3 - opsz
;
11632 int dsize
= is_q
? 128 : 64;
11636 unallocated_encoding(s
);
11640 if (!fp_access_check(s
)) {
11645 /* Special case bytes, use bswap op on each group of elements */
11646 int groups
= dsize
/ (8 << grp_size
);
11648 for (i
= 0; i
< groups
; i
++) {
11649 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11651 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11652 switch (grp_size
) {
11654 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11657 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11660 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11663 g_assert_not_reached();
11665 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11666 tcg_temp_free_i64(tcg_tmp
);
11668 clear_vec_high(s
, is_q
, rd
);
11670 int revmask
= (1 << grp_size
) - 1;
11671 int esize
= 8 << size
;
11672 int elements
= dsize
/ esize
;
11673 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11674 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11675 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11677 for (i
= 0; i
< elements
; i
++) {
11678 int e_rev
= (i
& 0xf) ^ revmask
;
11679 int off
= e_rev
* esize
;
11680 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11682 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11683 tcg_rn
, off
- 64, esize
);
11685 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11688 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11689 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11691 tcg_temp_free_i64(tcg_rd_hi
);
11692 tcg_temp_free_i64(tcg_rd
);
11693 tcg_temp_free_i64(tcg_rn
);
11697 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11698 bool is_q
, int size
, int rn
, int rd
)
11700 /* Implement the pairwise operations from 2-misc:
11701 * SADDLP, UADDLP, SADALP, UADALP.
11702 * These all add pairs of elements in the input to produce a
11703 * double-width result element in the output (possibly accumulating).
11705 bool accum
= (opcode
== 0x6);
11706 int maxpass
= is_q
? 2 : 1;
11708 TCGv_i64 tcg_res
[2];
11711 /* 32 + 32 -> 64 op */
11712 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11714 for (pass
= 0; pass
< maxpass
; pass
++) {
11715 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11716 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11718 tcg_res
[pass
] = tcg_temp_new_i64();
11720 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11721 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11722 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11724 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11725 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11728 tcg_temp_free_i64(tcg_op1
);
11729 tcg_temp_free_i64(tcg_op2
);
11732 for (pass
= 0; pass
< maxpass
; pass
++) {
11733 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11734 NeonGenOneOpFn
*genfn
;
11735 static NeonGenOneOpFn
* const fns
[2][2] = {
11736 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11737 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11740 genfn
= fns
[size
][u
];
11742 tcg_res
[pass
] = tcg_temp_new_i64();
11744 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11745 genfn(tcg_res
[pass
], tcg_op
);
11748 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11750 gen_helper_neon_addl_u16(tcg_res
[pass
],
11751 tcg_res
[pass
], tcg_op
);
11753 gen_helper_neon_addl_u32(tcg_res
[pass
],
11754 tcg_res
[pass
], tcg_op
);
11757 tcg_temp_free_i64(tcg_op
);
11761 tcg_res
[1] = tcg_const_i64(0);
11763 for (pass
= 0; pass
< 2; pass
++) {
11764 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11765 tcg_temp_free_i64(tcg_res
[pass
]);
11769 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11771 /* Implement SHLL and SHLL2 */
11773 int part
= is_q
? 2 : 0;
11774 TCGv_i64 tcg_res
[2];
11776 for (pass
= 0; pass
< 2; pass
++) {
11777 static NeonGenWidenFn
* const widenfns
[3] = {
11778 gen_helper_neon_widen_u8
,
11779 gen_helper_neon_widen_u16
,
11780 tcg_gen_extu_i32_i64
,
11782 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11783 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11785 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11786 tcg_res
[pass
] = tcg_temp_new_i64();
11787 widenfn(tcg_res
[pass
], tcg_op
);
11788 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11790 tcg_temp_free_i32(tcg_op
);
11793 for (pass
= 0; pass
< 2; pass
++) {
11794 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11795 tcg_temp_free_i64(tcg_res
[pass
]);
11799 /* AdvSIMD two reg misc
11800 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11801 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11802 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11803 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11805 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11807 int size
= extract32(insn
, 22, 2);
11808 int opcode
= extract32(insn
, 12, 5);
11809 bool u
= extract32(insn
, 29, 1);
11810 bool is_q
= extract32(insn
, 30, 1);
11811 int rn
= extract32(insn
, 5, 5);
11812 int rd
= extract32(insn
, 0, 5);
11813 bool need_fpstatus
= false;
11814 bool need_rmode
= false;
11816 TCGv_i32 tcg_rmode
;
11817 TCGv_ptr tcg_fpstatus
;
11820 case 0x0: /* REV64, REV32 */
11821 case 0x1: /* REV16 */
11822 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11824 case 0x5: /* CNT, NOT, RBIT */
11825 if (u
&& size
== 0) {
11828 } else if (u
&& size
== 1) {
11831 } else if (!u
&& size
== 0) {
11835 unallocated_encoding(s
);
11837 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11838 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11840 unallocated_encoding(s
);
11843 if (!fp_access_check(s
)) {
11847 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11849 case 0x4: /* CLS, CLZ */
11851 unallocated_encoding(s
);
11855 case 0x2: /* SADDLP, UADDLP */
11856 case 0x6: /* SADALP, UADALP */
11858 unallocated_encoding(s
);
11861 if (!fp_access_check(s
)) {
11864 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11866 case 0x13: /* SHLL, SHLL2 */
11867 if (u
== 0 || size
== 3) {
11868 unallocated_encoding(s
);
11871 if (!fp_access_check(s
)) {
11874 handle_shll(s
, is_q
, size
, rn
, rd
);
11876 case 0xa: /* CMLT */
11878 unallocated_encoding(s
);
11882 case 0x8: /* CMGT, CMGE */
11883 case 0x9: /* CMEQ, CMLE */
11884 case 0xb: /* ABS, NEG */
11885 if (size
== 3 && !is_q
) {
11886 unallocated_encoding(s
);
11890 case 0x3: /* SUQADD, USQADD */
11891 if (size
== 3 && !is_q
) {
11892 unallocated_encoding(s
);
11895 if (!fp_access_check(s
)) {
11898 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11900 case 0x7: /* SQABS, SQNEG */
11901 if (size
== 3 && !is_q
) {
11902 unallocated_encoding(s
);
11907 case 0x16 ... 0x1d:
11910 /* Floating point: U, size[1] and opcode indicate operation;
11911 * size[0] indicates single or double precision.
11913 int is_double
= extract32(size
, 0, 1);
11914 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11915 size
= is_double
? 3 : 2;
11917 case 0x2f: /* FABS */
11918 case 0x6f: /* FNEG */
11919 if (size
== 3 && !is_q
) {
11920 unallocated_encoding(s
);
11924 case 0x1d: /* SCVTF */
11925 case 0x5d: /* UCVTF */
11927 bool is_signed
= (opcode
== 0x1d) ? true : false;
11928 int elements
= is_double
? 2 : is_q
? 4 : 2;
11929 if (is_double
&& !is_q
) {
11930 unallocated_encoding(s
);
11933 if (!fp_access_check(s
)) {
11936 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11939 case 0x2c: /* FCMGT (zero) */
11940 case 0x2d: /* FCMEQ (zero) */
11941 case 0x2e: /* FCMLT (zero) */
11942 case 0x6c: /* FCMGE (zero) */
11943 case 0x6d: /* FCMLE (zero) */
11944 if (size
== 3 && !is_q
) {
11945 unallocated_encoding(s
);
11948 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11950 case 0x7f: /* FSQRT */
11951 if (size
== 3 && !is_q
) {
11952 unallocated_encoding(s
);
11956 case 0x1a: /* FCVTNS */
11957 case 0x1b: /* FCVTMS */
11958 case 0x3a: /* FCVTPS */
11959 case 0x3b: /* FCVTZS */
11960 case 0x5a: /* FCVTNU */
11961 case 0x5b: /* FCVTMU */
11962 case 0x7a: /* FCVTPU */
11963 case 0x7b: /* FCVTZU */
11964 need_fpstatus
= true;
11966 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11967 if (size
== 3 && !is_q
) {
11968 unallocated_encoding(s
);
11972 case 0x5c: /* FCVTAU */
11973 case 0x1c: /* FCVTAS */
11974 need_fpstatus
= true;
11976 rmode
= FPROUNDING_TIEAWAY
;
11977 if (size
== 3 && !is_q
) {
11978 unallocated_encoding(s
);
11982 case 0x3c: /* URECPE */
11984 unallocated_encoding(s
);
11988 case 0x3d: /* FRECPE */
11989 case 0x7d: /* FRSQRTE */
11990 if (size
== 3 && !is_q
) {
11991 unallocated_encoding(s
);
11994 if (!fp_access_check(s
)) {
11997 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11999 case 0x56: /* FCVTXN, FCVTXN2 */
12001 unallocated_encoding(s
);
12005 case 0x16: /* FCVTN, FCVTN2 */
12006 /* handle_2misc_narrow does a 2*size -> size operation, but these
12007 * instructions encode the source size rather than dest size.
12009 if (!fp_access_check(s
)) {
12012 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12014 case 0x17: /* FCVTL, FCVTL2 */
12015 if (!fp_access_check(s
)) {
12018 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12020 case 0x18: /* FRINTN */
12021 case 0x19: /* FRINTM */
12022 case 0x38: /* FRINTP */
12023 case 0x39: /* FRINTZ */
12025 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12027 case 0x59: /* FRINTX */
12028 case 0x79: /* FRINTI */
12029 need_fpstatus
= true;
12030 if (size
== 3 && !is_q
) {
12031 unallocated_encoding(s
);
12035 case 0x58: /* FRINTA */
12037 rmode
= FPROUNDING_TIEAWAY
;
12038 need_fpstatus
= true;
12039 if (size
== 3 && !is_q
) {
12040 unallocated_encoding(s
);
12044 case 0x7c: /* URSQRTE */
12046 unallocated_encoding(s
);
12049 need_fpstatus
= true;
12052 unallocated_encoding(s
);
12058 unallocated_encoding(s
);
12062 if (!fp_access_check(s
)) {
12066 if (need_fpstatus
|| need_rmode
) {
12067 tcg_fpstatus
= get_fpstatus_ptr(false);
12069 tcg_fpstatus
= NULL
;
12072 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12073 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12080 if (u
&& size
== 0) { /* NOT */
12081 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12087 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12094 /* All 64-bit element operations can be shared with scalar 2misc */
12097 /* Coverity claims (size == 3 && !is_q) has been eliminated
12098 * from all paths leading to here.
12100 tcg_debug_assert(is_q
);
12101 for (pass
= 0; pass
< 2; pass
++) {
12102 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12103 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12105 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12107 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12108 tcg_rmode
, tcg_fpstatus
);
12110 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12112 tcg_temp_free_i64(tcg_res
);
12113 tcg_temp_free_i64(tcg_op
);
12118 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12119 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12120 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12123 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12126 /* Special cases for 32 bit elements */
12128 case 0xa: /* CMLT */
12129 /* 32 bit integer comparison against zero, result is
12130 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12133 cond
= TCG_COND_LT
;
12135 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12136 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12138 case 0x8: /* CMGT, CMGE */
12139 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12141 case 0x9: /* CMEQ, CMLE */
12142 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12144 case 0x4: /* CLS */
12146 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12148 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12151 case 0x7: /* SQABS, SQNEG */
12153 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12155 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12158 case 0xb: /* ABS, NEG */
12160 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12162 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12163 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12164 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12165 tcg_zero
, tcg_op
, tcg_res
);
12166 tcg_temp_free_i32(tcg_zero
);
12169 case 0x2f: /* FABS */
12170 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12172 case 0x6f: /* FNEG */
12173 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12175 case 0x7f: /* FSQRT */
12176 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12178 case 0x1a: /* FCVTNS */
12179 case 0x1b: /* FCVTMS */
12180 case 0x1c: /* FCVTAS */
12181 case 0x3a: /* FCVTPS */
12182 case 0x3b: /* FCVTZS */
12184 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12185 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12186 tcg_shift
, tcg_fpstatus
);
12187 tcg_temp_free_i32(tcg_shift
);
12190 case 0x5a: /* FCVTNU */
12191 case 0x5b: /* FCVTMU */
12192 case 0x5c: /* FCVTAU */
12193 case 0x7a: /* FCVTPU */
12194 case 0x7b: /* FCVTZU */
12196 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12197 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12198 tcg_shift
, tcg_fpstatus
);
12199 tcg_temp_free_i32(tcg_shift
);
12202 case 0x18: /* FRINTN */
12203 case 0x19: /* FRINTM */
12204 case 0x38: /* FRINTP */
12205 case 0x39: /* FRINTZ */
12206 case 0x58: /* FRINTA */
12207 case 0x79: /* FRINTI */
12208 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12210 case 0x59: /* FRINTX */
12211 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12213 case 0x7c: /* URSQRTE */
12214 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12217 g_assert_not_reached();
12220 /* Use helpers for 8 and 16 bit elements */
12222 case 0x5: /* CNT, RBIT */
12223 /* For these two insns size is part of the opcode specifier
12224 * (handled earlier); they always operate on byte elements.
12227 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12229 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12232 case 0x7: /* SQABS, SQNEG */
12234 NeonGenOneOpEnvFn
*genfn
;
12235 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12236 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12237 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12239 genfn
= fns
[size
][u
];
12240 genfn(tcg_res
, cpu_env
, tcg_op
);
12243 case 0x8: /* CMGT, CMGE */
12244 case 0x9: /* CMEQ, CMLE */
12245 case 0xa: /* CMLT */
12247 static NeonGenTwoOpFn
* const fns
[3][2] = {
12248 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12249 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12250 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12252 NeonGenTwoOpFn
*genfn
;
12255 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12257 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12258 comp
= (opcode
- 0x8) * 2 + u
;
12259 /* ...but LE, LT are implemented as reverse GE, GT */
12260 reverse
= (comp
> 2);
12264 genfn
= fns
[comp
][size
];
12266 genfn(tcg_res
, tcg_zero
, tcg_op
);
12268 genfn(tcg_res
, tcg_op
, tcg_zero
);
12270 tcg_temp_free_i32(tcg_zero
);
12273 case 0xb: /* ABS, NEG */
12275 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12277 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12279 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12281 tcg_temp_free_i32(tcg_zero
);
12284 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12286 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12290 case 0x4: /* CLS, CLZ */
12293 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12295 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12299 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12301 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12306 g_assert_not_reached();
12310 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12312 tcg_temp_free_i32(tcg_res
);
12313 tcg_temp_free_i32(tcg_op
);
12316 clear_vec_high(s
, is_q
, rd
);
12319 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12320 tcg_temp_free_i32(tcg_rmode
);
12322 if (need_fpstatus
) {
12323 tcg_temp_free_ptr(tcg_fpstatus
);
12327 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12329 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12330 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12331 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12332 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12333 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12334 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12336 * This actually covers two groups where scalar access is governed by
12337 * bit 28. A bunch of the instructions (float to integral) only exist
12338 * in the vector form and are un-allocated for the scalar decode. Also
12339 * in the scalar decode Q is always 1.
12341 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12343 int fpop
, opcode
, a
, u
;
12347 bool only_in_vector
= false;
12350 TCGv_i32 tcg_rmode
= NULL
;
12351 TCGv_ptr tcg_fpstatus
= NULL
;
12352 bool need_rmode
= false;
12353 bool need_fpst
= true;
12356 if (!dc_isar_feature(aa64_fp16
, s
)) {
12357 unallocated_encoding(s
);
12361 rd
= extract32(insn
, 0, 5);
12362 rn
= extract32(insn
, 5, 5);
12364 a
= extract32(insn
, 23, 1);
12365 u
= extract32(insn
, 29, 1);
12366 is_scalar
= extract32(insn
, 28, 1);
12367 is_q
= extract32(insn
, 30, 1);
12369 opcode
= extract32(insn
, 12, 5);
12370 fpop
= deposit32(opcode
, 5, 1, a
);
12371 fpop
= deposit32(fpop
, 6, 1, u
);
12373 rd
= extract32(insn
, 0, 5);
12374 rn
= extract32(insn
, 5, 5);
12377 case 0x1d: /* SCVTF */
12378 case 0x5d: /* UCVTF */
12385 elements
= (is_q
? 8 : 4);
12388 if (!fp_access_check(s
)) {
12391 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12395 case 0x2c: /* FCMGT (zero) */
12396 case 0x2d: /* FCMEQ (zero) */
12397 case 0x2e: /* FCMLT (zero) */
12398 case 0x6c: /* FCMGE (zero) */
12399 case 0x6d: /* FCMLE (zero) */
12400 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12402 case 0x3d: /* FRECPE */
12403 case 0x3f: /* FRECPX */
12405 case 0x18: /* FRINTN */
12407 only_in_vector
= true;
12408 rmode
= FPROUNDING_TIEEVEN
;
12410 case 0x19: /* FRINTM */
12412 only_in_vector
= true;
12413 rmode
= FPROUNDING_NEGINF
;
12415 case 0x38: /* FRINTP */
12417 only_in_vector
= true;
12418 rmode
= FPROUNDING_POSINF
;
12420 case 0x39: /* FRINTZ */
12422 only_in_vector
= true;
12423 rmode
= FPROUNDING_ZERO
;
12425 case 0x58: /* FRINTA */
12427 only_in_vector
= true;
12428 rmode
= FPROUNDING_TIEAWAY
;
12430 case 0x59: /* FRINTX */
12431 case 0x79: /* FRINTI */
12432 only_in_vector
= true;
12433 /* current rounding mode */
12435 case 0x1a: /* FCVTNS */
12437 rmode
= FPROUNDING_TIEEVEN
;
12439 case 0x1b: /* FCVTMS */
12441 rmode
= FPROUNDING_NEGINF
;
12443 case 0x1c: /* FCVTAS */
12445 rmode
= FPROUNDING_TIEAWAY
;
12447 case 0x3a: /* FCVTPS */
12449 rmode
= FPROUNDING_POSINF
;
12451 case 0x3b: /* FCVTZS */
12453 rmode
= FPROUNDING_ZERO
;
12455 case 0x5a: /* FCVTNU */
12457 rmode
= FPROUNDING_TIEEVEN
;
12459 case 0x5b: /* FCVTMU */
12461 rmode
= FPROUNDING_NEGINF
;
12463 case 0x5c: /* FCVTAU */
12465 rmode
= FPROUNDING_TIEAWAY
;
12467 case 0x7a: /* FCVTPU */
12469 rmode
= FPROUNDING_POSINF
;
12471 case 0x7b: /* FCVTZU */
12473 rmode
= FPROUNDING_ZERO
;
12475 case 0x2f: /* FABS */
12476 case 0x6f: /* FNEG */
12479 case 0x7d: /* FRSQRTE */
12480 case 0x7f: /* FSQRT (vector) */
12483 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12484 g_assert_not_reached();
12488 /* Check additional constraints for the scalar encoding */
12491 unallocated_encoding(s
);
12494 /* FRINTxx is only in the vector form */
12495 if (only_in_vector
) {
12496 unallocated_encoding(s
);
12501 if (!fp_access_check(s
)) {
12505 if (need_rmode
|| need_fpst
) {
12506 tcg_fpstatus
= get_fpstatus_ptr(true);
12510 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12511 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12515 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12516 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12519 case 0x1a: /* FCVTNS */
12520 case 0x1b: /* FCVTMS */
12521 case 0x1c: /* FCVTAS */
12522 case 0x3a: /* FCVTPS */
12523 case 0x3b: /* FCVTZS */
12524 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12526 case 0x3d: /* FRECPE */
12527 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12529 case 0x3f: /* FRECPX */
12530 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12532 case 0x5a: /* FCVTNU */
12533 case 0x5b: /* FCVTMU */
12534 case 0x5c: /* FCVTAU */
12535 case 0x7a: /* FCVTPU */
12536 case 0x7b: /* FCVTZU */
12537 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12539 case 0x6f: /* FNEG */
12540 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12542 case 0x7d: /* FRSQRTE */
12543 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12546 g_assert_not_reached();
12549 /* limit any sign extension going on */
12550 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12551 write_fp_sreg(s
, rd
, tcg_res
);
12553 tcg_temp_free_i32(tcg_res
);
12554 tcg_temp_free_i32(tcg_op
);
12556 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12557 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12558 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12560 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12563 case 0x1a: /* FCVTNS */
12564 case 0x1b: /* FCVTMS */
12565 case 0x1c: /* FCVTAS */
12566 case 0x3a: /* FCVTPS */
12567 case 0x3b: /* FCVTZS */
12568 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12570 case 0x3d: /* FRECPE */
12571 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12573 case 0x5a: /* FCVTNU */
12574 case 0x5b: /* FCVTMU */
12575 case 0x5c: /* FCVTAU */
12576 case 0x7a: /* FCVTPU */
12577 case 0x7b: /* FCVTZU */
12578 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12580 case 0x18: /* FRINTN */
12581 case 0x19: /* FRINTM */
12582 case 0x38: /* FRINTP */
12583 case 0x39: /* FRINTZ */
12584 case 0x58: /* FRINTA */
12585 case 0x79: /* FRINTI */
12586 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12588 case 0x59: /* FRINTX */
12589 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12591 case 0x2f: /* FABS */
12592 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12594 case 0x6f: /* FNEG */
12595 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12597 case 0x7d: /* FRSQRTE */
12598 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12600 case 0x7f: /* FSQRT */
12601 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12604 g_assert_not_reached();
12607 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12609 tcg_temp_free_i32(tcg_res
);
12610 tcg_temp_free_i32(tcg_op
);
12613 clear_vec_high(s
, is_q
, rd
);
12617 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12618 tcg_temp_free_i32(tcg_rmode
);
12621 if (tcg_fpstatus
) {
12622 tcg_temp_free_ptr(tcg_fpstatus
);
12626 /* AdvSIMD scalar x indexed element
12627 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12628 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12629 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12630 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12631 * AdvSIMD vector x indexed element
12632 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12633 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12634 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12635 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12637 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12639 /* This encoding has two kinds of instruction:
12640 * normal, where we perform elt x idxelt => elt for each
12641 * element in the vector
12642 * long, where we perform elt x idxelt and generate a result of
12643 * double the width of the input element
12644 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12646 bool is_scalar
= extract32(insn
, 28, 1);
12647 bool is_q
= extract32(insn
, 30, 1);
12648 bool u
= extract32(insn
, 29, 1);
12649 int size
= extract32(insn
, 22, 2);
12650 int l
= extract32(insn
, 21, 1);
12651 int m
= extract32(insn
, 20, 1);
12652 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12653 int rm
= extract32(insn
, 16, 4);
12654 int opcode
= extract32(insn
, 12, 4);
12655 int h
= extract32(insn
, 11, 1);
12656 int rn
= extract32(insn
, 5, 5);
12657 int rd
= extract32(insn
, 0, 5);
12658 bool is_long
= false;
12660 bool is_fp16
= false;
12664 switch (16 * u
+ opcode
) {
12665 case 0x08: /* MUL */
12666 case 0x10: /* MLA */
12667 case 0x14: /* MLS */
12669 unallocated_encoding(s
);
12673 case 0x02: /* SMLAL, SMLAL2 */
12674 case 0x12: /* UMLAL, UMLAL2 */
12675 case 0x06: /* SMLSL, SMLSL2 */
12676 case 0x16: /* UMLSL, UMLSL2 */
12677 case 0x0a: /* SMULL, SMULL2 */
12678 case 0x1a: /* UMULL, UMULL2 */
12680 unallocated_encoding(s
);
12685 case 0x03: /* SQDMLAL, SQDMLAL2 */
12686 case 0x07: /* SQDMLSL, SQDMLSL2 */
12687 case 0x0b: /* SQDMULL, SQDMULL2 */
12690 case 0x0c: /* SQDMULH */
12691 case 0x0d: /* SQRDMULH */
12693 case 0x01: /* FMLA */
12694 case 0x05: /* FMLS */
12695 case 0x09: /* FMUL */
12696 case 0x19: /* FMULX */
12699 case 0x1d: /* SQRDMLAH */
12700 case 0x1f: /* SQRDMLSH */
12701 if (!dc_isar_feature(aa64_rdm
, s
)) {
12702 unallocated_encoding(s
);
12706 case 0x0e: /* SDOT */
12707 case 0x1e: /* UDOT */
12708 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12709 unallocated_encoding(s
);
12713 case 0x11: /* FCMLA #0 */
12714 case 0x13: /* FCMLA #90 */
12715 case 0x15: /* FCMLA #180 */
12716 case 0x17: /* FCMLA #270 */
12717 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12718 unallocated_encoding(s
);
12724 unallocated_encoding(s
);
12729 case 1: /* normal fp */
12730 /* convert insn encoded size to TCGMemOp size */
12732 case 0: /* half-precision */
12736 case MO_32
: /* single precision */
12737 case MO_64
: /* double precision */
12740 unallocated_encoding(s
);
12745 case 2: /* complex fp */
12746 /* Each indexable element is a complex pair. */
12751 unallocated_encoding(s
);
12759 unallocated_encoding(s
);
12764 default: /* integer */
12768 unallocated_encoding(s
);
12773 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12774 unallocated_encoding(s
);
12778 /* Given TCGMemOp size, adjust register and indexing. */
12781 index
= h
<< 2 | l
<< 1 | m
;
12784 index
= h
<< 1 | l
;
12789 unallocated_encoding(s
);
12796 g_assert_not_reached();
12799 if (!fp_access_check(s
)) {
12804 fpst
= get_fpstatus_ptr(is_fp16
);
12809 switch (16 * u
+ opcode
) {
12810 case 0x0e: /* SDOT */
12811 case 0x1e: /* UDOT */
12812 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12813 u
? gen_helper_gvec_udot_idx_b
12814 : gen_helper_gvec_sdot_idx_b
);
12816 case 0x11: /* FCMLA #0 */
12817 case 0x13: /* FCMLA #90 */
12818 case 0x15: /* FCMLA #180 */
12819 case 0x17: /* FCMLA #270 */
12821 int rot
= extract32(insn
, 13, 2);
12822 int data
= (index
<< 2) | rot
;
12823 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12824 vec_full_reg_offset(s
, rn
),
12825 vec_full_reg_offset(s
, rm
), fpst
,
12826 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12828 ? gen_helper_gvec_fcmlas_idx
12829 : gen_helper_gvec_fcmlah_idx
);
12830 tcg_temp_free_ptr(fpst
);
12836 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12839 assert(is_fp
&& is_q
&& !is_long
);
12841 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12843 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12844 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12845 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12847 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12849 switch (16 * u
+ opcode
) {
12850 case 0x05: /* FMLS */
12851 /* As usual for ARM, separate negation for fused multiply-add */
12852 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12854 case 0x01: /* FMLA */
12855 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12856 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12858 case 0x09: /* FMUL */
12859 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12861 case 0x19: /* FMULX */
12862 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12865 g_assert_not_reached();
12868 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12869 tcg_temp_free_i64(tcg_op
);
12870 tcg_temp_free_i64(tcg_res
);
12873 tcg_temp_free_i64(tcg_idx
);
12874 clear_vec_high(s
, !is_scalar
, rd
);
12875 } else if (!is_long
) {
12876 /* 32 bit floating point, or 16 or 32 bit integer.
12877 * For the 16 bit scalar case we use the usual Neon helpers and
12878 * rely on the fact that 0 op 0 == 0 with no side effects.
12880 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12881 int pass
, maxpasses
;
12886 maxpasses
= is_q
? 4 : 2;
12889 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12891 if (size
== 1 && !is_scalar
) {
12892 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12893 * the index into both halves of the 32 bit tcg_idx and then use
12894 * the usual Neon helpers.
12896 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12899 for (pass
= 0; pass
< maxpasses
; pass
++) {
12900 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12901 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12903 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12905 switch (16 * u
+ opcode
) {
12906 case 0x08: /* MUL */
12907 case 0x10: /* MLA */
12908 case 0x14: /* MLS */
12910 static NeonGenTwoOpFn
* const fns
[2][2] = {
12911 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12912 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12914 NeonGenTwoOpFn
*genfn
;
12915 bool is_sub
= opcode
== 0x4;
12918 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12920 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12922 if (opcode
== 0x8) {
12925 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12926 genfn
= fns
[size
- 1][is_sub
];
12927 genfn(tcg_res
, tcg_op
, tcg_res
);
12930 case 0x05: /* FMLS */
12931 case 0x01: /* FMLA */
12932 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12933 is_scalar
? size
: MO_32
);
12936 if (opcode
== 0x5) {
12937 /* As usual for ARM, separate negation for fused
12939 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12942 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12945 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12950 if (opcode
== 0x5) {
12951 /* As usual for ARM, separate negation for
12952 * fused multiply-add */
12953 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12955 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12959 g_assert_not_reached();
12962 case 0x09: /* FMUL */
12966 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12969 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12974 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12977 g_assert_not_reached();
12980 case 0x19: /* FMULX */
12984 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12987 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12992 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12995 g_assert_not_reached();
12998 case 0x0c: /* SQDMULH */
13000 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13003 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13007 case 0x0d: /* SQRDMULH */
13009 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13012 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13016 case 0x1d: /* SQRDMLAH */
13017 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13018 is_scalar
? size
: MO_32
);
13020 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13021 tcg_op
, tcg_idx
, tcg_res
);
13023 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13024 tcg_op
, tcg_idx
, tcg_res
);
13027 case 0x1f: /* SQRDMLSH */
13028 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13029 is_scalar
? size
: MO_32
);
13031 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13032 tcg_op
, tcg_idx
, tcg_res
);
13034 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13035 tcg_op
, tcg_idx
, tcg_res
);
13039 g_assert_not_reached();
13043 write_fp_sreg(s
, rd
, tcg_res
);
13045 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13048 tcg_temp_free_i32(tcg_op
);
13049 tcg_temp_free_i32(tcg_res
);
13052 tcg_temp_free_i32(tcg_idx
);
13053 clear_vec_high(s
, is_q
, rd
);
13055 /* long ops: 16x16->32 or 32x32->64 */
13056 TCGv_i64 tcg_res
[2];
13058 bool satop
= extract32(opcode
, 0, 1);
13059 TCGMemOp memop
= MO_32
;
13066 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13068 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13070 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13071 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13072 TCGv_i64 tcg_passres
;
13078 passelt
= pass
+ (is_q
* 2);
13081 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13083 tcg_res
[pass
] = tcg_temp_new_i64();
13085 if (opcode
== 0xa || opcode
== 0xb) {
13086 /* Non-accumulating ops */
13087 tcg_passres
= tcg_res
[pass
];
13089 tcg_passres
= tcg_temp_new_i64();
13092 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13093 tcg_temp_free_i64(tcg_op
);
13096 /* saturating, doubling */
13097 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13098 tcg_passres
, tcg_passres
);
13101 if (opcode
== 0xa || opcode
== 0xb) {
13105 /* Accumulating op: handle accumulate step */
13106 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13109 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13110 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13112 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13113 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13115 case 0x7: /* SQDMLSL, SQDMLSL2 */
13116 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13118 case 0x3: /* SQDMLAL, SQDMLAL2 */
13119 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13124 g_assert_not_reached();
13126 tcg_temp_free_i64(tcg_passres
);
13128 tcg_temp_free_i64(tcg_idx
);
13130 clear_vec_high(s
, !is_scalar
, rd
);
13132 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13135 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13138 /* The simplest way to handle the 16x16 indexed ops is to
13139 * duplicate the index into both halves of the 32 bit tcg_idx
13140 * and then use the usual Neon helpers.
13142 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13145 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13146 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13147 TCGv_i64 tcg_passres
;
13150 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13152 read_vec_element_i32(s
, tcg_op
, rn
,
13153 pass
+ (is_q
* 2), MO_32
);
13156 tcg_res
[pass
] = tcg_temp_new_i64();
13158 if (opcode
== 0xa || opcode
== 0xb) {
13159 /* Non-accumulating ops */
13160 tcg_passres
= tcg_res
[pass
];
13162 tcg_passres
= tcg_temp_new_i64();
13165 if (memop
& MO_SIGN
) {
13166 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13168 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13171 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13172 tcg_passres
, tcg_passres
);
13174 tcg_temp_free_i32(tcg_op
);
13176 if (opcode
== 0xa || opcode
== 0xb) {
13180 /* Accumulating op: handle accumulate step */
13181 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13184 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13185 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13188 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13189 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13192 case 0x7: /* SQDMLSL, SQDMLSL2 */
13193 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13195 case 0x3: /* SQDMLAL, SQDMLAL2 */
13196 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13201 g_assert_not_reached();
13203 tcg_temp_free_i64(tcg_passres
);
13205 tcg_temp_free_i32(tcg_idx
);
13208 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13213 tcg_res
[1] = tcg_const_i64(0);
13216 for (pass
= 0; pass
< 2; pass
++) {
13217 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13218 tcg_temp_free_i64(tcg_res
[pass
]);
13223 tcg_temp_free_ptr(fpst
);
13228 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13229 * +-----------------+------+-----------+--------+-----+------+------+
13230 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13231 * +-----------------+------+-----------+--------+-----+------+------+
13233 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13235 int size
= extract32(insn
, 22, 2);
13236 int opcode
= extract32(insn
, 12, 5);
13237 int rn
= extract32(insn
, 5, 5);
13238 int rd
= extract32(insn
, 0, 5);
13240 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13241 TCGv_i32 tcg_decrypt
;
13242 CryptoThreeOpIntFn
*genfn
;
13244 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13245 unallocated_encoding(s
);
13250 case 0x4: /* AESE */
13252 genfn
= gen_helper_crypto_aese
;
13254 case 0x6: /* AESMC */
13256 genfn
= gen_helper_crypto_aesmc
;
13258 case 0x5: /* AESD */
13260 genfn
= gen_helper_crypto_aese
;
13262 case 0x7: /* AESIMC */
13264 genfn
= gen_helper_crypto_aesmc
;
13267 unallocated_encoding(s
);
13271 if (!fp_access_check(s
)) {
13275 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13276 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13277 tcg_decrypt
= tcg_const_i32(decrypt
);
13279 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13281 tcg_temp_free_ptr(tcg_rd_ptr
);
13282 tcg_temp_free_ptr(tcg_rn_ptr
);
13283 tcg_temp_free_i32(tcg_decrypt
);
13286 /* Crypto three-reg SHA
13287 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13288 * +-----------------+------+---+------+---+--------+-----+------+------+
13289 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13290 * +-----------------+------+---+------+---+--------+-----+------+------+
13292 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13294 int size
= extract32(insn
, 22, 2);
13295 int opcode
= extract32(insn
, 12, 3);
13296 int rm
= extract32(insn
, 16, 5);
13297 int rn
= extract32(insn
, 5, 5);
13298 int rd
= extract32(insn
, 0, 5);
13299 CryptoThreeOpFn
*genfn
;
13300 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13304 unallocated_encoding(s
);
13309 case 0: /* SHA1C */
13310 case 1: /* SHA1P */
13311 case 2: /* SHA1M */
13312 case 3: /* SHA1SU0 */
13314 feature
= dc_isar_feature(aa64_sha1
, s
);
13316 case 4: /* SHA256H */
13317 genfn
= gen_helper_crypto_sha256h
;
13318 feature
= dc_isar_feature(aa64_sha256
, s
);
13320 case 5: /* SHA256H2 */
13321 genfn
= gen_helper_crypto_sha256h2
;
13322 feature
= dc_isar_feature(aa64_sha256
, s
);
13324 case 6: /* SHA256SU1 */
13325 genfn
= gen_helper_crypto_sha256su1
;
13326 feature
= dc_isar_feature(aa64_sha256
, s
);
13329 unallocated_encoding(s
);
13334 unallocated_encoding(s
);
13338 if (!fp_access_check(s
)) {
13342 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13343 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13344 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13347 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13349 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13351 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13352 tcg_rm_ptr
, tcg_opcode
);
13353 tcg_temp_free_i32(tcg_opcode
);
13356 tcg_temp_free_ptr(tcg_rd_ptr
);
13357 tcg_temp_free_ptr(tcg_rn_ptr
);
13358 tcg_temp_free_ptr(tcg_rm_ptr
);
13361 /* Crypto two-reg SHA
13362 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13363 * +-----------------+------+-----------+--------+-----+------+------+
13364 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13365 * +-----------------+------+-----------+--------+-----+------+------+
13367 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13369 int size
= extract32(insn
, 22, 2);
13370 int opcode
= extract32(insn
, 12, 5);
13371 int rn
= extract32(insn
, 5, 5);
13372 int rd
= extract32(insn
, 0, 5);
13373 CryptoTwoOpFn
*genfn
;
13375 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13378 unallocated_encoding(s
);
13383 case 0: /* SHA1H */
13384 feature
= dc_isar_feature(aa64_sha1
, s
);
13385 genfn
= gen_helper_crypto_sha1h
;
13387 case 1: /* SHA1SU1 */
13388 feature
= dc_isar_feature(aa64_sha1
, s
);
13389 genfn
= gen_helper_crypto_sha1su1
;
13391 case 2: /* SHA256SU0 */
13392 feature
= dc_isar_feature(aa64_sha256
, s
);
13393 genfn
= gen_helper_crypto_sha256su0
;
13396 unallocated_encoding(s
);
13401 unallocated_encoding(s
);
13405 if (!fp_access_check(s
)) {
13409 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13410 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13412 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13414 tcg_temp_free_ptr(tcg_rd_ptr
);
13415 tcg_temp_free_ptr(tcg_rn_ptr
);
13418 /* Crypto three-reg SHA512
13419 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13420 * +-----------------------+------+---+---+-----+--------+------+------+
13421 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13422 * +-----------------------+------+---+---+-----+--------+------+------+
13424 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13426 int opcode
= extract32(insn
, 10, 2);
13427 int o
= extract32(insn
, 14, 1);
13428 int rm
= extract32(insn
, 16, 5);
13429 int rn
= extract32(insn
, 5, 5);
13430 int rd
= extract32(insn
, 0, 5);
13432 CryptoThreeOpFn
*genfn
;
13436 case 0: /* SHA512H */
13437 feature
= dc_isar_feature(aa64_sha512
, s
);
13438 genfn
= gen_helper_crypto_sha512h
;
13440 case 1: /* SHA512H2 */
13441 feature
= dc_isar_feature(aa64_sha512
, s
);
13442 genfn
= gen_helper_crypto_sha512h2
;
13444 case 2: /* SHA512SU1 */
13445 feature
= dc_isar_feature(aa64_sha512
, s
);
13446 genfn
= gen_helper_crypto_sha512su1
;
13449 feature
= dc_isar_feature(aa64_sha3
, s
);
13455 case 0: /* SM3PARTW1 */
13456 feature
= dc_isar_feature(aa64_sm3
, s
);
13457 genfn
= gen_helper_crypto_sm3partw1
;
13459 case 1: /* SM3PARTW2 */
13460 feature
= dc_isar_feature(aa64_sm3
, s
);
13461 genfn
= gen_helper_crypto_sm3partw2
;
13463 case 2: /* SM4EKEY */
13464 feature
= dc_isar_feature(aa64_sm4
, s
);
13465 genfn
= gen_helper_crypto_sm4ekey
;
13468 unallocated_encoding(s
);
13474 unallocated_encoding(s
);
13478 if (!fp_access_check(s
)) {
13483 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13485 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13486 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13487 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13489 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13491 tcg_temp_free_ptr(tcg_rd_ptr
);
13492 tcg_temp_free_ptr(tcg_rn_ptr
);
13493 tcg_temp_free_ptr(tcg_rm_ptr
);
13495 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13498 tcg_op1
= tcg_temp_new_i64();
13499 tcg_op2
= tcg_temp_new_i64();
13500 tcg_res
[0] = tcg_temp_new_i64();
13501 tcg_res
[1] = tcg_temp_new_i64();
13503 for (pass
= 0; pass
< 2; pass
++) {
13504 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13505 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13507 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13508 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13510 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13511 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13513 tcg_temp_free_i64(tcg_op1
);
13514 tcg_temp_free_i64(tcg_op2
);
13515 tcg_temp_free_i64(tcg_res
[0]);
13516 tcg_temp_free_i64(tcg_res
[1]);
13520 /* Crypto two-reg SHA512
13521 * 31 12 11 10 9 5 4 0
13522 * +-----------------------------------------+--------+------+------+
13523 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13524 * +-----------------------------------------+--------+------+------+
13526 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13528 int opcode
= extract32(insn
, 10, 2);
13529 int rn
= extract32(insn
, 5, 5);
13530 int rd
= extract32(insn
, 0, 5);
13531 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13533 CryptoTwoOpFn
*genfn
;
13536 case 0: /* SHA512SU0 */
13537 feature
= dc_isar_feature(aa64_sha512
, s
);
13538 genfn
= gen_helper_crypto_sha512su0
;
13541 feature
= dc_isar_feature(aa64_sm4
, s
);
13542 genfn
= gen_helper_crypto_sm4e
;
13545 unallocated_encoding(s
);
13550 unallocated_encoding(s
);
13554 if (!fp_access_check(s
)) {
13558 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13559 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13561 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13563 tcg_temp_free_ptr(tcg_rd_ptr
);
13564 tcg_temp_free_ptr(tcg_rn_ptr
);
13567 /* Crypto four-register
13568 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13569 * +-------------------+-----+------+---+------+------+------+
13570 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13571 * +-------------------+-----+------+---+------+------+------+
13573 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13575 int op0
= extract32(insn
, 21, 2);
13576 int rm
= extract32(insn
, 16, 5);
13577 int ra
= extract32(insn
, 10, 5);
13578 int rn
= extract32(insn
, 5, 5);
13579 int rd
= extract32(insn
, 0, 5);
13585 feature
= dc_isar_feature(aa64_sha3
, s
);
13587 case 2: /* SM3SS1 */
13588 feature
= dc_isar_feature(aa64_sm3
, s
);
13591 unallocated_encoding(s
);
13596 unallocated_encoding(s
);
13600 if (!fp_access_check(s
)) {
13605 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13608 tcg_op1
= tcg_temp_new_i64();
13609 tcg_op2
= tcg_temp_new_i64();
13610 tcg_op3
= tcg_temp_new_i64();
13611 tcg_res
[0] = tcg_temp_new_i64();
13612 tcg_res
[1] = tcg_temp_new_i64();
13614 for (pass
= 0; pass
< 2; pass
++) {
13615 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13616 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13617 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13621 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13624 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13626 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13628 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13629 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13631 tcg_temp_free_i64(tcg_op1
);
13632 tcg_temp_free_i64(tcg_op2
);
13633 tcg_temp_free_i64(tcg_op3
);
13634 tcg_temp_free_i64(tcg_res
[0]);
13635 tcg_temp_free_i64(tcg_res
[1]);
13637 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13639 tcg_op1
= tcg_temp_new_i32();
13640 tcg_op2
= tcg_temp_new_i32();
13641 tcg_op3
= tcg_temp_new_i32();
13642 tcg_res
= tcg_temp_new_i32();
13643 tcg_zero
= tcg_const_i32(0);
13645 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13646 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13647 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13649 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13650 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13651 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13652 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13654 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13655 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13656 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13657 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13659 tcg_temp_free_i32(tcg_op1
);
13660 tcg_temp_free_i32(tcg_op2
);
13661 tcg_temp_free_i32(tcg_op3
);
13662 tcg_temp_free_i32(tcg_res
);
13663 tcg_temp_free_i32(tcg_zero
);
13668 * 31 21 20 16 15 10 9 5 4 0
13669 * +-----------------------+------+--------+------+------+
13670 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13671 * +-----------------------+------+--------+------+------+
13673 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13675 int rm
= extract32(insn
, 16, 5);
13676 int imm6
= extract32(insn
, 10, 6);
13677 int rn
= extract32(insn
, 5, 5);
13678 int rd
= extract32(insn
, 0, 5);
13679 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13682 if (!dc_isar_feature(aa64_sha3
, s
)) {
13683 unallocated_encoding(s
);
13687 if (!fp_access_check(s
)) {
13691 tcg_op1
= tcg_temp_new_i64();
13692 tcg_op2
= tcg_temp_new_i64();
13693 tcg_res
[0] = tcg_temp_new_i64();
13694 tcg_res
[1] = tcg_temp_new_i64();
13696 for (pass
= 0; pass
< 2; pass
++) {
13697 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13698 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13700 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13701 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13703 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13704 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13706 tcg_temp_free_i64(tcg_op1
);
13707 tcg_temp_free_i64(tcg_op2
);
13708 tcg_temp_free_i64(tcg_res
[0]);
13709 tcg_temp_free_i64(tcg_res
[1]);
13712 /* Crypto three-reg imm2
13713 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13714 * +-----------------------+------+-----+------+--------+------+------+
13715 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13716 * +-----------------------+------+-----+------+--------+------+------+
13718 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13720 int opcode
= extract32(insn
, 10, 2);
13721 int imm2
= extract32(insn
, 12, 2);
13722 int rm
= extract32(insn
, 16, 5);
13723 int rn
= extract32(insn
, 5, 5);
13724 int rd
= extract32(insn
, 0, 5);
13725 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13726 TCGv_i32 tcg_imm2
, tcg_opcode
;
13728 if (!dc_isar_feature(aa64_sm3
, s
)) {
13729 unallocated_encoding(s
);
13733 if (!fp_access_check(s
)) {
13737 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13738 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13739 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13740 tcg_imm2
= tcg_const_i32(imm2
);
13741 tcg_opcode
= tcg_const_i32(opcode
);
13743 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13746 tcg_temp_free_ptr(tcg_rd_ptr
);
13747 tcg_temp_free_ptr(tcg_rn_ptr
);
13748 tcg_temp_free_ptr(tcg_rm_ptr
);
13749 tcg_temp_free_i32(tcg_imm2
);
13750 tcg_temp_free_i32(tcg_opcode
);
13753 /* C3.6 Data processing - SIMD, inc Crypto
13755 * As the decode gets a little complex we are using a table based
13756 * approach for this part of the decode.
13758 static const AArch64DecodeTable data_proc_simd
[] = {
13759 /* pattern , mask , fn */
13760 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13761 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13762 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13763 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13764 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13765 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13766 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13767 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13768 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13769 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13770 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13771 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13772 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13773 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13774 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13775 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13776 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13777 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13778 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13779 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13780 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13781 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13782 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13783 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13784 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13785 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13786 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13787 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13788 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13789 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13790 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13791 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13792 { 0x00000000, 0x00000000, NULL
}
13795 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13797 /* Note that this is called with all non-FP cases from
13798 * table C3-6 so it must UNDEF for entries not specifically
13799 * allocated to instructions in that table.
13801 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13805 unallocated_encoding(s
);
13809 /* C3.6 Data processing - SIMD and floating point */
13810 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13812 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13813 disas_data_proc_fp(s
, insn
);
13815 /* SIMD, including crypto */
13816 disas_data_proc_simd(s
, insn
);
13822 * @env: The cpu environment
13823 * @s: The DisasContext
13825 * Return true if the page is guarded.
13827 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13829 #ifdef CONFIG_USER_ONLY
13830 return false; /* FIXME */
13832 uint64_t addr
= s
->base
.pc_first
;
13833 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13834 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13835 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13838 * We test this immediately after reading an insn, which means
13839 * that any normal page must be in the TLB. The only exception
13840 * would be for executing from flash or device memory, which
13841 * does not retain the TLB entry.
13843 * FIXME: Assume false for those, for now. We could use
13844 * arm_cpu_get_phys_page_attrs_debug to re-read the page
13845 * table entry even for that case.
13847 return (tlb_hit(entry
->addr_code
, addr
) &&
13848 env
->iotlb
[mmu_idx
][index
].attrs
.target_tlb_bit0
);
13853 * btype_destination_ok:
13854 * @insn: The instruction at the branch destination
13855 * @bt: SCTLR_ELx.BT
13856 * @btype: PSTATE.BTYPE, and is non-zero
13858 * On a guarded page, there are a limited number of insns
13859 * that may be present at the branch target:
13860 * - branch target identifiers,
13861 * - paciasp, pacibsp,
13864 * Anything else causes a Branch Target Exception.
13866 * Return true if the branch is compatible, false to raise BTITRAP.
13868 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
13870 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
13872 switch (extract32(insn
, 5, 7)) {
13873 case 0b011001: /* PACIASP */
13874 case 0b011011: /* PACIBSP */
13876 * If SCTLR_ELx.BT, then PACI*SP are not compatible
13877 * with btype == 3. Otherwise all btype are ok.
13879 return !bt
|| btype
!= 3;
13880 case 0b100000: /* BTI */
13881 /* Not compatible with any btype. */
13883 case 0b100010: /* BTI c */
13884 /* Not compatible with btype == 3 */
13886 case 0b100100: /* BTI j */
13887 /* Not compatible with btype == 2 */
13889 case 0b100110: /* BTI jc */
13890 /* Compatible with any btype. */
13894 switch (insn
& 0xffe0001fu
) {
13895 case 0xd4200000u
: /* BRK */
13896 case 0xd4400000u
: /* HLT */
13897 /* Give priority to the breakpoint exception. */
13904 /* C3.1 A64 instruction index by encoding */
13905 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13909 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13913 s
->fp_access_checked
= false;
13915 if (dc_isar_feature(aa64_bti
, s
)) {
13916 if (s
->base
.num_insns
== 1) {
13918 * At the first insn of the TB, compute s->guarded_page.
13919 * We delayed computing this until successfully reading
13920 * the first insn of the TB, above. This (mostly) ensures
13921 * that the softmmu tlb entry has been populated, and the
13922 * page table GP bit is available.
13924 * Note that we need to compute this even if btype == 0,
13925 * because this value is used for BR instructions later
13926 * where ENV is not available.
13928 s
->guarded_page
= is_guarded_page(env
, s
);
13930 /* First insn can have btype set to non-zero. */
13931 tcg_debug_assert(s
->btype
>= 0);
13934 * Note that the Branch Target Exception has fairly high
13935 * priority -- below debugging exceptions but above most
13936 * everything else. This allows us to handle this now
13937 * instead of waiting until the insn is otherwise decoded.
13941 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
13942 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_btitrap(s
->btype
),
13943 default_exception_el(s
));
13947 /* Not the first insn: btype must be 0. */
13948 tcg_debug_assert(s
->btype
== 0);
13952 switch (extract32(insn
, 25, 4)) {
13953 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
13954 unallocated_encoding(s
);
13957 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
13958 unallocated_encoding(s
);
13961 case 0x8: case 0x9: /* Data processing - immediate */
13962 disas_data_proc_imm(s
, insn
);
13964 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13965 disas_b_exc_sys(s
, insn
);
13970 case 0xe: /* Loads and stores */
13971 disas_ldst(s
, insn
);
13974 case 0xd: /* Data processing - register */
13975 disas_data_proc_reg(s
, insn
);
13978 case 0xf: /* Data processing - SIMD and floating point */
13979 disas_data_proc_simd_fp(s
, insn
);
13982 assert(FALSE
); /* all 15 cases should be handled above */
13986 /* if we allocated any temporaries, free them here */
13990 * After execution of most insns, btype is reset to 0.
13991 * Note that we set btype == -1 when the insn sets btype.
13993 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
13998 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14001 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14002 CPUARMState
*env
= cpu
->env_ptr
;
14003 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
14004 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14005 int bound
, core_mmu_idx
;
14007 dc
->isar
= &arm_cpu
->isar
;
14008 dc
->pc
= dc
->base
.pc_first
;
14012 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14013 * there is no secure EL1, so we route exceptions to EL3.
14015 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14016 !arm_el_is_aa64(env
, 3);
14019 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14020 dc
->condexec_mask
= 0;
14021 dc
->condexec_cond
= 0;
14022 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14023 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14024 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14025 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14026 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14027 #if !defined(CONFIG_USER_ONLY)
14028 dc
->user
= (dc
->current_el
== 0);
14030 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14031 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14032 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14033 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14034 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14035 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14037 dc
->vec_stride
= 0;
14038 dc
->cp_regs
= arm_cpu
->cp_regs
;
14039 dc
->features
= env
->features
;
14041 /* Single step state. The code-generation logic here is:
14043 * generate code with no special handling for single-stepping (except
14044 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14045 * this happens anyway because those changes are all system register or
14047 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14048 * emit code for one insn
14049 * emit code to clear PSTATE.SS
14050 * emit code to generate software step exception for completed step
14051 * end TB (as usual for having generated an exception)
14052 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14053 * emit code to generate a software step exception
14056 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14057 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14058 dc
->is_ldex
= false;
14059 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
14061 /* Bound the number of insns to execute to those left on the page. */
14062 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14064 /* If architectural single step active, limit to 1. */
14065 if (dc
->ss_active
) {
14068 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14070 init_tmp_a64_array(dc
);
14073 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14077 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14079 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14081 tcg_gen_insn_start(dc
->pc
, 0, 0);
14082 dc
->insn_start
= tcg_last_op();
14085 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14086 const CPUBreakpoint
*bp
)
14088 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14090 if (bp
->flags
& BP_CPU
) {
14091 gen_a64_set_pc_im(dc
->pc
);
14092 gen_helper_check_breakpoints(cpu_env
);
14093 /* End the TB early; it likely won't be executed */
14094 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14096 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
14097 /* The address covered by the breakpoint must be
14098 included in [tb->pc, tb->pc + tb->size) in order
14099 to for it to be properly cleared -- thus we
14100 increment the PC here so that the logic setting
14101 tb->size below does the right thing. */
14103 dc
->base
.is_jmp
= DISAS_NORETURN
;
14109 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14111 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14112 CPUARMState
*env
= cpu
->env_ptr
;
14114 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14115 /* Singlestep state is Active-pending.
14116 * If we're in this state at the start of a TB then either
14117 * a) we just took an exception to an EL which is being debugged
14118 * and this is the first insn in the exception handler
14119 * b) debug exceptions were masked and we just unmasked them
14120 * without changing EL (eg by clearing PSTATE.D)
14121 * In either case we're going to take a swstep exception in the
14122 * "did not step an insn" case, and so the syndrome ISV and EX
14123 * bits should be zero.
14125 assert(dc
->base
.num_insns
== 1);
14126 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
14127 default_exception_el(dc
));
14128 dc
->base
.is_jmp
= DISAS_NORETURN
;
14130 disas_a64_insn(env
, dc
);
14133 dc
->base
.pc_next
= dc
->pc
;
14134 translator_loop_temp_check(&dc
->base
);
14137 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14139 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14141 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14142 /* Note that this means single stepping WFI doesn't halt the CPU.
14143 * For conditional branch insns this is harmless unreachable code as
14144 * gen_goto_tb() has already handled emitting the debug exception
14145 * (and thus a tb-jump is not possible when singlestepping).
14147 switch (dc
->base
.is_jmp
) {
14149 gen_a64_set_pc_im(dc
->pc
);
14153 if (dc
->base
.singlestep_enabled
) {
14154 gen_exception_internal(EXCP_DEBUG
);
14156 gen_step_complete_exception(dc
);
14159 case DISAS_NORETURN
:
14163 switch (dc
->base
.is_jmp
) {
14165 case DISAS_TOO_MANY
:
14166 gen_goto_tb(dc
, 1, dc
->pc
);
14170 gen_a64_set_pc_im(dc
->pc
);
14173 tcg_gen_exit_tb(NULL
, 0);
14176 tcg_gen_lookup_and_goto_ptr();
14178 case DISAS_NORETURN
:
14182 gen_a64_set_pc_im(dc
->pc
);
14183 gen_helper_wfe(cpu_env
);
14186 gen_a64_set_pc_im(dc
->pc
);
14187 gen_helper_yield(cpu_env
);
14191 /* This is a special case because we don't want to just halt the CPU
14192 * if trying to debug across a WFI.
14194 TCGv_i32 tmp
= tcg_const_i32(4);
14196 gen_a64_set_pc_im(dc
->pc
);
14197 gen_helper_wfi(cpu_env
, tmp
);
14198 tcg_temp_free_i32(tmp
);
14199 /* The helper doesn't necessarily throw an exception, but we
14200 * must go back to the main loop to check for interrupts anyway.
14202 tcg_gen_exit_tb(NULL
, 0);
14208 /* Functions above can change dc->pc, so re-align db->pc_next */
14209 dc
->base
.pc_next
= dc
->pc
;
14212 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14215 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14217 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14218 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14221 const TranslatorOps aarch64_translator_ops
= {
14222 .init_disas_context
= aarch64_tr_init_disas_context
,
14223 .tb_start
= aarch64_tr_tb_start
,
14224 .insn_start
= aarch64_tr_insn_start
,
14225 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14226 .translate_insn
= aarch64_tr_translate_insn
,
14227 .tb_stop
= aarch64_tr_tb_stop
,
14228 .disas_log
= aarch64_tr_disas_log
,