4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
155 fprintf_function cpu_fprintf
, int flags
)
157 ARMCPU
*cpu
= ARM_CPU(cs
);
158 CPUARMState
*env
= &cpu
->env
;
159 uint32_t psr
= pstate_read(env
);
161 int el
= arm_current_el(env
);
162 const char *ns_status
;
164 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
165 for (i
= 0; i
< 32; i
++) {
167 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
169 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
170 (i
+ 2) % 3 ? " " : "\n");
174 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
175 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
179 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
181 psr
& PSTATE_N
? 'N' : '-',
182 psr
& PSTATE_Z
? 'Z' : '-',
183 psr
& PSTATE_C
? 'C' : '-',
184 psr
& PSTATE_V
? 'V' : '-',
187 psr
& PSTATE_SP
? 'h' : 't');
189 if (cpu_isar_feature(aa64_bti
, cpu
)) {
190 cpu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
192 if (!(flags
& CPU_DUMP_FPU
)) {
193 cpu_fprintf(f
, "\n");
196 if (fp_exception_el(env
, el
) != 0) {
197 cpu_fprintf(f
, " FPU disabled\n");
200 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
201 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
203 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
204 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
206 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
208 if (i
== FFR_PRED_NUM
) {
209 cpu_fprintf(f
, "FFR=");
210 /* It's last, so end the line. */
213 cpu_fprintf(f
, "P%02d=", i
);
226 /* More than one quadword per predicate. */
231 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
233 if (j
* 4 + 4 <= zcr_len
+ 1) {
236 digits
= (zcr_len
% 4 + 1) * 4;
238 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
239 env
->vfp
.pregs
[i
].p
[j
],
240 j
? ":" : eol
? "\n" : " ");
244 for (i
= 0; i
< 32; i
++) {
246 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
247 i
, env
->vfp
.zregs
[i
].d
[1],
248 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
249 } else if (zcr_len
== 1) {
250 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
251 ":%016" PRIx64
":%016" PRIx64
"\n",
252 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
253 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
255 for (j
= zcr_len
; j
>= 0; j
--) {
256 bool odd
= (zcr_len
- j
) % 2 != 0;
258 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
261 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
263 cpu_fprintf(f
, " [%x]=", j
);
266 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
267 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
268 env
->vfp
.zregs
[i
].d
[j
* 2],
269 odd
|| j
== 0 ? "\n" : ":");
274 for (i
= 0; i
< 32; i
++) {
275 uint64_t *q
= aa64_vfp_qreg(env
, i
);
276 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
277 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
282 void gen_a64_set_pc_im(uint64_t val
)
284 tcg_gen_movi_i64(cpu_pc
, val
);
288 * Handle Top Byte Ignore (TBI) bits.
290 * If address tagging is enabled via the TCR TBI bits:
291 * + for EL2 and EL3 there is only one TBI bit, and if it is set
292 * then the address is zero-extended, clearing bits [63:56]
293 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
294 * and TBI1 controls addressses with bit 55 == 1.
295 * If the appropriate TBI bit is set for the address then
296 * the address is sign-extended from bit 55 into bits [63:56]
298 * Here We have concatenated TBI{1,0} into tbi.
300 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
301 TCGv_i64 src
, int tbi
)
304 /* Load unmodified address */
305 tcg_gen_mov_i64(dst
, src
);
306 } else if (s
->current_el
>= 2) {
307 /* FIXME: ARMv8.1-VHE S2 translation regime. */
308 /* Force tag byte to all zero */
309 tcg_gen_extract_i64(dst
, src
, 0, 56);
311 /* Sign-extend from bit 55. */
312 tcg_gen_sextract_i64(dst
, src
, 0, 56);
315 TCGv_i64 tcg_zero
= tcg_const_i64(0);
318 * The two TBI bits differ.
319 * If tbi0, then !tbi1: only use the extension if positive.
320 * if !tbi0, then tbi1: only use the extension if negative.
322 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
323 dst
, dst
, tcg_zero
, dst
, src
);
324 tcg_temp_free_i64(tcg_zero
);
329 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
332 * If address tagging is enabled for instructions via the TCR TBI bits,
333 * then loading an address into the PC will clear out any tag.
335 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
339 * Return a "clean" address for ADDR according to TBID.
340 * This is always a fresh temporary, as we need to be able to
341 * increment this independently of a dirty write-back address.
343 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
345 TCGv_i64 clean
= new_tmp_a64(s
);
346 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
350 typedef struct DisasCompare64
{
355 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
359 arm_test_cc(&c32
, cc
);
361 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
362 * properly. The NE/EQ comparisons are also fine with this choice. */
363 c64
->cond
= c32
.cond
;
364 c64
->value
= tcg_temp_new_i64();
365 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
370 static void a64_free_cc(DisasCompare64
*c64
)
372 tcg_temp_free_i64(c64
->value
);
375 static void gen_exception_internal(int excp
)
377 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
379 assert(excp_is_internal(excp
));
380 gen_helper_exception_internal(cpu_env
, tcg_excp
);
381 tcg_temp_free_i32(tcg_excp
);
384 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
386 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
387 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
388 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
390 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
392 tcg_temp_free_i32(tcg_el
);
393 tcg_temp_free_i32(tcg_syn
);
394 tcg_temp_free_i32(tcg_excp
);
397 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
399 gen_a64_set_pc_im(s
->pc
- offset
);
400 gen_exception_internal(excp
);
401 s
->base
.is_jmp
= DISAS_NORETURN
;
404 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
405 uint32_t syndrome
, uint32_t target_el
)
407 gen_a64_set_pc_im(s
->pc
- offset
);
408 gen_exception(excp
, syndrome
, target_el
);
409 s
->base
.is_jmp
= DISAS_NORETURN
;
412 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
417 gen_a64_set_pc_im(s
->pc
- offset
);
418 tcg_syn
= tcg_const_i32(syndrome
);
419 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
420 tcg_temp_free_i32(tcg_syn
);
421 s
->base
.is_jmp
= DISAS_NORETURN
;
424 static void gen_ss_advance(DisasContext
*s
)
426 /* If the singlestep state is Active-not-pending, advance to
431 gen_helper_clear_pstate_ss(cpu_env
);
435 static void gen_step_complete_exception(DisasContext
*s
)
437 /* We just completed step of an insn. Move from Active-not-pending
438 * to Active-pending, and then also take the swstep exception.
439 * This corresponds to making the (IMPDEF) choice to prioritize
440 * swstep exceptions over asynchronous exceptions taken to an exception
441 * level where debug is disabled. This choice has the advantage that
442 * we do not need to maintain internal state corresponding to the
443 * ISV/EX syndrome bits between completion of the step and generation
444 * of the exception, and our syndrome information is always correct.
447 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
448 default_exception_el(s
));
449 s
->base
.is_jmp
= DISAS_NORETURN
;
452 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
454 /* No direct tb linking with singlestep (either QEMU's or the ARM
455 * debug architecture kind) or deterministic io
457 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
458 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
462 #ifndef CONFIG_USER_ONLY
463 /* Only link tbs from inside the same guest page */
464 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
472 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
474 TranslationBlock
*tb
;
477 if (use_goto_tb(s
, n
, dest
)) {
479 gen_a64_set_pc_im(dest
);
480 tcg_gen_exit_tb(tb
, n
);
481 s
->base
.is_jmp
= DISAS_NORETURN
;
483 gen_a64_set_pc_im(dest
);
485 gen_step_complete_exception(s
);
486 } else if (s
->base
.singlestep_enabled
) {
487 gen_exception_internal(EXCP_DEBUG
);
489 tcg_gen_lookup_and_goto_ptr();
490 s
->base
.is_jmp
= DISAS_NORETURN
;
495 void unallocated_encoding(DisasContext
*s
)
497 /* Unallocated and reserved encodings are uncategorized */
498 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
499 default_exception_el(s
));
502 static void init_tmp_a64_array(DisasContext
*s
)
504 #ifdef CONFIG_DEBUG_TCG
505 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
507 s
->tmp_a64_count
= 0;
510 static void free_tmp_a64(DisasContext
*s
)
513 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
514 tcg_temp_free_i64(s
->tmp_a64
[i
]);
516 init_tmp_a64_array(s
);
519 TCGv_i64
new_tmp_a64(DisasContext
*s
)
521 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
522 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
525 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
527 TCGv_i64 t
= new_tmp_a64(s
);
528 tcg_gen_movi_i64(t
, 0);
533 * Register access functions
535 * These functions are used for directly accessing a register in where
536 * changes to the final register value are likely to be made. If you
537 * need to use a register for temporary calculation (e.g. index type
538 * operations) use the read_* form.
540 * B1.2.1 Register mappings
542 * In instruction register encoding 31 can refer to ZR (zero register) or
543 * the SP (stack pointer) depending on context. In QEMU's case we map SP
544 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
545 * This is the point of the _sp forms.
547 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
550 return new_tmp_a64_zero(s
);
556 /* register access for when 31 == SP */
557 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
562 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
563 * representing the register contents. This TCGv is an auto-freed
564 * temporary so it need not be explicitly freed, and may be modified.
566 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
568 TCGv_i64 v
= new_tmp_a64(s
);
571 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
573 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
576 tcg_gen_movi_i64(v
, 0);
581 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
583 TCGv_i64 v
= new_tmp_a64(s
);
585 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
587 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
592 /* Return the offset into CPUARMState of a slice (from
593 * the least significant end) of FP register Qn (ie
595 * (Note that this is not the same mapping as for A32; see cpu.h)
597 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
599 return vec_reg_offset(s
, regno
, 0, size
);
602 /* Offset of the high half of the 128 bit vector Qn */
603 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
605 return vec_reg_offset(s
, regno
, 1, MO_64
);
608 /* Convenience accessors for reading and writing single and double
609 * FP registers. Writing clears the upper parts of the associated
610 * 128 bit vector register, as required by the architecture.
611 * Note that unlike the GP register accessors, the values returned
612 * by the read functions must be manually freed.
614 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
616 TCGv_i64 v
= tcg_temp_new_i64();
618 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
622 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
624 TCGv_i32 v
= tcg_temp_new_i32();
626 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
630 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
632 TCGv_i32 v
= tcg_temp_new_i32();
634 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
638 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
639 * If SVE is not enabled, then there are only 128 bits in the vector.
641 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
643 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
644 unsigned vsz
= vec_full_reg_size(s
);
647 TCGv_i64 tcg_zero
= tcg_const_i64(0);
648 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
649 tcg_temp_free_i64(tcg_zero
);
652 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
656 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
658 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
660 tcg_gen_st_i64(v
, cpu_env
, ofs
);
661 clear_vec_high(s
, false, reg
);
664 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
666 TCGv_i64 tmp
= tcg_temp_new_i64();
668 tcg_gen_extu_i32_i64(tmp
, v
);
669 write_fp_dreg(s
, reg
, tmp
);
670 tcg_temp_free_i64(tmp
);
673 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
675 TCGv_ptr statusptr
= tcg_temp_new_ptr();
678 /* In A64 all instructions (both FP and Neon) use the FPCR; there
679 * is no equivalent of the A32 Neon "standard FPSCR value".
680 * However half-precision operations operate under a different
681 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
684 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
686 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
688 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
692 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
693 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
694 GVecGen2Fn
*gvec_fn
, int vece
)
696 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
697 is_q
? 16 : 8, vec_full_reg_size(s
));
700 /* Expand a 2-operand + immediate AdvSIMD vector operation using
701 * an expander function.
703 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
704 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
706 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
707 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
710 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
711 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
712 GVecGen3Fn
*gvec_fn
, int vece
)
714 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
715 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
718 /* Expand a 2-operand + immediate AdvSIMD vector operation using
721 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
722 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
724 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
725 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
728 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
729 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
730 int rn
, int rm
, const GVecGen3
*gvec_op
)
732 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
733 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
734 vec_full_reg_size(s
), gvec_op
);
737 /* Expand a 3-operand operation using an out-of-line helper. */
738 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
739 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
741 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
742 vec_full_reg_offset(s
, rn
),
743 vec_full_reg_offset(s
, rm
),
744 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
747 /* Expand a 3-operand + env pointer operation using
748 * an out-of-line helper.
750 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
751 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
753 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
754 vec_full_reg_offset(s
, rn
),
755 vec_full_reg_offset(s
, rm
), cpu_env
,
756 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
759 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
760 * an out-of-line helper.
762 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
763 int rm
, bool is_fp16
, int data
,
764 gen_helper_gvec_3_ptr
*fn
)
766 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
767 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
768 vec_full_reg_offset(s
, rn
),
769 vec_full_reg_offset(s
, rm
), fpst
,
770 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
771 tcg_temp_free_ptr(fpst
);
774 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
775 * than the 32 bit equivalent.
777 static inline void gen_set_NZ64(TCGv_i64 result
)
779 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
780 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
783 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
784 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
787 gen_set_NZ64(result
);
789 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
790 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
792 tcg_gen_movi_i32(cpu_CF
, 0);
793 tcg_gen_movi_i32(cpu_VF
, 0);
796 /* dest = T0 + T1; compute C, N, V and Z flags */
797 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
800 TCGv_i64 result
, flag
, tmp
;
801 result
= tcg_temp_new_i64();
802 flag
= tcg_temp_new_i64();
803 tmp
= tcg_temp_new_i64();
805 tcg_gen_movi_i64(tmp
, 0);
806 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
808 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
810 gen_set_NZ64(result
);
812 tcg_gen_xor_i64(flag
, result
, t0
);
813 tcg_gen_xor_i64(tmp
, t0
, t1
);
814 tcg_gen_andc_i64(flag
, flag
, tmp
);
815 tcg_temp_free_i64(tmp
);
816 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
818 tcg_gen_mov_i64(dest
, result
);
819 tcg_temp_free_i64(result
);
820 tcg_temp_free_i64(flag
);
822 /* 32 bit arithmetic */
823 TCGv_i32 t0_32
= tcg_temp_new_i32();
824 TCGv_i32 t1_32
= tcg_temp_new_i32();
825 TCGv_i32 tmp
= tcg_temp_new_i32();
827 tcg_gen_movi_i32(tmp
, 0);
828 tcg_gen_extrl_i64_i32(t0_32
, t0
);
829 tcg_gen_extrl_i64_i32(t1_32
, t1
);
830 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
831 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
832 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
833 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
834 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
835 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
837 tcg_temp_free_i32(tmp
);
838 tcg_temp_free_i32(t0_32
);
839 tcg_temp_free_i32(t1_32
);
843 /* dest = T0 - T1; compute C, N, V and Z flags */
844 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
847 /* 64 bit arithmetic */
848 TCGv_i64 result
, flag
, tmp
;
850 result
= tcg_temp_new_i64();
851 flag
= tcg_temp_new_i64();
852 tcg_gen_sub_i64(result
, t0
, t1
);
854 gen_set_NZ64(result
);
856 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
857 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
859 tcg_gen_xor_i64(flag
, result
, t0
);
860 tmp
= tcg_temp_new_i64();
861 tcg_gen_xor_i64(tmp
, t0
, t1
);
862 tcg_gen_and_i64(flag
, flag
, tmp
);
863 tcg_temp_free_i64(tmp
);
864 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
865 tcg_gen_mov_i64(dest
, result
);
866 tcg_temp_free_i64(flag
);
867 tcg_temp_free_i64(result
);
869 /* 32 bit arithmetic */
870 TCGv_i32 t0_32
= tcg_temp_new_i32();
871 TCGv_i32 t1_32
= tcg_temp_new_i32();
874 tcg_gen_extrl_i64_i32(t0_32
, t0
);
875 tcg_gen_extrl_i64_i32(t1_32
, t1
);
876 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
877 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
878 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
879 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
880 tmp
= tcg_temp_new_i32();
881 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
882 tcg_temp_free_i32(t0_32
);
883 tcg_temp_free_i32(t1_32
);
884 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
885 tcg_temp_free_i32(tmp
);
886 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
890 /* dest = T0 + T1 + CF; do not compute flags. */
891 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
893 TCGv_i64 flag
= tcg_temp_new_i64();
894 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
895 tcg_gen_add_i64(dest
, t0
, t1
);
896 tcg_gen_add_i64(dest
, dest
, flag
);
897 tcg_temp_free_i64(flag
);
900 tcg_gen_ext32u_i64(dest
, dest
);
904 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
905 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
908 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
909 result
= tcg_temp_new_i64();
910 cf_64
= tcg_temp_new_i64();
911 vf_64
= tcg_temp_new_i64();
912 tmp
= tcg_const_i64(0);
914 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
915 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
916 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
917 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
918 gen_set_NZ64(result
);
920 tcg_gen_xor_i64(vf_64
, result
, t0
);
921 tcg_gen_xor_i64(tmp
, t0
, t1
);
922 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
923 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
925 tcg_gen_mov_i64(dest
, result
);
927 tcg_temp_free_i64(tmp
);
928 tcg_temp_free_i64(vf_64
);
929 tcg_temp_free_i64(cf_64
);
930 tcg_temp_free_i64(result
);
932 TCGv_i32 t0_32
, t1_32
, tmp
;
933 t0_32
= tcg_temp_new_i32();
934 t1_32
= tcg_temp_new_i32();
935 tmp
= tcg_const_i32(0);
937 tcg_gen_extrl_i64_i32(t0_32
, t0
);
938 tcg_gen_extrl_i64_i32(t1_32
, t1
);
939 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
940 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
942 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
943 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
944 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
945 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
946 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
948 tcg_temp_free_i32(tmp
);
949 tcg_temp_free_i32(t1_32
);
950 tcg_temp_free_i32(t0_32
);
955 * Load/Store generators
959 * Store from GPR register to memory.
961 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
962 TCGv_i64 tcg_addr
, int size
, int memidx
,
964 unsigned int iss_srt
,
965 bool iss_sf
, bool iss_ar
)
968 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
973 syn
= syn_data_abort_with_iss(0,
979 0, 0, 0, 0, 0, false);
980 disas_set_insn_syndrome(s
, syn
);
984 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
985 TCGv_i64 tcg_addr
, int size
,
987 unsigned int iss_srt
,
988 bool iss_sf
, bool iss_ar
)
990 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
991 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
995 * Load from memory to GPR register
997 static void do_gpr_ld_memidx(DisasContext
*s
,
998 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
999 int size
, bool is_signed
,
1000 bool extend
, int memidx
,
1001 bool iss_valid
, unsigned int iss_srt
,
1002 bool iss_sf
, bool iss_ar
)
1004 TCGMemOp memop
= s
->be_data
+ size
;
1006 g_assert(size
<= 3);
1012 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
1014 if (extend
&& is_signed
) {
1016 tcg_gen_ext32u_i64(dest
, dest
);
1022 syn
= syn_data_abort_with_iss(0,
1028 0, 0, 0, 0, 0, false);
1029 disas_set_insn_syndrome(s
, syn
);
1033 static void do_gpr_ld(DisasContext
*s
,
1034 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1035 int size
, bool is_signed
, bool extend
,
1036 bool iss_valid
, unsigned int iss_srt
,
1037 bool iss_sf
, bool iss_ar
)
1039 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1041 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1045 * Store from FP register to memory
1047 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1049 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1050 TCGv_i64 tmp
= tcg_temp_new_i64();
1051 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1053 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1056 bool be
= s
->be_data
== MO_BE
;
1057 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1059 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1060 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1062 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1063 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1065 tcg_temp_free_i64(tcg_hiaddr
);
1068 tcg_temp_free_i64(tmp
);
1072 * Load from memory to FP register
1074 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1076 /* This always zero-extends and writes to a full 128 bit wide vector */
1077 TCGv_i64 tmplo
= tcg_temp_new_i64();
1081 TCGMemOp memop
= s
->be_data
+ size
;
1082 tmphi
= tcg_const_i64(0);
1083 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1085 bool be
= s
->be_data
== MO_BE
;
1086 TCGv_i64 tcg_hiaddr
;
1088 tmphi
= tcg_temp_new_i64();
1089 tcg_hiaddr
= tcg_temp_new_i64();
1091 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1092 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1094 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1096 tcg_temp_free_i64(tcg_hiaddr
);
1099 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1100 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1102 tcg_temp_free_i64(tmplo
);
1103 tcg_temp_free_i64(tmphi
);
1105 clear_vec_high(s
, true, destidx
);
1109 * Vector load/store helpers.
1111 * The principal difference between this and a FP load is that we don't
1112 * zero extend as we are filling a partial chunk of the vector register.
1113 * These functions don't support 128 bit loads/stores, which would be
1114 * normal load/store operations.
1116 * The _i32 versions are useful when operating on 32 bit quantities
1117 * (eg for floating point single or using Neon helper functions).
1120 /* Get value of an element within a vector register */
1121 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1122 int element
, TCGMemOp memop
)
1124 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1127 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1130 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1133 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1136 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1139 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1142 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1146 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1149 g_assert_not_reached();
1153 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1154 int element
, TCGMemOp memop
)
1156 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1159 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1162 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1165 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1168 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1172 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1175 g_assert_not_reached();
1179 /* Set value of an element within a vector register */
1180 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1181 int element
, TCGMemOp memop
)
1183 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1186 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1189 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1192 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1195 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1198 g_assert_not_reached();
1202 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1203 int destidx
, int element
, TCGMemOp memop
)
1205 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1208 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1211 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1214 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1217 g_assert_not_reached();
1221 /* Store from vector register to memory */
1222 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1223 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1225 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1227 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1228 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1230 tcg_temp_free_i64(tcg_tmp
);
1233 /* Load from memory to vector register */
1234 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1235 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1237 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1239 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1240 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1242 tcg_temp_free_i64(tcg_tmp
);
1245 /* Check that FP/Neon access is enabled. If it is, return
1246 * true. If not, emit code to generate an appropriate exception,
1247 * and return false; the caller should not emit any code for
1248 * the instruction. Note that this check must happen after all
1249 * unallocated-encoding checks (otherwise the syndrome information
1250 * for the resulting exception will be incorrect).
1252 static inline bool fp_access_check(DisasContext
*s
)
1254 assert(!s
->fp_access_checked
);
1255 s
->fp_access_checked
= true;
1257 if (!s
->fp_excp_el
) {
1261 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1266 /* Check that SVE access is enabled. If it is, return true.
1267 * If not, emit code to generate an appropriate exception and return false.
1269 bool sve_access_check(DisasContext
*s
)
1271 if (s
->sve_excp_el
) {
1272 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1276 return fp_access_check(s
);
1280 * This utility function is for doing register extension with an
1281 * optional shift. You will likely want to pass a temporary for the
1282 * destination register. See DecodeRegExtend() in the ARM ARM.
1284 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1285 int option
, unsigned int shift
)
1287 int extsize
= extract32(option
, 0, 2);
1288 bool is_signed
= extract32(option
, 2, 1);
1293 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1296 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1299 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1302 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1308 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1311 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1314 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1317 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1323 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1327 static inline void gen_check_sp_alignment(DisasContext
*s
)
1329 /* The AArch64 architecture mandates that (if enabled via PSTATE
1330 * or SCTLR bits) there is a check that SP is 16-aligned on every
1331 * SP-relative load or store (with an exception generated if it is not).
1332 * In line with general QEMU practice regarding misaligned accesses,
1333 * we omit these checks for the sake of guest program performance.
1334 * This function is provided as a hook so we can more easily add these
1335 * checks in future (possibly as a "favour catching guest program bugs
1336 * over speed" user selectable option).
1341 * This provides a simple table based table lookup decoder. It is
1342 * intended to be used when the relevant bits for decode are too
1343 * awkwardly placed and switch/if based logic would be confusing and
1344 * deeply nested. Since it's a linear search through the table, tables
1345 * should be kept small.
1347 * It returns the first handler where insn & mask == pattern, or
1348 * NULL if there is no match.
1349 * The table is terminated by an empty mask (i.e. 0)
1351 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1354 const AArch64DecodeTable
*tptr
= table
;
1356 while (tptr
->mask
) {
1357 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1358 return tptr
->disas_fn
;
1366 * The instruction disassembly implemented here matches
1367 * the instruction encoding classifications in chapter C4
1368 * of the ARM Architecture Reference Manual (DDI0487B_a);
1369 * classification names and decode diagrams here should generally
1370 * match up with those in the manual.
1373 /* Unconditional branch (immediate)
1375 * +----+-----------+-------------------------------------+
1376 * | op | 0 0 1 0 1 | imm26 |
1377 * +----+-----------+-------------------------------------+
1379 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1381 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1383 if (insn
& (1U << 31)) {
1384 /* BL Branch with link */
1385 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1388 /* B Branch / BL Branch with link */
1390 gen_goto_tb(s
, 0, addr
);
1393 /* Compare and branch (immediate)
1394 * 31 30 25 24 23 5 4 0
1395 * +----+-------------+----+---------------------+--------+
1396 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1397 * +----+-------------+----+---------------------+--------+
1399 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1401 unsigned int sf
, op
, rt
;
1403 TCGLabel
*label_match
;
1406 sf
= extract32(insn
, 31, 1);
1407 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1408 rt
= extract32(insn
, 0, 5);
1409 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1411 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1412 label_match
= gen_new_label();
1415 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1416 tcg_cmp
, 0, label_match
);
1418 gen_goto_tb(s
, 0, s
->pc
);
1419 gen_set_label(label_match
);
1420 gen_goto_tb(s
, 1, addr
);
1423 /* Test and branch (immediate)
1424 * 31 30 25 24 23 19 18 5 4 0
1425 * +----+-------------+----+-------+-------------+------+
1426 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1427 * +----+-------------+----+-------+-------------+------+
1429 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1431 unsigned int bit_pos
, op
, rt
;
1433 TCGLabel
*label_match
;
1436 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1437 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1438 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1439 rt
= extract32(insn
, 0, 5);
1441 tcg_cmp
= tcg_temp_new_i64();
1442 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1443 label_match
= gen_new_label();
1446 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1447 tcg_cmp
, 0, label_match
);
1448 tcg_temp_free_i64(tcg_cmp
);
1449 gen_goto_tb(s
, 0, s
->pc
);
1450 gen_set_label(label_match
);
1451 gen_goto_tb(s
, 1, addr
);
1454 /* Conditional branch (immediate)
1455 * 31 25 24 23 5 4 3 0
1456 * +---------------+----+---------------------+----+------+
1457 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1458 * +---------------+----+---------------------+----+------+
1460 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1465 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1466 unallocated_encoding(s
);
1469 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1470 cond
= extract32(insn
, 0, 4);
1474 /* genuinely conditional branches */
1475 TCGLabel
*label_match
= gen_new_label();
1476 arm_gen_test_cc(cond
, label_match
);
1477 gen_goto_tb(s
, 0, s
->pc
);
1478 gen_set_label(label_match
);
1479 gen_goto_tb(s
, 1, addr
);
1481 /* 0xe and 0xf are both "always" conditions */
1482 gen_goto_tb(s
, 0, addr
);
1486 /* HINT instruction group, including various allocated HINTs */
1487 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1488 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1490 unsigned int selector
= crm
<< 3 | op2
;
1493 unallocated_encoding(s
);
1498 case 0b00000: /* NOP */
1500 case 0b00011: /* WFI */
1501 s
->base
.is_jmp
= DISAS_WFI
;
1503 case 0b00001: /* YIELD */
1504 /* When running in MTTCG we don't generate jumps to the yield and
1505 * WFE helpers as it won't affect the scheduling of other vCPUs.
1506 * If we wanted to more completely model WFE/SEV so we don't busy
1507 * spin unnecessarily we would need to do something more involved.
1509 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1510 s
->base
.is_jmp
= DISAS_YIELD
;
1513 case 0b00010: /* WFE */
1514 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1515 s
->base
.is_jmp
= DISAS_WFE
;
1518 case 0b00100: /* SEV */
1519 case 0b00101: /* SEVL */
1520 /* we treat all as NOP at least for now */
1522 case 0b00111: /* XPACLRI */
1523 if (s
->pauth_active
) {
1524 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1527 case 0b01000: /* PACIA1716 */
1528 if (s
->pauth_active
) {
1529 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1532 case 0b01010: /* PACIB1716 */
1533 if (s
->pauth_active
) {
1534 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1537 case 0b01100: /* AUTIA1716 */
1538 if (s
->pauth_active
) {
1539 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1542 case 0b01110: /* AUTIB1716 */
1543 if (s
->pauth_active
) {
1544 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1547 case 0b11000: /* PACIAZ */
1548 if (s
->pauth_active
) {
1549 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1550 new_tmp_a64_zero(s
));
1553 case 0b11001: /* PACIASP */
1554 if (s
->pauth_active
) {
1555 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1558 case 0b11010: /* PACIBZ */
1559 if (s
->pauth_active
) {
1560 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1561 new_tmp_a64_zero(s
));
1564 case 0b11011: /* PACIBSP */
1565 if (s
->pauth_active
) {
1566 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1569 case 0b11100: /* AUTIAZ */
1570 if (s
->pauth_active
) {
1571 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1572 new_tmp_a64_zero(s
));
1575 case 0b11101: /* AUTIASP */
1576 if (s
->pauth_active
) {
1577 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1580 case 0b11110: /* AUTIBZ */
1581 if (s
->pauth_active
) {
1582 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1583 new_tmp_a64_zero(s
));
1586 case 0b11111: /* AUTIBSP */
1587 if (s
->pauth_active
) {
1588 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1592 /* default specified as NOP equivalent */
1597 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1599 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1602 /* CLREX, DSB, DMB, ISB */
1603 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1604 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1609 unallocated_encoding(s
);
1620 case 1: /* MBReqTypes_Reads */
1621 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1623 case 2: /* MBReqTypes_Writes */
1624 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1626 default: /* MBReqTypes_All */
1627 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1633 /* We need to break the TB after this insn to execute
1634 * a self-modified code correctly and also to take
1635 * any pending interrupts immediately.
1638 gen_goto_tb(s
, 0, s
->pc
);
1642 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1643 goto do_unallocated
;
1646 * TODO: There is no speculation barrier opcode for TCG;
1647 * MB and end the TB instead.
1649 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1650 gen_goto_tb(s
, 0, s
->pc
);
1655 unallocated_encoding(s
);
1660 /* MSR (immediate) - move immediate to processor state field */
1661 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1662 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1664 int op
= op1
<< 3 | op2
;
1666 case 0x05: /* SPSel */
1667 if (s
->current_el
== 0) {
1668 unallocated_encoding(s
);
1672 case 0x1e: /* DAIFSet */
1673 case 0x1f: /* DAIFClear */
1675 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1676 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1677 gen_a64_set_pc_im(s
->pc
- 4);
1678 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1679 tcg_temp_free_i32(tcg_imm
);
1680 tcg_temp_free_i32(tcg_op
);
1681 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1682 gen_a64_set_pc_im(s
->pc
);
1683 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1687 unallocated_encoding(s
);
1692 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1694 TCGv_i32 tmp
= tcg_temp_new_i32();
1695 TCGv_i32 nzcv
= tcg_temp_new_i32();
1697 /* build bit 31, N */
1698 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1699 /* build bit 30, Z */
1700 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1701 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1702 /* build bit 29, C */
1703 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1704 /* build bit 28, V */
1705 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1706 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1707 /* generate result */
1708 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1710 tcg_temp_free_i32(nzcv
);
1711 tcg_temp_free_i32(tmp
);
1714 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1717 TCGv_i32 nzcv
= tcg_temp_new_i32();
1719 /* take NZCV from R[t] */
1720 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1723 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1725 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1726 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1728 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1729 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1731 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1732 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1733 tcg_temp_free_i32(nzcv
);
1736 /* MRS - move from system register
1737 * MSR (register) - move to system register
1740 * These are all essentially the same insn in 'read' and 'write'
1741 * versions, with varying op0 fields.
1743 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1744 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1745 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1747 const ARMCPRegInfo
*ri
;
1750 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1751 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1752 crn
, crm
, op0
, op1
, op2
));
1755 /* Unknown register; this might be a guest error or a QEMU
1756 * unimplemented feature.
1758 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1759 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1760 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1761 unallocated_encoding(s
);
1765 /* Check access permissions */
1766 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1767 unallocated_encoding(s
);
1772 /* Emit code to perform further access permissions checks at
1773 * runtime; this may result in an exception.
1776 TCGv_i32 tcg_syn
, tcg_isread
;
1779 gen_a64_set_pc_im(s
->pc
- 4);
1780 tmpptr
= tcg_const_ptr(ri
);
1781 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1782 tcg_syn
= tcg_const_i32(syndrome
);
1783 tcg_isread
= tcg_const_i32(isread
);
1784 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1785 tcg_temp_free_ptr(tmpptr
);
1786 tcg_temp_free_i32(tcg_syn
);
1787 tcg_temp_free_i32(tcg_isread
);
1790 /* Handle special cases first */
1791 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1795 tcg_rt
= cpu_reg(s
, rt
);
1797 gen_get_nzcv(tcg_rt
);
1799 gen_set_nzcv(tcg_rt
);
1802 case ARM_CP_CURRENTEL
:
1803 /* Reads as current EL value from pstate, which is
1804 * guaranteed to be constant by the tb flags.
1806 tcg_rt
= cpu_reg(s
, rt
);
1807 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1810 /* Writes clear the aligned block of memory which rt points into. */
1811 tcg_rt
= cpu_reg(s
, rt
);
1812 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1817 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1819 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1823 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1827 tcg_rt
= cpu_reg(s
, rt
);
1830 if (ri
->type
& ARM_CP_CONST
) {
1831 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1832 } else if (ri
->readfn
) {
1834 tmpptr
= tcg_const_ptr(ri
);
1835 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1836 tcg_temp_free_ptr(tmpptr
);
1838 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1841 if (ri
->type
& ARM_CP_CONST
) {
1842 /* If not forbidden by access permissions, treat as WI */
1844 } else if (ri
->writefn
) {
1846 tmpptr
= tcg_const_ptr(ri
);
1847 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1848 tcg_temp_free_ptr(tmpptr
);
1850 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1854 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1855 /* I/O operations must end the TB here (whether read or write) */
1857 s
->base
.is_jmp
= DISAS_UPDATE
;
1858 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1859 /* We default to ending the TB on a coprocessor register write,
1860 * but allow this to be suppressed by the register definition
1861 * (usually only necessary to work around guest bugs).
1863 s
->base
.is_jmp
= DISAS_UPDATE
;
1868 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1869 * +---------------------+---+-----+-----+-------+-------+-----+------+
1870 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1871 * +---------------------+---+-----+-----+-------+-------+-----+------+
1873 static void disas_system(DisasContext
*s
, uint32_t insn
)
1875 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1876 l
= extract32(insn
, 21, 1);
1877 op0
= extract32(insn
, 19, 2);
1878 op1
= extract32(insn
, 16, 3);
1879 crn
= extract32(insn
, 12, 4);
1880 crm
= extract32(insn
, 8, 4);
1881 op2
= extract32(insn
, 5, 3);
1882 rt
= extract32(insn
, 0, 5);
1885 if (l
|| rt
!= 31) {
1886 unallocated_encoding(s
);
1890 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1891 handle_hint(s
, insn
, op1
, op2
, crm
);
1893 case 3: /* CLREX, DSB, DMB, ISB */
1894 handle_sync(s
, insn
, op1
, op2
, crm
);
1896 case 4: /* MSR (immediate) */
1897 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1900 unallocated_encoding(s
);
1905 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1908 /* Exception generation
1910 * 31 24 23 21 20 5 4 2 1 0
1911 * +-----------------+-----+------------------------+-----+----+
1912 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1913 * +-----------------------+------------------------+----------+
1915 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1917 int opc
= extract32(insn
, 21, 3);
1918 int op2_ll
= extract32(insn
, 0, 5);
1919 int imm16
= extract32(insn
, 5, 16);
1924 /* For SVC, HVC and SMC we advance the single-step state
1925 * machine before taking the exception. This is architecturally
1926 * mandated, to ensure that single-stepping a system call
1927 * instruction works properly.
1932 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1933 default_exception_el(s
));
1936 if (s
->current_el
== 0) {
1937 unallocated_encoding(s
);
1940 /* The pre HVC helper handles cases when HVC gets trapped
1941 * as an undefined insn by runtime configuration.
1943 gen_a64_set_pc_im(s
->pc
- 4);
1944 gen_helper_pre_hvc(cpu_env
);
1946 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1949 if (s
->current_el
== 0) {
1950 unallocated_encoding(s
);
1953 gen_a64_set_pc_im(s
->pc
- 4);
1954 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1955 gen_helper_pre_smc(cpu_env
, tmp
);
1956 tcg_temp_free_i32(tmp
);
1958 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1961 unallocated_encoding(s
);
1967 unallocated_encoding(s
);
1971 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1975 unallocated_encoding(s
);
1978 /* HLT. This has two purposes.
1979 * Architecturally, it is an external halting debug instruction.
1980 * Since QEMU doesn't implement external debug, we treat this as
1981 * it is required for halting debug disabled: it will UNDEF.
1982 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1984 if (semihosting_enabled() && imm16
== 0xf000) {
1985 #ifndef CONFIG_USER_ONLY
1986 /* In system mode, don't allow userspace access to semihosting,
1987 * to provide some semblance of security (and for consistency
1988 * with our 32-bit semihosting).
1990 if (s
->current_el
== 0) {
1991 unsupported_encoding(s
, insn
);
1995 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1997 unsupported_encoding(s
, insn
);
2001 if (op2_ll
< 1 || op2_ll
> 3) {
2002 unallocated_encoding(s
);
2005 /* DCPS1, DCPS2, DCPS3 */
2006 unsupported_encoding(s
, insn
);
2009 unallocated_encoding(s
);
2014 /* Unconditional branch (register)
2015 * 31 25 24 21 20 16 15 10 9 5 4 0
2016 * +---------------+-------+-------+-------+------+-------+
2017 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2018 * +---------------+-------+-------+-------+------+-------+
2020 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2022 unsigned int opc
, op2
, op3
, rn
, op4
;
2023 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2027 opc
= extract32(insn
, 21, 4);
2028 op2
= extract32(insn
, 16, 5);
2029 op3
= extract32(insn
, 10, 6);
2030 rn
= extract32(insn
, 5, 5);
2031 op4
= extract32(insn
, 0, 5);
2034 goto do_unallocated
;
2046 goto do_unallocated
;
2048 dst
= cpu_reg(s
, rn
);
2053 if (!dc_isar_feature(aa64_pauth
, s
)) {
2054 goto do_unallocated
;
2058 if (rn
!= 0x1f || op4
!= 0x1f) {
2059 goto do_unallocated
;
2062 modifier
= cpu_X
[31];
2064 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2066 goto do_unallocated
;
2068 modifier
= new_tmp_a64_zero(s
);
2070 if (s
->pauth_active
) {
2071 dst
= new_tmp_a64(s
);
2073 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2075 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2078 dst
= cpu_reg(s
, rn
);
2083 goto do_unallocated
;
2085 gen_a64_set_pc(s
, dst
);
2086 /* BLR also needs to load return address */
2088 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2094 if (!dc_isar_feature(aa64_pauth
, s
)) {
2095 goto do_unallocated
;
2097 if ((op3
& ~1) != 2) {
2098 goto do_unallocated
;
2100 btype_mod
= opc
& 1;
2101 if (s
->pauth_active
) {
2102 dst
= new_tmp_a64(s
);
2103 modifier
= cpu_reg_sp(s
, op4
);
2105 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2107 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2110 dst
= cpu_reg(s
, rn
);
2112 gen_a64_set_pc(s
, dst
);
2113 /* BLRAA also needs to load return address */
2115 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2120 if (s
->current_el
== 0) {
2121 goto do_unallocated
;
2126 goto do_unallocated
;
2128 dst
= tcg_temp_new_i64();
2129 tcg_gen_ld_i64(dst
, cpu_env
,
2130 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2133 case 2: /* ERETAA */
2134 case 3: /* ERETAB */
2135 if (!dc_isar_feature(aa64_pauth
, s
)) {
2136 goto do_unallocated
;
2138 if (rn
!= 0x1f || op4
!= 0x1f) {
2139 goto do_unallocated
;
2141 dst
= tcg_temp_new_i64();
2142 tcg_gen_ld_i64(dst
, cpu_env
,
2143 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2144 if (s
->pauth_active
) {
2145 modifier
= cpu_X
[31];
2147 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2149 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2155 goto do_unallocated
;
2157 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2161 gen_helper_exception_return(cpu_env
, dst
);
2162 tcg_temp_free_i64(dst
);
2163 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2166 /* Must exit loop to check un-masked IRQs */
2167 s
->base
.is_jmp
= DISAS_EXIT
;
2171 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2172 goto do_unallocated
;
2174 unsupported_encoding(s
, insn
);
2180 unallocated_encoding(s
);
2184 switch (btype_mod
) {
2186 if (dc_isar_feature(aa64_bti
, s
)) {
2187 /* BR to {x16,x17} or !guard -> 1, else 3. */
2188 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2193 if (dc_isar_feature(aa64_bti
, s
)) {
2194 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2199 default: /* RET or none of the above. */
2200 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2204 s
->base
.is_jmp
= DISAS_JUMP
;
2207 /* Branches, exception generating and system instructions */
2208 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2210 switch (extract32(insn
, 25, 7)) {
2211 case 0x0a: case 0x0b:
2212 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2213 disas_uncond_b_imm(s
, insn
);
2215 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2216 disas_comp_b_imm(s
, insn
);
2218 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2219 disas_test_b_imm(s
, insn
);
2221 case 0x2a: /* Conditional branch (immediate) */
2222 disas_cond_b_imm(s
, insn
);
2224 case 0x6a: /* Exception generation / System */
2225 if (insn
& (1 << 24)) {
2226 if (extract32(insn
, 22, 2) == 0) {
2227 disas_system(s
, insn
);
2229 unallocated_encoding(s
);
2235 case 0x6b: /* Unconditional branch (register) */
2236 disas_uncond_b_reg(s
, insn
);
2239 unallocated_encoding(s
);
2245 * Load/Store exclusive instructions are implemented by remembering
2246 * the value/address loaded, and seeing if these are the same
2247 * when the store is performed. This is not actually the architecturally
2248 * mandated semantics, but it works for typical guest code sequences
2249 * and avoids having to monitor regular stores.
2251 * The store exclusive uses the atomic cmpxchg primitives to avoid
2252 * races in multi-threaded linux-user and when MTTCG softmmu is
2255 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2256 TCGv_i64 addr
, int size
, bool is_pair
)
2258 int idx
= get_mem_index(s
);
2259 TCGMemOp memop
= s
->be_data
;
2261 g_assert(size
<= 3);
2263 g_assert(size
>= 2);
2265 /* The pair must be single-copy atomic for the doubleword. */
2266 memop
|= MO_64
| MO_ALIGN
;
2267 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2268 if (s
->be_data
== MO_LE
) {
2269 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2270 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2272 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2273 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2276 /* The pair must be single-copy atomic for *each* doubleword, not
2277 the entire quadword, however it must be quadword aligned. */
2279 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2280 memop
| MO_ALIGN_16
);
2282 TCGv_i64 addr2
= tcg_temp_new_i64();
2283 tcg_gen_addi_i64(addr2
, addr
, 8);
2284 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2285 tcg_temp_free_i64(addr2
);
2287 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2288 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2291 memop
|= size
| MO_ALIGN
;
2292 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2293 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2295 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2298 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2299 TCGv_i64 addr
, int size
, int is_pair
)
2301 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2302 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2305 * [addr + datasize] = {Rt2};
2311 * env->exclusive_addr = -1;
2313 TCGLabel
*fail_label
= gen_new_label();
2314 TCGLabel
*done_label
= gen_new_label();
2317 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2319 tmp
= tcg_temp_new_i64();
2322 if (s
->be_data
== MO_LE
) {
2323 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2325 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2327 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2328 cpu_exclusive_val
, tmp
,
2330 MO_64
| MO_ALIGN
| s
->be_data
);
2331 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2332 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2333 if (!HAVE_CMPXCHG128
) {
2334 gen_helper_exit_atomic(cpu_env
);
2335 s
->base
.is_jmp
= DISAS_NORETURN
;
2336 } else if (s
->be_data
== MO_LE
) {
2337 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2342 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2347 } else if (s
->be_data
== MO_LE
) {
2348 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2349 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2351 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2352 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2355 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2356 cpu_reg(s
, rt
), get_mem_index(s
),
2357 size
| MO_ALIGN
| s
->be_data
);
2358 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2360 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2361 tcg_temp_free_i64(tmp
);
2362 tcg_gen_br(done_label
);
2364 gen_set_label(fail_label
);
2365 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2366 gen_set_label(done_label
);
2367 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2370 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2373 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2374 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2375 int memidx
= get_mem_index(s
);
2376 TCGv_i64 clean_addr
;
2379 gen_check_sp_alignment(s
);
2381 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2382 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2383 size
| MO_ALIGN
| s
->be_data
);
2386 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2389 TCGv_i64 s1
= cpu_reg(s
, rs
);
2390 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2391 TCGv_i64 t1
= cpu_reg(s
, rt
);
2392 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2393 TCGv_i64 clean_addr
;
2394 int memidx
= get_mem_index(s
);
2397 gen_check_sp_alignment(s
);
2399 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2402 TCGv_i64 cmp
= tcg_temp_new_i64();
2403 TCGv_i64 val
= tcg_temp_new_i64();
2405 if (s
->be_data
== MO_LE
) {
2406 tcg_gen_concat32_i64(val
, t1
, t2
);
2407 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2409 tcg_gen_concat32_i64(val
, t2
, t1
);
2410 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2413 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2414 MO_64
| MO_ALIGN
| s
->be_data
);
2415 tcg_temp_free_i64(val
);
2417 if (s
->be_data
== MO_LE
) {
2418 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2420 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2422 tcg_temp_free_i64(cmp
);
2423 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2424 if (HAVE_CMPXCHG128
) {
2425 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2426 if (s
->be_data
== MO_LE
) {
2427 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2428 clean_addr
, t1
, t2
);
2430 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2431 clean_addr
, t1
, t2
);
2433 tcg_temp_free_i32(tcg_rs
);
2435 gen_helper_exit_atomic(cpu_env
);
2436 s
->base
.is_jmp
= DISAS_NORETURN
;
2439 TCGv_i64 d1
= tcg_temp_new_i64();
2440 TCGv_i64 d2
= tcg_temp_new_i64();
2441 TCGv_i64 a2
= tcg_temp_new_i64();
2442 TCGv_i64 c1
= tcg_temp_new_i64();
2443 TCGv_i64 c2
= tcg_temp_new_i64();
2444 TCGv_i64 zero
= tcg_const_i64(0);
2446 /* Load the two words, in memory order. */
2447 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2448 MO_64
| MO_ALIGN_16
| s
->be_data
);
2449 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2450 tcg_gen_qemu_ld_i64(d2
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2452 /* Compare the two words, also in memory order. */
2453 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2454 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2455 tcg_gen_and_i64(c2
, c2
, c1
);
2457 /* If compare equal, write back new data, else write back old data. */
2458 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2459 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2460 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2461 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2462 tcg_temp_free_i64(a2
);
2463 tcg_temp_free_i64(c1
);
2464 tcg_temp_free_i64(c2
);
2465 tcg_temp_free_i64(zero
);
2467 /* Write back the data from memory to Rs. */
2468 tcg_gen_mov_i64(s1
, d1
);
2469 tcg_gen_mov_i64(s2
, d2
);
2470 tcg_temp_free_i64(d1
);
2471 tcg_temp_free_i64(d2
);
2475 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2476 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2478 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2480 int opc0
= extract32(opc
, 0, 1);
2484 regsize
= opc0
? 32 : 64;
2486 regsize
= size
== 3 ? 64 : 32;
2488 return regsize
== 64;
2491 /* Load/store exclusive
2493 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2494 * +-----+-------------+----+---+----+------+----+-------+------+------+
2495 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2496 * +-----+-------------+----+---+----+------+----+-------+------+------+
2498 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2499 * L: 0 -> store, 1 -> load
2500 * o2: 0 -> exclusive, 1 -> not
2501 * o1: 0 -> single register, 1 -> register pair
2502 * o0: 1 -> load-acquire/store-release, 0 -> not
2504 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2506 int rt
= extract32(insn
, 0, 5);
2507 int rn
= extract32(insn
, 5, 5);
2508 int rt2
= extract32(insn
, 10, 5);
2509 int rs
= extract32(insn
, 16, 5);
2510 int is_lasr
= extract32(insn
, 15, 1);
2511 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2512 int size
= extract32(insn
, 30, 2);
2513 TCGv_i64 clean_addr
;
2515 switch (o2_L_o1_o0
) {
2516 case 0x0: /* STXR */
2517 case 0x1: /* STLXR */
2519 gen_check_sp_alignment(s
);
2522 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2524 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2525 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2528 case 0x4: /* LDXR */
2529 case 0x5: /* LDAXR */
2531 gen_check_sp_alignment(s
);
2533 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2535 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2537 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2541 case 0x8: /* STLLR */
2542 if (!dc_isar_feature(aa64_lor
, s
)) {
2545 /* StoreLORelease is the same as Store-Release for QEMU. */
2547 case 0x9: /* STLR */
2548 /* Generate ISS for non-exclusive accesses including LASR. */
2550 gen_check_sp_alignment(s
);
2552 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2553 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2554 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2555 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2558 case 0xc: /* LDLAR */
2559 if (!dc_isar_feature(aa64_lor
, s
)) {
2562 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2564 case 0xd: /* LDAR */
2565 /* Generate ISS for non-exclusive accesses including LASR. */
2567 gen_check_sp_alignment(s
);
2569 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2570 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2571 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2572 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2575 case 0x2: case 0x3: /* CASP / STXP */
2576 if (size
& 2) { /* STXP / STLXP */
2578 gen_check_sp_alignment(s
);
2581 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2583 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2584 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2588 && ((rt
| rs
) & 1) == 0
2589 && dc_isar_feature(aa64_atomics
, s
)) {
2591 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2596 case 0x6: case 0x7: /* CASPA / LDXP */
2597 if (size
& 2) { /* LDXP / LDAXP */
2599 gen_check_sp_alignment(s
);
2601 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2603 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2605 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2610 && ((rt
| rs
) & 1) == 0
2611 && dc_isar_feature(aa64_atomics
, s
)) {
2612 /* CASPA / CASPAL */
2613 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2619 case 0xb: /* CASL */
2620 case 0xe: /* CASA */
2621 case 0xf: /* CASAL */
2622 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2623 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2628 unallocated_encoding(s
);
2632 * Load register (literal)
2634 * 31 30 29 27 26 25 24 23 5 4 0
2635 * +-----+-------+---+-----+-------------------+-------+
2636 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2637 * +-----+-------+---+-----+-------------------+-------+
2639 * V: 1 -> vector (simd/fp)
2640 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2641 * 10-> 32 bit signed, 11 -> prefetch
2642 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2644 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2646 int rt
= extract32(insn
, 0, 5);
2647 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2648 bool is_vector
= extract32(insn
, 26, 1);
2649 int opc
= extract32(insn
, 30, 2);
2650 bool is_signed
= false;
2652 TCGv_i64 tcg_rt
, clean_addr
;
2656 unallocated_encoding(s
);
2660 if (!fp_access_check(s
)) {
2665 /* PRFM (literal) : prefetch */
2668 size
= 2 + extract32(opc
, 0, 1);
2669 is_signed
= extract32(opc
, 1, 1);
2672 tcg_rt
= cpu_reg(s
, rt
);
2674 clean_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2676 do_fp_ld(s
, rt
, clean_addr
, size
);
2678 /* Only unsigned 32bit loads target 32bit registers. */
2679 bool iss_sf
= opc
!= 0;
2681 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2682 true, rt
, iss_sf
, false);
2684 tcg_temp_free_i64(clean_addr
);
2688 * LDNP (Load Pair - non-temporal hint)
2689 * LDP (Load Pair - non vector)
2690 * LDPSW (Load Pair Signed Word - non vector)
2691 * STNP (Store Pair - non-temporal hint)
2692 * STP (Store Pair - non vector)
2693 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2694 * LDP (Load Pair of SIMD&FP)
2695 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2696 * STP (Store Pair of SIMD&FP)
2698 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2699 * +-----+-------+---+---+-------+---+-----------------------------+
2700 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2701 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2703 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2705 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2706 * V: 0 -> GPR, 1 -> Vector
2707 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2708 * 10 -> signed offset, 11 -> pre-index
2709 * L: 0 -> Store 1 -> Load
2711 * Rt, Rt2 = GPR or SIMD registers to be stored
2712 * Rn = general purpose register containing address
2713 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2715 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2717 int rt
= extract32(insn
, 0, 5);
2718 int rn
= extract32(insn
, 5, 5);
2719 int rt2
= extract32(insn
, 10, 5);
2720 uint64_t offset
= sextract64(insn
, 15, 7);
2721 int index
= extract32(insn
, 23, 2);
2722 bool is_vector
= extract32(insn
, 26, 1);
2723 bool is_load
= extract32(insn
, 22, 1);
2724 int opc
= extract32(insn
, 30, 2);
2726 bool is_signed
= false;
2727 bool postindex
= false;
2730 TCGv_i64 clean_addr
, dirty_addr
;
2735 unallocated_encoding(s
);
2742 size
= 2 + extract32(opc
, 1, 1);
2743 is_signed
= extract32(opc
, 0, 1);
2744 if (!is_load
&& is_signed
) {
2745 unallocated_encoding(s
);
2751 case 1: /* post-index */
2756 /* signed offset with "non-temporal" hint. Since we don't emulate
2757 * caches we don't care about hints to the cache system about
2758 * data access patterns, and handle this identically to plain
2762 /* There is no non-temporal-hint version of LDPSW */
2763 unallocated_encoding(s
);
2768 case 2: /* signed offset, rn not updated */
2771 case 3: /* pre-index */
2777 if (is_vector
&& !fp_access_check(s
)) {
2784 gen_check_sp_alignment(s
);
2787 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2789 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2791 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2795 do_fp_ld(s
, rt
, clean_addr
, size
);
2797 do_fp_st(s
, rt
, clean_addr
, size
);
2799 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2801 do_fp_ld(s
, rt2
, clean_addr
, size
);
2803 do_fp_st(s
, rt2
, clean_addr
, size
);
2806 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2807 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2810 TCGv_i64 tmp
= tcg_temp_new_i64();
2812 /* Do not modify tcg_rt before recognizing any exception
2813 * from the second load.
2815 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2816 false, 0, false, false);
2817 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2818 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2819 false, 0, false, false);
2821 tcg_gen_mov_i64(tcg_rt
, tmp
);
2822 tcg_temp_free_i64(tmp
);
2824 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2825 false, 0, false, false);
2826 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2827 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2828 false, 0, false, false);
2834 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2836 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2841 * Load/store (immediate post-indexed)
2842 * Load/store (immediate pre-indexed)
2843 * Load/store (unscaled immediate)
2845 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2846 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2847 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2848 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2850 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2852 * V = 0 -> non-vector
2853 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2854 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2856 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2862 int rn
= extract32(insn
, 5, 5);
2863 int imm9
= sextract32(insn
, 12, 9);
2864 int idx
= extract32(insn
, 10, 2);
2865 bool is_signed
= false;
2866 bool is_store
= false;
2867 bool is_extended
= false;
2868 bool is_unpriv
= (idx
== 2);
2869 bool iss_valid
= !is_vector
;
2873 TCGv_i64 clean_addr
, dirty_addr
;
2876 size
|= (opc
& 2) << 1;
2877 if (size
> 4 || is_unpriv
) {
2878 unallocated_encoding(s
);
2881 is_store
= ((opc
& 1) == 0);
2882 if (!fp_access_check(s
)) {
2886 if (size
== 3 && opc
== 2) {
2887 /* PRFM - prefetch */
2889 unallocated_encoding(s
);
2894 if (opc
== 3 && size
> 1) {
2895 unallocated_encoding(s
);
2898 is_store
= (opc
== 0);
2899 is_signed
= extract32(opc
, 1, 1);
2900 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2918 g_assert_not_reached();
2922 gen_check_sp_alignment(s
);
2925 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2927 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2929 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2933 do_fp_st(s
, rt
, clean_addr
, size
);
2935 do_fp_ld(s
, rt
, clean_addr
, size
);
2938 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2939 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2940 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2943 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2944 iss_valid
, rt
, iss_sf
, false);
2946 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2947 is_signed
, is_extended
, memidx
,
2948 iss_valid
, rt
, iss_sf
, false);
2953 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2955 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2957 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2962 * Load/store (register offset)
2964 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2965 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2966 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2967 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2970 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2971 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2973 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2974 * opc<0>: 0 -> store, 1 -> load
2975 * V: 1 -> vector/simd
2976 * opt: extend encoding (see DecodeRegExtend)
2977 * S: if S=1 then scale (essentially index by sizeof(size))
2978 * Rt: register to transfer into/out of
2979 * Rn: address register or SP for base
2980 * Rm: offset register or ZR for offset
2982 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2988 int rn
= extract32(insn
, 5, 5);
2989 int shift
= extract32(insn
, 12, 1);
2990 int rm
= extract32(insn
, 16, 5);
2991 int opt
= extract32(insn
, 13, 3);
2992 bool is_signed
= false;
2993 bool is_store
= false;
2994 bool is_extended
= false;
2996 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2998 if (extract32(opt
, 1, 1) == 0) {
2999 unallocated_encoding(s
);
3004 size
|= (opc
& 2) << 1;
3006 unallocated_encoding(s
);
3009 is_store
= !extract32(opc
, 0, 1);
3010 if (!fp_access_check(s
)) {
3014 if (size
== 3 && opc
== 2) {
3015 /* PRFM - prefetch */
3018 if (opc
== 3 && size
> 1) {
3019 unallocated_encoding(s
);
3022 is_store
= (opc
== 0);
3023 is_signed
= extract32(opc
, 1, 1);
3024 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3028 gen_check_sp_alignment(s
);
3030 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3032 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3033 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3035 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3036 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3040 do_fp_st(s
, rt
, clean_addr
, size
);
3042 do_fp_ld(s
, rt
, clean_addr
, size
);
3045 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3046 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3048 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3049 true, rt
, iss_sf
, false);
3051 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3052 is_signed
, is_extended
,
3053 true, rt
, iss_sf
, false);
3059 * Load/store (unsigned immediate)
3061 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3062 * +----+-------+---+-----+-----+------------+-------+------+
3063 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3064 * +----+-------+---+-----+-----+------------+-------+------+
3067 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3068 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3070 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3071 * opc<0>: 0 -> store, 1 -> load
3072 * Rn: base address register (inc SP)
3073 * Rt: target register
3075 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3081 int rn
= extract32(insn
, 5, 5);
3082 unsigned int imm12
= extract32(insn
, 10, 12);
3083 unsigned int offset
;
3085 TCGv_i64 clean_addr
, dirty_addr
;
3088 bool is_signed
= false;
3089 bool is_extended
= false;
3092 size
|= (opc
& 2) << 1;
3094 unallocated_encoding(s
);
3097 is_store
= !extract32(opc
, 0, 1);
3098 if (!fp_access_check(s
)) {
3102 if (size
== 3 && opc
== 2) {
3103 /* PRFM - prefetch */
3106 if (opc
== 3 && size
> 1) {
3107 unallocated_encoding(s
);
3110 is_store
= (opc
== 0);
3111 is_signed
= extract32(opc
, 1, 1);
3112 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3116 gen_check_sp_alignment(s
);
3118 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3119 offset
= imm12
<< size
;
3120 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3121 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3125 do_fp_st(s
, rt
, clean_addr
, size
);
3127 do_fp_ld(s
, rt
, clean_addr
, size
);
3130 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3131 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3133 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3134 true, rt
, iss_sf
, false);
3136 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3137 true, rt
, iss_sf
, false);
3142 /* Atomic memory operations
3144 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3145 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3146 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3147 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3149 * Rt: the result register
3150 * Rn: base address or SP
3151 * Rs: the source register for the operation
3152 * V: vector flag (always 0 as of v8.3)
3156 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3157 int size
, int rt
, bool is_vector
)
3159 int rs
= extract32(insn
, 16, 5);
3160 int rn
= extract32(insn
, 5, 5);
3161 int o3_opc
= extract32(insn
, 12, 4);
3162 TCGv_i64 tcg_rs
, clean_addr
;
3163 AtomicThreeOpFn
*fn
;
3165 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3166 unallocated_encoding(s
);
3170 case 000: /* LDADD */
3171 fn
= tcg_gen_atomic_fetch_add_i64
;
3173 case 001: /* LDCLR */
3174 fn
= tcg_gen_atomic_fetch_and_i64
;
3176 case 002: /* LDEOR */
3177 fn
= tcg_gen_atomic_fetch_xor_i64
;
3179 case 003: /* LDSET */
3180 fn
= tcg_gen_atomic_fetch_or_i64
;
3182 case 004: /* LDSMAX */
3183 fn
= tcg_gen_atomic_fetch_smax_i64
;
3185 case 005: /* LDSMIN */
3186 fn
= tcg_gen_atomic_fetch_smin_i64
;
3188 case 006: /* LDUMAX */
3189 fn
= tcg_gen_atomic_fetch_umax_i64
;
3191 case 007: /* LDUMIN */
3192 fn
= tcg_gen_atomic_fetch_umin_i64
;
3195 fn
= tcg_gen_atomic_xchg_i64
;
3198 unallocated_encoding(s
);
3203 gen_check_sp_alignment(s
);
3205 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3206 tcg_rs
= read_cpu_reg(s
, rs
, true);
3208 if (o3_opc
== 1) { /* LDCLR */
3209 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3212 /* The tcg atomic primitives are all full barriers. Therefore we
3213 * can ignore the Acquire and Release bits of this instruction.
3215 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3216 s
->be_data
| size
| MO_ALIGN
);
3220 * PAC memory operations
3222 * 31 30 27 26 24 22 21 12 11 10 5 0
3223 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3224 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3225 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3227 * Rt: the result register
3228 * Rn: base address or SP
3229 * V: vector flag (always 0 as of v8.3)
3230 * M: clear for key DA, set for key DB
3231 * W: pre-indexing flag
3234 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3235 int size
, int rt
, bool is_vector
)
3237 int rn
= extract32(insn
, 5, 5);
3238 bool is_wback
= extract32(insn
, 11, 1);
3239 bool use_key_a
= !extract32(insn
, 23, 1);
3241 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3243 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3244 unallocated_encoding(s
);
3249 gen_check_sp_alignment(s
);
3251 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3253 if (s
->pauth_active
) {
3255 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3257 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3261 /* Form the 10-bit signed, scaled offset. */
3262 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3263 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3264 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3266 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3267 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3269 tcg_rt
= cpu_reg(s
, rt
);
3270 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3271 /* extend */ false, /* iss_valid */ !is_wback
,
3272 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3275 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3279 /* Load/store register (all forms) */
3280 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3282 int rt
= extract32(insn
, 0, 5);
3283 int opc
= extract32(insn
, 22, 2);
3284 bool is_vector
= extract32(insn
, 26, 1);
3285 int size
= extract32(insn
, 30, 2);
3287 switch (extract32(insn
, 24, 2)) {
3289 if (extract32(insn
, 21, 1) == 0) {
3290 /* Load/store register (unscaled immediate)
3291 * Load/store immediate pre/post-indexed
3292 * Load/store register unprivileged
3294 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3297 switch (extract32(insn
, 10, 2)) {
3299 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3302 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3305 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3310 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3313 unallocated_encoding(s
);
3316 /* AdvSIMD load/store multiple structures
3318 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3319 * +---+---+---------------+---+-------------+--------+------+------+------+
3320 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3321 * +---+---+---------------+---+-------------+--------+------+------+------+
3323 * AdvSIMD load/store multiple structures (post-indexed)
3325 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3326 * +---+---+---------------+---+---+---------+--------+------+------+------+
3327 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3328 * +---+---+---------------+---+---+---------+--------+------+------+------+
3330 * Rt: first (or only) SIMD&FP register to be transferred
3331 * Rn: base address or SP
3332 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3334 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3336 int rt
= extract32(insn
, 0, 5);
3337 int rn
= extract32(insn
, 5, 5);
3338 int rm
= extract32(insn
, 16, 5);
3339 int size
= extract32(insn
, 10, 2);
3340 int opcode
= extract32(insn
, 12, 4);
3341 bool is_store
= !extract32(insn
, 22, 1);
3342 bool is_postidx
= extract32(insn
, 23, 1);
3343 bool is_q
= extract32(insn
, 30, 1);
3344 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3345 TCGMemOp endian
= s
->be_data
;
3347 int ebytes
; /* bytes per element */
3348 int elements
; /* elements per vector */
3349 int rpt
; /* num iterations */
3350 int selem
; /* structure elements */
3353 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3354 unallocated_encoding(s
);
3358 if (!is_postidx
&& rm
!= 0) {
3359 unallocated_encoding(s
);
3363 /* From the shared decode logic */
3394 unallocated_encoding(s
);
3398 if (size
== 3 && !is_q
&& selem
!= 1) {
3400 unallocated_encoding(s
);
3404 if (!fp_access_check(s
)) {
3409 gen_check_sp_alignment(s
);
3412 /* For our purposes, bytes are always little-endian. */
3417 /* Consecutive little-endian elements from a single register
3418 * can be promoted to a larger little-endian operation.
3420 if (selem
== 1 && endian
== MO_LE
) {
3424 elements
= (is_q
? 16 : 8) / ebytes
;
3426 tcg_rn
= cpu_reg_sp(s
, rn
);
3427 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3428 tcg_ebytes
= tcg_const_i64(ebytes
);
3430 for (r
= 0; r
< rpt
; r
++) {
3432 for (e
= 0; e
< elements
; e
++) {
3434 for (xs
= 0; xs
< selem
; xs
++) {
3435 int tt
= (rt
+ r
+ xs
) % 32;
3437 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3439 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3441 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3445 tcg_temp_free_i64(tcg_ebytes
);
3448 /* For non-quad operations, setting a slice of the low
3449 * 64 bits of the register clears the high 64 bits (in
3450 * the ARM ARM pseudocode this is implicit in the fact
3451 * that 'rval' is a 64 bit wide variable).
3452 * For quad operations, we might still need to zero the
3455 for (r
= 0; r
< rpt
* selem
; r
++) {
3456 int tt
= (rt
+ r
) % 32;
3457 clear_vec_high(s
, is_q
, tt
);
3463 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3465 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3470 /* AdvSIMD load/store single structure
3472 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3473 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3474 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3475 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3477 * AdvSIMD load/store single structure (post-indexed)
3479 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3480 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3481 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3482 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3484 * Rt: first (or only) SIMD&FP register to be transferred
3485 * Rn: base address or SP
3486 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3487 * index = encoded in Q:S:size dependent on size
3489 * lane_size = encoded in R, opc
3490 * transfer width = encoded in opc, S, size
3492 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3494 int rt
= extract32(insn
, 0, 5);
3495 int rn
= extract32(insn
, 5, 5);
3496 int rm
= extract32(insn
, 16, 5);
3497 int size
= extract32(insn
, 10, 2);
3498 int S
= extract32(insn
, 12, 1);
3499 int opc
= extract32(insn
, 13, 3);
3500 int R
= extract32(insn
, 21, 1);
3501 int is_load
= extract32(insn
, 22, 1);
3502 int is_postidx
= extract32(insn
, 23, 1);
3503 int is_q
= extract32(insn
, 30, 1);
3505 int scale
= extract32(opc
, 1, 2);
3506 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3507 bool replicate
= false;
3508 int index
= is_q
<< 3 | S
<< 2 | size
;
3510 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3512 if (extract32(insn
, 31, 1)) {
3513 unallocated_encoding(s
);
3516 if (!is_postidx
&& rm
!= 0) {
3517 unallocated_encoding(s
);
3523 if (!is_load
|| S
) {
3524 unallocated_encoding(s
);
3533 if (extract32(size
, 0, 1)) {
3534 unallocated_encoding(s
);
3540 if (extract32(size
, 1, 1)) {
3541 unallocated_encoding(s
);
3544 if (!extract32(size
, 0, 1)) {
3548 unallocated_encoding(s
);
3556 g_assert_not_reached();
3559 if (!fp_access_check(s
)) {
3563 ebytes
= 1 << scale
;
3566 gen_check_sp_alignment(s
);
3569 tcg_rn
= cpu_reg_sp(s
, rn
);
3570 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3571 tcg_ebytes
= tcg_const_i64(ebytes
);
3573 for (xs
= 0; xs
< selem
; xs
++) {
3575 /* Load and replicate to all elements */
3576 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3578 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3579 get_mem_index(s
), s
->be_data
+ scale
);
3580 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3581 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3583 tcg_temp_free_i64(tcg_tmp
);
3585 /* Load/store one element per register */
3587 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3589 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3592 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3595 tcg_temp_free_i64(tcg_ebytes
);
3599 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3601 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3606 /* Loads and stores */
3607 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3609 switch (extract32(insn
, 24, 6)) {
3610 case 0x08: /* Load/store exclusive */
3611 disas_ldst_excl(s
, insn
);
3613 case 0x18: case 0x1c: /* Load register (literal) */
3614 disas_ld_lit(s
, insn
);
3616 case 0x28: case 0x29:
3617 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3618 disas_ldst_pair(s
, insn
);
3620 case 0x38: case 0x39:
3621 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3622 disas_ldst_reg(s
, insn
);
3624 case 0x0c: /* AdvSIMD load/store multiple structures */
3625 disas_ldst_multiple_struct(s
, insn
);
3627 case 0x0d: /* AdvSIMD load/store single structure */
3628 disas_ldst_single_struct(s
, insn
);
3631 unallocated_encoding(s
);
3636 /* PC-rel. addressing
3637 * 31 30 29 28 24 23 5 4 0
3638 * +----+-------+-----------+-------------------+------+
3639 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3640 * +----+-------+-----------+-------------------+------+
3642 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3644 unsigned int page
, rd
;
3648 page
= extract32(insn
, 31, 1);
3649 /* SignExtend(immhi:immlo) -> offset */
3650 offset
= sextract64(insn
, 5, 19);
3651 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3652 rd
= extract32(insn
, 0, 5);
3656 /* ADRP (page based) */
3661 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3665 * Add/subtract (immediate)
3667 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3668 * +--+--+--+-----------+-----+-------------+-----+-----+
3669 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3670 * +--+--+--+-----------+-----+-------------+-----+-----+
3672 * sf: 0 -> 32bit, 1 -> 64bit
3673 * op: 0 -> add , 1 -> sub
3675 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3677 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3679 int rd
= extract32(insn
, 0, 5);
3680 int rn
= extract32(insn
, 5, 5);
3681 uint64_t imm
= extract32(insn
, 10, 12);
3682 int shift
= extract32(insn
, 22, 2);
3683 bool setflags
= extract32(insn
, 29, 1);
3684 bool sub_op
= extract32(insn
, 30, 1);
3685 bool is_64bit
= extract32(insn
, 31, 1);
3687 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3688 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3689 TCGv_i64 tcg_result
;
3698 unallocated_encoding(s
);
3702 tcg_result
= tcg_temp_new_i64();
3705 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3707 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3710 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3712 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3714 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3716 tcg_temp_free_i64(tcg_imm
);
3720 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3722 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3725 tcg_temp_free_i64(tcg_result
);
3728 /* The input should be a value in the bottom e bits (with higher
3729 * bits zero); returns that value replicated into every element
3730 * of size e in a 64 bit integer.
3732 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3742 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3743 static inline uint64_t bitmask64(unsigned int length
)
3745 assert(length
> 0 && length
<= 64);
3746 return ~0ULL >> (64 - length
);
3749 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3750 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3751 * value (ie should cause a guest UNDEF exception), and true if they are
3752 * valid, in which case the decoded bit pattern is written to result.
3754 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3755 unsigned int imms
, unsigned int immr
)
3758 unsigned e
, levels
, s
, r
;
3761 assert(immn
< 2 && imms
< 64 && immr
< 64);
3763 /* The bit patterns we create here are 64 bit patterns which
3764 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3765 * 64 bits each. Each element contains the same value: a run
3766 * of between 1 and e-1 non-zero bits, rotated within the
3767 * element by between 0 and e-1 bits.
3769 * The element size and run length are encoded into immn (1 bit)
3770 * and imms (6 bits) as follows:
3771 * 64 bit elements: immn = 1, imms = <length of run - 1>
3772 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3773 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3774 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3775 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3776 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3777 * Notice that immn = 0, imms = 11111x is the only combination
3778 * not covered by one of the above options; this is reserved.
3779 * Further, <length of run - 1> all-ones is a reserved pattern.
3781 * In all cases the rotation is by immr % e (and immr is 6 bits).
3784 /* First determine the element size */
3785 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3787 /* This is the immn == 0, imms == 0x11111x case */
3797 /* <length of run - 1> mustn't be all-ones. */
3801 /* Create the value of one element: s+1 set bits rotated
3802 * by r within the element (which is e bits wide)...
3804 mask
= bitmask64(s
+ 1);
3806 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3807 mask
&= bitmask64(e
);
3809 /* ...then replicate the element over the whole 64 bit value */
3810 mask
= bitfield_replicate(mask
, e
);
3815 /* Logical (immediate)
3816 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3817 * +----+-----+-------------+---+------+------+------+------+
3818 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3819 * +----+-----+-------------+---+------+------+------+------+
3821 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3823 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3824 TCGv_i64 tcg_rd
, tcg_rn
;
3826 bool is_and
= false;
3828 sf
= extract32(insn
, 31, 1);
3829 opc
= extract32(insn
, 29, 2);
3830 is_n
= extract32(insn
, 22, 1);
3831 immr
= extract32(insn
, 16, 6);
3832 imms
= extract32(insn
, 10, 6);
3833 rn
= extract32(insn
, 5, 5);
3834 rd
= extract32(insn
, 0, 5);
3837 unallocated_encoding(s
);
3841 if (opc
== 0x3) { /* ANDS */
3842 tcg_rd
= cpu_reg(s
, rd
);
3844 tcg_rd
= cpu_reg_sp(s
, rd
);
3846 tcg_rn
= cpu_reg(s
, rn
);
3848 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3849 /* some immediate field values are reserved */
3850 unallocated_encoding(s
);
3855 wmask
&= 0xffffffff;
3859 case 0x3: /* ANDS */
3861 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3865 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3868 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3871 assert(FALSE
); /* must handle all above */
3875 if (!sf
&& !is_and
) {
3876 /* zero extend final result; we know we can skip this for AND
3877 * since the immediate had the high 32 bits clear.
3879 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3882 if (opc
== 3) { /* ANDS */
3883 gen_logic_CC(sf
, tcg_rd
);
3888 * Move wide (immediate)
3890 * 31 30 29 28 23 22 21 20 5 4 0
3891 * +--+-----+-------------+-----+----------------+------+
3892 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3893 * +--+-----+-------------+-----+----------------+------+
3895 * sf: 0 -> 32 bit, 1 -> 64 bit
3896 * opc: 00 -> N, 10 -> Z, 11 -> K
3897 * hw: shift/16 (0,16, and sf only 32, 48)
3899 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3901 int rd
= extract32(insn
, 0, 5);
3902 uint64_t imm
= extract32(insn
, 5, 16);
3903 int sf
= extract32(insn
, 31, 1);
3904 int opc
= extract32(insn
, 29, 2);
3905 int pos
= extract32(insn
, 21, 2) << 4;
3906 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3909 if (!sf
&& (pos
>= 32)) {
3910 unallocated_encoding(s
);
3924 tcg_gen_movi_i64(tcg_rd
, imm
);
3927 tcg_imm
= tcg_const_i64(imm
);
3928 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3929 tcg_temp_free_i64(tcg_imm
);
3931 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3935 unallocated_encoding(s
);
3941 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3942 * +----+-----+-------------+---+------+------+------+------+
3943 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3944 * +----+-----+-------------+---+------+------+------+------+
3946 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3948 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3949 TCGv_i64 tcg_rd
, tcg_tmp
;
3951 sf
= extract32(insn
, 31, 1);
3952 opc
= extract32(insn
, 29, 2);
3953 n
= extract32(insn
, 22, 1);
3954 ri
= extract32(insn
, 16, 6);
3955 si
= extract32(insn
, 10, 6);
3956 rn
= extract32(insn
, 5, 5);
3957 rd
= extract32(insn
, 0, 5);
3958 bitsize
= sf
? 64 : 32;
3960 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3961 unallocated_encoding(s
);
3965 tcg_rd
= cpu_reg(s
, rd
);
3967 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3968 to be smaller than bitsize, we'll never reference data outside the
3969 low 32-bits anyway. */
3970 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3972 /* Recognize simple(r) extractions. */
3974 /* Wd<s-r:0> = Wn<s:r> */
3975 len
= (si
- ri
) + 1;
3976 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3977 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3979 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3980 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3983 /* opc == 1, BXFIL fall through to deposit */
3984 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3987 /* Handle the ri > si case with a deposit
3988 * Wd<32+s-r,32-r> = Wn<s:0>
3991 pos
= (bitsize
- ri
) & (bitsize
- 1);
3994 if (opc
== 0 && len
< ri
) {
3995 /* SBFM: sign extend the destination field from len to fill
3996 the balance of the word. Let the deposit below insert all
3997 of those sign bits. */
3998 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4002 if (opc
== 1) { /* BFM, BXFIL */
4003 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4005 /* SBFM or UBFM: We start with zero, and we haven't modified
4006 any bits outside bitsize, therefore the zero-extension
4007 below is unneeded. */
4008 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4013 if (!sf
) { /* zero extend final result */
4014 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4019 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4020 * +----+------+-------------+---+----+------+--------+------+------+
4021 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4022 * +----+------+-------------+---+----+------+--------+------+------+
4024 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4026 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4028 sf
= extract32(insn
, 31, 1);
4029 n
= extract32(insn
, 22, 1);
4030 rm
= extract32(insn
, 16, 5);
4031 imm
= extract32(insn
, 10, 6);
4032 rn
= extract32(insn
, 5, 5);
4033 rd
= extract32(insn
, 0, 5);
4034 op21
= extract32(insn
, 29, 2);
4035 op0
= extract32(insn
, 21, 1);
4036 bitsize
= sf
? 64 : 32;
4038 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4039 unallocated_encoding(s
);
4041 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4043 tcg_rd
= cpu_reg(s
, rd
);
4045 if (unlikely(imm
== 0)) {
4046 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4047 * so an extract from bit 0 is a special case.
4050 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4052 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4054 } else if (rm
== rn
) { /* ROR */
4055 tcg_rm
= cpu_reg(s
, rm
);
4057 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
4059 TCGv_i32 tmp
= tcg_temp_new_i32();
4060 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
4061 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
4062 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
4063 tcg_temp_free_i32(tmp
);
4066 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4067 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4068 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
4069 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
4070 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
4072 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4078 /* Data processing - immediate */
4079 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4081 switch (extract32(insn
, 23, 6)) {
4082 case 0x20: case 0x21: /* PC-rel. addressing */
4083 disas_pc_rel_adr(s
, insn
);
4085 case 0x22: case 0x23: /* Add/subtract (immediate) */
4086 disas_add_sub_imm(s
, insn
);
4088 case 0x24: /* Logical (immediate) */
4089 disas_logic_imm(s
, insn
);
4091 case 0x25: /* Move wide (immediate) */
4092 disas_movw_imm(s
, insn
);
4094 case 0x26: /* Bitfield */
4095 disas_bitfield(s
, insn
);
4097 case 0x27: /* Extract */
4098 disas_extract(s
, insn
);
4101 unallocated_encoding(s
);
4106 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4107 * Note that it is the caller's responsibility to ensure that the
4108 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4109 * mandated semantics for out of range shifts.
4111 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4112 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4114 switch (shift_type
) {
4115 case A64_SHIFT_TYPE_LSL
:
4116 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4118 case A64_SHIFT_TYPE_LSR
:
4119 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4121 case A64_SHIFT_TYPE_ASR
:
4123 tcg_gen_ext32s_i64(dst
, src
);
4125 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4127 case A64_SHIFT_TYPE_ROR
:
4129 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4132 t0
= tcg_temp_new_i32();
4133 t1
= tcg_temp_new_i32();
4134 tcg_gen_extrl_i64_i32(t0
, src
);
4135 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4136 tcg_gen_rotr_i32(t0
, t0
, t1
);
4137 tcg_gen_extu_i32_i64(dst
, t0
);
4138 tcg_temp_free_i32(t0
);
4139 tcg_temp_free_i32(t1
);
4143 assert(FALSE
); /* all shift types should be handled */
4147 if (!sf
) { /* zero extend final result */
4148 tcg_gen_ext32u_i64(dst
, dst
);
4152 /* Shift a TCGv src by immediate, put result in dst.
4153 * The shift amount must be in range (this should always be true as the
4154 * relevant instructions will UNDEF on bad shift immediates).
4156 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4157 enum a64_shift_type shift_type
, unsigned int shift_i
)
4159 assert(shift_i
< (sf
? 64 : 32));
4162 tcg_gen_mov_i64(dst
, src
);
4164 TCGv_i64 shift_const
;
4166 shift_const
= tcg_const_i64(shift_i
);
4167 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4168 tcg_temp_free_i64(shift_const
);
4172 /* Logical (shifted register)
4173 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4174 * +----+-----+-----------+-------+---+------+--------+------+------+
4175 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4176 * +----+-----+-----------+-------+---+------+--------+------+------+
4178 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4180 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4181 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4183 sf
= extract32(insn
, 31, 1);
4184 opc
= extract32(insn
, 29, 2);
4185 shift_type
= extract32(insn
, 22, 2);
4186 invert
= extract32(insn
, 21, 1);
4187 rm
= extract32(insn
, 16, 5);
4188 shift_amount
= extract32(insn
, 10, 6);
4189 rn
= extract32(insn
, 5, 5);
4190 rd
= extract32(insn
, 0, 5);
4192 if (!sf
&& (shift_amount
& (1 << 5))) {
4193 unallocated_encoding(s
);
4197 tcg_rd
= cpu_reg(s
, rd
);
4199 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4200 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4201 * register-register MOV and MVN, so it is worth special casing.
4203 tcg_rm
= cpu_reg(s
, rm
);
4205 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4207 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4211 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4213 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4219 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4222 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4225 tcg_rn
= cpu_reg(s
, rn
);
4227 switch (opc
| (invert
<< 2)) {
4230 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4233 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4236 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4240 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4243 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4246 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4254 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4258 gen_logic_CC(sf
, tcg_rd
);
4263 * Add/subtract (extended register)
4265 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4266 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4267 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4268 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4270 * sf: 0 -> 32bit, 1 -> 64bit
4271 * op: 0 -> add , 1 -> sub
4274 * option: extension type (see DecodeRegExtend)
4275 * imm3: optional shift to Rm
4277 * Rd = Rn + LSL(extend(Rm), amount)
4279 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4281 int rd
= extract32(insn
, 0, 5);
4282 int rn
= extract32(insn
, 5, 5);
4283 int imm3
= extract32(insn
, 10, 3);
4284 int option
= extract32(insn
, 13, 3);
4285 int rm
= extract32(insn
, 16, 5);
4286 int opt
= extract32(insn
, 22, 2);
4287 bool setflags
= extract32(insn
, 29, 1);
4288 bool sub_op
= extract32(insn
, 30, 1);
4289 bool sf
= extract32(insn
, 31, 1);
4291 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4293 TCGv_i64 tcg_result
;
4295 if (imm3
> 4 || opt
!= 0) {
4296 unallocated_encoding(s
);
4300 /* non-flag setting ops may use SP */
4302 tcg_rd
= cpu_reg_sp(s
, rd
);
4304 tcg_rd
= cpu_reg(s
, rd
);
4306 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4308 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4309 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4311 tcg_result
= tcg_temp_new_i64();
4315 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4317 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4321 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4323 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4328 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4330 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4333 tcg_temp_free_i64(tcg_result
);
4337 * Add/subtract (shifted register)
4339 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4340 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4341 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4342 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4344 * sf: 0 -> 32bit, 1 -> 64bit
4345 * op: 0 -> add , 1 -> sub
4347 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4348 * imm6: Shift amount to apply to Rm before the add/sub
4350 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4352 int rd
= extract32(insn
, 0, 5);
4353 int rn
= extract32(insn
, 5, 5);
4354 int imm6
= extract32(insn
, 10, 6);
4355 int rm
= extract32(insn
, 16, 5);
4356 int shift_type
= extract32(insn
, 22, 2);
4357 bool setflags
= extract32(insn
, 29, 1);
4358 bool sub_op
= extract32(insn
, 30, 1);
4359 bool sf
= extract32(insn
, 31, 1);
4361 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4362 TCGv_i64 tcg_rn
, tcg_rm
;
4363 TCGv_i64 tcg_result
;
4365 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4366 unallocated_encoding(s
);
4370 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4371 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4373 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4375 tcg_result
= tcg_temp_new_i64();
4379 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4381 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4385 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4387 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4392 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4394 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4397 tcg_temp_free_i64(tcg_result
);
4400 /* Data-processing (3 source)
4402 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4403 * +--+------+-----------+------+------+----+------+------+------+
4404 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4405 * +--+------+-----------+------+------+----+------+------+------+
4407 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4409 int rd
= extract32(insn
, 0, 5);
4410 int rn
= extract32(insn
, 5, 5);
4411 int ra
= extract32(insn
, 10, 5);
4412 int rm
= extract32(insn
, 16, 5);
4413 int op_id
= (extract32(insn
, 29, 3) << 4) |
4414 (extract32(insn
, 21, 3) << 1) |
4415 extract32(insn
, 15, 1);
4416 bool sf
= extract32(insn
, 31, 1);
4417 bool is_sub
= extract32(op_id
, 0, 1);
4418 bool is_high
= extract32(op_id
, 2, 1);
4419 bool is_signed
= false;
4424 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4426 case 0x42: /* SMADDL */
4427 case 0x43: /* SMSUBL */
4428 case 0x44: /* SMULH */
4431 case 0x0: /* MADD (32bit) */
4432 case 0x1: /* MSUB (32bit) */
4433 case 0x40: /* MADD (64bit) */
4434 case 0x41: /* MSUB (64bit) */
4435 case 0x4a: /* UMADDL */
4436 case 0x4b: /* UMSUBL */
4437 case 0x4c: /* UMULH */
4440 unallocated_encoding(s
);
4445 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4446 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4447 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4448 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4451 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4453 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4456 tcg_temp_free_i64(low_bits
);
4460 tcg_op1
= tcg_temp_new_i64();
4461 tcg_op2
= tcg_temp_new_i64();
4462 tcg_tmp
= tcg_temp_new_i64();
4465 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4466 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4469 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4470 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4472 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4473 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4477 if (ra
== 31 && !is_sub
) {
4478 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4479 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4481 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4483 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4485 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4490 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4493 tcg_temp_free_i64(tcg_op1
);
4494 tcg_temp_free_i64(tcg_op2
);
4495 tcg_temp_free_i64(tcg_tmp
);
4498 /* Add/subtract (with carry)
4499 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4500 * +--+--+--+------------------------+------+---------+------+-----+
4501 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4502 * +--+--+--+------------------------+------+---------+------+-----+
4506 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4508 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4509 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4511 if (extract32(insn
, 10, 6) != 0) {
4512 unallocated_encoding(s
);
4516 sf
= extract32(insn
, 31, 1);
4517 op
= extract32(insn
, 30, 1);
4518 setflags
= extract32(insn
, 29, 1);
4519 rm
= extract32(insn
, 16, 5);
4520 rn
= extract32(insn
, 5, 5);
4521 rd
= extract32(insn
, 0, 5);
4523 tcg_rd
= cpu_reg(s
, rd
);
4524 tcg_rn
= cpu_reg(s
, rn
);
4527 tcg_y
= new_tmp_a64(s
);
4528 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4530 tcg_y
= cpu_reg(s
, rm
);
4534 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4536 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4540 /* Conditional compare (immediate / register)
4541 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4542 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4543 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4544 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4547 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4549 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4550 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4551 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4554 if (!extract32(insn
, 29, 1)) {
4555 unallocated_encoding(s
);
4558 if (insn
& (1 << 10 | 1 << 4)) {
4559 unallocated_encoding(s
);
4562 sf
= extract32(insn
, 31, 1);
4563 op
= extract32(insn
, 30, 1);
4564 is_imm
= extract32(insn
, 11, 1);
4565 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4566 cond
= extract32(insn
, 12, 4);
4567 rn
= extract32(insn
, 5, 5);
4568 nzcv
= extract32(insn
, 0, 4);
4570 /* Set T0 = !COND. */
4571 tcg_t0
= tcg_temp_new_i32();
4572 arm_test_cc(&c
, cond
);
4573 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4576 /* Load the arguments for the new comparison. */
4578 tcg_y
= new_tmp_a64(s
);
4579 tcg_gen_movi_i64(tcg_y
, y
);
4581 tcg_y
= cpu_reg(s
, y
);
4583 tcg_rn
= cpu_reg(s
, rn
);
4585 /* Set the flags for the new comparison. */
4586 tcg_tmp
= tcg_temp_new_i64();
4588 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4590 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4592 tcg_temp_free_i64(tcg_tmp
);
4594 /* If COND was false, force the flags to #nzcv. Compute two masks
4595 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4596 * For tcg hosts that support ANDC, we can make do with just T1.
4597 * In either case, allow the tcg optimizer to delete any unused mask.
4599 tcg_t1
= tcg_temp_new_i32();
4600 tcg_t2
= tcg_temp_new_i32();
4601 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4602 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4604 if (nzcv
& 8) { /* N */
4605 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4607 if (TCG_TARGET_HAS_andc_i32
) {
4608 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4610 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4613 if (nzcv
& 4) { /* Z */
4614 if (TCG_TARGET_HAS_andc_i32
) {
4615 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4617 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4620 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4622 if (nzcv
& 2) { /* C */
4623 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4625 if (TCG_TARGET_HAS_andc_i32
) {
4626 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4628 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4631 if (nzcv
& 1) { /* V */
4632 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4634 if (TCG_TARGET_HAS_andc_i32
) {
4635 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4637 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4640 tcg_temp_free_i32(tcg_t0
);
4641 tcg_temp_free_i32(tcg_t1
);
4642 tcg_temp_free_i32(tcg_t2
);
4645 /* Conditional select
4646 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4647 * +----+----+---+-----------------+------+------+-----+------+------+
4648 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4649 * +----+----+---+-----------------+------+------+-----+------+------+
4651 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4653 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4654 TCGv_i64 tcg_rd
, zero
;
4657 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4658 /* S == 1 or op2<1> == 1 */
4659 unallocated_encoding(s
);
4662 sf
= extract32(insn
, 31, 1);
4663 else_inv
= extract32(insn
, 30, 1);
4664 rm
= extract32(insn
, 16, 5);
4665 cond
= extract32(insn
, 12, 4);
4666 else_inc
= extract32(insn
, 10, 1);
4667 rn
= extract32(insn
, 5, 5);
4668 rd
= extract32(insn
, 0, 5);
4670 tcg_rd
= cpu_reg(s
, rd
);
4672 a64_test_cc(&c
, cond
);
4673 zero
= tcg_const_i64(0);
4675 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4677 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4679 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4682 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4683 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4684 if (else_inv
&& else_inc
) {
4685 tcg_gen_neg_i64(t_false
, t_false
);
4686 } else if (else_inv
) {
4687 tcg_gen_not_i64(t_false
, t_false
);
4688 } else if (else_inc
) {
4689 tcg_gen_addi_i64(t_false
, t_false
, 1);
4691 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4694 tcg_temp_free_i64(zero
);
4698 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4702 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4703 unsigned int rn
, unsigned int rd
)
4705 TCGv_i64 tcg_rd
, tcg_rn
;
4706 tcg_rd
= cpu_reg(s
, rd
);
4707 tcg_rn
= cpu_reg(s
, rn
);
4710 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4712 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4713 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4714 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4715 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4716 tcg_temp_free_i32(tcg_tmp32
);
4720 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4721 unsigned int rn
, unsigned int rd
)
4723 TCGv_i64 tcg_rd
, tcg_rn
;
4724 tcg_rd
= cpu_reg(s
, rd
);
4725 tcg_rn
= cpu_reg(s
, rn
);
4728 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4730 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4731 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4732 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4733 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4734 tcg_temp_free_i32(tcg_tmp32
);
4738 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4739 unsigned int rn
, unsigned int rd
)
4741 TCGv_i64 tcg_rd
, tcg_rn
;
4742 tcg_rd
= cpu_reg(s
, rd
);
4743 tcg_rn
= cpu_reg(s
, rn
);
4746 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4748 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4749 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4750 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4751 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4752 tcg_temp_free_i32(tcg_tmp32
);
4756 /* REV with sf==1, opcode==3 ("REV64") */
4757 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4758 unsigned int rn
, unsigned int rd
)
4761 unallocated_encoding(s
);
4764 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4767 /* REV with sf==0, opcode==2
4768 * REV32 (sf==1, opcode==2)
4770 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4771 unsigned int rn
, unsigned int rd
)
4773 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4776 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4777 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4779 /* bswap32_i64 requires zero high word */
4780 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4781 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4782 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4783 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4784 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4786 tcg_temp_free_i64(tcg_tmp
);
4788 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4789 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4793 /* REV16 (opcode==1) */
4794 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4795 unsigned int rn
, unsigned int rd
)
4797 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4798 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4799 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4800 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4802 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4803 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4804 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4805 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4806 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4808 tcg_temp_free_i64(mask
);
4809 tcg_temp_free_i64(tcg_tmp
);
4812 /* Data-processing (1 source)
4813 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4814 * +----+---+---+-----------------+---------+--------+------+------+
4815 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4816 * +----+---+---+-----------------+---------+--------+------+------+
4818 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4820 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4823 if (extract32(insn
, 29, 1)) {
4824 unallocated_encoding(s
);
4828 sf
= extract32(insn
, 31, 1);
4829 opcode
= extract32(insn
, 10, 6);
4830 opcode2
= extract32(insn
, 16, 5);
4831 rn
= extract32(insn
, 5, 5);
4832 rd
= extract32(insn
, 0, 5);
4834 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4836 switch (MAP(sf
, opcode2
, opcode
)) {
4837 case MAP(0, 0x00, 0x00): /* RBIT */
4838 case MAP(1, 0x00, 0x00):
4839 handle_rbit(s
, sf
, rn
, rd
);
4841 case MAP(0, 0x00, 0x01): /* REV16 */
4842 case MAP(1, 0x00, 0x01):
4843 handle_rev16(s
, sf
, rn
, rd
);
4845 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4846 case MAP(1, 0x00, 0x02):
4847 handle_rev32(s
, sf
, rn
, rd
);
4849 case MAP(1, 0x00, 0x03): /* REV64 */
4850 handle_rev64(s
, sf
, rn
, rd
);
4852 case MAP(0, 0x00, 0x04): /* CLZ */
4853 case MAP(1, 0x00, 0x04):
4854 handle_clz(s
, sf
, rn
, rd
);
4856 case MAP(0, 0x00, 0x05): /* CLS */
4857 case MAP(1, 0x00, 0x05):
4858 handle_cls(s
, sf
, rn
, rd
);
4860 case MAP(1, 0x01, 0x00): /* PACIA */
4861 if (s
->pauth_active
) {
4862 tcg_rd
= cpu_reg(s
, rd
);
4863 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4864 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4865 goto do_unallocated
;
4868 case MAP(1, 0x01, 0x01): /* PACIB */
4869 if (s
->pauth_active
) {
4870 tcg_rd
= cpu_reg(s
, rd
);
4871 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4872 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4873 goto do_unallocated
;
4876 case MAP(1, 0x01, 0x02): /* PACDA */
4877 if (s
->pauth_active
) {
4878 tcg_rd
= cpu_reg(s
, rd
);
4879 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4880 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4881 goto do_unallocated
;
4884 case MAP(1, 0x01, 0x03): /* PACDB */
4885 if (s
->pauth_active
) {
4886 tcg_rd
= cpu_reg(s
, rd
);
4887 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4888 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4889 goto do_unallocated
;
4892 case MAP(1, 0x01, 0x04): /* AUTIA */
4893 if (s
->pauth_active
) {
4894 tcg_rd
= cpu_reg(s
, rd
);
4895 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4896 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4897 goto do_unallocated
;
4900 case MAP(1, 0x01, 0x05): /* AUTIB */
4901 if (s
->pauth_active
) {
4902 tcg_rd
= cpu_reg(s
, rd
);
4903 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4904 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4905 goto do_unallocated
;
4908 case MAP(1, 0x01, 0x06): /* AUTDA */
4909 if (s
->pauth_active
) {
4910 tcg_rd
= cpu_reg(s
, rd
);
4911 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4912 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4913 goto do_unallocated
;
4916 case MAP(1, 0x01, 0x07): /* AUTDB */
4917 if (s
->pauth_active
) {
4918 tcg_rd
= cpu_reg(s
, rd
);
4919 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4920 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4921 goto do_unallocated
;
4924 case MAP(1, 0x01, 0x08): /* PACIZA */
4925 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4926 goto do_unallocated
;
4927 } else if (s
->pauth_active
) {
4928 tcg_rd
= cpu_reg(s
, rd
);
4929 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4932 case MAP(1, 0x01, 0x09): /* PACIZB */
4933 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4934 goto do_unallocated
;
4935 } else if (s
->pauth_active
) {
4936 tcg_rd
= cpu_reg(s
, rd
);
4937 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4940 case MAP(1, 0x01, 0x0a): /* PACDZA */
4941 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4942 goto do_unallocated
;
4943 } else if (s
->pauth_active
) {
4944 tcg_rd
= cpu_reg(s
, rd
);
4945 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4948 case MAP(1, 0x01, 0x0b): /* PACDZB */
4949 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4950 goto do_unallocated
;
4951 } else if (s
->pauth_active
) {
4952 tcg_rd
= cpu_reg(s
, rd
);
4953 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4956 case MAP(1, 0x01, 0x0c): /* AUTIZA */
4957 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4958 goto do_unallocated
;
4959 } else if (s
->pauth_active
) {
4960 tcg_rd
= cpu_reg(s
, rd
);
4961 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4964 case MAP(1, 0x01, 0x0d): /* AUTIZB */
4965 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4966 goto do_unallocated
;
4967 } else if (s
->pauth_active
) {
4968 tcg_rd
= cpu_reg(s
, rd
);
4969 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4972 case MAP(1, 0x01, 0x0e): /* AUTDZA */
4973 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4974 goto do_unallocated
;
4975 } else if (s
->pauth_active
) {
4976 tcg_rd
= cpu_reg(s
, rd
);
4977 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4980 case MAP(1, 0x01, 0x0f): /* AUTDZB */
4981 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4982 goto do_unallocated
;
4983 } else if (s
->pauth_active
) {
4984 tcg_rd
= cpu_reg(s
, rd
);
4985 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4988 case MAP(1, 0x01, 0x10): /* XPACI */
4989 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4990 goto do_unallocated
;
4991 } else if (s
->pauth_active
) {
4992 tcg_rd
= cpu_reg(s
, rd
);
4993 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
4996 case MAP(1, 0x01, 0x11): /* XPACD */
4997 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4998 goto do_unallocated
;
4999 } else if (s
->pauth_active
) {
5000 tcg_rd
= cpu_reg(s
, rd
);
5001 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5006 unallocated_encoding(s
);
5013 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5014 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5016 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5017 tcg_rd
= cpu_reg(s
, rd
);
5019 if (!sf
&& is_signed
) {
5020 tcg_n
= new_tmp_a64(s
);
5021 tcg_m
= new_tmp_a64(s
);
5022 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5023 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5025 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5026 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5030 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5032 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5035 if (!sf
) { /* zero extend final result */
5036 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5040 /* LSLV, LSRV, ASRV, RORV */
5041 static void handle_shift_reg(DisasContext
*s
,
5042 enum a64_shift_type shift_type
, unsigned int sf
,
5043 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5045 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5046 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5047 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5049 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5050 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5051 tcg_temp_free_i64(tcg_shift
);
5054 /* CRC32[BHWX], CRC32C[BHWX] */
5055 static void handle_crc32(DisasContext
*s
,
5056 unsigned int sf
, unsigned int sz
, bool crc32c
,
5057 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5059 TCGv_i64 tcg_acc
, tcg_val
;
5062 if (!dc_isar_feature(aa64_crc32
, s
)
5063 || (sf
== 1 && sz
!= 3)
5064 || (sf
== 0 && sz
== 3)) {
5065 unallocated_encoding(s
);
5070 tcg_val
= cpu_reg(s
, rm
);
5084 g_assert_not_reached();
5086 tcg_val
= new_tmp_a64(s
);
5087 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5090 tcg_acc
= cpu_reg(s
, rn
);
5091 tcg_bytes
= tcg_const_i32(1 << sz
);
5094 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5096 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5099 tcg_temp_free_i32(tcg_bytes
);
5102 /* Data-processing (2 source)
5103 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5104 * +----+---+---+-----------------+------+--------+------+------+
5105 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5106 * +----+---+---+-----------------+------+--------+------+------+
5108 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5110 unsigned int sf
, rm
, opcode
, rn
, rd
;
5111 sf
= extract32(insn
, 31, 1);
5112 rm
= extract32(insn
, 16, 5);
5113 opcode
= extract32(insn
, 10, 6);
5114 rn
= extract32(insn
, 5, 5);
5115 rd
= extract32(insn
, 0, 5);
5117 if (extract32(insn
, 29, 1)) {
5118 unallocated_encoding(s
);
5124 handle_div(s
, false, sf
, rm
, rn
, rd
);
5127 handle_div(s
, true, sf
, rm
, rn
, rd
);
5130 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5133 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5136 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5139 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5141 case 12: /* PACGA */
5142 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5143 goto do_unallocated
;
5145 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5146 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5155 case 23: /* CRC32 */
5157 int sz
= extract32(opcode
, 0, 2);
5158 bool crc32c
= extract32(opcode
, 2, 1);
5159 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5164 unallocated_encoding(s
);
5169 /* Data processing - register */
5170 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5172 switch (extract32(insn
, 24, 5)) {
5173 case 0x0a: /* Logical (shifted register) */
5174 disas_logic_reg(s
, insn
);
5176 case 0x0b: /* Add/subtract */
5177 if (insn
& (1 << 21)) { /* (extended register) */
5178 disas_add_sub_ext_reg(s
, insn
);
5180 disas_add_sub_reg(s
, insn
);
5183 case 0x1b: /* Data-processing (3 source) */
5184 disas_data_proc_3src(s
, insn
);
5187 switch (extract32(insn
, 21, 3)) {
5188 case 0x0: /* Add/subtract (with carry) */
5189 disas_adc_sbc(s
, insn
);
5191 case 0x2: /* Conditional compare */
5192 disas_cc(s
, insn
); /* both imm and reg forms */
5194 case 0x4: /* Conditional select */
5195 disas_cond_select(s
, insn
);
5197 case 0x6: /* Data-processing */
5198 if (insn
& (1 << 30)) { /* (1 source) */
5199 disas_data_proc_1src(s
, insn
);
5200 } else { /* (2 source) */
5201 disas_data_proc_2src(s
, insn
);
5205 unallocated_encoding(s
);
5210 unallocated_encoding(s
);
5215 static void handle_fp_compare(DisasContext
*s
, int size
,
5216 unsigned int rn
, unsigned int rm
,
5217 bool cmp_with_zero
, bool signal_all_nans
)
5219 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5220 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5222 if (size
== MO_64
) {
5223 TCGv_i64 tcg_vn
, tcg_vm
;
5225 tcg_vn
= read_fp_dreg(s
, rn
);
5226 if (cmp_with_zero
) {
5227 tcg_vm
= tcg_const_i64(0);
5229 tcg_vm
= read_fp_dreg(s
, rm
);
5231 if (signal_all_nans
) {
5232 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5234 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5236 tcg_temp_free_i64(tcg_vn
);
5237 tcg_temp_free_i64(tcg_vm
);
5239 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5240 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5242 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5243 if (cmp_with_zero
) {
5244 tcg_gen_movi_i32(tcg_vm
, 0);
5246 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5251 if (signal_all_nans
) {
5252 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5254 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5258 if (signal_all_nans
) {
5259 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5261 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5265 g_assert_not_reached();
5268 tcg_temp_free_i32(tcg_vn
);
5269 tcg_temp_free_i32(tcg_vm
);
5272 tcg_temp_free_ptr(fpst
);
5274 gen_set_nzcv(tcg_flags
);
5276 tcg_temp_free_i64(tcg_flags
);
5279 /* Floating point compare
5280 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5281 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5282 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5283 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5285 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5287 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5290 mos
= extract32(insn
, 29, 3);
5291 type
= extract32(insn
, 22, 2);
5292 rm
= extract32(insn
, 16, 5);
5293 op
= extract32(insn
, 14, 2);
5294 rn
= extract32(insn
, 5, 5);
5295 opc
= extract32(insn
, 3, 2);
5296 op2r
= extract32(insn
, 0, 3);
5298 if (mos
|| op
|| op2r
) {
5299 unallocated_encoding(s
);
5312 if (dc_isar_feature(aa64_fp16
, s
)) {
5317 unallocated_encoding(s
);
5321 if (!fp_access_check(s
)) {
5325 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5328 /* Floating point conditional compare
5329 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5330 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5331 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5332 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5334 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5336 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5338 TCGLabel
*label_continue
= NULL
;
5341 mos
= extract32(insn
, 29, 3);
5342 type
= extract32(insn
, 22, 2);
5343 rm
= extract32(insn
, 16, 5);
5344 cond
= extract32(insn
, 12, 4);
5345 rn
= extract32(insn
, 5, 5);
5346 op
= extract32(insn
, 4, 1);
5347 nzcv
= extract32(insn
, 0, 4);
5350 unallocated_encoding(s
);
5363 if (dc_isar_feature(aa64_fp16
, s
)) {
5368 unallocated_encoding(s
);
5372 if (!fp_access_check(s
)) {
5376 if (cond
< 0x0e) { /* not always */
5377 TCGLabel
*label_match
= gen_new_label();
5378 label_continue
= gen_new_label();
5379 arm_gen_test_cc(cond
, label_match
);
5381 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5382 gen_set_nzcv(tcg_flags
);
5383 tcg_temp_free_i64(tcg_flags
);
5384 tcg_gen_br(label_continue
);
5385 gen_set_label(label_match
);
5388 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5391 gen_set_label(label_continue
);
5395 /* Floating point conditional select
5396 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5397 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5398 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5399 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5401 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5403 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5404 TCGv_i64 t_true
, t_false
, t_zero
;
5408 mos
= extract32(insn
, 29, 3);
5409 type
= extract32(insn
, 22, 2);
5410 rm
= extract32(insn
, 16, 5);
5411 cond
= extract32(insn
, 12, 4);
5412 rn
= extract32(insn
, 5, 5);
5413 rd
= extract32(insn
, 0, 5);
5416 unallocated_encoding(s
);
5429 if (dc_isar_feature(aa64_fp16
, s
)) {
5434 unallocated_encoding(s
);
5438 if (!fp_access_check(s
)) {
5442 /* Zero extend sreg & hreg inputs to 64 bits now. */
5443 t_true
= tcg_temp_new_i64();
5444 t_false
= tcg_temp_new_i64();
5445 read_vec_element(s
, t_true
, rn
, 0, sz
);
5446 read_vec_element(s
, t_false
, rm
, 0, sz
);
5448 a64_test_cc(&c
, cond
);
5449 t_zero
= tcg_const_i64(0);
5450 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5451 tcg_temp_free_i64(t_zero
);
5452 tcg_temp_free_i64(t_false
);
5455 /* Note that sregs & hregs write back zeros to the high bits,
5456 and we've already done the zero-extension. */
5457 write_fp_dreg(s
, rd
, t_true
);
5458 tcg_temp_free_i64(t_true
);
5461 /* Floating-point data-processing (1 source) - half precision */
5462 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5464 TCGv_ptr fpst
= NULL
;
5465 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5466 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5469 case 0x0: /* FMOV */
5470 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5472 case 0x1: /* FABS */
5473 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5475 case 0x2: /* FNEG */
5476 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5478 case 0x3: /* FSQRT */
5479 fpst
= get_fpstatus_ptr(true);
5480 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5482 case 0x8: /* FRINTN */
5483 case 0x9: /* FRINTP */
5484 case 0xa: /* FRINTM */
5485 case 0xb: /* FRINTZ */
5486 case 0xc: /* FRINTA */
5488 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5489 fpst
= get_fpstatus_ptr(true);
5491 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5492 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5494 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5495 tcg_temp_free_i32(tcg_rmode
);
5498 case 0xe: /* FRINTX */
5499 fpst
= get_fpstatus_ptr(true);
5500 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5502 case 0xf: /* FRINTI */
5503 fpst
= get_fpstatus_ptr(true);
5504 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5510 write_fp_sreg(s
, rd
, tcg_res
);
5513 tcg_temp_free_ptr(fpst
);
5515 tcg_temp_free_i32(tcg_op
);
5516 tcg_temp_free_i32(tcg_res
);
5519 /* Floating-point data-processing (1 source) - single precision */
5520 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5526 fpst
= get_fpstatus_ptr(false);
5527 tcg_op
= read_fp_sreg(s
, rn
);
5528 tcg_res
= tcg_temp_new_i32();
5531 case 0x0: /* FMOV */
5532 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5534 case 0x1: /* FABS */
5535 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5537 case 0x2: /* FNEG */
5538 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5540 case 0x3: /* FSQRT */
5541 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5543 case 0x8: /* FRINTN */
5544 case 0x9: /* FRINTP */
5545 case 0xa: /* FRINTM */
5546 case 0xb: /* FRINTZ */
5547 case 0xc: /* FRINTA */
5549 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5551 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5552 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5554 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5555 tcg_temp_free_i32(tcg_rmode
);
5558 case 0xe: /* FRINTX */
5559 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5561 case 0xf: /* FRINTI */
5562 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5568 write_fp_sreg(s
, rd
, tcg_res
);
5570 tcg_temp_free_ptr(fpst
);
5571 tcg_temp_free_i32(tcg_op
);
5572 tcg_temp_free_i32(tcg_res
);
5575 /* Floating-point data-processing (1 source) - double precision */
5576 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5583 case 0x0: /* FMOV */
5584 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5588 fpst
= get_fpstatus_ptr(false);
5589 tcg_op
= read_fp_dreg(s
, rn
);
5590 tcg_res
= tcg_temp_new_i64();
5593 case 0x1: /* FABS */
5594 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5596 case 0x2: /* FNEG */
5597 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5599 case 0x3: /* FSQRT */
5600 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5602 case 0x8: /* FRINTN */
5603 case 0x9: /* FRINTP */
5604 case 0xa: /* FRINTM */
5605 case 0xb: /* FRINTZ */
5606 case 0xc: /* FRINTA */
5608 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5610 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5611 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5613 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5614 tcg_temp_free_i32(tcg_rmode
);
5617 case 0xe: /* FRINTX */
5618 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5620 case 0xf: /* FRINTI */
5621 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5627 write_fp_dreg(s
, rd
, tcg_res
);
5629 tcg_temp_free_ptr(fpst
);
5630 tcg_temp_free_i64(tcg_op
);
5631 tcg_temp_free_i64(tcg_res
);
5634 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5635 int rd
, int rn
, int dtype
, int ntype
)
5640 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5642 /* Single to double */
5643 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5644 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5645 write_fp_dreg(s
, rd
, tcg_rd
);
5646 tcg_temp_free_i64(tcg_rd
);
5648 /* Single to half */
5649 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5650 TCGv_i32 ahp
= get_ahp_flag();
5651 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5653 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5654 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5655 write_fp_sreg(s
, rd
, tcg_rd
);
5656 tcg_temp_free_i32(tcg_rd
);
5657 tcg_temp_free_i32(ahp
);
5658 tcg_temp_free_ptr(fpst
);
5660 tcg_temp_free_i32(tcg_rn
);
5665 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5666 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5668 /* Double to single */
5669 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5671 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5672 TCGv_i32 ahp
= get_ahp_flag();
5673 /* Double to half */
5674 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5675 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5676 tcg_temp_free_ptr(fpst
);
5677 tcg_temp_free_i32(ahp
);
5679 write_fp_sreg(s
, rd
, tcg_rd
);
5680 tcg_temp_free_i32(tcg_rd
);
5681 tcg_temp_free_i64(tcg_rn
);
5686 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5687 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5688 TCGv_i32 tcg_ahp
= get_ahp_flag();
5689 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5691 /* Half to single */
5692 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5693 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5694 write_fp_sreg(s
, rd
, tcg_rd
);
5695 tcg_temp_free_ptr(tcg_fpst
);
5696 tcg_temp_free_i32(tcg_ahp
);
5697 tcg_temp_free_i32(tcg_rd
);
5699 /* Half to double */
5700 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5701 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5702 write_fp_dreg(s
, rd
, tcg_rd
);
5703 tcg_temp_free_i64(tcg_rd
);
5705 tcg_temp_free_i32(tcg_rn
);
5713 /* Floating point data-processing (1 source)
5714 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5715 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5716 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5717 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5719 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5721 int mos
= extract32(insn
, 29, 3);
5722 int type
= extract32(insn
, 22, 2);
5723 int opcode
= extract32(insn
, 15, 6);
5724 int rn
= extract32(insn
, 5, 5);
5725 int rd
= extract32(insn
, 0, 5);
5728 unallocated_encoding(s
);
5733 case 0x4: case 0x5: case 0x7:
5735 /* FCVT between half, single and double precision */
5736 int dtype
= extract32(opcode
, 0, 2);
5737 if (type
== 2 || dtype
== type
) {
5738 unallocated_encoding(s
);
5741 if (!fp_access_check(s
)) {
5745 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5751 /* 32-to-32 and 64-to-64 ops */
5754 if (!fp_access_check(s
)) {
5758 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5761 if (!fp_access_check(s
)) {
5765 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5768 if (!dc_isar_feature(aa64_fp16
, s
)) {
5769 unallocated_encoding(s
);
5773 if (!fp_access_check(s
)) {
5777 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5780 unallocated_encoding(s
);
5784 unallocated_encoding(s
);
5789 /* Floating-point data-processing (2 source) - single precision */
5790 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5791 int rd
, int rn
, int rm
)
5798 tcg_res
= tcg_temp_new_i32();
5799 fpst
= get_fpstatus_ptr(false);
5800 tcg_op1
= read_fp_sreg(s
, rn
);
5801 tcg_op2
= read_fp_sreg(s
, rm
);
5804 case 0x0: /* FMUL */
5805 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5807 case 0x1: /* FDIV */
5808 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5810 case 0x2: /* FADD */
5811 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5813 case 0x3: /* FSUB */
5814 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5816 case 0x4: /* FMAX */
5817 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5819 case 0x5: /* FMIN */
5820 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5822 case 0x6: /* FMAXNM */
5823 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5825 case 0x7: /* FMINNM */
5826 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5828 case 0x8: /* FNMUL */
5829 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5830 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5834 write_fp_sreg(s
, rd
, tcg_res
);
5836 tcg_temp_free_ptr(fpst
);
5837 tcg_temp_free_i32(tcg_op1
);
5838 tcg_temp_free_i32(tcg_op2
);
5839 tcg_temp_free_i32(tcg_res
);
5842 /* Floating-point data-processing (2 source) - double precision */
5843 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5844 int rd
, int rn
, int rm
)
5851 tcg_res
= tcg_temp_new_i64();
5852 fpst
= get_fpstatus_ptr(false);
5853 tcg_op1
= read_fp_dreg(s
, rn
);
5854 tcg_op2
= read_fp_dreg(s
, rm
);
5857 case 0x0: /* FMUL */
5858 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5860 case 0x1: /* FDIV */
5861 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5863 case 0x2: /* FADD */
5864 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5866 case 0x3: /* FSUB */
5867 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5869 case 0x4: /* FMAX */
5870 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5872 case 0x5: /* FMIN */
5873 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5875 case 0x6: /* FMAXNM */
5876 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5878 case 0x7: /* FMINNM */
5879 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5881 case 0x8: /* FNMUL */
5882 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5883 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5887 write_fp_dreg(s
, rd
, tcg_res
);
5889 tcg_temp_free_ptr(fpst
);
5890 tcg_temp_free_i64(tcg_op1
);
5891 tcg_temp_free_i64(tcg_op2
);
5892 tcg_temp_free_i64(tcg_res
);
5895 /* Floating-point data-processing (2 source) - half precision */
5896 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5897 int rd
, int rn
, int rm
)
5904 tcg_res
= tcg_temp_new_i32();
5905 fpst
= get_fpstatus_ptr(true);
5906 tcg_op1
= read_fp_hreg(s
, rn
);
5907 tcg_op2
= read_fp_hreg(s
, rm
);
5910 case 0x0: /* FMUL */
5911 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5913 case 0x1: /* FDIV */
5914 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5916 case 0x2: /* FADD */
5917 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5919 case 0x3: /* FSUB */
5920 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5922 case 0x4: /* FMAX */
5923 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5925 case 0x5: /* FMIN */
5926 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5928 case 0x6: /* FMAXNM */
5929 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5931 case 0x7: /* FMINNM */
5932 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5934 case 0x8: /* FNMUL */
5935 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5936 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5939 g_assert_not_reached();
5942 write_fp_sreg(s
, rd
, tcg_res
);
5944 tcg_temp_free_ptr(fpst
);
5945 tcg_temp_free_i32(tcg_op1
);
5946 tcg_temp_free_i32(tcg_op2
);
5947 tcg_temp_free_i32(tcg_res
);
5950 /* Floating point data-processing (2 source)
5951 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5952 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5953 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5954 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5956 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5958 int mos
= extract32(insn
, 29, 3);
5959 int type
= extract32(insn
, 22, 2);
5960 int rd
= extract32(insn
, 0, 5);
5961 int rn
= extract32(insn
, 5, 5);
5962 int rm
= extract32(insn
, 16, 5);
5963 int opcode
= extract32(insn
, 12, 4);
5965 if (opcode
> 8 || mos
) {
5966 unallocated_encoding(s
);
5972 if (!fp_access_check(s
)) {
5975 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5978 if (!fp_access_check(s
)) {
5981 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5984 if (!dc_isar_feature(aa64_fp16
, s
)) {
5985 unallocated_encoding(s
);
5988 if (!fp_access_check(s
)) {
5991 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5994 unallocated_encoding(s
);
5998 /* Floating-point data-processing (3 source) - single precision */
5999 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6000 int rd
, int rn
, int rm
, int ra
)
6002 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6003 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6004 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6006 tcg_op1
= read_fp_sreg(s
, rn
);
6007 tcg_op2
= read_fp_sreg(s
, rm
);
6008 tcg_op3
= read_fp_sreg(s
, ra
);
6010 /* These are fused multiply-add, and must be done as one
6011 * floating point operation with no rounding between the
6012 * multiplication and addition steps.
6013 * NB that doing the negations here as separate steps is
6014 * correct : an input NaN should come out with its sign bit
6015 * flipped if it is a negated-input.
6018 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6022 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6025 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6027 write_fp_sreg(s
, rd
, tcg_res
);
6029 tcg_temp_free_ptr(fpst
);
6030 tcg_temp_free_i32(tcg_op1
);
6031 tcg_temp_free_i32(tcg_op2
);
6032 tcg_temp_free_i32(tcg_op3
);
6033 tcg_temp_free_i32(tcg_res
);
6036 /* Floating-point data-processing (3 source) - double precision */
6037 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6038 int rd
, int rn
, int rm
, int ra
)
6040 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6041 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6042 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6044 tcg_op1
= read_fp_dreg(s
, rn
);
6045 tcg_op2
= read_fp_dreg(s
, rm
);
6046 tcg_op3
= read_fp_dreg(s
, ra
);
6048 /* These are fused multiply-add, and must be done as one
6049 * floating point operation with no rounding between the
6050 * multiplication and addition steps.
6051 * NB that doing the negations here as separate steps is
6052 * correct : an input NaN should come out with its sign bit
6053 * flipped if it is a negated-input.
6056 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6060 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6063 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6065 write_fp_dreg(s
, rd
, tcg_res
);
6067 tcg_temp_free_ptr(fpst
);
6068 tcg_temp_free_i64(tcg_op1
);
6069 tcg_temp_free_i64(tcg_op2
);
6070 tcg_temp_free_i64(tcg_op3
);
6071 tcg_temp_free_i64(tcg_res
);
6074 /* Floating-point data-processing (3 source) - half precision */
6075 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6076 int rd
, int rn
, int rm
, int ra
)
6078 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6079 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6080 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6082 tcg_op1
= read_fp_hreg(s
, rn
);
6083 tcg_op2
= read_fp_hreg(s
, rm
);
6084 tcg_op3
= read_fp_hreg(s
, ra
);
6086 /* These are fused multiply-add, and must be done as one
6087 * floating point operation with no rounding between the
6088 * multiplication and addition steps.
6089 * NB that doing the negations here as separate steps is
6090 * correct : an input NaN should come out with its sign bit
6091 * flipped if it is a negated-input.
6094 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6098 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6101 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6103 write_fp_sreg(s
, rd
, tcg_res
);
6105 tcg_temp_free_ptr(fpst
);
6106 tcg_temp_free_i32(tcg_op1
);
6107 tcg_temp_free_i32(tcg_op2
);
6108 tcg_temp_free_i32(tcg_op3
);
6109 tcg_temp_free_i32(tcg_res
);
6112 /* Floating point data-processing (3 source)
6113 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6114 * +---+---+---+-----------+------+----+------+----+------+------+------+
6115 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6116 * +---+---+---+-----------+------+----+------+----+------+------+------+
6118 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6120 int mos
= extract32(insn
, 29, 3);
6121 int type
= extract32(insn
, 22, 2);
6122 int rd
= extract32(insn
, 0, 5);
6123 int rn
= extract32(insn
, 5, 5);
6124 int ra
= extract32(insn
, 10, 5);
6125 int rm
= extract32(insn
, 16, 5);
6126 bool o0
= extract32(insn
, 15, 1);
6127 bool o1
= extract32(insn
, 21, 1);
6130 unallocated_encoding(s
);
6136 if (!fp_access_check(s
)) {
6139 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6142 if (!fp_access_check(s
)) {
6145 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6148 if (!dc_isar_feature(aa64_fp16
, s
)) {
6149 unallocated_encoding(s
);
6152 if (!fp_access_check(s
)) {
6155 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6158 unallocated_encoding(s
);
6162 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
6163 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
6164 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
6166 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
6172 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6173 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
6174 extract32(imm8
, 0, 6);
6178 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6179 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
6180 (extract32(imm8
, 0, 6) << 3);
6184 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6185 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
6186 (extract32(imm8
, 0, 6) << 6);
6189 g_assert_not_reached();
6194 /* Floating point immediate
6195 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6196 * +---+---+---+-----------+------+---+------------+-------+------+------+
6197 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6198 * +---+---+---+-----------+------+---+------------+-------+------+------+
6200 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6202 int rd
= extract32(insn
, 0, 5);
6203 int imm5
= extract32(insn
, 5, 5);
6204 int imm8
= extract32(insn
, 13, 8);
6205 int type
= extract32(insn
, 22, 2);
6206 int mos
= extract32(insn
, 29, 3);
6212 unallocated_encoding(s
);
6225 if (dc_isar_feature(aa64_fp16
, s
)) {
6230 unallocated_encoding(s
);
6234 if (!fp_access_check(s
)) {
6238 imm
= vfp_expand_imm(sz
, imm8
);
6240 tcg_res
= tcg_const_i64(imm
);
6241 write_fp_dreg(s
, rd
, tcg_res
);
6242 tcg_temp_free_i64(tcg_res
);
6245 /* Handle floating point <=> fixed point conversions. Note that we can
6246 * also deal with fp <=> integer conversions as a special case (scale == 64)
6247 * OPTME: consider handling that special case specially or at least skipping
6248 * the call to scalbn in the helpers for zero shifts.
6250 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6251 bool itof
, int rmode
, int scale
, int sf
, int type
)
6253 bool is_signed
= !(opcode
& 1);
6254 TCGv_ptr tcg_fpstatus
;
6255 TCGv_i32 tcg_shift
, tcg_single
;
6256 TCGv_i64 tcg_double
;
6258 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6260 tcg_shift
= tcg_const_i32(64 - scale
);
6263 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6265 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6268 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6270 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6273 tcg_int
= tcg_extend
;
6277 case 1: /* float64 */
6278 tcg_double
= tcg_temp_new_i64();
6280 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6281 tcg_shift
, tcg_fpstatus
);
6283 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6284 tcg_shift
, tcg_fpstatus
);
6286 write_fp_dreg(s
, rd
, tcg_double
);
6287 tcg_temp_free_i64(tcg_double
);
6290 case 0: /* float32 */
6291 tcg_single
= tcg_temp_new_i32();
6293 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6294 tcg_shift
, tcg_fpstatus
);
6296 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6297 tcg_shift
, tcg_fpstatus
);
6299 write_fp_sreg(s
, rd
, tcg_single
);
6300 tcg_temp_free_i32(tcg_single
);
6303 case 3: /* float16 */
6304 tcg_single
= tcg_temp_new_i32();
6306 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6307 tcg_shift
, tcg_fpstatus
);
6309 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6310 tcg_shift
, tcg_fpstatus
);
6312 write_fp_sreg(s
, rd
, tcg_single
);
6313 tcg_temp_free_i32(tcg_single
);
6317 g_assert_not_reached();
6320 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6323 if (extract32(opcode
, 2, 1)) {
6324 /* There are too many rounding modes to all fit into rmode,
6325 * so FCVTA[US] is a special case.
6327 rmode
= FPROUNDING_TIEAWAY
;
6330 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6332 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6335 case 1: /* float64 */
6336 tcg_double
= read_fp_dreg(s
, rn
);
6339 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6340 tcg_shift
, tcg_fpstatus
);
6342 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6343 tcg_shift
, tcg_fpstatus
);
6347 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6348 tcg_shift
, tcg_fpstatus
);
6350 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6351 tcg_shift
, tcg_fpstatus
);
6355 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6357 tcg_temp_free_i64(tcg_double
);
6360 case 0: /* float32 */
6361 tcg_single
= read_fp_sreg(s
, rn
);
6364 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6365 tcg_shift
, tcg_fpstatus
);
6367 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6368 tcg_shift
, tcg_fpstatus
);
6371 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6373 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6374 tcg_shift
, tcg_fpstatus
);
6376 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6377 tcg_shift
, tcg_fpstatus
);
6379 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6380 tcg_temp_free_i32(tcg_dest
);
6382 tcg_temp_free_i32(tcg_single
);
6385 case 3: /* float16 */
6386 tcg_single
= read_fp_sreg(s
, rn
);
6389 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6390 tcg_shift
, tcg_fpstatus
);
6392 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6393 tcg_shift
, tcg_fpstatus
);
6396 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6398 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6399 tcg_shift
, tcg_fpstatus
);
6401 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6402 tcg_shift
, tcg_fpstatus
);
6404 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6405 tcg_temp_free_i32(tcg_dest
);
6407 tcg_temp_free_i32(tcg_single
);
6411 g_assert_not_reached();
6414 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6415 tcg_temp_free_i32(tcg_rmode
);
6418 tcg_temp_free_ptr(tcg_fpstatus
);
6419 tcg_temp_free_i32(tcg_shift
);
6422 /* Floating point <-> fixed point conversions
6423 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6424 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6425 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6426 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6428 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6430 int rd
= extract32(insn
, 0, 5);
6431 int rn
= extract32(insn
, 5, 5);
6432 int scale
= extract32(insn
, 10, 6);
6433 int opcode
= extract32(insn
, 16, 3);
6434 int rmode
= extract32(insn
, 19, 2);
6435 int type
= extract32(insn
, 22, 2);
6436 bool sbit
= extract32(insn
, 29, 1);
6437 bool sf
= extract32(insn
, 31, 1);
6440 if (sbit
|| (!sf
&& scale
< 32)) {
6441 unallocated_encoding(s
);
6446 case 0: /* float32 */
6447 case 1: /* float64 */
6449 case 3: /* float16 */
6450 if (dc_isar_feature(aa64_fp16
, s
)) {
6455 unallocated_encoding(s
);
6459 switch ((rmode
<< 3) | opcode
) {
6460 case 0x2: /* SCVTF */
6461 case 0x3: /* UCVTF */
6464 case 0x18: /* FCVTZS */
6465 case 0x19: /* FCVTZU */
6469 unallocated_encoding(s
);
6473 if (!fp_access_check(s
)) {
6477 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6480 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6482 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6483 * without conversion.
6487 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6493 tmp
= tcg_temp_new_i64();
6494 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6495 write_fp_dreg(s
, rd
, tmp
);
6496 tcg_temp_free_i64(tmp
);
6500 write_fp_dreg(s
, rd
, tcg_rn
);
6503 /* 64 bit to top half. */
6504 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6505 clear_vec_high(s
, true, rd
);
6509 tmp
= tcg_temp_new_i64();
6510 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6511 write_fp_dreg(s
, rd
, tmp
);
6512 tcg_temp_free_i64(tmp
);
6515 g_assert_not_reached();
6518 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6523 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6527 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6530 /* 64 bits from top half */
6531 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6535 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6538 g_assert_not_reached();
6543 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6545 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6546 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6548 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6550 tcg_temp_free_ptr(fpstatus
);
6552 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6553 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6554 tcg_gen_movi_i32(cpu_CF
, 0);
6555 tcg_gen_movi_i32(cpu_NF
, 0);
6556 tcg_gen_movi_i32(cpu_VF
, 0);
6558 tcg_temp_free_i64(t
);
6561 /* Floating point <-> integer conversions
6562 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6563 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6564 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6565 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6567 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6569 int rd
= extract32(insn
, 0, 5);
6570 int rn
= extract32(insn
, 5, 5);
6571 int opcode
= extract32(insn
, 16, 3);
6572 int rmode
= extract32(insn
, 19, 2);
6573 int type
= extract32(insn
, 22, 2);
6574 bool sbit
= extract32(insn
, 29, 1);
6575 bool sf
= extract32(insn
, 31, 1);
6579 goto do_unallocated
;
6587 case 4: /* FCVTAS */
6588 case 5: /* FCVTAU */
6590 goto do_unallocated
;
6593 case 0: /* FCVT[NPMZ]S */
6594 case 1: /* FCVT[NPMZ]U */
6596 case 0: /* float32 */
6597 case 1: /* float64 */
6599 case 3: /* float16 */
6600 if (!dc_isar_feature(aa64_fp16
, s
)) {
6601 goto do_unallocated
;
6605 goto do_unallocated
;
6607 if (!fp_access_check(s
)) {
6610 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6614 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6615 case 0b01100110: /* FMOV half <-> 32-bit int */
6617 case 0b11100110: /* FMOV half <-> 64-bit int */
6619 if (!dc_isar_feature(aa64_fp16
, s
)) {
6620 goto do_unallocated
;
6623 case 0b00000110: /* FMOV 32-bit */
6625 case 0b10100110: /* FMOV 64-bit */
6627 case 0b11001110: /* FMOV top half of 128-bit */
6629 if (!fp_access_check(s
)) {
6633 handle_fmov(s
, rd
, rn
, type
, itof
);
6636 case 0b00111110: /* FJCVTZS */
6637 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6638 goto do_unallocated
;
6639 } else if (fp_access_check(s
)) {
6640 handle_fjcvtzs(s
, rd
, rn
);
6646 unallocated_encoding(s
);
6653 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6654 * 31 30 29 28 25 24 0
6655 * +---+---+---+---------+-----------------------------+
6656 * | | 0 | | 1 1 1 1 | |
6657 * +---+---+---+---------+-----------------------------+
6659 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6661 if (extract32(insn
, 24, 1)) {
6662 /* Floating point data-processing (3 source) */
6663 disas_fp_3src(s
, insn
);
6664 } else if (extract32(insn
, 21, 1) == 0) {
6665 /* Floating point to fixed point conversions */
6666 disas_fp_fixed_conv(s
, insn
);
6668 switch (extract32(insn
, 10, 2)) {
6670 /* Floating point conditional compare */
6671 disas_fp_ccomp(s
, insn
);
6674 /* Floating point data-processing (2 source) */
6675 disas_fp_2src(s
, insn
);
6678 /* Floating point conditional select */
6679 disas_fp_csel(s
, insn
);
6682 switch (ctz32(extract32(insn
, 12, 4))) {
6683 case 0: /* [15:12] == xxx1 */
6684 /* Floating point immediate */
6685 disas_fp_imm(s
, insn
);
6687 case 1: /* [15:12] == xx10 */
6688 /* Floating point compare */
6689 disas_fp_compare(s
, insn
);
6691 case 2: /* [15:12] == x100 */
6692 /* Floating point data-processing (1 source) */
6693 disas_fp_1src(s
, insn
);
6695 case 3: /* [15:12] == 1000 */
6696 unallocated_encoding(s
);
6698 default: /* [15:12] == 0000 */
6699 /* Floating point <-> integer conversions */
6700 disas_fp_int_conv(s
, insn
);
6708 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6711 /* Extract 64 bits from the middle of two concatenated 64 bit
6712 * vector register slices left:right. The extracted bits start
6713 * at 'pos' bits into the right (least significant) side.
6714 * We return the result in tcg_right, and guarantee not to
6717 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6718 assert(pos
> 0 && pos
< 64);
6720 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6721 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6722 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6724 tcg_temp_free_i64(tcg_tmp
);
6728 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6729 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6730 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6731 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6733 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6735 int is_q
= extract32(insn
, 30, 1);
6736 int op2
= extract32(insn
, 22, 2);
6737 int imm4
= extract32(insn
, 11, 4);
6738 int rm
= extract32(insn
, 16, 5);
6739 int rn
= extract32(insn
, 5, 5);
6740 int rd
= extract32(insn
, 0, 5);
6741 int pos
= imm4
<< 3;
6742 TCGv_i64 tcg_resl
, tcg_resh
;
6744 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6745 unallocated_encoding(s
);
6749 if (!fp_access_check(s
)) {
6753 tcg_resh
= tcg_temp_new_i64();
6754 tcg_resl
= tcg_temp_new_i64();
6756 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6757 * either extracting 128 bits from a 128:128 concatenation, or
6758 * extracting 64 bits from a 64:64 concatenation.
6761 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6763 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6764 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6766 tcg_gen_movi_i64(tcg_resh
, 0);
6773 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6774 EltPosns
*elt
= eltposns
;
6781 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6783 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6786 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6787 tcg_hh
= tcg_temp_new_i64();
6788 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6789 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6790 tcg_temp_free_i64(tcg_hh
);
6794 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6795 tcg_temp_free_i64(tcg_resl
);
6796 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6797 tcg_temp_free_i64(tcg_resh
);
6801 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6802 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6803 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6804 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6806 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6808 int op2
= extract32(insn
, 22, 2);
6809 int is_q
= extract32(insn
, 30, 1);
6810 int rm
= extract32(insn
, 16, 5);
6811 int rn
= extract32(insn
, 5, 5);
6812 int rd
= extract32(insn
, 0, 5);
6813 int is_tblx
= extract32(insn
, 12, 1);
6814 int len
= extract32(insn
, 13, 2);
6815 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6816 TCGv_i32 tcg_regno
, tcg_numregs
;
6819 unallocated_encoding(s
);
6823 if (!fp_access_check(s
)) {
6827 /* This does a table lookup: for every byte element in the input
6828 * we index into a table formed from up to four vector registers,
6829 * and then the output is the result of the lookups. Our helper
6830 * function does the lookup operation for a single 64 bit part of
6833 tcg_resl
= tcg_temp_new_i64();
6834 tcg_resh
= tcg_temp_new_i64();
6837 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6839 tcg_gen_movi_i64(tcg_resl
, 0);
6841 if (is_tblx
&& is_q
) {
6842 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6844 tcg_gen_movi_i64(tcg_resh
, 0);
6847 tcg_idx
= tcg_temp_new_i64();
6848 tcg_regno
= tcg_const_i32(rn
);
6849 tcg_numregs
= tcg_const_i32(len
+ 1);
6850 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6851 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6852 tcg_regno
, tcg_numregs
);
6854 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6855 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6856 tcg_regno
, tcg_numregs
);
6858 tcg_temp_free_i64(tcg_idx
);
6859 tcg_temp_free_i32(tcg_regno
);
6860 tcg_temp_free_i32(tcg_numregs
);
6862 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6863 tcg_temp_free_i64(tcg_resl
);
6864 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6865 tcg_temp_free_i64(tcg_resh
);
6869 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6870 * +---+---+-------------+------+---+------+---+------------------+------+
6871 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6872 * +---+---+-------------+------+---+------+---+------------------+------+
6874 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6876 int rd
= extract32(insn
, 0, 5);
6877 int rn
= extract32(insn
, 5, 5);
6878 int rm
= extract32(insn
, 16, 5);
6879 int size
= extract32(insn
, 22, 2);
6880 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6881 * bit 2 indicates 1 vs 2 variant of the insn.
6883 int opcode
= extract32(insn
, 12, 2);
6884 bool part
= extract32(insn
, 14, 1);
6885 bool is_q
= extract32(insn
, 30, 1);
6886 int esize
= 8 << size
;
6888 int datasize
= is_q
? 128 : 64;
6889 int elements
= datasize
/ esize
;
6890 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6892 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6893 unallocated_encoding(s
);
6897 if (!fp_access_check(s
)) {
6901 tcg_resl
= tcg_const_i64(0);
6902 tcg_resh
= tcg_const_i64(0);
6903 tcg_res
= tcg_temp_new_i64();
6905 for (i
= 0; i
< elements
; i
++) {
6907 case 1: /* UZP1/2 */
6909 int midpoint
= elements
/ 2;
6911 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6913 read_vec_element(s
, tcg_res
, rm
,
6914 2 * (i
- midpoint
) + part
, size
);
6918 case 2: /* TRN1/2 */
6920 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6922 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6925 case 3: /* ZIP1/2 */
6927 int base
= part
* elements
/ 2;
6929 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6931 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6936 g_assert_not_reached();
6941 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6942 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6944 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6945 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6949 tcg_temp_free_i64(tcg_res
);
6951 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6952 tcg_temp_free_i64(tcg_resl
);
6953 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6954 tcg_temp_free_i64(tcg_resh
);
6958 * do_reduction_op helper
6960 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6961 * important for correct NaN propagation that we do these
6962 * operations in exactly the order specified by the pseudocode.
6964 * This is a recursive function, TCG temps should be freed by the
6965 * calling function once it is done with the values.
6967 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6968 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6970 if (esize
== size
) {
6972 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6975 /* We should have one register left here */
6976 assert(ctpop8(vmap
) == 1);
6977 element
= ctz32(vmap
);
6978 assert(element
< 8);
6980 tcg_elem
= tcg_temp_new_i32();
6981 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6984 int bits
= size
/ 2;
6985 int shift
= ctpop8(vmap
) / 2;
6986 int vmap_lo
= (vmap
>> shift
) & vmap
;
6987 int vmap_hi
= (vmap
& ~vmap_lo
);
6988 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6990 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6991 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6992 tcg_res
= tcg_temp_new_i32();
6995 case 0x0c: /* fmaxnmv half-precision */
6996 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6998 case 0x0f: /* fmaxv half-precision */
6999 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7001 case 0x1c: /* fminnmv half-precision */
7002 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7004 case 0x1f: /* fminv half-precision */
7005 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7007 case 0x2c: /* fmaxnmv */
7008 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7010 case 0x2f: /* fmaxv */
7011 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7013 case 0x3c: /* fminnmv */
7014 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7016 case 0x3f: /* fminv */
7017 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7020 g_assert_not_reached();
7023 tcg_temp_free_i32(tcg_hi
);
7024 tcg_temp_free_i32(tcg_lo
);
7029 /* AdvSIMD across lanes
7030 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7031 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7032 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7033 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7035 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7037 int rd
= extract32(insn
, 0, 5);
7038 int rn
= extract32(insn
, 5, 5);
7039 int size
= extract32(insn
, 22, 2);
7040 int opcode
= extract32(insn
, 12, 5);
7041 bool is_q
= extract32(insn
, 30, 1);
7042 bool is_u
= extract32(insn
, 29, 1);
7044 bool is_min
= false;
7048 TCGv_i64 tcg_res
, tcg_elt
;
7051 case 0x1b: /* ADDV */
7053 unallocated_encoding(s
);
7057 case 0x3: /* SADDLV, UADDLV */
7058 case 0xa: /* SMAXV, UMAXV */
7059 case 0x1a: /* SMINV, UMINV */
7060 if (size
== 3 || (size
== 2 && !is_q
)) {
7061 unallocated_encoding(s
);
7065 case 0xc: /* FMAXNMV, FMINNMV */
7066 case 0xf: /* FMAXV, FMINV */
7067 /* Bit 1 of size field encodes min vs max and the actual size
7068 * depends on the encoding of the U bit. If not set (and FP16
7069 * enabled) then we do half-precision float instead of single
7072 is_min
= extract32(size
, 1, 1);
7074 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7076 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7077 unallocated_encoding(s
);
7084 unallocated_encoding(s
);
7088 if (!fp_access_check(s
)) {
7093 elements
= (is_q
? 128 : 64) / esize
;
7095 tcg_res
= tcg_temp_new_i64();
7096 tcg_elt
= tcg_temp_new_i64();
7098 /* These instructions operate across all lanes of a vector
7099 * to produce a single result. We can guarantee that a 64
7100 * bit intermediate is sufficient:
7101 * + for [US]ADDLV the maximum element size is 32 bits, and
7102 * the result type is 64 bits
7103 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7104 * same as the element size, which is 32 bits at most
7105 * For the integer operations we can choose to work at 64
7106 * or 32 bits and truncate at the end; for simplicity
7107 * we use 64 bits always. The floating point
7108 * ops do require 32 bit intermediates, though.
7111 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7113 for (i
= 1; i
< elements
; i
++) {
7114 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7117 case 0x03: /* SADDLV / UADDLV */
7118 case 0x1b: /* ADDV */
7119 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7121 case 0x0a: /* SMAXV / UMAXV */
7123 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7125 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7128 case 0x1a: /* SMINV / UMINV */
7130 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7132 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7136 g_assert_not_reached();
7141 /* Floating point vector reduction ops which work across 32
7142 * bit (single) or 16 bit (half-precision) intermediates.
7143 * Note that correct NaN propagation requires that we do these
7144 * operations in exactly the order specified by the pseudocode.
7146 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7147 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7148 int vmap
= (1 << elements
) - 1;
7149 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7150 (is_q
? 128 : 64), vmap
, fpst
);
7151 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7152 tcg_temp_free_i32(tcg_res32
);
7153 tcg_temp_free_ptr(fpst
);
7156 tcg_temp_free_i64(tcg_elt
);
7158 /* Now truncate the result to the width required for the final output */
7159 if (opcode
== 0x03) {
7160 /* SADDLV, UADDLV: result is 2*esize */
7166 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7169 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7172 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7177 g_assert_not_reached();
7180 write_fp_dreg(s
, rd
, tcg_res
);
7181 tcg_temp_free_i64(tcg_res
);
7184 /* DUP (Element, Vector)
7186 * 31 30 29 21 20 16 15 10 9 5 4 0
7187 * +---+---+-------------------+--------+-------------+------+------+
7188 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7189 * +---+---+-------------------+--------+-------------+------+------+
7191 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7193 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7196 int size
= ctz32(imm5
);
7197 int index
= imm5
>> (size
+ 1);
7199 if (size
> 3 || (size
== 3 && !is_q
)) {
7200 unallocated_encoding(s
);
7204 if (!fp_access_check(s
)) {
7208 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7209 vec_reg_offset(s
, rn
, index
, size
),
7210 is_q
? 16 : 8, vec_full_reg_size(s
));
7213 /* DUP (element, scalar)
7214 * 31 21 20 16 15 10 9 5 4 0
7215 * +-----------------------+--------+-------------+------+------+
7216 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7217 * +-----------------------+--------+-------------+------+------+
7219 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7222 int size
= ctz32(imm5
);
7227 unallocated_encoding(s
);
7231 if (!fp_access_check(s
)) {
7235 index
= imm5
>> (size
+ 1);
7237 /* This instruction just extracts the specified element and
7238 * zero-extends it into the bottom of the destination register.
7240 tmp
= tcg_temp_new_i64();
7241 read_vec_element(s
, tmp
, rn
, index
, size
);
7242 write_fp_dreg(s
, rd
, tmp
);
7243 tcg_temp_free_i64(tmp
);
7248 * 31 30 29 21 20 16 15 10 9 5 4 0
7249 * +---+---+-------------------+--------+-------------+------+------+
7250 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7251 * +---+---+-------------------+--------+-------------+------+------+
7253 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7255 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7258 int size
= ctz32(imm5
);
7259 uint32_t dofs
, oprsz
, maxsz
;
7261 if (size
> 3 || ((size
== 3) && !is_q
)) {
7262 unallocated_encoding(s
);
7266 if (!fp_access_check(s
)) {
7270 dofs
= vec_full_reg_offset(s
, rd
);
7271 oprsz
= is_q
? 16 : 8;
7272 maxsz
= vec_full_reg_size(s
);
7274 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7279 * 31 21 20 16 15 14 11 10 9 5 4 0
7280 * +-----------------------+--------+------------+---+------+------+
7281 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7282 * +-----------------------+--------+------------+---+------+------+
7284 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7285 * index: encoded in imm5<4:size+1>
7287 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7290 int size
= ctz32(imm5
);
7291 int src_index
, dst_index
;
7295 unallocated_encoding(s
);
7299 if (!fp_access_check(s
)) {
7303 dst_index
= extract32(imm5
, 1+size
, 5);
7304 src_index
= extract32(imm4
, size
, 4);
7306 tmp
= tcg_temp_new_i64();
7308 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7309 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7311 tcg_temp_free_i64(tmp
);
7317 * 31 21 20 16 15 10 9 5 4 0
7318 * +-----------------------+--------+-------------+------+------+
7319 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7320 * +-----------------------+--------+-------------+------+------+
7322 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7323 * index: encoded in imm5<4:size+1>
7325 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7327 int size
= ctz32(imm5
);
7331 unallocated_encoding(s
);
7335 if (!fp_access_check(s
)) {
7339 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7340 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7347 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7348 * +---+---+-------------------+--------+-------------+------+------+
7349 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7350 * +---+---+-------------------+--------+-------------+------+------+
7352 * U: unsigned when set
7353 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7355 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7356 int rn
, int rd
, int imm5
)
7358 int size
= ctz32(imm5
);
7362 /* Check for UnallocatedEncodings */
7364 if (size
> 2 || (size
== 2 && !is_q
)) {
7365 unallocated_encoding(s
);
7370 || (size
< 3 && is_q
)
7371 || (size
== 3 && !is_q
)) {
7372 unallocated_encoding(s
);
7377 if (!fp_access_check(s
)) {
7381 element
= extract32(imm5
, 1+size
, 4);
7383 tcg_rd
= cpu_reg(s
, rd
);
7384 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7385 if (is_signed
&& !is_q
) {
7386 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7391 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7392 * +---+---+----+-----------------+------+---+------+---+------+------+
7393 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7394 * +---+---+----+-----------------+------+---+------+---+------+------+
7396 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7398 int rd
= extract32(insn
, 0, 5);
7399 int rn
= extract32(insn
, 5, 5);
7400 int imm4
= extract32(insn
, 11, 4);
7401 int op
= extract32(insn
, 29, 1);
7402 int is_q
= extract32(insn
, 30, 1);
7403 int imm5
= extract32(insn
, 16, 5);
7408 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7410 unallocated_encoding(s
);
7415 /* DUP (element - vector) */
7416 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7420 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7425 handle_simd_insg(s
, rd
, rn
, imm5
);
7427 unallocated_encoding(s
);
7432 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7433 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7436 unallocated_encoding(s
);
7442 /* AdvSIMD modified immediate
7443 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7444 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7445 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7446 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7448 * There are a number of operations that can be carried out here:
7449 * MOVI - move (shifted) imm into register
7450 * MVNI - move inverted (shifted) imm into register
7451 * ORR - bitwise OR of (shifted) imm with register
7452 * BIC - bitwise clear of (shifted) imm with register
7453 * With ARMv8.2 we also have:
7454 * FMOV half-precision
7456 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7458 int rd
= extract32(insn
, 0, 5);
7459 int cmode
= extract32(insn
, 12, 4);
7460 int cmode_3_1
= extract32(cmode
, 1, 3);
7461 int cmode_0
= extract32(cmode
, 0, 1);
7462 int o2
= extract32(insn
, 11, 1);
7463 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7464 bool is_neg
= extract32(insn
, 29, 1);
7465 bool is_q
= extract32(insn
, 30, 1);
7468 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7469 /* Check for FMOV (vector, immediate) - half-precision */
7470 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7471 unallocated_encoding(s
);
7476 if (!fp_access_check(s
)) {
7480 /* See AdvSIMDExpandImm() in ARM ARM */
7481 switch (cmode_3_1
) {
7482 case 0: /* Replicate(Zeros(24):imm8, 2) */
7483 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7484 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7485 case 3: /* Replicate(imm8:Zeros(24), 2) */
7487 int shift
= cmode_3_1
* 8;
7488 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7491 case 4: /* Replicate(Zeros(8):imm8, 4) */
7492 case 5: /* Replicate(imm8:Zeros(8), 4) */
7494 int shift
= (cmode_3_1
& 0x1) * 8;
7495 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7500 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7501 imm
= (abcdefgh
<< 16) | 0xffff;
7503 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7504 imm
= (abcdefgh
<< 8) | 0xff;
7506 imm
= bitfield_replicate(imm
, 32);
7509 if (!cmode_0
&& !is_neg
) {
7510 imm
= bitfield_replicate(abcdefgh
, 8);
7511 } else if (!cmode_0
&& is_neg
) {
7514 for (i
= 0; i
< 8; i
++) {
7515 if ((abcdefgh
) & (1 << i
)) {
7516 imm
|= 0xffULL
<< (i
* 8);
7519 } else if (cmode_0
) {
7521 imm
= (abcdefgh
& 0x3f) << 48;
7522 if (abcdefgh
& 0x80) {
7523 imm
|= 0x8000000000000000ULL
;
7525 if (abcdefgh
& 0x40) {
7526 imm
|= 0x3fc0000000000000ULL
;
7528 imm
|= 0x4000000000000000ULL
;
7532 /* FMOV (vector, immediate) - half-precision */
7533 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7534 /* now duplicate across the lanes */
7535 imm
= bitfield_replicate(imm
, 16);
7537 imm
= (abcdefgh
& 0x3f) << 19;
7538 if (abcdefgh
& 0x80) {
7541 if (abcdefgh
& 0x40) {
7552 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7553 g_assert_not_reached();
7556 if (cmode_3_1
!= 7 && is_neg
) {
7560 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7561 /* MOVI or MVNI, with MVNI negation handled above. */
7562 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7563 vec_full_reg_size(s
), imm
);
7565 /* ORR or BIC, with BIC negation to AND handled above. */
7567 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7569 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7574 /* AdvSIMD scalar copy
7575 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7576 * +-----+----+-----------------+------+---+------+---+------+------+
7577 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7578 * +-----+----+-----------------+------+---+------+---+------+------+
7580 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7582 int rd
= extract32(insn
, 0, 5);
7583 int rn
= extract32(insn
, 5, 5);
7584 int imm4
= extract32(insn
, 11, 4);
7585 int imm5
= extract32(insn
, 16, 5);
7586 int op
= extract32(insn
, 29, 1);
7588 if (op
!= 0 || imm4
!= 0) {
7589 unallocated_encoding(s
);
7593 /* DUP (element, scalar) */
7594 handle_simd_dupes(s
, rd
, rn
, imm5
);
7597 /* AdvSIMD scalar pairwise
7598 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7599 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7600 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7601 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7603 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7605 int u
= extract32(insn
, 29, 1);
7606 int size
= extract32(insn
, 22, 2);
7607 int opcode
= extract32(insn
, 12, 5);
7608 int rn
= extract32(insn
, 5, 5);
7609 int rd
= extract32(insn
, 0, 5);
7612 /* For some ops (the FP ones), size[1] is part of the encoding.
7613 * For ADDP strictly it is not but size[1] is always 1 for valid
7616 opcode
|= (extract32(size
, 1, 1) << 5);
7619 case 0x3b: /* ADDP */
7620 if (u
|| size
!= 3) {
7621 unallocated_encoding(s
);
7624 if (!fp_access_check(s
)) {
7630 case 0xc: /* FMAXNMP */
7631 case 0xd: /* FADDP */
7632 case 0xf: /* FMAXP */
7633 case 0x2c: /* FMINNMP */
7634 case 0x2f: /* FMINP */
7635 /* FP op, size[0] is 32 or 64 bit*/
7637 if (!dc_isar_feature(aa64_fp16
, s
)) {
7638 unallocated_encoding(s
);
7644 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7647 if (!fp_access_check(s
)) {
7651 fpst
= get_fpstatus_ptr(size
== MO_16
);
7654 unallocated_encoding(s
);
7658 if (size
== MO_64
) {
7659 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7660 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7661 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7663 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7664 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7667 case 0x3b: /* ADDP */
7668 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7670 case 0xc: /* FMAXNMP */
7671 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7673 case 0xd: /* FADDP */
7674 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7676 case 0xf: /* FMAXP */
7677 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7679 case 0x2c: /* FMINNMP */
7680 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7682 case 0x2f: /* FMINP */
7683 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7686 g_assert_not_reached();
7689 write_fp_dreg(s
, rd
, tcg_res
);
7691 tcg_temp_free_i64(tcg_op1
);
7692 tcg_temp_free_i64(tcg_op2
);
7693 tcg_temp_free_i64(tcg_res
);
7695 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7696 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7697 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7699 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7700 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7702 if (size
== MO_16
) {
7704 case 0xc: /* FMAXNMP */
7705 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7707 case 0xd: /* FADDP */
7708 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7710 case 0xf: /* FMAXP */
7711 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7713 case 0x2c: /* FMINNMP */
7714 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7716 case 0x2f: /* FMINP */
7717 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7720 g_assert_not_reached();
7724 case 0xc: /* FMAXNMP */
7725 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7727 case 0xd: /* FADDP */
7728 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7730 case 0xf: /* FMAXP */
7731 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7733 case 0x2c: /* FMINNMP */
7734 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7736 case 0x2f: /* FMINP */
7737 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7740 g_assert_not_reached();
7744 write_fp_sreg(s
, rd
, tcg_res
);
7746 tcg_temp_free_i32(tcg_op1
);
7747 tcg_temp_free_i32(tcg_op2
);
7748 tcg_temp_free_i32(tcg_res
);
7752 tcg_temp_free_ptr(fpst
);
7757 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7759 * This code is handles the common shifting code and is used by both
7760 * the vector and scalar code.
7762 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7763 TCGv_i64 tcg_rnd
, bool accumulate
,
7764 bool is_u
, int size
, int shift
)
7766 bool extended_result
= false;
7767 bool round
= tcg_rnd
!= NULL
;
7769 TCGv_i64 tcg_src_hi
;
7771 if (round
&& size
== 3) {
7772 extended_result
= true;
7773 ext_lshift
= 64 - shift
;
7774 tcg_src_hi
= tcg_temp_new_i64();
7775 } else if (shift
== 64) {
7776 if (!accumulate
&& is_u
) {
7777 /* result is zero */
7778 tcg_gen_movi_i64(tcg_res
, 0);
7783 /* Deal with the rounding step */
7785 if (extended_result
) {
7786 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7788 /* take care of sign extending tcg_res */
7789 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7790 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7791 tcg_src
, tcg_src_hi
,
7794 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7798 tcg_temp_free_i64(tcg_zero
);
7800 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7804 /* Now do the shift right */
7805 if (round
&& extended_result
) {
7806 /* extended case, >64 bit precision required */
7807 if (ext_lshift
== 0) {
7808 /* special case, only high bits matter */
7809 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7811 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7812 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7813 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7818 /* essentially shifting in 64 zeros */
7819 tcg_gen_movi_i64(tcg_src
, 0);
7821 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7825 /* effectively extending the sign-bit */
7826 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7828 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7834 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7836 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7839 if (extended_result
) {
7840 tcg_temp_free_i64(tcg_src_hi
);
7844 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7845 static void handle_scalar_simd_shri(DisasContext
*s
,
7846 bool is_u
, int immh
, int immb
,
7847 int opcode
, int rn
, int rd
)
7850 int immhb
= immh
<< 3 | immb
;
7851 int shift
= 2 * (8 << size
) - immhb
;
7852 bool accumulate
= false;
7854 bool insert
= false;
7859 if (!extract32(immh
, 3, 1)) {
7860 unallocated_encoding(s
);
7864 if (!fp_access_check(s
)) {
7869 case 0x02: /* SSRA / USRA (accumulate) */
7872 case 0x04: /* SRSHR / URSHR (rounding) */
7875 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7876 accumulate
= round
= true;
7878 case 0x08: /* SRI */
7884 uint64_t round_const
= 1ULL << (shift
- 1);
7885 tcg_round
= tcg_const_i64(round_const
);
7890 tcg_rn
= read_fp_dreg(s
, rn
);
7891 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7894 /* shift count same as element size is valid but does nothing;
7895 * special case to avoid potential shift by 64.
7897 int esize
= 8 << size
;
7898 if (shift
!= esize
) {
7899 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7900 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7903 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7904 accumulate
, is_u
, size
, shift
);
7907 write_fp_dreg(s
, rd
, tcg_rd
);
7909 tcg_temp_free_i64(tcg_rn
);
7910 tcg_temp_free_i64(tcg_rd
);
7912 tcg_temp_free_i64(tcg_round
);
7916 /* SHL/SLI - Scalar shift left */
7917 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7918 int immh
, int immb
, int opcode
,
7921 int size
= 32 - clz32(immh
) - 1;
7922 int immhb
= immh
<< 3 | immb
;
7923 int shift
= immhb
- (8 << size
);
7924 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7925 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7927 if (!extract32(immh
, 3, 1)) {
7928 unallocated_encoding(s
);
7932 if (!fp_access_check(s
)) {
7936 tcg_rn
= read_fp_dreg(s
, rn
);
7937 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7940 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7942 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7945 write_fp_dreg(s
, rd
, tcg_rd
);
7947 tcg_temp_free_i64(tcg_rn
);
7948 tcg_temp_free_i64(tcg_rd
);
7951 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7952 * (signed/unsigned) narrowing */
7953 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7954 bool is_u_shift
, bool is_u_narrow
,
7955 int immh
, int immb
, int opcode
,
7958 int immhb
= immh
<< 3 | immb
;
7959 int size
= 32 - clz32(immh
) - 1;
7960 int esize
= 8 << size
;
7961 int shift
= (2 * esize
) - immhb
;
7962 int elements
= is_scalar
? 1 : (64 / esize
);
7963 bool round
= extract32(opcode
, 0, 1);
7964 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7965 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7966 TCGv_i32 tcg_rd_narrowed
;
7969 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7970 { gen_helper_neon_narrow_sat_s8
,
7971 gen_helper_neon_unarrow_sat8
},
7972 { gen_helper_neon_narrow_sat_s16
,
7973 gen_helper_neon_unarrow_sat16
},
7974 { gen_helper_neon_narrow_sat_s32
,
7975 gen_helper_neon_unarrow_sat32
},
7978 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7979 gen_helper_neon_narrow_sat_u8
,
7980 gen_helper_neon_narrow_sat_u16
,
7981 gen_helper_neon_narrow_sat_u32
,
7984 NeonGenNarrowEnvFn
*narrowfn
;
7990 if (extract32(immh
, 3, 1)) {
7991 unallocated_encoding(s
);
7995 if (!fp_access_check(s
)) {
8000 narrowfn
= unsigned_narrow_fns
[size
];
8002 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8005 tcg_rn
= tcg_temp_new_i64();
8006 tcg_rd
= tcg_temp_new_i64();
8007 tcg_rd_narrowed
= tcg_temp_new_i32();
8008 tcg_final
= tcg_const_i64(0);
8011 uint64_t round_const
= 1ULL << (shift
- 1);
8012 tcg_round
= tcg_const_i64(round_const
);
8017 for (i
= 0; i
< elements
; i
++) {
8018 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8019 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8020 false, is_u_shift
, size
+1, shift
);
8021 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8022 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8023 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8027 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8029 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8033 tcg_temp_free_i64(tcg_round
);
8035 tcg_temp_free_i64(tcg_rn
);
8036 tcg_temp_free_i64(tcg_rd
);
8037 tcg_temp_free_i32(tcg_rd_narrowed
);
8038 tcg_temp_free_i64(tcg_final
);
8040 clear_vec_high(s
, is_q
, rd
);
8043 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8044 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8045 bool src_unsigned
, bool dst_unsigned
,
8046 int immh
, int immb
, int rn
, int rd
)
8048 int immhb
= immh
<< 3 | immb
;
8049 int size
= 32 - clz32(immh
) - 1;
8050 int shift
= immhb
- (8 << size
);
8054 assert(!(scalar
&& is_q
));
8057 if (!is_q
&& extract32(immh
, 3, 1)) {
8058 unallocated_encoding(s
);
8062 /* Since we use the variable-shift helpers we must
8063 * replicate the shift count into each element of
8064 * the tcg_shift value.
8068 shift
|= shift
<< 8;
8071 shift
|= shift
<< 16;
8077 g_assert_not_reached();
8081 if (!fp_access_check(s
)) {
8086 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8087 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8088 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8089 { NULL
, gen_helper_neon_qshl_u64
},
8091 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8092 int maxpass
= is_q
? 2 : 1;
8094 for (pass
= 0; pass
< maxpass
; pass
++) {
8095 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8097 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8098 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8099 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8101 tcg_temp_free_i64(tcg_op
);
8103 tcg_temp_free_i64(tcg_shift
);
8104 clear_vec_high(s
, is_q
, rd
);
8106 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8107 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8109 { gen_helper_neon_qshl_s8
,
8110 gen_helper_neon_qshl_s16
,
8111 gen_helper_neon_qshl_s32
},
8112 { gen_helper_neon_qshlu_s8
,
8113 gen_helper_neon_qshlu_s16
,
8114 gen_helper_neon_qshlu_s32
}
8116 { NULL
, NULL
, NULL
},
8117 { gen_helper_neon_qshl_u8
,
8118 gen_helper_neon_qshl_u16
,
8119 gen_helper_neon_qshl_u32
}
8122 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8123 TCGMemOp memop
= scalar
? size
: MO_32
;
8124 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8126 for (pass
= 0; pass
< maxpass
; pass
++) {
8127 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8129 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8130 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8134 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8137 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8142 g_assert_not_reached();
8144 write_fp_sreg(s
, rd
, tcg_op
);
8146 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8149 tcg_temp_free_i32(tcg_op
);
8151 tcg_temp_free_i32(tcg_shift
);
8154 clear_vec_high(s
, is_q
, rd
);
8159 /* Common vector code for handling integer to FP conversion */
8160 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8161 int elements
, int is_signed
,
8162 int fracbits
, int size
)
8164 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8165 TCGv_i32 tcg_shift
= NULL
;
8167 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8170 if (fracbits
|| size
== MO_64
) {
8171 tcg_shift
= tcg_const_i32(fracbits
);
8174 if (size
== MO_64
) {
8175 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8176 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8178 for (pass
= 0; pass
< elements
; pass
++) {
8179 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8182 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8183 tcg_shift
, tcg_fpst
);
8185 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8186 tcg_shift
, tcg_fpst
);
8188 if (elements
== 1) {
8189 write_fp_dreg(s
, rd
, tcg_double
);
8191 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8195 tcg_temp_free_i64(tcg_int64
);
8196 tcg_temp_free_i64(tcg_double
);
8199 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8200 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8202 for (pass
= 0; pass
< elements
; pass
++) {
8203 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8209 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8210 tcg_shift
, tcg_fpst
);
8212 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8213 tcg_shift
, tcg_fpst
);
8217 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8219 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8226 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8227 tcg_shift
, tcg_fpst
);
8229 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8230 tcg_shift
, tcg_fpst
);
8234 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8236 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8241 g_assert_not_reached();
8244 if (elements
== 1) {
8245 write_fp_sreg(s
, rd
, tcg_float
);
8247 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8251 tcg_temp_free_i32(tcg_int32
);
8252 tcg_temp_free_i32(tcg_float
);
8255 tcg_temp_free_ptr(tcg_fpst
);
8257 tcg_temp_free_i32(tcg_shift
);
8260 clear_vec_high(s
, elements
<< size
== 16, rd
);
8263 /* UCVTF/SCVTF - Integer to FP conversion */
8264 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8265 bool is_q
, bool is_u
,
8266 int immh
, int immb
, int opcode
,
8269 int size
, elements
, fracbits
;
8270 int immhb
= immh
<< 3 | immb
;
8274 if (!is_scalar
&& !is_q
) {
8275 unallocated_encoding(s
);
8278 } else if (immh
& 4) {
8280 } else if (immh
& 2) {
8282 if (!dc_isar_feature(aa64_fp16
, s
)) {
8283 unallocated_encoding(s
);
8287 /* immh == 0 would be a failure of the decode logic */
8288 g_assert(immh
== 1);
8289 unallocated_encoding(s
);
8296 elements
= (8 << is_q
) >> size
;
8298 fracbits
= (16 << size
) - immhb
;
8300 if (!fp_access_check(s
)) {
8304 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8307 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8308 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8309 bool is_q
, bool is_u
,
8310 int immh
, int immb
, int rn
, int rd
)
8312 int immhb
= immh
<< 3 | immb
;
8313 int pass
, size
, fracbits
;
8314 TCGv_ptr tcg_fpstatus
;
8315 TCGv_i32 tcg_rmode
, tcg_shift
;
8319 if (!is_scalar
&& !is_q
) {
8320 unallocated_encoding(s
);
8323 } else if (immh
& 0x4) {
8325 } else if (immh
& 0x2) {
8327 if (!dc_isar_feature(aa64_fp16
, s
)) {
8328 unallocated_encoding(s
);
8332 /* Should have split out AdvSIMD modified immediate earlier. */
8334 unallocated_encoding(s
);
8338 if (!fp_access_check(s
)) {
8342 assert(!(is_scalar
&& is_q
));
8344 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8345 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8346 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8347 fracbits
= (16 << size
) - immhb
;
8348 tcg_shift
= tcg_const_i32(fracbits
);
8350 if (size
== MO_64
) {
8351 int maxpass
= is_scalar
? 1 : 2;
8353 for (pass
= 0; pass
< maxpass
; pass
++) {
8354 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8356 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8358 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8360 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8362 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8363 tcg_temp_free_i64(tcg_op
);
8365 clear_vec_high(s
, is_q
, rd
);
8367 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8368 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8373 fn
= gen_helper_vfp_touhh
;
8375 fn
= gen_helper_vfp_toshh
;
8380 fn
= gen_helper_vfp_touls
;
8382 fn
= gen_helper_vfp_tosls
;
8386 g_assert_not_reached();
8389 for (pass
= 0; pass
< maxpass
; pass
++) {
8390 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8392 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8393 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8395 write_fp_sreg(s
, rd
, tcg_op
);
8397 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8399 tcg_temp_free_i32(tcg_op
);
8402 clear_vec_high(s
, is_q
, rd
);
8406 tcg_temp_free_ptr(tcg_fpstatus
);
8407 tcg_temp_free_i32(tcg_shift
);
8408 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8409 tcg_temp_free_i32(tcg_rmode
);
8412 /* AdvSIMD scalar shift by immediate
8413 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8414 * +-----+---+-------------+------+------+--------+---+------+------+
8415 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8416 * +-----+---+-------------+------+------+--------+---+------+------+
8418 * This is the scalar version so it works on a fixed sized registers
8420 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8422 int rd
= extract32(insn
, 0, 5);
8423 int rn
= extract32(insn
, 5, 5);
8424 int opcode
= extract32(insn
, 11, 5);
8425 int immb
= extract32(insn
, 16, 3);
8426 int immh
= extract32(insn
, 19, 4);
8427 bool is_u
= extract32(insn
, 29, 1);
8430 unallocated_encoding(s
);
8435 case 0x08: /* SRI */
8437 unallocated_encoding(s
);
8441 case 0x00: /* SSHR / USHR */
8442 case 0x02: /* SSRA / USRA */
8443 case 0x04: /* SRSHR / URSHR */
8444 case 0x06: /* SRSRA / URSRA */
8445 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8447 case 0x0a: /* SHL / SLI */
8448 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8450 case 0x1c: /* SCVTF, UCVTF */
8451 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8454 case 0x10: /* SQSHRUN, SQSHRUN2 */
8455 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8457 unallocated_encoding(s
);
8460 handle_vec_simd_sqshrn(s
, true, false, false, true,
8461 immh
, immb
, opcode
, rn
, rd
);
8463 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8464 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8465 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8466 immh
, immb
, opcode
, rn
, rd
);
8468 case 0xc: /* SQSHLU */
8470 unallocated_encoding(s
);
8473 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8475 case 0xe: /* SQSHL, UQSHL */
8476 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8478 case 0x1f: /* FCVTZS, FCVTZU */
8479 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8482 unallocated_encoding(s
);
8487 /* AdvSIMD scalar three different
8488 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8489 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8490 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8491 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8493 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8495 bool is_u
= extract32(insn
, 29, 1);
8496 int size
= extract32(insn
, 22, 2);
8497 int opcode
= extract32(insn
, 12, 4);
8498 int rm
= extract32(insn
, 16, 5);
8499 int rn
= extract32(insn
, 5, 5);
8500 int rd
= extract32(insn
, 0, 5);
8503 unallocated_encoding(s
);
8508 case 0x9: /* SQDMLAL, SQDMLAL2 */
8509 case 0xb: /* SQDMLSL, SQDMLSL2 */
8510 case 0xd: /* SQDMULL, SQDMULL2 */
8511 if (size
== 0 || size
== 3) {
8512 unallocated_encoding(s
);
8517 unallocated_encoding(s
);
8521 if (!fp_access_check(s
)) {
8526 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8527 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8528 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8530 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8531 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8533 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8534 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8537 case 0xd: /* SQDMULL, SQDMULL2 */
8539 case 0xb: /* SQDMLSL, SQDMLSL2 */
8540 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8542 case 0x9: /* SQDMLAL, SQDMLAL2 */
8543 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8544 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8548 g_assert_not_reached();
8551 write_fp_dreg(s
, rd
, tcg_res
);
8553 tcg_temp_free_i64(tcg_op1
);
8554 tcg_temp_free_i64(tcg_op2
);
8555 tcg_temp_free_i64(tcg_res
);
8557 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8558 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8559 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8561 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8562 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8565 case 0xd: /* SQDMULL, SQDMULL2 */
8567 case 0xb: /* SQDMLSL, SQDMLSL2 */
8568 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8570 case 0x9: /* SQDMLAL, SQDMLAL2 */
8572 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8573 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8574 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8576 tcg_temp_free_i64(tcg_op3
);
8580 g_assert_not_reached();
8583 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8584 write_fp_dreg(s
, rd
, tcg_res
);
8586 tcg_temp_free_i32(tcg_op1
);
8587 tcg_temp_free_i32(tcg_op2
);
8588 tcg_temp_free_i64(tcg_res
);
8592 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8593 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8595 /* Handle 64x64->64 opcodes which are shared between the scalar
8596 * and vector 3-same groups. We cover every opcode where size == 3
8597 * is valid in either the three-reg-same (integer, not pairwise)
8598 * or scalar-three-reg-same groups.
8603 case 0x1: /* SQADD */
8605 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8607 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8610 case 0x5: /* SQSUB */
8612 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8614 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8617 case 0x6: /* CMGT, CMHI */
8618 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8619 * We implement this using setcond (test) and then negating.
8621 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8623 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8624 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8626 case 0x7: /* CMGE, CMHS */
8627 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8629 case 0x11: /* CMTST, CMEQ */
8634 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8636 case 0x8: /* SSHL, USHL */
8638 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8640 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8643 case 0x9: /* SQSHL, UQSHL */
8645 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8647 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8650 case 0xa: /* SRSHL, URSHL */
8652 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8654 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8657 case 0xb: /* SQRSHL, UQRSHL */
8659 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8661 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8664 case 0x10: /* ADD, SUB */
8666 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8668 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8672 g_assert_not_reached();
8676 /* Handle the 3-same-operands float operations; shared by the scalar
8677 * and vector encodings. The caller must filter out any encodings
8678 * not allocated for the encoding it is dealing with.
8680 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8681 int fpopcode
, int rd
, int rn
, int rm
)
8684 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8686 for (pass
= 0; pass
< elements
; pass
++) {
8689 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8690 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8691 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8693 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8694 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8697 case 0x39: /* FMLS */
8698 /* As usual for ARM, separate negation for fused multiply-add */
8699 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8701 case 0x19: /* FMLA */
8702 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8703 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8706 case 0x18: /* FMAXNM */
8707 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8709 case 0x1a: /* FADD */
8710 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8712 case 0x1b: /* FMULX */
8713 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8715 case 0x1c: /* FCMEQ */
8716 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8718 case 0x1e: /* FMAX */
8719 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8721 case 0x1f: /* FRECPS */
8722 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8724 case 0x38: /* FMINNM */
8725 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8727 case 0x3a: /* FSUB */
8728 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8730 case 0x3e: /* FMIN */
8731 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8733 case 0x3f: /* FRSQRTS */
8734 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8736 case 0x5b: /* FMUL */
8737 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8739 case 0x5c: /* FCMGE */
8740 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8742 case 0x5d: /* FACGE */
8743 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8745 case 0x5f: /* FDIV */
8746 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8748 case 0x7a: /* FABD */
8749 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8750 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8752 case 0x7c: /* FCMGT */
8753 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8755 case 0x7d: /* FACGT */
8756 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8759 g_assert_not_reached();
8762 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8764 tcg_temp_free_i64(tcg_res
);
8765 tcg_temp_free_i64(tcg_op1
);
8766 tcg_temp_free_i64(tcg_op2
);
8769 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8770 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8771 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8773 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8774 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8777 case 0x39: /* FMLS */
8778 /* As usual for ARM, separate negation for fused multiply-add */
8779 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8781 case 0x19: /* FMLA */
8782 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8783 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8786 case 0x1a: /* FADD */
8787 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8789 case 0x1b: /* FMULX */
8790 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8792 case 0x1c: /* FCMEQ */
8793 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8795 case 0x1e: /* FMAX */
8796 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8798 case 0x1f: /* FRECPS */
8799 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8801 case 0x18: /* FMAXNM */
8802 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8804 case 0x38: /* FMINNM */
8805 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8807 case 0x3a: /* FSUB */
8808 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8810 case 0x3e: /* FMIN */
8811 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8813 case 0x3f: /* FRSQRTS */
8814 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8816 case 0x5b: /* FMUL */
8817 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8819 case 0x5c: /* FCMGE */
8820 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8822 case 0x5d: /* FACGE */
8823 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8825 case 0x5f: /* FDIV */
8826 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8828 case 0x7a: /* FABD */
8829 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8830 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8832 case 0x7c: /* FCMGT */
8833 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8835 case 0x7d: /* FACGT */
8836 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8839 g_assert_not_reached();
8842 if (elements
== 1) {
8843 /* scalar single so clear high part */
8844 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8846 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8847 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8848 tcg_temp_free_i64(tcg_tmp
);
8850 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8853 tcg_temp_free_i32(tcg_res
);
8854 tcg_temp_free_i32(tcg_op1
);
8855 tcg_temp_free_i32(tcg_op2
);
8859 tcg_temp_free_ptr(fpst
);
8861 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8864 /* AdvSIMD scalar three same
8865 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8866 * +-----+---+-----------+------+---+------+--------+---+------+------+
8867 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8868 * +-----+---+-----------+------+---+------+--------+---+------+------+
8870 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8872 int rd
= extract32(insn
, 0, 5);
8873 int rn
= extract32(insn
, 5, 5);
8874 int opcode
= extract32(insn
, 11, 5);
8875 int rm
= extract32(insn
, 16, 5);
8876 int size
= extract32(insn
, 22, 2);
8877 bool u
= extract32(insn
, 29, 1);
8880 if (opcode
>= 0x18) {
8881 /* Floating point: U, size[1] and opcode indicate operation */
8882 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8884 case 0x1b: /* FMULX */
8885 case 0x1f: /* FRECPS */
8886 case 0x3f: /* FRSQRTS */
8887 case 0x5d: /* FACGE */
8888 case 0x7d: /* FACGT */
8889 case 0x1c: /* FCMEQ */
8890 case 0x5c: /* FCMGE */
8891 case 0x7c: /* FCMGT */
8892 case 0x7a: /* FABD */
8895 unallocated_encoding(s
);
8899 if (!fp_access_check(s
)) {
8903 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8908 case 0x1: /* SQADD, UQADD */
8909 case 0x5: /* SQSUB, UQSUB */
8910 case 0x9: /* SQSHL, UQSHL */
8911 case 0xb: /* SQRSHL, UQRSHL */
8913 case 0x8: /* SSHL, USHL */
8914 case 0xa: /* SRSHL, URSHL */
8915 case 0x6: /* CMGT, CMHI */
8916 case 0x7: /* CMGE, CMHS */
8917 case 0x11: /* CMTST, CMEQ */
8918 case 0x10: /* ADD, SUB (vector) */
8920 unallocated_encoding(s
);
8924 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8925 if (size
!= 1 && size
!= 2) {
8926 unallocated_encoding(s
);
8931 unallocated_encoding(s
);
8935 if (!fp_access_check(s
)) {
8939 tcg_rd
= tcg_temp_new_i64();
8942 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8943 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8945 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8946 tcg_temp_free_i64(tcg_rn
);
8947 tcg_temp_free_i64(tcg_rm
);
8949 /* Do a single operation on the lowest element in the vector.
8950 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8951 * no side effects for all these operations.
8952 * OPTME: special-purpose helpers would avoid doing some
8953 * unnecessary work in the helper for the 8 and 16 bit cases.
8955 NeonGenTwoOpEnvFn
*genenvfn
;
8956 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8957 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8958 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8960 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8961 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8964 case 0x1: /* SQADD, UQADD */
8966 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8967 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8968 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8969 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8971 genenvfn
= fns
[size
][u
];
8974 case 0x5: /* SQSUB, UQSUB */
8976 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8977 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8978 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8979 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8981 genenvfn
= fns
[size
][u
];
8984 case 0x9: /* SQSHL, UQSHL */
8986 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8987 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8988 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8989 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8991 genenvfn
= fns
[size
][u
];
8994 case 0xb: /* SQRSHL, UQRSHL */
8996 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8997 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8998 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8999 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9001 genenvfn
= fns
[size
][u
];
9004 case 0x16: /* SQDMULH, SQRDMULH */
9006 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9007 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9008 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9010 assert(size
== 1 || size
== 2);
9011 genenvfn
= fns
[size
- 1][u
];
9015 g_assert_not_reached();
9018 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9019 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9020 tcg_temp_free_i32(tcg_rd32
);
9021 tcg_temp_free_i32(tcg_rn
);
9022 tcg_temp_free_i32(tcg_rm
);
9025 write_fp_dreg(s
, rd
, tcg_rd
);
9027 tcg_temp_free_i64(tcg_rd
);
9030 /* AdvSIMD scalar three same FP16
9031 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9032 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9033 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9034 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9035 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9036 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9038 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9041 int rd
= extract32(insn
, 0, 5);
9042 int rn
= extract32(insn
, 5, 5);
9043 int opcode
= extract32(insn
, 11, 3);
9044 int rm
= extract32(insn
, 16, 5);
9045 bool u
= extract32(insn
, 29, 1);
9046 bool a
= extract32(insn
, 23, 1);
9047 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9054 case 0x03: /* FMULX */
9055 case 0x04: /* FCMEQ (reg) */
9056 case 0x07: /* FRECPS */
9057 case 0x0f: /* FRSQRTS */
9058 case 0x14: /* FCMGE (reg) */
9059 case 0x15: /* FACGE */
9060 case 0x1a: /* FABD */
9061 case 0x1c: /* FCMGT (reg) */
9062 case 0x1d: /* FACGT */
9065 unallocated_encoding(s
);
9069 if (!dc_isar_feature(aa64_fp16
, s
)) {
9070 unallocated_encoding(s
);
9073 if (!fp_access_check(s
)) {
9077 fpst
= get_fpstatus_ptr(true);
9079 tcg_op1
= read_fp_hreg(s
, rn
);
9080 tcg_op2
= read_fp_hreg(s
, rm
);
9081 tcg_res
= tcg_temp_new_i32();
9084 case 0x03: /* FMULX */
9085 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9087 case 0x04: /* FCMEQ (reg) */
9088 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9090 case 0x07: /* FRECPS */
9091 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9093 case 0x0f: /* FRSQRTS */
9094 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9096 case 0x14: /* FCMGE (reg) */
9097 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9099 case 0x15: /* FACGE */
9100 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9102 case 0x1a: /* FABD */
9103 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9104 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9106 case 0x1c: /* FCMGT (reg) */
9107 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9109 case 0x1d: /* FACGT */
9110 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9113 g_assert_not_reached();
9116 write_fp_sreg(s
, rd
, tcg_res
);
9119 tcg_temp_free_i32(tcg_res
);
9120 tcg_temp_free_i32(tcg_op1
);
9121 tcg_temp_free_i32(tcg_op2
);
9122 tcg_temp_free_ptr(fpst
);
9125 /* AdvSIMD scalar three same extra
9126 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9127 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9128 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9129 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9131 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9134 int rd
= extract32(insn
, 0, 5);
9135 int rn
= extract32(insn
, 5, 5);
9136 int opcode
= extract32(insn
, 11, 4);
9137 int rm
= extract32(insn
, 16, 5);
9138 int size
= extract32(insn
, 22, 2);
9139 bool u
= extract32(insn
, 29, 1);
9140 TCGv_i32 ele1
, ele2
, ele3
;
9144 switch (u
* 16 + opcode
) {
9145 case 0x10: /* SQRDMLAH (vector) */
9146 case 0x11: /* SQRDMLSH (vector) */
9147 if (size
!= 1 && size
!= 2) {
9148 unallocated_encoding(s
);
9151 feature
= dc_isar_feature(aa64_rdm
, s
);
9154 unallocated_encoding(s
);
9158 unallocated_encoding(s
);
9161 if (!fp_access_check(s
)) {
9165 /* Do a single operation on the lowest element in the vector.
9166 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9167 * with no side effects for all these operations.
9168 * OPTME: special-purpose helpers would avoid doing some
9169 * unnecessary work in the helper for the 16 bit cases.
9171 ele1
= tcg_temp_new_i32();
9172 ele2
= tcg_temp_new_i32();
9173 ele3
= tcg_temp_new_i32();
9175 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9176 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9177 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9180 case 0x0: /* SQRDMLAH */
9182 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9184 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9187 case 0x1: /* SQRDMLSH */
9189 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9191 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9195 g_assert_not_reached();
9197 tcg_temp_free_i32(ele1
);
9198 tcg_temp_free_i32(ele2
);
9200 res
= tcg_temp_new_i64();
9201 tcg_gen_extu_i32_i64(res
, ele3
);
9202 tcg_temp_free_i32(ele3
);
9204 write_fp_dreg(s
, rd
, res
);
9205 tcg_temp_free_i64(res
);
9208 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9209 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9210 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9212 /* Handle 64->64 opcodes which are shared between the scalar and
9213 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9214 * is valid in either group and also the double-precision fp ops.
9215 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9221 case 0x4: /* CLS, CLZ */
9223 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9225 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9229 /* This opcode is shared with CNT and RBIT but we have earlier
9230 * enforced that size == 3 if and only if this is the NOT insn.
9232 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9234 case 0x7: /* SQABS, SQNEG */
9236 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9238 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9241 case 0xa: /* CMLT */
9242 /* 64 bit integer comparison against zero, result is
9243 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9248 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9249 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9251 case 0x8: /* CMGT, CMGE */
9252 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9254 case 0x9: /* CMEQ, CMLE */
9255 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9257 case 0xb: /* ABS, NEG */
9259 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9261 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9262 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9263 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
9265 tcg_temp_free_i64(tcg_zero
);
9268 case 0x2f: /* FABS */
9269 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9271 case 0x6f: /* FNEG */
9272 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9274 case 0x7f: /* FSQRT */
9275 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9277 case 0x1a: /* FCVTNS */
9278 case 0x1b: /* FCVTMS */
9279 case 0x1c: /* FCVTAS */
9280 case 0x3a: /* FCVTPS */
9281 case 0x3b: /* FCVTZS */
9283 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9284 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9285 tcg_temp_free_i32(tcg_shift
);
9288 case 0x5a: /* FCVTNU */
9289 case 0x5b: /* FCVTMU */
9290 case 0x5c: /* FCVTAU */
9291 case 0x7a: /* FCVTPU */
9292 case 0x7b: /* FCVTZU */
9294 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9295 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9296 tcg_temp_free_i32(tcg_shift
);
9299 case 0x18: /* FRINTN */
9300 case 0x19: /* FRINTM */
9301 case 0x38: /* FRINTP */
9302 case 0x39: /* FRINTZ */
9303 case 0x58: /* FRINTA */
9304 case 0x79: /* FRINTI */
9305 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9307 case 0x59: /* FRINTX */
9308 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9311 g_assert_not_reached();
9315 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9316 bool is_scalar
, bool is_u
, bool is_q
,
9317 int size
, int rn
, int rd
)
9319 bool is_double
= (size
== MO_64
);
9322 if (!fp_access_check(s
)) {
9326 fpst
= get_fpstatus_ptr(size
== MO_16
);
9329 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9330 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9331 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9332 NeonGenTwoDoubleOPFn
*genfn
;
9337 case 0x2e: /* FCMLT (zero) */
9340 case 0x2c: /* FCMGT (zero) */
9341 genfn
= gen_helper_neon_cgt_f64
;
9343 case 0x2d: /* FCMEQ (zero) */
9344 genfn
= gen_helper_neon_ceq_f64
;
9346 case 0x6d: /* FCMLE (zero) */
9349 case 0x6c: /* FCMGE (zero) */
9350 genfn
= gen_helper_neon_cge_f64
;
9353 g_assert_not_reached();
9356 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9357 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9359 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9361 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9363 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9365 tcg_temp_free_i64(tcg_res
);
9366 tcg_temp_free_i64(tcg_zero
);
9367 tcg_temp_free_i64(tcg_op
);
9369 clear_vec_high(s
, !is_scalar
, rd
);
9371 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9372 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9373 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9374 NeonGenTwoSingleOPFn
*genfn
;
9376 int pass
, maxpasses
;
9378 if (size
== MO_16
) {
9380 case 0x2e: /* FCMLT (zero) */
9383 case 0x2c: /* FCMGT (zero) */
9384 genfn
= gen_helper_advsimd_cgt_f16
;
9386 case 0x2d: /* FCMEQ (zero) */
9387 genfn
= gen_helper_advsimd_ceq_f16
;
9389 case 0x6d: /* FCMLE (zero) */
9392 case 0x6c: /* FCMGE (zero) */
9393 genfn
= gen_helper_advsimd_cge_f16
;
9396 g_assert_not_reached();
9400 case 0x2e: /* FCMLT (zero) */
9403 case 0x2c: /* FCMGT (zero) */
9404 genfn
= gen_helper_neon_cgt_f32
;
9406 case 0x2d: /* FCMEQ (zero) */
9407 genfn
= gen_helper_neon_ceq_f32
;
9409 case 0x6d: /* FCMLE (zero) */
9412 case 0x6c: /* FCMGE (zero) */
9413 genfn
= gen_helper_neon_cge_f32
;
9416 g_assert_not_reached();
9423 int vector_size
= 8 << is_q
;
9424 maxpasses
= vector_size
>> size
;
9427 for (pass
= 0; pass
< maxpasses
; pass
++) {
9428 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9430 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9432 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9435 write_fp_sreg(s
, rd
, tcg_res
);
9437 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9440 tcg_temp_free_i32(tcg_res
);
9441 tcg_temp_free_i32(tcg_zero
);
9442 tcg_temp_free_i32(tcg_op
);
9444 clear_vec_high(s
, is_q
, rd
);
9448 tcg_temp_free_ptr(fpst
);
9451 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9452 bool is_scalar
, bool is_u
, bool is_q
,
9453 int size
, int rn
, int rd
)
9455 bool is_double
= (size
== 3);
9456 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9459 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9460 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9463 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9464 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9466 case 0x3d: /* FRECPE */
9467 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9469 case 0x3f: /* FRECPX */
9470 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9472 case 0x7d: /* FRSQRTE */
9473 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9476 g_assert_not_reached();
9478 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9480 tcg_temp_free_i64(tcg_res
);
9481 tcg_temp_free_i64(tcg_op
);
9482 clear_vec_high(s
, !is_scalar
, rd
);
9484 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9485 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9486 int pass
, maxpasses
;
9491 maxpasses
= is_q
? 4 : 2;
9494 for (pass
= 0; pass
< maxpasses
; pass
++) {
9495 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9498 case 0x3c: /* URECPE */
9499 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9501 case 0x3d: /* FRECPE */
9502 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9504 case 0x3f: /* FRECPX */
9505 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9507 case 0x7d: /* FRSQRTE */
9508 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9511 g_assert_not_reached();
9515 write_fp_sreg(s
, rd
, tcg_res
);
9517 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9520 tcg_temp_free_i32(tcg_res
);
9521 tcg_temp_free_i32(tcg_op
);
9523 clear_vec_high(s
, is_q
, rd
);
9526 tcg_temp_free_ptr(fpst
);
9529 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9530 int opcode
, bool u
, bool is_q
,
9531 int size
, int rn
, int rd
)
9533 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9534 * in the source becomes a size element in the destination).
9537 TCGv_i32 tcg_res
[2];
9538 int destelt
= is_q
? 2 : 0;
9539 int passes
= scalar
? 1 : 2;
9542 tcg_res
[1] = tcg_const_i32(0);
9545 for (pass
= 0; pass
< passes
; pass
++) {
9546 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9547 NeonGenNarrowFn
*genfn
= NULL
;
9548 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9551 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9553 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9555 tcg_res
[pass
] = tcg_temp_new_i32();
9558 case 0x12: /* XTN, SQXTUN */
9560 static NeonGenNarrowFn
* const xtnfns
[3] = {
9561 gen_helper_neon_narrow_u8
,
9562 gen_helper_neon_narrow_u16
,
9563 tcg_gen_extrl_i64_i32
,
9565 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9566 gen_helper_neon_unarrow_sat8
,
9567 gen_helper_neon_unarrow_sat16
,
9568 gen_helper_neon_unarrow_sat32
,
9571 genenvfn
= sqxtunfns
[size
];
9573 genfn
= xtnfns
[size
];
9577 case 0x14: /* SQXTN, UQXTN */
9579 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9580 { gen_helper_neon_narrow_sat_s8
,
9581 gen_helper_neon_narrow_sat_u8
},
9582 { gen_helper_neon_narrow_sat_s16
,
9583 gen_helper_neon_narrow_sat_u16
},
9584 { gen_helper_neon_narrow_sat_s32
,
9585 gen_helper_neon_narrow_sat_u32
},
9587 genenvfn
= fns
[size
][u
];
9590 case 0x16: /* FCVTN, FCVTN2 */
9591 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9593 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9595 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9596 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9597 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9598 TCGv_i32 ahp
= get_ahp_flag();
9600 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9601 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9602 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9603 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9604 tcg_temp_free_i32(tcg_lo
);
9605 tcg_temp_free_i32(tcg_hi
);
9606 tcg_temp_free_ptr(fpst
);
9607 tcg_temp_free_i32(ahp
);
9610 case 0x56: /* FCVTXN, FCVTXN2 */
9611 /* 64 bit to 32 bit float conversion
9612 * with von Neumann rounding (round to odd)
9615 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9618 g_assert_not_reached();
9622 genfn(tcg_res
[pass
], tcg_op
);
9623 } else if (genenvfn
) {
9624 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9627 tcg_temp_free_i64(tcg_op
);
9630 for (pass
= 0; pass
< 2; pass
++) {
9631 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9632 tcg_temp_free_i32(tcg_res
[pass
]);
9634 clear_vec_high(s
, is_q
, rd
);
9637 /* Remaining saturating accumulating ops */
9638 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9639 bool is_q
, int size
, int rn
, int rd
)
9641 bool is_double
= (size
== 3);
9644 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9645 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9648 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9649 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9650 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9652 if (is_u
) { /* USQADD */
9653 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9654 } else { /* SUQADD */
9655 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9657 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9659 tcg_temp_free_i64(tcg_rd
);
9660 tcg_temp_free_i64(tcg_rn
);
9661 clear_vec_high(s
, !is_scalar
, rd
);
9663 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9664 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9665 int pass
, maxpasses
;
9670 maxpasses
= is_q
? 4 : 2;
9673 for (pass
= 0; pass
< maxpasses
; pass
++) {
9675 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9676 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9678 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9679 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9682 if (is_u
) { /* USQADD */
9685 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9688 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9691 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9694 g_assert_not_reached();
9696 } else { /* SUQADD */
9699 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9702 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9705 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9708 g_assert_not_reached();
9713 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9714 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9715 tcg_temp_free_i64(tcg_zero
);
9717 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9719 tcg_temp_free_i32(tcg_rd
);
9720 tcg_temp_free_i32(tcg_rn
);
9721 clear_vec_high(s
, is_q
, rd
);
9725 /* AdvSIMD scalar two reg misc
9726 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9727 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9728 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9729 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9731 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9733 int rd
= extract32(insn
, 0, 5);
9734 int rn
= extract32(insn
, 5, 5);
9735 int opcode
= extract32(insn
, 12, 5);
9736 int size
= extract32(insn
, 22, 2);
9737 bool u
= extract32(insn
, 29, 1);
9738 bool is_fcvt
= false;
9741 TCGv_ptr tcg_fpstatus
;
9744 case 0x3: /* USQADD / SUQADD*/
9745 if (!fp_access_check(s
)) {
9748 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9750 case 0x7: /* SQABS / SQNEG */
9752 case 0xa: /* CMLT */
9754 unallocated_encoding(s
);
9758 case 0x8: /* CMGT, CMGE */
9759 case 0x9: /* CMEQ, CMLE */
9760 case 0xb: /* ABS, NEG */
9762 unallocated_encoding(s
);
9766 case 0x12: /* SQXTUN */
9768 unallocated_encoding(s
);
9772 case 0x14: /* SQXTN, UQXTN */
9774 unallocated_encoding(s
);
9777 if (!fp_access_check(s
)) {
9780 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9785 /* Floating point: U, size[1] and opcode indicate operation;
9786 * size[0] indicates single or double precision.
9788 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9789 size
= extract32(size
, 0, 1) ? 3 : 2;
9791 case 0x2c: /* FCMGT (zero) */
9792 case 0x2d: /* FCMEQ (zero) */
9793 case 0x2e: /* FCMLT (zero) */
9794 case 0x6c: /* FCMGE (zero) */
9795 case 0x6d: /* FCMLE (zero) */
9796 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9798 case 0x1d: /* SCVTF */
9799 case 0x5d: /* UCVTF */
9801 bool is_signed
= (opcode
== 0x1d);
9802 if (!fp_access_check(s
)) {
9805 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9808 case 0x3d: /* FRECPE */
9809 case 0x3f: /* FRECPX */
9810 case 0x7d: /* FRSQRTE */
9811 if (!fp_access_check(s
)) {
9814 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9816 case 0x1a: /* FCVTNS */
9817 case 0x1b: /* FCVTMS */
9818 case 0x3a: /* FCVTPS */
9819 case 0x3b: /* FCVTZS */
9820 case 0x5a: /* FCVTNU */
9821 case 0x5b: /* FCVTMU */
9822 case 0x7a: /* FCVTPU */
9823 case 0x7b: /* FCVTZU */
9825 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9827 case 0x1c: /* FCVTAS */
9828 case 0x5c: /* FCVTAU */
9829 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9831 rmode
= FPROUNDING_TIEAWAY
;
9833 case 0x56: /* FCVTXN, FCVTXN2 */
9835 unallocated_encoding(s
);
9838 if (!fp_access_check(s
)) {
9841 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9844 unallocated_encoding(s
);
9849 unallocated_encoding(s
);
9853 if (!fp_access_check(s
)) {
9858 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9859 tcg_fpstatus
= get_fpstatus_ptr(false);
9860 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9863 tcg_fpstatus
= NULL
;
9867 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9868 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9870 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9871 write_fp_dreg(s
, rd
, tcg_rd
);
9872 tcg_temp_free_i64(tcg_rd
);
9873 tcg_temp_free_i64(tcg_rn
);
9875 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9876 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9878 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9881 case 0x7: /* SQABS, SQNEG */
9883 NeonGenOneOpEnvFn
*genfn
;
9884 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9885 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9886 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9887 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9889 genfn
= fns
[size
][u
];
9890 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9893 case 0x1a: /* FCVTNS */
9894 case 0x1b: /* FCVTMS */
9895 case 0x1c: /* FCVTAS */
9896 case 0x3a: /* FCVTPS */
9897 case 0x3b: /* FCVTZS */
9899 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9900 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9901 tcg_temp_free_i32(tcg_shift
);
9904 case 0x5a: /* FCVTNU */
9905 case 0x5b: /* FCVTMU */
9906 case 0x5c: /* FCVTAU */
9907 case 0x7a: /* FCVTPU */
9908 case 0x7b: /* FCVTZU */
9910 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9911 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9912 tcg_temp_free_i32(tcg_shift
);
9916 g_assert_not_reached();
9919 write_fp_sreg(s
, rd
, tcg_rd
);
9920 tcg_temp_free_i32(tcg_rd
);
9921 tcg_temp_free_i32(tcg_rn
);
9925 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9926 tcg_temp_free_i32(tcg_rmode
);
9927 tcg_temp_free_ptr(tcg_fpstatus
);
9931 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9932 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9933 int immh
, int immb
, int opcode
, int rn
, int rd
)
9935 int size
= 32 - clz32(immh
) - 1;
9936 int immhb
= immh
<< 3 | immb
;
9937 int shift
= 2 * (8 << size
) - immhb
;
9938 bool accumulate
= false;
9939 int dsize
= is_q
? 128 : 64;
9940 int esize
= 8 << size
;
9941 int elements
= dsize
/esize
;
9942 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9943 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9944 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9946 uint64_t round_const
;
9949 if (extract32(immh
, 3, 1) && !is_q
) {
9950 unallocated_encoding(s
);
9953 tcg_debug_assert(size
<= 3);
9955 if (!fp_access_check(s
)) {
9960 case 0x02: /* SSRA / USRA (accumulate) */
9962 /* Shift count same as element size produces zero to add. */
9963 if (shift
== 8 << size
) {
9966 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9968 /* Shift count same as element size produces all sign to add. */
9969 if (shift
== 8 << size
) {
9972 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9975 case 0x08: /* SRI */
9976 /* Shift count same as element size is valid but does nothing. */
9977 if (shift
== 8 << size
) {
9980 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9983 case 0x00: /* SSHR / USHR */
9985 if (shift
== 8 << size
) {
9986 /* Shift count the same size as element size produces zero. */
9987 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9988 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9990 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9993 /* Shift count the same size as element size produces all sign. */
9994 if (shift
== 8 << size
) {
9997 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
10001 case 0x04: /* SRSHR / URSHR (rounding) */
10003 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10007 g_assert_not_reached();
10010 round_const
= 1ULL << (shift
- 1);
10011 tcg_round
= tcg_const_i64(round_const
);
10013 for (i
= 0; i
< elements
; i
++) {
10014 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
10016 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
10019 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10020 accumulate
, is_u
, size
, shift
);
10022 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
10024 tcg_temp_free_i64(tcg_round
);
10027 clear_vec_high(s
, is_q
, rd
);
10030 /* SHL/SLI - Vector shift left */
10031 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10032 int immh
, int immb
, int opcode
, int rn
, int rd
)
10034 int size
= 32 - clz32(immh
) - 1;
10035 int immhb
= immh
<< 3 | immb
;
10036 int shift
= immhb
- (8 << size
);
10038 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10039 assert(size
>= 0 && size
<= 3);
10041 if (extract32(immh
, 3, 1) && !is_q
) {
10042 unallocated_encoding(s
);
10046 if (!fp_access_check(s
)) {
10051 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
10053 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10057 /* USHLL/SHLL - Vector shift left with widening */
10058 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10059 int immh
, int immb
, int opcode
, int rn
, int rd
)
10061 int size
= 32 - clz32(immh
) - 1;
10062 int immhb
= immh
<< 3 | immb
;
10063 int shift
= immhb
- (8 << size
);
10065 int esize
= 8 << size
;
10066 int elements
= dsize
/esize
;
10067 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10068 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10072 unallocated_encoding(s
);
10076 if (!fp_access_check(s
)) {
10080 /* For the LL variants the store is larger than the load,
10081 * so if rd == rn we would overwrite parts of our input.
10082 * So load everything right now and use shifts in the main loop.
10084 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10086 for (i
= 0; i
< elements
; i
++) {
10087 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10088 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10089 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10090 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10094 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10095 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10096 int immh
, int immb
, int opcode
, int rn
, int rd
)
10098 int immhb
= immh
<< 3 | immb
;
10099 int size
= 32 - clz32(immh
) - 1;
10101 int esize
= 8 << size
;
10102 int elements
= dsize
/esize
;
10103 int shift
= (2 * esize
) - immhb
;
10104 bool round
= extract32(opcode
, 0, 1);
10105 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10106 TCGv_i64 tcg_round
;
10109 if (extract32(immh
, 3, 1)) {
10110 unallocated_encoding(s
);
10114 if (!fp_access_check(s
)) {
10118 tcg_rn
= tcg_temp_new_i64();
10119 tcg_rd
= tcg_temp_new_i64();
10120 tcg_final
= tcg_temp_new_i64();
10121 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10124 uint64_t round_const
= 1ULL << (shift
- 1);
10125 tcg_round
= tcg_const_i64(round_const
);
10130 for (i
= 0; i
< elements
; i
++) {
10131 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10132 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10133 false, true, size
+1, shift
);
10135 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10139 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10141 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10144 tcg_temp_free_i64(tcg_round
);
10146 tcg_temp_free_i64(tcg_rn
);
10147 tcg_temp_free_i64(tcg_rd
);
10148 tcg_temp_free_i64(tcg_final
);
10150 clear_vec_high(s
, is_q
, rd
);
10154 /* AdvSIMD shift by immediate
10155 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10156 * +---+---+---+-------------+------+------+--------+---+------+------+
10157 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10158 * +---+---+---+-------------+------+------+--------+---+------+------+
10160 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10162 int rd
= extract32(insn
, 0, 5);
10163 int rn
= extract32(insn
, 5, 5);
10164 int opcode
= extract32(insn
, 11, 5);
10165 int immb
= extract32(insn
, 16, 3);
10166 int immh
= extract32(insn
, 19, 4);
10167 bool is_u
= extract32(insn
, 29, 1);
10168 bool is_q
= extract32(insn
, 30, 1);
10171 case 0x08: /* SRI */
10173 unallocated_encoding(s
);
10177 case 0x00: /* SSHR / USHR */
10178 case 0x02: /* SSRA / USRA (accumulate) */
10179 case 0x04: /* SRSHR / URSHR (rounding) */
10180 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10181 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10183 case 0x0a: /* SHL / SLI */
10184 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10186 case 0x10: /* SHRN */
10187 case 0x11: /* RSHRN / SQRSHRUN */
10189 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10192 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10195 case 0x12: /* SQSHRN / UQSHRN */
10196 case 0x13: /* SQRSHRN / UQRSHRN */
10197 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10200 case 0x14: /* SSHLL / USHLL */
10201 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10203 case 0x1c: /* SCVTF / UCVTF */
10204 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10207 case 0xc: /* SQSHLU */
10209 unallocated_encoding(s
);
10212 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10214 case 0xe: /* SQSHL, UQSHL */
10215 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10217 case 0x1f: /* FCVTZS/ FCVTZU */
10218 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10221 unallocated_encoding(s
);
10226 /* Generate code to do a "long" addition or subtraction, ie one done in
10227 * TCGv_i64 on vector lanes twice the width specified by size.
10229 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10230 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10232 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10233 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10234 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10235 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10237 NeonGenTwo64OpFn
*genfn
;
10240 genfn
= fns
[size
][is_sub
];
10241 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10244 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10245 int opcode
, int rd
, int rn
, int rm
)
10247 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10248 TCGv_i64 tcg_res
[2];
10251 tcg_res
[0] = tcg_temp_new_i64();
10252 tcg_res
[1] = tcg_temp_new_i64();
10254 /* Does this op do an adding accumulate, a subtracting accumulate,
10255 * or no accumulate at all?
10273 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10274 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10277 /* size == 2 means two 32x32->64 operations; this is worth special
10278 * casing because we can generally handle it inline.
10281 for (pass
= 0; pass
< 2; pass
++) {
10282 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10283 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10284 TCGv_i64 tcg_passres
;
10285 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10287 int elt
= pass
+ is_q
* 2;
10289 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10290 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10293 tcg_passres
= tcg_res
[pass
];
10295 tcg_passres
= tcg_temp_new_i64();
10299 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10300 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10302 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10303 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10305 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10306 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10308 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10309 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10311 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10312 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10313 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10315 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10316 tcg_temp_free_i64(tcg_tmp1
);
10317 tcg_temp_free_i64(tcg_tmp2
);
10320 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10321 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10322 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10323 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10325 case 9: /* SQDMLAL, SQDMLAL2 */
10326 case 11: /* SQDMLSL, SQDMLSL2 */
10327 case 13: /* SQDMULL, SQDMULL2 */
10328 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10329 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10330 tcg_passres
, tcg_passres
);
10333 g_assert_not_reached();
10336 if (opcode
== 9 || opcode
== 11) {
10337 /* saturating accumulate ops */
10339 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10341 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10342 tcg_res
[pass
], tcg_passres
);
10343 } else if (accop
> 0) {
10344 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10345 } else if (accop
< 0) {
10346 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10350 tcg_temp_free_i64(tcg_passres
);
10353 tcg_temp_free_i64(tcg_op1
);
10354 tcg_temp_free_i64(tcg_op2
);
10357 /* size 0 or 1, generally helper functions */
10358 for (pass
= 0; pass
< 2; pass
++) {
10359 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10360 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10361 TCGv_i64 tcg_passres
;
10362 int elt
= pass
+ is_q
* 2;
10364 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10365 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10368 tcg_passres
= tcg_res
[pass
];
10370 tcg_passres
= tcg_temp_new_i64();
10374 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10375 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10377 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10378 static NeonGenWidenFn
* const widenfns
[2][2] = {
10379 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10380 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10382 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10384 widenfn(tcg_op2_64
, tcg_op2
);
10385 widenfn(tcg_passres
, tcg_op1
);
10386 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10387 tcg_passres
, tcg_op2_64
);
10388 tcg_temp_free_i64(tcg_op2_64
);
10391 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10392 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10395 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10397 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10401 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10403 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10407 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10408 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10409 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10412 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10414 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10418 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10420 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10424 case 9: /* SQDMLAL, SQDMLAL2 */
10425 case 11: /* SQDMLSL, SQDMLSL2 */
10426 case 13: /* SQDMULL, SQDMULL2 */
10428 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10429 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10430 tcg_passres
, tcg_passres
);
10432 case 14: /* PMULL */
10434 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10437 g_assert_not_reached();
10439 tcg_temp_free_i32(tcg_op1
);
10440 tcg_temp_free_i32(tcg_op2
);
10443 if (opcode
== 9 || opcode
== 11) {
10444 /* saturating accumulate ops */
10446 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10448 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10452 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10453 tcg_res
[pass
], tcg_passres
);
10455 tcg_temp_free_i64(tcg_passres
);
10460 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10461 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10462 tcg_temp_free_i64(tcg_res
[0]);
10463 tcg_temp_free_i64(tcg_res
[1]);
10466 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10467 int opcode
, int rd
, int rn
, int rm
)
10469 TCGv_i64 tcg_res
[2];
10470 int part
= is_q
? 2 : 0;
10473 for (pass
= 0; pass
< 2; pass
++) {
10474 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10475 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10476 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10477 static NeonGenWidenFn
* const widenfns
[3][2] = {
10478 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10479 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10480 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10482 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10484 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10485 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10486 widenfn(tcg_op2_wide
, tcg_op2
);
10487 tcg_temp_free_i32(tcg_op2
);
10488 tcg_res
[pass
] = tcg_temp_new_i64();
10489 gen_neon_addl(size
, (opcode
== 3),
10490 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10491 tcg_temp_free_i64(tcg_op1
);
10492 tcg_temp_free_i64(tcg_op2_wide
);
10495 for (pass
= 0; pass
< 2; pass
++) {
10496 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10497 tcg_temp_free_i64(tcg_res
[pass
]);
10501 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10503 tcg_gen_addi_i64(in
, in
, 1U << 31);
10504 tcg_gen_extrh_i64_i32(res
, in
);
10507 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10508 int opcode
, int rd
, int rn
, int rm
)
10510 TCGv_i32 tcg_res
[2];
10511 int part
= is_q
? 2 : 0;
10514 for (pass
= 0; pass
< 2; pass
++) {
10515 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10516 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10517 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10518 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10519 { gen_helper_neon_narrow_high_u8
,
10520 gen_helper_neon_narrow_round_high_u8
},
10521 { gen_helper_neon_narrow_high_u16
,
10522 gen_helper_neon_narrow_round_high_u16
},
10523 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10525 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10527 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10528 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10530 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10532 tcg_temp_free_i64(tcg_op1
);
10533 tcg_temp_free_i64(tcg_op2
);
10535 tcg_res
[pass
] = tcg_temp_new_i32();
10536 gennarrow(tcg_res
[pass
], tcg_wideres
);
10537 tcg_temp_free_i64(tcg_wideres
);
10540 for (pass
= 0; pass
< 2; pass
++) {
10541 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10542 tcg_temp_free_i32(tcg_res
[pass
]);
10544 clear_vec_high(s
, is_q
, rd
);
10547 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10549 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10550 * is the only three-reg-diff instruction which produces a
10551 * 128-bit wide result from a single operation. However since
10552 * it's possible to calculate the two halves more or less
10553 * separately we just use two helper calls.
10555 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10556 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10557 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10559 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10560 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10561 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10562 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10563 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10564 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10566 tcg_temp_free_i64(tcg_op1
);
10567 tcg_temp_free_i64(tcg_op2
);
10568 tcg_temp_free_i64(tcg_res
);
10571 /* AdvSIMD three different
10572 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10573 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10574 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10575 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10577 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10579 /* Instructions in this group fall into three basic classes
10580 * (in each case with the operation working on each element in
10581 * the input vectors):
10582 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10584 * (2) wide 64 x 128 -> 128
10585 * (3) narrowing 128 x 128 -> 64
10586 * Here we do initial decode, catch unallocated cases and
10587 * dispatch to separate functions for each class.
10589 int is_q
= extract32(insn
, 30, 1);
10590 int is_u
= extract32(insn
, 29, 1);
10591 int size
= extract32(insn
, 22, 2);
10592 int opcode
= extract32(insn
, 12, 4);
10593 int rm
= extract32(insn
, 16, 5);
10594 int rn
= extract32(insn
, 5, 5);
10595 int rd
= extract32(insn
, 0, 5);
10598 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10599 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10600 /* 64 x 128 -> 128 */
10602 unallocated_encoding(s
);
10605 if (!fp_access_check(s
)) {
10608 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10610 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10611 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10612 /* 128 x 128 -> 64 */
10614 unallocated_encoding(s
);
10617 if (!fp_access_check(s
)) {
10620 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10622 case 14: /* PMULL, PMULL2 */
10623 if (is_u
|| size
== 1 || size
== 2) {
10624 unallocated_encoding(s
);
10628 if (!dc_isar_feature(aa64_pmull
, s
)) {
10629 unallocated_encoding(s
);
10632 if (!fp_access_check(s
)) {
10635 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10639 case 9: /* SQDMLAL, SQDMLAL2 */
10640 case 11: /* SQDMLSL, SQDMLSL2 */
10641 case 13: /* SQDMULL, SQDMULL2 */
10642 if (is_u
|| size
== 0) {
10643 unallocated_encoding(s
);
10647 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10648 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10649 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10650 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10651 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10652 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10653 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10654 /* 64 x 64 -> 128 */
10656 unallocated_encoding(s
);
10660 if (!fp_access_check(s
)) {
10664 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10667 /* opcode 15 not allocated */
10668 unallocated_encoding(s
);
10673 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10674 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10676 int rd
= extract32(insn
, 0, 5);
10677 int rn
= extract32(insn
, 5, 5);
10678 int rm
= extract32(insn
, 16, 5);
10679 int size
= extract32(insn
, 22, 2);
10680 bool is_u
= extract32(insn
, 29, 1);
10681 bool is_q
= extract32(insn
, 30, 1);
10683 if (!fp_access_check(s
)) {
10687 switch (size
+ 4 * is_u
) {
10689 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10692 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10695 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10698 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10701 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10704 case 5: /* BSL bitwise select */
10705 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10707 case 6: /* BIT, bitwise insert if true */
10708 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10710 case 7: /* BIF, bitwise insert if false */
10711 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10715 g_assert_not_reached();
10719 /* Pairwise op subgroup of C3.6.16.
10721 * This is called directly or via the handle_3same_float for float pairwise
10722 * operations where the opcode and size are calculated differently.
10724 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10725 int size
, int rn
, int rm
, int rd
)
10730 /* Floating point operations need fpst */
10731 if (opcode
>= 0x58) {
10732 fpst
= get_fpstatus_ptr(false);
10737 if (!fp_access_check(s
)) {
10741 /* These operations work on the concatenated rm:rn, with each pair of
10742 * adjacent elements being operated on to produce an element in the result.
10745 TCGv_i64 tcg_res
[2];
10747 for (pass
= 0; pass
< 2; pass
++) {
10748 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10749 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10750 int passreg
= (pass
== 0) ? rn
: rm
;
10752 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10753 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10754 tcg_res
[pass
] = tcg_temp_new_i64();
10757 case 0x17: /* ADDP */
10758 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10760 case 0x58: /* FMAXNMP */
10761 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10763 case 0x5a: /* FADDP */
10764 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10766 case 0x5e: /* FMAXP */
10767 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10769 case 0x78: /* FMINNMP */
10770 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10772 case 0x7e: /* FMINP */
10773 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10776 g_assert_not_reached();
10779 tcg_temp_free_i64(tcg_op1
);
10780 tcg_temp_free_i64(tcg_op2
);
10783 for (pass
= 0; pass
< 2; pass
++) {
10784 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10785 tcg_temp_free_i64(tcg_res
[pass
]);
10788 int maxpass
= is_q
? 4 : 2;
10789 TCGv_i32 tcg_res
[4];
10791 for (pass
= 0; pass
< maxpass
; pass
++) {
10792 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10793 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10794 NeonGenTwoOpFn
*genfn
= NULL
;
10795 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10796 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10798 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10799 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10800 tcg_res
[pass
] = tcg_temp_new_i32();
10803 case 0x17: /* ADDP */
10805 static NeonGenTwoOpFn
* const fns
[3] = {
10806 gen_helper_neon_padd_u8
,
10807 gen_helper_neon_padd_u16
,
10813 case 0x14: /* SMAXP, UMAXP */
10815 static NeonGenTwoOpFn
* const fns
[3][2] = {
10816 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10817 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10818 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10820 genfn
= fns
[size
][u
];
10823 case 0x15: /* SMINP, UMINP */
10825 static NeonGenTwoOpFn
* const fns
[3][2] = {
10826 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10827 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10828 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10830 genfn
= fns
[size
][u
];
10833 /* The FP operations are all on single floats (32 bit) */
10834 case 0x58: /* FMAXNMP */
10835 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10837 case 0x5a: /* FADDP */
10838 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10840 case 0x5e: /* FMAXP */
10841 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10843 case 0x78: /* FMINNMP */
10844 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10846 case 0x7e: /* FMINP */
10847 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10850 g_assert_not_reached();
10853 /* FP ops called directly, otherwise call now */
10855 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10858 tcg_temp_free_i32(tcg_op1
);
10859 tcg_temp_free_i32(tcg_op2
);
10862 for (pass
= 0; pass
< maxpass
; pass
++) {
10863 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10864 tcg_temp_free_i32(tcg_res
[pass
]);
10866 clear_vec_high(s
, is_q
, rd
);
10870 tcg_temp_free_ptr(fpst
);
10874 /* Floating point op subgroup of C3.6.16. */
10875 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10877 /* For floating point ops, the U, size[1] and opcode bits
10878 * together indicate the operation. size[0] indicates single
10881 int fpopcode
= extract32(insn
, 11, 5)
10882 | (extract32(insn
, 23, 1) << 5)
10883 | (extract32(insn
, 29, 1) << 6);
10884 int is_q
= extract32(insn
, 30, 1);
10885 int size
= extract32(insn
, 22, 1);
10886 int rm
= extract32(insn
, 16, 5);
10887 int rn
= extract32(insn
, 5, 5);
10888 int rd
= extract32(insn
, 0, 5);
10890 int datasize
= is_q
? 128 : 64;
10891 int esize
= 32 << size
;
10892 int elements
= datasize
/ esize
;
10894 if (size
== 1 && !is_q
) {
10895 unallocated_encoding(s
);
10899 switch (fpopcode
) {
10900 case 0x58: /* FMAXNMP */
10901 case 0x5a: /* FADDP */
10902 case 0x5e: /* FMAXP */
10903 case 0x78: /* FMINNMP */
10904 case 0x7e: /* FMINP */
10905 if (size
&& !is_q
) {
10906 unallocated_encoding(s
);
10909 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10912 case 0x1b: /* FMULX */
10913 case 0x1f: /* FRECPS */
10914 case 0x3f: /* FRSQRTS */
10915 case 0x5d: /* FACGE */
10916 case 0x7d: /* FACGT */
10917 case 0x19: /* FMLA */
10918 case 0x39: /* FMLS */
10919 case 0x18: /* FMAXNM */
10920 case 0x1a: /* FADD */
10921 case 0x1c: /* FCMEQ */
10922 case 0x1e: /* FMAX */
10923 case 0x38: /* FMINNM */
10924 case 0x3a: /* FSUB */
10925 case 0x3e: /* FMIN */
10926 case 0x5b: /* FMUL */
10927 case 0x5c: /* FCMGE */
10928 case 0x5f: /* FDIV */
10929 case 0x7a: /* FABD */
10930 case 0x7c: /* FCMGT */
10931 if (!fp_access_check(s
)) {
10934 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10937 case 0x1d: /* FMLAL */
10938 case 0x3d: /* FMLSL */
10939 case 0x59: /* FMLAL2 */
10940 case 0x79: /* FMLSL2 */
10941 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
10942 unallocated_encoding(s
);
10945 if (fp_access_check(s
)) {
10946 int is_s
= extract32(insn
, 23, 1);
10947 int is_2
= extract32(insn
, 29, 1);
10948 int data
= (is_2
<< 1) | is_s
;
10949 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
10950 vec_full_reg_offset(s
, rn
),
10951 vec_full_reg_offset(s
, rm
), cpu_env
,
10952 is_q
? 16 : 8, vec_full_reg_size(s
),
10953 data
, gen_helper_gvec_fmlal_a64
);
10958 unallocated_encoding(s
);
10963 /* Integer op subgroup of C3.6.16. */
10964 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10966 int is_q
= extract32(insn
, 30, 1);
10967 int u
= extract32(insn
, 29, 1);
10968 int size
= extract32(insn
, 22, 2);
10969 int opcode
= extract32(insn
, 11, 5);
10970 int rm
= extract32(insn
, 16, 5);
10971 int rn
= extract32(insn
, 5, 5);
10972 int rd
= extract32(insn
, 0, 5);
10977 case 0x13: /* MUL, PMUL */
10978 if (u
&& size
!= 0) {
10979 unallocated_encoding(s
);
10983 case 0x0: /* SHADD, UHADD */
10984 case 0x2: /* SRHADD, URHADD */
10985 case 0x4: /* SHSUB, UHSUB */
10986 case 0xc: /* SMAX, UMAX */
10987 case 0xd: /* SMIN, UMIN */
10988 case 0xe: /* SABD, UABD */
10989 case 0xf: /* SABA, UABA */
10990 case 0x12: /* MLA, MLS */
10992 unallocated_encoding(s
);
10996 case 0x16: /* SQDMULH, SQRDMULH */
10997 if (size
== 0 || size
== 3) {
10998 unallocated_encoding(s
);
11003 if (size
== 3 && !is_q
) {
11004 unallocated_encoding(s
);
11010 if (!fp_access_check(s
)) {
11015 case 0x01: /* SQADD, UQADD */
11016 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11017 offsetof(CPUARMState
, vfp
.qc
),
11018 vec_full_reg_offset(s
, rn
),
11019 vec_full_reg_offset(s
, rm
),
11020 is_q
? 16 : 8, vec_full_reg_size(s
),
11021 (u
? uqadd_op
: sqadd_op
) + size
);
11023 case 0x05: /* SQSUB, UQSUB */
11024 tcg_gen_gvec_4(vec_full_reg_offset(s
, rd
),
11025 offsetof(CPUARMState
, vfp
.qc
),
11026 vec_full_reg_offset(s
, rn
),
11027 vec_full_reg_offset(s
, rm
),
11028 is_q
? 16 : 8, vec_full_reg_size(s
),
11029 (u
? uqsub_op
: sqsub_op
) + size
);
11031 case 0x0c: /* SMAX, UMAX */
11033 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11035 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11038 case 0x0d: /* SMIN, UMIN */
11040 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11042 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11045 case 0x10: /* ADD, SUB */
11047 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11049 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11052 case 0x13: /* MUL, PMUL */
11053 if (!u
) { /* MUL */
11054 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11058 case 0x12: /* MLA, MLS */
11060 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
11062 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
11066 if (!u
) { /* CMTST */
11067 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
11071 cond
= TCG_COND_EQ
;
11073 case 0x06: /* CMGT, CMHI */
11074 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11076 case 0x07: /* CMGE, CMHS */
11077 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11079 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11080 vec_full_reg_offset(s
, rn
),
11081 vec_full_reg_offset(s
, rm
),
11082 is_q
? 16 : 8, vec_full_reg_size(s
));
11088 for (pass
= 0; pass
< 2; pass
++) {
11089 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11090 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11091 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11093 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11094 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11096 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11098 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11100 tcg_temp_free_i64(tcg_res
);
11101 tcg_temp_free_i64(tcg_op1
);
11102 tcg_temp_free_i64(tcg_op2
);
11105 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11106 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11107 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11108 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11109 NeonGenTwoOpFn
*genfn
= NULL
;
11110 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11112 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11113 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11116 case 0x0: /* SHADD, UHADD */
11118 static NeonGenTwoOpFn
* const fns
[3][2] = {
11119 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11120 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11121 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11123 genfn
= fns
[size
][u
];
11126 case 0x2: /* SRHADD, URHADD */
11128 static NeonGenTwoOpFn
* const fns
[3][2] = {
11129 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11130 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11131 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11133 genfn
= fns
[size
][u
];
11136 case 0x4: /* SHSUB, UHSUB */
11138 static NeonGenTwoOpFn
* const fns
[3][2] = {
11139 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11140 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11141 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11143 genfn
= fns
[size
][u
];
11146 case 0x8: /* SSHL, USHL */
11148 static NeonGenTwoOpFn
* const fns
[3][2] = {
11149 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11150 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11151 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11153 genfn
= fns
[size
][u
];
11156 case 0x9: /* SQSHL, UQSHL */
11158 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11159 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11160 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11161 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11163 genenvfn
= fns
[size
][u
];
11166 case 0xa: /* SRSHL, URSHL */
11168 static NeonGenTwoOpFn
* const fns
[3][2] = {
11169 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11170 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11171 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11173 genfn
= fns
[size
][u
];
11176 case 0xb: /* SQRSHL, UQRSHL */
11178 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11179 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11180 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11181 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11183 genenvfn
= fns
[size
][u
];
11186 case 0xe: /* SABD, UABD */
11187 case 0xf: /* SABA, UABA */
11189 static NeonGenTwoOpFn
* const fns
[3][2] = {
11190 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11191 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11192 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11194 genfn
= fns
[size
][u
];
11197 case 0x13: /* MUL, PMUL */
11198 assert(u
); /* PMUL */
11200 genfn
= gen_helper_neon_mul_p8
;
11202 case 0x16: /* SQDMULH, SQRDMULH */
11204 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11205 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11206 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11208 assert(size
== 1 || size
== 2);
11209 genenvfn
= fns
[size
- 1][u
];
11213 g_assert_not_reached();
11217 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11219 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11222 if (opcode
== 0xf) {
11223 /* SABA, UABA: accumulating ops */
11224 static NeonGenTwoOpFn
* const fns
[3] = {
11225 gen_helper_neon_add_u8
,
11226 gen_helper_neon_add_u16
,
11230 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11231 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11234 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11236 tcg_temp_free_i32(tcg_res
);
11237 tcg_temp_free_i32(tcg_op1
);
11238 tcg_temp_free_i32(tcg_op2
);
11241 clear_vec_high(s
, is_q
, rd
);
11244 /* AdvSIMD three same
11245 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11246 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11247 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11248 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11250 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11252 int opcode
= extract32(insn
, 11, 5);
11255 case 0x3: /* logic ops */
11256 disas_simd_3same_logic(s
, insn
);
11258 case 0x17: /* ADDP */
11259 case 0x14: /* SMAXP, UMAXP */
11260 case 0x15: /* SMINP, UMINP */
11262 /* Pairwise operations */
11263 int is_q
= extract32(insn
, 30, 1);
11264 int u
= extract32(insn
, 29, 1);
11265 int size
= extract32(insn
, 22, 2);
11266 int rm
= extract32(insn
, 16, 5);
11267 int rn
= extract32(insn
, 5, 5);
11268 int rd
= extract32(insn
, 0, 5);
11269 if (opcode
== 0x17) {
11270 if (u
|| (size
== 3 && !is_q
)) {
11271 unallocated_encoding(s
);
11276 unallocated_encoding(s
);
11280 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11283 case 0x18 ... 0x31:
11284 /* floating point ops, sz[1] and U are part of opcode */
11285 disas_simd_3same_float(s
, insn
);
11288 disas_simd_3same_int(s
, insn
);
11294 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11296 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11297 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11298 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11299 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11301 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11302 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11305 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11307 int opcode
, fpopcode
;
11308 int is_q
, u
, a
, rm
, rn
, rd
;
11309 int datasize
, elements
;
11312 bool pairwise
= false;
11314 if (!dc_isar_feature(aa64_fp16
, s
)) {
11315 unallocated_encoding(s
);
11319 if (!fp_access_check(s
)) {
11323 /* For these floating point ops, the U, a and opcode bits
11324 * together indicate the operation.
11326 opcode
= extract32(insn
, 11, 3);
11327 u
= extract32(insn
, 29, 1);
11328 a
= extract32(insn
, 23, 1);
11329 is_q
= extract32(insn
, 30, 1);
11330 rm
= extract32(insn
, 16, 5);
11331 rn
= extract32(insn
, 5, 5);
11332 rd
= extract32(insn
, 0, 5);
11334 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11335 datasize
= is_q
? 128 : 64;
11336 elements
= datasize
/ 16;
11338 switch (fpopcode
) {
11339 case 0x10: /* FMAXNMP */
11340 case 0x12: /* FADDP */
11341 case 0x16: /* FMAXP */
11342 case 0x18: /* FMINNMP */
11343 case 0x1e: /* FMINP */
11348 fpst
= get_fpstatus_ptr(true);
11351 int maxpass
= is_q
? 8 : 4;
11352 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11353 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11354 TCGv_i32 tcg_res
[8];
11356 for (pass
= 0; pass
< maxpass
; pass
++) {
11357 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11358 int passelt
= (pass
<< 1) & (maxpass
- 1);
11360 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11361 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11362 tcg_res
[pass
] = tcg_temp_new_i32();
11364 switch (fpopcode
) {
11365 case 0x10: /* FMAXNMP */
11366 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11369 case 0x12: /* FADDP */
11370 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11372 case 0x16: /* FMAXP */
11373 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11375 case 0x18: /* FMINNMP */
11376 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11379 case 0x1e: /* FMINP */
11380 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11383 g_assert_not_reached();
11387 for (pass
= 0; pass
< maxpass
; pass
++) {
11388 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11389 tcg_temp_free_i32(tcg_res
[pass
]);
11392 tcg_temp_free_i32(tcg_op1
);
11393 tcg_temp_free_i32(tcg_op2
);
11396 for (pass
= 0; pass
< elements
; pass
++) {
11397 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11398 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11399 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11401 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11402 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11404 switch (fpopcode
) {
11405 case 0x0: /* FMAXNM */
11406 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11408 case 0x1: /* FMLA */
11409 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11410 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11413 case 0x2: /* FADD */
11414 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11416 case 0x3: /* FMULX */
11417 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11419 case 0x4: /* FCMEQ */
11420 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11422 case 0x6: /* FMAX */
11423 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11425 case 0x7: /* FRECPS */
11426 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11428 case 0x8: /* FMINNM */
11429 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11431 case 0x9: /* FMLS */
11432 /* As usual for ARM, separate negation for fused multiply-add */
11433 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11434 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11435 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11438 case 0xa: /* FSUB */
11439 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11441 case 0xe: /* FMIN */
11442 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11444 case 0xf: /* FRSQRTS */
11445 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11447 case 0x13: /* FMUL */
11448 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11450 case 0x14: /* FCMGE */
11451 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11453 case 0x15: /* FACGE */
11454 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11456 case 0x17: /* FDIV */
11457 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11459 case 0x1a: /* FABD */
11460 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11461 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11463 case 0x1c: /* FCMGT */
11464 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11466 case 0x1d: /* FACGT */
11467 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11470 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11471 __func__
, insn
, fpopcode
, s
->pc
);
11472 g_assert_not_reached();
11475 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11476 tcg_temp_free_i32(tcg_res
);
11477 tcg_temp_free_i32(tcg_op1
);
11478 tcg_temp_free_i32(tcg_op2
);
11482 tcg_temp_free_ptr(fpst
);
11484 clear_vec_high(s
, is_q
, rd
);
11487 /* AdvSIMD three same extra
11488 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11489 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11490 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11491 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11493 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11495 int rd
= extract32(insn
, 0, 5);
11496 int rn
= extract32(insn
, 5, 5);
11497 int opcode
= extract32(insn
, 11, 4);
11498 int rm
= extract32(insn
, 16, 5);
11499 int size
= extract32(insn
, 22, 2);
11500 bool u
= extract32(insn
, 29, 1);
11501 bool is_q
= extract32(insn
, 30, 1);
11505 switch (u
* 16 + opcode
) {
11506 case 0x10: /* SQRDMLAH (vector) */
11507 case 0x11: /* SQRDMLSH (vector) */
11508 if (size
!= 1 && size
!= 2) {
11509 unallocated_encoding(s
);
11512 feature
= dc_isar_feature(aa64_rdm
, s
);
11514 case 0x02: /* SDOT (vector) */
11515 case 0x12: /* UDOT (vector) */
11516 if (size
!= MO_32
) {
11517 unallocated_encoding(s
);
11520 feature
= dc_isar_feature(aa64_dp
, s
);
11522 case 0x18: /* FCMLA, #0 */
11523 case 0x19: /* FCMLA, #90 */
11524 case 0x1a: /* FCMLA, #180 */
11525 case 0x1b: /* FCMLA, #270 */
11526 case 0x1c: /* FCADD, #90 */
11527 case 0x1e: /* FCADD, #270 */
11529 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11530 || (size
== 3 && !is_q
)) {
11531 unallocated_encoding(s
);
11534 feature
= dc_isar_feature(aa64_fcma
, s
);
11537 unallocated_encoding(s
);
11541 unallocated_encoding(s
);
11544 if (!fp_access_check(s
)) {
11549 case 0x0: /* SQRDMLAH (vector) */
11552 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11555 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11558 g_assert_not_reached();
11562 case 0x1: /* SQRDMLSH (vector) */
11565 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11568 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11571 g_assert_not_reached();
11575 case 0x2: /* SDOT / UDOT */
11576 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11577 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11580 case 0x8: /* FCMLA, #0 */
11581 case 0x9: /* FCMLA, #90 */
11582 case 0xa: /* FCMLA, #180 */
11583 case 0xb: /* FCMLA, #270 */
11584 rot
= extract32(opcode
, 0, 2);
11587 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11588 gen_helper_gvec_fcmlah
);
11591 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11592 gen_helper_gvec_fcmlas
);
11595 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11596 gen_helper_gvec_fcmlad
);
11599 g_assert_not_reached();
11603 case 0xc: /* FCADD, #90 */
11604 case 0xe: /* FCADD, #270 */
11605 rot
= extract32(opcode
, 1, 1);
11608 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11609 gen_helper_gvec_fcaddh
);
11612 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11613 gen_helper_gvec_fcadds
);
11616 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11617 gen_helper_gvec_fcaddd
);
11620 g_assert_not_reached();
11625 g_assert_not_reached();
11629 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11630 int size
, int rn
, int rd
)
11632 /* Handle 2-reg-misc ops which are widening (so each size element
11633 * in the source becomes a 2*size element in the destination.
11634 * The only instruction like this is FCVTL.
11639 /* 32 -> 64 bit fp conversion */
11640 TCGv_i64 tcg_res
[2];
11641 int srcelt
= is_q
? 2 : 0;
11643 for (pass
= 0; pass
< 2; pass
++) {
11644 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11645 tcg_res
[pass
] = tcg_temp_new_i64();
11647 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11648 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11649 tcg_temp_free_i32(tcg_op
);
11651 for (pass
= 0; pass
< 2; pass
++) {
11652 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11653 tcg_temp_free_i64(tcg_res
[pass
]);
11656 /* 16 -> 32 bit fp conversion */
11657 int srcelt
= is_q
? 4 : 0;
11658 TCGv_i32 tcg_res
[4];
11659 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11660 TCGv_i32 ahp
= get_ahp_flag();
11662 for (pass
= 0; pass
< 4; pass
++) {
11663 tcg_res
[pass
] = tcg_temp_new_i32();
11665 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11666 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11669 for (pass
= 0; pass
< 4; pass
++) {
11670 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11671 tcg_temp_free_i32(tcg_res
[pass
]);
11674 tcg_temp_free_ptr(fpst
);
11675 tcg_temp_free_i32(ahp
);
11679 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11680 bool is_q
, int size
, int rn
, int rd
)
11682 int op
= (opcode
<< 1) | u
;
11683 int opsz
= op
+ size
;
11684 int grp_size
= 3 - opsz
;
11685 int dsize
= is_q
? 128 : 64;
11689 unallocated_encoding(s
);
11693 if (!fp_access_check(s
)) {
11698 /* Special case bytes, use bswap op on each group of elements */
11699 int groups
= dsize
/ (8 << grp_size
);
11701 for (i
= 0; i
< groups
; i
++) {
11702 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11704 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11705 switch (grp_size
) {
11707 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11710 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11713 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11716 g_assert_not_reached();
11718 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11719 tcg_temp_free_i64(tcg_tmp
);
11721 clear_vec_high(s
, is_q
, rd
);
11723 int revmask
= (1 << grp_size
) - 1;
11724 int esize
= 8 << size
;
11725 int elements
= dsize
/ esize
;
11726 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11727 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11728 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11730 for (i
= 0; i
< elements
; i
++) {
11731 int e_rev
= (i
& 0xf) ^ revmask
;
11732 int off
= e_rev
* esize
;
11733 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11735 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11736 tcg_rn
, off
- 64, esize
);
11738 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11741 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11742 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11744 tcg_temp_free_i64(tcg_rd_hi
);
11745 tcg_temp_free_i64(tcg_rd
);
11746 tcg_temp_free_i64(tcg_rn
);
11750 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11751 bool is_q
, int size
, int rn
, int rd
)
11753 /* Implement the pairwise operations from 2-misc:
11754 * SADDLP, UADDLP, SADALP, UADALP.
11755 * These all add pairs of elements in the input to produce a
11756 * double-width result element in the output (possibly accumulating).
11758 bool accum
= (opcode
== 0x6);
11759 int maxpass
= is_q
? 2 : 1;
11761 TCGv_i64 tcg_res
[2];
11764 /* 32 + 32 -> 64 op */
11765 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11767 for (pass
= 0; pass
< maxpass
; pass
++) {
11768 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11769 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11771 tcg_res
[pass
] = tcg_temp_new_i64();
11773 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11774 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11775 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11777 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11778 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11781 tcg_temp_free_i64(tcg_op1
);
11782 tcg_temp_free_i64(tcg_op2
);
11785 for (pass
= 0; pass
< maxpass
; pass
++) {
11786 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11787 NeonGenOneOpFn
*genfn
;
11788 static NeonGenOneOpFn
* const fns
[2][2] = {
11789 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11790 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11793 genfn
= fns
[size
][u
];
11795 tcg_res
[pass
] = tcg_temp_new_i64();
11797 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11798 genfn(tcg_res
[pass
], tcg_op
);
11801 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11803 gen_helper_neon_addl_u16(tcg_res
[pass
],
11804 tcg_res
[pass
], tcg_op
);
11806 gen_helper_neon_addl_u32(tcg_res
[pass
],
11807 tcg_res
[pass
], tcg_op
);
11810 tcg_temp_free_i64(tcg_op
);
11814 tcg_res
[1] = tcg_const_i64(0);
11816 for (pass
= 0; pass
< 2; pass
++) {
11817 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11818 tcg_temp_free_i64(tcg_res
[pass
]);
11822 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11824 /* Implement SHLL and SHLL2 */
11826 int part
= is_q
? 2 : 0;
11827 TCGv_i64 tcg_res
[2];
11829 for (pass
= 0; pass
< 2; pass
++) {
11830 static NeonGenWidenFn
* const widenfns
[3] = {
11831 gen_helper_neon_widen_u8
,
11832 gen_helper_neon_widen_u16
,
11833 tcg_gen_extu_i32_i64
,
11835 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11836 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11838 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11839 tcg_res
[pass
] = tcg_temp_new_i64();
11840 widenfn(tcg_res
[pass
], tcg_op
);
11841 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11843 tcg_temp_free_i32(tcg_op
);
11846 for (pass
= 0; pass
< 2; pass
++) {
11847 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11848 tcg_temp_free_i64(tcg_res
[pass
]);
11852 /* AdvSIMD two reg misc
11853 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11854 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11855 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11856 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11858 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11860 int size
= extract32(insn
, 22, 2);
11861 int opcode
= extract32(insn
, 12, 5);
11862 bool u
= extract32(insn
, 29, 1);
11863 bool is_q
= extract32(insn
, 30, 1);
11864 int rn
= extract32(insn
, 5, 5);
11865 int rd
= extract32(insn
, 0, 5);
11866 bool need_fpstatus
= false;
11867 bool need_rmode
= false;
11869 TCGv_i32 tcg_rmode
;
11870 TCGv_ptr tcg_fpstatus
;
11873 case 0x0: /* REV64, REV32 */
11874 case 0x1: /* REV16 */
11875 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11877 case 0x5: /* CNT, NOT, RBIT */
11878 if (u
&& size
== 0) {
11881 } else if (u
&& size
== 1) {
11884 } else if (!u
&& size
== 0) {
11888 unallocated_encoding(s
);
11890 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11891 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11893 unallocated_encoding(s
);
11896 if (!fp_access_check(s
)) {
11900 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11902 case 0x4: /* CLS, CLZ */
11904 unallocated_encoding(s
);
11908 case 0x2: /* SADDLP, UADDLP */
11909 case 0x6: /* SADALP, UADALP */
11911 unallocated_encoding(s
);
11914 if (!fp_access_check(s
)) {
11917 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11919 case 0x13: /* SHLL, SHLL2 */
11920 if (u
== 0 || size
== 3) {
11921 unallocated_encoding(s
);
11924 if (!fp_access_check(s
)) {
11927 handle_shll(s
, is_q
, size
, rn
, rd
);
11929 case 0xa: /* CMLT */
11931 unallocated_encoding(s
);
11935 case 0x8: /* CMGT, CMGE */
11936 case 0x9: /* CMEQ, CMLE */
11937 case 0xb: /* ABS, NEG */
11938 if (size
== 3 && !is_q
) {
11939 unallocated_encoding(s
);
11943 case 0x3: /* SUQADD, USQADD */
11944 if (size
== 3 && !is_q
) {
11945 unallocated_encoding(s
);
11948 if (!fp_access_check(s
)) {
11951 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11953 case 0x7: /* SQABS, SQNEG */
11954 if (size
== 3 && !is_q
) {
11955 unallocated_encoding(s
);
11960 case 0x16 ... 0x1d:
11963 /* Floating point: U, size[1] and opcode indicate operation;
11964 * size[0] indicates single or double precision.
11966 int is_double
= extract32(size
, 0, 1);
11967 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11968 size
= is_double
? 3 : 2;
11970 case 0x2f: /* FABS */
11971 case 0x6f: /* FNEG */
11972 if (size
== 3 && !is_q
) {
11973 unallocated_encoding(s
);
11977 case 0x1d: /* SCVTF */
11978 case 0x5d: /* UCVTF */
11980 bool is_signed
= (opcode
== 0x1d) ? true : false;
11981 int elements
= is_double
? 2 : is_q
? 4 : 2;
11982 if (is_double
&& !is_q
) {
11983 unallocated_encoding(s
);
11986 if (!fp_access_check(s
)) {
11989 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11992 case 0x2c: /* FCMGT (zero) */
11993 case 0x2d: /* FCMEQ (zero) */
11994 case 0x2e: /* FCMLT (zero) */
11995 case 0x6c: /* FCMGE (zero) */
11996 case 0x6d: /* FCMLE (zero) */
11997 if (size
== 3 && !is_q
) {
11998 unallocated_encoding(s
);
12001 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12003 case 0x7f: /* FSQRT */
12004 if (size
== 3 && !is_q
) {
12005 unallocated_encoding(s
);
12009 case 0x1a: /* FCVTNS */
12010 case 0x1b: /* FCVTMS */
12011 case 0x3a: /* FCVTPS */
12012 case 0x3b: /* FCVTZS */
12013 case 0x5a: /* FCVTNU */
12014 case 0x5b: /* FCVTMU */
12015 case 0x7a: /* FCVTPU */
12016 case 0x7b: /* FCVTZU */
12017 need_fpstatus
= true;
12019 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12020 if (size
== 3 && !is_q
) {
12021 unallocated_encoding(s
);
12025 case 0x5c: /* FCVTAU */
12026 case 0x1c: /* FCVTAS */
12027 need_fpstatus
= true;
12029 rmode
= FPROUNDING_TIEAWAY
;
12030 if (size
== 3 && !is_q
) {
12031 unallocated_encoding(s
);
12035 case 0x3c: /* URECPE */
12037 unallocated_encoding(s
);
12041 case 0x3d: /* FRECPE */
12042 case 0x7d: /* FRSQRTE */
12043 if (size
== 3 && !is_q
) {
12044 unallocated_encoding(s
);
12047 if (!fp_access_check(s
)) {
12050 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12052 case 0x56: /* FCVTXN, FCVTXN2 */
12054 unallocated_encoding(s
);
12058 case 0x16: /* FCVTN, FCVTN2 */
12059 /* handle_2misc_narrow does a 2*size -> size operation, but these
12060 * instructions encode the source size rather than dest size.
12062 if (!fp_access_check(s
)) {
12065 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12067 case 0x17: /* FCVTL, FCVTL2 */
12068 if (!fp_access_check(s
)) {
12071 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12073 case 0x18: /* FRINTN */
12074 case 0x19: /* FRINTM */
12075 case 0x38: /* FRINTP */
12076 case 0x39: /* FRINTZ */
12078 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12080 case 0x59: /* FRINTX */
12081 case 0x79: /* FRINTI */
12082 need_fpstatus
= true;
12083 if (size
== 3 && !is_q
) {
12084 unallocated_encoding(s
);
12088 case 0x58: /* FRINTA */
12090 rmode
= FPROUNDING_TIEAWAY
;
12091 need_fpstatus
= true;
12092 if (size
== 3 && !is_q
) {
12093 unallocated_encoding(s
);
12097 case 0x7c: /* URSQRTE */
12099 unallocated_encoding(s
);
12102 need_fpstatus
= true;
12105 unallocated_encoding(s
);
12111 unallocated_encoding(s
);
12115 if (!fp_access_check(s
)) {
12119 if (need_fpstatus
|| need_rmode
) {
12120 tcg_fpstatus
= get_fpstatus_ptr(false);
12122 tcg_fpstatus
= NULL
;
12125 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12126 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12133 if (u
&& size
== 0) { /* NOT */
12134 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12140 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12147 /* All 64-bit element operations can be shared with scalar 2misc */
12150 /* Coverity claims (size == 3 && !is_q) has been eliminated
12151 * from all paths leading to here.
12153 tcg_debug_assert(is_q
);
12154 for (pass
= 0; pass
< 2; pass
++) {
12155 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12156 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12158 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12160 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12161 tcg_rmode
, tcg_fpstatus
);
12163 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12165 tcg_temp_free_i64(tcg_res
);
12166 tcg_temp_free_i64(tcg_op
);
12171 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12172 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12173 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12176 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12179 /* Special cases for 32 bit elements */
12181 case 0xa: /* CMLT */
12182 /* 32 bit integer comparison against zero, result is
12183 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12186 cond
= TCG_COND_LT
;
12188 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12189 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12191 case 0x8: /* CMGT, CMGE */
12192 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12194 case 0x9: /* CMEQ, CMLE */
12195 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12197 case 0x4: /* CLS */
12199 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12201 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12204 case 0x7: /* SQABS, SQNEG */
12206 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12208 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12211 case 0xb: /* ABS, NEG */
12213 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12215 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12216 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12217 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12218 tcg_zero
, tcg_op
, tcg_res
);
12219 tcg_temp_free_i32(tcg_zero
);
12222 case 0x2f: /* FABS */
12223 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12225 case 0x6f: /* FNEG */
12226 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12228 case 0x7f: /* FSQRT */
12229 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12231 case 0x1a: /* FCVTNS */
12232 case 0x1b: /* FCVTMS */
12233 case 0x1c: /* FCVTAS */
12234 case 0x3a: /* FCVTPS */
12235 case 0x3b: /* FCVTZS */
12237 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12238 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12239 tcg_shift
, tcg_fpstatus
);
12240 tcg_temp_free_i32(tcg_shift
);
12243 case 0x5a: /* FCVTNU */
12244 case 0x5b: /* FCVTMU */
12245 case 0x5c: /* FCVTAU */
12246 case 0x7a: /* FCVTPU */
12247 case 0x7b: /* FCVTZU */
12249 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12250 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12251 tcg_shift
, tcg_fpstatus
);
12252 tcg_temp_free_i32(tcg_shift
);
12255 case 0x18: /* FRINTN */
12256 case 0x19: /* FRINTM */
12257 case 0x38: /* FRINTP */
12258 case 0x39: /* FRINTZ */
12259 case 0x58: /* FRINTA */
12260 case 0x79: /* FRINTI */
12261 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12263 case 0x59: /* FRINTX */
12264 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12266 case 0x7c: /* URSQRTE */
12267 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12270 g_assert_not_reached();
12273 /* Use helpers for 8 and 16 bit elements */
12275 case 0x5: /* CNT, RBIT */
12276 /* For these two insns size is part of the opcode specifier
12277 * (handled earlier); they always operate on byte elements.
12280 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12282 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12285 case 0x7: /* SQABS, SQNEG */
12287 NeonGenOneOpEnvFn
*genfn
;
12288 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12289 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12290 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12292 genfn
= fns
[size
][u
];
12293 genfn(tcg_res
, cpu_env
, tcg_op
);
12296 case 0x8: /* CMGT, CMGE */
12297 case 0x9: /* CMEQ, CMLE */
12298 case 0xa: /* CMLT */
12300 static NeonGenTwoOpFn
* const fns
[3][2] = {
12301 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12302 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12303 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12305 NeonGenTwoOpFn
*genfn
;
12308 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12310 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12311 comp
= (opcode
- 0x8) * 2 + u
;
12312 /* ...but LE, LT are implemented as reverse GE, GT */
12313 reverse
= (comp
> 2);
12317 genfn
= fns
[comp
][size
];
12319 genfn(tcg_res
, tcg_zero
, tcg_op
);
12321 genfn(tcg_res
, tcg_op
, tcg_zero
);
12323 tcg_temp_free_i32(tcg_zero
);
12326 case 0xb: /* ABS, NEG */
12328 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12330 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12332 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12334 tcg_temp_free_i32(tcg_zero
);
12337 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12339 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12343 case 0x4: /* CLS, CLZ */
12346 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12348 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12352 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12354 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12359 g_assert_not_reached();
12363 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12365 tcg_temp_free_i32(tcg_res
);
12366 tcg_temp_free_i32(tcg_op
);
12369 clear_vec_high(s
, is_q
, rd
);
12372 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12373 tcg_temp_free_i32(tcg_rmode
);
12375 if (need_fpstatus
) {
12376 tcg_temp_free_ptr(tcg_fpstatus
);
12380 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12382 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12383 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12384 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12385 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12386 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12387 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12389 * This actually covers two groups where scalar access is governed by
12390 * bit 28. A bunch of the instructions (float to integral) only exist
12391 * in the vector form and are un-allocated for the scalar decode. Also
12392 * in the scalar decode Q is always 1.
12394 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12396 int fpop
, opcode
, a
, u
;
12400 bool only_in_vector
= false;
12403 TCGv_i32 tcg_rmode
= NULL
;
12404 TCGv_ptr tcg_fpstatus
= NULL
;
12405 bool need_rmode
= false;
12406 bool need_fpst
= true;
12409 if (!dc_isar_feature(aa64_fp16
, s
)) {
12410 unallocated_encoding(s
);
12414 rd
= extract32(insn
, 0, 5);
12415 rn
= extract32(insn
, 5, 5);
12417 a
= extract32(insn
, 23, 1);
12418 u
= extract32(insn
, 29, 1);
12419 is_scalar
= extract32(insn
, 28, 1);
12420 is_q
= extract32(insn
, 30, 1);
12422 opcode
= extract32(insn
, 12, 5);
12423 fpop
= deposit32(opcode
, 5, 1, a
);
12424 fpop
= deposit32(fpop
, 6, 1, u
);
12426 rd
= extract32(insn
, 0, 5);
12427 rn
= extract32(insn
, 5, 5);
12430 case 0x1d: /* SCVTF */
12431 case 0x5d: /* UCVTF */
12438 elements
= (is_q
? 8 : 4);
12441 if (!fp_access_check(s
)) {
12444 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12448 case 0x2c: /* FCMGT (zero) */
12449 case 0x2d: /* FCMEQ (zero) */
12450 case 0x2e: /* FCMLT (zero) */
12451 case 0x6c: /* FCMGE (zero) */
12452 case 0x6d: /* FCMLE (zero) */
12453 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12455 case 0x3d: /* FRECPE */
12456 case 0x3f: /* FRECPX */
12458 case 0x18: /* FRINTN */
12460 only_in_vector
= true;
12461 rmode
= FPROUNDING_TIEEVEN
;
12463 case 0x19: /* FRINTM */
12465 only_in_vector
= true;
12466 rmode
= FPROUNDING_NEGINF
;
12468 case 0x38: /* FRINTP */
12470 only_in_vector
= true;
12471 rmode
= FPROUNDING_POSINF
;
12473 case 0x39: /* FRINTZ */
12475 only_in_vector
= true;
12476 rmode
= FPROUNDING_ZERO
;
12478 case 0x58: /* FRINTA */
12480 only_in_vector
= true;
12481 rmode
= FPROUNDING_TIEAWAY
;
12483 case 0x59: /* FRINTX */
12484 case 0x79: /* FRINTI */
12485 only_in_vector
= true;
12486 /* current rounding mode */
12488 case 0x1a: /* FCVTNS */
12490 rmode
= FPROUNDING_TIEEVEN
;
12492 case 0x1b: /* FCVTMS */
12494 rmode
= FPROUNDING_NEGINF
;
12496 case 0x1c: /* FCVTAS */
12498 rmode
= FPROUNDING_TIEAWAY
;
12500 case 0x3a: /* FCVTPS */
12502 rmode
= FPROUNDING_POSINF
;
12504 case 0x3b: /* FCVTZS */
12506 rmode
= FPROUNDING_ZERO
;
12508 case 0x5a: /* FCVTNU */
12510 rmode
= FPROUNDING_TIEEVEN
;
12512 case 0x5b: /* FCVTMU */
12514 rmode
= FPROUNDING_NEGINF
;
12516 case 0x5c: /* FCVTAU */
12518 rmode
= FPROUNDING_TIEAWAY
;
12520 case 0x7a: /* FCVTPU */
12522 rmode
= FPROUNDING_POSINF
;
12524 case 0x7b: /* FCVTZU */
12526 rmode
= FPROUNDING_ZERO
;
12528 case 0x2f: /* FABS */
12529 case 0x6f: /* FNEG */
12532 case 0x7d: /* FRSQRTE */
12533 case 0x7f: /* FSQRT (vector) */
12536 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12537 g_assert_not_reached();
12541 /* Check additional constraints for the scalar encoding */
12544 unallocated_encoding(s
);
12547 /* FRINTxx is only in the vector form */
12548 if (only_in_vector
) {
12549 unallocated_encoding(s
);
12554 if (!fp_access_check(s
)) {
12558 if (need_rmode
|| need_fpst
) {
12559 tcg_fpstatus
= get_fpstatus_ptr(true);
12563 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12564 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12568 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12569 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12572 case 0x1a: /* FCVTNS */
12573 case 0x1b: /* FCVTMS */
12574 case 0x1c: /* FCVTAS */
12575 case 0x3a: /* FCVTPS */
12576 case 0x3b: /* FCVTZS */
12577 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12579 case 0x3d: /* FRECPE */
12580 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12582 case 0x3f: /* FRECPX */
12583 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12585 case 0x5a: /* FCVTNU */
12586 case 0x5b: /* FCVTMU */
12587 case 0x5c: /* FCVTAU */
12588 case 0x7a: /* FCVTPU */
12589 case 0x7b: /* FCVTZU */
12590 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12592 case 0x6f: /* FNEG */
12593 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12595 case 0x7d: /* FRSQRTE */
12596 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12599 g_assert_not_reached();
12602 /* limit any sign extension going on */
12603 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12604 write_fp_sreg(s
, rd
, tcg_res
);
12606 tcg_temp_free_i32(tcg_res
);
12607 tcg_temp_free_i32(tcg_op
);
12609 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12610 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12611 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12613 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12616 case 0x1a: /* FCVTNS */
12617 case 0x1b: /* FCVTMS */
12618 case 0x1c: /* FCVTAS */
12619 case 0x3a: /* FCVTPS */
12620 case 0x3b: /* FCVTZS */
12621 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12623 case 0x3d: /* FRECPE */
12624 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12626 case 0x5a: /* FCVTNU */
12627 case 0x5b: /* FCVTMU */
12628 case 0x5c: /* FCVTAU */
12629 case 0x7a: /* FCVTPU */
12630 case 0x7b: /* FCVTZU */
12631 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12633 case 0x18: /* FRINTN */
12634 case 0x19: /* FRINTM */
12635 case 0x38: /* FRINTP */
12636 case 0x39: /* FRINTZ */
12637 case 0x58: /* FRINTA */
12638 case 0x79: /* FRINTI */
12639 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12641 case 0x59: /* FRINTX */
12642 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12644 case 0x2f: /* FABS */
12645 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12647 case 0x6f: /* FNEG */
12648 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12650 case 0x7d: /* FRSQRTE */
12651 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12653 case 0x7f: /* FSQRT */
12654 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12657 g_assert_not_reached();
12660 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12662 tcg_temp_free_i32(tcg_res
);
12663 tcg_temp_free_i32(tcg_op
);
12666 clear_vec_high(s
, is_q
, rd
);
12670 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12671 tcg_temp_free_i32(tcg_rmode
);
12674 if (tcg_fpstatus
) {
12675 tcg_temp_free_ptr(tcg_fpstatus
);
12679 /* AdvSIMD scalar x indexed element
12680 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12681 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12682 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12683 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12684 * AdvSIMD vector x indexed element
12685 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12686 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12687 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12688 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12690 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12692 /* This encoding has two kinds of instruction:
12693 * normal, where we perform elt x idxelt => elt for each
12694 * element in the vector
12695 * long, where we perform elt x idxelt and generate a result of
12696 * double the width of the input element
12697 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12699 bool is_scalar
= extract32(insn
, 28, 1);
12700 bool is_q
= extract32(insn
, 30, 1);
12701 bool u
= extract32(insn
, 29, 1);
12702 int size
= extract32(insn
, 22, 2);
12703 int l
= extract32(insn
, 21, 1);
12704 int m
= extract32(insn
, 20, 1);
12705 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12706 int rm
= extract32(insn
, 16, 4);
12707 int opcode
= extract32(insn
, 12, 4);
12708 int h
= extract32(insn
, 11, 1);
12709 int rn
= extract32(insn
, 5, 5);
12710 int rd
= extract32(insn
, 0, 5);
12711 bool is_long
= false;
12713 bool is_fp16
= false;
12717 switch (16 * u
+ opcode
) {
12718 case 0x08: /* MUL */
12719 case 0x10: /* MLA */
12720 case 0x14: /* MLS */
12722 unallocated_encoding(s
);
12726 case 0x02: /* SMLAL, SMLAL2 */
12727 case 0x12: /* UMLAL, UMLAL2 */
12728 case 0x06: /* SMLSL, SMLSL2 */
12729 case 0x16: /* UMLSL, UMLSL2 */
12730 case 0x0a: /* SMULL, SMULL2 */
12731 case 0x1a: /* UMULL, UMULL2 */
12733 unallocated_encoding(s
);
12738 case 0x03: /* SQDMLAL, SQDMLAL2 */
12739 case 0x07: /* SQDMLSL, SQDMLSL2 */
12740 case 0x0b: /* SQDMULL, SQDMULL2 */
12743 case 0x0c: /* SQDMULH */
12744 case 0x0d: /* SQRDMULH */
12746 case 0x01: /* FMLA */
12747 case 0x05: /* FMLS */
12748 case 0x09: /* FMUL */
12749 case 0x19: /* FMULX */
12752 case 0x1d: /* SQRDMLAH */
12753 case 0x1f: /* SQRDMLSH */
12754 if (!dc_isar_feature(aa64_rdm
, s
)) {
12755 unallocated_encoding(s
);
12759 case 0x0e: /* SDOT */
12760 case 0x1e: /* UDOT */
12761 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12762 unallocated_encoding(s
);
12766 case 0x11: /* FCMLA #0 */
12767 case 0x13: /* FCMLA #90 */
12768 case 0x15: /* FCMLA #180 */
12769 case 0x17: /* FCMLA #270 */
12770 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12771 unallocated_encoding(s
);
12776 case 0x00: /* FMLAL */
12777 case 0x04: /* FMLSL */
12778 case 0x18: /* FMLAL2 */
12779 case 0x1c: /* FMLSL2 */
12780 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12781 unallocated_encoding(s
);
12785 /* is_fp, but we pass cpu_env not fp_status. */
12788 unallocated_encoding(s
);
12793 case 1: /* normal fp */
12794 /* convert insn encoded size to TCGMemOp size */
12796 case 0: /* half-precision */
12800 case MO_32
: /* single precision */
12801 case MO_64
: /* double precision */
12804 unallocated_encoding(s
);
12809 case 2: /* complex fp */
12810 /* Each indexable element is a complex pair. */
12815 unallocated_encoding(s
);
12823 unallocated_encoding(s
);
12828 default: /* integer */
12832 unallocated_encoding(s
);
12837 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12838 unallocated_encoding(s
);
12842 /* Given TCGMemOp size, adjust register and indexing. */
12845 index
= h
<< 2 | l
<< 1 | m
;
12848 index
= h
<< 1 | l
;
12853 unallocated_encoding(s
);
12860 g_assert_not_reached();
12863 if (!fp_access_check(s
)) {
12868 fpst
= get_fpstatus_ptr(is_fp16
);
12873 switch (16 * u
+ opcode
) {
12874 case 0x0e: /* SDOT */
12875 case 0x1e: /* UDOT */
12876 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12877 u
? gen_helper_gvec_udot_idx_b
12878 : gen_helper_gvec_sdot_idx_b
);
12880 case 0x11: /* FCMLA #0 */
12881 case 0x13: /* FCMLA #90 */
12882 case 0x15: /* FCMLA #180 */
12883 case 0x17: /* FCMLA #270 */
12885 int rot
= extract32(insn
, 13, 2);
12886 int data
= (index
<< 2) | rot
;
12887 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12888 vec_full_reg_offset(s
, rn
),
12889 vec_full_reg_offset(s
, rm
), fpst
,
12890 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12892 ? gen_helper_gvec_fcmlas_idx
12893 : gen_helper_gvec_fcmlah_idx
);
12894 tcg_temp_free_ptr(fpst
);
12898 case 0x00: /* FMLAL */
12899 case 0x04: /* FMLSL */
12900 case 0x18: /* FMLAL2 */
12901 case 0x1c: /* FMLSL2 */
12903 int is_s
= extract32(opcode
, 2, 1);
12905 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
12906 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12907 vec_full_reg_offset(s
, rn
),
12908 vec_full_reg_offset(s
, rm
), cpu_env
,
12909 is_q
? 16 : 8, vec_full_reg_size(s
),
12910 data
, gen_helper_gvec_fmlal_idx_a64
);
12916 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12919 assert(is_fp
&& is_q
&& !is_long
);
12921 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12923 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12924 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12925 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12927 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12929 switch (16 * u
+ opcode
) {
12930 case 0x05: /* FMLS */
12931 /* As usual for ARM, separate negation for fused multiply-add */
12932 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12934 case 0x01: /* FMLA */
12935 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12936 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12938 case 0x09: /* FMUL */
12939 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12941 case 0x19: /* FMULX */
12942 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12945 g_assert_not_reached();
12948 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12949 tcg_temp_free_i64(tcg_op
);
12950 tcg_temp_free_i64(tcg_res
);
12953 tcg_temp_free_i64(tcg_idx
);
12954 clear_vec_high(s
, !is_scalar
, rd
);
12955 } else if (!is_long
) {
12956 /* 32 bit floating point, or 16 or 32 bit integer.
12957 * For the 16 bit scalar case we use the usual Neon helpers and
12958 * rely on the fact that 0 op 0 == 0 with no side effects.
12960 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12961 int pass
, maxpasses
;
12966 maxpasses
= is_q
? 4 : 2;
12969 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12971 if (size
== 1 && !is_scalar
) {
12972 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12973 * the index into both halves of the 32 bit tcg_idx and then use
12974 * the usual Neon helpers.
12976 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12979 for (pass
= 0; pass
< maxpasses
; pass
++) {
12980 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12981 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12983 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12985 switch (16 * u
+ opcode
) {
12986 case 0x08: /* MUL */
12987 case 0x10: /* MLA */
12988 case 0x14: /* MLS */
12990 static NeonGenTwoOpFn
* const fns
[2][2] = {
12991 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12992 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12994 NeonGenTwoOpFn
*genfn
;
12995 bool is_sub
= opcode
== 0x4;
12998 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13000 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13002 if (opcode
== 0x8) {
13005 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13006 genfn
= fns
[size
- 1][is_sub
];
13007 genfn(tcg_res
, tcg_op
, tcg_res
);
13010 case 0x05: /* FMLS */
13011 case 0x01: /* FMLA */
13012 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13013 is_scalar
? size
: MO_32
);
13016 if (opcode
== 0x5) {
13017 /* As usual for ARM, separate negation for fused
13019 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13022 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13025 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13030 if (opcode
== 0x5) {
13031 /* As usual for ARM, separate negation for
13032 * fused multiply-add */
13033 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13035 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13039 g_assert_not_reached();
13042 case 0x09: /* FMUL */
13046 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13049 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13054 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13057 g_assert_not_reached();
13060 case 0x19: /* FMULX */
13064 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13067 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13072 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13075 g_assert_not_reached();
13078 case 0x0c: /* SQDMULH */
13080 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13083 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13087 case 0x0d: /* SQRDMULH */
13089 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13092 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13096 case 0x1d: /* SQRDMLAH */
13097 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13098 is_scalar
? size
: MO_32
);
13100 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13101 tcg_op
, tcg_idx
, tcg_res
);
13103 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13104 tcg_op
, tcg_idx
, tcg_res
);
13107 case 0x1f: /* SQRDMLSH */
13108 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13109 is_scalar
? size
: MO_32
);
13111 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13112 tcg_op
, tcg_idx
, tcg_res
);
13114 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13115 tcg_op
, tcg_idx
, tcg_res
);
13119 g_assert_not_reached();
13123 write_fp_sreg(s
, rd
, tcg_res
);
13125 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13128 tcg_temp_free_i32(tcg_op
);
13129 tcg_temp_free_i32(tcg_res
);
13132 tcg_temp_free_i32(tcg_idx
);
13133 clear_vec_high(s
, is_q
, rd
);
13135 /* long ops: 16x16->32 or 32x32->64 */
13136 TCGv_i64 tcg_res
[2];
13138 bool satop
= extract32(opcode
, 0, 1);
13139 TCGMemOp memop
= MO_32
;
13146 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13148 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13150 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13151 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13152 TCGv_i64 tcg_passres
;
13158 passelt
= pass
+ (is_q
* 2);
13161 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13163 tcg_res
[pass
] = tcg_temp_new_i64();
13165 if (opcode
== 0xa || opcode
== 0xb) {
13166 /* Non-accumulating ops */
13167 tcg_passres
= tcg_res
[pass
];
13169 tcg_passres
= tcg_temp_new_i64();
13172 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13173 tcg_temp_free_i64(tcg_op
);
13176 /* saturating, doubling */
13177 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13178 tcg_passres
, tcg_passres
);
13181 if (opcode
== 0xa || opcode
== 0xb) {
13185 /* Accumulating op: handle accumulate step */
13186 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13189 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13190 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13192 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13193 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13195 case 0x7: /* SQDMLSL, SQDMLSL2 */
13196 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13198 case 0x3: /* SQDMLAL, SQDMLAL2 */
13199 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13204 g_assert_not_reached();
13206 tcg_temp_free_i64(tcg_passres
);
13208 tcg_temp_free_i64(tcg_idx
);
13210 clear_vec_high(s
, !is_scalar
, rd
);
13212 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13215 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13218 /* The simplest way to handle the 16x16 indexed ops is to
13219 * duplicate the index into both halves of the 32 bit tcg_idx
13220 * and then use the usual Neon helpers.
13222 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13225 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13226 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13227 TCGv_i64 tcg_passres
;
13230 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13232 read_vec_element_i32(s
, tcg_op
, rn
,
13233 pass
+ (is_q
* 2), MO_32
);
13236 tcg_res
[pass
] = tcg_temp_new_i64();
13238 if (opcode
== 0xa || opcode
== 0xb) {
13239 /* Non-accumulating ops */
13240 tcg_passres
= tcg_res
[pass
];
13242 tcg_passres
= tcg_temp_new_i64();
13245 if (memop
& MO_SIGN
) {
13246 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13248 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13251 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13252 tcg_passres
, tcg_passres
);
13254 tcg_temp_free_i32(tcg_op
);
13256 if (opcode
== 0xa || opcode
== 0xb) {
13260 /* Accumulating op: handle accumulate step */
13261 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13264 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13265 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13268 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13269 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13272 case 0x7: /* SQDMLSL, SQDMLSL2 */
13273 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13275 case 0x3: /* SQDMLAL, SQDMLAL2 */
13276 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13281 g_assert_not_reached();
13283 tcg_temp_free_i64(tcg_passres
);
13285 tcg_temp_free_i32(tcg_idx
);
13288 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13293 tcg_res
[1] = tcg_const_i64(0);
13296 for (pass
= 0; pass
< 2; pass
++) {
13297 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13298 tcg_temp_free_i64(tcg_res
[pass
]);
13303 tcg_temp_free_ptr(fpst
);
13308 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13309 * +-----------------+------+-----------+--------+-----+------+------+
13310 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13311 * +-----------------+------+-----------+--------+-----+------+------+
13313 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13315 int size
= extract32(insn
, 22, 2);
13316 int opcode
= extract32(insn
, 12, 5);
13317 int rn
= extract32(insn
, 5, 5);
13318 int rd
= extract32(insn
, 0, 5);
13320 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13321 TCGv_i32 tcg_decrypt
;
13322 CryptoThreeOpIntFn
*genfn
;
13324 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13325 unallocated_encoding(s
);
13330 case 0x4: /* AESE */
13332 genfn
= gen_helper_crypto_aese
;
13334 case 0x6: /* AESMC */
13336 genfn
= gen_helper_crypto_aesmc
;
13338 case 0x5: /* AESD */
13340 genfn
= gen_helper_crypto_aese
;
13342 case 0x7: /* AESIMC */
13344 genfn
= gen_helper_crypto_aesmc
;
13347 unallocated_encoding(s
);
13351 if (!fp_access_check(s
)) {
13355 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13356 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13357 tcg_decrypt
= tcg_const_i32(decrypt
);
13359 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13361 tcg_temp_free_ptr(tcg_rd_ptr
);
13362 tcg_temp_free_ptr(tcg_rn_ptr
);
13363 tcg_temp_free_i32(tcg_decrypt
);
13366 /* Crypto three-reg SHA
13367 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13368 * +-----------------+------+---+------+---+--------+-----+------+------+
13369 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13370 * +-----------------+------+---+------+---+--------+-----+------+------+
13372 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13374 int size
= extract32(insn
, 22, 2);
13375 int opcode
= extract32(insn
, 12, 3);
13376 int rm
= extract32(insn
, 16, 5);
13377 int rn
= extract32(insn
, 5, 5);
13378 int rd
= extract32(insn
, 0, 5);
13379 CryptoThreeOpFn
*genfn
;
13380 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13384 unallocated_encoding(s
);
13389 case 0: /* SHA1C */
13390 case 1: /* SHA1P */
13391 case 2: /* SHA1M */
13392 case 3: /* SHA1SU0 */
13394 feature
= dc_isar_feature(aa64_sha1
, s
);
13396 case 4: /* SHA256H */
13397 genfn
= gen_helper_crypto_sha256h
;
13398 feature
= dc_isar_feature(aa64_sha256
, s
);
13400 case 5: /* SHA256H2 */
13401 genfn
= gen_helper_crypto_sha256h2
;
13402 feature
= dc_isar_feature(aa64_sha256
, s
);
13404 case 6: /* SHA256SU1 */
13405 genfn
= gen_helper_crypto_sha256su1
;
13406 feature
= dc_isar_feature(aa64_sha256
, s
);
13409 unallocated_encoding(s
);
13414 unallocated_encoding(s
);
13418 if (!fp_access_check(s
)) {
13422 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13423 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13424 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13427 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13429 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13431 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13432 tcg_rm_ptr
, tcg_opcode
);
13433 tcg_temp_free_i32(tcg_opcode
);
13436 tcg_temp_free_ptr(tcg_rd_ptr
);
13437 tcg_temp_free_ptr(tcg_rn_ptr
);
13438 tcg_temp_free_ptr(tcg_rm_ptr
);
13441 /* Crypto two-reg SHA
13442 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13443 * +-----------------+------+-----------+--------+-----+------+------+
13444 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13445 * +-----------------+------+-----------+--------+-----+------+------+
13447 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13449 int size
= extract32(insn
, 22, 2);
13450 int opcode
= extract32(insn
, 12, 5);
13451 int rn
= extract32(insn
, 5, 5);
13452 int rd
= extract32(insn
, 0, 5);
13453 CryptoTwoOpFn
*genfn
;
13455 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13458 unallocated_encoding(s
);
13463 case 0: /* SHA1H */
13464 feature
= dc_isar_feature(aa64_sha1
, s
);
13465 genfn
= gen_helper_crypto_sha1h
;
13467 case 1: /* SHA1SU1 */
13468 feature
= dc_isar_feature(aa64_sha1
, s
);
13469 genfn
= gen_helper_crypto_sha1su1
;
13471 case 2: /* SHA256SU0 */
13472 feature
= dc_isar_feature(aa64_sha256
, s
);
13473 genfn
= gen_helper_crypto_sha256su0
;
13476 unallocated_encoding(s
);
13481 unallocated_encoding(s
);
13485 if (!fp_access_check(s
)) {
13489 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13490 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13492 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13494 tcg_temp_free_ptr(tcg_rd_ptr
);
13495 tcg_temp_free_ptr(tcg_rn_ptr
);
13498 /* Crypto three-reg SHA512
13499 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13500 * +-----------------------+------+---+---+-----+--------+------+------+
13501 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13502 * +-----------------------+------+---+---+-----+--------+------+------+
13504 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13506 int opcode
= extract32(insn
, 10, 2);
13507 int o
= extract32(insn
, 14, 1);
13508 int rm
= extract32(insn
, 16, 5);
13509 int rn
= extract32(insn
, 5, 5);
13510 int rd
= extract32(insn
, 0, 5);
13512 CryptoThreeOpFn
*genfn
;
13516 case 0: /* SHA512H */
13517 feature
= dc_isar_feature(aa64_sha512
, s
);
13518 genfn
= gen_helper_crypto_sha512h
;
13520 case 1: /* SHA512H2 */
13521 feature
= dc_isar_feature(aa64_sha512
, s
);
13522 genfn
= gen_helper_crypto_sha512h2
;
13524 case 2: /* SHA512SU1 */
13525 feature
= dc_isar_feature(aa64_sha512
, s
);
13526 genfn
= gen_helper_crypto_sha512su1
;
13529 feature
= dc_isar_feature(aa64_sha3
, s
);
13535 case 0: /* SM3PARTW1 */
13536 feature
= dc_isar_feature(aa64_sm3
, s
);
13537 genfn
= gen_helper_crypto_sm3partw1
;
13539 case 1: /* SM3PARTW2 */
13540 feature
= dc_isar_feature(aa64_sm3
, s
);
13541 genfn
= gen_helper_crypto_sm3partw2
;
13543 case 2: /* SM4EKEY */
13544 feature
= dc_isar_feature(aa64_sm4
, s
);
13545 genfn
= gen_helper_crypto_sm4ekey
;
13548 unallocated_encoding(s
);
13554 unallocated_encoding(s
);
13558 if (!fp_access_check(s
)) {
13563 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13565 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13566 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13567 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13569 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13571 tcg_temp_free_ptr(tcg_rd_ptr
);
13572 tcg_temp_free_ptr(tcg_rn_ptr
);
13573 tcg_temp_free_ptr(tcg_rm_ptr
);
13575 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13578 tcg_op1
= tcg_temp_new_i64();
13579 tcg_op2
= tcg_temp_new_i64();
13580 tcg_res
[0] = tcg_temp_new_i64();
13581 tcg_res
[1] = tcg_temp_new_i64();
13583 for (pass
= 0; pass
< 2; pass
++) {
13584 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13585 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13587 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13588 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13590 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13591 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13593 tcg_temp_free_i64(tcg_op1
);
13594 tcg_temp_free_i64(tcg_op2
);
13595 tcg_temp_free_i64(tcg_res
[0]);
13596 tcg_temp_free_i64(tcg_res
[1]);
13600 /* Crypto two-reg SHA512
13601 * 31 12 11 10 9 5 4 0
13602 * +-----------------------------------------+--------+------+------+
13603 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13604 * +-----------------------------------------+--------+------+------+
13606 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13608 int opcode
= extract32(insn
, 10, 2);
13609 int rn
= extract32(insn
, 5, 5);
13610 int rd
= extract32(insn
, 0, 5);
13611 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13613 CryptoTwoOpFn
*genfn
;
13616 case 0: /* SHA512SU0 */
13617 feature
= dc_isar_feature(aa64_sha512
, s
);
13618 genfn
= gen_helper_crypto_sha512su0
;
13621 feature
= dc_isar_feature(aa64_sm4
, s
);
13622 genfn
= gen_helper_crypto_sm4e
;
13625 unallocated_encoding(s
);
13630 unallocated_encoding(s
);
13634 if (!fp_access_check(s
)) {
13638 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13639 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13641 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13643 tcg_temp_free_ptr(tcg_rd_ptr
);
13644 tcg_temp_free_ptr(tcg_rn_ptr
);
13647 /* Crypto four-register
13648 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13649 * +-------------------+-----+------+---+------+------+------+
13650 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13651 * +-------------------+-----+------+---+------+------+------+
13653 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13655 int op0
= extract32(insn
, 21, 2);
13656 int rm
= extract32(insn
, 16, 5);
13657 int ra
= extract32(insn
, 10, 5);
13658 int rn
= extract32(insn
, 5, 5);
13659 int rd
= extract32(insn
, 0, 5);
13665 feature
= dc_isar_feature(aa64_sha3
, s
);
13667 case 2: /* SM3SS1 */
13668 feature
= dc_isar_feature(aa64_sm3
, s
);
13671 unallocated_encoding(s
);
13676 unallocated_encoding(s
);
13680 if (!fp_access_check(s
)) {
13685 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13688 tcg_op1
= tcg_temp_new_i64();
13689 tcg_op2
= tcg_temp_new_i64();
13690 tcg_op3
= tcg_temp_new_i64();
13691 tcg_res
[0] = tcg_temp_new_i64();
13692 tcg_res
[1] = tcg_temp_new_i64();
13694 for (pass
= 0; pass
< 2; pass
++) {
13695 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13696 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13697 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13701 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13704 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13706 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13708 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13709 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13711 tcg_temp_free_i64(tcg_op1
);
13712 tcg_temp_free_i64(tcg_op2
);
13713 tcg_temp_free_i64(tcg_op3
);
13714 tcg_temp_free_i64(tcg_res
[0]);
13715 tcg_temp_free_i64(tcg_res
[1]);
13717 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13719 tcg_op1
= tcg_temp_new_i32();
13720 tcg_op2
= tcg_temp_new_i32();
13721 tcg_op3
= tcg_temp_new_i32();
13722 tcg_res
= tcg_temp_new_i32();
13723 tcg_zero
= tcg_const_i32(0);
13725 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13726 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13727 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13729 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13730 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13731 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13732 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13734 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13735 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13736 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13737 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13739 tcg_temp_free_i32(tcg_op1
);
13740 tcg_temp_free_i32(tcg_op2
);
13741 tcg_temp_free_i32(tcg_op3
);
13742 tcg_temp_free_i32(tcg_res
);
13743 tcg_temp_free_i32(tcg_zero
);
13748 * 31 21 20 16 15 10 9 5 4 0
13749 * +-----------------------+------+--------+------+------+
13750 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13751 * +-----------------------+------+--------+------+------+
13753 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13755 int rm
= extract32(insn
, 16, 5);
13756 int imm6
= extract32(insn
, 10, 6);
13757 int rn
= extract32(insn
, 5, 5);
13758 int rd
= extract32(insn
, 0, 5);
13759 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13762 if (!dc_isar_feature(aa64_sha3
, s
)) {
13763 unallocated_encoding(s
);
13767 if (!fp_access_check(s
)) {
13771 tcg_op1
= tcg_temp_new_i64();
13772 tcg_op2
= tcg_temp_new_i64();
13773 tcg_res
[0] = tcg_temp_new_i64();
13774 tcg_res
[1] = tcg_temp_new_i64();
13776 for (pass
= 0; pass
< 2; pass
++) {
13777 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13778 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13780 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13781 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13783 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13784 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13786 tcg_temp_free_i64(tcg_op1
);
13787 tcg_temp_free_i64(tcg_op2
);
13788 tcg_temp_free_i64(tcg_res
[0]);
13789 tcg_temp_free_i64(tcg_res
[1]);
13792 /* Crypto three-reg imm2
13793 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13794 * +-----------------------+------+-----+------+--------+------+------+
13795 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13796 * +-----------------------+------+-----+------+--------+------+------+
13798 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13800 int opcode
= extract32(insn
, 10, 2);
13801 int imm2
= extract32(insn
, 12, 2);
13802 int rm
= extract32(insn
, 16, 5);
13803 int rn
= extract32(insn
, 5, 5);
13804 int rd
= extract32(insn
, 0, 5);
13805 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13806 TCGv_i32 tcg_imm2
, tcg_opcode
;
13808 if (!dc_isar_feature(aa64_sm3
, s
)) {
13809 unallocated_encoding(s
);
13813 if (!fp_access_check(s
)) {
13817 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13818 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13819 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13820 tcg_imm2
= tcg_const_i32(imm2
);
13821 tcg_opcode
= tcg_const_i32(opcode
);
13823 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13826 tcg_temp_free_ptr(tcg_rd_ptr
);
13827 tcg_temp_free_ptr(tcg_rn_ptr
);
13828 tcg_temp_free_ptr(tcg_rm_ptr
);
13829 tcg_temp_free_i32(tcg_imm2
);
13830 tcg_temp_free_i32(tcg_opcode
);
13833 /* C3.6 Data processing - SIMD, inc Crypto
13835 * As the decode gets a little complex we are using a table based
13836 * approach for this part of the decode.
13838 static const AArch64DecodeTable data_proc_simd
[] = {
13839 /* pattern , mask , fn */
13840 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13841 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13842 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13843 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13844 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13845 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13846 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13847 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13848 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13849 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13850 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13851 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13852 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13853 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13854 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13855 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13856 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13857 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13858 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13859 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13860 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13861 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13862 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13863 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13864 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13865 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13866 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13867 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13868 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13869 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13870 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13871 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13872 { 0x00000000, 0x00000000, NULL
}
13875 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13877 /* Note that this is called with all non-FP cases from
13878 * table C3-6 so it must UNDEF for entries not specifically
13879 * allocated to instructions in that table.
13881 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13885 unallocated_encoding(s
);
13889 /* C3.6 Data processing - SIMD and floating point */
13890 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13892 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13893 disas_data_proc_fp(s
, insn
);
13895 /* SIMD, including crypto */
13896 disas_data_proc_simd(s
, insn
);
13902 * @env: The cpu environment
13903 * @s: The DisasContext
13905 * Return true if the page is guarded.
13907 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13909 #ifdef CONFIG_USER_ONLY
13910 return false; /* FIXME */
13912 uint64_t addr
= s
->base
.pc_first
;
13913 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13914 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13915 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13918 * We test this immediately after reading an insn, which means
13919 * that any normal page must be in the TLB. The only exception
13920 * would be for executing from flash or device memory, which
13921 * does not retain the TLB entry.
13923 * FIXME: Assume false for those, for now. We could use
13924 * arm_cpu_get_phys_page_attrs_debug to re-read the page
13925 * table entry even for that case.
13927 return (tlb_hit(entry
->addr_code
, addr
) &&
13928 env
->iotlb
[mmu_idx
][index
].attrs
.target_tlb_bit0
);
13933 * btype_destination_ok:
13934 * @insn: The instruction at the branch destination
13935 * @bt: SCTLR_ELx.BT
13936 * @btype: PSTATE.BTYPE, and is non-zero
13938 * On a guarded page, there are a limited number of insns
13939 * that may be present at the branch target:
13940 * - branch target identifiers,
13941 * - paciasp, pacibsp,
13944 * Anything else causes a Branch Target Exception.
13946 * Return true if the branch is compatible, false to raise BTITRAP.
13948 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
13950 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
13952 switch (extract32(insn
, 5, 7)) {
13953 case 0b011001: /* PACIASP */
13954 case 0b011011: /* PACIBSP */
13956 * If SCTLR_ELx.BT, then PACI*SP are not compatible
13957 * with btype == 3. Otherwise all btype are ok.
13959 return !bt
|| btype
!= 3;
13960 case 0b100000: /* BTI */
13961 /* Not compatible with any btype. */
13963 case 0b100010: /* BTI c */
13964 /* Not compatible with btype == 3 */
13966 case 0b100100: /* BTI j */
13967 /* Not compatible with btype == 2 */
13969 case 0b100110: /* BTI jc */
13970 /* Compatible with any btype. */
13974 switch (insn
& 0xffe0001fu
) {
13975 case 0xd4200000u
: /* BRK */
13976 case 0xd4400000u
: /* HLT */
13977 /* Give priority to the breakpoint exception. */
13984 /* C3.1 A64 instruction index by encoding */
13985 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13989 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13993 s
->fp_access_checked
= false;
13995 if (dc_isar_feature(aa64_bti
, s
)) {
13996 if (s
->base
.num_insns
== 1) {
13998 * At the first insn of the TB, compute s->guarded_page.
13999 * We delayed computing this until successfully reading
14000 * the first insn of the TB, above. This (mostly) ensures
14001 * that the softmmu tlb entry has been populated, and the
14002 * page table GP bit is available.
14004 * Note that we need to compute this even if btype == 0,
14005 * because this value is used for BR instructions later
14006 * where ENV is not available.
14008 s
->guarded_page
= is_guarded_page(env
, s
);
14010 /* First insn can have btype set to non-zero. */
14011 tcg_debug_assert(s
->btype
>= 0);
14014 * Note that the Branch Target Exception has fairly high
14015 * priority -- below debugging exceptions but above most
14016 * everything else. This allows us to handle this now
14017 * instead of waiting until the insn is otherwise decoded.
14021 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14022 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_btitrap(s
->btype
),
14023 default_exception_el(s
));
14027 /* Not the first insn: btype must be 0. */
14028 tcg_debug_assert(s
->btype
== 0);
14032 switch (extract32(insn
, 25, 4)) {
14033 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14034 unallocated_encoding(s
);
14037 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14038 unallocated_encoding(s
);
14041 case 0x8: case 0x9: /* Data processing - immediate */
14042 disas_data_proc_imm(s
, insn
);
14044 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14045 disas_b_exc_sys(s
, insn
);
14050 case 0xe: /* Loads and stores */
14051 disas_ldst(s
, insn
);
14054 case 0xd: /* Data processing - register */
14055 disas_data_proc_reg(s
, insn
);
14058 case 0xf: /* Data processing - SIMD and floating point */
14059 disas_data_proc_simd_fp(s
, insn
);
14062 assert(FALSE
); /* all 15 cases should be handled above */
14066 /* if we allocated any temporaries, free them here */
14070 * After execution of most insns, btype is reset to 0.
14071 * Note that we set btype == -1 when the insn sets btype.
14073 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14078 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14081 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14082 CPUARMState
*env
= cpu
->env_ptr
;
14083 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
14084 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14085 int bound
, core_mmu_idx
;
14087 dc
->isar
= &arm_cpu
->isar
;
14088 dc
->pc
= dc
->base
.pc_first
;
14092 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14093 * there is no secure EL1, so we route exceptions to EL3.
14095 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14096 !arm_el_is_aa64(env
, 3);
14099 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14100 dc
->condexec_mask
= 0;
14101 dc
->condexec_cond
= 0;
14102 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14103 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14104 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14105 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14106 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14107 #if !defined(CONFIG_USER_ONLY)
14108 dc
->user
= (dc
->current_el
== 0);
14110 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14111 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14112 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14113 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14114 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14115 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14117 dc
->vec_stride
= 0;
14118 dc
->cp_regs
= arm_cpu
->cp_regs
;
14119 dc
->features
= env
->features
;
14121 /* Single step state. The code-generation logic here is:
14123 * generate code with no special handling for single-stepping (except
14124 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14125 * this happens anyway because those changes are all system register or
14127 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14128 * emit code for one insn
14129 * emit code to clear PSTATE.SS
14130 * emit code to generate software step exception for completed step
14131 * end TB (as usual for having generated an exception)
14132 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14133 * emit code to generate a software step exception
14136 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14137 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14138 dc
->is_ldex
= false;
14139 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
14141 /* Bound the number of insns to execute to those left on the page. */
14142 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14144 /* If architectural single step active, limit to 1. */
14145 if (dc
->ss_active
) {
14148 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14150 init_tmp_a64_array(dc
);
14153 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14157 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14159 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14161 tcg_gen_insn_start(dc
->pc
, 0, 0);
14162 dc
->insn_start
= tcg_last_op();
14165 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14166 const CPUBreakpoint
*bp
)
14168 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14170 if (bp
->flags
& BP_CPU
) {
14171 gen_a64_set_pc_im(dc
->pc
);
14172 gen_helper_check_breakpoints(cpu_env
);
14173 /* End the TB early; it likely won't be executed */
14174 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14176 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
14177 /* The address covered by the breakpoint must be
14178 included in [tb->pc, tb->pc + tb->size) in order
14179 to for it to be properly cleared -- thus we
14180 increment the PC here so that the logic setting
14181 tb->size below does the right thing. */
14183 dc
->base
.is_jmp
= DISAS_NORETURN
;
14189 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14191 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14192 CPUARMState
*env
= cpu
->env_ptr
;
14194 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14195 /* Singlestep state is Active-pending.
14196 * If we're in this state at the start of a TB then either
14197 * a) we just took an exception to an EL which is being debugged
14198 * and this is the first insn in the exception handler
14199 * b) debug exceptions were masked and we just unmasked them
14200 * without changing EL (eg by clearing PSTATE.D)
14201 * In either case we're going to take a swstep exception in the
14202 * "did not step an insn" case, and so the syndrome ISV and EX
14203 * bits should be zero.
14205 assert(dc
->base
.num_insns
== 1);
14206 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
14207 default_exception_el(dc
));
14208 dc
->base
.is_jmp
= DISAS_NORETURN
;
14210 disas_a64_insn(env
, dc
);
14213 dc
->base
.pc_next
= dc
->pc
;
14214 translator_loop_temp_check(&dc
->base
);
14217 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14219 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14221 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14222 /* Note that this means single stepping WFI doesn't halt the CPU.
14223 * For conditional branch insns this is harmless unreachable code as
14224 * gen_goto_tb() has already handled emitting the debug exception
14225 * (and thus a tb-jump is not possible when singlestepping).
14227 switch (dc
->base
.is_jmp
) {
14229 gen_a64_set_pc_im(dc
->pc
);
14233 if (dc
->base
.singlestep_enabled
) {
14234 gen_exception_internal(EXCP_DEBUG
);
14236 gen_step_complete_exception(dc
);
14239 case DISAS_NORETURN
:
14243 switch (dc
->base
.is_jmp
) {
14245 case DISAS_TOO_MANY
:
14246 gen_goto_tb(dc
, 1, dc
->pc
);
14250 gen_a64_set_pc_im(dc
->pc
);
14253 tcg_gen_exit_tb(NULL
, 0);
14256 tcg_gen_lookup_and_goto_ptr();
14258 case DISAS_NORETURN
:
14262 gen_a64_set_pc_im(dc
->pc
);
14263 gen_helper_wfe(cpu_env
);
14266 gen_a64_set_pc_im(dc
->pc
);
14267 gen_helper_yield(cpu_env
);
14271 /* This is a special case because we don't want to just halt the CPU
14272 * if trying to debug across a WFI.
14274 TCGv_i32 tmp
= tcg_const_i32(4);
14276 gen_a64_set_pc_im(dc
->pc
);
14277 gen_helper_wfi(cpu_env
, tmp
);
14278 tcg_temp_free_i32(tmp
);
14279 /* The helper doesn't necessarily throw an exception, but we
14280 * must go back to the main loop to check for interrupts anyway.
14282 tcg_gen_exit_tb(NULL
, 0);
14288 /* Functions above can change dc->pc, so re-align db->pc_next */
14289 dc
->base
.pc_next
= dc
->pc
;
14292 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14295 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14297 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14298 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14301 const TranslatorOps aarch64_translator_ops
= {
14302 .init_disas_context
= aarch64_tr_init_disas_context
,
14303 .tb_start
= aarch64_tr_tb_start
,
14304 .insn_start
= aarch64_tr_insn_start
,
14305 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14306 .translate_insn
= aarch64_tr_translate_insn
,
14307 .tb_stop
= aarch64_tr_tb_stop
,
14308 .disas_log
= aarch64_tr_disas_log
,