target/arm/translate-a64.h

   1 /*
   2  *  AArch64 translation, common definitions.
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef TARGET_ARM_TRANSLATE_A64_H
  19 #define TARGET_ARM_TRANSLATE_A64_H
  20
  21 #define unsupported_encoding(s, insn)                                    \
  22     do {                                                                 \
  23         qemu_log_mask(LOG_UNIMP,                                         \
  24                       "%s:%d: unsupported instruction encoding 0x%08x "  \
  25                       "at pc=%016" PRIx64 "\n",                          \
  26                       __FILE__, __LINE__, insn, s->pc_curr);             \
  27         unallocated_encoding(s);                                         \
  28     } while (0)
  29
  30 TCGv_i64 new_tmp_a64(DisasContext *s);
  31 TCGv_i64 new_tmp_a64_zero(DisasContext *s);
  32 TCGv_i64 cpu_reg(DisasContext *s, int reg);
  33 TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
  34 TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
  35 TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
  36 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
  37 TCGv_ptr get_fpstatus_ptr(bool);
  38 bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
  39                             unsigned int imms, unsigned int immr);
  40 bool sve_access_check(DisasContext *s);
  41
  42 /* We should have at some point before trying to access an FP register
  43  * done the necessary access check, so assert that
  44  * (a) we did the check and
  45  * (b) we didn't then just plough ahead anyway if it failed.
  46  * Print the instruction pattern in the abort message so we can figure
  47  * out what we need to fix if a user encounters this problem in the wild.
  48  */
  49 static inline void assert_fp_access_checked(DisasContext *s)
  50 {
  51 #ifdef CONFIG_DEBUG_TCG
  52     if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
  53         fprintf(stderr, "target-arm: FP access check missing for "
  54                 "instruction 0x%08x\n", s->insn);
  55         abort();
  56     }
  57 #endif
  58 }
  59
  60 /* Return the offset into CPUARMState of an element of specified
  61  * size, 'element' places in from the least significant end of
  62  * the FP/vector register Qn.
  63  */
  64 static inline int vec_reg_offset(DisasContext *s, int regno,
  65                                  int element, TCGMemOp size)
  66 {
  67     int element_size = 1 << size;
  68     int offs = element * element_size;
  69 #ifdef HOST_WORDS_BIGENDIAN
  70     /* This is complicated slightly because vfp.zregs[n].d[0] is
  71      * still the lowest and vfp.zregs[n].d[15] the highest of the
  72      * 256 byte vector, even on big endian systems.
  73      *
  74      * Calculate the offset assuming fully little-endian,
  75      * then XOR to account for the order of the 8-byte units.
  76      *
  77      * For 16 byte elements, the two 8 byte halves will not form a
  78      * host int128 if the host is bigendian, since they're in the
  79      * wrong order.  However the only 16 byte operation we have is
  80      * a move, so we can ignore this for the moment.  More complicated
  81      * operations will have to special case loading and storing from
  82      * the zregs array.
  83      */
  84     if (element_size < 8) {
  85         offs ^= 8 - element_size;
  86     }
  87 #endif
  88     offs += offsetof(CPUARMState, vfp.zregs[regno]);
  89     assert_fp_access_checked(s);
  90     return offs;
  91 }
  92
  93 /* Return the offset info CPUARMState of the "whole" vector register Qn.  */
  94 static inline int vec_full_reg_offset(DisasContext *s, int regno)
  95 {
  96     assert_fp_access_checked(s);
  97     return offsetof(CPUARMState, vfp.zregs[regno]);
  98 }
  99
 100 /* Return a newly allocated pointer to the vector register.  */
 101 static inline TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
 102 {
 103     TCGv_ptr ret = tcg_temp_new_ptr();
 104     tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno));
 105     return ret;
 106 }
 107
 108 /* Return the byte size of the "whole" vector register, VL / 8.  */
 109 static inline int vec_full_reg_size(DisasContext *s)
 110 {
 111     return s->sve_len;
 112 }
 113
 114 bool disas_sve(DisasContext *, uint32_t);
 115
 116 /* Note that the gvec expanders operate on offsets + sizes.  */
 117 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
 118 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
 119                          uint32_t, uint32_t);
 120 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
 121                         uint32_t, uint32_t, uint32_t);
 122 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
 123                         uint32_t, uint32_t, uint32_t);
 124
 125 #endif /* TARGET_ARM_TRANSLATE_A64_H */