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2 * ARM translation: AArch32 VFP instructions
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2005-2007 CodeSourcery
6 * Copyright (c) 2007 OpenedHand, Ltd.
7 * Copyright (c) 2019 Linaro, Ltd.
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
24 * This file is intended to be included from translate.c; it uses
25 * some macros and definitions provided by that file.
26 * It might be possible to convert it to a standalone .c file eventually.
29 /* Include the generated VFP decoder */
30 #include "decode-vfp.inc.c"
31 #include "decode-vfp-uncond.inc.c"
34 * Check that VFP access is enabled. If it is, do the necessary
35 * M-profile lazy-FP handling and then return true.
36 * If not, emit code to generate an appropriate exception and
38 * The ignore_vfp_enabled argument specifies that we should ignore
39 * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX
40 * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns.
42 static bool full_vfp_access_check(DisasContext
*s
, bool ignore_vfp_enabled
)
45 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
46 gen_exception_insn(s
, 4, EXCP_NOCP
, syn_uncategorized(),
49 gen_exception_insn(s
, 4, EXCP_UDEF
,
50 syn_fp_access_trap(1, 0xe, false),
56 if (!s
->vfp_enabled
&& !ignore_vfp_enabled
) {
57 assert(!arm_dc_feature(s
, ARM_FEATURE_M
));
58 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
59 default_exception_el(s
));
63 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
64 /* Handle M-profile lazy FP state mechanics */
66 /* Trigger lazy-state preservation if necessary */
69 * Lazy state saving affects external memory and also the NVIC,
70 * so we must mark it as an IO operation for icount.
72 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
75 gen_helper_v7m_preserve_fp_state(cpu_env
);
76 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
80 * If the preserve_fp_state helper doesn't throw an exception
81 * then it will clear LSPACT; we don't need to repeat this for
82 * any further FP insns in this TB.
84 s
->v7m_lspact
= false;
87 /* Update ownership of FP context: set FPCCR.S to match current state */
88 if (s
->v8m_fpccr_s_wrong
) {
91 tmp
= load_cpu_field(v7m
.fpccr
[M_REG_S
]);
93 tcg_gen_ori_i32(tmp
, tmp
, R_V7M_FPCCR_S_MASK
);
95 tcg_gen_andi_i32(tmp
, tmp
, ~R_V7M_FPCCR_S_MASK
);
97 store_cpu_field(tmp
, v7m
.fpccr
[M_REG_S
]);
98 /* Don't need to do this for any further FP insns in this TB */
99 s
->v8m_fpccr_s_wrong
= false;
102 if (s
->v7m_new_fp_ctxt_needed
) {
104 * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA
107 TCGv_i32 control
, fpscr
;
108 uint32_t bits
= R_V7M_CONTROL_FPCA_MASK
;
110 fpscr
= load_cpu_field(v7m
.fpdscr
[s
->v8m_secure
]);
111 gen_helper_vfp_set_fpscr(cpu_env
, fpscr
);
112 tcg_temp_free_i32(fpscr
);
114 * We don't need to arrange to end the TB, because the only
115 * parts of FPSCR which we cache in the TB flags are the VECLEN
116 * and VECSTRIDE, and those don't exist for M-profile.
120 bits
|= R_V7M_CONTROL_SFPA_MASK
;
122 control
= load_cpu_field(v7m
.control
[M_REG_S
]);
123 tcg_gen_ori_i32(control
, control
, bits
);
124 store_cpu_field(control
, v7m
.control
[M_REG_S
]);
125 /* Don't need to do this for any further FP insns in this TB */
126 s
->v7m_new_fp_ctxt_needed
= false;
134 * The most usual kind of VFP access check, for everything except
135 * FMXR/FMRX to the always-available special registers.
137 static bool vfp_access_check(DisasContext
*s
)
139 return full_vfp_access_check(s
, false);
142 static bool trans_VSEL(DisasContext
*s
, arg_VSEL
*a
)
147 if (!dc_isar_feature(aa32_vsel
, s
)) {
151 /* UNDEF accesses to D16-D31 if they don't exist */
152 if (dp
&& !dc_isar_feature(aa32_fp_d32
, s
) &&
153 ((a
->vm
| a
->vn
| a
->vd
) & 0x10)) {
160 if (!vfp_access_check(s
)) {
165 TCGv_i64 frn
, frm
, dest
;
166 TCGv_i64 tmp
, zero
, zf
, nf
, vf
;
168 zero
= tcg_const_i64(0);
170 frn
= tcg_temp_new_i64();
171 frm
= tcg_temp_new_i64();
172 dest
= tcg_temp_new_i64();
174 zf
= tcg_temp_new_i64();
175 nf
= tcg_temp_new_i64();
176 vf
= tcg_temp_new_i64();
178 tcg_gen_extu_i32_i64(zf
, cpu_ZF
);
179 tcg_gen_ext_i32_i64(nf
, cpu_NF
);
180 tcg_gen_ext_i32_i64(vf
, cpu_VF
);
182 neon_load_reg64(frn
, rn
);
183 neon_load_reg64(frm
, rm
);
186 tcg_gen_movcond_i64(TCG_COND_EQ
, dest
, zf
, zero
,
190 tcg_gen_movcond_i64(TCG_COND_LT
, dest
, vf
, zero
,
193 case 2: /* ge: N == V -> N ^ V == 0 */
194 tmp
= tcg_temp_new_i64();
195 tcg_gen_xor_i64(tmp
, vf
, nf
);
196 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
198 tcg_temp_free_i64(tmp
);
200 case 3: /* gt: !Z && N == V */
201 tcg_gen_movcond_i64(TCG_COND_NE
, dest
, zf
, zero
,
203 tmp
= tcg_temp_new_i64();
204 tcg_gen_xor_i64(tmp
, vf
, nf
);
205 tcg_gen_movcond_i64(TCG_COND_GE
, dest
, tmp
, zero
,
207 tcg_temp_free_i64(tmp
);
210 neon_store_reg64(dest
, rd
);
211 tcg_temp_free_i64(frn
);
212 tcg_temp_free_i64(frm
);
213 tcg_temp_free_i64(dest
);
215 tcg_temp_free_i64(zf
);
216 tcg_temp_free_i64(nf
);
217 tcg_temp_free_i64(vf
);
219 tcg_temp_free_i64(zero
);
221 TCGv_i32 frn
, frm
, dest
;
224 zero
= tcg_const_i32(0);
226 frn
= tcg_temp_new_i32();
227 frm
= tcg_temp_new_i32();
228 dest
= tcg_temp_new_i32();
229 neon_load_reg32(frn
, rn
);
230 neon_load_reg32(frm
, rm
);
233 tcg_gen_movcond_i32(TCG_COND_EQ
, dest
, cpu_ZF
, zero
,
237 tcg_gen_movcond_i32(TCG_COND_LT
, dest
, cpu_VF
, zero
,
240 case 2: /* ge: N == V -> N ^ V == 0 */
241 tmp
= tcg_temp_new_i32();
242 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
243 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
245 tcg_temp_free_i32(tmp
);
247 case 3: /* gt: !Z && N == V */
248 tcg_gen_movcond_i32(TCG_COND_NE
, dest
, cpu_ZF
, zero
,
250 tmp
= tcg_temp_new_i32();
251 tcg_gen_xor_i32(tmp
, cpu_VF
, cpu_NF
);
252 tcg_gen_movcond_i32(TCG_COND_GE
, dest
, tmp
, zero
,
254 tcg_temp_free_i32(tmp
);
257 neon_store_reg32(dest
, rd
);
258 tcg_temp_free_i32(frn
);
259 tcg_temp_free_i32(frm
);
260 tcg_temp_free_i32(dest
);
262 tcg_temp_free_i32(zero
);
268 static bool trans_VMINMAXNM(DisasContext
*s
, arg_VMINMAXNM
*a
)
275 if (!dc_isar_feature(aa32_vminmaxnm
, s
)) {
279 /* UNDEF accesses to D16-D31 if they don't exist */
280 if (dp
&& !dc_isar_feature(aa32_fp_d32
, s
) &&
281 ((a
->vm
| a
->vn
| a
->vd
) & 0x10)) {
288 if (!vfp_access_check(s
)) {
292 fpst
= get_fpstatus_ptr(0);
295 TCGv_i64 frn
, frm
, dest
;
297 frn
= tcg_temp_new_i64();
298 frm
= tcg_temp_new_i64();
299 dest
= tcg_temp_new_i64();
301 neon_load_reg64(frn
, rn
);
302 neon_load_reg64(frm
, rm
);
304 gen_helper_vfp_minnumd(dest
, frn
, frm
, fpst
);
306 gen_helper_vfp_maxnumd(dest
, frn
, frm
, fpst
);
308 neon_store_reg64(dest
, rd
);
309 tcg_temp_free_i64(frn
);
310 tcg_temp_free_i64(frm
);
311 tcg_temp_free_i64(dest
);
313 TCGv_i32 frn
, frm
, dest
;
315 frn
= tcg_temp_new_i32();
316 frm
= tcg_temp_new_i32();
317 dest
= tcg_temp_new_i32();
319 neon_load_reg32(frn
, rn
);
320 neon_load_reg32(frm
, rm
);
322 gen_helper_vfp_minnums(dest
, frn
, frm
, fpst
);
324 gen_helper_vfp_maxnums(dest
, frn
, frm
, fpst
);
326 neon_store_reg32(dest
, rd
);
327 tcg_temp_free_i32(frn
);
328 tcg_temp_free_i32(frm
);
329 tcg_temp_free_i32(dest
);
332 tcg_temp_free_ptr(fpst
);
337 * Table for converting the most common AArch32 encoding of
338 * rounding mode to arm_fprounding order (which matches the
339 * common AArch64 order); see ARM ARM pseudocode FPDecodeRM().
341 static const uint8_t fp_decode_rm
[] = {
348 static bool trans_VRINT(DisasContext
*s
, arg_VRINT
*a
)
354 int rounding
= fp_decode_rm
[a
->rm
];
356 if (!dc_isar_feature(aa32_vrint
, s
)) {
360 /* UNDEF accesses to D16-D31 if they don't exist */
361 if (dp
&& !dc_isar_feature(aa32_fp_d32
, s
) &&
362 ((a
->vm
| a
->vd
) & 0x10)) {
368 if (!vfp_access_check(s
)) {
372 fpst
= get_fpstatus_ptr(0);
374 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
375 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
380 tcg_op
= tcg_temp_new_i64();
381 tcg_res
= tcg_temp_new_i64();
382 neon_load_reg64(tcg_op
, rm
);
383 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
384 neon_store_reg64(tcg_res
, rd
);
385 tcg_temp_free_i64(tcg_op
);
386 tcg_temp_free_i64(tcg_res
);
390 tcg_op
= tcg_temp_new_i32();
391 tcg_res
= tcg_temp_new_i32();
392 neon_load_reg32(tcg_op
, rm
);
393 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
394 neon_store_reg32(tcg_res
, rd
);
395 tcg_temp_free_i32(tcg_op
);
396 tcg_temp_free_i32(tcg_res
);
399 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
400 tcg_temp_free_i32(tcg_rmode
);
402 tcg_temp_free_ptr(fpst
);
406 static bool trans_VCVT(DisasContext
*s
, arg_VCVT
*a
)
411 TCGv_i32 tcg_rmode
, tcg_shift
;
412 int rounding
= fp_decode_rm
[a
->rm
];
413 bool is_signed
= a
->op
;
415 if (!dc_isar_feature(aa32_vcvt_dr
, s
)) {
419 /* UNDEF accesses to D16-D31 if they don't exist */
420 if (dp
&& !dc_isar_feature(aa32_fp_d32
, s
) && (a
->vm
& 0x10)) {
426 if (!vfp_access_check(s
)) {
430 fpst
= get_fpstatus_ptr(0);
432 tcg_shift
= tcg_const_i32(0);
434 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rounding
));
435 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
438 TCGv_i64 tcg_double
, tcg_res
;
440 tcg_double
= tcg_temp_new_i64();
441 tcg_res
= tcg_temp_new_i64();
442 tcg_tmp
= tcg_temp_new_i32();
443 neon_load_reg64(tcg_double
, rm
);
445 gen_helper_vfp_tosld(tcg_res
, tcg_double
, tcg_shift
, fpst
);
447 gen_helper_vfp_tould(tcg_res
, tcg_double
, tcg_shift
, fpst
);
449 tcg_gen_extrl_i64_i32(tcg_tmp
, tcg_res
);
450 neon_store_reg32(tcg_tmp
, rd
);
451 tcg_temp_free_i32(tcg_tmp
);
452 tcg_temp_free_i64(tcg_res
);
453 tcg_temp_free_i64(tcg_double
);
455 TCGv_i32 tcg_single
, tcg_res
;
456 tcg_single
= tcg_temp_new_i32();
457 tcg_res
= tcg_temp_new_i32();
458 neon_load_reg32(tcg_single
, rm
);
460 gen_helper_vfp_tosls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
462 gen_helper_vfp_touls(tcg_res
, tcg_single
, tcg_shift
, fpst
);
464 neon_store_reg32(tcg_res
, rd
);
465 tcg_temp_free_i32(tcg_res
);
466 tcg_temp_free_i32(tcg_single
);
469 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
470 tcg_temp_free_i32(tcg_rmode
);
472 tcg_temp_free_i32(tcg_shift
);
474 tcg_temp_free_ptr(fpst
);
479 static bool trans_VMOV_to_gp(DisasContext
*s
, arg_VMOV_to_gp
*a
)
481 /* VMOV scalar to general purpose register */
486 /* UNDEF accesses to D16-D31 if they don't exist */
487 if (!dc_isar_feature(aa32_fp_d32
, s
) && (a
->vn
& 0x10)) {
491 offset
= a
->index
<< a
->size
;
492 pass
= extract32(offset
, 2, 1);
493 offset
= extract32(offset
, 0, 2) * 8;
495 if (a
->size
!= 2 && !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
499 if (!vfp_access_check(s
)) {
503 tmp
= neon_load_reg(a
->vn
, pass
);
507 tcg_gen_shri_i32(tmp
, tmp
, offset
);
518 tcg_gen_shri_i32(tmp
, tmp
, 16);
524 tcg_gen_sari_i32(tmp
, tmp
, 16);
533 store_reg(s
, a
->rt
, tmp
);
538 static bool trans_VMOV_from_gp(DisasContext
*s
, arg_VMOV_from_gp
*a
)
540 /* VMOV general purpose register to scalar */
545 /* UNDEF accesses to D16-D31 if they don't exist */
546 if (!dc_isar_feature(aa32_fp_d32
, s
) && (a
->vn
& 0x10)) {
550 offset
= a
->index
<< a
->size
;
551 pass
= extract32(offset
, 2, 1);
552 offset
= extract32(offset
, 0, 2) * 8;
554 if (a
->size
!= 2 && !arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
558 if (!vfp_access_check(s
)) {
562 tmp
= load_reg(s
, a
->rt
);
565 tmp2
= neon_load_reg(a
->vn
, pass
);
566 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 8);
567 tcg_temp_free_i32(tmp2
);
570 tmp2
= neon_load_reg(a
->vn
, pass
);
571 tcg_gen_deposit_i32(tmp
, tmp2
, tmp
, offset
, 16);
572 tcg_temp_free_i32(tmp2
);
577 neon_store_reg(a
->vn
, pass
, tmp
);
582 static bool trans_VDUP(DisasContext
*s
, arg_VDUP
*a
)
584 /* VDUP (general purpose register) */
588 if (!arm_dc_feature(s
, ARM_FEATURE_NEON
)) {
592 /* UNDEF accesses to D16-D31 if they don't exist */
593 if (!dc_isar_feature(aa32_fp_d32
, s
) && (a
->vn
& 0x10)) {
601 if (a
->q
&& (a
->vn
& 1)) {
605 vec_size
= a
->q
? 16 : 8;
614 if (!vfp_access_check(s
)) {
618 tmp
= load_reg(s
, a
->rt
);
619 tcg_gen_gvec_dup_i32(size
, neon_reg_offset(a
->vn
, 0),
620 vec_size
, vec_size
, tmp
);
621 tcg_temp_free_i32(tmp
);
626 static bool trans_VMSR_VMRS(DisasContext
*s
, arg_VMSR_VMRS
*a
)
629 bool ignore_vfp_enabled
= false;
631 if (arm_dc_feature(s
, ARM_FEATURE_M
)) {
633 * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
634 * Writes to R15 are UNPREDICTABLE; we choose to undef.
636 if (a
->rt
== 15 || a
->reg
!= ARM_VFP_FPSCR
) {
644 * VFPv2 allows access to FPSID from userspace; VFPv3 restricts
645 * all ID registers to privileged access only.
647 if (IS_USER(s
) && arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
650 ignore_vfp_enabled
= true;
654 if (IS_USER(s
) || !arm_dc_feature(s
, ARM_FEATURE_MVFR
)) {
657 ignore_vfp_enabled
= true;
660 if (IS_USER(s
) || !arm_dc_feature(s
, ARM_FEATURE_V8
)) {
663 ignore_vfp_enabled
= true;
671 ignore_vfp_enabled
= true;
674 case ARM_VFP_FPINST2
:
675 /* Not present in VFPv3 */
676 if (IS_USER(s
) || arm_dc_feature(s
, ARM_FEATURE_VFP3
)) {
684 if (!full_vfp_access_check(s
, ignore_vfp_enabled
)) {
689 /* VMRS, move VFP special register to gp register */
694 case ARM_VFP_FPINST2
:
698 tmp
= load_cpu_field(vfp
.xregs
[a
->reg
]);
702 tmp
= load_cpu_field(vfp
.xregs
[ARM_VFP_FPSCR
]);
703 tcg_gen_andi_i32(tmp
, tmp
, 0xf0000000);
705 tmp
= tcg_temp_new_i32();
706 gen_helper_vfp_get_fpscr(tmp
, cpu_env
);
710 g_assert_not_reached();
714 /* Set the 4 flag bits in the CPSR. */
716 tcg_temp_free_i32(tmp
);
718 store_reg(s
, a
->rt
, tmp
);
721 /* VMSR, move gp register to VFP special register */
727 /* Writes are ignored. */
730 tmp
= load_reg(s
, a
->rt
);
731 gen_helper_vfp_set_fpscr(cpu_env
, tmp
);
732 tcg_temp_free_i32(tmp
);
737 * TODO: VFP subarchitecture support.
738 * For now, keep the EN bit only
740 tmp
= load_reg(s
, a
->rt
);
741 tcg_gen_andi_i32(tmp
, tmp
, 1 << 30);
742 store_cpu_field(tmp
, vfp
.xregs
[a
->reg
]);
746 case ARM_VFP_FPINST2
:
747 tmp
= load_reg(s
, a
->rt
);
748 store_cpu_field(tmp
, vfp
.xregs
[a
->reg
]);
751 g_assert_not_reached();
758 static bool trans_VMOV_single(DisasContext
*s
, arg_VMOV_single
*a
)
762 if (!vfp_access_check(s
)) {
767 /* VFP to general purpose register */
768 tmp
= tcg_temp_new_i32();
769 neon_load_reg32(tmp
, a
->vn
);
771 /* Set the 4 flag bits in the CPSR. */
773 tcg_temp_free_i32(tmp
);
775 store_reg(s
, a
->rt
, tmp
);
778 /* general purpose register to VFP */
779 tmp
= load_reg(s
, a
->rt
);
780 neon_store_reg32(tmp
, a
->vn
);
781 tcg_temp_free_i32(tmp
);
787 static bool trans_VMOV_64_sp(DisasContext
*s
, arg_VMOV_64_sp
*a
)
792 * VMOV between two general-purpose registers and two single precision
793 * floating point registers
795 if (!vfp_access_check(s
)) {
801 tmp
= tcg_temp_new_i32();
802 neon_load_reg32(tmp
, a
->vm
);
803 store_reg(s
, a
->rt
, tmp
);
804 tmp
= tcg_temp_new_i32();
805 neon_load_reg32(tmp
, a
->vm
+ 1);
806 store_reg(s
, a
->rt2
, tmp
);
809 tmp
= load_reg(s
, a
->rt
);
810 neon_store_reg32(tmp
, a
->vm
);
811 tmp
= load_reg(s
, a
->rt2
);
812 neon_store_reg32(tmp
, a
->vm
+ 1);
818 static bool trans_VMOV_64_dp(DisasContext
*s
, arg_VMOV_64_sp
*a
)
823 * VMOV between two general-purpose registers and one double precision
824 * floating point register
827 /* UNDEF accesses to D16-D31 if they don't exist */
828 if (!dc_isar_feature(aa32_fp_d32
, s
) && (a
->vm
& 0x10)) {
832 if (!vfp_access_check(s
)) {
838 tmp
= tcg_temp_new_i32();
839 neon_load_reg32(tmp
, a
->vm
* 2);
840 store_reg(s
, a
->rt
, tmp
);
841 tmp
= tcg_temp_new_i32();
842 neon_load_reg32(tmp
, a
->vm
* 2 + 1);
843 store_reg(s
, a
->rt2
, tmp
);
846 tmp
= load_reg(s
, a
->rt
);
847 neon_store_reg32(tmp
, a
->vm
* 2);
848 tcg_temp_free_i32(tmp
);
849 tmp
= load_reg(s
, a
->rt2
);
850 neon_store_reg32(tmp
, a
->vm
* 2 + 1);
851 tcg_temp_free_i32(tmp
);
857 static bool trans_VLDR_VSTR_sp(DisasContext
*s
, arg_VLDR_VSTR_sp
*a
)
862 if (!vfp_access_check(s
)) {
866 offset
= a
->imm
<< 2;
871 if (s
->thumb
&& a
->rn
== 15) {
872 /* This is actually UNPREDICTABLE */
873 addr
= tcg_temp_new_i32();
874 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
876 addr
= load_reg(s
, a
->rn
);
878 tcg_gen_addi_i32(addr
, addr
, offset
);
879 tmp
= tcg_temp_new_i32();
881 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
882 neon_store_reg32(tmp
, a
->vd
);
884 neon_load_reg32(tmp
, a
->vd
);
885 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
887 tcg_temp_free_i32(tmp
);
888 tcg_temp_free_i32(addr
);
893 static bool trans_VLDR_VSTR_dp(DisasContext
*s
, arg_VLDR_VSTR_sp
*a
)
899 /* UNDEF accesses to D16-D31 if they don't exist */
900 if (!dc_isar_feature(aa32_fp_d32
, s
) && (a
->vd
& 0x10)) {
904 if (!vfp_access_check(s
)) {
908 offset
= a
->imm
<< 2;
913 if (s
->thumb
&& a
->rn
== 15) {
914 /* This is actually UNPREDICTABLE */
915 addr
= tcg_temp_new_i32();
916 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
918 addr
= load_reg(s
, a
->rn
);
920 tcg_gen_addi_i32(addr
, addr
, offset
);
921 tmp
= tcg_temp_new_i64();
923 gen_aa32_ld64(s
, tmp
, addr
, get_mem_index(s
));
924 neon_store_reg64(tmp
, a
->vd
);
926 neon_load_reg64(tmp
, a
->vd
);
927 gen_aa32_st64(s
, tmp
, addr
, get_mem_index(s
));
929 tcg_temp_free_i64(tmp
);
930 tcg_temp_free_i32(addr
);
935 static bool trans_VLDM_VSTM_sp(DisasContext
*s
, arg_VLDM_VSTM_sp
*a
)
943 if (n
== 0 || (a
->vd
+ n
) > 32) {
945 * UNPREDICTABLE cases for bad immediates: we choose to
946 * UNDEF to avoid generating huge numbers of TCG ops
950 if (a
->rn
== 15 && a
->w
) {
951 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
955 if (!vfp_access_check(s
)) {
959 if (s
->thumb
&& a
->rn
== 15) {
960 /* This is actually UNPREDICTABLE */
961 addr
= tcg_temp_new_i32();
962 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
964 addr
= load_reg(s
, a
->rn
);
968 tcg_gen_addi_i32(addr
, addr
, -(a
->imm
<< 2));
971 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
973 * Here 'addr' is the lowest address we will store to,
974 * and is either the old SP (if post-increment) or
975 * the new SP (if pre-decrement). For post-increment
976 * where the old value is below the limit and the new
977 * value is above, it is UNKNOWN whether the limit check
978 * triggers; we choose to trigger.
980 gen_helper_v8m_stackcheck(cpu_env
, addr
);
984 tmp
= tcg_temp_new_i32();
985 for (i
= 0; i
< n
; i
++) {
988 gen_aa32_ld32u(s
, tmp
, addr
, get_mem_index(s
));
989 neon_store_reg32(tmp
, a
->vd
+ i
);
992 neon_load_reg32(tmp
, a
->vd
+ i
);
993 gen_aa32_st32(s
, tmp
, addr
, get_mem_index(s
));
995 tcg_gen_addi_i32(addr
, addr
, offset
);
997 tcg_temp_free_i32(tmp
);
1001 offset
= -offset
* n
;
1002 tcg_gen_addi_i32(addr
, addr
, offset
);
1004 store_reg(s
, a
->rn
, addr
);
1006 tcg_temp_free_i32(addr
);
1012 static bool trans_VLDM_VSTM_dp(DisasContext
*s
, arg_VLDM_VSTM_dp
*a
)
1021 if (n
== 0 || (a
->vd
+ n
) > 32 || n
> 16) {
1023 * UNPREDICTABLE cases for bad immediates: we choose to
1024 * UNDEF to avoid generating huge numbers of TCG ops
1028 if (a
->rn
== 15 && a
->w
) {
1029 /* writeback to PC is UNPREDICTABLE, we choose to UNDEF */
1033 /* UNDEF accesses to D16-D31 if they don't exist */
1034 if (!dc_isar_feature(aa32_fp_d32
, s
) && (a
->vd
+ n
) > 16) {
1038 if (!vfp_access_check(s
)) {
1042 if (s
->thumb
&& a
->rn
== 15) {
1043 /* This is actually UNPREDICTABLE */
1044 addr
= tcg_temp_new_i32();
1045 tcg_gen_movi_i32(addr
, s
->pc
& ~2);
1047 addr
= load_reg(s
, a
->rn
);
1051 tcg_gen_addi_i32(addr
, addr
, -(a
->imm
<< 2));
1054 if (s
->v8m_stackcheck
&& a
->rn
== 13 && a
->w
) {
1056 * Here 'addr' is the lowest address we will store to,
1057 * and is either the old SP (if post-increment) or
1058 * the new SP (if pre-decrement). For post-increment
1059 * where the old value is below the limit and the new
1060 * value is above, it is UNKNOWN whether the limit check
1061 * triggers; we choose to trigger.
1063 gen_helper_v8m_stackcheck(cpu_env
, addr
);
1067 tmp
= tcg_temp_new_i64();
1068 for (i
= 0; i
< n
; i
++) {
1071 gen_aa32_ld64(s
, tmp
, addr
, get_mem_index(s
));
1072 neon_store_reg64(tmp
, a
->vd
+ i
);
1075 neon_load_reg64(tmp
, a
->vd
+ i
);
1076 gen_aa32_st64(s
, tmp
, addr
, get_mem_index(s
));
1078 tcg_gen_addi_i32(addr
, addr
, offset
);
1080 tcg_temp_free_i64(tmp
);
1084 offset
= -offset
* n
;
1085 } else if (a
->imm
& 1) {
1092 tcg_gen_addi_i32(addr
, addr
, offset
);
1094 store_reg(s
, a
->rn
, addr
);
1096 tcg_temp_free_i32(addr
);
1103 * Types for callbacks for do_vfp_3op_sp() and do_vfp_3op_dp().
1104 * The callback should emit code to write a value to vd. If
1105 * do_vfp_3op_{sp,dp}() was passed reads_vd then the TCGv vd
1106 * will contain the old value of the relevant VFP register;
1107 * otherwise it must be written to only.
1109 typedef void VFPGen3OpSPFn(TCGv_i32 vd
,
1110 TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
);
1111 typedef void VFPGen3OpDPFn(TCGv_i64 vd
,
1112 TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
);
1115 * Perform a 3-operand VFP data processing instruction. fn is the
1116 * callback to do the actual operation; this function deals with the
1117 * code to handle looping around for VFP vector processing.
1119 static bool do_vfp_3op_sp(DisasContext
*s
, VFPGen3OpSPFn
*fn
,
1120 int vd
, int vn
, int vm
, bool reads_vd
)
1122 uint32_t delta_m
= 0;
1123 uint32_t delta_d
= 0;
1124 uint32_t bank_mask
= 0;
1125 int veclen
= s
->vec_len
;
1126 TCGv_i32 f0
, f1
, fd
;
1129 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1130 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1134 if (!vfp_access_check(s
)) {
1141 /* Figure out what type of vector operation this is. */
1142 if ((vd
& bank_mask
) == 0) {
1146 delta_d
= s
->vec_stride
+ 1;
1148 if ((vm
& bank_mask
) == 0) {
1149 /* mixed scalar/vector */
1158 f0
= tcg_temp_new_i32();
1159 f1
= tcg_temp_new_i32();
1160 fd
= tcg_temp_new_i32();
1161 fpst
= get_fpstatus_ptr(0);
1163 neon_load_reg32(f0
, vn
);
1164 neon_load_reg32(f1
, vm
);
1168 neon_load_reg32(fd
, vd
);
1170 fn(fd
, f0
, f1
, fpst
);
1171 neon_store_reg32(fd
, vd
);
1177 /* Set up the operands for the next iteration */
1179 vd
= ((vd
+ delta_d
) & (bank_mask
- 1)) | (vd
& bank_mask
);
1180 vn
= ((vn
+ delta_d
) & (bank_mask
- 1)) | (vn
& bank_mask
);
1181 neon_load_reg32(f0
, vn
);
1183 vm
= ((vm
+ delta_m
) & (bank_mask
- 1)) | (vm
& bank_mask
);
1184 neon_load_reg32(f1
, vm
);
1188 tcg_temp_free_i32(f0
);
1189 tcg_temp_free_i32(f1
);
1190 tcg_temp_free_i32(fd
);
1191 tcg_temp_free_ptr(fpst
);
1196 static bool do_vfp_3op_dp(DisasContext
*s
, VFPGen3OpDPFn
*fn
,
1197 int vd
, int vn
, int vm
, bool reads_vd
)
1199 uint32_t delta_m
= 0;
1200 uint32_t delta_d
= 0;
1201 uint32_t bank_mask
= 0;
1202 int veclen
= s
->vec_len
;
1203 TCGv_i64 f0
, f1
, fd
;
1206 /* UNDEF accesses to D16-D31 if they don't exist */
1207 if (!dc_isar_feature(aa32_fp_d32
, s
) && ((vd
| vn
| vm
) & 0x10)) {
1211 if (!dc_isar_feature(aa32_fpshvec
, s
) &&
1212 (veclen
!= 0 || s
->vec_stride
!= 0)) {
1216 if (!vfp_access_check(s
)) {
1223 /* Figure out what type of vector operation this is. */
1224 if ((vd
& bank_mask
) == 0) {
1228 delta_d
= (s
->vec_stride
>> 1) + 1;
1230 if ((vm
& bank_mask
) == 0) {
1231 /* mixed scalar/vector */
1240 f0
= tcg_temp_new_i64();
1241 f1
= tcg_temp_new_i64();
1242 fd
= tcg_temp_new_i64();
1243 fpst
= get_fpstatus_ptr(0);
1245 neon_load_reg64(f0
, vn
);
1246 neon_load_reg64(f1
, vm
);
1250 neon_load_reg64(fd
, vd
);
1252 fn(fd
, f0
, f1
, fpst
);
1253 neon_store_reg64(fd
, vd
);
1258 /* Set up the operands for the next iteration */
1260 vd
= ((vd
+ delta_d
) & (bank_mask
- 1)) | (vd
& bank_mask
);
1261 vn
= ((vn
+ delta_d
) & (bank_mask
- 1)) | (vn
& bank_mask
);
1262 neon_load_reg64(f0
, vn
);
1264 vm
= ((vm
+ delta_m
) & (bank_mask
- 1)) | (vm
& bank_mask
);
1265 neon_load_reg64(f1
, vm
);
1269 tcg_temp_free_i64(f0
);
1270 tcg_temp_free_i64(f1
);
1271 tcg_temp_free_i64(fd
);
1272 tcg_temp_free_ptr(fpst
);
1277 static void gen_VMLA_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1279 /* Note that order of inputs to the add matters for NaNs */
1280 TCGv_i32 tmp
= tcg_temp_new_i32();
1282 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1283 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1284 tcg_temp_free_i32(tmp
);
1287 static bool trans_VMLA_sp(DisasContext
*s
, arg_VMLA_sp
*a
)
1289 return do_vfp_3op_sp(s
, gen_VMLA_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1292 static void gen_VMLA_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1294 /* Note that order of inputs to the add matters for NaNs */
1295 TCGv_i64 tmp
= tcg_temp_new_i64();
1297 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1298 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1299 tcg_temp_free_i64(tmp
);
1302 static bool trans_VMLA_dp(DisasContext
*s
, arg_VMLA_sp
*a
)
1304 return do_vfp_3op_dp(s
, gen_VMLA_dp
, a
->vd
, a
->vn
, a
->vm
, true);
1307 static void gen_VMLS_sp(TCGv_i32 vd
, TCGv_i32 vn
, TCGv_i32 vm
, TCGv_ptr fpst
)
1310 * VMLS: vd = vd + -(vn * vm)
1311 * Note that order of inputs to the add matters for NaNs.
1313 TCGv_i32 tmp
= tcg_temp_new_i32();
1315 gen_helper_vfp_muls(tmp
, vn
, vm
, fpst
);
1316 gen_helper_vfp_negs(tmp
, tmp
);
1317 gen_helper_vfp_adds(vd
, vd
, tmp
, fpst
);
1318 tcg_temp_free_i32(tmp
);
1321 static bool trans_VMLS_sp(DisasContext
*s
, arg_VMLS_sp
*a
)
1323 return do_vfp_3op_sp(s
, gen_VMLS_sp
, a
->vd
, a
->vn
, a
->vm
, true);
1326 static void gen_VMLS_dp(TCGv_i64 vd
, TCGv_i64 vn
, TCGv_i64 vm
, TCGv_ptr fpst
)
1329 * VMLS: vd = vd + -(vn * vm)
1330 * Note that order of inputs to the add matters for NaNs.
1332 TCGv_i64 tmp
= tcg_temp_new_i64();
1334 gen_helper_vfp_muld(tmp
, vn
, vm
, fpst
);
1335 gen_helper_vfp_negd(tmp
, tmp
);
1336 gen_helper_vfp_addd(vd
, vd
, tmp
, fpst
);
1337 tcg_temp_free_i64(tmp
);
1340 static bool trans_VMLS_dp(DisasContext
*s
, arg_VMLS_sp
*a
)
1342 return do_vfp_3op_dp(s
, gen_VMLS_dp
, a
->vd
, a
->vn
, a
->vm
, true);