1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
4 #include "exec/translator.h"
11 * Save pc_save across a branch, so that we may restore the value from
12 * before the branch at the point the label is emitted.
14 typedef struct DisasLabel
{
19 typedef struct DisasContext
{
20 DisasContextBase base
;
21 const ARMISARegisters
*isar
;
23 /* The address of the current instruction being translated. */
26 * For TARGET_TB_PCREL, the full value of cpu_pc is not known
27 * (although the page offset is known). For convenience, the
28 * translation loop uses the full virtual address that triggered
29 * the translation, from base.pc_start through pc_curr.
30 * For efficiency, we do not update cpu_pc for every instruction.
31 * Instead, pc_save has the value of pc_curr at the time of the
32 * last update to cpu_pc, which allows us to compute the addend
33 * needed to bring cpu_pc current: pc_curr - pc_save.
34 * If cpu_pc now contains the destination of an indirect branch,
35 * pc_save contains -1 to indicate that relative updates are no
39 target_ulong page_start
;
41 /* Nonzero if this instruction has been conditionally skipped. */
43 /* The label that will be jumped to when the instruction is skipped. */
45 /* Thumb-2 conditional execution bits. */
48 /* M-profile ECI/ICI exception-continuable instruction state */
51 * trans_ functions for insns which are continuable should set this true
52 * after decode (ie after any UNDEF checks)
57 #if !defined(CONFIG_USER_ONLY)
60 ARMMMUIdx mmu_idx
; /* MMU index to use for normal loads/stores */
61 uint8_t tbii
; /* TBI1|TBI0 for insns */
62 uint8_t tbid
; /* TBI1|TBI0 for data */
63 uint8_t tcma
; /* TCMA1|TCMA0 for MTE */
64 bool ns
; /* Use non-secure CPREG bank on access */
65 int fp_excp_el
; /* FP exception EL or 0 if enabled */
66 int sve_excp_el
; /* SVE exception EL or 0 if enabled */
67 int sme_excp_el
; /* SME exception EL or 0 if enabled */
68 int vl
; /* current vector length in bytes */
69 int svl
; /* current streaming vector length in bytes */
70 bool vfp_enabled
; /* FP enabled via FPSCR.EN */
73 bool v7m_handler_mode
;
74 bool v8m_secure
; /* true if v8M and we're in Secure mode */
75 bool v8m_stackcheck
; /* true if we need to perform v8M stack limit checks */
76 bool v8m_fpccr_s_wrong
; /* true if v8M FPCCR.S != v8m_secure */
77 bool v7m_new_fp_ctxt_needed
; /* ASPEN set but no active FP context */
78 bool v7m_lspact
; /* FPCCR.LSPACT set */
79 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
80 * so that top level loop can generate correct syndrome information.
85 uint64_t features
; /* CPU features bits */
88 /* Because unallocated encodings generate different exception syndrome
89 * information from traps due to FP being disabled, we can't do a single
90 * "is fp access disabled" check at a high level in the decode tree.
91 * To help in catching bugs where the access check was forgotten in some
92 * code path, we set this flag when the access check is done, and assert
93 * that it is set at the point where we actually touch the FP regs.
95 bool fp_access_checked
;
96 bool sve_access_checked
;
97 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
98 * single-step support).
102 /* True if the insn just emitted was a load-exclusive instruction
103 * (necessary for syndrome information for single step exceptions),
104 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
107 /* True if AccType_UNPRIV should be used for LDTR et al */
109 /* True if v8.3-PAuth is active. */
111 /* True if v8.5-MTE access to tags is enabled. */
113 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */
115 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
117 /* True if any CP15 access is trapped by HSTR_EL2 */
119 /* True if memory operations require alignment */
121 /* True if PSTATE.IL is set */
123 /* True if PSTATE.SM is set. */
125 /* True if PSTATE.ZA is set. */
127 /* True if non-streaming insns should raise an SME Streaming exception. */
128 bool sme_trap_nonstreaming
;
129 /* True if the current instruction is non-streaming. */
130 bool is_nonstreaming
;
131 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
133 /* True if fine-grained traps are active */
136 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
137 * < 0, set by the current instruction.
140 /* A copy of cpu->dcz_blocksize. */
141 uint8_t dcz_blocksize
;
142 /* True if this page is guarded. */
144 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
146 /* TCG op of the current insn_start. */
148 #define TMP_A64_MAX 16
150 TCGv_i64 tmp_a64
[TMP_A64_MAX
];
153 typedef struct DisasCompare
{
159 /* Share the TCG temporaries common between 32 and 64 bit modes. */
160 extern TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
161 extern TCGv_i64 cpu_exclusive_addr
;
162 extern TCGv_i64 cpu_exclusive_val
;
165 * Constant expanders for the decoders.
168 static inline int negate(DisasContext
*s
, int x
)
173 static inline int plus_1(DisasContext
*s
, int x
)
178 static inline int plus_2(DisasContext
*s
, int x
)
183 static inline int plus_12(DisasContext
*s
, int x
)
188 static inline int times_2(DisasContext
*s
, int x
)
193 static inline int times_4(DisasContext
*s
, int x
)
198 static inline int times_2_plus_1(DisasContext
*s
, int x
)
203 static inline int rsub_64(DisasContext
*s
, int x
)
208 static inline int rsub_32(DisasContext
*s
, int x
)
213 static inline int rsub_16(DisasContext
*s
, int x
)
218 static inline int rsub_8(DisasContext
*s
, int x
)
223 static inline int neon_3same_fp_size(DisasContext
*s
, int x
)
225 /* Convert 0==fp32, 1==fp16 into a MO_* value */
229 static inline int arm_dc_feature(DisasContext
*dc
, int feature
)
231 return (dc
->features
& (1ULL << feature
)) != 0;
234 static inline int get_mem_index(DisasContext
*s
)
236 return arm_to_core_mmu_idx(s
->mmu_idx
);
239 static inline void disas_set_insn_syndrome(DisasContext
*s
, uint32_t syn
)
241 /* We don't need to save all of the syndrome so we mask and shift
242 * out unneeded bits to help the sleb128 encoder do a better job.
244 syn
&= ARM_INSN_START_WORD2_MASK
;
245 syn
>>= ARM_INSN_START_WORD2_SHIFT
;
247 /* We check and clear insn_start_idx to catch multiple updates. */
248 assert(s
->insn_start
!= NULL
);
249 tcg_set_insn_start_param(s
->insn_start
, 2, syn
);
250 s
->insn_start
= NULL
;
253 static inline int curr_insn_len(DisasContext
*s
)
255 return s
->base
.pc_next
- s
->pc_curr
;
258 /* is_jmp field values */
259 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
260 /* CPU state was modified dynamically; exit to main loop for interrupts. */
261 #define DISAS_UPDATE_EXIT DISAS_TARGET_1
262 /* These instructions trap after executing, so the A32/T32 decoder must
263 * defer them until after the conditional execution state has been updated.
264 * WFI also needs special handling when single-stepping.
266 #define DISAS_WFI DISAS_TARGET_2
267 #define DISAS_SWI DISAS_TARGET_3
269 #define DISAS_WFE DISAS_TARGET_4
270 #define DISAS_HVC DISAS_TARGET_5
271 #define DISAS_SMC DISAS_TARGET_6
272 #define DISAS_YIELD DISAS_TARGET_7
273 /* M profile branch which might be an exception return (and so needs
274 * custom end-of-TB code)
276 #define DISAS_BX_EXCRET DISAS_TARGET_8
278 * For instructions which want an immediate exit to the main loop, as opposed
279 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
280 * doesn't write the PC on exiting the translation loop so you need to ensure
281 * something (gen_a64_update_pc or runtime helper) has done so before we reach
282 * return from cpu_tb_exec.
284 #define DISAS_EXIT DISAS_TARGET_9
285 /* CPU state was modified dynamically; no need to exit, but do not chain. */
286 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
288 #ifdef TARGET_AARCH64
289 void a64_translate_init(void);
290 void gen_a64_update_pc(DisasContext
*s
, target_long diff
);
291 extern const TranslatorOps aarch64_translator_ops
;
293 static inline void a64_translate_init(void)
297 static inline void gen_a64_update_pc(DisasContext
*s
, target_long diff
)
302 void arm_test_cc(DisasCompare
*cmp
, int cc
);
303 void arm_free_cc(DisasCompare
*cmp
);
304 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
);
305 void arm_gen_test_cc(int cc
, TCGLabel
*label
);
306 MemOp
pow2_align(unsigned i
);
307 void unallocated_encoding(DisasContext
*s
);
308 void gen_exception_insn_el(DisasContext
*s
, target_long pc_diff
, int excp
,
309 uint32_t syn
, uint32_t target_el
);
310 void gen_exception_insn(DisasContext
*s
, target_long pc_diff
,
311 int excp
, uint32_t syn
);
313 /* Return state of Alternate Half-precision flag, caller frees result */
314 static inline TCGv_i32
get_ahp_flag(void)
316 TCGv_i32 ret
= tcg_temp_new_i32();
318 tcg_gen_ld_i32(ret
, cpu_env
,
319 offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPSCR
]));
320 tcg_gen_extract_i32(ret
, ret
, 26, 1);
325 /* Set bits within PSTATE. */
326 static inline void set_pstate_bits(uint32_t bits
)
328 TCGv_i32 p
= tcg_temp_new_i32();
330 tcg_debug_assert(!(bits
& CACHED_PSTATE_BITS
));
332 tcg_gen_ld_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
333 tcg_gen_ori_i32(p
, p
, bits
);
334 tcg_gen_st_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
335 tcg_temp_free_i32(p
);
338 /* Clear bits within PSTATE. */
339 static inline void clear_pstate_bits(uint32_t bits
)
341 TCGv_i32 p
= tcg_temp_new_i32();
343 tcg_debug_assert(!(bits
& CACHED_PSTATE_BITS
));
345 tcg_gen_ld_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
346 tcg_gen_andi_i32(p
, p
, ~bits
);
347 tcg_gen_st_i32(p
, cpu_env
, offsetof(CPUARMState
, pstate
));
348 tcg_temp_free_i32(p
);
351 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
352 static inline void gen_ss_advance(DisasContext
*s
)
356 clear_pstate_bits(PSTATE_SS
);
360 /* Generate an architectural singlestep exception */
361 static inline void gen_swstep_exception(DisasContext
*s
, int isv
, int ex
)
363 /* Fill in the same_el field of the syndrome in the helper. */
364 uint32_t syn
= syn_swstep(false, isv
, ex
);
365 gen_helper_exception_swstep(cpu_env
, tcg_constant_i32(syn
));
369 * Given a VFP floating point constant encoded into an 8 bit immediate in an
370 * instruction, expand it to the actual constant value of the specified
371 * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
373 uint64_t vfp_expand_imm(int size
, uint8_t imm8
);
375 /* Vector operations shared between ARM and AArch64. */
376 void gen_gvec_ceq0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
377 uint32_t opr_sz
, uint32_t max_sz
);
378 void gen_gvec_clt0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
379 uint32_t opr_sz
, uint32_t max_sz
);
380 void gen_gvec_cgt0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
381 uint32_t opr_sz
, uint32_t max_sz
);
382 void gen_gvec_cle0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
383 uint32_t opr_sz
, uint32_t max_sz
);
384 void gen_gvec_cge0(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
385 uint32_t opr_sz
, uint32_t max_sz
);
387 void gen_gvec_mla(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
388 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
389 void gen_gvec_mls(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
390 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
392 void gen_gvec_cmtst(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
393 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
394 void gen_gvec_sshl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
395 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
396 void gen_gvec_ushl(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
397 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
399 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
400 void gen_ushl_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
);
401 void gen_sshl_i32(TCGv_i32 d
, TCGv_i32 a
, TCGv_i32 b
);
402 void gen_ushl_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
403 void gen_sshl_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
405 void gen_gvec_uqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
406 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
407 void gen_gvec_sqadd_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
408 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
409 void gen_gvec_uqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
410 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
411 void gen_gvec_sqsub_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
412 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
414 void gen_gvec_ssra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
415 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
416 void gen_gvec_usra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
417 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
419 void gen_gvec_srshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
420 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
421 void gen_gvec_urshr(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
422 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
423 void gen_gvec_srsra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
424 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
425 void gen_gvec_ursra(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
426 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
428 void gen_gvec_sri(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
429 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
430 void gen_gvec_sli(unsigned vece
, uint32_t rd_ofs
, uint32_t rm_ofs
,
431 int64_t shift
, uint32_t opr_sz
, uint32_t max_sz
);
433 void gen_gvec_sqrdmlah_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
434 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
435 void gen_gvec_sqrdmlsh_qc(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
436 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
438 void gen_gvec_sabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
439 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
440 void gen_gvec_uabd(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
441 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
443 void gen_gvec_saba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
444 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
445 void gen_gvec_uaba(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
446 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
);
449 * Forward to the isar_feature_* tests given a DisasContext pointer.
451 #define dc_isar_feature(name, ctx) \
452 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
454 /* Note that the gvec expanders operate on offsets + sizes. */
455 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
456 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
458 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
459 uint32_t, uint32_t, uint32_t);
460 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
461 uint32_t, uint32_t, uint32_t);
463 /* Function prototype for gen_ functions for calling Neon helpers */
464 typedef void NeonGenOneOpFn(TCGv_i32
, TCGv_i32
);
465 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
466 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
467 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
468 typedef void NeonGenThreeOpEnvFn(TCGv_i32
, TCGv_env
, TCGv_i32
,
470 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
471 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
472 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
473 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
474 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
475 typedef void NeonGenTwoOpWidenFn(TCGv_i64
, TCGv_i32
, TCGv_i32
);
476 typedef void NeonGenOneSingleOpFn(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
477 typedef void NeonGenTwoSingleOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
478 typedef void NeonGenTwoDoubleOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
479 typedef void NeonGenOne64OpFn(TCGv_i64
, TCGv_i64
);
480 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
481 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
482 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
483 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, MemOp
);
484 typedef void WideShiftImmFn(TCGv_i64
, TCGv_i64
, int64_t shift
);
485 typedef void WideShiftFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i32
);
486 typedef void ShiftImmFn(TCGv_i32
, TCGv_i32
, int32_t shift
);
487 typedef void ShiftFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
490 * arm_tbflags_from_tb:
491 * @tb: the TranslationBlock
493 * Extract the flag values from @tb.
495 static inline CPUARMTBFlags
arm_tbflags_from_tb(const TranslationBlock
*tb
)
497 return (CPUARMTBFlags
){ tb
->flags
, tb
->cs_base
};
501 * Enum for argument to fpstatus_ptr().
503 typedef enum ARMFPStatusFlavour
{
508 } ARMFPStatusFlavour
;
511 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
513 * We have multiple softfloat float_status fields in the Arm CPU state struct
514 * (see the comment in cpu.h for details). Return a TCGv_ptr which has
515 * been set up to point to the requested field in the CPU state struct.
519 * for non-FP16 operations controlled by the FPCR
521 * for operations controlled by the FPCR where FPCR.FZ16 is to be used
523 * for A32/T32 Neon operations using the "standard FPSCR value"
525 * as FPST_STD, but where FPCR.FZ16 is to be used
527 static inline TCGv_ptr
fpstatus_ptr(ARMFPStatusFlavour flavour
)
529 TCGv_ptr statusptr
= tcg_temp_new_ptr();
534 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
537 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
540 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status
);
543 offset
= offsetof(CPUARMState
, vfp
.standard_fp_status_f16
);
546 g_assert_not_reached();
548 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
555 * @opc: size+sign+align of the memory operation
557 * Build the complete MemOp for a memory operation, including alignment
560 * If (op & MO_AMASK) then the operation already contains the required
561 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally
562 * unaligned operation, e.g. for AccType_NORMAL.
564 * In the latter case, there are configuration bits that require alignment,
565 * and this is applied here. Note that there is no way to indicate that
566 * no alignment should ever be enforced; this must be handled manually.
568 static inline MemOp
finalize_memop(DisasContext
*s
, MemOp opc
)
570 if (s
->align_mem
&& !(opc
& MO_AMASK
)) {
573 return opc
| s
->be_data
;
577 * asimd_imm_const: Expand an encoded SIMD constant value
579 * Expand a SIMD constant value. This is essentially the pseudocode
580 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
581 * VMVN and VBIC (when cmode < 14 && op == 1).
583 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
584 * callers must catch this; we return the 64-bit constant value defined
587 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
588 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
589 * we produce an immediate constant value of 0 in these cases.
591 uint64_t asimd_imm_const(uint32_t imm
, int cmode
, int op
);
595 * Create a label and cache a copy of pc_save.
597 static inline DisasLabel
gen_disas_label(DisasContext
*s
)
600 .label
= gen_new_label(),
601 .pc_save
= s
->pc_save
,
607 * Emit a label and restore the cached copy of pc_save.
609 static inline void set_disas_label(DisasContext
*s
, DisasLabel l
)
611 gen_set_label(l
.label
);
612 s
->pc_save
= l
.pc_save
;
615 static inline TCGv_ptr
gen_lookup_cp_reg(uint32_t key
)
617 TCGv_ptr ret
= tcg_temp_new_ptr();
618 gen_helper_lookup_cp_reg(ret
, cpu_env
, tcg_constant_i32(key
));
623 * Helpers for implementing sets of trans_* functions.
624 * Defer the implementation of NAME to FUNC, with optional extra arguments.
626 #define TRANS(NAME, FUNC, ...) \
627 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
628 { return FUNC(s, __VA_ARGS__); }
629 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
630 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
631 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
633 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \
634 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
636 s->is_nonstreaming = true; \
637 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
640 #endif /* TARGET_ARM_TRANSLATE_H */