target/arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 #include "exec/translator.h"
   5 #include "internals.h"
   6
   7
   8 /* internal defines */
   9 typedef struct DisasContext {
  10     DisasContextBase base;
  11     const ARMISARegisters *isar;
  12
  13     /* The address of the current instruction being translated. */
  14     target_ulong pc_curr;
  15     target_ulong page_start;
  16     uint32_t insn;
  17     /* Nonzero if this instruction has been conditionally skipped.  */
  18     int condjmp;
  19     /* The label that will be jumped to when the instruction is skipped.  */
  20     TCGLabel *condlabel;
  21     /* Thumb-2 conditional execution bits.  */
  22     int condexec_mask;
  23     int condexec_cond;
  24     int thumb;
  25     int sctlr_b;
  26     MemOp be_data;
  27 #if !defined(CONFIG_USER_ONLY)
  28     int user;
  29 #endif
  30     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  31     uint8_t tbii;      /* TBI1|TBI0 for insns */
  32     uint8_t tbid;      /* TBI1|TBI0 for data */
  33     bool ns;        /* Use non-secure CPREG bank on access */
  34     int fp_excp_el; /* FP exception EL or 0 if enabled */
  35     int sve_excp_el; /* SVE exception EL or 0 if enabled */
  36     int sve_len;     /* SVE vector length in bytes */
  37     /* Flag indicating that exceptions from secure mode are routed to EL3. */
  38     bool secure_routed_to_el3;
  39     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  40     int vec_len;
  41     int vec_stride;
  42     bool v7m_handler_mode;
  43     bool v8m_secure; /* true if v8M and we're in Secure mode */
  44     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
  45     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
  46     bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
  47     bool v7m_lspact; /* FPCCR.LSPACT set */
  48     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  49      * so that top level loop can generate correct syndrome information.
  50      */
  51     uint32_t svc_imm;
  52     int aarch64;
  53     int current_el;
  54     /* Debug target exception level for single-step exceptions */
  55     int debug_target_el;
  56     GHashTable *cp_regs;
  57     uint64_t features; /* CPU features bits */
  58     /* Because unallocated encodings generate different exception syndrome
  59      * information from traps due to FP being disabled, we can't do a single
  60      * "is fp access disabled" check at a high level in the decode tree.
  61      * To help in catching bugs where the access check was forgotten in some
  62      * code path, we set this flag when the access check is done, and assert
  63      * that it is set at the point where we actually touch the FP regs.
  64      */
  65     bool fp_access_checked;
  66     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  67      * single-step support).
  68      */
  69     bool ss_active;
  70     bool pstate_ss;
  71     /* True if the insn just emitted was a load-exclusive instruction
  72      * (necessary for syndrome information for single step exceptions),
  73      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  74      */
  75     bool is_ldex;
  76     /* True if AccType_UNPRIV should be used for LDTR et al */
  77     bool unpriv;
  78     /* True if v8.3-PAuth is active.  */
  79     bool pauth_active;
  80     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
  81     bool bt;
  82     /* True if any CP15 access is trapped by HSTR_EL2 */
  83     bool hstr_active;
  84     /*
  85      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
  86      *  < 0, set by the current instruction.
  87      */
  88     int8_t btype;
  89     /* True if this page is guarded.  */
  90     bool guarded_page;
  91     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  92     int c15_cpar;
  93     /* TCG op of the current insn_start.  */
  94     TCGOp *insn_start;
  95 #define TMP_A64_MAX 16
  96     int tmp_a64_count;
  97     TCGv_i64 tmp_a64[TMP_A64_MAX];
  98 } DisasContext;
  99
 100 typedef struct DisasCompare {
 101     TCGCond cond;
 102     TCGv_i32 value;
 103     bool value_global;
 104 } DisasCompare;
 105
 106 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
 107 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
 108 extern TCGv_i64 cpu_exclusive_addr;
 109 extern TCGv_i64 cpu_exclusive_val;
 110
 111 static inline int arm_dc_feature(DisasContext *dc, int feature)
 112 {
 113     return (dc->features & (1ULL << feature)) != 0;
 114 }
 115
 116 static inline int get_mem_index(DisasContext *s)
 117 {
 118     return arm_to_core_mmu_idx(s->mmu_idx);
 119 }
 120
 121 /* Function used to determine the target exception EL when otherwise not known
 122  * or default.
 123  */
 124 static inline int default_exception_el(DisasContext *s)
 125 {
 126     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 127      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 128      * exceptions can only be routed to ELs above 1, so we target the higher of
 129      * 1 or the current EL.
 130      */
 131     return (s->mmu_idx == ARMMMUIdx_SE10_0 && s->secure_routed_to_el3)
 132             ? 3 : MAX(1, s->current_el);
 133 }
 134
 135 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 136 {
 137     /* We don't need to save all of the syndrome so we mask and shift
 138      * out unneeded bits to help the sleb128 encoder do a better job.
 139      */
 140     syn &= ARM_INSN_START_WORD2_MASK;
 141     syn >>= ARM_INSN_START_WORD2_SHIFT;
 142
 143     /* We check and clear insn_start_idx to catch multiple updates.  */
 144     assert(s->insn_start != NULL);
 145     tcg_set_insn_start_param(s->insn_start, 2, syn);
 146     s->insn_start = NULL;
 147 }
 148
 149 /* is_jmp field values */
 150 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 151 /* CPU state was modified dynamically; exit to main loop for interrupts. */
 152 #define DISAS_UPDATE_EXIT  DISAS_TARGET_1
 153 /* These instructions trap after executing, so the A32/T32 decoder must
 154  * defer them until after the conditional execution state has been updated.
 155  * WFI also needs special handling when single-stepping.
 156  */
 157 #define DISAS_WFI       DISAS_TARGET_2
 158 #define DISAS_SWI       DISAS_TARGET_3
 159 /* WFE */
 160 #define DISAS_WFE       DISAS_TARGET_4
 161 #define DISAS_HVC       DISAS_TARGET_5
 162 #define DISAS_SMC       DISAS_TARGET_6
 163 #define DISAS_YIELD     DISAS_TARGET_7
 164 /* M profile branch which might be an exception return (and so needs
 165  * custom end-of-TB code)
 166  */
 167 #define DISAS_BX_EXCRET DISAS_TARGET_8
 168 /*
 169  * For instructions which want an immediate exit to the main loop, as opposed
 170  * to attempting to use lookup_and_goto_ptr.  Unlike DISAS_UPDATE_EXIT, this
 171  * doesn't write the PC on exiting the translation loop so you need to ensure
 172  * something (gen_a64_set_pc_im or runtime helper) has done so before we reach
 173  * return from cpu_tb_exec.
 174  */
 175 #define DISAS_EXIT      DISAS_TARGET_9
 176 /* CPU state was modified dynamically; no need to exit, but do not chain. */
 177 #define DISAS_UPDATE_NOCHAIN  DISAS_TARGET_10
 178
 179 #ifdef TARGET_AARCH64
 180 void a64_translate_init(void);
 181 void gen_a64_set_pc_im(uint64_t val);
 182 extern const TranslatorOps aarch64_translator_ops;
 183 #else
 184 static inline void a64_translate_init(void)
 185 {
 186 }
 187
 188 static inline void gen_a64_set_pc_im(uint64_t val)
 189 {
 190 }
 191 #endif
 192
 193 void arm_test_cc(DisasCompare *cmp, int cc);
 194 void arm_free_cc(DisasCompare *cmp);
 195 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 196 void arm_gen_test_cc(int cc, TCGLabel *label);
 197
 198 /* Return state of Alternate Half-precision flag, caller frees result */
 199 static inline TCGv_i32 get_ahp_flag(void)
 200 {
 201     TCGv_i32 ret = tcg_temp_new_i32();
 202
 203     tcg_gen_ld_i32(ret, cpu_env,
 204                    offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
 205     tcg_gen_extract_i32(ret, ret, 26, 1);
 206
 207     return ret;
 208 }
 209
 210 /* Set bits within PSTATE.  */
 211 static inline void set_pstate_bits(uint32_t bits)
 212 {
 213     TCGv_i32 p = tcg_temp_new_i32();
 214
 215     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 216
 217     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 218     tcg_gen_ori_i32(p, p, bits);
 219     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 220     tcg_temp_free_i32(p);
 221 }
 222
 223 /* Clear bits within PSTATE.  */
 224 static inline void clear_pstate_bits(uint32_t bits)
 225 {
 226     TCGv_i32 p = tcg_temp_new_i32();
 227
 228     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 229
 230     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 231     tcg_gen_andi_i32(p, p, ~bits);
 232     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 233     tcg_temp_free_i32(p);
 234 }
 235
 236 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
 237 static inline void gen_ss_advance(DisasContext *s)
 238 {
 239     if (s->ss_active) {
 240         s->pstate_ss = 0;
 241         clear_pstate_bits(PSTATE_SS);
 242     }
 243 }
 244
 245 static inline void gen_exception(int excp, uint32_t syndrome,
 246                                  uint32_t target_el)
 247 {
 248     TCGv_i32 tcg_excp = tcg_const_i32(excp);
 249     TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
 250     TCGv_i32 tcg_el = tcg_const_i32(target_el);
 251
 252     gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
 253                                        tcg_syn, tcg_el);
 254
 255     tcg_temp_free_i32(tcg_el);
 256     tcg_temp_free_i32(tcg_syn);
 257     tcg_temp_free_i32(tcg_excp);
 258 }
 259
 260 /* Generate an architectural singlestep exception */
 261 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
 262 {
 263     bool same_el = (s->debug_target_el == s->current_el);
 264
 265     /*
 266      * If singlestep is targeting a lower EL than the current one,
 267      * then s->ss_active must be false and we can never get here.
 268      */
 269     assert(s->debug_target_el >= s->current_el);
 270
 271     gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
 272 }
 273
 274 /*
 275  * Given a VFP floating point constant encoded into an 8 bit immediate in an
 276  * instruction, expand it to the actual constant value of the specified
 277  * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
 278  */
 279 uint64_t vfp_expand_imm(int size, uint8_t imm8);
 280
 281 /* Vector operations shared between ARM and AArch64.  */
 282 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 283                    uint32_t opr_sz, uint32_t max_sz);
 284 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 285                    uint32_t opr_sz, uint32_t max_sz);
 286 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 287                    uint32_t opr_sz, uint32_t max_sz);
 288 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 289                    uint32_t opr_sz, uint32_t max_sz);
 290 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 291                    uint32_t opr_sz, uint32_t max_sz);
 292
 293 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 294                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 295 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 296                   uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 297
 298 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 299                     uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 300 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 301                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 302 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 303                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 304
 305 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 306 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
 307 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
 308 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 309 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 310
 311 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 312                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 313 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 314                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 315 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 316                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 317 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 318                        uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 319
 320 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 321                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 322 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 323                    int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 324
 325 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 326                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 327 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 328                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 329 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 330                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 331 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 332                     int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 333
 334 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 335                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 336 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
 337                   int64_t shift, uint32_t opr_sz, uint32_t max_sz);
 338
 339 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 340                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 341 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 342                           uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 343
 344 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 345                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 346 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 347                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 348
 349 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 350                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 351 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
 352                    uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
 353
 354 /*
 355  * Forward to the isar_feature_* tests given a DisasContext pointer.
 356  */
 357 #define dc_isar_feature(name, ctx) \
 358     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 359
 360 /* Note that the gvec expanders operate on offsets + sizes.  */
 361 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
 362 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
 363                          uint32_t, uint32_t);
 364 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
 365                         uint32_t, uint32_t, uint32_t);
 366 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
 367                         uint32_t, uint32_t, uint32_t);
 368
 369 /* Function prototype for gen_ functions for calling Neon helpers */
 370 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
 371 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
 372 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
 373 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
 374 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
 375 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
 376 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
 377 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
 378 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
 379 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
 380 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
 381 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
 382 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
 383 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
 384 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
 385 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
 386 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
 387 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
 388
 389 #endif /* TARGET_ARM_TRANSLATE_H */