1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
4 #include "exec/translator.h"
8 typedef struct DisasContext
{
10 const ARMISARegisters
*isar
;
13 target_ulong page_start
;
15 /* Nonzero if this instruction has been conditionally skipped. */
17 /* The label that will be jumped to when the instruction is skipped. */
19 /* Thumb-2 conditional execution bits. */
25 #if !defined(CONFIG_USER_ONLY)
28 ARMMMUIdx mmu_idx
; /* MMU index to use for normal loads/stores */
29 bool tbi0
; /* TBI0 for EL0/1 or TBI for EL2/3 */
30 bool tbi1
; /* TBI1 for EL0/1, not used for EL2/3 */
31 bool ns
; /* Use non-secure CPREG bank on access */
32 int fp_excp_el
; /* FP exception EL or 0 if enabled */
33 int sve_excp_el
; /* SVE exception EL or 0 if enabled */
34 int sve_len
; /* SVE vector length in bytes */
35 /* Flag indicating that exceptions from secure mode are routed to EL3. */
36 bool secure_routed_to_el3
;
37 bool vfp_enabled
; /* FP enabled via FPSCR.EN */
40 bool v7m_handler_mode
;
41 bool v8m_secure
; /* true if v8M and we're in Secure mode */
42 bool v8m_stackcheck
; /* true if we need to perform v8M stack limit checks */
43 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
44 * so that top level loop can generate correct syndrome information.
50 uint64_t features
; /* CPU features bits */
51 /* Because unallocated encodings generate different exception syndrome
52 * information from traps due to FP being disabled, we can't do a single
53 * "is fp access disabled" check at a high level in the decode tree.
54 * To help in catching bugs where the access check was forgotten in some
55 * code path, we set this flag when the access check is done, and assert
56 * that it is set at the point where we actually touch the FP regs.
58 bool fp_access_checked
;
59 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
60 * single-step support).
64 /* True if the insn just emitted was a load-exclusive instruction
65 * (necessary for syndrome information for single step exceptions),
66 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
69 /* True if a single-step exception will be taken to the current EL */
71 /* True if v8.3-PAuth is active. */
73 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
75 /* TCG op of the current insn_start. */
77 #define TMP_A64_MAX 16
79 TCGv_i64 tmp_a64
[TMP_A64_MAX
];
82 typedef struct DisasCompare
{
88 /* Share the TCG temporaries common between 32 and 64 bit modes. */
89 extern TCGv_i32 cpu_NF
, cpu_ZF
, cpu_CF
, cpu_VF
;
90 extern TCGv_i64 cpu_exclusive_addr
;
91 extern TCGv_i64 cpu_exclusive_val
;
93 static inline int arm_dc_feature(DisasContext
*dc
, int feature
)
95 return (dc
->features
& (1ULL << feature
)) != 0;
98 static inline int get_mem_index(DisasContext
*s
)
100 return arm_to_core_mmu_idx(s
->mmu_idx
);
103 /* Function used to determine the target exception EL when otherwise not known
106 static inline int default_exception_el(DisasContext
*s
)
108 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
109 * there is no secure EL1, so we route exceptions to EL3. Otherwise,
110 * exceptions can only be routed to ELs above 1, so we target the higher of
111 * 1 or the current EL.
113 return (s
->mmu_idx
== ARMMMUIdx_S1SE0
&& s
->secure_routed_to_el3
)
114 ? 3 : MAX(1, s
->current_el
);
117 static inline void disas_set_insn_syndrome(DisasContext
*s
, uint32_t syn
)
119 /* We don't need to save all of the syndrome so we mask and shift
120 * out unneeded bits to help the sleb128 encoder do a better job.
122 syn
&= ARM_INSN_START_WORD2_MASK
;
123 syn
>>= ARM_INSN_START_WORD2_SHIFT
;
125 /* We check and clear insn_start_idx to catch multiple updates. */
126 assert(s
->insn_start
!= NULL
);
127 tcg_set_insn_start_param(s
->insn_start
, 2, syn
);
128 s
->insn_start
= NULL
;
131 /* is_jmp field values */
132 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
133 #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
134 /* These instructions trap after executing, so the A32/T32 decoder must
135 * defer them until after the conditional execution state has been updated.
136 * WFI also needs special handling when single-stepping.
138 #define DISAS_WFI DISAS_TARGET_2
139 #define DISAS_SWI DISAS_TARGET_3
141 #define DISAS_WFE DISAS_TARGET_4
142 #define DISAS_HVC DISAS_TARGET_5
143 #define DISAS_SMC DISAS_TARGET_6
144 #define DISAS_YIELD DISAS_TARGET_7
145 /* M profile branch which might be an exception return (and so needs
146 * custom end-of-TB code)
148 #define DISAS_BX_EXCRET DISAS_TARGET_8
149 /* For instructions which want an immediate exit to the main loop,
150 * as opposed to attempting to use lookup_and_goto_ptr. Unlike
151 * DISAS_UPDATE this doesn't write the PC on exiting the translation
152 * loop so you need to ensure something (gen_a64_set_pc_im or runtime
153 * helper) has done so before we reach return from cpu_tb_exec.
155 #define DISAS_EXIT DISAS_TARGET_9
157 #ifdef TARGET_AARCH64
158 void a64_translate_init(void);
159 void gen_a64_set_pc_im(uint64_t val
);
160 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
161 fprintf_function cpu_fprintf
, int flags
);
162 extern const TranslatorOps aarch64_translator_ops
;
164 static inline void a64_translate_init(void)
168 static inline void gen_a64_set_pc_im(uint64_t val
)
172 static inline void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
173 fprintf_function cpu_fprintf
,
179 void arm_test_cc(DisasCompare
*cmp
, int cc
);
180 void arm_free_cc(DisasCompare
*cmp
);
181 void arm_jump_cc(DisasCompare
*cmp
, TCGLabel
*label
);
182 void arm_gen_test_cc(int cc
, TCGLabel
*label
);
184 /* Return state of Alternate Half-precision flag, caller frees result */
185 static inline TCGv_i32
get_ahp_flag(void)
187 TCGv_i32 ret
= tcg_temp_new_i32();
189 tcg_gen_ld_i32(ret
, cpu_env
,
190 offsetof(CPUARMState
, vfp
.xregs
[ARM_VFP_FPSCR
]));
191 tcg_gen_extract_i32(ret
, ret
, 26, 1);
197 /* Vector operations shared between ARM and AArch64. */
198 extern const GVecGen3 bsl_op
;
199 extern const GVecGen3 bit_op
;
200 extern const GVecGen3 bif_op
;
201 extern const GVecGen3 mla_op
[4];
202 extern const GVecGen3 mls_op
[4];
203 extern const GVecGen3 cmtst_op
[4];
204 extern const GVecGen2i ssra_op
[4];
205 extern const GVecGen2i usra_op
[4];
206 extern const GVecGen2i sri_op
[4];
207 extern const GVecGen2i sli_op
[4];
208 void gen_cmtst_i64(TCGv_i64 d
, TCGv_i64 a
, TCGv_i64 b
);
211 * Forward to the isar_feature_* tests given a DisasContext pointer.
213 #define dc_isar_feature(name, ctx) \
214 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
216 #endif /* TARGET_ARM_TRANSLATE_H */