target/arm/translate.h

   1 #ifndef TARGET_ARM_TRANSLATE_H
   2 #define TARGET_ARM_TRANSLATE_H
   3
   4 #include "exec/translator.h"
   5
   6
   7 /* internal defines */
   8 typedef struct DisasContext {
   9     DisasContextBase base;
  10     const ARMISARegisters *isar;
  11
  12     target_ulong pc;
  13     target_ulong page_start;
  14     uint32_t insn;
  15     /* Nonzero if this instruction has been conditionally skipped.  */
  16     int condjmp;
  17     /* The label that will be jumped to when the instruction is skipped.  */
  18     TCGLabel *condlabel;
  19     /* Thumb-2 conditional execution bits.  */
  20     int condexec_mask;
  21     int condexec_cond;
  22     int thumb;
  23     int sctlr_b;
  24     TCGMemOp be_data;
  25 #if !defined(CONFIG_USER_ONLY)
  26     int user;
  27 #endif
  28     ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
  29     uint8_t tbii;      /* TBI1|TBI0 for insns */
  30     uint8_t tbid;      /* TBI1|TBI0 for data */
  31     bool ns;        /* Use non-secure CPREG bank on access */
  32     int fp_excp_el; /* FP exception EL or 0 if enabled */
  33     int sve_excp_el; /* SVE exception EL or 0 if enabled */
  34     int sve_len;     /* SVE vector length in bytes */
  35     /* Flag indicating that exceptions from secure mode are routed to EL3. */
  36     bool secure_routed_to_el3;
  37     bool vfp_enabled; /* FP enabled via FPSCR.EN */
  38     int vec_len;
  39     int vec_stride;
  40     bool v7m_handler_mode;
  41     bool v8m_secure; /* true if v8M and we're in Secure mode */
  42     bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
  43     bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
  44     bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
  45     bool v7m_lspact; /* FPCCR.LSPACT set */
  46     /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
  47      * so that top level loop can generate correct syndrome information.
  48      */
  49     uint32_t svc_imm;
  50     int aarch64;
  51     int current_el;
  52     GHashTable *cp_regs;
  53     uint64_t features; /* CPU features bits */
  54     /* Because unallocated encodings generate different exception syndrome
  55      * information from traps due to FP being disabled, we can't do a single
  56      * "is fp access disabled" check at a high level in the decode tree.
  57      * To help in catching bugs where the access check was forgotten in some
  58      * code path, we set this flag when the access check is done, and assert
  59      * that it is set at the point where we actually touch the FP regs.
  60      */
  61     bool fp_access_checked;
  62     /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
  63      * single-step support).
  64      */
  65     bool ss_active;
  66     bool pstate_ss;
  67     /* True if the insn just emitted was a load-exclusive instruction
  68      * (necessary for syndrome information for single step exceptions),
  69      * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
  70      */
  71     bool is_ldex;
  72     /* True if a single-step exception will be taken to the current EL */
  73     bool ss_same_el;
  74     /* True if v8.3-PAuth is active.  */
  75     bool pauth_active;
  76     /* True with v8.5-BTI and SCTLR_ELx.BT* set.  */
  77     bool bt;
  78     /*
  79      * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
  80      *  < 0, set by the current instruction.
  81      */
  82     int8_t btype;
  83     /* True if this page is guarded.  */
  84     bool guarded_page;
  85     /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
  86     int c15_cpar;
  87     /* TCG op of the current insn_start.  */
  88     TCGOp *insn_start;
  89 #define TMP_A64_MAX 16
  90     int tmp_a64_count;
  91     TCGv_i64 tmp_a64[TMP_A64_MAX];
  92 } DisasContext;
  93
  94 typedef struct DisasCompare {
  95     TCGCond cond;
  96     TCGv_i32 value;
  97     bool value_global;
  98 } DisasCompare;
  99
 100 /* Share the TCG temporaries common between 32 and 64 bit modes.  */
 101 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
 102 extern TCGv_i64 cpu_exclusive_addr;
 103 extern TCGv_i64 cpu_exclusive_val;
 104
 105 static inline int arm_dc_feature(DisasContext *dc, int feature)
 106 {
 107     return (dc->features & (1ULL << feature)) != 0;
 108 }
 109
 110 static inline int get_mem_index(DisasContext *s)
 111 {
 112     return arm_to_core_mmu_idx(s->mmu_idx);
 113 }
 114
 115 /* Function used to determine the target exception EL when otherwise not known
 116  * or default.
 117  */
 118 static inline int default_exception_el(DisasContext *s)
 119 {
 120     /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
 121      * there is no secure EL1, so we route exceptions to EL3.  Otherwise,
 122      * exceptions can only be routed to ELs above 1, so we target the higher of
 123      * 1 or the current EL.
 124      */
 125     return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3)
 126             ? 3 : MAX(1, s->current_el);
 127 }
 128
 129 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
 130 {
 131     /* We don't need to save all of the syndrome so we mask and shift
 132      * out unneeded bits to help the sleb128 encoder do a better job.
 133      */
 134     syn &= ARM_INSN_START_WORD2_MASK;
 135     syn >>= ARM_INSN_START_WORD2_SHIFT;
 136
 137     /* We check and clear insn_start_idx to catch multiple updates.  */
 138     assert(s->insn_start != NULL);
 139     tcg_set_insn_start_param(s->insn_start, 2, syn);
 140     s->insn_start = NULL;
 141 }
 142
 143 /* is_jmp field values */
 144 #define DISAS_JUMP      DISAS_TARGET_0 /* only pc was modified dynamically */
 145 #define DISAS_UPDATE    DISAS_TARGET_1 /* cpu state was modified dynamically */
 146 /* These instructions trap after executing, so the A32/T32 decoder must
 147  * defer them until after the conditional execution state has been updated.
 148  * WFI also needs special handling when single-stepping.
 149  */
 150 #define DISAS_WFI       DISAS_TARGET_2
 151 #define DISAS_SWI       DISAS_TARGET_3
 152 /* WFE */
 153 #define DISAS_WFE       DISAS_TARGET_4
 154 #define DISAS_HVC       DISAS_TARGET_5
 155 #define DISAS_SMC       DISAS_TARGET_6
 156 #define DISAS_YIELD     DISAS_TARGET_7
 157 /* M profile branch which might be an exception return (and so needs
 158  * custom end-of-TB code)
 159  */
 160 #define DISAS_BX_EXCRET DISAS_TARGET_8
 161 /* For instructions which want an immediate exit to the main loop,
 162  * as opposed to attempting to use lookup_and_goto_ptr. Unlike
 163  * DISAS_UPDATE this doesn't write the PC on exiting the translation
 164  * loop so you need to ensure something (gen_a64_set_pc_im or runtime
 165  * helper) has done so before we reach return from cpu_tb_exec.
 166  */
 167 #define DISAS_EXIT      DISAS_TARGET_9
 168
 169 #ifdef TARGET_AARCH64
 170 void a64_translate_init(void);
 171 void gen_a64_set_pc_im(uint64_t val);
 172 extern const TranslatorOps aarch64_translator_ops;
 173 #else
 174 static inline void a64_translate_init(void)
 175 {
 176 }
 177
 178 static inline void gen_a64_set_pc_im(uint64_t val)
 179 {
 180 }
 181 #endif
 182
 183 void arm_test_cc(DisasCompare *cmp, int cc);
 184 void arm_free_cc(DisasCompare *cmp);
 185 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
 186 void arm_gen_test_cc(int cc, TCGLabel *label);
 187
 188 /* Return state of Alternate Half-precision flag, caller frees result */
 189 static inline TCGv_i32 get_ahp_flag(void)
 190 {
 191     TCGv_i32 ret = tcg_temp_new_i32();
 192
 193     tcg_gen_ld_i32(ret, cpu_env,
 194                    offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
 195     tcg_gen_extract_i32(ret, ret, 26, 1);
 196
 197     return ret;
 198 }
 199
 200 /* Set bits within PSTATE.  */
 201 static inline void set_pstate_bits(uint32_t bits)
 202 {
 203     TCGv_i32 p = tcg_temp_new_i32();
 204
 205     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 206
 207     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 208     tcg_gen_ori_i32(p, p, bits);
 209     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 210     tcg_temp_free_i32(p);
 211 }
 212
 213 /* Clear bits within PSTATE.  */
 214 static inline void clear_pstate_bits(uint32_t bits)
 215 {
 216     TCGv_i32 p = tcg_temp_new_i32();
 217
 218     tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
 219
 220     tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 221     tcg_gen_andi_i32(p, p, ~bits);
 222     tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
 223     tcg_temp_free_i32(p);
 224 }
 225
 226 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
 227 static inline void gen_ss_advance(DisasContext *s)
 228 {
 229     if (s->ss_active) {
 230         s->pstate_ss = 0;
 231         clear_pstate_bits(PSTATE_SS);
 232     }
 233 }
 234
 235 /*
 236  * Given a VFP floating point constant encoded into an 8 bit immediate in an
 237  * instruction, expand it to the actual constant value of the specified
 238  * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
 239  */
 240 uint64_t vfp_expand_imm(int size, uint8_t imm8);
 241
 242 /* Vector operations shared between ARM and AArch64.  */
 243 extern const GVecGen3 mla_op[4];
 244 extern const GVecGen3 mls_op[4];
 245 extern const GVecGen3 cmtst_op[4];
 246 extern const GVecGen2i ssra_op[4];
 247 extern const GVecGen2i usra_op[4];
 248 extern const GVecGen2i sri_op[4];
 249 extern const GVecGen2i sli_op[4];
 250 extern const GVecGen4 uqadd_op[4];
 251 extern const GVecGen4 sqadd_op[4];
 252 extern const GVecGen4 uqsub_op[4];
 253 extern const GVecGen4 sqsub_op[4];
 254 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
 255
 256 /*
 257  * Forward to the isar_feature_* tests given a DisasContext pointer.
 258  */
 259 #define dc_isar_feature(name, ctx) \
 260     ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
 261
 262 #endif /* TARGET_ARM_TRANSLATE_H */