target/arm/vfp-uncond.decode

   1 # AArch32 VFP instruction descriptions (unconditional insns)
   2 #
   3 #  Copyright (c) 2019 Linaro, Ltd
   4 #
   5 # This library is free software; you can redistribute it and/or
   6 # modify it under the terms of the GNU Lesser General Public
   7 # License as published by the Free Software Foundation; either
   8 # version 2.1 of the License, or (at your option) any later version.
   9 #
  10 # This library is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 # Lesser General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU Lesser General Public
  16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
  17
  18 #
  19 # This file is processed by scripts/decodetree.py
  20 #
  21 # Encodings for the unconditional VFP instructions are here:
  22 # generally anything matching A32
  23 #  1111 1110 .... .... .... 101. ...0 ....
  24 # and T32
  25 #  1111 110. .... .... .... 101. .... ....
  26 #  1111 1110 .... .... .... 101. .... ....
  27 # (but those patterns might also cover some Neon instructions,
  28 # which do not live in this file.)
  29
  30 # VFP registers have an odd encoding with a four-bit field
  31 # and a one-bit field which are assembled in different orders
  32 # depending on whether the register is double or single precision.
  33 # Each individual instruction function must do the checks for
  34 # "double register selected but CPU does not have double support"
  35 # and "double register number has bit 4 set but CPU does not
  36 # support D16-D31" (which should UNDEF).
  37 %vm_dp  5:1 0:4
  38 %vm_sp  0:4 5:1
  39 %vn_dp  7:1 16:4
  40 %vn_sp  16:4 7:1
  41 %vd_dp  22:1 12:4
  42 %vd_sp  12:4 22:1
  43
  44 @vfp_dnm_s   ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
  45 @vfp_dnm_d   ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
  46
  47 VSEL        1111 1110 0. cc:2 .... .... 1001 .0.0 .... \
  48             vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=1
  49 VSEL        1111 1110 0. cc:2 .... .... 1010 .0.0 .... \
  50             vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=2
  51 VSEL        1111 1110 0. cc:2 .... .... 1011 .0.0 .... \
  52             vm=%vm_dp vn=%vn_dp vd=%vd_dp sz=3
  53
  54 VMAXNM_hp   1111 1110 1.00 .... .... 1001 .0.0 ....         @vfp_dnm_s
  55 VMINNM_hp   1111 1110 1.00 .... .... 1001 .1.0 ....         @vfp_dnm_s
  56
  57 VMAXNM_sp   1111 1110 1.00 .... .... 1010 .0.0 ....         @vfp_dnm_s
  58 VMINNM_sp   1111 1110 1.00 .... .... 1010 .1.0 ....         @vfp_dnm_s
  59
  60 VMAXNM_dp   1111 1110 1.00 .... .... 1011 .0.0 ....         @vfp_dnm_d
  61 VMINNM_dp   1111 1110 1.00 .... .... 1011 .1.0 ....         @vfp_dnm_d
  62
  63 VRINT       1111 1110 1.11 10 rm:2 .... 1001 01.0 .... \
  64             vm=%vm_sp vd=%vd_sp sz=1
  65 VRINT       1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \
  66             vm=%vm_sp vd=%vd_sp sz=2
  67 VRINT       1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \
  68             vm=%vm_dp vd=%vd_dp sz=3
  69
  70 # VCVT float to int with specified rounding mode; Vd is always single-precision
  71 VCVT        1111 1110 1.11 11 rm:2 .... 1001 op:1 1.0 .... \
  72             vm=%vm_sp vd=%vd_sp sz=1
  73 VCVT        1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \
  74             vm=%vm_sp vd=%vd_sp sz=2
  75 VCVT        1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \
  76             vm=%vm_dp vd=%vd_sp sz=3
  77
  78 VMOVX       1111 1110 1.11 0000 .... 1010 01 . 0 .... \
  79             vd=%vd_sp vm=%vm_sp
  80
  81 VINS        1111 1110 1.11 0000 .... 1010 11 . 0 .... \
  82             vd=%vd_sp vm=%vm_sp