target/arm/vfp.decode

   1 # AArch32 VFP instruction descriptions (conditional insns)
   2 #
   3 #  Copyright (c) 2019 Linaro, Ltd
   4 #
   5 # This library is free software; you can redistribute it and/or
   6 # modify it under the terms of the GNU Lesser General Public
   7 # License as published by the Free Software Foundation; either
   8 # version 2 of the License, or (at your option) any later version.
   9 #
  10 # This library is distributed in the hope that it will be useful,
  11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 # Lesser General Public License for more details.
  14 #
  15 # You should have received a copy of the GNU Lesser General Public
  16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
  17
  18 #
  19 # This file is processed by scripts/decodetree.py
  20 #
  21 # Encodings for the conditional VFP instructions are here:
  22 # generally anything matching A32
  23 #  cccc 11.. .... .... .... 101. .... ....
  24 # and T32
  25 #  1110 110. .... .... .... 101. .... ....
  26 #  1110 1110 .... .... .... 101. .... ....
  27 # (but those patterns might also cover some Neon instructions,
  28 # which do not live in this file.)
  29
  30 # VFP registers have an odd encoding with a four-bit field
  31 # and a one-bit field which are assembled in different orders
  32 # depending on whether the register is double or single precision.
  33 # Each individual instruction function must do the checks for
  34 # "double register selected but CPU does not have double support"
  35 # and "double register number has bit 4 set but CPU does not
  36 # support D16-D31" (which should UNDEF).
  37 %vm_dp  5:1 0:4
  38 %vm_sp  0:4 5:1
  39 %vn_dp  7:1 16:4
  40 %vn_sp  16:4 7:1
  41 %vd_dp  22:1 12:4
  42 %vd_sp  12:4 22:1
  43
  44 %vmov_idx_b     21:1 5:2
  45 %vmov_idx_h     21:1 6:1
  46
  47 %vmov_imm 16:4 0:4
  48
  49 # VMOV scalar to general-purpose register; note that this does
  50 # include some Neon cases.
  51 VMOV_to_gp   ---- 1110 u:1 1.        1 .... rt:4 1011 ... 1 0000 \
  52              vn=%vn_dp size=0 index=%vmov_idx_b
  53 VMOV_to_gp   ---- 1110 u:1 0.        1 .... rt:4 1011 ..1 1 0000 \
  54              vn=%vn_dp size=1 index=%vmov_idx_h
  55 VMOV_to_gp   ---- 1110 0   0 index:1 1 .... rt:4 1011 .00 1 0000 \
  56              vn=%vn_dp size=2 u=0
  57
  58 VMOV_from_gp ---- 1110 0 1.        0 .... rt:4 1011 ... 1 0000 \
  59              vn=%vn_dp size=0 index=%vmov_idx_b
  60 VMOV_from_gp ---- 1110 0 0.        0 .... rt:4 1011 ..1 1 0000 \
  61              vn=%vn_dp size=1 index=%vmov_idx_h
  62 VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \
  63              vn=%vn_dp size=2
  64
  65 VDUP         ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
  66              vn=%vn_dp
  67
  68 VMSR_VMRS    ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
  69 VMOV_single  ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \
  70              vn=%vn_sp
  71
  72 VMOV_64_sp   ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \
  73              vm=%vm_sp
  74 VMOV_64_dp   ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \
  75              vm=%vm_dp
  76
  77 # Note that the half-precision variants of VLDR and VSTR are
  78 # not part of this decodetree at all because they have bits [9:8] == 0b01
  79 VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \
  80              vd=%vd_sp
  81 VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \
  82              vd=%vd_dp
  83
  84 # We split the load/store multiple up into two patterns to avoid
  85 # overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
  86 # grouping:
  87 #   P=0 U=0 W=0 is 64-bit VMOV
  88 #   P=1 W=0 is VLDR/VSTR
  89 #   P=U W=1 is UNDEF
  90 # leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple.
  91 # These include FSTM/FLDM.
  92 VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
  93              vd=%vd_sp p=0 u=1
  94 VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
  95              vd=%vd_dp p=0 u=1
  96
  97 VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
  98              vd=%vd_sp p=1 u=0 w=1
  99 VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
 100              vd=%vd_dp p=1 u=0 w=1
 101
 102 # 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
 103 VMLA_sp      ---- 1110 0.00 .... .... 1010 .0.0 .... \
 104              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 105 VMLA_dp      ---- 1110 0.00 .... .... 1011 .0.0 .... \
 106              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 107
 108 VMLS_sp      ---- 1110 0.00 .... .... 1010 .1.0 .... \
 109              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 110 VMLS_dp      ---- 1110 0.00 .... .... 1011 .1.0 .... \
 111              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 112
 113 VNMLS_sp     ---- 1110 0.01 .... .... 1010 .0.0 .... \
 114              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 115 VNMLS_dp     ---- 1110 0.01 .... .... 1011 .0.0 .... \
 116              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 117
 118 VNMLA_sp     ---- 1110 0.01 .... .... 1010 .1.0 .... \
 119              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 120 VNMLA_dp     ---- 1110 0.01 .... .... 1011 .1.0 .... \
 121              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 122
 123 VMUL_sp      ---- 1110 0.10 .... .... 1010 .0.0 .... \
 124              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 125 VMUL_dp      ---- 1110 0.10 .... .... 1011 .0.0 .... \
 126              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 127
 128 VNMUL_sp     ---- 1110 0.10 .... .... 1010 .1.0 .... \
 129              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 130 VNMUL_dp     ---- 1110 0.10 .... .... 1011 .1.0 .... \
 131              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 132
 133 VADD_sp      ---- 1110 0.11 .... .... 1010 .0.0 .... \
 134              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 135 VADD_dp      ---- 1110 0.11 .... .... 1011 .0.0 .... \
 136              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 137
 138 VSUB_sp      ---- 1110 0.11 .... .... 1010 .1.0 .... \
 139              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 140 VSUB_dp      ---- 1110 0.11 .... .... 1011 .1.0 .... \
 141              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 142
 143 VDIV_sp      ---- 1110 1.00 .... .... 1010 .0.0 .... \
 144              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 145 VDIV_dp      ---- 1110 1.00 .... .... 1011 .0.0 .... \
 146              vm=%vm_dp vn=%vn_dp vd=%vd_dp
 147
 148 VFM_sp       ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \
 149              vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=1
 150 VFM_dp       ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \
 151              vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=1
 152 VFM_sp       ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \
 153              vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=2
 154 VFM_dp       ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \
 155              vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2
 156
 157 VMOV_imm_sp  ---- 1110 1.11 .... .... 1010 0000 .... \
 158              vd=%vd_sp imm=%vmov_imm
 159 VMOV_imm_dp  ---- 1110 1.11 .... .... 1011 0000 .... \
 160              vd=%vd_dp imm=%vmov_imm
 161
 162 VMOV_reg_sp  ---- 1110 1.11 0000 .... 1010 01.0 .... \
 163              vd=%vd_sp vm=%vm_sp
 164 VMOV_reg_dp  ---- 1110 1.11 0000 .... 1011 01.0 .... \
 165              vd=%vd_dp vm=%vm_dp
 166
 167 VABS_sp      ---- 1110 1.11 0000 .... 1010 11.0 .... \
 168              vd=%vd_sp vm=%vm_sp
 169 VABS_dp      ---- 1110 1.11 0000 .... 1011 11.0 .... \
 170              vd=%vd_dp vm=%vm_dp
 171
 172 VNEG_sp      ---- 1110 1.11 0001 .... 1010 01.0 .... \
 173              vd=%vd_sp vm=%vm_sp
 174 VNEG_dp      ---- 1110 1.11 0001 .... 1011 01.0 .... \
 175              vd=%vd_dp vm=%vm_dp
 176
 177 VSQRT_sp     ---- 1110 1.11 0001 .... 1010 11.0 .... \
 178              vd=%vd_sp vm=%vm_sp
 179 VSQRT_dp     ---- 1110 1.11 0001 .... 1011 11.0 .... \
 180              vd=%vd_dp vm=%vm_dp
 181
 182 VCMP_sp      ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
 183              vd=%vd_sp vm=%vm_sp
 184 VCMP_dp      ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \
 185              vd=%vd_dp vm=%vm_dp
 186
 187 # VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp
 188 VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
 189              vd=%vd_sp vm=%vm_sp
 190 VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
 191              vd=%vd_dp vm=%vm_sp
 192
 193 # VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on size bit
 194 VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
 195              vd=%vd_sp vm=%vm_sp
 196 VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
 197              vd=%vd_sp vm=%vm_dp
 198
 199 VRINTR_sp    ---- 1110 1.11 0110 .... 1010 01.0 .... \
 200              vd=%vd_sp vm=%vm_sp
 201 VRINTR_dp    ---- 1110 1.11 0110 .... 1011 01.0 .... \
 202              vd=%vd_dp vm=%vm_dp
 203
 204 VRINTZ_sp    ---- 1110 1.11 0110 .... 1010 11.0 .... \
 205              vd=%vd_sp vm=%vm_sp
 206 VRINTZ_dp    ---- 1110 1.11 0110 .... 1011 11.0 .... \
 207              vd=%vd_dp vm=%vm_dp
 208
 209 VRINTX_sp    ---- 1110 1.11 0111 .... 1010 01.0 .... \
 210              vd=%vd_sp vm=%vm_sp
 211 VRINTX_dp    ---- 1110 1.11 0111 .... 1011 01.0 .... \
 212              vd=%vd_dp vm=%vm_dp
 213
 214 # VCVT between single and double: Vm precision depends on size; Vd is its reverse
 215 VCVT_sp      ---- 1110 1.11 0111 .... 1010 11.0 .... \
 216              vd=%vd_dp vm=%vm_sp
 217 VCVT_dp      ---- 1110 1.11 0111 .... 1011 11.0 .... \
 218              vd=%vd_sp vm=%vm_dp
 219
 220 # VCVT from integer to floating point: Vm always single; Vd depends on size
 221 VCVT_int_sp  ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
 222              vd=%vd_sp vm=%vm_sp
 223 VCVT_int_dp  ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
 224              vd=%vd_dp vm=%vm_sp
 225
 226 # VJCVT is always dp to sp
 227 VJCVT        ---- 1110 1.11 1001 .... 1011 11.0 .... \
 228              vd=%vd_sp vm=%vm_dp
 229
 230 # VCVT between floating-point and fixed-point. The immediate value
 231 # is in the same format as a Vm single-precision register number.
 232 # We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field
 233 # for the convenience of the trans_VCVT_fix functions.
 234 %vcvt_fix_op 18:1 16:1 7:1
 235 VCVT_fix_sp  ---- 1110 1.11 1.1. .... 1010 .1.0 .... \
 236              vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
 237 VCVT_fix_dp  ---- 1110 1.11 1.1. .... 1011 .1.0 .... \
 238              vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op
 239
 240 # VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size
 241 VCVT_sp_int  ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
 242              vd=%vd_sp vm=%vm_sp
 243 VCVT_dp_int  ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
 244              vd=%vd_sp vm=%vm_dp