2 * ARM VFP floating-point operations
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "exec/helper-proto.h"
24 #include "fpu/softfloat.h"
25 #include "internals.h"
28 /* VFP support. We follow the convention used for VFP instructions:
29 Single precision routines have a "s" suffix, double precision a
32 /* Convert host exception flags to vfp form. */
33 static inline int vfp_exceptbits_from_host(int host_bits
)
37 if (host_bits
& float_flag_invalid
) {
40 if (host_bits
& float_flag_divbyzero
) {
43 if (host_bits
& float_flag_overflow
) {
46 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
)) {
49 if (host_bits
& float_flag_inexact
) {
52 if (host_bits
& float_flag_input_denormal
) {
58 /* Convert vfp exception flags to target form. */
59 static inline int vfp_exceptbits_to_host(int target_bits
)
63 if (target_bits
& 1) {
64 host_bits
|= float_flag_invalid
;
66 if (target_bits
& 2) {
67 host_bits
|= float_flag_divbyzero
;
69 if (target_bits
& 4) {
70 host_bits
|= float_flag_overflow
;
72 if (target_bits
& 8) {
73 host_bits
|= float_flag_underflow
;
75 if (target_bits
& 0x10) {
76 host_bits
|= float_flag_inexact
;
78 if (target_bits
& 0x80) {
79 host_bits
|= float_flag_input_denormal
;
84 static void vfp_set_fpscr_to_host(CPUARMState
*env
, uint32_t val
)
87 uint32_t changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
90 if (changed
& (3 << 22)) {
93 case FPROUNDING_TIEEVEN
:
94 i
= float_round_nearest_even
;
96 case FPROUNDING_POSINF
:
99 case FPROUNDING_NEGINF
:
100 i
= float_round_down
;
102 case FPROUNDING_ZERO
:
103 i
= float_round_to_zero
;
106 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
107 set_float_rounding_mode(i
, &env
->vfp
.fp_status_f16
);
109 if (changed
& FPCR_FZ16
) {
110 bool ftz_enabled
= val
& FPCR_FZ16
;
111 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
112 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status_f16
);
114 if (changed
& FPCR_FZ
) {
115 bool ftz_enabled
= val
& FPCR_FZ
;
116 set_flush_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
117 set_flush_inputs_to_zero(ftz_enabled
, &env
->vfp
.fp_status
);
119 if (changed
& FPCR_DN
) {
120 bool dnan_enabled
= val
& FPCR_DN
;
121 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status
);
122 set_default_nan_mode(dnan_enabled
, &env
->vfp
.fp_status_f16
);
126 * The exception flags are ORed together when we read fpscr so we
127 * only need to preserve the current state in one of our
128 * float_status values.
130 i
= vfp_exceptbits_to_host(val
);
131 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
132 set_float_exception_flags(0, &env
->vfp
.fp_status_f16
);
133 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
136 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
140 fpscr
= env
->vfp
.xregs
[ARM_VFP_FPSCR
]
141 | (env
->vfp
.vec_len
<< 16)
142 | (env
->vfp
.vec_stride
<< 20);
144 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
145 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
146 /* FZ16 does not generate an input denormal exception. */
147 i
|= (get_float_exception_flags(&env
->vfp
.fp_status_f16
)
148 & ~float_flag_input_denormal
);
149 fpscr
|= vfp_exceptbits_from_host(i
);
151 i
= env
->vfp
.qc
[0] | env
->vfp
.qc
[1] | env
->vfp
.qc
[2] | env
->vfp
.qc
[3];
152 fpscr
|= i
? FPCR_QC
: 0;
157 uint32_t vfp_get_fpscr(CPUARMState
*env
)
159 return HELPER(vfp_get_fpscr
)(env
);
162 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
164 /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */
165 if (!cpu_isar_feature(aa64_fp16
, env_archcpu(env
))) {
169 if (arm_feature(env
, ARM_FEATURE_M
)) {
171 * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits
172 * and also for the trapped-exception-handling bits IxE.
178 * We don't implement trapped exception handling, so the
179 * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!)
181 * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC
182 * (which are stored in fp_status), and the other RES0 bits
183 * in between, then we clear all of the low 16 bits.
185 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = val
& 0xf7c80000;
186 env
->vfp
.vec_len
= (val
>> 16) & 7;
187 env
->vfp
.vec_stride
= (val
>> 20) & 3;
190 * The bit we set within fpscr_q is arbitrary; the register as a
191 * whole being zero/non-zero is what counts.
193 env
->vfp
.qc
[0] = val
& FPCR_QC
;
198 vfp_set_fpscr_to_host(env
, val
);
201 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
203 HELPER(vfp_set_fpscr
)(env
, val
);
206 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
208 #define VFP_BINOP(name) \
209 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
211 float_status *fpst = fpstp; \
212 return float32_ ## name(a, b, fpst); \
214 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
216 float_status *fpst = fpstp; \
217 return float64_ ## name(a, b, fpst); \
229 float32
VFP_HELPER(neg
, s
)(float32 a
)
231 return float32_chs(a
);
234 float64
VFP_HELPER(neg
, d
)(float64 a
)
236 return float64_chs(a
);
239 float32
VFP_HELPER(abs
, s
)(float32 a
)
241 return float32_abs(a
);
244 float64
VFP_HELPER(abs
, d
)(float64 a
)
246 return float64_abs(a
);
249 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
251 return float32_sqrt(a
, &env
->vfp
.fp_status
);
254 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
256 return float64_sqrt(a
, &env
->vfp
.fp_status
);
259 static void softfloat_to_vfp_compare(CPUARMState
*env
, int cmp
)
263 case float_relation_equal
:
266 case float_relation_less
:
269 case float_relation_greater
:
272 case float_relation_unordered
:
276 g_assert_not_reached();
278 env
->vfp
.xregs
[ARM_VFP_FPSCR
] =
279 deposit32(env
->vfp
.xregs
[ARM_VFP_FPSCR
], 28, 4, flags
);
282 /* XXX: check quiet/signaling case */
283 #define DO_VFP_cmp(p, type) \
284 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
286 softfloat_to_vfp_compare(env, \
287 type ## _compare_quiet(a, b, &env->vfp.fp_status)); \
289 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
291 softfloat_to_vfp_compare(env, \
292 type ## _compare(a, b, &env->vfp.fp_status)); \
294 DO_VFP_cmp(s
, float32
)
295 DO_VFP_cmp(d
, float64
)
298 /* Integer to float and float to integer conversions */
300 #define CONV_ITOF(name, ftype, fsz, sign) \
301 ftype HELPER(name)(uint32_t x, void *fpstp) \
303 float_status *fpst = fpstp; \
304 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
307 #define CONV_FTOI(name, ftype, fsz, sign, round) \
308 sign##int32_t HELPER(name)(ftype x, void *fpstp) \
310 float_status *fpst = fpstp; \
311 if (float##fsz##_is_any_nan(x)) { \
312 float_raise(float_flag_invalid, fpst); \
315 return float##fsz##_to_##sign##int32##round(x, fpst); \
318 #define FLOAT_CONVS(name, p, ftype, fsz, sign) \
319 CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
320 CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
321 CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
323 FLOAT_CONVS(si
, h
, uint32_t, 16, )
324 FLOAT_CONVS(si
, s
, float32
, 32, )
325 FLOAT_CONVS(si
, d
, float64
, 64, )
326 FLOAT_CONVS(ui
, h
, uint32_t, 16, u
)
327 FLOAT_CONVS(ui
, s
, float32
, 32, u
)
328 FLOAT_CONVS(ui
, d
, float64
, 64, u
)
334 /* floating point conversion */
335 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
337 return float32_to_float64(x
, &env
->vfp
.fp_status
);
340 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
342 return float64_to_float32(x
, &env
->vfp
.fp_status
);
345 /* VFP3 fixed point conversion. */
346 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
347 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t x, uint32_t shift, \
349 { return itype##_to_##float##fsz##_scalbn(x, -shift, fpstp); }
351 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, ROUND, suff) \
352 uint##isz##_t HELPER(vfp_to##name##p##suff)(float##fsz x, uint32_t shift, \
355 if (unlikely(float##fsz##_is_any_nan(x))) { \
356 float_raise(float_flag_invalid, fpst); \
359 return float##fsz##_to_##itype##_scalbn(x, ROUND, shift, fpst); \
362 #define VFP_CONV_FIX(name, p, fsz, isz, itype) \
363 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
364 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
365 float_round_to_zero, _round_to_zero) \
366 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
367 get_float_rounding_mode(fpst), )
369 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype) \
370 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
371 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, \
372 get_float_rounding_mode(fpst), )
374 VFP_CONV_FIX(sh
, d
, 64, 64, int16
)
375 VFP_CONV_FIX(sl
, d
, 64, 64, int32
)
376 VFP_CONV_FIX_A64(sq
, d
, 64, 64, int64
)
377 VFP_CONV_FIX(uh
, d
, 64, 64, uint16
)
378 VFP_CONV_FIX(ul
, d
, 64, 64, uint32
)
379 VFP_CONV_FIX_A64(uq
, d
, 64, 64, uint64
)
380 VFP_CONV_FIX(sh
, s
, 32, 32, int16
)
381 VFP_CONV_FIX(sl
, s
, 32, 32, int32
)
382 VFP_CONV_FIX_A64(sq
, s
, 32, 64, int64
)
383 VFP_CONV_FIX(uh
, s
, 32, 32, uint16
)
384 VFP_CONV_FIX(ul
, s
, 32, 32, uint32
)
385 VFP_CONV_FIX_A64(uq
, s
, 32, 64, uint64
)
388 #undef VFP_CONV_FIX_FLOAT
389 #undef VFP_CONV_FLOAT_FIX_ROUND
390 #undef VFP_CONV_FIX_A64
392 uint32_t HELPER(vfp_sltoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
394 return int32_to_float16_scalbn(x
, -shift
, fpst
);
397 uint32_t HELPER(vfp_ultoh
)(uint32_t x
, uint32_t shift
, void *fpst
)
399 return uint32_to_float16_scalbn(x
, -shift
, fpst
);
402 uint32_t HELPER(vfp_sqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
404 return int64_to_float16_scalbn(x
, -shift
, fpst
);
407 uint32_t HELPER(vfp_uqtoh
)(uint64_t x
, uint32_t shift
, void *fpst
)
409 return uint64_to_float16_scalbn(x
, -shift
, fpst
);
412 uint32_t HELPER(vfp_toshh
)(uint32_t x
, uint32_t shift
, void *fpst
)
414 if (unlikely(float16_is_any_nan(x
))) {
415 float_raise(float_flag_invalid
, fpst
);
418 return float16_to_int16_scalbn(x
, get_float_rounding_mode(fpst
),
422 uint32_t HELPER(vfp_touhh
)(uint32_t x
, uint32_t shift
, void *fpst
)
424 if (unlikely(float16_is_any_nan(x
))) {
425 float_raise(float_flag_invalid
, fpst
);
428 return float16_to_uint16_scalbn(x
, get_float_rounding_mode(fpst
),
432 uint32_t HELPER(vfp_toslh
)(uint32_t x
, uint32_t shift
, void *fpst
)
434 if (unlikely(float16_is_any_nan(x
))) {
435 float_raise(float_flag_invalid
, fpst
);
438 return float16_to_int32_scalbn(x
, get_float_rounding_mode(fpst
),
442 uint32_t HELPER(vfp_toulh
)(uint32_t x
, uint32_t shift
, void *fpst
)
444 if (unlikely(float16_is_any_nan(x
))) {
445 float_raise(float_flag_invalid
, fpst
);
448 return float16_to_uint32_scalbn(x
, get_float_rounding_mode(fpst
),
452 uint64_t HELPER(vfp_tosqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
454 if (unlikely(float16_is_any_nan(x
))) {
455 float_raise(float_flag_invalid
, fpst
);
458 return float16_to_int64_scalbn(x
, get_float_rounding_mode(fpst
),
462 uint64_t HELPER(vfp_touqh
)(uint32_t x
, uint32_t shift
, void *fpst
)
464 if (unlikely(float16_is_any_nan(x
))) {
465 float_raise(float_flag_invalid
, fpst
);
468 return float16_to_uint64_scalbn(x
, get_float_rounding_mode(fpst
),
472 /* Set the current fp rounding mode and return the old one.
473 * The argument is a softfloat float_round_ value.
475 uint32_t HELPER(set_rmode
)(uint32_t rmode
, void *fpstp
)
477 float_status
*fp_status
= fpstp
;
479 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
480 set_float_rounding_mode(rmode
, fp_status
);
485 /* Set the current fp rounding mode in the standard fp status and return
486 * the old one. This is for NEON instructions that need to change the
487 * rounding mode but wish to use the standard FPSCR values for everything
488 * else. Always set the rounding mode back to the correct value after
490 * The argument is a softfloat float_round_ value.
492 uint32_t HELPER(set_neon_rmode
)(uint32_t rmode
, CPUARMState
*env
)
494 float_status
*fp_status
= &env
->vfp
.standard_fp_status
;
496 uint32_t prev_rmode
= get_float_rounding_mode(fp_status
);
497 set_float_rounding_mode(rmode
, fp_status
);
502 /* Half precision conversions. */
503 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
505 /* Squash FZ16 to 0 for the duration of conversion. In this case,
506 * it would affect flushing input denormals.
508 float_status
*fpst
= fpstp
;
509 flag save
= get_flush_inputs_to_zero(fpst
);
510 set_flush_inputs_to_zero(false, fpst
);
511 float32 r
= float16_to_float32(a
, !ahp_mode
, fpst
);
512 set_flush_inputs_to_zero(save
, fpst
);
516 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, void *fpstp
, uint32_t ahp_mode
)
518 /* Squash FZ16 to 0 for the duration of conversion. In this case,
519 * it would affect flushing output denormals.
521 float_status
*fpst
= fpstp
;
522 flag save
= get_flush_to_zero(fpst
);
523 set_flush_to_zero(false, fpst
);
524 float16 r
= float32_to_float16(a
, !ahp_mode
, fpst
);
525 set_flush_to_zero(save
, fpst
);
529 float64
HELPER(vfp_fcvt_f16_to_f64
)(uint32_t a
, void *fpstp
, uint32_t ahp_mode
)
531 /* Squash FZ16 to 0 for the duration of conversion. In this case,
532 * it would affect flushing input denormals.
534 float_status
*fpst
= fpstp
;
535 flag save
= get_flush_inputs_to_zero(fpst
);
536 set_flush_inputs_to_zero(false, fpst
);
537 float64 r
= float16_to_float64(a
, !ahp_mode
, fpst
);
538 set_flush_inputs_to_zero(save
, fpst
);
542 uint32_t HELPER(vfp_fcvt_f64_to_f16
)(float64 a
, void *fpstp
, uint32_t ahp_mode
)
544 /* Squash FZ16 to 0 for the duration of conversion. In this case,
545 * it would affect flushing output denormals.
547 float_status
*fpst
= fpstp
;
548 flag save
= get_flush_to_zero(fpst
);
549 set_flush_to_zero(false, fpst
);
550 float16 r
= float64_to_float16(a
, !ahp_mode
, fpst
);
551 set_flush_to_zero(save
, fpst
);
555 #define float32_two make_float32(0x40000000)
556 #define float32_three make_float32(0x40400000)
557 #define float32_one_point_five make_float32(0x3fc00000)
559 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
561 float_status
*s
= &env
->vfp
.standard_fp_status
;
562 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
563 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
564 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
565 float_raise(float_flag_input_denormal
, s
);
569 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
572 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
574 float_status
*s
= &env
->vfp
.standard_fp_status
;
576 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
577 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
578 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
579 float_raise(float_flag_input_denormal
, s
);
581 return float32_one_point_five
;
583 product
= float32_mul(a
, b
, s
);
584 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
589 /* Constants 256 and 512 are used in some helpers; we avoid relying on
590 * int->float conversions at run-time. */
591 #define float64_256 make_float64(0x4070000000000000LL)
592 #define float64_512 make_float64(0x4080000000000000LL)
593 #define float16_maxnorm make_float16(0x7bff)
594 #define float32_maxnorm make_float32(0x7f7fffff)
595 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
597 /* Reciprocal functions
599 * The algorithm that must be used to calculate the estimate
600 * is specified by the ARM ARM, see FPRecipEstimate()/RecipEstimate
603 /* See RecipEstimate()
605 * input is a 9 bit fixed point number
606 * input range 256 .. 511 for a number from 0.5 <= x < 1.0.
607 * result range 256 .. 511 for a number from 1.0 to 511/256.
610 static int recip_estimate(int input
)
613 assert(256 <= input
&& input
< 512);
617 assert(256 <= r
&& r
< 512);
622 * Common wrapper to call recip_estimate
624 * The parameters are exponent and 64 bit fraction (without implicit
625 * bit) where the binary point is nominally at bit 52. Returns a
626 * float64 which can then be rounded to the appropriate size by the
630 static uint64_t call_recip_estimate(int *exp
, int exp_off
, uint64_t frac
)
632 uint32_t scaled
, estimate
;
633 uint64_t result_frac
;
636 /* Handle sub-normals */
638 if (extract64(frac
, 51, 1) == 0) {
646 /* scaled = UInt('1':fraction<51:44>) */
647 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
648 estimate
= recip_estimate(scaled
);
650 result_exp
= exp_off
- *exp
;
651 result_frac
= deposit64(0, 44, 8, estimate
);
652 if (result_exp
== 0) {
653 result_frac
= deposit64(result_frac
>> 1, 51, 1, 1);
654 } else if (result_exp
== -1) {
655 result_frac
= deposit64(result_frac
>> 2, 50, 2, 1);
664 static bool round_to_inf(float_status
*fpst
, bool sign_bit
)
666 switch (fpst
->float_rounding_mode
) {
667 case float_round_nearest_even
: /* Round to Nearest */
669 case float_round_up
: /* Round to +Inf */
671 case float_round_down
: /* Round to -Inf */
673 case float_round_to_zero
: /* Round to Zero */
677 g_assert_not_reached();
680 uint32_t HELPER(recpe_f16
)(uint32_t input
, void *fpstp
)
682 float_status
*fpst
= fpstp
;
683 float16 f16
= float16_squash_input_denormal(input
, fpst
);
684 uint32_t f16_val
= float16_val(f16
);
685 uint32_t f16_sign
= float16_is_neg(f16
);
686 int f16_exp
= extract32(f16_val
, 10, 5);
687 uint32_t f16_frac
= extract32(f16_val
, 0, 10);
690 if (float16_is_any_nan(f16
)) {
692 if (float16_is_signaling_nan(f16
, fpst
)) {
693 float_raise(float_flag_invalid
, fpst
);
694 nan
= float16_silence_nan(f16
, fpst
);
696 if (fpst
->default_nan_mode
) {
697 nan
= float16_default_nan(fpst
);
700 } else if (float16_is_infinity(f16
)) {
701 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
702 } else if (float16_is_zero(f16
)) {
703 float_raise(float_flag_divbyzero
, fpst
);
704 return float16_set_sign(float16_infinity
, float16_is_neg(f16
));
705 } else if (float16_abs(f16
) < (1 << 8)) {
706 /* Abs(value) < 2.0^-16 */
707 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
708 if (round_to_inf(fpst
, f16_sign
)) {
709 return float16_set_sign(float16_infinity
, f16_sign
);
711 return float16_set_sign(float16_maxnorm
, f16_sign
);
713 } else if (f16_exp
>= 29 && fpst
->flush_to_zero
) {
714 float_raise(float_flag_underflow
, fpst
);
715 return float16_set_sign(float16_zero
, float16_is_neg(f16
));
718 f64_frac
= call_recip_estimate(&f16_exp
, 29,
719 ((uint64_t) f16_frac
) << (52 - 10));
721 /* result = sign : result_exp<4:0> : fraction<51:42> */
722 f16_val
= deposit32(0, 15, 1, f16_sign
);
723 f16_val
= deposit32(f16_val
, 10, 5, f16_exp
);
724 f16_val
= deposit32(f16_val
, 0, 10, extract64(f64_frac
, 52 - 10, 10));
725 return make_float16(f16_val
);
728 float32
HELPER(recpe_f32
)(float32 input
, void *fpstp
)
730 float_status
*fpst
= fpstp
;
731 float32 f32
= float32_squash_input_denormal(input
, fpst
);
732 uint32_t f32_val
= float32_val(f32
);
733 bool f32_sign
= float32_is_neg(f32
);
734 int f32_exp
= extract32(f32_val
, 23, 8);
735 uint32_t f32_frac
= extract32(f32_val
, 0, 23);
738 if (float32_is_any_nan(f32
)) {
740 if (float32_is_signaling_nan(f32
, fpst
)) {
741 float_raise(float_flag_invalid
, fpst
);
742 nan
= float32_silence_nan(f32
, fpst
);
744 if (fpst
->default_nan_mode
) {
745 nan
= float32_default_nan(fpst
);
748 } else if (float32_is_infinity(f32
)) {
749 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
750 } else if (float32_is_zero(f32
)) {
751 float_raise(float_flag_divbyzero
, fpst
);
752 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
753 } else if (float32_abs(f32
) < (1ULL << 21)) {
754 /* Abs(value) < 2.0^-128 */
755 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
756 if (round_to_inf(fpst
, f32_sign
)) {
757 return float32_set_sign(float32_infinity
, f32_sign
);
759 return float32_set_sign(float32_maxnorm
, f32_sign
);
761 } else if (f32_exp
>= 253 && fpst
->flush_to_zero
) {
762 float_raise(float_flag_underflow
, fpst
);
763 return float32_set_sign(float32_zero
, float32_is_neg(f32
));
766 f64_frac
= call_recip_estimate(&f32_exp
, 253,
767 ((uint64_t) f32_frac
) << (52 - 23));
769 /* result = sign : result_exp<7:0> : fraction<51:29> */
770 f32_val
= deposit32(0, 31, 1, f32_sign
);
771 f32_val
= deposit32(f32_val
, 23, 8, f32_exp
);
772 f32_val
= deposit32(f32_val
, 0, 23, extract64(f64_frac
, 52 - 23, 23));
773 return make_float32(f32_val
);
776 float64
HELPER(recpe_f64
)(float64 input
, void *fpstp
)
778 float_status
*fpst
= fpstp
;
779 float64 f64
= float64_squash_input_denormal(input
, fpst
);
780 uint64_t f64_val
= float64_val(f64
);
781 bool f64_sign
= float64_is_neg(f64
);
782 int f64_exp
= extract64(f64_val
, 52, 11);
783 uint64_t f64_frac
= extract64(f64_val
, 0, 52);
785 /* Deal with any special cases */
786 if (float64_is_any_nan(f64
)) {
788 if (float64_is_signaling_nan(f64
, fpst
)) {
789 float_raise(float_flag_invalid
, fpst
);
790 nan
= float64_silence_nan(f64
, fpst
);
792 if (fpst
->default_nan_mode
) {
793 nan
= float64_default_nan(fpst
);
796 } else if (float64_is_infinity(f64
)) {
797 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
798 } else if (float64_is_zero(f64
)) {
799 float_raise(float_flag_divbyzero
, fpst
);
800 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
801 } else if ((f64_val
& ~(1ULL << 63)) < (1ULL << 50)) {
802 /* Abs(value) < 2.0^-1024 */
803 float_raise(float_flag_overflow
| float_flag_inexact
, fpst
);
804 if (round_to_inf(fpst
, f64_sign
)) {
805 return float64_set_sign(float64_infinity
, f64_sign
);
807 return float64_set_sign(float64_maxnorm
, f64_sign
);
809 } else if (f64_exp
>= 2045 && fpst
->flush_to_zero
) {
810 float_raise(float_flag_underflow
, fpst
);
811 return float64_set_sign(float64_zero
, float64_is_neg(f64
));
814 f64_frac
= call_recip_estimate(&f64_exp
, 2045, f64_frac
);
816 /* result = sign : result_exp<10:0> : fraction<51:0>; */
817 f64_val
= deposit64(0, 63, 1, f64_sign
);
818 f64_val
= deposit64(f64_val
, 52, 11, f64_exp
);
819 f64_val
= deposit64(f64_val
, 0, 52, f64_frac
);
820 return make_float64(f64_val
);
823 /* The algorithm that must be used to calculate the estimate
824 * is specified by the ARM ARM.
827 static int do_recip_sqrt_estimate(int a
)
831 assert(128 <= a
&& a
< 512);
839 while (a
* (b
+ 1) * (b
+ 1) < (1 << 28)) {
842 estimate
= (b
+ 1) / 2;
843 assert(256 <= estimate
&& estimate
< 512);
849 static uint64_t recip_sqrt_estimate(int *exp
, int exp_off
, uint64_t frac
)
855 while (extract64(frac
, 51, 1) == 0) {
859 frac
= extract64(frac
, 0, 51) << 1;
863 /* scaled = UInt('01':fraction<51:45>) */
864 scaled
= deposit32(1 << 7, 0, 7, extract64(frac
, 45, 7));
866 /* scaled = UInt('1':fraction<51:44>) */
867 scaled
= deposit32(1 << 8, 0, 8, extract64(frac
, 44, 8));
869 estimate
= do_recip_sqrt_estimate(scaled
);
871 *exp
= (exp_off
- *exp
) / 2;
872 return extract64(estimate
, 0, 8) << 44;
875 uint32_t HELPER(rsqrte_f16
)(uint32_t input
, void *fpstp
)
877 float_status
*s
= fpstp
;
878 float16 f16
= float16_squash_input_denormal(input
, s
);
879 uint16_t val
= float16_val(f16
);
880 bool f16_sign
= float16_is_neg(f16
);
881 int f16_exp
= extract32(val
, 10, 5);
882 uint16_t f16_frac
= extract32(val
, 0, 10);
885 if (float16_is_any_nan(f16
)) {
887 if (float16_is_signaling_nan(f16
, s
)) {
888 float_raise(float_flag_invalid
, s
);
889 nan
= float16_silence_nan(f16
, s
);
891 if (s
->default_nan_mode
) {
892 nan
= float16_default_nan(s
);
895 } else if (float16_is_zero(f16
)) {
896 float_raise(float_flag_divbyzero
, s
);
897 return float16_set_sign(float16_infinity
, f16_sign
);
898 } else if (f16_sign
) {
899 float_raise(float_flag_invalid
, s
);
900 return float16_default_nan(s
);
901 } else if (float16_is_infinity(f16
)) {
905 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
906 * preserving the parity of the exponent. */
908 f64_frac
= ((uint64_t) f16_frac
) << (52 - 10);
910 f64_frac
= recip_sqrt_estimate(&f16_exp
, 44, f64_frac
);
912 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(2) */
913 val
= deposit32(0, 15, 1, f16_sign
);
914 val
= deposit32(val
, 10, 5, f16_exp
);
915 val
= deposit32(val
, 2, 8, extract64(f64_frac
, 52 - 8, 8));
916 return make_float16(val
);
919 float32
HELPER(rsqrte_f32
)(float32 input
, void *fpstp
)
921 float_status
*s
= fpstp
;
922 float32 f32
= float32_squash_input_denormal(input
, s
);
923 uint32_t val
= float32_val(f32
);
924 uint32_t f32_sign
= float32_is_neg(f32
);
925 int f32_exp
= extract32(val
, 23, 8);
926 uint32_t f32_frac
= extract32(val
, 0, 23);
929 if (float32_is_any_nan(f32
)) {
931 if (float32_is_signaling_nan(f32
, s
)) {
932 float_raise(float_flag_invalid
, s
);
933 nan
= float32_silence_nan(f32
, s
);
935 if (s
->default_nan_mode
) {
936 nan
= float32_default_nan(s
);
939 } else if (float32_is_zero(f32
)) {
940 float_raise(float_flag_divbyzero
, s
);
941 return float32_set_sign(float32_infinity
, float32_is_neg(f32
));
942 } else if (float32_is_neg(f32
)) {
943 float_raise(float_flag_invalid
, s
);
944 return float32_default_nan(s
);
945 } else if (float32_is_infinity(f32
)) {
949 /* Scale and normalize to a double-precision value between 0.25 and 1.0,
950 * preserving the parity of the exponent. */
952 f64_frac
= ((uint64_t) f32_frac
) << 29;
954 f64_frac
= recip_sqrt_estimate(&f32_exp
, 380, f64_frac
);
956 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(15) */
957 val
= deposit32(0, 31, 1, f32_sign
);
958 val
= deposit32(val
, 23, 8, f32_exp
);
959 val
= deposit32(val
, 15, 8, extract64(f64_frac
, 52 - 8, 8));
960 return make_float32(val
);
963 float64
HELPER(rsqrte_f64
)(float64 input
, void *fpstp
)
965 float_status
*s
= fpstp
;
966 float64 f64
= float64_squash_input_denormal(input
, s
);
967 uint64_t val
= float64_val(f64
);
968 bool f64_sign
= float64_is_neg(f64
);
969 int f64_exp
= extract64(val
, 52, 11);
970 uint64_t f64_frac
= extract64(val
, 0, 52);
972 if (float64_is_any_nan(f64
)) {
974 if (float64_is_signaling_nan(f64
, s
)) {
975 float_raise(float_flag_invalid
, s
);
976 nan
= float64_silence_nan(f64
, s
);
978 if (s
->default_nan_mode
) {
979 nan
= float64_default_nan(s
);
982 } else if (float64_is_zero(f64
)) {
983 float_raise(float_flag_divbyzero
, s
);
984 return float64_set_sign(float64_infinity
, float64_is_neg(f64
));
985 } else if (float64_is_neg(f64
)) {
986 float_raise(float_flag_invalid
, s
);
987 return float64_default_nan(s
);
988 } else if (float64_is_infinity(f64
)) {
992 f64_frac
= recip_sqrt_estimate(&f64_exp
, 3068, f64_frac
);
994 /* result = sign : result_exp<4:0> : estimate<7:0> : Zeros(44) */
995 val
= deposit64(0, 61, 1, f64_sign
);
996 val
= deposit64(val
, 52, 11, f64_exp
);
997 val
= deposit64(val
, 44, 8, extract64(f64_frac
, 52 - 8, 8));
998 return make_float64(val
);
1001 uint32_t HELPER(recpe_u32
)(uint32_t a
, void *fpstp
)
1003 /* float_status *s = fpstp; */
1004 int input
, estimate
;
1006 if ((a
& 0x80000000) == 0) {
1010 input
= extract32(a
, 23, 9);
1011 estimate
= recip_estimate(input
);
1013 return deposit32(0, (32 - 9), 9, estimate
);
1016 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, void *fpstp
)
1020 if ((a
& 0xc0000000) == 0) {
1024 estimate
= do_recip_sqrt_estimate(extract32(a
, 23, 9));
1026 return deposit32(0, 23, 9, estimate
);
1029 /* VFPv4 fused multiply-accumulate */
1030 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
1032 float_status
*fpst
= fpstp
;
1033 return float32_muladd(a
, b
, c
, 0, fpst
);
1036 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
1038 float_status
*fpst
= fpstp
;
1039 return float64_muladd(a
, b
, c
, 0, fpst
);
1042 /* ARMv8 round to integral */
1043 float32
HELPER(rints_exact
)(float32 x
, void *fp_status
)
1045 return float32_round_to_int(x
, fp_status
);
1048 float64
HELPER(rintd_exact
)(float64 x
, void *fp_status
)
1050 return float64_round_to_int(x
, fp_status
);
1053 float32
HELPER(rints
)(float32 x
, void *fp_status
)
1055 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1058 ret
= float32_round_to_int(x
, fp_status
);
1060 /* Suppress any inexact exceptions the conversion produced */
1061 if (!(old_flags
& float_flag_inexact
)) {
1062 new_flags
= get_float_exception_flags(fp_status
);
1063 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1069 float64
HELPER(rintd
)(float64 x
, void *fp_status
)
1071 int old_flags
= get_float_exception_flags(fp_status
), new_flags
;
1074 ret
= float64_round_to_int(x
, fp_status
);
1076 new_flags
= get_float_exception_flags(fp_status
);
1078 /* Suppress any inexact exceptions the conversion produced */
1079 if (!(old_flags
& float_flag_inexact
)) {
1080 new_flags
= get_float_exception_flags(fp_status
);
1081 set_float_exception_flags(new_flags
& ~float_flag_inexact
, fp_status
);
1087 /* Convert ARM rounding mode to softfloat */
1088 int arm_rmode_to_sf(int rmode
)
1091 case FPROUNDING_TIEAWAY
:
1092 rmode
= float_round_ties_away
;
1094 case FPROUNDING_ODD
:
1095 /* FIXME: add support for TIEAWAY and ODD */
1096 qemu_log_mask(LOG_UNIMP
, "arm: unimplemented rounding mode: %d\n",
1098 /* fall through for now */
1099 case FPROUNDING_TIEEVEN
:
1101 rmode
= float_round_nearest_even
;
1103 case FPROUNDING_POSINF
:
1104 rmode
= float_round_up
;
1106 case FPROUNDING_NEGINF
:
1107 rmode
= float_round_down
;
1109 case FPROUNDING_ZERO
:
1110 rmode
= float_round_to_zero
;
1117 * Implement float64 to int32_t conversion without saturation;
1118 * the result is supplied modulo 2^32.
1120 uint64_t HELPER(fjcvtzs
)(float64 value
, void *vstatus
)
1122 float_status
*status
= vstatus
;
1125 uint32_t inexact
= 1; /* !Z */
1127 sign
= extract64(value
, 63, 1);
1128 exp
= extract64(value
, 52, 11);
1129 frac
= extract64(value
, 0, 52);
1132 /* While not inexact for IEEE FP, -0.0 is inexact for JavaScript. */
1135 if (status
->flush_inputs_to_zero
) {
1136 float_raise(float_flag_input_denormal
, status
);
1138 float_raise(float_flag_inexact
, status
);
1143 } else if (exp
== 0x7ff) {
1144 /* This operation raises Invalid for both NaN and overflow (Inf). */
1145 float_raise(float_flag_invalid
, status
);
1148 int true_exp
= exp
- 1023;
1149 int shift
= true_exp
- 52;
1151 /* Restore implicit bit. */
1154 /* Shift the fraction into place. */
1156 /* The number is so large we must shift the fraction left. */
1158 /* The fraction is shifted out entirely. */
1163 } else if (shift
> -64) {
1164 /* Normal case -- shift right and notice if bits shift out. */
1165 inexact
= (frac
<< (64 + shift
)) != 0;
1168 /* The fraction is shifted out entirely. */
1172 /* Notice overflow or inexact exceptions. */
1173 if (true_exp
> 31 || frac
> (sign
? 0x80000000ull
: 0x7fffffff)) {
1174 /* Overflow, for which this operation raises invalid. */
1175 float_raise(float_flag_invalid
, status
);
1177 } else if (inexact
) {
1178 float_raise(float_flag_inexact
, status
);
1181 /* Honor the sign. */
1187 /* Pack the result and the env->ZF representation of Z together. */
1188 return deposit64(frac
, 32, 32, inexact
);
1191 uint32_t HELPER(vjcvt
)(float64 value
, CPUARMState
*env
)
1193 uint64_t pair
= HELPER(fjcvtzs
)(value
, &env
->vfp
.fp_status
);
1194 uint32_t result
= pair
;
1195 uint32_t z
= (pair
>> 32) == 0;
1197 /* Store Z, clear NCV, in FPSCR.NZCV. */
1198 env
->vfp
.xregs
[ARM_VFP_FPSCR
]
1199 = (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & ~CPSR_NZCV
) | (z
* CPSR_Z
);
1204 /* Round a float32 to an integer that fits in int32_t or int64_t. */
1205 static float32
frint_s(float32 f
, float_status
*fpst
, int intsize
)
1207 int old_flags
= get_float_exception_flags(fpst
);
1208 uint32_t exp
= extract32(f
, 23, 8);
1210 if (unlikely(exp
== 0xff)) {
1215 /* Round and re-extract the exponent. */
1216 f
= float32_round_to_int(f
, fpst
);
1217 exp
= extract32(f
, 23, 8);
1219 /* Validate the range of the result. */
1220 if (exp
< 126 + intsize
) {
1221 /* abs(F) <= INT{N}_MAX */
1224 if (exp
== 126 + intsize
) {
1225 uint32_t sign
= extract32(f
, 31, 1);
1226 uint32_t frac
= extract32(f
, 0, 23);
1227 if (sign
&& frac
== 0) {
1228 /* F == INT{N}_MIN */
1235 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1236 * inexact exception float32_round_to_int may have raised.
1238 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1239 return (0x100u
+ 126u + intsize
) << 23;
1242 float32
HELPER(frint32_s
)(float32 f
, void *fpst
)
1244 return frint_s(f
, fpst
, 32);
1247 float32
HELPER(frint64_s
)(float32 f
, void *fpst
)
1249 return frint_s(f
, fpst
, 64);
1252 /* Round a float64 to an integer that fits in int32_t or int64_t. */
1253 static float64
frint_d(float64 f
, float_status
*fpst
, int intsize
)
1255 int old_flags
= get_float_exception_flags(fpst
);
1256 uint32_t exp
= extract64(f
, 52, 11);
1258 if (unlikely(exp
== 0x7ff)) {
1263 /* Round and re-extract the exponent. */
1264 f
= float64_round_to_int(f
, fpst
);
1265 exp
= extract64(f
, 52, 11);
1267 /* Validate the range of the result. */
1268 if (exp
< 1022 + intsize
) {
1269 /* abs(F) <= INT{N}_MAX */
1272 if (exp
== 1022 + intsize
) {
1273 uint64_t sign
= extract64(f
, 63, 1);
1274 uint64_t frac
= extract64(f
, 0, 52);
1275 if (sign
&& frac
== 0) {
1276 /* F == INT{N}_MIN */
1283 * Raise Invalid and return INT{N}_MIN as a float. Revert any
1284 * inexact exception float64_round_to_int may have raised.
1286 set_float_exception_flags(old_flags
| float_flag_invalid
, fpst
);
1287 return (uint64_t)(0x800 + 1022 + intsize
) << 52;
1290 float64
HELPER(frint32_d
)(float64 f
, void *fpst
)
1292 return frint_d(f
, fpst
, 32);
1295 float64
HELPER(frint64_d
)(float64 f
, void *fpst
)
1297 return frint_d(f
, fpst
, 64);