target/avr/cpu.c

   1 /*
   2  * QEMU AVR CPU
   3  *
   4  * Copyright (c) 2019-2020 Michael Rolnik
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "qemu/qemu-print.h"
  24 #include "exec/exec-all.h"
  25 #include "cpu.h"
  26 #include "disas/dis-asm.h"
  27 #include "tcg/debug-assert.h"
  28
  29 static void avr_cpu_set_pc(CPUState *cs, vaddr value)
  30 {
  31     AVRCPU *cpu = AVR_CPU(cs);
  32
  33     cpu->env.pc_w = value / 2; /* internally PC points to words */
  34 }
  35
  36 static vaddr avr_cpu_get_pc(CPUState *cs)
  37 {
  38     AVRCPU *cpu = AVR_CPU(cs);
  39
  40     return cpu->env.pc_w * 2;
  41 }
  42
  43 static bool avr_cpu_has_work(CPUState *cs)
  44 {
  45     AVRCPU *cpu = AVR_CPU(cs);
  46     CPUAVRState *env = &cpu->env;
  47
  48     return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET))
  49             && cpu_interrupts_enabled(env);
  50 }
  51
  52 static void avr_cpu_synchronize_from_tb(CPUState *cs,
  53                                         const TranslationBlock *tb)
  54 {
  55     AVRCPU *cpu = AVR_CPU(cs);
  56     CPUAVRState *env = &cpu->env;
  57
  58     tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
  59     env->pc_w = tb->pc / 2; /* internally PC points to words */
  60 }
  61
  62 static void avr_restore_state_to_opc(CPUState *cs,
  63                                      const TranslationBlock *tb,
  64                                      const uint64_t *data)
  65 {
  66     AVRCPU *cpu = AVR_CPU(cs);
  67     CPUAVRState *env = &cpu->env;
  68
  69     env->pc_w = data[0];
  70 }
  71
  72 static void avr_cpu_reset_hold(Object *obj)
  73 {
  74     CPUState *cs = CPU(obj);
  75     AVRCPU *cpu = AVR_CPU(cs);
  76     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(cpu);
  77     CPUAVRState *env = &cpu->env;
  78
  79     if (mcc->parent_phases.hold) {
  80         mcc->parent_phases.hold(obj);
  81     }
  82
  83     env->pc_w = 0;
  84     env->sregI = 1;
  85     env->sregC = 0;
  86     env->sregZ = 0;
  87     env->sregN = 0;
  88     env->sregV = 0;
  89     env->sregS = 0;
  90     env->sregH = 0;
  91     env->sregT = 0;
  92
  93     env->rampD = 0;
  94     env->rampX = 0;
  95     env->rampY = 0;
  96     env->rampZ = 0;
  97     env->eind = 0;
  98     env->sp = 0;
  99
 100     env->skip = 0;
 101
 102     memset(env->r, 0, sizeof(env->r));
 103 }
 104
 105 static void avr_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
 106 {
 107     info->mach = bfd_arch_avr;
 108     info->print_insn = avr_print_insn;
 109 }
 110
 111 static void avr_cpu_realizefn(DeviceState *dev, Error **errp)
 112 {
 113     CPUState *cs = CPU(dev);
 114     AVRCPUClass *mcc = AVR_CPU_GET_CLASS(dev);
 115     Error *local_err = NULL;
 116
 117     cpu_exec_realizefn(cs, &local_err);
 118     if (local_err != NULL) {
 119         error_propagate(errp, local_err);
 120         return;
 121     }
 122     qemu_init_vcpu(cs);
 123     cpu_reset(cs);
 124
 125     mcc->parent_realize(dev, errp);
 126 }
 127
 128 static void avr_cpu_set_int(void *opaque, int irq, int level)
 129 {
 130     AVRCPU *cpu = opaque;
 131     CPUAVRState *env = &cpu->env;
 132     CPUState *cs = CPU(cpu);
 133     uint64_t mask = (1ull << irq);
 134
 135     if (level) {
 136         env->intsrc |= mask;
 137         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 138     } else {
 139         env->intsrc &= ~mask;
 140         if (env->intsrc == 0) {
 141             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 142         }
 143     }
 144 }
 145
 146 static void avr_cpu_initfn(Object *obj)
 147 {
 148     AVRCPU *cpu = AVR_CPU(obj);
 149
 150     cpu_set_cpustate_pointers(cpu);
 151
 152     /* Set the number of interrupts supported by the CPU. */
 153     qdev_init_gpio_in(DEVICE(cpu), avr_cpu_set_int,
 154                       sizeof(cpu->env.intsrc) * 8);
 155 }
 156
 157 static ObjectClass *avr_cpu_class_by_name(const char *cpu_model)
 158 {
 159     ObjectClass *oc;
 160
 161     oc = object_class_by_name(cpu_model);
 162     if (object_class_dynamic_cast(oc, TYPE_AVR_CPU) == NULL ||
 163         object_class_is_abstract(oc)) {
 164         oc = NULL;
 165     }
 166     return oc;
 167 }
 168
 169 static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 170 {
 171     AVRCPU *cpu = AVR_CPU(cs);
 172     CPUAVRState *env = &cpu->env;
 173     int i;
 174
 175     qemu_fprintf(f, "\n");
 176     qemu_fprintf(f, "PC:    %06x\n", env->pc_w * 2); /* PC points to words */
 177     qemu_fprintf(f, "SP:      %04x\n", env->sp);
 178     qemu_fprintf(f, "rampD:     %02x\n", env->rampD >> 16);
 179     qemu_fprintf(f, "rampX:     %02x\n", env->rampX >> 16);
 180     qemu_fprintf(f, "rampY:     %02x\n", env->rampY >> 16);
 181     qemu_fprintf(f, "rampZ:     %02x\n", env->rampZ >> 16);
 182     qemu_fprintf(f, "EIND:      %02x\n", env->eind >> 16);
 183     qemu_fprintf(f, "X:       %02x%02x\n", env->r[27], env->r[26]);
 184     qemu_fprintf(f, "Y:       %02x%02x\n", env->r[29], env->r[28]);
 185     qemu_fprintf(f, "Z:       %02x%02x\n", env->r[31], env->r[30]);
 186     qemu_fprintf(f, "SREG:    [ %c %c %c %c %c %c %c %c ]\n",
 187                  env->sregI ? 'I' : '-',
 188                  env->sregT ? 'T' : '-',
 189                  env->sregH ? 'H' : '-',
 190                  env->sregS ? 'S' : '-',
 191                  env->sregV ? 'V' : '-',
 192                  env->sregN ? '-' : 'N', /* Zf has negative logic */
 193                  env->sregZ ? 'Z' : '-',
 194                  env->sregC ? 'I' : '-');
 195     qemu_fprintf(f, "SKIP:    %02x\n", env->skip);
 196
 197     qemu_fprintf(f, "\n");
 198     for (i = 0; i < ARRAY_SIZE(env->r); i++) {
 199         qemu_fprintf(f, "R[%02d]:  %02x   ", i, env->r[i]);
 200
 201         if ((i % 8) == 7) {
 202             qemu_fprintf(f, "\n");
 203         }
 204     }
 205     qemu_fprintf(f, "\n");
 206 }
 207
 208 #include "hw/core/sysemu-cpu-ops.h"
 209
 210 static const struct SysemuCPUOps avr_sysemu_ops = {
 211     .get_phys_page_debug = avr_cpu_get_phys_page_debug,
 212 };
 213
 214 #include "hw/core/tcg-cpu-ops.h"
 215
 216 static const struct TCGCPUOps avr_tcg_ops = {
 217     .initialize = avr_cpu_tcg_init,
 218     .synchronize_from_tb = avr_cpu_synchronize_from_tb,
 219     .restore_state_to_opc = avr_restore_state_to_opc,
 220     .cpu_exec_interrupt = avr_cpu_exec_interrupt,
 221     .tlb_fill = avr_cpu_tlb_fill,
 222     .do_interrupt = avr_cpu_do_interrupt,
 223 };
 224
 225 static void avr_cpu_class_init(ObjectClass *oc, void *data)
 226 {
 227     DeviceClass *dc = DEVICE_CLASS(oc);
 228     CPUClass *cc = CPU_CLASS(oc);
 229     AVRCPUClass *mcc = AVR_CPU_CLASS(oc);
 230     ResettableClass *rc = RESETTABLE_CLASS(oc);
 231
 232     device_class_set_parent_realize(dc, avr_cpu_realizefn, &mcc->parent_realize);
 233
 234     resettable_class_set_parent_phases(rc, NULL, avr_cpu_reset_hold, NULL,
 235                                        &mcc->parent_phases);
 236
 237     cc->class_by_name = avr_cpu_class_by_name;
 238
 239     cc->has_work = avr_cpu_has_work;
 240     cc->dump_state = avr_cpu_dump_state;
 241     cc->set_pc = avr_cpu_set_pc;
 242     cc->get_pc = avr_cpu_get_pc;
 243     dc->vmsd = &vms_avr_cpu;
 244     cc->sysemu_ops = &avr_sysemu_ops;
 245     cc->disas_set_info = avr_cpu_disas_set_info;
 246     cc->gdb_read_register = avr_cpu_gdb_read_register;
 247     cc->gdb_write_register = avr_cpu_gdb_write_register;
 248     cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;
 249     cc->gdb_num_core_regs = 35;
 250     cc->gdb_core_xml_file = "avr-cpu.xml";
 251     cc->tcg_ops = &avr_tcg_ops;
 252 }
 253
 254 /*
 255  * Setting features of AVR core type avr5
 256  * --------------------------------------
 257  *
 258  * This type of AVR core is present in the following AVR MCUs:
 259  *
 260  * ata5702m322, ata5782, ata5790, ata5790n, ata5791, ata5795, ata5831, ata6613c,
 261  * ata6614q, ata8210, ata8510, atmega16, atmega16a, atmega161, atmega162,
 262  * atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a,
 263  * atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa,
 264  * atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega16hvb,
 265  * atmega16hvbrevb, atmega16m1, atmega16u4, atmega32a, atmega32, atmega323,
 266  * atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p,
 267  * atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328,
 268  * atmega328p, atmega328pb, atmega329, atmega329a, atmega329p, atmega329pa,
 269  * atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega32c1, atmega32m1,
 270  * atmega32u4, atmega32u6, atmega406, atmega64, atmega64a, atmega640, atmega644,
 271  * atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p,
 272  * atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p,
 273  * atmega6490, atmega16hva, atmega16hva2, atmega32hvb, atmega6490a, atmega6490p,
 274  * atmega64c1, atmega64m1, atmega64hve, atmega64hve2, atmega64rfr2,
 275  * atmega644rfr2, atmega32hvbrevb, at90can32, at90can64, at90pwm161, at90pwm216,
 276  * at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000
 277  */
 278 static void avr_avr5_initfn(Object *obj)
 279 {
 280     AVRCPU *cpu = AVR_CPU(obj);
 281     CPUAVRState *env = &cpu->env;
 282
 283     set_avr_feature(env, AVR_FEATURE_LPM);
 284     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 285     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 286     set_avr_feature(env, AVR_FEATURE_SRAM);
 287     set_avr_feature(env, AVR_FEATURE_BREAK);
 288
 289     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 290     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 291     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 292     set_avr_feature(env, AVR_FEATURE_LPMX);
 293     set_avr_feature(env, AVR_FEATURE_MOVW);
 294     set_avr_feature(env, AVR_FEATURE_MUL);
 295 }
 296
 297 /*
 298  * Setting features of AVR core type avr51
 299  * --------------------------------------
 300  *
 301  * This type of AVR core is present in the following AVR MCUs:
 302  *
 303  * atmega128, atmega128a, atmega1280, atmega1281, atmega1284, atmega1284p,
 304  * atmega128rfa1, atmega128rfr2, atmega1284rfr2, at90can128, at90usb1286,
 305  * at90usb1287
 306  */
 307 static void avr_avr51_initfn(Object *obj)
 308 {
 309     AVRCPU *cpu = AVR_CPU(obj);
 310     CPUAVRState *env = &cpu->env;
 311
 312     set_avr_feature(env, AVR_FEATURE_LPM);
 313     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 314     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 315     set_avr_feature(env, AVR_FEATURE_SRAM);
 316     set_avr_feature(env, AVR_FEATURE_BREAK);
 317
 318     set_avr_feature(env, AVR_FEATURE_2_BYTE_PC);
 319     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 320     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 321     set_avr_feature(env, AVR_FEATURE_ELPMX);
 322     set_avr_feature(env, AVR_FEATURE_ELPM);
 323     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 324     set_avr_feature(env, AVR_FEATURE_LPMX);
 325     set_avr_feature(env, AVR_FEATURE_MOVW);
 326     set_avr_feature(env, AVR_FEATURE_MUL);
 327 }
 328
 329 /*
 330  * Setting features of AVR core type avr6
 331  * --------------------------------------
 332  *
 333  * This type of AVR core is present in the following AVR MCUs:
 334  *
 335  * atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2
 336  */
 337 static void avr_avr6_initfn(Object *obj)
 338 {
 339     AVRCPU *cpu = AVR_CPU(obj);
 340     CPUAVRState *env = &cpu->env;
 341
 342     set_avr_feature(env, AVR_FEATURE_LPM);
 343     set_avr_feature(env, AVR_FEATURE_IJMP_ICALL);
 344     set_avr_feature(env, AVR_FEATURE_ADIW_SBIW);
 345     set_avr_feature(env, AVR_FEATURE_SRAM);
 346     set_avr_feature(env, AVR_FEATURE_BREAK);
 347
 348     set_avr_feature(env, AVR_FEATURE_3_BYTE_PC);
 349     set_avr_feature(env, AVR_FEATURE_2_BYTE_SP);
 350     set_avr_feature(env, AVR_FEATURE_RAMPZ);
 351     set_avr_feature(env, AVR_FEATURE_EIJMP_EICALL);
 352     set_avr_feature(env, AVR_FEATURE_ELPMX);
 353     set_avr_feature(env, AVR_FEATURE_ELPM);
 354     set_avr_feature(env, AVR_FEATURE_JMP_CALL);
 355     set_avr_feature(env, AVR_FEATURE_LPMX);
 356     set_avr_feature(env, AVR_FEATURE_MOVW);
 357     set_avr_feature(env, AVR_FEATURE_MUL);
 358 }
 359
 360 typedef struct AVRCPUInfo {
 361     const char *name;
 362     void (*initfn)(Object *obj);
 363 } AVRCPUInfo;
 364
 365
 366 static void avr_cpu_list_entry(gpointer data, gpointer user_data)
 367 {
 368     const char *typename = object_class_get_name(OBJECT_CLASS(data));
 369
 370     qemu_printf("%s\n", typename);
 371 }
 372
 373 void avr_cpu_list(void)
 374 {
 375     GSList *list;
 376     list = object_class_get_list_sorted(TYPE_AVR_CPU, false);
 377     g_slist_foreach(list, avr_cpu_list_entry, NULL);
 378     g_slist_free(list);
 379 }
 380
 381 #define DEFINE_AVR_CPU_TYPE(model, initfn) \
 382     { \
 383         .parent = TYPE_AVR_CPU, \
 384         .instance_init = initfn, \
 385         .name = AVR_CPU_TYPE_NAME(model), \
 386     }
 387
 388 static const TypeInfo avr_cpu_type_info[] = {
 389     {
 390         .name = TYPE_AVR_CPU,
 391         .parent = TYPE_CPU,
 392         .instance_size = sizeof(AVRCPU),
 393         .instance_align = __alignof(AVRCPU),
 394         .instance_init = avr_cpu_initfn,
 395         .class_size = sizeof(AVRCPUClass),
 396         .class_init = avr_cpu_class_init,
 397         .abstract = true,
 398     },
 399     DEFINE_AVR_CPU_TYPE("avr5", avr_avr5_initfn),
 400     DEFINE_AVR_CPU_TYPE("avr51", avr_avr51_initfn),
 401     DEFINE_AVR_CPU_TYPE("avr6", avr_avr6_initfn),
 402 };
 403
 404 DEFINE_TYPES(avr_cpu_type_info)