4 * Copyright (c) 2016-2020 Michael Rolnik
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
24 #include "hw/core/tcg-cpu-ops.h"
25 #include "exec/exec-all.h"
26 #include "exec/address-spaces.h"
27 #include "exec/helper-proto.h"
29 bool avr_cpu_exec_interrupt(CPUState
*cs
, int interrupt_request
)
32 CPUClass
*cc
= CPU_GET_CLASS(cs
);
33 AVRCPU
*cpu
= AVR_CPU(cs
);
34 CPUAVRState
*env
= &cpu
->env
;
36 if (interrupt_request
& CPU_INTERRUPT_RESET
) {
37 if (cpu_interrupts_enabled(env
)) {
38 cs
->exception_index
= EXCP_RESET
;
39 cc
->tcg_ops
->do_interrupt(cs
);
41 cs
->interrupt_request
&= ~CPU_INTERRUPT_RESET
;
46 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
47 if (cpu_interrupts_enabled(env
) && env
->intsrc
!= 0) {
48 int index
= ctz32(env
->intsrc
);
49 cs
->exception_index
= EXCP_INT(index
);
50 cc
->tcg_ops
->do_interrupt(cs
);
52 env
->intsrc
&= env
->intsrc
- 1; /* clear the interrupt */
54 cs
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
63 void avr_cpu_do_interrupt(CPUState
*cs
)
65 AVRCPU
*cpu
= AVR_CPU(cs
);
66 CPUAVRState
*env
= &cpu
->env
;
68 uint32_t ret
= env
->pc_w
;
70 int size
= avr_feature(env
, AVR_FEATURE_JMP_CALL
) ? 2 : 1;
73 if (cs
->exception_index
== EXCP_RESET
) {
75 } else if (env
->intsrc
!= 0) {
76 vector
= ctz32(env
->intsrc
) + 1;
79 if (avr_feature(env
, AVR_FEATURE_3_BYTE_PC
)) {
80 cpu_stb_data(env
, env
->sp
--, (ret
& 0x0000ff));
81 cpu_stb_data(env
, env
->sp
--, (ret
& 0x00ff00) >> 8);
82 cpu_stb_data(env
, env
->sp
--, (ret
& 0xff0000) >> 16);
83 } else if (avr_feature(env
, AVR_FEATURE_2_BYTE_PC
)) {
84 cpu_stb_data(env
, env
->sp
--, (ret
& 0x0000ff));
85 cpu_stb_data(env
, env
->sp
--, (ret
& 0x00ff00) >> 8);
87 cpu_stb_data(env
, env
->sp
--, (ret
& 0x0000ff));
90 env
->pc_w
= base
+ vector
* size
;
91 env
->sregI
= 0; /* clear Global Interrupt Flag */
93 cs
->exception_index
= -1;
96 int avr_cpu_memory_rw_debug(CPUState
*cs
, vaddr addr
, uint8_t *buf
,
97 int len
, bool is_write
)
99 return cpu_memory_rw_debug(cs
, addr
, buf
, len
, is_write
);
102 hwaddr
avr_cpu_get_phys_page_debug(CPUState
*cs
, vaddr addr
)
104 return addr
; /* I assume 1:1 address correspondence */
107 bool avr_cpu_tlb_fill(CPUState
*cs
, vaddr address
, int size
,
108 MMUAccessType access_type
, int mmu_idx
,
109 bool probe
, uintptr_t retaddr
)
112 MemTxAttrs attrs
= {};
115 address
&= TARGET_PAGE_MASK
;
117 if (mmu_idx
== MMU_CODE_IDX
) {
118 /* access to code in flash */
119 paddr
= OFFSET_CODE
+ address
;
120 prot
= PAGE_READ
| PAGE_EXEC
;
121 if (paddr
+ TARGET_PAGE_SIZE
> OFFSET_DATA
) {
122 error_report("execution left flash memory");
125 } else if (address
< NUMBER_OF_CPU_REGISTERS
+ NUMBER_OF_IO_REGISTERS
) {
127 * access to CPU registers, exit and rebuilt this TB to use full access
128 * incase it touches specially handled registers like SREG or SP
130 AVRCPU
*cpu
= AVR_CPU(cs
);
131 CPUAVRState
*env
= &cpu
->env
;
133 cpu_loop_exit_restore(cs
, retaddr
);
135 /* access to memory. nothing special */
136 paddr
= OFFSET_DATA
+ address
;
137 prot
= PAGE_READ
| PAGE_WRITE
;
140 tlb_set_page_with_attrs(cs
, address
, paddr
, attrs
, prot
,
141 mmu_idx
, TARGET_PAGE_SIZE
);
150 void helper_sleep(CPUAVRState
*env
)
152 CPUState
*cs
= env_cpu(env
);
154 cs
->exception_index
= EXCP_HLT
;
158 void helper_unsupported(CPUAVRState
*env
)
160 CPUState
*cs
= env_cpu(env
);
163 * I count not find what happens on the real platform, so
164 * it's EXCP_DEBUG for meanwhile
166 cs
->exception_index
= EXCP_DEBUG
;
167 if (qemu_loglevel_mask(LOG_UNIMP
)) {
168 qemu_log("UNSUPPORTED\n");
169 cpu_dump_state(cs
, stderr
, 0);
174 void helper_debug(CPUAVRState
*env
)
176 CPUState
*cs
= env_cpu(env
);
178 cs
->exception_index
= EXCP_DEBUG
;
182 void helper_break(CPUAVRState
*env
)
184 CPUState
*cs
= env_cpu(env
);
186 cs
->exception_index
= EXCP_DEBUG
;
190 void helper_wdr(CPUAVRState
*env
)
192 qemu_log_mask(LOG_UNIMP
, "WDG reset (not implemented)\n");
196 * This function implements IN instruction
198 * It does the following
199 * a. if an IO register belongs to CPU, its value is read and returned
200 * b. otherwise io address is translated to mem address and physical memory
202 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
205 target_ulong
helper_inb(CPUAVRState
*env
, uint32_t port
)
207 target_ulong data
= 0;
210 case 0x38: /* RAMPD */
211 data
= 0xff & (env
->rampD
>> 16);
213 case 0x39: /* RAMPX */
214 data
= 0xff & (env
->rampX
>> 16);
216 case 0x3a: /* RAMPY */
217 data
= 0xff & (env
->rampY
>> 16);
219 case 0x3b: /* RAMPZ */
220 data
= 0xff & (env
->rampZ
>> 16);
222 case 0x3c: /* EIND */
223 data
= 0xff & (env
->eind
>> 16);
226 data
= env
->sp
& 0x00ff;
231 case 0x3f: /* SREG */
232 data
= cpu_get_sreg(env
);
235 /* not a special register, pass to normal memory access */
236 data
= address_space_ldub(&address_space_memory
,
237 OFFSET_IO_REGISTERS
+ port
,
238 MEMTXATTRS_UNSPECIFIED
, NULL
);
245 * This function implements OUT instruction
247 * It does the following
248 * a. if an IO register belongs to CPU, its value is written into the register
249 * b. otherwise io address is translated to mem address and physical memory
251 * c. it caches the value for sake of SBI, SBIC, SBIS & CBI implementation
254 void helper_outb(CPUAVRState
*env
, uint32_t port
, uint32_t data
)
259 case 0x38: /* RAMPD */
260 if (avr_feature(env
, AVR_FEATURE_RAMPD
)) {
261 env
->rampD
= (data
& 0xff) << 16;
264 case 0x39: /* RAMPX */
265 if (avr_feature(env
, AVR_FEATURE_RAMPX
)) {
266 env
->rampX
= (data
& 0xff) << 16;
269 case 0x3a: /* RAMPY */
270 if (avr_feature(env
, AVR_FEATURE_RAMPY
)) {
271 env
->rampY
= (data
& 0xff) << 16;
274 case 0x3b: /* RAMPZ */
275 if (avr_feature(env
, AVR_FEATURE_RAMPZ
)) {
276 env
->rampZ
= (data
& 0xff) << 16;
279 case 0x3c: /* EIDN */
280 env
->eind
= (data
& 0xff) << 16;
283 env
->sp
= (env
->sp
& 0xff00) | (data
);
286 if (avr_feature(env
, AVR_FEATURE_2_BYTE_SP
)) {
287 env
->sp
= (env
->sp
& 0x00ff) | (data
<< 8);
290 case 0x3f: /* SREG */
291 cpu_set_sreg(env
, data
);
294 /* not a special register, pass to normal memory access */
295 address_space_stb(&address_space_memory
, OFFSET_IO_REGISTERS
+ port
,
296 data
, MEMTXATTRS_UNSPECIFIED
, NULL
);
301 * this function implements LD instruction when there is a possibility to read
302 * from a CPU register
304 target_ulong
helper_fullrd(CPUAVRState
*env
, uint32_t addr
)
308 env
->fullacc
= false;
310 if (addr
< NUMBER_OF_CPU_REGISTERS
) {
313 } else if (addr
< NUMBER_OF_CPU_REGISTERS
+ NUMBER_OF_IO_REGISTERS
) {
315 data
= helper_inb(env
, addr
- NUMBER_OF_CPU_REGISTERS
);
318 data
= address_space_ldub(&address_space_memory
, OFFSET_DATA
+ addr
,
319 MEMTXATTRS_UNSPECIFIED
, NULL
);
325 * this function implements ST instruction when there is a possibility to write
326 * into a CPU register
328 void helper_fullwr(CPUAVRState
*env
, uint32_t data
, uint32_t addr
)
330 env
->fullacc
= false;
332 /* Following logic assumes this: */
333 assert(OFFSET_CPU_REGISTERS
== OFFSET_DATA
);
334 assert(OFFSET_IO_REGISTERS
== OFFSET_CPU_REGISTERS
+
335 NUMBER_OF_CPU_REGISTERS
);
337 if (addr
< NUMBER_OF_CPU_REGISTERS
) {
340 } else if (addr
< NUMBER_OF_CPU_REGISTERS
+ NUMBER_OF_IO_REGISTERS
) {
342 helper_outb(env
, addr
- NUMBER_OF_CPU_REGISTERS
, data
);
345 address_space_stb(&address_space_memory
, OFFSET_DATA
+ addr
, data
,
346 MEMTXATTRS_UNSPECIFIED
, NULL
);