4 * Copyright (c) 2019-2020 Michael Rolnik
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
22 #include "qemu/qemu-print.h"
25 #include "exec/exec-all.h"
26 #include "tcg/tcg-op.h"
27 #include "exec/cpu_ldst.h"
28 #include "exec/helper-proto.h"
29 #include "exec/helper-gen.h"
31 #include "exec/translator.h"
32 #include "exec/gen-icount.h"
35 * Define if you want a BREAK instruction translated to a breakpoint
36 * Active debugging connection is assumed
38 * https://github.com/seharris/qemu-avr-tests/tree/master/instruction-tests
41 #undef BREAKPOINT_ON_BREAK
54 static TCGv cpu_rampD
;
55 static TCGv cpu_rampX
;
56 static TCGv cpu_rampY
;
57 static TCGv cpu_rampZ
;
59 static TCGv cpu_r
[NUMBER_OF_CPU_REGISTERS
];
65 static const char reg_names
[NUMBER_OF_CPU_REGISTERS
][8] = {
66 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
67 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
68 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
69 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
71 #define REG(x) (cpu_r[x])
74 DISAS_EXIT
= DISAS_TARGET_0
, /* We want return to the cpu main loop. */
75 DISAS_LOOKUP
= DISAS_TARGET_1
, /* We have a variable condition exit. */
76 DISAS_CHAIN
= DISAS_TARGET_2
, /* We have a single condition exit. */
79 typedef struct DisasContext DisasContext
;
81 /* This is the state at translation time. */
91 /* Routine used to access memory */
97 * some AVR instructions can make the following instruction to be skipped
98 * Let's name those instructions
99 * A - instruction that can skip the next one
100 * B - instruction that can be skipped. this depends on execution of A
101 * there are two scenarios
102 * 1. A and B belong to the same translation block
103 * 2. A is the last instruction in the translation block and B is the last
105 * following variables are used to simplify the skipping logic, they are
106 * used in the following manner (sketch)
108 * TCGLabel *skip_label = NULL;
109 * if (ctx.skip_cond != TCG_COND_NEVER) {
110 * skip_label = gen_new_label();
111 * tcg_gen_brcond_tl(skip_cond, skip_var0, skip_var1, skip_label);
114 * if (free_skip_var0) {
115 * tcg_temp_free(skip_var0);
116 * free_skip_var0 = false;
122 * gen_set_label(skip_label);
131 static int to_regs_16_31_by_one(DisasContext
*ctx
, int indx
)
133 return 16 + (indx
% 16);
136 static int to_regs_16_23_by_one(DisasContext
*ctx
, int indx
)
138 return 16 + (indx
% 8);
141 static int to_regs_24_30_by_two(DisasContext
*ctx
, int indx
)
143 return 24 + (indx
% 4) * 2;
146 static int to_regs_00_30_by_two(DisasContext
*ctx
, int indx
)
148 return (indx
% 16) * 2;
151 static uint16_t next_word(DisasContext
*ctx
)
153 return cpu_lduw_code(ctx
->env
, ctx
->npc
++ * 2);
156 static int append_16(DisasContext
*ctx
, int x
)
158 return x
<< 16 | next_word(ctx
);
161 static bool avr_have_feature(DisasContext
*ctx
, int feature
)
163 if (!avr_feature(ctx
->env
, feature
)) {
164 gen_helper_unsupported(cpu_env
);
165 ctx
->bstate
= DISAS_NORETURN
;
171 static bool decode_insn(DisasContext
*ctx
, uint16_t insn
);
172 #include "decode_insn.inc.c"
175 * Arithmetic Instructions
179 * Utility functions for updating status registers:
190 static void gen_add_CHf(TCGv R
, TCGv Rd
, TCGv Rr
)
192 TCGv t1
= tcg_temp_new_i32();
193 TCGv t2
= tcg_temp_new_i32();
194 TCGv t3
= tcg_temp_new_i32();
196 tcg_gen_and_tl(t1
, Rd
, Rr
); /* t1 = Rd & Rr */
197 tcg_gen_andc_tl(t2
, Rd
, R
); /* t2 = Rd & ~R */
198 tcg_gen_andc_tl(t3
, Rr
, R
); /* t3 = Rr & ~R */
199 tcg_gen_or_tl(t1
, t1
, t2
); /* t1 = t1 | t2 | t3 */
200 tcg_gen_or_tl(t1
, t1
, t3
);
202 tcg_gen_shri_tl(cpu_Cf
, t1
, 7); /* Cf = t1(7) */
203 tcg_gen_shri_tl(cpu_Hf
, t1
, 3); /* Hf = t1(3) */
204 tcg_gen_andi_tl(cpu_Hf
, cpu_Hf
, 1);
206 tcg_temp_free_i32(t3
);
207 tcg_temp_free_i32(t2
);
208 tcg_temp_free_i32(t1
);
211 static void gen_add_Vf(TCGv R
, TCGv Rd
, TCGv Rr
)
213 TCGv t1
= tcg_temp_new_i32();
214 TCGv t2
= tcg_temp_new_i32();
216 /* t1 = Rd & Rr & ~R | ~Rd & ~Rr & R */
217 /* = (Rd ^ R) & ~(Rd ^ Rr) */
218 tcg_gen_xor_tl(t1
, Rd
, R
);
219 tcg_gen_xor_tl(t2
, Rd
, Rr
);
220 tcg_gen_andc_tl(t1
, t1
, t2
);
222 tcg_gen_shri_tl(cpu_Vf
, t1
, 7); /* Vf = t1(7) */
224 tcg_temp_free_i32(t2
);
225 tcg_temp_free_i32(t1
);
228 static void gen_sub_CHf(TCGv R
, TCGv Rd
, TCGv Rr
)
230 TCGv t1
= tcg_temp_new_i32();
231 TCGv t2
= tcg_temp_new_i32();
232 TCGv t3
= tcg_temp_new_i32();
234 tcg_gen_not_tl(t1
, Rd
); /* t1 = ~Rd */
235 tcg_gen_and_tl(t2
, t1
, Rr
); /* t2 = ~Rd & Rr */
236 tcg_gen_or_tl(t3
, t1
, Rr
); /* t3 = (~Rd | Rr) & R */
237 tcg_gen_and_tl(t3
, t3
, R
);
238 tcg_gen_or_tl(t2
, t2
, t3
); /* t2 = ~Rd & Rr | ~Rd & R | R & Rr */
240 tcg_gen_shri_tl(cpu_Cf
, t2
, 7); /* Cf = t2(7) */
241 tcg_gen_shri_tl(cpu_Hf
, t2
, 3); /* Hf = t2(3) */
242 tcg_gen_andi_tl(cpu_Hf
, cpu_Hf
, 1);
244 tcg_temp_free_i32(t3
);
245 tcg_temp_free_i32(t2
);
246 tcg_temp_free_i32(t1
);
249 static void gen_sub_Vf(TCGv R
, TCGv Rd
, TCGv Rr
)
251 TCGv t1
= tcg_temp_new_i32();
252 TCGv t2
= tcg_temp_new_i32();
254 /* t1 = Rd & ~Rr & ~R | ~Rd & Rr & R */
255 /* = (Rd ^ R) & (Rd ^ R) */
256 tcg_gen_xor_tl(t1
, Rd
, R
);
257 tcg_gen_xor_tl(t2
, Rd
, Rr
);
258 tcg_gen_and_tl(t1
, t1
, t2
);
260 tcg_gen_shri_tl(cpu_Vf
, t1
, 7); /* Vf = t1(7) */
262 tcg_temp_free_i32(t2
);
263 tcg_temp_free_i32(t1
);
266 static void gen_NSf(TCGv R
)
268 tcg_gen_shri_tl(cpu_Nf
, R
, 7); /* Nf = R(7) */
269 tcg_gen_xor_tl(cpu_Sf
, cpu_Nf
, cpu_Vf
); /* Sf = Nf ^ Vf */
272 static void gen_ZNSf(TCGv R
)
274 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
276 /* update status register */
277 tcg_gen_shri_tl(cpu_Nf
, R
, 7); /* Nf = R(7) */
278 tcg_gen_xor_tl(cpu_Sf
, cpu_Nf
, cpu_Vf
); /* Sf = Nf ^ Vf */
282 * Adds two registers without the C Flag and places the result in the
283 * destination register Rd.
285 static bool trans_ADD(DisasContext
*ctx
, arg_ADD
*a
)
287 TCGv Rd
= cpu_r
[a
->rd
];
288 TCGv Rr
= cpu_r
[a
->rr
];
289 TCGv R
= tcg_temp_new_i32();
291 tcg_gen_add_tl(R
, Rd
, Rr
); /* Rd = Rd + Rr */
292 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
294 /* update status register */
295 gen_add_CHf(R
, Rd
, Rr
);
296 gen_add_Vf(R
, Rd
, Rr
);
299 /* update output registers */
300 tcg_gen_mov_tl(Rd
, R
);
302 tcg_temp_free_i32(R
);
308 * Adds two registers and the contents of the C Flag and places the result in
309 * the destination register Rd.
311 static bool trans_ADC(DisasContext
*ctx
, arg_ADC
*a
)
313 TCGv Rd
= cpu_r
[a
->rd
];
314 TCGv Rr
= cpu_r
[a
->rr
];
315 TCGv R
= tcg_temp_new_i32();
317 tcg_gen_add_tl(R
, Rd
, Rr
); /* R = Rd + Rr + Cf */
318 tcg_gen_add_tl(R
, R
, cpu_Cf
);
319 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
321 /* update status register */
322 gen_add_CHf(R
, Rd
, Rr
);
323 gen_add_Vf(R
, Rd
, Rr
);
326 /* update output registers */
327 tcg_gen_mov_tl(Rd
, R
);
329 tcg_temp_free_i32(R
);
335 * Adds an immediate value (0 - 63) to a register pair and places the result
336 * in the register pair. This instruction operates on the upper four register
337 * pairs, and is well suited for operations on the pointer registers. This
338 * instruction is not available in all devices. Refer to the device specific
339 * instruction set summary.
341 static bool trans_ADIW(DisasContext
*ctx
, arg_ADIW
*a
)
343 if (!avr_have_feature(ctx
, AVR_FEATURE_ADIW_SBIW
)) {
347 TCGv RdL
= cpu_r
[a
->rd
];
348 TCGv RdH
= cpu_r
[a
->rd
+ 1];
350 TCGv R
= tcg_temp_new_i32();
351 TCGv Rd
= tcg_temp_new_i32();
353 tcg_gen_deposit_tl(Rd
, RdL
, RdH
, 8, 8); /* Rd = RdH:RdL */
354 tcg_gen_addi_tl(R
, Rd
, Imm
); /* R = Rd + Imm */
355 tcg_gen_andi_tl(R
, R
, 0xffff); /* make it 16 bits */
357 /* update status register */
358 tcg_gen_andc_tl(cpu_Cf
, Rd
, R
); /* Cf = Rd & ~R */
359 tcg_gen_shri_tl(cpu_Cf
, cpu_Cf
, 15);
360 tcg_gen_andc_tl(cpu_Vf
, R
, Rd
); /* Vf = R & ~Rd */
361 tcg_gen_shri_tl(cpu_Vf
, cpu_Vf
, 15);
362 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
363 tcg_gen_shri_tl(cpu_Nf
, R
, 15); /* Nf = R(15) */
364 tcg_gen_xor_tl(cpu_Sf
, cpu_Nf
, cpu_Vf
);/* Sf = Nf ^ Vf */
366 /* update output registers */
367 tcg_gen_andi_tl(RdL
, R
, 0xff);
368 tcg_gen_shri_tl(RdH
, R
, 8);
370 tcg_temp_free_i32(Rd
);
371 tcg_temp_free_i32(R
);
377 * Subtracts two registers and places the result in the destination
380 static bool trans_SUB(DisasContext
*ctx
, arg_SUB
*a
)
382 TCGv Rd
= cpu_r
[a
->rd
];
383 TCGv Rr
= cpu_r
[a
->rr
];
384 TCGv R
= tcg_temp_new_i32();
386 tcg_gen_sub_tl(R
, Rd
, Rr
); /* R = Rd - Rr */
387 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
389 /* update status register */
390 tcg_gen_andc_tl(cpu_Cf
, Rd
, R
); /* Cf = Rd & ~R */
391 gen_sub_CHf(R
, Rd
, Rr
);
392 gen_sub_Vf(R
, Rd
, Rr
);
395 /* update output registers */
396 tcg_gen_mov_tl(Rd
, R
);
398 tcg_temp_free_i32(R
);
404 * Subtracts a register and a constant and places the result in the
405 * destination register Rd. This instruction is working on Register R16 to R31
406 * and is very well suited for operations on the X, Y, and Z-pointers.
408 static bool trans_SUBI(DisasContext
*ctx
, arg_SUBI
*a
)
410 TCGv Rd
= cpu_r
[a
->rd
];
411 TCGv Rr
= tcg_const_i32(a
->imm
);
412 TCGv R
= tcg_temp_new_i32();
414 tcg_gen_sub_tl(R
, Rd
, Rr
); /* R = Rd - Imm */
415 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
417 /* update status register */
418 gen_sub_CHf(R
, Rd
, Rr
);
419 gen_sub_Vf(R
, Rd
, Rr
);
422 /* update output registers */
423 tcg_gen_mov_tl(Rd
, R
);
425 tcg_temp_free_i32(R
);
426 tcg_temp_free_i32(Rr
);
432 * Subtracts two registers and subtracts with the C Flag and places the
433 * result in the destination register Rd.
435 static bool trans_SBC(DisasContext
*ctx
, arg_SBC
*a
)
437 TCGv Rd
= cpu_r
[a
->rd
];
438 TCGv Rr
= cpu_r
[a
->rr
];
439 TCGv R
= tcg_temp_new_i32();
440 TCGv zero
= tcg_const_i32(0);
442 tcg_gen_sub_tl(R
, Rd
, Rr
); /* R = Rd - Rr - Cf */
443 tcg_gen_sub_tl(R
, R
, cpu_Cf
);
444 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
446 /* update status register */
447 gen_sub_CHf(R
, Rd
, Rr
);
448 gen_sub_Vf(R
, Rd
, Rr
);
452 * Previous value remains unchanged when the result is zero;
455 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_Zf
, R
, zero
, cpu_Zf
, zero
);
457 /* update output registers */
458 tcg_gen_mov_tl(Rd
, R
);
460 tcg_temp_free_i32(zero
);
461 tcg_temp_free_i32(R
);
467 * SBCI -- Subtract Immediate with Carry
469 static bool trans_SBCI(DisasContext
*ctx
, arg_SBCI
*a
)
471 TCGv Rd
= cpu_r
[a
->rd
];
472 TCGv Rr
= tcg_const_i32(a
->imm
);
473 TCGv R
= tcg_temp_new_i32();
474 TCGv zero
= tcg_const_i32(0);
476 tcg_gen_sub_tl(R
, Rd
, Rr
); /* R = Rd - Rr - Cf */
477 tcg_gen_sub_tl(R
, R
, cpu_Cf
);
478 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
480 /* update status register */
481 gen_sub_CHf(R
, Rd
, Rr
);
482 gen_sub_Vf(R
, Rd
, Rr
);
486 * Previous value remains unchanged when the result is zero;
489 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_Zf
, R
, zero
, cpu_Zf
, zero
);
491 /* update output registers */
492 tcg_gen_mov_tl(Rd
, R
);
494 tcg_temp_free_i32(zero
);
495 tcg_temp_free_i32(R
);
496 tcg_temp_free_i32(Rr
);
502 * Subtracts an immediate value (0-63) from a register pair and places the
503 * result in the register pair. This instruction operates on the upper four
504 * register pairs, and is well suited for operations on the Pointer Registers.
505 * This instruction is not available in all devices. Refer to the device
506 * specific instruction set summary.
508 static bool trans_SBIW(DisasContext
*ctx
, arg_SBIW
*a
)
510 if (!avr_have_feature(ctx
, AVR_FEATURE_ADIW_SBIW
)) {
514 TCGv RdL
= cpu_r
[a
->rd
];
515 TCGv RdH
= cpu_r
[a
->rd
+ 1];
517 TCGv R
= tcg_temp_new_i32();
518 TCGv Rd
= tcg_temp_new_i32();
520 tcg_gen_deposit_tl(Rd
, RdL
, RdH
, 8, 8); /* Rd = RdH:RdL */
521 tcg_gen_subi_tl(R
, Rd
, Imm
); /* R = Rd - Imm */
522 tcg_gen_andi_tl(R
, R
, 0xffff); /* make it 16 bits */
524 /* update status register */
525 tcg_gen_andc_tl(cpu_Cf
, R
, Rd
);
526 tcg_gen_shri_tl(cpu_Cf
, cpu_Cf
, 15); /* Cf = R & ~Rd */
527 tcg_gen_andc_tl(cpu_Vf
, Rd
, R
);
528 tcg_gen_shri_tl(cpu_Vf
, cpu_Vf
, 15); /* Vf = Rd & ~R */
529 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
530 tcg_gen_shri_tl(cpu_Nf
, R
, 15); /* Nf = R(15) */
531 tcg_gen_xor_tl(cpu_Sf
, cpu_Nf
, cpu_Vf
); /* Sf = Nf ^ Vf */
533 /* update output registers */
534 tcg_gen_andi_tl(RdL
, R
, 0xff);
535 tcg_gen_shri_tl(RdH
, R
, 8);
537 tcg_temp_free_i32(Rd
);
538 tcg_temp_free_i32(R
);
544 * Performs the logical AND between the contents of register Rd and register
545 * Rr and places the result in the destination register Rd.
547 static bool trans_AND(DisasContext
*ctx
, arg_AND
*a
)
549 TCGv Rd
= cpu_r
[a
->rd
];
550 TCGv Rr
= cpu_r
[a
->rr
];
551 TCGv R
= tcg_temp_new_i32();
553 tcg_gen_and_tl(R
, Rd
, Rr
); /* Rd = Rd and Rr */
555 /* update status register */
556 tcg_gen_movi_tl(cpu_Vf
, 0); /* Vf = 0 */
557 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
560 /* update output registers */
561 tcg_gen_mov_tl(Rd
, R
);
563 tcg_temp_free_i32(R
);
569 * Performs the logical AND between the contents of register Rd and a constant
570 * and places the result in the destination register Rd.
572 static bool trans_ANDI(DisasContext
*ctx
, arg_ANDI
*a
)
574 TCGv Rd
= cpu_r
[a
->rd
];
577 tcg_gen_andi_tl(Rd
, Rd
, Imm
); /* Rd = Rd & Imm */
579 /* update status register */
580 tcg_gen_movi_tl(cpu_Vf
, 0x00); /* Vf = 0 */
587 * Performs the logical OR between the contents of register Rd and register
588 * Rr and places the result in the destination register Rd.
590 static bool trans_OR(DisasContext
*ctx
, arg_OR
*a
)
592 TCGv Rd
= cpu_r
[a
->rd
];
593 TCGv Rr
= cpu_r
[a
->rr
];
594 TCGv R
= tcg_temp_new_i32();
596 tcg_gen_or_tl(R
, Rd
, Rr
);
598 /* update status register */
599 tcg_gen_movi_tl(cpu_Vf
, 0);
602 /* update output registers */
603 tcg_gen_mov_tl(Rd
, R
);
605 tcg_temp_free_i32(R
);
611 * Performs the logical OR between the contents of register Rd and a
612 * constant and places the result in the destination register Rd.
614 static bool trans_ORI(DisasContext
*ctx
, arg_ORI
*a
)
616 TCGv Rd
= cpu_r
[a
->rd
];
619 tcg_gen_ori_tl(Rd
, Rd
, Imm
); /* Rd = Rd | Imm */
621 /* update status register */
622 tcg_gen_movi_tl(cpu_Vf
, 0x00); /* Vf = 0 */
629 * Performs the logical EOR between the contents of register Rd and
630 * register Rr and places the result in the destination register Rd.
632 static bool trans_EOR(DisasContext
*ctx
, arg_EOR
*a
)
634 TCGv Rd
= cpu_r
[a
->rd
];
635 TCGv Rr
= cpu_r
[a
->rr
];
637 tcg_gen_xor_tl(Rd
, Rd
, Rr
);
639 /* update status register */
640 tcg_gen_movi_tl(cpu_Vf
, 0);
647 * Clears the specified bits in register Rd. Performs the logical AND
648 * between the contents of register Rd and the complement of the constant mask
649 * K. The result will be placed in register Rd.
651 static bool trans_COM(DisasContext
*ctx
, arg_COM
*a
)
653 TCGv Rd
= cpu_r
[a
->rd
];
654 TCGv R
= tcg_temp_new_i32();
656 tcg_gen_xori_tl(Rd
, Rd
, 0xff);
658 /* update status register */
659 tcg_gen_movi_tl(cpu_Cf
, 1); /* Cf = 1 */
660 tcg_gen_movi_tl(cpu_Vf
, 0); /* Vf = 0 */
663 tcg_temp_free_i32(R
);
669 * Replaces the contents of register Rd with its two's complement; the
670 * value $80 is left unchanged.
672 static bool trans_NEG(DisasContext
*ctx
, arg_NEG
*a
)
674 TCGv Rd
= cpu_r
[a
->rd
];
675 TCGv t0
= tcg_const_i32(0);
676 TCGv R
= tcg_temp_new_i32();
678 tcg_gen_sub_tl(R
, t0
, Rd
); /* R = 0 - Rd */
679 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
681 /* update status register */
682 gen_sub_CHf(R
, t0
, Rd
);
683 gen_sub_Vf(R
, t0
, Rd
);
686 /* update output registers */
687 tcg_gen_mov_tl(Rd
, R
);
689 tcg_temp_free_i32(t0
);
690 tcg_temp_free_i32(R
);
696 * Adds one -1- to the contents of register Rd and places the result in the
697 * destination register Rd. The C Flag in SREG is not affected by the
698 * operation, thus allowing the INC instruction to be used on a loop counter in
699 * multiple-precision computations. When operating on unsigned numbers, only
700 * BREQ and BRNE branches can be expected to perform consistently. When
701 * operating on two's complement values, all signed branches are available.
703 static bool trans_INC(DisasContext
*ctx
, arg_INC
*a
)
705 TCGv Rd
= cpu_r
[a
->rd
];
707 tcg_gen_addi_tl(Rd
, Rd
, 1);
708 tcg_gen_andi_tl(Rd
, Rd
, 0xff);
710 /* update status register */
711 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Vf
, Rd
, 0x80); /* Vf = Rd == 0x80 */
718 * Subtracts one -1- from the contents of register Rd and places the result
719 * in the destination register Rd. The C Flag in SREG is not affected by the
720 * operation, thus allowing the DEC instruction to be used on a loop counter in
721 * multiple-precision computations. When operating on unsigned values, only
722 * BREQ and BRNE branches can be expected to perform consistently. When
723 * operating on two's complement values, all signed branches are available.
725 static bool trans_DEC(DisasContext
*ctx
, arg_DEC
*a
)
727 TCGv Rd
= cpu_r
[a
->rd
];
729 tcg_gen_subi_tl(Rd
, Rd
, 1); /* Rd = Rd - 1 */
730 tcg_gen_andi_tl(Rd
, Rd
, 0xff); /* make it 8 bits */
732 /* update status register */
733 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Vf
, Rd
, 0x7f); /* Vf = Rd == 0x7f */
740 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned multiplication.
742 static bool trans_MUL(DisasContext
*ctx
, arg_MUL
*a
)
744 if (!avr_have_feature(ctx
, AVR_FEATURE_MUL
)) {
750 TCGv Rd
= cpu_r
[a
->rd
];
751 TCGv Rr
= cpu_r
[a
->rr
];
752 TCGv R
= tcg_temp_new_i32();
754 tcg_gen_mul_tl(R
, Rd
, Rr
); /* R = Rd * Rr */
755 tcg_gen_andi_tl(R0
, R
, 0xff);
756 tcg_gen_shri_tl(R1
, R
, 8);
758 /* update status register */
759 tcg_gen_shri_tl(cpu_Cf
, R
, 15); /* Cf = R(15) */
760 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
762 tcg_temp_free_i32(R
);
768 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication.
770 static bool trans_MULS(DisasContext
*ctx
, arg_MULS
*a
)
772 if (!avr_have_feature(ctx
, AVR_FEATURE_MUL
)) {
778 TCGv Rd
= cpu_r
[a
->rd
];
779 TCGv Rr
= cpu_r
[a
->rr
];
780 TCGv R
= tcg_temp_new_i32();
781 TCGv t0
= tcg_temp_new_i32();
782 TCGv t1
= tcg_temp_new_i32();
784 tcg_gen_ext8s_tl(t0
, Rd
); /* make Rd full 32 bit signed */
785 tcg_gen_ext8s_tl(t1
, Rr
); /* make Rr full 32 bit signed */
786 tcg_gen_mul_tl(R
, t0
, t1
); /* R = Rd * Rr */
787 tcg_gen_andi_tl(R
, R
, 0xffff); /* make it 16 bits */
788 tcg_gen_andi_tl(R0
, R
, 0xff);
789 tcg_gen_shri_tl(R1
, R
, 8);
791 /* update status register */
792 tcg_gen_shri_tl(cpu_Cf
, R
, 15); /* Cf = R(15) */
793 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
795 tcg_temp_free_i32(t1
);
796 tcg_temp_free_i32(t0
);
797 tcg_temp_free_i32(R
);
803 * This instruction performs 8-bit x 8-bit -> 16-bit multiplication of a
804 * signed and an unsigned number.
806 static bool trans_MULSU(DisasContext
*ctx
, arg_MULSU
*a
)
808 if (!avr_have_feature(ctx
, AVR_FEATURE_MUL
)) {
814 TCGv Rd
= cpu_r
[a
->rd
];
815 TCGv Rr
= cpu_r
[a
->rr
];
816 TCGv R
= tcg_temp_new_i32();
817 TCGv t0
= tcg_temp_new_i32();
819 tcg_gen_ext8s_tl(t0
, Rd
); /* make Rd full 32 bit signed */
820 tcg_gen_mul_tl(R
, t0
, Rr
); /* R = Rd * Rr */
821 tcg_gen_andi_tl(R
, R
, 0xffff); /* make R 16 bits */
822 tcg_gen_andi_tl(R0
, R
, 0xff);
823 tcg_gen_shri_tl(R1
, R
, 8);
825 /* update status register */
826 tcg_gen_shri_tl(cpu_Cf
, R
, 15); /* Cf = R(15) */
827 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
829 tcg_temp_free_i32(t0
);
830 tcg_temp_free_i32(R
);
836 * This instruction performs 8-bit x 8-bit -> 16-bit unsigned
837 * multiplication and shifts the result one bit left.
839 static bool trans_FMUL(DisasContext
*ctx
, arg_FMUL
*a
)
841 if (!avr_have_feature(ctx
, AVR_FEATURE_MUL
)) {
847 TCGv Rd
= cpu_r
[a
->rd
];
848 TCGv Rr
= cpu_r
[a
->rr
];
849 TCGv R
= tcg_temp_new_i32();
851 tcg_gen_mul_tl(R
, Rd
, Rr
); /* R = Rd * Rr */
853 /* update status register */
854 tcg_gen_shri_tl(cpu_Cf
, R
, 15); /* Cf = R(15) */
855 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
857 /* update output registers */
858 tcg_gen_shli_tl(R
, R
, 1);
859 tcg_gen_andi_tl(R0
, R
, 0xff);
860 tcg_gen_shri_tl(R1
, R
, 8);
861 tcg_gen_andi_tl(R1
, R1
, 0xff);
864 tcg_temp_free_i32(R
);
870 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
871 * and shifts the result one bit left.
873 static bool trans_FMULS(DisasContext
*ctx
, arg_FMULS
*a
)
875 if (!avr_have_feature(ctx
, AVR_FEATURE_MUL
)) {
881 TCGv Rd
= cpu_r
[a
->rd
];
882 TCGv Rr
= cpu_r
[a
->rr
];
883 TCGv R
= tcg_temp_new_i32();
884 TCGv t0
= tcg_temp_new_i32();
885 TCGv t1
= tcg_temp_new_i32();
887 tcg_gen_ext8s_tl(t0
, Rd
); /* make Rd full 32 bit signed */
888 tcg_gen_ext8s_tl(t1
, Rr
); /* make Rr full 32 bit signed */
889 tcg_gen_mul_tl(R
, t0
, t1
); /* R = Rd * Rr */
890 tcg_gen_andi_tl(R
, R
, 0xffff); /* make it 16 bits */
892 /* update status register */
893 tcg_gen_shri_tl(cpu_Cf
, R
, 15); /* Cf = R(15) */
894 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
896 /* update output registers */
897 tcg_gen_shli_tl(R
, R
, 1);
898 tcg_gen_andi_tl(R0
, R
, 0xff);
899 tcg_gen_shri_tl(R1
, R
, 8);
900 tcg_gen_andi_tl(R1
, R1
, 0xff);
902 tcg_temp_free_i32(t1
);
903 tcg_temp_free_i32(t0
);
904 tcg_temp_free_i32(R
);
910 * This instruction performs 8-bit x 8-bit -> 16-bit signed multiplication
911 * and shifts the result one bit left.
913 static bool trans_FMULSU(DisasContext
*ctx
, arg_FMULSU
*a
)
915 if (!avr_have_feature(ctx
, AVR_FEATURE_MUL
)) {
921 TCGv Rd
= cpu_r
[a
->rd
];
922 TCGv Rr
= cpu_r
[a
->rr
];
923 TCGv R
= tcg_temp_new_i32();
924 TCGv t0
= tcg_temp_new_i32();
926 tcg_gen_ext8s_tl(t0
, Rd
); /* make Rd full 32 bit signed */
927 tcg_gen_mul_tl(R
, t0
, Rr
); /* R = Rd * Rr */
928 tcg_gen_andi_tl(R
, R
, 0xffff); /* make it 16 bits */
930 /* update status register */
931 tcg_gen_shri_tl(cpu_Cf
, R
, 15); /* Cf = R(15) */
932 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
934 /* update output registers */
935 tcg_gen_shli_tl(R
, R
, 1);
936 tcg_gen_andi_tl(R0
, R
, 0xff);
937 tcg_gen_shri_tl(R1
, R
, 8);
938 tcg_gen_andi_tl(R1
, R1
, 0xff);
940 tcg_temp_free_i32(t0
);
941 tcg_temp_free_i32(R
);
947 * The module is an instruction set extension to the AVR CPU, performing
948 * DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in
949 * the CPU register file, registers R0-R7, where LSB of data is placed in LSB
950 * of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including
951 * parity bits) is placed in registers R8- R15, organized in the register file
952 * with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES
953 * instruction performs one round in the DES algorithm. Sixteen rounds must be
954 * executed in increasing order to form the correct DES ciphertext or
955 * plaintext. Intermediate results are stored in the register file (R0-R15)
956 * after each DES instruction. The instruction's operand (K) determines which
957 * round is executed, and the half carry flag (H) determines whether encryption
958 * or decryption is performed. The DES algorithm is described in
959 * "Specifications for the Data Encryption Standard" (Federal Information
960 * Processing Standards Publication 46). Intermediate results in this
961 * implementation differ from the standard because the initial permutation and
962 * the inverse initial permutation are performed each iteration. This does not
963 * affect the result in the final ciphertext or plaintext, but reduces
966 static bool trans_DES(DisasContext
*ctx
, arg_DES
*a
)
969 if (!avr_have_feature(ctx
, AVR_FEATURE_DES
)) {
973 qemu_log_mask(LOG_UNIMP
, "%s: not implemented\n", __func__
);
979 * Branch Instructions
981 static void gen_jmp_ez(DisasContext
*ctx
)
983 tcg_gen_deposit_tl(cpu_pc
, cpu_r
[30], cpu_r
[31], 8, 8);
984 tcg_gen_or_tl(cpu_pc
, cpu_pc
, cpu_eind
);
985 ctx
->bstate
= DISAS_LOOKUP
;
988 static void gen_jmp_z(DisasContext
*ctx
)
990 tcg_gen_deposit_tl(cpu_pc
, cpu_r
[30], cpu_r
[31], 8, 8);
991 ctx
->bstate
= DISAS_LOOKUP
;
994 static void gen_push_ret(DisasContext
*ctx
, int ret
)
996 if (avr_feature(ctx
->env
, AVR_FEATURE_1_BYTE_PC
)) {
998 TCGv t0
= tcg_const_i32((ret
& 0x0000ff));
1000 tcg_gen_qemu_st_tl(t0
, cpu_sp
, MMU_DATA_IDX
, MO_UB
);
1001 tcg_gen_subi_tl(cpu_sp
, cpu_sp
, 1);
1003 tcg_temp_free_i32(t0
);
1004 } else if (avr_feature(ctx
->env
, AVR_FEATURE_2_BYTE_PC
)) {
1006 TCGv t0
= tcg_const_i32((ret
& 0x00ffff));
1008 tcg_gen_subi_tl(cpu_sp
, cpu_sp
, 1);
1009 tcg_gen_qemu_st_tl(t0
, cpu_sp
, MMU_DATA_IDX
, MO_BEUW
);
1010 tcg_gen_subi_tl(cpu_sp
, cpu_sp
, 1);
1012 tcg_temp_free_i32(t0
);
1014 } else if (avr_feature(ctx
->env
, AVR_FEATURE_3_BYTE_PC
)) {
1016 TCGv lo
= tcg_const_i32((ret
& 0x0000ff));
1017 TCGv hi
= tcg_const_i32((ret
& 0xffff00) >> 8);
1019 tcg_gen_qemu_st_tl(lo
, cpu_sp
, MMU_DATA_IDX
, MO_UB
);
1020 tcg_gen_subi_tl(cpu_sp
, cpu_sp
, 2);
1021 tcg_gen_qemu_st_tl(hi
, cpu_sp
, MMU_DATA_IDX
, MO_BEUW
);
1022 tcg_gen_subi_tl(cpu_sp
, cpu_sp
, 1);
1024 tcg_temp_free_i32(lo
);
1025 tcg_temp_free_i32(hi
);
1029 static void gen_pop_ret(DisasContext
*ctx
, TCGv ret
)
1031 if (avr_feature(ctx
->env
, AVR_FEATURE_1_BYTE_PC
)) {
1032 tcg_gen_addi_tl(cpu_sp
, cpu_sp
, 1);
1033 tcg_gen_qemu_ld_tl(ret
, cpu_sp
, MMU_DATA_IDX
, MO_UB
);
1034 } else if (avr_feature(ctx
->env
, AVR_FEATURE_2_BYTE_PC
)) {
1035 tcg_gen_addi_tl(cpu_sp
, cpu_sp
, 1);
1036 tcg_gen_qemu_ld_tl(ret
, cpu_sp
, MMU_DATA_IDX
, MO_BEUW
);
1037 tcg_gen_addi_tl(cpu_sp
, cpu_sp
, 1);
1038 } else if (avr_feature(ctx
->env
, AVR_FEATURE_3_BYTE_PC
)) {
1039 TCGv lo
= tcg_temp_new_i32();
1040 TCGv hi
= tcg_temp_new_i32();
1042 tcg_gen_addi_tl(cpu_sp
, cpu_sp
, 1);
1043 tcg_gen_qemu_ld_tl(hi
, cpu_sp
, MMU_DATA_IDX
, MO_BEUW
);
1045 tcg_gen_addi_tl(cpu_sp
, cpu_sp
, 2);
1046 tcg_gen_qemu_ld_tl(lo
, cpu_sp
, MMU_DATA_IDX
, MO_UB
);
1048 tcg_gen_deposit_tl(ret
, lo
, hi
, 8, 16);
1050 tcg_temp_free_i32(lo
);
1051 tcg_temp_free_i32(hi
);
1055 static void gen_goto_tb(DisasContext
*ctx
, int n
, target_ulong dest
)
1057 TranslationBlock
*tb
= ctx
->tb
;
1059 if (ctx
->singlestep
== 0) {
1061 tcg_gen_movi_i32(cpu_pc
, dest
);
1062 tcg_gen_exit_tb(tb
, n
);
1064 tcg_gen_movi_i32(cpu_pc
, dest
);
1065 gen_helper_debug(cpu_env
);
1066 tcg_gen_exit_tb(NULL
, 0);
1068 ctx
->bstate
= DISAS_NORETURN
;
1072 * Relative jump to an address within PC - 2K +1 and PC + 2K (words). For
1073 * AVR microcontrollers with Program memory not exceeding 4K words (8KB) this
1074 * instruction can address the entire memory from every address location. See
1077 static bool trans_RJMP(DisasContext
*ctx
, arg_RJMP
*a
)
1079 int dst
= ctx
->npc
+ a
->imm
;
1081 gen_goto_tb(ctx
, 0, dst
);
1087 * Indirect jump to the address pointed to by the Z (16 bits) Pointer
1088 * Register in the Register File. The Z-pointer Register is 16 bits wide and
1089 * allows jump within the lowest 64K words (128KB) section of Program memory.
1090 * This instruction is not available in all devices. Refer to the device
1091 * specific instruction set summary.
1093 static bool trans_IJMP(DisasContext
*ctx
, arg_IJMP
*a
)
1095 if (!avr_have_feature(ctx
, AVR_FEATURE_IJMP_ICALL
)) {
1105 * Indirect jump to the address pointed to by the Z (16 bits) Pointer
1106 * Register in the Register File and the EIND Register in the I/O space. This
1107 * instruction allows for indirect jumps to the entire 4M (words) Program
1108 * memory space. See also IJMP. This instruction is not available in all
1109 * devices. Refer to the device specific instruction set summary.
1111 static bool trans_EIJMP(DisasContext
*ctx
, arg_EIJMP
*a
)
1113 if (!avr_have_feature(ctx
, AVR_FEATURE_EIJMP_EICALL
)) {
1122 * Jump to an address within the entire 4M (words) Program memory. See also
1123 * RJMP. This instruction is not available in all devices. Refer to the device
1124 * specific instruction set summary.0
1126 static bool trans_JMP(DisasContext
*ctx
, arg_JMP
*a
)
1128 if (!avr_have_feature(ctx
, AVR_FEATURE_JMP_CALL
)) {
1132 gen_goto_tb(ctx
, 0, a
->imm
);
1138 * Relative call to an address within PC - 2K + 1 and PC + 2K (words). The
1139 * return address (the instruction after the RCALL) is stored onto the Stack.
1140 * See also CALL. For AVR microcontrollers with Program memory not exceeding 4K
1141 * words (8KB) this instruction can address the entire memory from every
1142 * address location. The Stack Pointer uses a post-decrement scheme during
1145 static bool trans_RCALL(DisasContext
*ctx
, arg_RCALL
*a
)
1148 int dst
= ctx
->npc
+ a
->imm
;
1150 gen_push_ret(ctx
, ret
);
1151 gen_goto_tb(ctx
, 0, dst
);
1157 * Calls to a subroutine within the entire 4M (words) Program memory. The
1158 * return address (to the instruction after the CALL) will be stored onto the
1159 * Stack. See also RCALL. The Stack Pointer uses a post-decrement scheme during
1160 * CALL. This instruction is not available in all devices. Refer to the device
1161 * specific instruction set summary.
1163 static bool trans_ICALL(DisasContext
*ctx
, arg_ICALL
*a
)
1165 if (!avr_have_feature(ctx
, AVR_FEATURE_IJMP_ICALL
)) {
1171 gen_push_ret(ctx
, ret
);
1178 * Indirect call of a subroutine pointed to by the Z (16 bits) Pointer
1179 * Register in the Register File and the EIND Register in the I/O space. This
1180 * instruction allows for indirect calls to the entire 4M (words) Program
1181 * memory space. See also ICALL. The Stack Pointer uses a post-decrement scheme
1182 * during EICALL. This instruction is not available in all devices. Refer to
1183 * the device specific instruction set summary.
1185 static bool trans_EICALL(DisasContext
*ctx
, arg_EICALL
*a
)
1187 if (!avr_have_feature(ctx
, AVR_FEATURE_EIJMP_EICALL
)) {
1193 gen_push_ret(ctx
, ret
);
1199 * Calls to a subroutine within the entire Program memory. The return
1200 * address (to the instruction after the CALL) will be stored onto the Stack.
1201 * (See also RCALL). The Stack Pointer uses a post-decrement scheme during
1202 * CALL. This instruction is not available in all devices. Refer to the device
1203 * specific instruction set summary.
1205 static bool trans_CALL(DisasContext
*ctx
, arg_CALL
*a
)
1207 if (!avr_have_feature(ctx
, AVR_FEATURE_JMP_CALL
)) {
1214 gen_push_ret(ctx
, ret
);
1215 gen_goto_tb(ctx
, 0, Imm
);
1221 * Returns from subroutine. The return address is loaded from the STACK.
1222 * The Stack Pointer uses a preincrement scheme during RET.
1224 static bool trans_RET(DisasContext
*ctx
, arg_RET
*a
)
1226 gen_pop_ret(ctx
, cpu_pc
);
1228 ctx
->bstate
= DISAS_LOOKUP
;
1233 * Returns from interrupt. The return address is loaded from the STACK and
1234 * the Global Interrupt Flag is set. Note that the Status Register is not
1235 * automatically stored when entering an interrupt routine, and it is not
1236 * restored when returning from an interrupt routine. This must be handled by
1237 * the application program. The Stack Pointer uses a pre-increment scheme
1240 static bool trans_RETI(DisasContext
*ctx
, arg_RETI
*a
)
1242 gen_pop_ret(ctx
, cpu_pc
);
1243 tcg_gen_movi_tl(cpu_If
, 1);
1245 /* Need to return to main loop to re-evaluate interrupts. */
1246 ctx
->bstate
= DISAS_EXIT
;
1251 * This instruction performs a compare between two registers Rd and Rr, and
1252 * skips the next instruction if Rd = Rr.
1254 static bool trans_CPSE(DisasContext
*ctx
, arg_CPSE
*a
)
1256 ctx
->skip_cond
= TCG_COND_EQ
;
1257 ctx
->skip_var0
= cpu_r
[a
->rd
];
1258 ctx
->skip_var1
= cpu_r
[a
->rr
];
1263 * This instruction performs a compare between two registers Rd and Rr.
1264 * None of the registers are changed. All conditional branches can be used
1265 * after this instruction.
1267 static bool trans_CP(DisasContext
*ctx
, arg_CP
*a
)
1269 TCGv Rd
= cpu_r
[a
->rd
];
1270 TCGv Rr
= cpu_r
[a
->rr
];
1271 TCGv R
= tcg_temp_new_i32();
1273 tcg_gen_sub_tl(R
, Rd
, Rr
); /* R = Rd - Rr */
1274 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
1276 /* update status register */
1277 gen_sub_CHf(R
, Rd
, Rr
);
1278 gen_sub_Vf(R
, Rd
, Rr
);
1281 tcg_temp_free_i32(R
);
1287 * This instruction performs a compare between two registers Rd and Rr and
1288 * also takes into account the previous carry. None of the registers are
1289 * changed. All conditional branches can be used after this instruction.
1291 static bool trans_CPC(DisasContext
*ctx
, arg_CPC
*a
)
1293 TCGv Rd
= cpu_r
[a
->rd
];
1294 TCGv Rr
= cpu_r
[a
->rr
];
1295 TCGv R
= tcg_temp_new_i32();
1296 TCGv zero
= tcg_const_i32(0);
1298 tcg_gen_sub_tl(R
, Rd
, Rr
); /* R = Rd - Rr - Cf */
1299 tcg_gen_sub_tl(R
, R
, cpu_Cf
);
1300 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
1301 /* update status register */
1302 gen_sub_CHf(R
, Rd
, Rr
);
1303 gen_sub_Vf(R
, Rd
, Rr
);
1307 * Previous value remains unchanged when the result is zero;
1308 * cleared otherwise.
1310 tcg_gen_movcond_tl(TCG_COND_EQ
, cpu_Zf
, R
, zero
, cpu_Zf
, zero
);
1312 tcg_temp_free_i32(zero
);
1313 tcg_temp_free_i32(R
);
1319 * This instruction performs a compare between register Rd and a constant.
1320 * The register is not changed. All conditional branches can be used after this
1323 static bool trans_CPI(DisasContext
*ctx
, arg_CPI
*a
)
1325 TCGv Rd
= cpu_r
[a
->rd
];
1327 TCGv Rr
= tcg_const_i32(Imm
);
1328 TCGv R
= tcg_temp_new_i32();
1330 tcg_gen_sub_tl(R
, Rd
, Rr
); /* R = Rd - Rr */
1331 tcg_gen_andi_tl(R
, R
, 0xff); /* make it 8 bits */
1333 /* update status register */
1334 gen_sub_CHf(R
, Rd
, Rr
);
1335 gen_sub_Vf(R
, Rd
, Rr
);
1338 tcg_temp_free_i32(R
);
1339 tcg_temp_free_i32(Rr
);
1345 * This instruction tests a single bit in a register and skips the next
1346 * instruction if the bit is cleared.
1348 static bool trans_SBRC(DisasContext
*ctx
, arg_SBRC
*a
)
1350 TCGv Rr
= cpu_r
[a
->rr
];
1352 ctx
->skip_cond
= TCG_COND_EQ
;
1353 ctx
->skip_var0
= tcg_temp_new();
1354 ctx
->free_skip_var0
= true;
1356 tcg_gen_andi_tl(ctx
->skip_var0
, Rr
, 1 << a
->bit
);
1361 * This instruction tests a single bit in a register and skips the next
1362 * instruction if the bit is set.
1364 static bool trans_SBRS(DisasContext
*ctx
, arg_SBRS
*a
)
1366 TCGv Rr
= cpu_r
[a
->rr
];
1368 ctx
->skip_cond
= TCG_COND_NE
;
1369 ctx
->skip_var0
= tcg_temp_new();
1370 ctx
->free_skip_var0
= true;
1372 tcg_gen_andi_tl(ctx
->skip_var0
, Rr
, 1 << a
->bit
);
1377 * This instruction tests a single bit in an I/O Register and skips the
1378 * next instruction if the bit is cleared. This instruction operates on the
1379 * lower 32 I/O Registers -- addresses 0-31.
1381 static bool trans_SBIC(DisasContext
*ctx
, arg_SBIC
*a
)
1383 TCGv temp
= tcg_const_i32(a
->reg
);
1385 gen_helper_inb(temp
, cpu_env
, temp
);
1386 tcg_gen_andi_tl(temp
, temp
, 1 << a
->bit
);
1387 ctx
->skip_cond
= TCG_COND_EQ
;
1388 ctx
->skip_var0
= temp
;
1389 ctx
->free_skip_var0
= true;
1395 * This instruction tests a single bit in an I/O Register and skips the
1396 * next instruction if the bit is set. This instruction operates on the lower
1397 * 32 I/O Registers -- addresses 0-31.
1399 static bool trans_SBIS(DisasContext
*ctx
, arg_SBIS
*a
)
1401 TCGv temp
= tcg_const_i32(a
->reg
);
1403 gen_helper_inb(temp
, cpu_env
, temp
);
1404 tcg_gen_andi_tl(temp
, temp
, 1 << a
->bit
);
1405 ctx
->skip_cond
= TCG_COND_NE
;
1406 ctx
->skip_var0
= temp
;
1407 ctx
->free_skip_var0
= true;
1413 * Conditional relative branch. Tests a single bit in SREG and branches
1414 * relatively to PC if the bit is cleared. This instruction branches relatively
1415 * to PC in either direction (PC - 63 < = destination <= PC + 64). The
1416 * parameter k is the offset from PC and is represented in two's complement
1419 static bool trans_BRBC(DisasContext
*ctx
, arg_BRBC
*a
)
1421 TCGLabel
*not_taken
= gen_new_label();
1451 g_assert_not_reached();
1454 tcg_gen_brcondi_i32(TCG_COND_NE
, var
, 0, not_taken
);
1455 gen_goto_tb(ctx
, 0, ctx
->npc
+ a
->imm
);
1456 gen_set_label(not_taken
);
1458 ctx
->bstate
= DISAS_CHAIN
;
1463 * Conditional relative branch. Tests a single bit in SREG and branches
1464 * relatively to PC if the bit is set. This instruction branches relatively to
1465 * PC in either direction (PC - 63 < = destination <= PC + 64). The parameter k
1466 * is the offset from PC and is represented in two's complement form.
1468 static bool trans_BRBS(DisasContext
*ctx
, arg_BRBS
*a
)
1470 TCGLabel
*not_taken
= gen_new_label();
1500 g_assert_not_reached();
1503 tcg_gen_brcondi_i32(TCG_COND_EQ
, var
, 0, not_taken
);
1504 gen_goto_tb(ctx
, 0, ctx
->npc
+ a
->imm
);
1505 gen_set_label(not_taken
);
1507 ctx
->bstate
= DISAS_CHAIN
;
1512 * Data Transfer Instructions
1516 * in the gen_set_addr & gen_get_addr functions
1517 * H assumed to be in 0x00ff0000 format
1518 * M assumed to be in 0x000000ff format
1519 * L assumed to be in 0x000000ff format
1521 static void gen_set_addr(TCGv addr
, TCGv H
, TCGv M
, TCGv L
)
1524 tcg_gen_andi_tl(L
, addr
, 0x000000ff);
1526 tcg_gen_andi_tl(M
, addr
, 0x0000ff00);
1527 tcg_gen_shri_tl(M
, M
, 8);
1529 tcg_gen_andi_tl(H
, addr
, 0x00ff0000);
1532 static void gen_set_xaddr(TCGv addr
)
1534 gen_set_addr(addr
, cpu_rampX
, cpu_r
[27], cpu_r
[26]);
1537 static void gen_set_yaddr(TCGv addr
)
1539 gen_set_addr(addr
, cpu_rampY
, cpu_r
[29], cpu_r
[28]);
1542 static void gen_set_zaddr(TCGv addr
)
1544 gen_set_addr(addr
, cpu_rampZ
, cpu_r
[31], cpu_r
[30]);
1547 static TCGv
gen_get_addr(TCGv H
, TCGv M
, TCGv L
)
1549 TCGv addr
= tcg_temp_new_i32();
1551 tcg_gen_deposit_tl(addr
, M
, H
, 8, 8);
1552 tcg_gen_deposit_tl(addr
, L
, addr
, 8, 16);
1557 static TCGv
gen_get_xaddr(void)
1559 return gen_get_addr(cpu_rampX
, cpu_r
[27], cpu_r
[26]);
1562 static TCGv
gen_get_yaddr(void)
1564 return gen_get_addr(cpu_rampY
, cpu_r
[29], cpu_r
[28]);
1567 static TCGv
gen_get_zaddr(void)
1569 return gen_get_addr(cpu_rampZ
, cpu_r
[31], cpu_r
[30]);
1573 * Load one byte indirect from data space to register and stores an clear
1574 * the bits in data space specified by the register. The instruction can only
1575 * be used towards internal SRAM. The data location is pointed to by the Z (16
1576 * bits) Pointer Register in the Register File. Memory access is limited to the
1577 * current data segment of 64KB. To access another data segment in devices with
1578 * more than 64KB data space, the RAMPZ in register in the I/O area has to be
1579 * changed. The Z-pointer Register is left unchanged by the operation. This
1580 * instruction is especially suited for clearing status bits stored in SRAM.
1582 static void gen_data_store(DisasContext
*ctx
, TCGv data
, TCGv addr
)
1584 if (ctx
->tb
->flags
& TB_FLAGS_FULL_ACCESS
) {
1585 gen_helper_fullwr(cpu_env
, data
, addr
);
1587 tcg_gen_qemu_st8(data
, addr
, MMU_DATA_IDX
); /* mem[addr] = data */
1591 static void gen_data_load(DisasContext
*ctx
, TCGv data
, TCGv addr
)
1593 if (ctx
->tb
->flags
& TB_FLAGS_FULL_ACCESS
) {
1594 gen_helper_fullrd(data
, cpu_env
, addr
);
1596 tcg_gen_qemu_ld8u(data
, addr
, MMU_DATA_IDX
); /* data = mem[addr] */
1601 * This instruction makes a copy of one register into another. The source
1602 * register Rr is left unchanged, while the destination register Rd is loaded
1603 * with a copy of Rr.
1605 static bool trans_MOV(DisasContext
*ctx
, arg_MOV
*a
)
1607 TCGv Rd
= cpu_r
[a
->rd
];
1608 TCGv Rr
= cpu_r
[a
->rr
];
1610 tcg_gen_mov_tl(Rd
, Rr
);
1616 * This instruction makes a copy of one register pair into another register
1617 * pair. The source register pair Rr+1:Rr is left unchanged, while the
1618 * destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr. This
1619 * instruction is not available in all devices. Refer to the device specific
1620 * instruction set summary.
1622 static bool trans_MOVW(DisasContext
*ctx
, arg_MOVW
*a
)
1624 if (!avr_have_feature(ctx
, AVR_FEATURE_MOVW
)) {
1628 TCGv RdL
= cpu_r
[a
->rd
];
1629 TCGv RdH
= cpu_r
[a
->rd
+ 1];
1630 TCGv RrL
= cpu_r
[a
->rr
];
1631 TCGv RrH
= cpu_r
[a
->rr
+ 1];
1633 tcg_gen_mov_tl(RdH
, RrH
);
1634 tcg_gen_mov_tl(RdL
, RrL
);
1640 * Loads an 8 bit constant directly to register 16 to 31.
1642 static bool trans_LDI(DisasContext
*ctx
, arg_LDI
*a
)
1644 TCGv Rd
= cpu_r
[a
->rd
];
1647 tcg_gen_movi_tl(Rd
, imm
);
1653 * Loads one byte from the data space to a register. For parts with SRAM,
1654 * the data space consists of the Register File, I/O memory and internal SRAM
1655 * (and external SRAM if applicable). For parts without SRAM, the data space
1656 * consists of the register file only. The EEPROM has a separate address space.
1657 * A 16-bit address must be supplied. Memory access is limited to the current
1658 * data segment of 64KB. The LDS instruction uses the RAMPD Register to access
1659 * memory above 64KB. To access another data segment in devices with more than
1660 * 64KB data space, the RAMPD in register in the I/O area has to be changed.
1661 * This instruction is not available in all devices. Refer to the device
1662 * specific instruction set summary.
1664 static bool trans_LDS(DisasContext
*ctx
, arg_LDS
*a
)
1666 TCGv Rd
= cpu_r
[a
->rd
];
1667 TCGv addr
= tcg_temp_new_i32();
1669 a
->imm
= next_word(ctx
);
1671 tcg_gen_mov_tl(addr
, H
); /* addr = H:M:L */
1672 tcg_gen_shli_tl(addr
, addr
, 16);
1673 tcg_gen_ori_tl(addr
, addr
, a
->imm
);
1675 gen_data_load(ctx
, Rd
, addr
);
1677 tcg_temp_free_i32(addr
);
1683 * Loads one byte indirect from the data space to a register. For parts
1684 * with SRAM, the data space consists of the Register File, I/O memory and
1685 * internal SRAM (and external SRAM if applicable). For parts without SRAM, the
1686 * data space consists of the Register File only. In some parts the Flash
1687 * Memory has been mapped to the data space and can be read using this command.
1688 * The EEPROM has a separate address space. The data location is pointed to by
1689 * the X (16 bits) Pointer Register in the Register File. Memory access is
1690 * limited to the current data segment of 64KB. To access another data segment
1691 * in devices with more than 64KB data space, the RAMPX in register in the I/O
1692 * area has to be changed. The X-pointer Register can either be left unchanged
1693 * by the operation, or it can be post-incremented or predecremented. These
1694 * features are especially suited for accessing arrays, tables, and Stack
1695 * Pointer usage of the X-pointer Register. Note that only the low byte of the
1696 * X-pointer is updated in devices with no more than 256 bytes data space. For
1697 * such devices, the high byte of the pointer is not used by this instruction
1698 * and can be used for other purposes. The RAMPX Register in the I/O area is
1699 * updated in parts with more than 64KB data space or more than 64KB Program
1700 * memory, and the increment/decrement is added to the entire 24-bit address on
1701 * such devices. Not all variants of this instruction is available in all
1702 * devices. Refer to the device specific instruction set summary. In the
1703 * Reduced Core tinyAVR the LD instruction can be used to achieve the same
1704 * operation as LPM since the program memory is mapped to the data memory
1707 static bool trans_LDX1(DisasContext
*ctx
, arg_LDX1
*a
)
1709 TCGv Rd
= cpu_r
[a
->rd
];
1710 TCGv addr
= gen_get_xaddr();
1712 gen_data_load(ctx
, Rd
, addr
);
1714 tcg_temp_free_i32(addr
);
1719 static bool trans_LDX2(DisasContext
*ctx
, arg_LDX2
*a
)
1721 TCGv Rd
= cpu_r
[a
->rd
];
1722 TCGv addr
= gen_get_xaddr();
1724 gen_data_load(ctx
, Rd
, addr
);
1725 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
1727 gen_set_xaddr(addr
);
1729 tcg_temp_free_i32(addr
);
1734 static bool trans_LDX3(DisasContext
*ctx
, arg_LDX3
*a
)
1736 TCGv Rd
= cpu_r
[a
->rd
];
1737 TCGv addr
= gen_get_xaddr();
1739 tcg_gen_subi_tl(addr
, addr
, 1); /* addr = addr - 1 */
1740 gen_data_load(ctx
, Rd
, addr
);
1741 gen_set_xaddr(addr
);
1743 tcg_temp_free_i32(addr
);
1749 * Loads one byte indirect with or without displacement from the data space
1750 * to a register. For parts with SRAM, the data space consists of the Register
1751 * File, I/O memory and internal SRAM (and external SRAM if applicable). For
1752 * parts without SRAM, the data space consists of the Register File only. In
1753 * some parts the Flash Memory has been mapped to the data space and can be
1754 * read using this command. The EEPROM has a separate address space. The data
1755 * location is pointed to by the Y (16 bits) Pointer Register in the Register
1756 * File. Memory access is limited to the current data segment of 64KB. To
1757 * access another data segment in devices with more than 64KB data space, the
1758 * RAMPY in register in the I/O area has to be changed. The Y-pointer Register
1759 * can either be left unchanged by the operation, or it can be post-incremented
1760 * or predecremented. These features are especially suited for accessing
1761 * arrays, tables, and Stack Pointer usage of the Y-pointer Register. Note that
1762 * only the low byte of the Y-pointer is updated in devices with no more than
1763 * 256 bytes data space. For such devices, the high byte of the pointer is not
1764 * used by this instruction and can be used for other purposes. The RAMPY
1765 * Register in the I/O area is updated in parts with more than 64KB data space
1766 * or more than 64KB Program memory, and the increment/decrement/displacement
1767 * is added to the entire 24-bit address on such devices. Not all variants of
1768 * this instruction is available in all devices. Refer to the device specific
1769 * instruction set summary. In the Reduced Core tinyAVR the LD instruction can
1770 * be used to achieve the same operation as LPM since the program memory is
1771 * mapped to the data memory space.
1773 static bool trans_LDY2(DisasContext
*ctx
, arg_LDY2
*a
)
1775 TCGv Rd
= cpu_r
[a
->rd
];
1776 TCGv addr
= gen_get_yaddr();
1778 gen_data_load(ctx
, Rd
, addr
);
1779 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
1781 gen_set_yaddr(addr
);
1783 tcg_temp_free_i32(addr
);
1788 static bool trans_LDY3(DisasContext
*ctx
, arg_LDY3
*a
)
1790 TCGv Rd
= cpu_r
[a
->rd
];
1791 TCGv addr
= gen_get_yaddr();
1793 tcg_gen_subi_tl(addr
, addr
, 1); /* addr = addr - 1 */
1794 gen_data_load(ctx
, Rd
, addr
);
1795 gen_set_yaddr(addr
);
1797 tcg_temp_free_i32(addr
);
1802 static bool trans_LDDY(DisasContext
*ctx
, arg_LDDY
*a
)
1804 TCGv Rd
= cpu_r
[a
->rd
];
1805 TCGv addr
= gen_get_yaddr();
1807 tcg_gen_addi_tl(addr
, addr
, a
->imm
); /* addr = addr + q */
1808 gen_data_load(ctx
, Rd
, addr
);
1810 tcg_temp_free_i32(addr
);
1816 * Loads one byte indirect with or without displacement from the data space
1817 * to a register. For parts with SRAM, the data space consists of the Register
1818 * File, I/O memory and internal SRAM (and external SRAM if applicable). For
1819 * parts without SRAM, the data space consists of the Register File only. In
1820 * some parts the Flash Memory has been mapped to the data space and can be
1821 * read using this command. The EEPROM has a separate address space. The data
1822 * location is pointed to by the Z (16 bits) Pointer Register in the Register
1823 * File. Memory access is limited to the current data segment of 64KB. To
1824 * access another data segment in devices with more than 64KB data space, the
1825 * RAMPZ in register in the I/O area has to be changed. The Z-pointer Register
1826 * can either be left unchanged by the operation, or it can be post-incremented
1827 * or predecremented. These features are especially suited for Stack Pointer
1828 * usage of the Z-pointer Register, however because the Z-pointer Register can
1829 * be used for indirect subroutine calls, indirect jumps and table lookup, it
1830 * is often more convenient to use the X or Y-pointer as a dedicated Stack
1831 * Pointer. Note that only the low byte of the Z-pointer is updated in devices
1832 * with no more than 256 bytes data space. For such devices, the high byte of
1833 * the pointer is not used by this instruction and can be used for other
1834 * purposes. The RAMPZ Register in the I/O area is updated in parts with more
1835 * than 64KB data space or more than 64KB Program memory, and the
1836 * increment/decrement/displacement is added to the entire 24-bit address on
1837 * such devices. Not all variants of this instruction is available in all
1838 * devices. Refer to the device specific instruction set summary. In the
1839 * Reduced Core tinyAVR the LD instruction can be used to achieve the same
1840 * operation as LPM since the program memory is mapped to the data memory
1841 * space. For using the Z-pointer for table lookup in Program memory see the
1842 * LPM and ELPM instructions.
1844 static bool trans_LDZ2(DisasContext
*ctx
, arg_LDZ2
*a
)
1846 TCGv Rd
= cpu_r
[a
->rd
];
1847 TCGv addr
= gen_get_zaddr();
1849 gen_data_load(ctx
, Rd
, addr
);
1850 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
1852 gen_set_zaddr(addr
);
1854 tcg_temp_free_i32(addr
);
1859 static bool trans_LDZ3(DisasContext
*ctx
, arg_LDZ3
*a
)
1861 TCGv Rd
= cpu_r
[a
->rd
];
1862 TCGv addr
= gen_get_zaddr();
1864 tcg_gen_subi_tl(addr
, addr
, 1); /* addr = addr - 1 */
1865 gen_data_load(ctx
, Rd
, addr
);
1867 gen_set_zaddr(addr
);
1869 tcg_temp_free_i32(addr
);
1874 static bool trans_LDDZ(DisasContext
*ctx
, arg_LDDZ
*a
)
1876 TCGv Rd
= cpu_r
[a
->rd
];
1877 TCGv addr
= gen_get_zaddr();
1879 tcg_gen_addi_tl(addr
, addr
, a
->imm
); /* addr = addr + q */
1880 gen_data_load(ctx
, Rd
, addr
);
1882 tcg_temp_free_i32(addr
);
1888 * Stores one byte from a Register to the data space. For parts with SRAM,
1889 * the data space consists of the Register File, I/O memory and internal SRAM
1890 * (and external SRAM if applicable). For parts without SRAM, the data space
1891 * consists of the Register File only. The EEPROM has a separate address space.
1892 * A 16-bit address must be supplied. Memory access is limited to the current
1893 * data segment of 64KB. The STS instruction uses the RAMPD Register to access
1894 * memory above 64KB. To access another data segment in devices with more than
1895 * 64KB data space, the RAMPD in register in the I/O area has to be changed.
1896 * This instruction is not available in all devices. Refer to the device
1897 * specific instruction set summary.
1899 static bool trans_STS(DisasContext
*ctx
, arg_STS
*a
)
1901 TCGv Rd
= cpu_r
[a
->rd
];
1902 TCGv addr
= tcg_temp_new_i32();
1904 a
->imm
= next_word(ctx
);
1906 tcg_gen_mov_tl(addr
, H
); /* addr = H:M:L */
1907 tcg_gen_shli_tl(addr
, addr
, 16);
1908 tcg_gen_ori_tl(addr
, addr
, a
->imm
);
1909 gen_data_store(ctx
, Rd
, addr
);
1911 tcg_temp_free_i32(addr
);
1917 * Stores one byte indirect from a register to data space. For parts with SRAM,
1918 * the data space consists of the Register File, I/O memory, and internal SRAM
1919 * (and external SRAM if applicable). For parts without SRAM, the data space
1920 * consists of the Register File only. The EEPROM has a separate address space.
1922 * The data location is pointed to by the X (16 bits) Pointer Register in the
1923 * Register File. Memory access is limited to the current data segment of 64KB.
1924 * To access another data segment in devices with more than 64KB data space, the
1925 * RAMPX in register in the I/O area has to be changed.
1927 * The X-pointer Register can either be left unchanged by the operation, or it
1928 * can be post-incremented or pre-decremented. These features are especially
1929 * suited for accessing arrays, tables, and Stack Pointer usage of the
1930 * X-pointer Register. Note that only the low byte of the X-pointer is updated
1931 * in devices with no more than 256 bytes data space. For such devices, the high
1932 * byte of the pointer is not used by this instruction and can be used for other
1933 * purposes. The RAMPX Register in the I/O area is updated in parts with more
1934 * than 64KB data space or more than 64KB Program memory, and the increment /
1935 * decrement is added to the entire 24-bit address on such devices.
1937 static bool trans_STX1(DisasContext
*ctx
, arg_STX1
*a
)
1939 TCGv Rd
= cpu_r
[a
->rr
];
1940 TCGv addr
= gen_get_xaddr();
1942 gen_data_store(ctx
, Rd
, addr
);
1944 tcg_temp_free_i32(addr
);
1949 static bool trans_STX2(DisasContext
*ctx
, arg_STX2
*a
)
1951 TCGv Rd
= cpu_r
[a
->rr
];
1952 TCGv addr
= gen_get_xaddr();
1954 gen_data_store(ctx
, Rd
, addr
);
1955 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
1956 gen_set_xaddr(addr
);
1958 tcg_temp_free_i32(addr
);
1963 static bool trans_STX3(DisasContext
*ctx
, arg_STX3
*a
)
1965 TCGv Rd
= cpu_r
[a
->rr
];
1966 TCGv addr
= gen_get_xaddr();
1968 tcg_gen_subi_tl(addr
, addr
, 1); /* addr = addr - 1 */
1969 gen_data_store(ctx
, Rd
, addr
);
1970 gen_set_xaddr(addr
);
1972 tcg_temp_free_i32(addr
);
1978 * Stores one byte indirect with or without displacement from a register to data
1979 * space. For parts with SRAM, the data space consists of the Register File, I/O
1980 * memory, and internal SRAM (and external SRAM if applicable). For parts
1981 * without SRAM, the data space consists of the Register File only. The EEPROM
1982 * has a separate address space.
1984 * The data location is pointed to by the Y (16 bits) Pointer Register in the
1985 * Register File. Memory access is limited to the current data segment of 64KB.
1986 * To access another data segment in devices with more than 64KB data space, the
1987 * RAMPY in register in the I/O area has to be changed.
1989 * The Y-pointer Register can either be left unchanged by the operation, or it
1990 * can be post-incremented or pre-decremented. These features are especially
1991 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer
1992 * Register. Note that only the low byte of the Y-pointer is updated in devices
1993 * with no more than 256 bytes data space. For such devices, the high byte of
1994 * the pointer is not used by this instruction and can be used for other
1995 * purposes. The RAMPY Register in the I/O area is updated in parts with more
1996 * than 64KB data space or more than 64KB Program memory, and the increment /
1997 * decrement / displacement is added to the entire 24-bit address on such
2000 static bool trans_STY2(DisasContext
*ctx
, arg_STY2
*a
)
2002 TCGv Rd
= cpu_r
[a
->rd
];
2003 TCGv addr
= gen_get_yaddr();
2005 gen_data_store(ctx
, Rd
, addr
);
2006 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
2007 gen_set_yaddr(addr
);
2009 tcg_temp_free_i32(addr
);
2014 static bool trans_STY3(DisasContext
*ctx
, arg_STY3
*a
)
2016 TCGv Rd
= cpu_r
[a
->rd
];
2017 TCGv addr
= gen_get_yaddr();
2019 tcg_gen_subi_tl(addr
, addr
, 1); /* addr = addr - 1 */
2020 gen_data_store(ctx
, Rd
, addr
);
2021 gen_set_yaddr(addr
);
2023 tcg_temp_free_i32(addr
);
2028 static bool trans_STDY(DisasContext
*ctx
, arg_STDY
*a
)
2030 TCGv Rd
= cpu_r
[a
->rd
];
2031 TCGv addr
= gen_get_yaddr();
2033 tcg_gen_addi_tl(addr
, addr
, a
->imm
); /* addr = addr + q */
2034 gen_data_store(ctx
, Rd
, addr
);
2036 tcg_temp_free_i32(addr
);
2042 * Stores one byte indirect with or without displacement from a register to data
2043 * space. For parts with SRAM, the data space consists of the Register File, I/O
2044 * memory, and internal SRAM (and external SRAM if applicable). For parts
2045 * without SRAM, the data space consists of the Register File only. The EEPROM
2046 * has a separate address space.
2048 * The data location is pointed to by the Y (16 bits) Pointer Register in the
2049 * Register File. Memory access is limited to the current data segment of 64KB.
2050 * To access another data segment in devices with more than 64KB data space, the
2051 * RAMPY in register in the I/O area has to be changed.
2053 * The Y-pointer Register can either be left unchanged by the operation, or it
2054 * can be post-incremented or pre-decremented. These features are especially
2055 * suited for accessing arrays, tables, and Stack Pointer usage of the Y-pointer
2056 * Register. Note that only the low byte of the Y-pointer is updated in devices
2057 * with no more than 256 bytes data space. For such devices, the high byte of
2058 * the pointer is not used by this instruction and can be used for other
2059 * purposes. The RAMPY Register in the I/O area is updated in parts with more
2060 * than 64KB data space or more than 64KB Program memory, and the increment /
2061 * decrement / displacement is added to the entire 24-bit address on such
2064 static bool trans_STZ2(DisasContext
*ctx
, arg_STZ2
*a
)
2066 TCGv Rd
= cpu_r
[a
->rd
];
2067 TCGv addr
= gen_get_zaddr();
2069 gen_data_store(ctx
, Rd
, addr
);
2070 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
2072 gen_set_zaddr(addr
);
2074 tcg_temp_free_i32(addr
);
2079 static bool trans_STZ3(DisasContext
*ctx
, arg_STZ3
*a
)
2081 TCGv Rd
= cpu_r
[a
->rd
];
2082 TCGv addr
= gen_get_zaddr();
2084 tcg_gen_subi_tl(addr
, addr
, 1); /* addr = addr - 1 */
2085 gen_data_store(ctx
, Rd
, addr
);
2087 gen_set_zaddr(addr
);
2089 tcg_temp_free_i32(addr
);
2094 static bool trans_STDZ(DisasContext
*ctx
, arg_STDZ
*a
)
2096 TCGv Rd
= cpu_r
[a
->rd
];
2097 TCGv addr
= gen_get_zaddr();
2099 tcg_gen_addi_tl(addr
, addr
, a
->imm
); /* addr = addr + q */
2100 gen_data_store(ctx
, Rd
, addr
);
2102 tcg_temp_free_i32(addr
);
2108 * Loads one byte pointed to by the Z-register into the destination
2109 * register Rd. This instruction features a 100% space effective constant
2110 * initialization or constant data fetch. The Program memory is organized in
2111 * 16-bit words while the Z-pointer is a byte address. Thus, the least
2112 * significant bit of the Z-pointer selects either low byte (ZLSB = 0) or high
2113 * byte (ZLSB = 1). This instruction can address the first 64KB (32K words) of
2114 * Program memory. The Zpointer Register can either be left unchanged by the
2115 * operation, or it can be incremented. The incrementation does not apply to
2116 * the RAMPZ Register.
2118 * Devices with Self-Programming capability can use the LPM instruction to read
2119 * the Fuse and Lock bit values.
2121 static bool trans_LPM1(DisasContext
*ctx
, arg_LPM1
*a
)
2123 if (!avr_have_feature(ctx
, AVR_FEATURE_LPM
)) {
2128 TCGv addr
= tcg_temp_new_i32();
2132 tcg_gen_shli_tl(addr
, H
, 8); /* addr = H:L */
2133 tcg_gen_or_tl(addr
, addr
, L
);
2134 tcg_gen_qemu_ld8u(Rd
, addr
, MMU_CODE_IDX
); /* Rd = mem[addr] */
2136 tcg_temp_free_i32(addr
);
2141 static bool trans_LPM2(DisasContext
*ctx
, arg_LPM2
*a
)
2143 if (!avr_have_feature(ctx
, AVR_FEATURE_LPM
)) {
2147 TCGv Rd
= cpu_r
[a
->rd
];
2148 TCGv addr
= tcg_temp_new_i32();
2152 tcg_gen_shli_tl(addr
, H
, 8); /* addr = H:L */
2153 tcg_gen_or_tl(addr
, addr
, L
);
2154 tcg_gen_qemu_ld8u(Rd
, addr
, MMU_CODE_IDX
); /* Rd = mem[addr] */
2156 tcg_temp_free_i32(addr
);
2161 static bool trans_LPMX(DisasContext
*ctx
, arg_LPMX
*a
)
2163 if (!avr_have_feature(ctx
, AVR_FEATURE_LPMX
)) {
2167 TCGv Rd
= cpu_r
[a
->rd
];
2168 TCGv addr
= tcg_temp_new_i32();
2172 tcg_gen_shli_tl(addr
, H
, 8); /* addr = H:L */
2173 tcg_gen_or_tl(addr
, addr
, L
);
2174 tcg_gen_qemu_ld8u(Rd
, addr
, MMU_CODE_IDX
); /* Rd = mem[addr] */
2175 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
2176 tcg_gen_andi_tl(L
, addr
, 0xff);
2177 tcg_gen_shri_tl(addr
, addr
, 8);
2178 tcg_gen_andi_tl(H
, addr
, 0xff);
2180 tcg_temp_free_i32(addr
);
2186 * Loads one byte pointed to by the Z-register and the RAMPZ Register in
2187 * the I/O space, and places this byte in the destination register Rd. This
2188 * instruction features a 100% space effective constant initialization or
2189 * constant data fetch. The Program memory is organized in 16-bit words while
2190 * the Z-pointer is a byte address. Thus, the least significant bit of the
2191 * Z-pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This
2192 * instruction can address the entire Program memory space. The Z-pointer
2193 * Register can either be left unchanged by the operation, or it can be
2194 * incremented. The incrementation applies to the entire 24-bit concatenation
2195 * of the RAMPZ and Z-pointer Registers.
2197 * Devices with Self-Programming capability can use the ELPM instruction to
2198 * read the Fuse and Lock bit value.
2200 static bool trans_ELPM1(DisasContext
*ctx
, arg_ELPM1
*a
)
2202 if (!avr_have_feature(ctx
, AVR_FEATURE_ELPM
)) {
2207 TCGv addr
= gen_get_zaddr();
2209 tcg_gen_qemu_ld8u(Rd
, addr
, MMU_CODE_IDX
); /* Rd = mem[addr] */
2211 tcg_temp_free_i32(addr
);
2216 static bool trans_ELPM2(DisasContext
*ctx
, arg_ELPM2
*a
)
2218 if (!avr_have_feature(ctx
, AVR_FEATURE_ELPM
)) {
2222 TCGv Rd
= cpu_r
[a
->rd
];
2223 TCGv addr
= gen_get_zaddr();
2225 tcg_gen_qemu_ld8u(Rd
, addr
, MMU_CODE_IDX
); /* Rd = mem[addr] */
2227 tcg_temp_free_i32(addr
);
2232 static bool trans_ELPMX(DisasContext
*ctx
, arg_ELPMX
*a
)
2234 if (!avr_have_feature(ctx
, AVR_FEATURE_ELPMX
)) {
2238 TCGv Rd
= cpu_r
[a
->rd
];
2239 TCGv addr
= gen_get_zaddr();
2241 tcg_gen_qemu_ld8u(Rd
, addr
, MMU_CODE_IDX
); /* Rd = mem[addr] */
2242 tcg_gen_addi_tl(addr
, addr
, 1); /* addr = addr + 1 */
2243 gen_set_zaddr(addr
);
2245 tcg_temp_free_i32(addr
);
2251 * SPM can be used to erase a page in the Program memory, to write a page
2252 * in the Program memory (that is already erased), and to set Boot Loader Lock
2253 * bits. In some devices, the Program memory can be written one word at a time,
2254 * in other devices an entire page can be programmed simultaneously after first
2255 * filling a temporary page buffer. In all cases, the Program memory must be
2256 * erased one page at a time. When erasing the Program memory, the RAMPZ and
2257 * Z-register are used as page address. When writing the Program memory, the
2258 * RAMPZ and Z-register are used as page or word address, and the R1:R0
2259 * register pair is used as data(1). When setting the Boot Loader Lock bits,
2260 * the R1:R0 register pair is used as data. Refer to the device documentation
2261 * for detailed description of SPM usage. This instruction can address the
2262 * entire Program memory.
2264 * The SPM instruction is not available in all devices. Refer to the device
2265 * specific instruction set summary.
2267 * Note: 1. R1 determines the instruction high byte, and R0 determines the
2268 * instruction low byte.
2270 static bool trans_SPM(DisasContext
*ctx
, arg_SPM
*a
)
2273 if (!avr_have_feature(ctx
, AVR_FEATURE_SPM
)) {
2280 static bool trans_SPMX(DisasContext
*ctx
, arg_SPMX
*a
)
2283 if (!avr_have_feature(ctx
, AVR_FEATURE_SPMX
)) {
2291 * Loads data from the I/O Space (Ports, Timers, Configuration Registers,
2292 * etc.) into register Rd in the Register File.
2294 static bool trans_IN(DisasContext
*ctx
, arg_IN
*a
)
2296 TCGv Rd
= cpu_r
[a
->rd
];
2297 TCGv port
= tcg_const_i32(a
->imm
);
2299 gen_helper_inb(Rd
, cpu_env
, port
);
2301 tcg_temp_free_i32(port
);
2307 * Stores data from register Rr in the Register File to I/O Space (Ports,
2308 * Timers, Configuration Registers, etc.).
2310 static bool trans_OUT(DisasContext
*ctx
, arg_OUT
*a
)
2312 TCGv Rd
= cpu_r
[a
->rd
];
2313 TCGv port
= tcg_const_i32(a
->imm
);
2315 gen_helper_outb(cpu_env
, port
, Rd
);
2317 tcg_temp_free_i32(port
);
2323 * This instruction stores the contents of register Rr on the STACK. The
2324 * Stack Pointer is post-decremented by 1 after the PUSH. This instruction is
2325 * not available in all devices. Refer to the device specific instruction set
2328 static bool trans_PUSH(DisasContext
*ctx
, arg_PUSH
*a
)
2330 TCGv Rd
= cpu_r
[a
->rd
];
2332 gen_data_store(ctx
, Rd
, cpu_sp
);
2333 tcg_gen_subi_tl(cpu_sp
, cpu_sp
, 1);
2339 * This instruction loads register Rd with a byte from the STACK. The Stack
2340 * Pointer is pre-incremented by 1 before the POP. This instruction is not
2341 * available in all devices. Refer to the device specific instruction set
2344 static bool trans_POP(DisasContext
*ctx
, arg_POP
*a
)
2347 * Using a temp to work around some strange behaviour:
2348 * tcg_gen_addi_tl(cpu_sp, cpu_sp, 1);
2349 * gen_data_load(ctx, Rd, cpu_sp);
2350 * seems to cause the add to happen twice.
2351 * This doesn't happen if either the add or the load is removed.
2353 TCGv t1
= tcg_temp_new_i32();
2354 TCGv Rd
= cpu_r
[a
->rd
];
2356 tcg_gen_addi_tl(t1
, cpu_sp
, 1);
2357 gen_data_load(ctx
, Rd
, t1
);
2358 tcg_gen_mov_tl(cpu_sp
, t1
);
2364 * Exchanges one byte indirect between register and data space. The data
2365 * location is pointed to by the Z (16 bits) Pointer Register in the Register
2366 * File. Memory access is limited to the current data segment of 64KB. To
2367 * access another data segment in devices with more than 64KB data space, the
2368 * RAMPZ in register in the I/O area has to be changed.
2370 * The Z-pointer Register is left unchanged by the operation. This instruction
2371 * is especially suited for writing/reading status bits stored in SRAM.
2373 static bool trans_XCH(DisasContext
*ctx
, arg_XCH
*a
)
2375 if (!avr_have_feature(ctx
, AVR_FEATURE_RMW
)) {
2379 TCGv Rd
= cpu_r
[a
->rd
];
2380 TCGv t0
= tcg_temp_new_i32();
2381 TCGv addr
= gen_get_zaddr();
2383 gen_data_load(ctx
, t0
, addr
);
2384 gen_data_store(ctx
, Rd
, addr
);
2385 tcg_gen_mov_tl(Rd
, t0
);
2387 tcg_temp_free_i32(t0
);
2388 tcg_temp_free_i32(addr
);
2394 * Load one byte indirect from data space to register and set bits in data
2395 * space specified by the register. The instruction can only be used towards
2396 * internal SRAM. The data location is pointed to by the Z (16 bits) Pointer
2397 * Register in the Register File. Memory access is limited to the current data
2398 * segment of 64KB. To access another data segment in devices with more than
2399 * 64KB data space, the RAMPZ in register in the I/O area has to be changed.
2401 * The Z-pointer Register is left unchanged by the operation. This instruction
2402 * is especially suited for setting status bits stored in SRAM.
2404 static bool trans_LAS(DisasContext
*ctx
, arg_LAS
*a
)
2406 if (!avr_have_feature(ctx
, AVR_FEATURE_RMW
)) {
2410 TCGv Rr
= cpu_r
[a
->rd
];
2411 TCGv addr
= gen_get_zaddr();
2412 TCGv t0
= tcg_temp_new_i32();
2413 TCGv t1
= tcg_temp_new_i32();
2415 gen_data_load(ctx
, t0
, addr
); /* t0 = mem[addr] */
2416 tcg_gen_or_tl(t1
, t0
, Rr
);
2417 tcg_gen_mov_tl(Rr
, t0
); /* Rr = t0 */
2418 gen_data_store(ctx
, t1
, addr
); /* mem[addr] = t1 */
2420 tcg_temp_free_i32(t1
);
2421 tcg_temp_free_i32(t0
);
2422 tcg_temp_free_i32(addr
);
2428 * Load one byte indirect from data space to register and stores and clear
2429 * the bits in data space specified by the register. The instruction can
2430 * only be used towards internal SRAM. The data location is pointed to by
2431 * the Z (16 bits) Pointer Register in the Register File. Memory access is
2432 * limited to the current data segment of 64KB. To access another data
2433 * segment in devices with more than 64KB data space, the RAMPZ in register
2434 * in the I/O area has to be changed.
2436 * The Z-pointer Register is left unchanged by the operation. This instruction
2437 * is especially suited for clearing status bits stored in SRAM.
2439 static bool trans_LAC(DisasContext
*ctx
, arg_LAC
*a
)
2441 if (!avr_have_feature(ctx
, AVR_FEATURE_RMW
)) {
2445 TCGv Rr
= cpu_r
[a
->rd
];
2446 TCGv addr
= gen_get_zaddr();
2447 TCGv t0
= tcg_temp_new_i32();
2448 TCGv t1
= tcg_temp_new_i32();
2450 gen_data_load(ctx
, t0
, addr
); /* t0 = mem[addr] */
2451 tcg_gen_andc_tl(t1
, t0
, Rr
); /* t1 = t0 & (0xff - Rr) = t0 & ~Rr */
2452 tcg_gen_mov_tl(Rr
, t0
); /* Rr = t0 */
2453 gen_data_store(ctx
, t1
, addr
); /* mem[addr] = t1 */
2455 tcg_temp_free_i32(t1
);
2456 tcg_temp_free_i32(t0
);
2457 tcg_temp_free_i32(addr
);
2464 * Load one byte indirect from data space to register and toggles bits in
2465 * the data space specified by the register. The instruction can only be used
2466 * towards SRAM. The data location is pointed to by the Z (16 bits) Pointer
2467 * Register in the Register File. Memory access is limited to the current data
2468 * segment of 64KB. To access another data segment in devices with more than
2469 * 64KB data space, the RAMPZ in register in the I/O area has to be changed.
2471 * The Z-pointer Register is left unchanged by the operation. This instruction
2472 * is especially suited for changing status bits stored in SRAM.
2474 static bool trans_LAT(DisasContext
*ctx
, arg_LAT
*a
)
2476 if (!avr_have_feature(ctx
, AVR_FEATURE_RMW
)) {
2480 TCGv Rd
= cpu_r
[a
->rd
];
2481 TCGv addr
= gen_get_zaddr();
2482 TCGv t0
= tcg_temp_new_i32();
2483 TCGv t1
= tcg_temp_new_i32();
2485 gen_data_load(ctx
, t0
, addr
); /* t0 = mem[addr] */
2486 tcg_gen_xor_tl(t1
, t0
, Rd
);
2487 tcg_gen_mov_tl(Rd
, t0
); /* Rd = t0 */
2488 gen_data_store(ctx
, t1
, addr
); /* mem[addr] = t1 */
2490 tcg_temp_free_i32(t1
);
2491 tcg_temp_free_i32(t0
);
2492 tcg_temp_free_i32(addr
);
2498 * Bit and Bit-test Instructions
2500 static void gen_rshift_ZNVSf(TCGv R
)
2502 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, R
, 0); /* Zf = R == 0 */
2503 tcg_gen_shri_tl(cpu_Nf
, R
, 7); /* Nf = R(7) */
2504 tcg_gen_xor_tl(cpu_Vf
, cpu_Nf
, cpu_Cf
);
2505 tcg_gen_xor_tl(cpu_Sf
, cpu_Nf
, cpu_Vf
); /* Sf = Nf ^ Vf */
2509 * Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is
2510 * loaded into the C Flag of the SREG. This operation effectively divides an
2511 * unsigned value by two. The C Flag can be used to round the result.
2513 static bool trans_LSR(DisasContext
*ctx
, arg_LSR
*a
)
2515 TCGv Rd
= cpu_r
[a
->rd
];
2517 tcg_gen_andi_tl(cpu_Cf
, Rd
, 1);
2518 tcg_gen_shri_tl(Rd
, Rd
, 1);
2520 /* update status register */
2521 tcg_gen_setcondi_tl(TCG_COND_EQ
, cpu_Zf
, Rd
, 0); /* Zf = Rd == 0 */
2522 tcg_gen_movi_tl(cpu_Nf
, 0);
2523 tcg_gen_mov_tl(cpu_Vf
, cpu_Cf
);
2524 tcg_gen_mov_tl(cpu_Sf
, cpu_Vf
);
2530 * Shifts all bits in Rd one place to the right. The C Flag is shifted into
2531 * bit 7 of Rd. Bit 0 is shifted into the C Flag. This operation, combined
2532 * with ASR, effectively divides multi-byte signed values by two. Combined with
2533 * LSR it effectively divides multi-byte unsigned values by two. The Carry Flag
2534 * can be used to round the result.
2536 static bool trans_ROR(DisasContext
*ctx
, arg_ROR
*a
)
2538 TCGv Rd
= cpu_r
[a
->rd
];
2539 TCGv t0
= tcg_temp_new_i32();
2541 tcg_gen_shli_tl(t0
, cpu_Cf
, 7);
2543 /* update status register */
2544 tcg_gen_andi_tl(cpu_Cf
, Rd
, 1);
2546 /* update output register */
2547 tcg_gen_shri_tl(Rd
, Rd
, 1);
2548 tcg_gen_or_tl(Rd
, Rd
, t0
);
2550 /* update status register */
2551 gen_rshift_ZNVSf(Rd
);
2553 tcg_temp_free_i32(t0
);
2559 * Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0
2560 * is loaded into the C Flag of the SREG. This operation effectively divides a
2561 * signed value by two without changing its sign. The Carry Flag can be used to
2564 static bool trans_ASR(DisasContext
*ctx
, arg_ASR
*a
)
2566 TCGv Rd
= cpu_r
[a
->rd
];
2567 TCGv t0
= tcg_temp_new_i32();
2569 /* update status register */
2570 tcg_gen_andi_tl(cpu_Cf
, Rd
, 1); /* Cf = Rd(0) */
2572 /* update output register */
2573 tcg_gen_andi_tl(t0
, Rd
, 0x80); /* Rd = (Rd & 0x80) | (Rd >> 1) */
2574 tcg_gen_shri_tl(Rd
, Rd
, 1);
2575 tcg_gen_or_tl(Rd
, Rd
, t0
);
2577 /* update status register */
2578 gen_rshift_ZNVSf(Rd
);
2580 tcg_temp_free_i32(t0
);
2586 * Swaps high and low nibbles in a register.
2588 static bool trans_SWAP(DisasContext
*ctx
, arg_SWAP
*a
)
2590 TCGv Rd
= cpu_r
[a
->rd
];
2591 TCGv t0
= tcg_temp_new_i32();
2592 TCGv t1
= tcg_temp_new_i32();
2594 tcg_gen_andi_tl(t0
, Rd
, 0x0f);
2595 tcg_gen_shli_tl(t0
, t0
, 4);
2596 tcg_gen_andi_tl(t1
, Rd
, 0xf0);
2597 tcg_gen_shri_tl(t1
, t1
, 4);
2598 tcg_gen_or_tl(Rd
, t0
, t1
);
2600 tcg_temp_free_i32(t1
);
2601 tcg_temp_free_i32(t0
);
2607 * Sets a specified bit in an I/O Register. This instruction operates on
2608 * the lower 32 I/O Registers -- addresses 0-31.
2610 static bool trans_SBI(DisasContext
*ctx
, arg_SBI
*a
)
2612 TCGv data
= tcg_temp_new_i32();
2613 TCGv port
= tcg_const_i32(a
->reg
);
2615 gen_helper_inb(data
, cpu_env
, port
);
2616 tcg_gen_ori_tl(data
, data
, 1 << a
->bit
);
2617 gen_helper_outb(cpu_env
, port
, data
);
2619 tcg_temp_free_i32(port
);
2620 tcg_temp_free_i32(data
);
2626 * Clears a specified bit in an I/O Register. This instruction operates on
2627 * the lower 32 I/O Registers -- addresses 0-31.
2629 static bool trans_CBI(DisasContext
*ctx
, arg_CBI
*a
)
2631 TCGv data
= tcg_temp_new_i32();
2632 TCGv port
= tcg_const_i32(a
->reg
);
2634 gen_helper_inb(data
, cpu_env
, port
);
2635 tcg_gen_andi_tl(data
, data
, ~(1 << a
->bit
));
2636 gen_helper_outb(cpu_env
, port
, data
);
2638 tcg_temp_free_i32(data
);
2639 tcg_temp_free_i32(port
);
2645 * Stores bit b from Rd to the T Flag in SREG (Status Register).
2647 static bool trans_BST(DisasContext
*ctx
, arg_BST
*a
)
2649 TCGv Rd
= cpu_r
[a
->rd
];
2651 tcg_gen_andi_tl(cpu_Tf
, Rd
, 1 << a
->bit
);
2652 tcg_gen_shri_tl(cpu_Tf
, cpu_Tf
, a
->bit
);
2658 * Copies the T Flag in the SREG (Status Register) to bit b in register Rd.
2660 static bool trans_BLD(DisasContext
*ctx
, arg_BLD
*a
)
2662 TCGv Rd
= cpu_r
[a
->rd
];
2663 TCGv t1
= tcg_temp_new_i32();
2665 tcg_gen_andi_tl(Rd
, Rd
, ~(1u << a
->bit
)); /* clear bit */
2666 tcg_gen_shli_tl(t1
, cpu_Tf
, a
->bit
); /* create mask */
2667 tcg_gen_or_tl(Rd
, Rd
, t1
);
2669 tcg_temp_free_i32(t1
);
2675 * Sets a single Flag or bit in SREG.
2677 static bool trans_BSET(DisasContext
*ctx
, arg_BSET
*a
)
2681 tcg_gen_movi_tl(cpu_Cf
, 0x01);
2684 tcg_gen_movi_tl(cpu_Zf
, 0x01);
2687 tcg_gen_movi_tl(cpu_Nf
, 0x01);
2690 tcg_gen_movi_tl(cpu_Vf
, 0x01);
2693 tcg_gen_movi_tl(cpu_Sf
, 0x01);
2696 tcg_gen_movi_tl(cpu_Hf
, 0x01);
2699 tcg_gen_movi_tl(cpu_Tf
, 0x01);
2702 tcg_gen_movi_tl(cpu_If
, 0x01);
2710 * Clears a single Flag in SREG.
2712 static bool trans_BCLR(DisasContext
*ctx
, arg_BCLR
*a
)
2716 tcg_gen_movi_tl(cpu_Cf
, 0x00);
2719 tcg_gen_movi_tl(cpu_Zf
, 0x00);
2722 tcg_gen_movi_tl(cpu_Nf
, 0x00);
2725 tcg_gen_movi_tl(cpu_Vf
, 0x00);
2728 tcg_gen_movi_tl(cpu_Sf
, 0x00);
2731 tcg_gen_movi_tl(cpu_Hf
, 0x00);
2734 tcg_gen_movi_tl(cpu_Tf
, 0x00);
2737 tcg_gen_movi_tl(cpu_If
, 0x00);
2745 * MCU Control Instructions
2749 * The BREAK instruction is used by the On-chip Debug system, and is
2750 * normally not used in the application software. When the BREAK instruction is
2751 * executed, the AVR CPU is set in the Stopped Mode. This gives the On-chip
2752 * Debugger access to internal resources. If any Lock bits are set, or either
2753 * the JTAGEN or OCDEN Fuses are unprogrammed, the CPU will treat the BREAK
2754 * instruction as a NOP and will not enter the Stopped mode. This instruction
2755 * is not available in all devices. Refer to the device specific instruction
2758 static bool trans_BREAK(DisasContext
*ctx
, arg_BREAK
*a
)
2760 if (!avr_have_feature(ctx
, AVR_FEATURE_BREAK
)) {
2764 #ifdef BREAKPOINT_ON_BREAK
2765 tcg_gen_movi_tl(cpu_pc
, ctx
->npc
- 1);
2766 gen_helper_debug(cpu_env
);
2767 ctx
->bstate
= DISAS_EXIT
;
2776 * This instruction performs a single cycle No Operation.
2778 static bool trans_NOP(DisasContext
*ctx
, arg_NOP
*a
)
2787 * This instruction sets the circuit in sleep mode defined by the MCU
2790 static bool trans_SLEEP(DisasContext
*ctx
, arg_SLEEP
*a
)
2792 gen_helper_sleep(cpu_env
);
2793 ctx
->bstate
= DISAS_NORETURN
;
2798 * This instruction resets the Watchdog Timer. This instruction must be
2799 * executed within a limited time given by the WD prescaler. See the Watchdog
2800 * Timer hardware specification.
2802 static bool trans_WDR(DisasContext
*ctx
, arg_WDR
*a
)
2804 gen_helper_wdr(cpu_env
);