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git.proxmox.com Git - mirror_qemu.git/blob - target/hexagon/genptr.c
2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "qemu/osdep.h"
22 #include "tcg/tcg-op.h"
25 #include "translate.h"
26 #define QEMU_GENERATE /* Used internally by macros.h */
31 static inline TCGv
gen_read_preg(TCGv pred
, uint8_t num
)
33 tcg_gen_mov_tl(pred
, hex_pred
[num
]);
37 static inline void gen_log_predicated_reg_write(int rnum
, TCGv val
, int slot
)
39 TCGv zero
= tcg_const_tl(0);
40 TCGv slot_mask
= tcg_temp_new();
42 tcg_gen_andi_tl(slot_mask
, hex_slot_cancelled
, 1 << slot
);
43 tcg_gen_movcond_tl(TCG_COND_EQ
, hex_new_value
[rnum
], slot_mask
, zero
,
44 val
, hex_new_value
[rnum
]);
47 * Do this so HELPER(debug_commit_end) will know
49 * Note that slot_mask indicates the value is not written
50 * (i.e., slot was cancelled), so we create a true/false value before
51 * or'ing with hex_reg_written[rnum].
53 tcg_gen_setcond_tl(TCG_COND_EQ
, slot_mask
, slot_mask
, zero
);
54 tcg_gen_or_tl(hex_reg_written
[rnum
], hex_reg_written
[rnum
], slot_mask
);
58 tcg_temp_free(slot_mask
);
61 static inline void gen_log_reg_write(int rnum
, TCGv val
)
63 tcg_gen_mov_tl(hex_new_value
[rnum
], val
);
65 /* Do this so HELPER(debug_commit_end) will know */
66 tcg_gen_movi_tl(hex_reg_written
[rnum
], 1);
70 static void gen_log_predicated_reg_write_pair(int rnum
, TCGv_i64 val
, int slot
)
72 TCGv val32
= tcg_temp_new();
73 TCGv zero
= tcg_const_tl(0);
74 TCGv slot_mask
= tcg_temp_new();
76 tcg_gen_andi_tl(slot_mask
, hex_slot_cancelled
, 1 << slot
);
78 tcg_gen_extrl_i64_i32(val32
, val
);
79 tcg_gen_movcond_tl(TCG_COND_EQ
, hex_new_value
[rnum
],
81 val32
, hex_new_value
[rnum
]);
83 tcg_gen_extrh_i64_i32(val32
, val
);
84 tcg_gen_movcond_tl(TCG_COND_EQ
, hex_new_value
[rnum
+ 1],
86 val32
, hex_new_value
[rnum
+ 1]);
89 * Do this so HELPER(debug_commit_end) will know
91 * Note that slot_mask indicates the value is not written
92 * (i.e., slot was cancelled), so we create a true/false value before
93 * or'ing with hex_reg_written[rnum].
95 tcg_gen_setcond_tl(TCG_COND_EQ
, slot_mask
, slot_mask
, zero
);
96 tcg_gen_or_tl(hex_reg_written
[rnum
], hex_reg_written
[rnum
], slot_mask
);
97 tcg_gen_or_tl(hex_reg_written
[rnum
+ 1], hex_reg_written
[rnum
+ 1],
101 tcg_temp_free(val32
);
103 tcg_temp_free(slot_mask
);
106 static void gen_log_reg_write_pair(int rnum
, TCGv_i64 val
)
109 tcg_gen_extrl_i64_i32(hex_new_value
[rnum
], val
);
111 /* Do this so HELPER(debug_commit_end) will know */
112 tcg_gen_movi_tl(hex_reg_written
[rnum
], 1);
116 tcg_gen_extrh_i64_i32(hex_new_value
[rnum
+ 1], val
);
118 /* Do this so HELPER(debug_commit_end) will know */
119 tcg_gen_movi_tl(hex_reg_written
[rnum
+ 1], 1);
123 static inline void gen_log_pred_write(DisasContext
*ctx
, int pnum
, TCGv val
)
125 TCGv zero
= tcg_const_tl(0);
126 TCGv base_val
= tcg_temp_new();
127 TCGv and_val
= tcg_temp_new();
128 TCGv pred_written
= tcg_temp_new();
130 tcg_gen_andi_tl(base_val
, val
, 0xff);
133 * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual
135 * Multiple writes to the same preg are and'ed together
136 * If this is the first predicate write in the packet, do a
137 * straight assignment. Otherwise, do an and.
139 if (!test_bit(pnum
, ctx
->pregs_written
)) {
140 tcg_gen_mov_tl(hex_new_pred_value
[pnum
], base_val
);
142 tcg_gen_and_tl(hex_new_pred_value
[pnum
],
143 hex_new_pred_value
[pnum
], base_val
);
145 tcg_gen_ori_tl(hex_pred_written
, hex_pred_written
, 1 << pnum
);
148 tcg_temp_free(base_val
);
149 tcg_temp_free(and_val
);
150 tcg_temp_free(pred_written
);
153 static inline void gen_read_p3_0(TCGv control_reg
)
155 tcg_gen_movi_tl(control_reg
, 0);
156 for (int i
= 0; i
< NUM_PREGS
; i
++) {
157 tcg_gen_deposit_tl(control_reg
, control_reg
, hex_pred
[i
], i
* 8, 8);
162 * Certain control registers require special handling on read
163 * HEX_REG_P3_0 aliased to the predicate registers
164 * -> concat the 4 predicate registers together
165 * HEX_REG_PC actual value stored in DisasContext
166 * -> assign from ctx->base.pc_next
167 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
168 * -> add current TB changes to existing reg value
170 static inline void gen_read_ctrl_reg(DisasContext
*ctx
, const int reg_num
,
173 if (reg_num
== HEX_REG_P3_0
) {
175 } else if (reg_num
== HEX_REG_PC
) {
176 tcg_gen_movi_tl(dest
, ctx
->base
.pc_next
);
177 } else if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
178 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
180 } else if (reg_num
== HEX_REG_QEMU_INSN_CNT
) {
181 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
184 tcg_gen_mov_tl(dest
, hex_gpr
[reg_num
]);
188 static inline void gen_read_ctrl_reg_pair(DisasContext
*ctx
, const int reg_num
,
191 if (reg_num
== HEX_REG_P3_0
) {
192 TCGv p3_0
= tcg_temp_new();
194 tcg_gen_concat_i32_i64(dest
, p3_0
, hex_gpr
[reg_num
+ 1]);
196 } else if (reg_num
== HEX_REG_PC
- 1) {
197 TCGv pc
= tcg_const_tl(ctx
->base
.pc_next
);
198 tcg_gen_concat_i32_i64(dest
, hex_gpr
[reg_num
], pc
);
200 } else if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
201 TCGv pkt_cnt
= tcg_temp_new();
202 TCGv insn_cnt
= tcg_temp_new();
203 tcg_gen_addi_tl(pkt_cnt
, hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
205 tcg_gen_addi_tl(insn_cnt
, hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
207 tcg_gen_concat_i32_i64(dest
, pkt_cnt
, insn_cnt
);
208 tcg_temp_free(pkt_cnt
);
209 tcg_temp_free(insn_cnt
);
211 tcg_gen_concat_i32_i64(dest
,
213 hex_gpr
[reg_num
+ 1]);
217 static inline void gen_write_p3_0(TCGv control_reg
)
219 for (int i
= 0; i
< NUM_PREGS
; i
++) {
220 tcg_gen_extract_tl(hex_pred
[i
], control_reg
, i
* 8, 8);
225 * Certain control registers require special handling on write
226 * HEX_REG_P3_0 aliased to the predicate registers
227 * -> break the value across 4 predicate registers
228 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
229 * -> clear the changes
231 static inline void gen_write_ctrl_reg(DisasContext
*ctx
, int reg_num
,
234 if (reg_num
== HEX_REG_P3_0
) {
237 gen_log_reg_write(reg_num
, val
);
238 ctx_log_reg_write(ctx
, reg_num
);
239 if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
240 ctx
->num_packets
= 0;
242 if (reg_num
== HEX_REG_QEMU_INSN_CNT
) {
248 static inline void gen_write_ctrl_reg_pair(DisasContext
*ctx
, int reg_num
,
251 if (reg_num
== HEX_REG_P3_0
) {
252 TCGv val32
= tcg_temp_new();
253 tcg_gen_extrl_i64_i32(val32
, val
);
254 gen_write_p3_0(val32
);
255 tcg_gen_extrh_i64_i32(val32
, val
);
256 gen_log_reg_write(reg_num
+ 1, val32
);
257 tcg_temp_free(val32
);
258 ctx_log_reg_write(ctx
, reg_num
+ 1);
260 gen_log_reg_write_pair(reg_num
, val
);
261 ctx_log_reg_write_pair(ctx
, reg_num
);
262 if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
263 ctx
->num_packets
= 0;
269 static TCGv
gen_get_byte_i64(TCGv result
, int N
, TCGv_i64 src
, bool sign
)
271 TCGv_i64 res64
= tcg_temp_new_i64();
273 tcg_gen_sextract_i64(res64
, src
, N
* 8, 8);
275 tcg_gen_extract_i64(res64
, src
, N
* 8, 8);
277 tcg_gen_extrl_i64_i32(result
, res64
);
278 tcg_temp_free_i64(res64
);
283 static void gen_set_byte_i64(int N
, TCGv_i64 result
, TCGv src
)
285 TCGv_i64 src64
= tcg_temp_new_i64();
286 tcg_gen_extu_i32_i64(src64
, src
);
287 tcg_gen_deposit_i64(result
, result
, src64
, N
* 8, 8);
288 tcg_temp_free_i64(src64
);
291 static inline void gen_load_locked4u(TCGv dest
, TCGv vaddr
, int mem_index
)
293 tcg_gen_qemu_ld32u(dest
, vaddr
, mem_index
);
294 tcg_gen_mov_tl(hex_llsc_addr
, vaddr
);
295 tcg_gen_mov_tl(hex_llsc_val
, dest
);
298 static inline void gen_load_locked8u(TCGv_i64 dest
, TCGv vaddr
, int mem_index
)
300 tcg_gen_qemu_ld64(dest
, vaddr
, mem_index
);
301 tcg_gen_mov_tl(hex_llsc_addr
, vaddr
);
302 tcg_gen_mov_i64(hex_llsc_val_i64
, dest
);
305 static inline void gen_store_conditional4(CPUHexagonState
*env
,
306 DisasContext
*ctx
, int prednum
,
307 TCGv pred
, TCGv vaddr
, TCGv src
)
309 TCGLabel
*fail
= gen_new_label();
310 TCGLabel
*done
= gen_new_label();
313 tcg_gen_brcond_tl(TCG_COND_NE
, vaddr
, hex_llsc_addr
, fail
);
315 one
= tcg_const_tl(0xff);
316 zero
= tcg_const_tl(0);
317 tmp
= tcg_temp_new();
318 tcg_gen_atomic_cmpxchg_tl(tmp
, hex_llsc_addr
, hex_llsc_val
, src
,
319 ctx
->mem_idx
, MO_32
);
320 tcg_gen_movcond_tl(TCG_COND_EQ
, hex_pred
[prednum
], tmp
, hex_llsc_val
,
328 tcg_gen_movi_tl(pred
, 0);
331 tcg_gen_movi_tl(hex_llsc_addr
, ~0);
334 static inline void gen_store_conditional8(CPUHexagonState
*env
,
335 DisasContext
*ctx
, int prednum
,
336 TCGv pred
, TCGv vaddr
, TCGv_i64 src
)
338 TCGLabel
*fail
= gen_new_label();
339 TCGLabel
*done
= gen_new_label();
340 TCGv_i64 one
, zero
, tmp
;
342 tcg_gen_brcond_tl(TCG_COND_NE
, vaddr
, hex_llsc_addr
, fail
);
344 one
= tcg_const_i64(0xff);
345 zero
= tcg_const_i64(0);
346 tmp
= tcg_temp_new_i64();
347 tcg_gen_atomic_cmpxchg_i64(tmp
, hex_llsc_addr
, hex_llsc_val_i64
, src
,
348 ctx
->mem_idx
, MO_64
);
349 tcg_gen_movcond_i64(TCG_COND_EQ
, tmp
, tmp
, hex_llsc_val_i64
,
351 tcg_gen_extrl_i64_i32(hex_pred
[prednum
], tmp
);
352 tcg_temp_free_i64(one
);
353 tcg_temp_free_i64(zero
);
354 tcg_temp_free_i64(tmp
);
358 tcg_gen_movi_tl(pred
, 0);
361 tcg_gen_movi_tl(hex_llsc_addr
, ~0);
364 #include "tcg_funcs_generated.c.inc"
365 #include "tcg_func_table_generated.c.inc"