2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "qemu/osdep.h"
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
25 #include "translate.h"
26 #define QEMU_GENERATE /* Used internally by macros.h */
28 #include "mmvec/macros.h"
31 #include "gen_tcg_hvx.h"
34 TCGv
gen_read_reg(TCGv result
, int num
)
36 tcg_gen_mov_tl(result
, hex_gpr
[num
]);
40 TCGv
gen_read_preg(TCGv pred
, uint8_t num
)
42 tcg_gen_mov_tl(pred
, hex_pred
[num
]);
46 #define IMMUTABLE (~0)
48 static const target_ulong reg_immut_masks
[TOTAL_PER_THREAD_REGS
] = {
49 [HEX_REG_USR
] = 0xc13000c0,
50 [HEX_REG_PC
] = IMMUTABLE
,
52 [HEX_REG_UPCYCLELO
] = IMMUTABLE
,
53 [HEX_REG_UPCYCLEHI
] = IMMUTABLE
,
54 [HEX_REG_UTIMERLO
] = IMMUTABLE
,
55 [HEX_REG_UTIMERHI
] = IMMUTABLE
,
58 static inline void gen_masked_reg_write(TCGv new_val
, TCGv cur_val
,
59 target_ulong reg_mask
)
62 TCGv tmp
= tcg_temp_new();
64 /* new_val = (new_val & ~reg_mask) | (cur_val & reg_mask) */
65 tcg_gen_andi_tl(new_val
, new_val
, ~reg_mask
);
66 tcg_gen_andi_tl(tmp
, cur_val
, reg_mask
);
67 tcg_gen_or_tl(new_val
, new_val
, tmp
);
71 static inline void gen_log_predicated_reg_write(int rnum
, TCGv val
,
74 TCGv zero
= tcg_constant_tl(0);
75 TCGv slot_mask
= tcg_temp_new();
77 tcg_gen_andi_tl(slot_mask
, hex_slot_cancelled
, 1 << slot
);
78 tcg_gen_movcond_tl(TCG_COND_EQ
, hex_new_value
[rnum
], slot_mask
, zero
,
79 val
, hex_new_value
[rnum
]);
82 * Do this so HELPER(debug_commit_end) will know
84 * Note that slot_mask indicates the value is not written
85 * (i.e., slot was cancelled), so we create a true/false value before
86 * or'ing with hex_reg_written[rnum].
88 tcg_gen_setcond_tl(TCG_COND_EQ
, slot_mask
, slot_mask
, zero
);
89 tcg_gen_or_tl(hex_reg_written
[rnum
], hex_reg_written
[rnum
], slot_mask
);
93 void gen_log_reg_write(int rnum
, TCGv val
)
95 const target_ulong reg_mask
= reg_immut_masks
[rnum
];
97 gen_masked_reg_write(val
, hex_gpr
[rnum
], reg_mask
);
98 tcg_gen_mov_tl(hex_new_value
[rnum
], val
);
100 /* Do this so HELPER(debug_commit_end) will know */
101 tcg_gen_movi_tl(hex_reg_written
[rnum
], 1);
105 static void gen_log_predicated_reg_write_pair(int rnum
, TCGv_i64 val
,
108 TCGv val32
= tcg_temp_new();
109 TCGv zero
= tcg_constant_tl(0);
110 TCGv slot_mask
= tcg_temp_new();
112 tcg_gen_andi_tl(slot_mask
, hex_slot_cancelled
, 1 << slot
);
114 tcg_gen_extrl_i64_i32(val32
, val
);
115 tcg_gen_movcond_tl(TCG_COND_EQ
, hex_new_value
[rnum
],
117 val32
, hex_new_value
[rnum
]);
119 tcg_gen_extrh_i64_i32(val32
, val
);
120 tcg_gen_movcond_tl(TCG_COND_EQ
, hex_new_value
[rnum
+ 1],
122 val32
, hex_new_value
[rnum
+ 1]);
125 * Do this so HELPER(debug_commit_end) will know
127 * Note that slot_mask indicates the value is not written
128 * (i.e., slot was cancelled), so we create a true/false value before
129 * or'ing with hex_reg_written[rnum].
131 tcg_gen_setcond_tl(TCG_COND_EQ
, slot_mask
, slot_mask
, zero
);
132 tcg_gen_or_tl(hex_reg_written
[rnum
], hex_reg_written
[rnum
], slot_mask
);
133 tcg_gen_or_tl(hex_reg_written
[rnum
+ 1], hex_reg_written
[rnum
+ 1],
138 static void gen_log_reg_write_pair(int rnum
, TCGv_i64 val
)
140 const target_ulong reg_mask_low
= reg_immut_masks
[rnum
];
141 const target_ulong reg_mask_high
= reg_immut_masks
[rnum
+ 1];
142 TCGv val32
= tcg_temp_new();
145 tcg_gen_extrl_i64_i32(val32
, val
);
146 gen_masked_reg_write(val32
, hex_gpr
[rnum
], reg_mask_low
);
147 tcg_gen_mov_tl(hex_new_value
[rnum
], val32
);
149 /* Do this so HELPER(debug_commit_end) will know */
150 tcg_gen_movi_tl(hex_reg_written
[rnum
], 1);
154 tcg_gen_extrh_i64_i32(val32
, val
);
155 gen_masked_reg_write(val32
, hex_gpr
[rnum
+ 1], reg_mask_high
);
156 tcg_gen_mov_tl(hex_new_value
[rnum
+ 1], val32
);
158 /* Do this so HELPER(debug_commit_end) will know */
159 tcg_gen_movi_tl(hex_reg_written
[rnum
+ 1], 1);
163 void gen_log_pred_write(DisasContext
*ctx
, int pnum
, TCGv val
)
165 TCGv base_val
= tcg_temp_new();
167 tcg_gen_andi_tl(base_val
, val
, 0xff);
170 * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual
172 * Multiple writes to the same preg are and'ed together
173 * If this is the first predicate write in the packet, do a
174 * straight assignment. Otherwise, do an and.
176 if (!test_bit(pnum
, ctx
->pregs_written
)) {
177 tcg_gen_mov_tl(hex_new_pred_value
[pnum
], base_val
);
179 tcg_gen_and_tl(hex_new_pred_value
[pnum
],
180 hex_new_pred_value
[pnum
], base_val
);
182 tcg_gen_ori_tl(hex_pred_written
, hex_pred_written
, 1 << pnum
);
183 set_bit(pnum
, ctx
->pregs_written
);
186 static inline void gen_read_p3_0(TCGv control_reg
)
188 tcg_gen_movi_tl(control_reg
, 0);
189 for (int i
= 0; i
< NUM_PREGS
; i
++) {
190 tcg_gen_deposit_tl(control_reg
, control_reg
, hex_pred
[i
], i
* 8, 8);
195 * Certain control registers require special handling on read
196 * HEX_REG_P3_0_ALIASED aliased to the predicate registers
197 * -> concat the 4 predicate registers together
198 * HEX_REG_PC actual value stored in DisasContext
199 * -> assign from ctx->base.pc_next
200 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
201 * -> add current TB changes to existing reg value
203 static inline void gen_read_ctrl_reg(DisasContext
*ctx
, const int reg_num
,
206 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
208 } else if (reg_num
== HEX_REG_PC
) {
209 tcg_gen_movi_tl(dest
, ctx
->base
.pc_next
);
210 } else if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
211 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
213 } else if (reg_num
== HEX_REG_QEMU_INSN_CNT
) {
214 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
216 } else if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
217 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_HVX_CNT
],
220 tcg_gen_mov_tl(dest
, hex_gpr
[reg_num
]);
224 static inline void gen_read_ctrl_reg_pair(DisasContext
*ctx
, const int reg_num
,
227 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
228 TCGv p3_0
= tcg_temp_new();
230 tcg_gen_concat_i32_i64(dest
, p3_0
, hex_gpr
[reg_num
+ 1]);
231 } else if (reg_num
== HEX_REG_PC
- 1) {
232 TCGv pc
= tcg_constant_tl(ctx
->base
.pc_next
);
233 tcg_gen_concat_i32_i64(dest
, hex_gpr
[reg_num
], pc
);
234 } else if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
235 TCGv pkt_cnt
= tcg_temp_new();
236 TCGv insn_cnt
= tcg_temp_new();
237 tcg_gen_addi_tl(pkt_cnt
, hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
239 tcg_gen_addi_tl(insn_cnt
, hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
241 tcg_gen_concat_i32_i64(dest
, pkt_cnt
, insn_cnt
);
242 } else if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
243 TCGv hvx_cnt
= tcg_temp_new();
244 tcg_gen_addi_tl(hvx_cnt
, hex_gpr
[HEX_REG_QEMU_HVX_CNT
],
246 tcg_gen_concat_i32_i64(dest
, hvx_cnt
, hex_gpr
[reg_num
+ 1]);
248 tcg_gen_concat_i32_i64(dest
,
250 hex_gpr
[reg_num
+ 1]);
254 static void gen_write_p3_0(DisasContext
*ctx
, TCGv control_reg
)
256 TCGv hex_p8
= tcg_temp_new();
257 for (int i
= 0; i
< NUM_PREGS
; i
++) {
258 tcg_gen_extract_tl(hex_p8
, control_reg
, i
* 8, 8);
259 gen_log_pred_write(ctx
, i
, hex_p8
);
264 * Certain control registers require special handling on write
265 * HEX_REG_P3_0_ALIASED aliased to the predicate registers
266 * -> break the value across 4 predicate registers
267 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
268 * -> clear the changes
270 static inline void gen_write_ctrl_reg(DisasContext
*ctx
, int reg_num
,
273 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
274 gen_write_p3_0(ctx
, val
);
276 gen_log_reg_write(reg_num
, val
);
277 if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
278 ctx
->num_packets
= 0;
280 if (reg_num
== HEX_REG_QEMU_INSN_CNT
) {
283 if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
284 ctx
->num_hvx_insns
= 0;
289 static inline void gen_write_ctrl_reg_pair(DisasContext
*ctx
, int reg_num
,
292 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
293 TCGv val32
= tcg_temp_new();
294 tcg_gen_extrl_i64_i32(val32
, val
);
295 gen_write_p3_0(ctx
, val32
);
296 tcg_gen_extrh_i64_i32(val32
, val
);
297 gen_log_reg_write(reg_num
+ 1, val32
);
299 gen_log_reg_write_pair(reg_num
, val
);
300 if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
301 ctx
->num_packets
= 0;
304 if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
305 ctx
->num_hvx_insns
= 0;
310 TCGv
gen_get_byte(TCGv result
, int N
, TCGv src
, bool sign
)
313 tcg_gen_sextract_tl(result
, src
, N
* 8, 8);
315 tcg_gen_extract_tl(result
, src
, N
* 8, 8);
320 TCGv
gen_get_byte_i64(TCGv result
, int N
, TCGv_i64 src
, bool sign
)
322 TCGv_i64 res64
= tcg_temp_new_i64();
324 tcg_gen_sextract_i64(res64
, src
, N
* 8, 8);
326 tcg_gen_extract_i64(res64
, src
, N
* 8, 8);
328 tcg_gen_extrl_i64_i32(result
, res64
);
333 TCGv
gen_get_half(TCGv result
, int N
, TCGv src
, bool sign
)
336 tcg_gen_sextract_tl(result
, src
, N
* 16, 16);
338 tcg_gen_extract_tl(result
, src
, N
* 16, 16);
343 void gen_set_half(int N
, TCGv result
, TCGv src
)
345 tcg_gen_deposit_tl(result
, result
, src
, N
* 16, 16);
348 void gen_set_half_i64(int N
, TCGv_i64 result
, TCGv src
)
350 TCGv_i64 src64
= tcg_temp_new_i64();
351 tcg_gen_extu_i32_i64(src64
, src
);
352 tcg_gen_deposit_i64(result
, result
, src64
, N
* 16, 16);
355 void gen_set_byte_i64(int N
, TCGv_i64 result
, TCGv src
)
357 TCGv_i64 src64
= tcg_temp_new_i64();
358 tcg_gen_extu_i32_i64(src64
, src
);
359 tcg_gen_deposit_i64(result
, result
, src64
, N
* 8, 8);
362 static inline void gen_load_locked4u(TCGv dest
, TCGv vaddr
, int mem_index
)
364 tcg_gen_qemu_ld32u(dest
, vaddr
, mem_index
);
365 tcg_gen_mov_tl(hex_llsc_addr
, vaddr
);
366 tcg_gen_mov_tl(hex_llsc_val
, dest
);
369 static inline void gen_load_locked8u(TCGv_i64 dest
, TCGv vaddr
, int mem_index
)
371 tcg_gen_qemu_ld64(dest
, vaddr
, mem_index
);
372 tcg_gen_mov_tl(hex_llsc_addr
, vaddr
);
373 tcg_gen_mov_i64(hex_llsc_val_i64
, dest
);
376 static inline void gen_store_conditional4(DisasContext
*ctx
,
377 TCGv pred
, TCGv vaddr
, TCGv src
)
379 TCGLabel
*fail
= gen_new_label();
380 TCGLabel
*done
= gen_new_label();
383 tcg_gen_brcond_tl(TCG_COND_NE
, vaddr
, hex_llsc_addr
, fail
);
385 one
= tcg_constant_tl(0xff);
386 zero
= tcg_constant_tl(0);
387 tmp
= tcg_temp_new();
388 tcg_gen_atomic_cmpxchg_tl(tmp
, hex_llsc_addr
, hex_llsc_val
, src
,
389 ctx
->mem_idx
, MO_32
);
390 tcg_gen_movcond_tl(TCG_COND_EQ
, pred
, tmp
, hex_llsc_val
,
395 tcg_gen_movi_tl(pred
, 0);
398 tcg_gen_movi_tl(hex_llsc_addr
, ~0);
401 static inline void gen_store_conditional8(DisasContext
*ctx
,
402 TCGv pred
, TCGv vaddr
, TCGv_i64 src
)
404 TCGLabel
*fail
= gen_new_label();
405 TCGLabel
*done
= gen_new_label();
406 TCGv_i64 one
, zero
, tmp
;
408 tcg_gen_brcond_tl(TCG_COND_NE
, vaddr
, hex_llsc_addr
, fail
);
410 one
= tcg_constant_i64(0xff);
411 zero
= tcg_constant_i64(0);
412 tmp
= tcg_temp_new_i64();
413 tcg_gen_atomic_cmpxchg_i64(tmp
, hex_llsc_addr
, hex_llsc_val_i64
, src
,
414 ctx
->mem_idx
, MO_64
);
415 tcg_gen_movcond_i64(TCG_COND_EQ
, tmp
, tmp
, hex_llsc_val_i64
,
417 tcg_gen_extrl_i64_i32(pred
, tmp
);
421 tcg_gen_movi_tl(pred
, 0);
424 tcg_gen_movi_tl(hex_llsc_addr
, ~0);
427 void gen_store32(TCGv vaddr
, TCGv src
, int width
, uint32_t slot
)
429 tcg_gen_mov_tl(hex_store_addr
[slot
], vaddr
);
430 tcg_gen_movi_tl(hex_store_width
[slot
], width
);
431 tcg_gen_mov_tl(hex_store_val32
[slot
], src
);
434 void gen_store1(TCGv_env cpu_env
, TCGv vaddr
, TCGv src
, uint32_t slot
)
436 gen_store32(vaddr
, src
, 1, slot
);
439 void gen_store1i(TCGv_env cpu_env
, TCGv vaddr
, int32_t src
, uint32_t slot
)
441 TCGv tmp
= tcg_constant_tl(src
);
442 gen_store1(cpu_env
, vaddr
, tmp
, slot
);
445 void gen_store2(TCGv_env cpu_env
, TCGv vaddr
, TCGv src
, uint32_t slot
)
447 gen_store32(vaddr
, src
, 2, slot
);
450 void gen_store2i(TCGv_env cpu_env
, TCGv vaddr
, int32_t src
, uint32_t slot
)
452 TCGv tmp
= tcg_constant_tl(src
);
453 gen_store2(cpu_env
, vaddr
, tmp
, slot
);
456 void gen_store4(TCGv_env cpu_env
, TCGv vaddr
, TCGv src
, uint32_t slot
)
458 gen_store32(vaddr
, src
, 4, slot
);
461 void gen_store4i(TCGv_env cpu_env
, TCGv vaddr
, int32_t src
, uint32_t slot
)
463 TCGv tmp
= tcg_constant_tl(src
);
464 gen_store4(cpu_env
, vaddr
, tmp
, slot
);
467 void gen_store8(TCGv_env cpu_env
, TCGv vaddr
, TCGv_i64 src
, uint32_t slot
)
469 tcg_gen_mov_tl(hex_store_addr
[slot
], vaddr
);
470 tcg_gen_movi_tl(hex_store_width
[slot
], 8);
471 tcg_gen_mov_i64(hex_store_val64
[slot
], src
);
474 void gen_store8i(TCGv_env cpu_env
, TCGv vaddr
, int64_t src
, uint32_t slot
)
476 TCGv_i64 tmp
= tcg_constant_i64(src
);
477 gen_store8(cpu_env
, vaddr
, tmp
, slot
);
480 TCGv
gen_8bitsof(TCGv result
, TCGv value
)
482 TCGv zero
= tcg_constant_tl(0);
483 TCGv ones
= tcg_constant_tl(0xff);
484 tcg_gen_movcond_tl(TCG_COND_NE
, result
, value
, zero
, ones
, zero
);
489 static void gen_write_new_pc_addr(DisasContext
*ctx
, TCGv addr
,
490 TCGCond cond
, TCGv pred
)
492 TCGLabel
*pred_false
= NULL
;
493 if (cond
!= TCG_COND_ALWAYS
) {
494 pred_false
= gen_new_label();
495 tcg_gen_brcondi_tl(cond
, pred
, 0, pred_false
);
498 if (ctx
->pkt
->pkt_has_multi_cof
) {
499 /* If there are multiple branches in a packet, ignore the second one */
500 tcg_gen_movcond_tl(TCG_COND_NE
, hex_gpr
[HEX_REG_PC
],
501 hex_branch_taken
, tcg_constant_tl(0),
502 hex_gpr
[HEX_REG_PC
], addr
);
503 tcg_gen_movi_tl(hex_branch_taken
, 1);
505 tcg_gen_mov_tl(hex_gpr
[HEX_REG_PC
], addr
);
508 if (cond
!= TCG_COND_ALWAYS
) {
509 gen_set_label(pred_false
);
513 static void gen_write_new_pc_pcrel(DisasContext
*ctx
, int pc_off
,
514 TCGCond cond
, TCGv pred
)
516 target_ulong dest
= ctx
->pkt
->pc
+ pc_off
;
517 if (ctx
->pkt
->pkt_has_multi_cof
) {
518 gen_write_new_pc_addr(ctx
, tcg_constant_tl(dest
), cond
, pred
);
520 /* Defer this jump to the end of the TB */
521 ctx
->branch_cond
= TCG_COND_ALWAYS
;
523 ctx
->branch_cond
= cond
;
524 tcg_gen_mov_tl(hex_branch_taken
, pred
);
526 ctx
->branch_dest
= dest
;
530 void gen_set_usr_field(int field
, TCGv val
)
532 tcg_gen_deposit_tl(hex_new_value
[HEX_REG_USR
], hex_new_value
[HEX_REG_USR
],
534 reg_field_info
[field
].offset
,
535 reg_field_info
[field
].width
);
538 void gen_set_usr_fieldi(int field
, int x
)
540 if (reg_field_info
[field
].width
== 1) {
541 target_ulong bit
= 1 << reg_field_info
[field
].offset
;
543 tcg_gen_ori_tl(hex_new_value
[HEX_REG_USR
],
544 hex_new_value
[HEX_REG_USR
],
547 tcg_gen_andi_tl(hex_new_value
[HEX_REG_USR
],
548 hex_new_value
[HEX_REG_USR
],
552 TCGv val
= tcg_constant_tl(x
);
553 gen_set_usr_field(field
, val
);
557 static void gen_compare(TCGCond cond
, TCGv res
, TCGv arg1
, TCGv arg2
)
559 TCGv one
= tcg_constant_tl(0xff);
560 TCGv zero
= tcg_constant_tl(0);
562 tcg_gen_movcond_tl(cond
, res
, arg1
, arg2
, one
, zero
);
565 static void gen_cond_jumpr(DisasContext
*ctx
, TCGv dst_pc
,
566 TCGCond cond
, TCGv pred
)
568 gen_write_new_pc_addr(ctx
, dst_pc
, cond
, pred
);
571 static void gen_cond_jumpr31(DisasContext
*ctx
, TCGCond cond
, TCGv pred
)
573 TCGv LSB
= tcg_temp_new();
574 tcg_gen_andi_tl(LSB
, pred
, 1);
575 gen_cond_jumpr(ctx
, hex_gpr
[HEX_REG_LR
], cond
, LSB
);
578 static void gen_cond_jump(DisasContext
*ctx
, TCGCond cond
, TCGv pred
,
581 gen_write_new_pc_pcrel(ctx
, pc_off
, cond
, pred
);
584 static void gen_cmpnd_cmp_jmp(DisasContext
*ctx
,
585 int pnum
, TCGCond cond1
, TCGv arg1
, TCGv arg2
,
586 TCGCond cond2
, int pc_off
)
588 if (ctx
->insn
->part1
) {
589 TCGv pred
= tcg_temp_new();
590 gen_compare(cond1
, pred
, arg1
, arg2
);
591 gen_log_pred_write(ctx
, pnum
, pred
);
593 TCGv pred
= tcg_temp_new();
594 tcg_gen_mov_tl(pred
, hex_new_pred_value
[pnum
]);
595 gen_cond_jump(ctx
, cond2
, pred
, pc_off
);
599 static void gen_cmpnd_cmp_jmp_t(DisasContext
*ctx
,
600 int pnum
, TCGCond cond
, TCGv arg1
, TCGv arg2
,
603 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, arg2
, TCG_COND_EQ
, pc_off
);
606 static void gen_cmpnd_cmp_jmp_f(DisasContext
*ctx
,
607 int pnum
, TCGCond cond
, TCGv arg1
, TCGv arg2
,
610 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, arg2
, TCG_COND_NE
, pc_off
);
613 static void gen_cmpnd_cmpi_jmp_t(DisasContext
*ctx
,
614 int pnum
, TCGCond cond
, TCGv arg1
, int arg2
,
617 TCGv tmp
= tcg_constant_tl(arg2
);
618 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, tmp
, TCG_COND_EQ
, pc_off
);
621 static void gen_cmpnd_cmpi_jmp_f(DisasContext
*ctx
,
622 int pnum
, TCGCond cond
, TCGv arg1
, int arg2
,
625 TCGv tmp
= tcg_constant_tl(arg2
);
626 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, tmp
, TCG_COND_NE
, pc_off
);
629 static void gen_cmpnd_cmp_n1_jmp_t(DisasContext
*ctx
, int pnum
, TCGCond cond
,
630 TCGv arg
, int pc_off
)
632 gen_cmpnd_cmpi_jmp_t(ctx
, pnum
, cond
, arg
, -1, pc_off
);
635 static void gen_cmpnd_cmp_n1_jmp_f(DisasContext
*ctx
, int pnum
, TCGCond cond
,
636 TCGv arg
, int pc_off
)
638 gen_cmpnd_cmpi_jmp_f(ctx
, pnum
, cond
, arg
, -1, pc_off
);
641 static void gen_cmpnd_tstbit0_jmp(DisasContext
*ctx
,
642 int pnum
, TCGv arg
, TCGCond cond
, int pc_off
)
644 if (ctx
->insn
->part1
) {
645 TCGv pred
= tcg_temp_new();
646 tcg_gen_andi_tl(pred
, arg
, 1);
647 gen_8bitsof(pred
, pred
);
648 gen_log_pred_write(ctx
, pnum
, pred
);
650 TCGv pred
= tcg_temp_new();
651 tcg_gen_mov_tl(pred
, hex_new_pred_value
[pnum
]);
652 gen_cond_jump(ctx
, cond
, pred
, pc_off
);
656 static void gen_testbit0_jumpnv(DisasContext
*ctx
,
657 TCGv arg
, TCGCond cond
, int pc_off
)
659 TCGv pred
= tcg_temp_new();
660 tcg_gen_andi_tl(pred
, arg
, 1);
661 gen_cond_jump(ctx
, cond
, pred
, pc_off
);
664 static void gen_jump(DisasContext
*ctx
, int pc_off
)
666 gen_write_new_pc_pcrel(ctx
, pc_off
, TCG_COND_ALWAYS
, NULL
);
669 static void gen_jumpr(DisasContext
*ctx
, TCGv new_pc
)
671 gen_write_new_pc_addr(ctx
, new_pc
, TCG_COND_ALWAYS
, NULL
);
674 static void gen_call(DisasContext
*ctx
, int pc_off
)
677 tcg_constant_tl(ctx
->pkt
->pc
+ ctx
->pkt
->encod_pkt_size_in_bytes
);
678 gen_log_reg_write(HEX_REG_LR
, next_PC
);
679 gen_write_new_pc_pcrel(ctx
, pc_off
, TCG_COND_ALWAYS
, NULL
);
682 static void gen_callr(DisasContext
*ctx
, TCGv new_pc
)
684 TCGv next_PC
= tcg_constant_tl(ctx
->next_PC
);
685 gen_log_reg_write(HEX_REG_LR
, next_PC
);
686 gen_write_new_pc_addr(ctx
, new_pc
, TCG_COND_ALWAYS
, NULL
);
689 static void gen_cond_call(DisasContext
*ctx
, TCGv pred
,
690 TCGCond cond
, int pc_off
)
693 TCGv lsb
= tcg_temp_new();
694 TCGLabel
*skip
= gen_new_label();
695 tcg_gen_andi_tl(lsb
, pred
, 1);
696 gen_write_new_pc_pcrel(ctx
, pc_off
, cond
, lsb
);
697 tcg_gen_brcondi_tl(cond
, lsb
, 0, skip
);
699 tcg_constant_tl(ctx
->pkt
->pc
+ ctx
->pkt
->encod_pkt_size_in_bytes
);
700 gen_log_reg_write(HEX_REG_LR
, next_PC
);
704 static void gen_cond_callr(DisasContext
*ctx
,
705 TCGCond cond
, TCGv pred
, TCGv new_pc
)
707 TCGv lsb
= tcg_temp_new();
708 TCGLabel
*skip
= gen_new_label();
709 tcg_gen_andi_tl(lsb
, pred
, 1);
710 tcg_gen_brcondi_tl(cond
, lsb
, 0, skip
);
711 gen_callr(ctx
, new_pc
);
715 /* frame ^= (int64_t)FRAMEKEY << 32 */
716 static void gen_frame_unscramble(TCGv_i64 frame
)
718 TCGv_i64 framekey
= tcg_temp_new_i64();
719 tcg_gen_extu_i32_i64(framekey
, hex_gpr
[HEX_REG_FRAMEKEY
]);
720 tcg_gen_shli_i64(framekey
, framekey
, 32);
721 tcg_gen_xor_i64(frame
, frame
, framekey
);
724 static void gen_load_frame(DisasContext
*ctx
, TCGv_i64 frame
, TCGv EA
)
726 Insn
*insn
= ctx
->insn
; /* Needed for CHECK_NOSHUF */
728 tcg_gen_qemu_ld64(frame
, EA
, ctx
->mem_idx
);
731 static void gen_return_base(DisasContext
*ctx
, TCGv_i64 dst
, TCGv src
,
736 * dst = frame_unscramble(frame)
740 TCGv_i64 frame
= tcg_temp_new_i64();
741 TCGv r31
= tcg_temp_new();
743 gen_load_frame(ctx
, frame
, src
);
744 gen_frame_unscramble(frame
);
745 tcg_gen_mov_i64(dst
, frame
);
746 tcg_gen_addi_tl(r29
, src
, 8);
747 tcg_gen_extrh_i64_i32(r31
, dst
);
751 static void gen_return(DisasContext
*ctx
, TCGv_i64 dst
, TCGv src
)
753 TCGv r29
= tcg_temp_new();
754 gen_return_base(ctx
, dst
, src
, r29
);
755 gen_log_reg_write(HEX_REG_SP
, r29
);
758 /* if (pred) dst = dealloc_return(src):raw */
759 static void gen_cond_return(DisasContext
*ctx
, TCGv_i64 dst
, TCGv src
,
760 TCGv pred
, TCGCond cond
)
762 TCGv LSB
= tcg_temp_new();
763 TCGv mask
= tcg_temp_new();
764 TCGv r29
= tcg_temp_new();
765 TCGLabel
*skip
= gen_new_label();
766 tcg_gen_andi_tl(LSB
, pred
, 1);
768 /* Initialize the results in case the predicate is false */
769 tcg_gen_movi_i64(dst
, 0);
770 tcg_gen_movi_tl(r29
, 0);
772 /* Set the bit in hex_slot_cancelled if the predicate is flase */
773 tcg_gen_movi_tl(mask
, 1 << ctx
->insn
->slot
);
774 tcg_gen_or_tl(mask
, hex_slot_cancelled
, mask
);
775 tcg_gen_movcond_tl(cond
, hex_slot_cancelled
, LSB
, tcg_constant_tl(0),
776 mask
, hex_slot_cancelled
);
778 tcg_gen_brcondi_tl(cond
, LSB
, 0, skip
);
779 gen_return_base(ctx
, dst
, src
, r29
);
781 gen_log_predicated_reg_write(HEX_REG_SP
, r29
, ctx
->insn
->slot
);
784 /* sub-instruction version (no RddV, so handle it manually) */
785 static void gen_cond_return_subinsn(DisasContext
*ctx
, TCGCond cond
, TCGv pred
)
787 TCGv_i64 RddV
= tcg_temp_new_i64();
788 gen_cond_return(ctx
, RddV
, hex_gpr
[HEX_REG_FP
], pred
, cond
);
789 gen_log_predicated_reg_write_pair(HEX_REG_FP
, RddV
, ctx
->insn
->slot
);
792 static void gen_endloop0(DisasContext
*ctx
)
794 TCGv lpcfg
= tcg_temp_new();
796 GET_USR_FIELD(USR_LPCFG
, lpcfg
);
800 * hex_new_pred_value[3] = 0xff;
801 * hex_pred_written |= 1 << 3;
804 TCGLabel
*label1
= gen_new_label();
805 tcg_gen_brcondi_tl(TCG_COND_NE
, lpcfg
, 1, label1
);
807 tcg_gen_movi_tl(hex_new_pred_value
[3], 0xff);
808 tcg_gen_ori_tl(hex_pred_written
, hex_pred_written
, 1 << 3);
810 gen_set_label(label1
);
814 * SET_USR_FIELD(USR_LPCFG, lpcfg - 1);
817 TCGLabel
*label2
= gen_new_label();
818 tcg_gen_brcondi_tl(TCG_COND_EQ
, lpcfg
, 0, label2
);
820 tcg_gen_subi_tl(lpcfg
, lpcfg
, 1);
821 SET_USR_FIELD(USR_LPCFG
, lpcfg
);
823 gen_set_label(label2
);
826 * If we're in a tight loop, we'll do this at the end of the TB to take
827 * advantage of direct block chaining.
829 if (!ctx
->is_tight_loop
) {
831 * if (hex_gpr[HEX_REG_LC0] > 1) {
832 * PC = hex_gpr[HEX_REG_SA0];
833 * hex_new_value[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1;
836 TCGLabel
*label3
= gen_new_label();
837 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC0
], 1, label3
);
839 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA0
]);
840 tcg_gen_subi_tl(hex_new_value
[HEX_REG_LC0
],
841 hex_gpr
[HEX_REG_LC0
], 1);
843 gen_set_label(label3
);
847 static void gen_endloop1(DisasContext
*ctx
)
850 * if (hex_gpr[HEX_REG_LC1] > 1) {
851 * PC = hex_gpr[HEX_REG_SA1];
852 * hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1;
855 TCGLabel
*label
= gen_new_label();
856 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC1
], 1, label
);
858 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA1
]);
859 tcg_gen_subi_tl(hex_new_value
[HEX_REG_LC1
], hex_gpr
[HEX_REG_LC1
], 1);
861 gen_set_label(label
);
864 static void gen_endloop01(DisasContext
*ctx
)
866 TCGv lpcfg
= tcg_temp_new();
867 TCGLabel
*label1
= gen_new_label();
868 TCGLabel
*label2
= gen_new_label();
869 TCGLabel
*label3
= gen_new_label();
870 TCGLabel
*done
= gen_new_label();
872 GET_USR_FIELD(USR_LPCFG
, lpcfg
);
876 * hex_new_pred_value[3] = 0xff;
877 * hex_pred_written |= 1 << 3;
880 tcg_gen_brcondi_tl(TCG_COND_NE
, lpcfg
, 1, label1
);
882 tcg_gen_movi_tl(hex_new_pred_value
[3], 0xff);
883 tcg_gen_ori_tl(hex_pred_written
, hex_pred_written
, 1 << 3);
885 gen_set_label(label1
);
889 * SET_USR_FIELD(USR_LPCFG, lpcfg - 1);
892 tcg_gen_brcondi_tl(TCG_COND_EQ
, lpcfg
, 0, label2
);
894 tcg_gen_subi_tl(lpcfg
, lpcfg
, 1);
895 SET_USR_FIELD(USR_LPCFG
, lpcfg
);
897 gen_set_label(label2
);
900 * if (hex_gpr[HEX_REG_LC0] > 1) {
901 * PC = hex_gpr[HEX_REG_SA0];
902 * hex_new_value[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1;
904 * if (hex_gpr[HEX_REG_LC1] > 1) {
905 * hex_next_pc = hex_gpr[HEX_REG_SA1];
906 * hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1;
910 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC0
], 1, label3
);
912 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA0
]);
913 tcg_gen_subi_tl(hex_new_value
[HEX_REG_LC0
], hex_gpr
[HEX_REG_LC0
], 1);
916 gen_set_label(label3
);
917 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC1
], 1, done
);
919 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA1
]);
920 tcg_gen_subi_tl(hex_new_value
[HEX_REG_LC1
], hex_gpr
[HEX_REG_LC1
], 1);
925 static void gen_cmp_jumpnv(DisasContext
*ctx
,
926 TCGCond cond
, TCGv val
, TCGv src
, int pc_off
)
928 TCGv pred
= tcg_temp_new();
929 tcg_gen_setcond_tl(cond
, pred
, val
, src
);
930 gen_cond_jump(ctx
, TCG_COND_EQ
, pred
, pc_off
);
933 static void gen_cmpi_jumpnv(DisasContext
*ctx
,
934 TCGCond cond
, TCGv val
, int src
, int pc_off
)
936 TCGv pred
= tcg_temp_new();
937 tcg_gen_setcondi_tl(cond
, pred
, val
, src
);
938 gen_cond_jump(ctx
, TCG_COND_EQ
, pred
, pc_off
);
941 /* Shift left with saturation */
942 static void gen_shl_sat(TCGv dst
, TCGv src
, TCGv shift_amt
)
944 TCGv sh32
= tcg_temp_new();
945 TCGv dst_sar
= tcg_temp_new();
946 TCGv ovf
= tcg_temp_new();
947 TCGv satval
= tcg_temp_new();
948 TCGv min
= tcg_constant_tl(0x80000000);
949 TCGv max
= tcg_constant_tl(0x7fffffff);
952 * Possible values for shift_amt are 0 .. 64
953 * We need special handling for values above 31
956 * dst = sh32 == shift ? src : 0;
958 * dst_sar = dst >> sh32;
959 * satval = src < 0 ? min : max;
960 * if (dst_asr != src) {
966 tcg_gen_andi_tl(sh32
, shift_amt
, 31);
967 tcg_gen_movcond_tl(TCG_COND_EQ
, dst
, sh32
, shift_amt
,
968 src
, tcg_constant_tl(0));
969 tcg_gen_shl_tl(dst
, dst
, sh32
);
970 tcg_gen_sar_tl(dst_sar
, dst
, sh32
);
971 tcg_gen_movcond_tl(TCG_COND_LT
, satval
, src
, tcg_constant_tl(0), min
, max
);
973 tcg_gen_setcond_tl(TCG_COND_NE
, ovf
, dst_sar
, src
);
974 tcg_gen_shli_tl(ovf
, ovf
, reg_field_info
[USR_OVF
].offset
);
975 tcg_gen_or_tl(hex_new_value
[HEX_REG_USR
], hex_new_value
[HEX_REG_USR
], ovf
);
977 tcg_gen_movcond_tl(TCG_COND_EQ
, dst
, dst_sar
, src
, dst
, satval
);
980 static void gen_sar(TCGv dst
, TCGv src
, TCGv shift_amt
)
983 * Shift arithmetic right
984 * Robust when shift_amt is >31 bits
986 TCGv tmp
= tcg_temp_new();
987 tcg_gen_umin_tl(tmp
, shift_amt
, tcg_constant_tl(31));
988 tcg_gen_sar_tl(dst
, src
, tmp
);
991 /* Bidirectional shift right with saturation */
992 static void gen_asr_r_r_sat(TCGv RdV
, TCGv RsV
, TCGv RtV
)
994 TCGv shift_amt
= tcg_temp_new();
995 TCGLabel
*positive
= gen_new_label();
996 TCGLabel
*done
= gen_new_label();
998 tcg_gen_sextract_i32(shift_amt
, RtV
, 0, 7);
999 tcg_gen_brcondi_tl(TCG_COND_GE
, shift_amt
, 0, positive
);
1001 /* Negative shift amount => shift left */
1002 tcg_gen_neg_tl(shift_amt
, shift_amt
);
1003 gen_shl_sat(RdV
, RsV
, shift_amt
);
1006 gen_set_label(positive
);
1007 /* Positive shift amount => shift right */
1008 gen_sar(RdV
, RsV
, shift_amt
);
1010 gen_set_label(done
);
1013 /* Bidirectional shift left with saturation */
1014 static void gen_asl_r_r_sat(TCGv RdV
, TCGv RsV
, TCGv RtV
)
1016 TCGv shift_amt
= tcg_temp_new();
1017 TCGLabel
*positive
= gen_new_label();
1018 TCGLabel
*done
= gen_new_label();
1020 tcg_gen_sextract_i32(shift_amt
, RtV
, 0, 7);
1021 tcg_gen_brcondi_tl(TCG_COND_GE
, shift_amt
, 0, positive
);
1023 /* Negative shift amount => shift right */
1024 tcg_gen_neg_tl(shift_amt
, shift_amt
);
1025 gen_sar(RdV
, RsV
, shift_amt
);
1028 gen_set_label(positive
);
1029 /* Positive shift amount => shift left */
1030 gen_shl_sat(RdV
, RsV
, shift_amt
);
1032 gen_set_label(done
);
1035 static intptr_t vreg_src_off(DisasContext
*ctx
, int num
)
1037 intptr_t offset
= offsetof(CPUHexagonState
, VRegs
[num
]);
1039 if (test_bit(num
, ctx
->vregs_select
)) {
1040 offset
= ctx_future_vreg_off(ctx
, num
, 1, false);
1042 if (test_bit(num
, ctx
->vregs_updated_tmp
)) {
1043 offset
= ctx_tmp_vreg_off(ctx
, num
, 1, false);
1048 static void gen_log_vreg_write(DisasContext
*ctx
, intptr_t srcoff
, int num
,
1049 VRegWriteType type
, int slot_num
,
1052 TCGLabel
*label_end
= NULL
;
1055 if (is_predicated
) {
1056 TCGv cancelled
= tcg_temp_new();
1057 label_end
= gen_new_label();
1059 /* Don't do anything if the slot was cancelled */
1060 tcg_gen_extract_tl(cancelled
, hex_slot_cancelled
, slot_num
, 1);
1061 tcg_gen_brcondi_tl(TCG_COND_NE
, cancelled
, 0, label_end
);
1064 if (type
!= EXT_TMP
) {
1065 dstoff
= ctx_future_vreg_off(ctx
, num
, 1, true);
1066 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
,
1067 sizeof(MMVector
), sizeof(MMVector
));
1068 tcg_gen_ori_tl(hex_VRegs_updated
, hex_VRegs_updated
, 1 << num
);
1070 dstoff
= ctx_tmp_vreg_off(ctx
, num
, 1, false);
1071 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
,
1072 sizeof(MMVector
), sizeof(MMVector
));
1075 if (is_predicated
) {
1076 gen_set_label(label_end
);
1080 static void gen_log_vreg_write_pair(DisasContext
*ctx
, intptr_t srcoff
, int num
,
1081 VRegWriteType type
, int slot_num
,
1084 gen_log_vreg_write(ctx
, srcoff
, num
^ 0, type
, slot_num
, is_predicated
);
1085 srcoff
+= sizeof(MMVector
);
1086 gen_log_vreg_write(ctx
, srcoff
, num
^ 1, type
, slot_num
, is_predicated
);
1089 static void gen_log_qreg_write(intptr_t srcoff
, int num
, int vnew
,
1090 int slot_num
, bool is_predicated
)
1092 TCGLabel
*label_end
= NULL
;
1095 if (is_predicated
) {
1096 TCGv cancelled
= tcg_temp_new();
1097 label_end
= gen_new_label();
1099 /* Don't do anything if the slot was cancelled */
1100 tcg_gen_extract_tl(cancelled
, hex_slot_cancelled
, slot_num
, 1);
1101 tcg_gen_brcondi_tl(TCG_COND_NE
, cancelled
, 0, label_end
);
1104 dstoff
= offsetof(CPUHexagonState
, future_QRegs
[num
]);
1105 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, sizeof(MMQReg
), sizeof(MMQReg
));
1107 if (is_predicated
) {
1108 tcg_gen_ori_tl(hex_QRegs_updated
, hex_QRegs_updated
, 1 << num
);
1109 gen_set_label(label_end
);
1113 static void gen_vreg_load(DisasContext
*ctx
, intptr_t dstoff
, TCGv src
,
1116 TCGv_i64 tmp
= tcg_temp_new_i64();
1118 tcg_gen_andi_tl(src
, src
, ~((int32_t)sizeof(MMVector
) - 1));
1120 for (int i
= 0; i
< sizeof(MMVector
) / 8; i
++) {
1121 tcg_gen_qemu_ld64(tmp
, src
, ctx
->mem_idx
);
1122 tcg_gen_addi_tl(src
, src
, 8);
1123 tcg_gen_st_i64(tmp
, cpu_env
, dstoff
+ i
* 8);
1127 static void gen_vreg_store(DisasContext
*ctx
, TCGv EA
, intptr_t srcoff
,
1128 int slot
, bool aligned
)
1130 intptr_t dstoff
= offsetof(CPUHexagonState
, vstore
[slot
].data
);
1131 intptr_t maskoff
= offsetof(CPUHexagonState
, vstore
[slot
].mask
);
1133 if (is_gather_store_insn(ctx
)) {
1134 TCGv sl
= tcg_constant_tl(slot
);
1135 gen_helper_gather_store(cpu_env
, EA
, sl
);
1139 tcg_gen_movi_tl(hex_vstore_pending
[slot
], 1);
1141 tcg_gen_andi_tl(hex_vstore_addr
[slot
], EA
,
1142 ~((int32_t)sizeof(MMVector
) - 1));
1144 tcg_gen_mov_tl(hex_vstore_addr
[slot
], EA
);
1146 tcg_gen_movi_tl(hex_vstore_size
[slot
], sizeof(MMVector
));
1148 /* Copy the data to the vstore buffer */
1149 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, sizeof(MMVector
), sizeof(MMVector
));
1150 /* Set the mask to all 1's */
1151 tcg_gen_gvec_dup_imm(MO_64
, maskoff
, sizeof(MMQReg
), sizeof(MMQReg
), ~0LL);
1154 static void gen_vreg_masked_store(DisasContext
*ctx
, TCGv EA
, intptr_t srcoff
,
1155 intptr_t bitsoff
, int slot
, bool invert
)
1157 intptr_t dstoff
= offsetof(CPUHexagonState
, vstore
[slot
].data
);
1158 intptr_t maskoff
= offsetof(CPUHexagonState
, vstore
[slot
].mask
);
1160 tcg_gen_movi_tl(hex_vstore_pending
[slot
], 1);
1161 tcg_gen_andi_tl(hex_vstore_addr
[slot
], EA
,
1162 ~((int32_t)sizeof(MMVector
) - 1));
1163 tcg_gen_movi_tl(hex_vstore_size
[slot
], sizeof(MMVector
));
1165 /* Copy the data to the vstore buffer */
1166 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, sizeof(MMVector
), sizeof(MMVector
));
1168 tcg_gen_gvec_mov(MO_64
, maskoff
, bitsoff
, sizeof(MMQReg
), sizeof(MMQReg
));
1170 tcg_gen_gvec_not(MO_64
, maskoff
, maskoff
,
1171 sizeof(MMQReg
), sizeof(MMQReg
));
1175 static void vec_to_qvec(size_t size
, intptr_t dstoff
, intptr_t srcoff
)
1177 TCGv_i64 tmp
= tcg_temp_new_i64();
1178 TCGv_i64 word
= tcg_temp_new_i64();
1179 TCGv_i64 bits
= tcg_temp_new_i64();
1180 TCGv_i64 mask
= tcg_temp_new_i64();
1181 TCGv_i64 zero
= tcg_constant_i64(0);
1182 TCGv_i64 ones
= tcg_constant_i64(~0);
1184 for (int i
= 0; i
< sizeof(MMVector
) / 8; i
++) {
1185 tcg_gen_ld_i64(tmp
, cpu_env
, srcoff
+ i
* 8);
1186 tcg_gen_movi_i64(mask
, 0);
1188 for (int j
= 0; j
< 8; j
+= size
) {
1189 tcg_gen_extract_i64(word
, tmp
, j
* 8, size
* 8);
1190 tcg_gen_movcond_i64(TCG_COND_NE
, bits
, word
, zero
, ones
, zero
);
1191 tcg_gen_deposit_i64(mask
, mask
, bits
, j
, size
);
1194 tcg_gen_st8_i64(mask
, cpu_env
, dstoff
+ i
);
1198 void probe_noshuf_load(TCGv va
, int s
, int mi
)
1200 TCGv size
= tcg_constant_tl(s
);
1201 TCGv mem_idx
= tcg_constant_tl(mi
);
1202 gen_helper_probe_noshuf_load(cpu_env
, va
, size
, mem_idx
);
1206 * Note: Since this function might branch, `val` is
1207 * required to be a `tcg_temp_local`.
1209 void gen_set_usr_field_if(int field
, TCGv val
)
1211 /* Sets the USR field if `val` is non-zero */
1212 if (reg_field_info
[field
].width
== 1) {
1213 TCGv tmp
= tcg_temp_new();
1214 tcg_gen_extract_tl(tmp
, val
, 0, reg_field_info
[field
].width
);
1215 tcg_gen_shli_tl(tmp
, tmp
, reg_field_info
[field
].offset
);
1216 tcg_gen_or_tl(hex_new_value
[HEX_REG_USR
],
1217 hex_new_value
[HEX_REG_USR
],
1220 TCGLabel
*skip_label
= gen_new_label();
1221 tcg_gen_brcondi_tl(TCG_COND_EQ
, val
, 0, skip_label
);
1222 gen_set_usr_field(field
, val
);
1223 gen_set_label(skip_label
);
1227 void gen_sat_i32(TCGv dest
, TCGv source
, int width
)
1229 TCGv max_val
= tcg_constant_tl((1 << (width
- 1)) - 1);
1230 TCGv min_val
= tcg_constant_tl(-(1 << (width
- 1)));
1231 tcg_gen_smin_tl(dest
, source
, max_val
);
1232 tcg_gen_smax_tl(dest
, dest
, min_val
);
1235 void gen_sat_i32_ovfl(TCGv ovfl
, TCGv dest
, TCGv source
, int width
)
1237 gen_sat_i32(dest
, source
, width
);
1238 tcg_gen_setcond_tl(TCG_COND_NE
, ovfl
, source
, dest
);
1241 void gen_satu_i32(TCGv dest
, TCGv source
, int width
)
1243 TCGv max_val
= tcg_constant_tl((1 << width
) - 1);
1244 TCGv zero
= tcg_constant_tl(0);
1245 tcg_gen_movcond_tl(TCG_COND_GTU
, dest
, source
, max_val
, max_val
, source
);
1246 tcg_gen_movcond_tl(TCG_COND_LT
, dest
, source
, zero
, zero
, dest
);
1249 void gen_satu_i32_ovfl(TCGv ovfl
, TCGv dest
, TCGv source
, int width
)
1251 gen_satu_i32(dest
, source
, width
);
1252 tcg_gen_setcond_tl(TCG_COND_NE
, ovfl
, source
, dest
);
1255 void gen_sat_i64(TCGv_i64 dest
, TCGv_i64 source
, int width
)
1257 TCGv_i64 max_val
= tcg_constant_i64((1LL << (width
- 1)) - 1LL);
1258 TCGv_i64 min_val
= tcg_constant_i64(-(1LL << (width
- 1)));
1259 tcg_gen_smin_i64(dest
, source
, max_val
);
1260 tcg_gen_smax_i64(dest
, dest
, min_val
);
1263 void gen_sat_i64_ovfl(TCGv ovfl
, TCGv_i64 dest
, TCGv_i64 source
, int width
)
1266 gen_sat_i64(dest
, source
, width
);
1267 ovfl_64
= tcg_temp_new_i64();
1268 tcg_gen_setcond_i64(TCG_COND_NE
, ovfl_64
, dest
, source
);
1269 tcg_gen_trunc_i64_tl(ovfl
, ovfl_64
);
1272 void gen_satu_i64(TCGv_i64 dest
, TCGv_i64 source
, int width
)
1274 TCGv_i64 max_val
= tcg_constant_i64((1LL << width
) - 1LL);
1275 TCGv_i64 zero
= tcg_constant_i64(0);
1276 tcg_gen_movcond_i64(TCG_COND_GTU
, dest
, source
, max_val
, max_val
, source
);
1277 tcg_gen_movcond_i64(TCG_COND_LT
, dest
, source
, zero
, zero
, dest
);
1280 void gen_satu_i64_ovfl(TCGv ovfl
, TCGv_i64 dest
, TCGv_i64 source
, int width
)
1283 gen_satu_i64(dest
, source
, width
);
1284 ovfl_64
= tcg_temp_new_i64();
1285 tcg_gen_setcond_i64(TCG_COND_NE
, ovfl_64
, dest
, source
);
1286 tcg_gen_trunc_i64_tl(ovfl
, ovfl_64
);
1289 /* Implements the fADDSAT64 macro in TCG */
1290 void gen_add_sat_i64(TCGv_i64 ret
, TCGv_i64 a
, TCGv_i64 b
)
1292 TCGv_i64 sum
= tcg_temp_new_i64();
1293 TCGv_i64
xor = tcg_temp_new_i64();
1294 TCGv_i64 cond1
= tcg_temp_new_i64();
1295 TCGv_i64 cond2
= tcg_temp_new_i64();
1296 TCGv_i64 cond3
= tcg_temp_new_i64();
1297 TCGv_i64 mask
= tcg_constant_i64(0x8000000000000000ULL
);
1298 TCGv_i64 max_pos
= tcg_constant_i64(0x7FFFFFFFFFFFFFFFLL
);
1299 TCGv_i64 max_neg
= tcg_constant_i64(0x8000000000000000LL
);
1300 TCGv_i64 zero
= tcg_constant_i64(0);
1301 TCGLabel
*no_ovfl_label
= gen_new_label();
1302 TCGLabel
*ovfl_label
= gen_new_label();
1303 TCGLabel
*ret_label
= gen_new_label();
1305 tcg_gen_add_i64(sum
, a
, b
);
1306 tcg_gen_xor_i64(xor, a
, b
);
1308 /* if (xor & mask) */
1309 tcg_gen_and_i64(cond1
, xor, mask
);
1310 tcg_gen_brcondi_i64(TCG_COND_NE
, cond1
, 0, no_ovfl_label
);
1312 /* else if ((a ^ sum) & mask) */
1313 tcg_gen_xor_i64(cond2
, a
, sum
);
1314 tcg_gen_and_i64(cond2
, cond2
, mask
);
1315 tcg_gen_brcondi_i64(TCG_COND_NE
, cond2
, 0, ovfl_label
);
1316 /* fallthrough to no_ovfl_label branch */
1319 gen_set_label(no_ovfl_label
);
1320 tcg_gen_mov_i64(ret
, sum
);
1321 tcg_gen_br(ret_label
);
1323 /* else if branch */
1324 gen_set_label(ovfl_label
);
1325 tcg_gen_and_i64(cond3
, sum
, mask
);
1326 tcg_gen_movcond_i64(TCG_COND_NE
, ret
, cond3
, zero
, max_pos
, max_neg
);
1327 SET_USR_FIELD(USR_OVF
, 1);
1329 gen_set_label(ret_label
);
1332 #include "tcg_funcs_generated.c.inc"
1333 #include "tcg_func_table_generated.c.inc"