target/hexagon/genptr.c

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #define QEMU_GENERATE
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "internal.h"
  22 #include "tcg/tcg-op.h"
  23 #include "insn.h"
  24 #include "opcodes.h"
  25 #include "translate.h"
  26 #include "macros.h"
  27 #include "gen_tcg.h"
  28
  29 static inline TCGv gen_read_preg(TCGv pred, uint8_t num)
  30 {
  31     tcg_gen_mov_tl(pred, hex_pred[num]);
  32     return pred;
  33 }
  34
  35 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
  36 {
  37     TCGv one = tcg_const_tl(1);
  38     TCGv zero = tcg_const_tl(0);
  39     TCGv slot_mask = tcg_temp_new();
  40
  41     tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
  42     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
  43                            val, hex_new_value[rnum]);
  44 #if HEX_DEBUG
  45     /* Do this so HELPER(debug_commit_end) will know */
  46     tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero,
  47                        one, hex_reg_written[rnum]);
  48 #endif
  49
  50     tcg_temp_free(one);
  51     tcg_temp_free(zero);
  52     tcg_temp_free(slot_mask);
  53 }
  54
  55 static inline void gen_log_reg_write(int rnum, TCGv val)
  56 {
  57     tcg_gen_mov_tl(hex_new_value[rnum], val);
  58 #if HEX_DEBUG
  59     /* Do this so HELPER(debug_commit_end) will know */
  60     tcg_gen_movi_tl(hex_reg_written[rnum], 1);
  61 #endif
  62 }
  63
  64 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
  65 {
  66     TCGv val32 = tcg_temp_new();
  67     TCGv one = tcg_const_tl(1);
  68     TCGv zero = tcg_const_tl(0);
  69     TCGv slot_mask = tcg_temp_new();
  70
  71     tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
  72     /* Low word */
  73     tcg_gen_extrl_i64_i32(val32, val);
  74     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
  75                        val32, hex_new_value[rnum]);
  76 #if HEX_DEBUG
  77     /* Do this so HELPER(debug_commit_end) will know */
  78     tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum],
  79                        slot_mask, zero,
  80                        one, hex_reg_written[rnum]);
  81 #endif
  82
  83     /* High word */
  84     tcg_gen_extrh_i64_i32(val32, val);
  85     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
  86                        slot_mask, zero,
  87                        val32, hex_new_value[rnum + 1]);
  88 #if HEX_DEBUG
  89     /* Do this so HELPER(debug_commit_end) will know */
  90     tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum + 1],
  91                        slot_mask, zero,
  92                        one, hex_reg_written[rnum + 1]);
  93 #endif
  94
  95     tcg_temp_free(val32);
  96     tcg_temp_free(one);
  97     tcg_temp_free(zero);
  98     tcg_temp_free(slot_mask);
  99 }
 100
 101 static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
 102 {
 103     /* Low word */
 104     tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
 105 #if HEX_DEBUG
 106     /* Do this so HELPER(debug_commit_end) will know */
 107     tcg_gen_movi_tl(hex_reg_written[rnum], 1);
 108 #endif
 109
 110     /* High word */
 111     tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
 112 #if HEX_DEBUG
 113     /* Do this so HELPER(debug_commit_end) will know */
 114     tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
 115 #endif
 116 }
 117
 118 static inline void gen_log_pred_write(int pnum, TCGv val)
 119 {
 120     TCGv zero = tcg_const_tl(0);
 121     TCGv base_val = tcg_temp_new();
 122     TCGv and_val = tcg_temp_new();
 123     TCGv pred_written = tcg_temp_new();
 124
 125     /* Multiple writes to the same preg are and'ed together */
 126     tcg_gen_andi_tl(base_val, val, 0xff);
 127     tcg_gen_and_tl(and_val, base_val, hex_new_pred_value[pnum]);
 128     tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pnum);
 129     tcg_gen_movcond_tl(TCG_COND_NE, hex_new_pred_value[pnum],
 130                        pred_written, zero,
 131                        and_val, base_val);
 132     tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
 133
 134     tcg_temp_free(zero);
 135     tcg_temp_free(base_val);
 136     tcg_temp_free(and_val);
 137     tcg_temp_free(pred_written);
 138 }
 139
 140 static inline void gen_read_p3_0(TCGv control_reg)
 141 {
 142     tcg_gen_movi_tl(control_reg, 0);
 143     for (int i = 0; i < NUM_PREGS; i++) {
 144         tcg_gen_deposit_tl(control_reg, control_reg, hex_pred[i], i * 8, 8);
 145     }
 146 }
 147
 148 /*
 149  * Certain control registers require special handling on read
 150  *     HEX_REG_P3_0          aliased to the predicate registers
 151  *                           -> concat the 4 predicate registers together
 152  *     HEX_REG_PC            actual value stored in DisasContext
 153  *                           -> assign from ctx->base.pc_next
 154  *     HEX_REG_QEMU_*_CNT    changes in current TB in DisasContext
 155  *                           -> add current TB changes to existing reg value
 156  */
 157 static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
 158                                      TCGv dest)
 159 {
 160     if (reg_num == HEX_REG_P3_0) {
 161         gen_read_p3_0(dest);
 162     } else if (reg_num == HEX_REG_PC) {
 163         tcg_gen_movi_tl(dest, ctx->base.pc_next);
 164     } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 165         tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_PKT_CNT],
 166                         ctx->num_packets);
 167     } else if (reg_num == HEX_REG_QEMU_INSN_CNT) {
 168         tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT],
 169                         ctx->num_insns);
 170     } else {
 171         tcg_gen_mov_tl(dest, hex_gpr[reg_num]);
 172     }
 173 }
 174
 175 static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
 176                                           TCGv_i64 dest)
 177 {
 178     if (reg_num == HEX_REG_P3_0) {
 179         TCGv p3_0 = tcg_temp_new();
 180         gen_read_p3_0(p3_0);
 181         tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
 182         tcg_temp_free(p3_0);
 183     } else if (reg_num == HEX_REG_PC - 1) {
 184         TCGv pc = tcg_const_tl(ctx->base.pc_next);
 185         tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc);
 186         tcg_temp_free(pc);
 187     } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 188         TCGv pkt_cnt = tcg_temp_new();
 189         TCGv insn_cnt = tcg_temp_new();
 190         tcg_gen_addi_tl(pkt_cnt, hex_gpr[HEX_REG_QEMU_PKT_CNT],
 191                         ctx->num_packets);
 192         tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT],
 193                         ctx->num_insns);
 194         tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt);
 195         tcg_temp_free(pkt_cnt);
 196         tcg_temp_free(insn_cnt);
 197     } else {
 198         tcg_gen_concat_i32_i64(dest,
 199             hex_gpr[reg_num],
 200             hex_gpr[reg_num + 1]);
 201     }
 202 }
 203
 204 static inline void gen_write_p3_0(TCGv control_reg)
 205 {
 206     for (int i = 0; i < NUM_PREGS; i++) {
 207         tcg_gen_extract_tl(hex_pred[i], control_reg, i * 8, 8);
 208     }
 209 }
 210
 211 /*
 212  * Certain control registers require special handling on write
 213  *     HEX_REG_P3_0          aliased to the predicate registers
 214  *                           -> break the value across 4 predicate registers
 215  *     HEX_REG_QEMU_*_CNT    changes in current TB in DisasContext
 216  *                            -> clear the changes
 217  */
 218 static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
 219                                       TCGv val)
 220 {
 221     if (reg_num == HEX_REG_P3_0) {
 222         gen_write_p3_0(val);
 223     } else {
 224         gen_log_reg_write(reg_num, val);
 225         ctx_log_reg_write(ctx, reg_num);
 226         if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 227             ctx->num_packets = 0;
 228         }
 229         if (reg_num == HEX_REG_QEMU_INSN_CNT) {
 230             ctx->num_insns = 0;
 231         }
 232     }
 233 }
 234
 235 static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
 236                                            TCGv_i64 val)
 237 {
 238     if (reg_num == HEX_REG_P3_0) {
 239         TCGv val32 = tcg_temp_new();
 240         tcg_gen_extrl_i64_i32(val32, val);
 241         gen_write_p3_0(val32);
 242         tcg_gen_extrh_i64_i32(val32, val);
 243         gen_log_reg_write(reg_num + 1, val32);
 244         tcg_temp_free(val32);
 245         ctx_log_reg_write(ctx, reg_num + 1);
 246     } else {
 247         gen_log_reg_write_pair(reg_num, val);
 248         ctx_log_reg_write_pair(ctx, reg_num);
 249         if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 250             ctx->num_packets = 0;
 251             ctx->num_insns = 0;
 252         }
 253     }
 254 }
 255
 256 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
 257 {
 258     tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
 259     tcg_gen_mov_tl(hex_llsc_addr, vaddr);
 260     tcg_gen_mov_tl(hex_llsc_val, dest);
 261 }
 262
 263 static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
 264 {
 265     tcg_gen_qemu_ld64(dest, vaddr, mem_index);
 266     tcg_gen_mov_tl(hex_llsc_addr, vaddr);
 267     tcg_gen_mov_i64(hex_llsc_val_i64, dest);
 268 }
 269
 270 static inline void gen_store_conditional4(CPUHexagonState *env,
 271                                           DisasContext *ctx, int prednum,
 272                                           TCGv pred, TCGv vaddr, TCGv src)
 273 {
 274     TCGLabel *fail = gen_new_label();
 275     TCGLabel *done = gen_new_label();
 276     TCGv one, zero, tmp;
 277
 278     tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
 279
 280     one = tcg_const_tl(0xff);
 281     zero = tcg_const_tl(0);
 282     tmp = tcg_temp_new();
 283     tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
 284                               ctx->mem_idx, MO_32);
 285     tcg_gen_movcond_tl(TCG_COND_EQ, hex_pred[prednum], tmp, hex_llsc_val,
 286                        one, zero);
 287     tcg_temp_free(one);
 288     tcg_temp_free(zero);
 289     tcg_temp_free(tmp);
 290     tcg_gen_br(done);
 291
 292     gen_set_label(fail);
 293     tcg_gen_movi_tl(pred, 0);
 294
 295     gen_set_label(done);
 296     tcg_gen_movi_tl(hex_llsc_addr, ~0);
 297 }
 298
 299 static inline void gen_store_conditional8(CPUHexagonState *env,
 300                                           DisasContext *ctx, int prednum,
 301                                           TCGv pred, TCGv vaddr, TCGv_i64 src)
 302 {
 303     TCGLabel *fail = gen_new_label();
 304     TCGLabel *done = gen_new_label();
 305     TCGv_i64 one, zero, tmp;
 306
 307     tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
 308
 309     one = tcg_const_i64(0xff);
 310     zero = tcg_const_i64(0);
 311     tmp = tcg_temp_new_i64();
 312     tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src,
 313                                ctx->mem_idx, MO_64);
 314     tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
 315                         one, zero);
 316     tcg_gen_extrl_i64_i32(hex_pred[prednum], tmp);
 317     tcg_temp_free_i64(one);
 318     tcg_temp_free_i64(zero);
 319     tcg_temp_free_i64(tmp);
 320     tcg_gen_br(done);
 321
 322     gen_set_label(fail);
 323     tcg_gen_movi_tl(pred, 0);
 324
 325     gen_set_label(done);
 326     tcg_gen_movi_tl(hex_llsc_addr, ~0);
 327 }
 328
 329 #include "tcg_funcs_generated.c.inc"
 330 #include "tcg_func_table_generated.c.inc"