2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 #include "qemu/osdep.h"
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
25 #include "translate.h"
26 #define QEMU_GENERATE /* Used internally by macros.h */
28 #include "mmvec/macros.h"
31 #include "gen_tcg_hvx.h"
34 TCGv
gen_read_reg(TCGv result
, int num
)
36 tcg_gen_mov_tl(result
, hex_gpr
[num
]);
40 TCGv
gen_read_preg(TCGv pred
, uint8_t num
)
42 tcg_gen_mov_tl(pred
, hex_pred
[num
]);
46 #define IMMUTABLE (~0)
48 const target_ulong reg_immut_masks
[TOTAL_PER_THREAD_REGS
] = {
49 [HEX_REG_USR
] = 0xc13000c0,
50 [HEX_REG_PC
] = IMMUTABLE
,
52 [HEX_REG_UPCYCLELO
] = IMMUTABLE
,
53 [HEX_REG_UPCYCLEHI
] = IMMUTABLE
,
54 [HEX_REG_UTIMERLO
] = IMMUTABLE
,
55 [HEX_REG_UTIMERHI
] = IMMUTABLE
,
58 static inline void gen_masked_reg_write(TCGv new_val
, TCGv cur_val
,
59 target_ulong reg_mask
)
62 TCGv tmp
= tcg_temp_new();
64 /* new_val = (new_val & ~reg_mask) | (cur_val & reg_mask) */
65 tcg_gen_andi_tl(new_val
, new_val
, ~reg_mask
);
66 tcg_gen_andi_tl(tmp
, cur_val
, reg_mask
);
67 tcg_gen_or_tl(new_val
, new_val
, tmp
);
71 TCGv
get_result_gpr(DisasContext
*ctx
, int rnum
)
73 if (ctx
->need_commit
) {
74 if (rnum
== HEX_REG_USR
) {
75 return hex_new_value_usr
;
77 if (ctx
->new_value
[rnum
] == NULL
) {
78 ctx
->new_value
[rnum
] = tcg_temp_new();
79 tcg_gen_movi_tl(ctx
->new_value
[rnum
], 0);
81 return ctx
->new_value
[rnum
];
88 static TCGv_i64
get_result_gpr_pair(DisasContext
*ctx
, int rnum
)
90 TCGv_i64 result
= tcg_temp_new_i64();
91 tcg_gen_concat_i32_i64(result
, get_result_gpr(ctx
, rnum
),
92 get_result_gpr(ctx
, rnum
+ 1));
96 void gen_log_reg_write(DisasContext
*ctx
, int rnum
, TCGv val
)
98 const target_ulong reg_mask
= reg_immut_masks
[rnum
];
100 gen_masked_reg_write(val
, hex_gpr
[rnum
], reg_mask
);
101 tcg_gen_mov_tl(get_result_gpr(ctx
, rnum
), val
);
103 /* Do this so HELPER(debug_commit_end) will know */
104 tcg_gen_movi_tl(hex_reg_written
[rnum
], 1);
108 static void gen_log_reg_write_pair(DisasContext
*ctx
, int rnum
, TCGv_i64 val
)
110 TCGv val32
= tcg_temp_new();
113 tcg_gen_extrl_i64_i32(val32
, val
);
114 gen_log_reg_write(ctx
, rnum
, val32
);
117 tcg_gen_extrh_i64_i32(val32
, val
);
118 gen_log_reg_write(ctx
, rnum
+ 1, val32
);
121 TCGv
get_result_pred(DisasContext
*ctx
, int pnum
)
123 if (ctx
->need_commit
) {
124 if (ctx
->new_pred_value
[pnum
] == NULL
) {
125 ctx
->new_pred_value
[pnum
] = tcg_temp_new();
126 tcg_gen_movi_tl(ctx
->new_pred_value
[pnum
], 0);
128 return ctx
->new_pred_value
[pnum
];
130 return hex_pred
[pnum
];
134 void gen_log_pred_write(DisasContext
*ctx
, int pnum
, TCGv val
)
136 TCGv pred
= get_result_pred(ctx
, pnum
);
137 TCGv base_val
= tcg_temp_new();
139 tcg_gen_andi_tl(base_val
, val
, 0xff);
142 * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual
144 * Multiple writes to the same preg are and'ed together
145 * If this is the first predicate write in the packet, do a
146 * straight assignment. Otherwise, do an and.
148 if (!test_bit(pnum
, ctx
->pregs_written
)) {
149 tcg_gen_mov_tl(pred
, base_val
);
151 tcg_gen_and_tl(pred
, pred
, base_val
);
154 tcg_gen_ori_tl(ctx
->pred_written
, ctx
->pred_written
, 1 << pnum
);
156 set_bit(pnum
, ctx
->pregs_written
);
159 static inline void gen_read_p3_0(TCGv control_reg
)
161 tcg_gen_movi_tl(control_reg
, 0);
162 for (int i
= 0; i
< NUM_PREGS
; i
++) {
163 tcg_gen_deposit_tl(control_reg
, control_reg
, hex_pred
[i
], i
* 8, 8);
168 * Certain control registers require special handling on read
169 * HEX_REG_P3_0_ALIASED aliased to the predicate registers
170 * -> concat the 4 predicate registers together
171 * HEX_REG_PC actual value stored in DisasContext
172 * -> assign from ctx->base.pc_next
173 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
174 * -> add current TB changes to existing reg value
176 static inline void gen_read_ctrl_reg(DisasContext
*ctx
, const int reg_num
,
179 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
181 } else if (reg_num
== HEX_REG_PC
) {
182 tcg_gen_movi_tl(dest
, ctx
->base
.pc_next
);
183 } else if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
184 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
186 } else if (reg_num
== HEX_REG_QEMU_INSN_CNT
) {
187 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
189 } else if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
190 tcg_gen_addi_tl(dest
, hex_gpr
[HEX_REG_QEMU_HVX_CNT
],
193 tcg_gen_mov_tl(dest
, hex_gpr
[reg_num
]);
197 static inline void gen_read_ctrl_reg_pair(DisasContext
*ctx
, const int reg_num
,
200 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
201 TCGv p3_0
= tcg_temp_new();
203 tcg_gen_concat_i32_i64(dest
, p3_0
, hex_gpr
[reg_num
+ 1]);
204 } else if (reg_num
== HEX_REG_PC
- 1) {
205 TCGv pc
= tcg_constant_tl(ctx
->base
.pc_next
);
206 tcg_gen_concat_i32_i64(dest
, hex_gpr
[reg_num
], pc
);
207 } else if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
208 TCGv pkt_cnt
= tcg_temp_new();
209 TCGv insn_cnt
= tcg_temp_new();
210 tcg_gen_addi_tl(pkt_cnt
, hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
212 tcg_gen_addi_tl(insn_cnt
, hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
214 tcg_gen_concat_i32_i64(dest
, pkt_cnt
, insn_cnt
);
215 } else if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
216 TCGv hvx_cnt
= tcg_temp_new();
217 tcg_gen_addi_tl(hvx_cnt
, hex_gpr
[HEX_REG_QEMU_HVX_CNT
],
219 tcg_gen_concat_i32_i64(dest
, hvx_cnt
, hex_gpr
[reg_num
+ 1]);
221 tcg_gen_concat_i32_i64(dest
,
223 hex_gpr
[reg_num
+ 1]);
227 static void gen_write_p3_0(DisasContext
*ctx
, TCGv control_reg
)
229 TCGv hex_p8
= tcg_temp_new();
230 for (int i
= 0; i
< NUM_PREGS
; i
++) {
231 tcg_gen_extract_tl(hex_p8
, control_reg
, i
* 8, 8);
232 gen_log_pred_write(ctx
, i
, hex_p8
);
237 * Certain control registers require special handling on write
238 * HEX_REG_P3_0_ALIASED aliased to the predicate registers
239 * -> break the value across 4 predicate registers
240 * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
241 * -> clear the changes
243 static inline void gen_write_ctrl_reg(DisasContext
*ctx
, int reg_num
,
246 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
247 gen_write_p3_0(ctx
, val
);
249 gen_log_reg_write(ctx
, reg_num
, val
);
250 if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
251 ctx
->num_packets
= 0;
253 if (reg_num
== HEX_REG_QEMU_INSN_CNT
) {
256 if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
257 ctx
->num_hvx_insns
= 0;
262 static inline void gen_write_ctrl_reg_pair(DisasContext
*ctx
, int reg_num
,
265 if (reg_num
== HEX_REG_P3_0_ALIASED
) {
266 TCGv result
= get_result_gpr(ctx
, reg_num
+ 1);
267 TCGv val32
= tcg_temp_new();
268 tcg_gen_extrl_i64_i32(val32
, val
);
269 gen_write_p3_0(ctx
, val32
);
270 tcg_gen_extrh_i64_i32(val32
, val
);
271 tcg_gen_mov_tl(result
, val32
);
273 gen_log_reg_write_pair(ctx
, reg_num
, val
);
274 if (reg_num
== HEX_REG_QEMU_PKT_CNT
) {
275 ctx
->num_packets
= 0;
278 if (reg_num
== HEX_REG_QEMU_HVX_CNT
) {
279 ctx
->num_hvx_insns
= 0;
284 TCGv
gen_get_byte(TCGv result
, int N
, TCGv src
, bool sign
)
287 tcg_gen_sextract_tl(result
, src
, N
* 8, 8);
289 tcg_gen_extract_tl(result
, src
, N
* 8, 8);
294 TCGv
gen_get_byte_i64(TCGv result
, int N
, TCGv_i64 src
, bool sign
)
296 TCGv_i64 res64
= tcg_temp_new_i64();
298 tcg_gen_sextract_i64(res64
, src
, N
* 8, 8);
300 tcg_gen_extract_i64(res64
, src
, N
* 8, 8);
302 tcg_gen_extrl_i64_i32(result
, res64
);
307 TCGv
gen_get_half(TCGv result
, int N
, TCGv src
, bool sign
)
310 tcg_gen_sextract_tl(result
, src
, N
* 16, 16);
312 tcg_gen_extract_tl(result
, src
, N
* 16, 16);
317 void gen_set_half(int N
, TCGv result
, TCGv src
)
319 tcg_gen_deposit_tl(result
, result
, src
, N
* 16, 16);
322 void gen_set_half_i64(int N
, TCGv_i64 result
, TCGv src
)
324 TCGv_i64 src64
= tcg_temp_new_i64();
325 tcg_gen_extu_i32_i64(src64
, src
);
326 tcg_gen_deposit_i64(result
, result
, src64
, N
* 16, 16);
329 void gen_set_byte_i64(int N
, TCGv_i64 result
, TCGv src
)
331 TCGv_i64 src64
= tcg_temp_new_i64();
332 tcg_gen_extu_i32_i64(src64
, src
);
333 tcg_gen_deposit_i64(result
, result
, src64
, N
* 8, 8);
336 static inline void gen_load_locked4u(TCGv dest
, TCGv vaddr
, int mem_index
)
338 tcg_gen_qemu_ld_tl(dest
, vaddr
, mem_index
, MO_TEUL
);
339 tcg_gen_mov_tl(hex_llsc_addr
, vaddr
);
340 tcg_gen_mov_tl(hex_llsc_val
, dest
);
343 static inline void gen_load_locked8u(TCGv_i64 dest
, TCGv vaddr
, int mem_index
)
345 tcg_gen_qemu_ld_i64(dest
, vaddr
, mem_index
, MO_TEUQ
);
346 tcg_gen_mov_tl(hex_llsc_addr
, vaddr
);
347 tcg_gen_mov_i64(hex_llsc_val_i64
, dest
);
350 static inline void gen_store_conditional4(DisasContext
*ctx
,
351 TCGv pred
, TCGv vaddr
, TCGv src
)
353 TCGLabel
*fail
= gen_new_label();
354 TCGLabel
*done
= gen_new_label();
357 tcg_gen_brcond_tl(TCG_COND_NE
, vaddr
, hex_llsc_addr
, fail
);
359 one
= tcg_constant_tl(0xff);
360 zero
= tcg_constant_tl(0);
361 tmp
= tcg_temp_new();
362 tcg_gen_atomic_cmpxchg_tl(tmp
, hex_llsc_addr
, hex_llsc_val
, src
,
363 ctx
->mem_idx
, MO_32
);
364 tcg_gen_movcond_tl(TCG_COND_EQ
, pred
, tmp
, hex_llsc_val
,
369 tcg_gen_movi_tl(pred
, 0);
372 tcg_gen_movi_tl(hex_llsc_addr
, ~0);
375 static inline void gen_store_conditional8(DisasContext
*ctx
,
376 TCGv pred
, TCGv vaddr
, TCGv_i64 src
)
378 TCGLabel
*fail
= gen_new_label();
379 TCGLabel
*done
= gen_new_label();
380 TCGv_i64 one
, zero
, tmp
;
382 tcg_gen_brcond_tl(TCG_COND_NE
, vaddr
, hex_llsc_addr
, fail
);
384 one
= tcg_constant_i64(0xff);
385 zero
= tcg_constant_i64(0);
386 tmp
= tcg_temp_new_i64();
387 tcg_gen_atomic_cmpxchg_i64(tmp
, hex_llsc_addr
, hex_llsc_val_i64
, src
,
388 ctx
->mem_idx
, MO_64
);
389 tcg_gen_movcond_i64(TCG_COND_EQ
, tmp
, tmp
, hex_llsc_val_i64
,
391 tcg_gen_extrl_i64_i32(pred
, tmp
);
395 tcg_gen_movi_tl(pred
, 0);
398 tcg_gen_movi_tl(hex_llsc_addr
, ~0);
401 void gen_store32(TCGv vaddr
, TCGv src
, int width
, uint32_t slot
)
403 tcg_gen_mov_tl(hex_store_addr
[slot
], vaddr
);
404 tcg_gen_movi_tl(hex_store_width
[slot
], width
);
405 tcg_gen_mov_tl(hex_store_val32
[slot
], src
);
408 void gen_store1(TCGv_env cpu_env
, TCGv vaddr
, TCGv src
, uint32_t slot
)
410 gen_store32(vaddr
, src
, 1, slot
);
413 void gen_store1i(TCGv_env cpu_env
, TCGv vaddr
, int32_t src
, uint32_t slot
)
415 TCGv tmp
= tcg_constant_tl(src
);
416 gen_store1(cpu_env
, vaddr
, tmp
, slot
);
419 void gen_store2(TCGv_env cpu_env
, TCGv vaddr
, TCGv src
, uint32_t slot
)
421 gen_store32(vaddr
, src
, 2, slot
);
424 void gen_store2i(TCGv_env cpu_env
, TCGv vaddr
, int32_t src
, uint32_t slot
)
426 TCGv tmp
= tcg_constant_tl(src
);
427 gen_store2(cpu_env
, vaddr
, tmp
, slot
);
430 void gen_store4(TCGv_env cpu_env
, TCGv vaddr
, TCGv src
, uint32_t slot
)
432 gen_store32(vaddr
, src
, 4, slot
);
435 void gen_store4i(TCGv_env cpu_env
, TCGv vaddr
, int32_t src
, uint32_t slot
)
437 TCGv tmp
= tcg_constant_tl(src
);
438 gen_store4(cpu_env
, vaddr
, tmp
, slot
);
441 void gen_store8(TCGv_env cpu_env
, TCGv vaddr
, TCGv_i64 src
, uint32_t slot
)
443 tcg_gen_mov_tl(hex_store_addr
[slot
], vaddr
);
444 tcg_gen_movi_tl(hex_store_width
[slot
], 8);
445 tcg_gen_mov_i64(hex_store_val64
[slot
], src
);
448 void gen_store8i(TCGv_env cpu_env
, TCGv vaddr
, int64_t src
, uint32_t slot
)
450 TCGv_i64 tmp
= tcg_constant_i64(src
);
451 gen_store8(cpu_env
, vaddr
, tmp
, slot
);
454 TCGv
gen_8bitsof(TCGv result
, TCGv value
)
456 TCGv zero
= tcg_constant_tl(0);
457 TCGv ones
= tcg_constant_tl(0xff);
458 tcg_gen_movcond_tl(TCG_COND_NE
, result
, value
, zero
, ones
, zero
);
463 static void gen_write_new_pc_addr(DisasContext
*ctx
, TCGv addr
,
464 TCGCond cond
, TCGv pred
)
466 TCGLabel
*pred_false
= NULL
;
467 if (cond
!= TCG_COND_ALWAYS
) {
468 pred_false
= gen_new_label();
469 tcg_gen_brcondi_tl(cond
, pred
, 0, pred_false
);
472 if (ctx
->pkt
->pkt_has_multi_cof
) {
473 /* If there are multiple branches in a packet, ignore the second one */
474 tcg_gen_movcond_tl(TCG_COND_NE
, hex_gpr
[HEX_REG_PC
],
475 hex_branch_taken
, tcg_constant_tl(0),
476 hex_gpr
[HEX_REG_PC
], addr
);
477 tcg_gen_movi_tl(hex_branch_taken
, 1);
479 tcg_gen_mov_tl(hex_gpr
[HEX_REG_PC
], addr
);
482 if (cond
!= TCG_COND_ALWAYS
) {
483 gen_set_label(pred_false
);
487 static void gen_write_new_pc_pcrel(DisasContext
*ctx
, int pc_off
,
488 TCGCond cond
, TCGv pred
)
490 target_ulong dest
= ctx
->pkt
->pc
+ pc_off
;
491 if (ctx
->pkt
->pkt_has_multi_cof
) {
492 gen_write_new_pc_addr(ctx
, tcg_constant_tl(dest
), cond
, pred
);
494 /* Defer this jump to the end of the TB */
495 ctx
->branch_cond
= TCG_COND_ALWAYS
;
497 ctx
->branch_cond
= cond
;
498 tcg_gen_mov_tl(hex_branch_taken
, pred
);
500 ctx
->branch_dest
= dest
;
504 void gen_set_usr_field(DisasContext
*ctx
, int field
, TCGv val
)
506 TCGv usr
= get_result_gpr(ctx
, HEX_REG_USR
);
507 tcg_gen_deposit_tl(usr
, usr
, val
,
508 reg_field_info
[field
].offset
,
509 reg_field_info
[field
].width
);
512 void gen_set_usr_fieldi(DisasContext
*ctx
, int field
, int x
)
514 if (reg_field_info
[field
].width
== 1) {
515 TCGv usr
= get_result_gpr(ctx
, HEX_REG_USR
);
516 target_ulong bit
= 1 << reg_field_info
[field
].offset
;
518 tcg_gen_ori_tl(usr
, usr
, bit
);
520 tcg_gen_andi_tl(usr
, usr
, ~bit
);
523 TCGv val
= tcg_constant_tl(x
);
524 gen_set_usr_field(ctx
, field
, val
);
528 static void gen_compare(TCGCond cond
, TCGv res
, TCGv arg1
, TCGv arg2
)
530 TCGv one
= tcg_constant_tl(0xff);
531 TCGv zero
= tcg_constant_tl(0);
533 tcg_gen_movcond_tl(cond
, res
, arg1
, arg2
, one
, zero
);
536 #ifndef CONFIG_HEXAGON_IDEF_PARSER
537 static inline void gen_loop0r(DisasContext
*ctx
, TCGv RsV
, int riV
)
541 gen_log_reg_write(ctx
, HEX_REG_LC0
, RsV
);
542 gen_log_reg_write(ctx
, HEX_REG_SA0
, tcg_constant_tl(ctx
->pkt
->pc
+ riV
));
543 gen_set_usr_fieldi(ctx
, USR_LPCFG
, 0);
546 static void gen_loop0i(DisasContext
*ctx
, int count
, int riV
)
548 gen_loop0r(ctx
, tcg_constant_tl(count
), riV
);
551 static inline void gen_loop1r(DisasContext
*ctx
, TCGv RsV
, int riV
)
555 gen_log_reg_write(ctx
, HEX_REG_LC1
, RsV
);
556 gen_log_reg_write(ctx
, HEX_REG_SA1
, tcg_constant_tl(ctx
->pkt
->pc
+ riV
));
559 static void gen_loop1i(DisasContext
*ctx
, int count
, int riV
)
561 gen_loop1r(ctx
, tcg_constant_tl(count
), riV
);
564 static void gen_ploopNsr(DisasContext
*ctx
, int N
, TCGv RsV
, int riV
)
568 gen_log_reg_write(ctx
, HEX_REG_LC0
, RsV
);
569 gen_log_reg_write(ctx
, HEX_REG_SA0
, tcg_constant_tl(ctx
->pkt
->pc
+ riV
));
570 gen_set_usr_fieldi(ctx
, USR_LPCFG
, N
);
571 gen_log_pred_write(ctx
, 3, tcg_constant_tl(0));
574 static void gen_ploopNsi(DisasContext
*ctx
, int N
, int count
, int riV
)
576 gen_ploopNsr(ctx
, N
, tcg_constant_tl(count
), riV
);
579 static inline void gen_comparei(TCGCond cond
, TCGv res
, TCGv arg1
, int arg2
)
581 gen_compare(cond
, res
, arg1
, tcg_constant_tl(arg2
));
585 static void gen_cond_jumpr(DisasContext
*ctx
, TCGv dst_pc
,
586 TCGCond cond
, TCGv pred
)
588 gen_write_new_pc_addr(ctx
, dst_pc
, cond
, pred
);
591 static void gen_cond_jumpr31(DisasContext
*ctx
, TCGCond cond
, TCGv pred
)
593 TCGv LSB
= tcg_temp_new();
594 tcg_gen_andi_tl(LSB
, pred
, 1);
595 gen_cond_jumpr(ctx
, hex_gpr
[HEX_REG_LR
], cond
, LSB
);
598 static void gen_cond_jump(DisasContext
*ctx
, TCGCond cond
, TCGv pred
,
601 gen_write_new_pc_pcrel(ctx
, pc_off
, cond
, pred
);
604 static void gen_cmpnd_cmp_jmp(DisasContext
*ctx
,
605 int pnum
, TCGCond cond1
, TCGv arg1
, TCGv arg2
,
606 TCGCond cond2
, int pc_off
)
608 if (ctx
->insn
->part1
) {
609 TCGv pred
= tcg_temp_new();
610 gen_compare(cond1
, pred
, arg1
, arg2
);
611 gen_log_pred_write(ctx
, pnum
, pred
);
613 TCGv pred
= tcg_temp_new();
614 tcg_gen_mov_tl(pred
, ctx
->new_pred_value
[pnum
]);
615 gen_cond_jump(ctx
, cond2
, pred
, pc_off
);
619 static void gen_cmpnd_cmp_jmp_t(DisasContext
*ctx
,
620 int pnum
, TCGCond cond
, TCGv arg1
, TCGv arg2
,
623 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, arg2
, TCG_COND_EQ
, pc_off
);
626 static void gen_cmpnd_cmp_jmp_f(DisasContext
*ctx
,
627 int pnum
, TCGCond cond
, TCGv arg1
, TCGv arg2
,
630 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, arg2
, TCG_COND_NE
, pc_off
);
633 static void gen_cmpnd_cmpi_jmp_t(DisasContext
*ctx
,
634 int pnum
, TCGCond cond
, TCGv arg1
, int arg2
,
637 TCGv tmp
= tcg_constant_tl(arg2
);
638 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, tmp
, TCG_COND_EQ
, pc_off
);
641 static void gen_cmpnd_cmpi_jmp_f(DisasContext
*ctx
,
642 int pnum
, TCGCond cond
, TCGv arg1
, int arg2
,
645 TCGv tmp
= tcg_constant_tl(arg2
);
646 gen_cmpnd_cmp_jmp(ctx
, pnum
, cond
, arg1
, tmp
, TCG_COND_NE
, pc_off
);
649 static void gen_cmpnd_cmp_n1_jmp_t(DisasContext
*ctx
, int pnum
, TCGCond cond
,
650 TCGv arg
, int pc_off
)
652 gen_cmpnd_cmpi_jmp_t(ctx
, pnum
, cond
, arg
, -1, pc_off
);
655 static void gen_cmpnd_cmp_n1_jmp_f(DisasContext
*ctx
, int pnum
, TCGCond cond
,
656 TCGv arg
, int pc_off
)
658 gen_cmpnd_cmpi_jmp_f(ctx
, pnum
, cond
, arg
, -1, pc_off
);
661 static void gen_cmpnd_tstbit0_jmp(DisasContext
*ctx
,
662 int pnum
, TCGv arg
, TCGCond cond
, int pc_off
)
664 if (ctx
->insn
->part1
) {
665 TCGv pred
= tcg_temp_new();
666 tcg_gen_andi_tl(pred
, arg
, 1);
667 gen_8bitsof(pred
, pred
);
668 gen_log_pred_write(ctx
, pnum
, pred
);
670 TCGv pred
= tcg_temp_new();
671 tcg_gen_mov_tl(pred
, ctx
->new_pred_value
[pnum
]);
672 gen_cond_jump(ctx
, cond
, pred
, pc_off
);
676 static void gen_testbit0_jumpnv(DisasContext
*ctx
,
677 TCGv arg
, TCGCond cond
, int pc_off
)
679 TCGv pred
= tcg_temp_new();
680 tcg_gen_andi_tl(pred
, arg
, 1);
681 gen_cond_jump(ctx
, cond
, pred
, pc_off
);
684 static void gen_jump(DisasContext
*ctx
, int pc_off
)
686 gen_write_new_pc_pcrel(ctx
, pc_off
, TCG_COND_ALWAYS
, NULL
);
689 static void gen_jumpr(DisasContext
*ctx
, TCGv new_pc
)
691 gen_write_new_pc_addr(ctx
, new_pc
, TCG_COND_ALWAYS
, NULL
);
694 static void gen_call(DisasContext
*ctx
, int pc_off
)
696 TCGv lr
= get_result_gpr(ctx
, HEX_REG_LR
);
697 tcg_gen_movi_tl(lr
, ctx
->next_PC
);
698 gen_write_new_pc_pcrel(ctx
, pc_off
, TCG_COND_ALWAYS
, NULL
);
701 static void gen_callr(DisasContext
*ctx
, TCGv new_pc
)
703 TCGv lr
= get_result_gpr(ctx
, HEX_REG_LR
);
704 tcg_gen_movi_tl(lr
, ctx
->next_PC
);
705 gen_write_new_pc_addr(ctx
, new_pc
, TCG_COND_ALWAYS
, NULL
);
708 static void gen_cond_call(DisasContext
*ctx
, TCGv pred
,
709 TCGCond cond
, int pc_off
)
711 TCGv lr
= get_result_gpr(ctx
, HEX_REG_LR
);
712 TCGv lsb
= tcg_temp_new();
713 TCGLabel
*skip
= gen_new_label();
714 tcg_gen_andi_tl(lsb
, pred
, 1);
715 gen_write_new_pc_pcrel(ctx
, pc_off
, cond
, lsb
);
716 tcg_gen_brcondi_tl(cond
, lsb
, 0, skip
);
717 tcg_gen_movi_tl(lr
, ctx
->next_PC
);
721 static void gen_cond_callr(DisasContext
*ctx
,
722 TCGCond cond
, TCGv pred
, TCGv new_pc
)
724 TCGv lsb
= tcg_temp_new();
725 TCGLabel
*skip
= gen_new_label();
726 tcg_gen_andi_tl(lsb
, pred
, 1);
727 tcg_gen_brcondi_tl(cond
, lsb
, 0, skip
);
728 gen_callr(ctx
, new_pc
);
732 #ifndef CONFIG_HEXAGON_IDEF_PARSER
733 /* frame = ((LR << 32) | FP) ^ (FRAMEKEY << 32)) */
734 static TCGv_i64
gen_frame_scramble(void)
736 TCGv_i64 frame
= tcg_temp_new_i64();
737 TCGv tmp
= tcg_temp_new();
738 tcg_gen_xor_tl(tmp
, hex_gpr
[HEX_REG_LR
], hex_gpr
[HEX_REG_FRAMEKEY
]);
739 tcg_gen_concat_i32_i64(frame
, hex_gpr
[HEX_REG_FP
], tmp
);
744 /* frame ^= (int64_t)FRAMEKEY << 32 */
745 static void gen_frame_unscramble(TCGv_i64 frame
)
747 TCGv_i64 framekey
= tcg_temp_new_i64();
748 tcg_gen_extu_i32_i64(framekey
, hex_gpr
[HEX_REG_FRAMEKEY
]);
749 tcg_gen_shli_i64(framekey
, framekey
, 32);
750 tcg_gen_xor_i64(frame
, frame
, framekey
);
753 static void gen_load_frame(DisasContext
*ctx
, TCGv_i64 frame
, TCGv EA
)
755 Insn
*insn
= ctx
->insn
; /* Needed for CHECK_NOSHUF */
757 tcg_gen_qemu_ld_i64(frame
, EA
, ctx
->mem_idx
, MO_TEUQ
);
760 #ifndef CONFIG_HEXAGON_IDEF_PARSER
761 /* Stack overflow check */
762 static void gen_framecheck(TCGv EA
, int framesize
)
764 /* Not modelled in linux-user mode */
765 /* Placeholder for system mode */
766 #ifndef CONFIG_USER_ONLY
767 g_assert_not_reached();
771 static void gen_allocframe(DisasContext
*ctx
, TCGv r29
, int framesize
)
773 TCGv r30
= tcg_temp_new();
775 tcg_gen_addi_tl(r30
, r29
, -8);
776 frame
= gen_frame_scramble();
777 gen_store8(cpu_env
, r30
, frame
, ctx
->insn
->slot
);
778 gen_log_reg_write(ctx
, HEX_REG_FP
, r30
);
779 gen_framecheck(r30
, framesize
);
780 tcg_gen_subi_tl(r29
, r30
, framesize
);
783 static void gen_deallocframe(DisasContext
*ctx
, TCGv_i64 r31_30
, TCGv r30
)
785 TCGv r29
= tcg_temp_new();
786 TCGv_i64 frame
= tcg_temp_new_i64();
787 gen_load_frame(ctx
, frame
, r30
);
788 gen_frame_unscramble(frame
);
789 tcg_gen_mov_i64(r31_30
, frame
);
790 tcg_gen_addi_tl(r29
, r30
, 8);
791 gen_log_reg_write(ctx
, HEX_REG_SP
, r29
);
795 static void gen_return(DisasContext
*ctx
, TCGv_i64 dst
, TCGv src
)
799 * dst = frame_unscramble(frame)
803 TCGv_i64 frame
= tcg_temp_new_i64();
804 TCGv r31
= tcg_temp_new();
805 TCGv r29
= get_result_gpr(ctx
, HEX_REG_SP
);
807 gen_load_frame(ctx
, frame
, src
);
808 gen_frame_unscramble(frame
);
809 tcg_gen_mov_i64(dst
, frame
);
810 tcg_gen_addi_tl(r29
, src
, 8);
811 tcg_gen_extrh_i64_i32(r31
, dst
);
815 /* if (pred) dst = dealloc_return(src):raw */
816 static void gen_cond_return(DisasContext
*ctx
, TCGv_i64 dst
, TCGv src
,
817 TCGv pred
, TCGCond cond
)
819 TCGv LSB
= tcg_temp_new();
820 TCGLabel
*skip
= gen_new_label();
821 tcg_gen_andi_tl(LSB
, pred
, 1);
823 tcg_gen_brcondi_tl(cond
, LSB
, 0, skip
);
824 gen_return(ctx
, dst
, src
);
828 /* sub-instruction version (no RddV, so handle it manually) */
829 static void gen_cond_return_subinsn(DisasContext
*ctx
, TCGCond cond
, TCGv pred
)
831 TCGv_i64 RddV
= get_result_gpr_pair(ctx
, HEX_REG_FP
);
832 gen_cond_return(ctx
, RddV
, hex_gpr
[HEX_REG_FP
], pred
, cond
);
833 gen_log_reg_write_pair(ctx
, HEX_REG_FP
, RddV
);
836 static void gen_endloop0(DisasContext
*ctx
)
838 TCGv lpcfg
= tcg_temp_new();
840 GET_USR_FIELD(USR_LPCFG
, lpcfg
);
847 TCGLabel
*label1
= gen_new_label();
848 tcg_gen_brcondi_tl(TCG_COND_NE
, lpcfg
, 1, label1
);
850 gen_log_pred_write(ctx
, 3, tcg_constant_tl(0xff));
852 gen_set_label(label1
);
856 * SET_USR_FIELD(USR_LPCFG, lpcfg - 1);
859 TCGLabel
*label2
= gen_new_label();
860 tcg_gen_brcondi_tl(TCG_COND_EQ
, lpcfg
, 0, label2
);
862 tcg_gen_subi_tl(lpcfg
, lpcfg
, 1);
863 gen_set_usr_field(ctx
, USR_LPCFG
, lpcfg
);
865 gen_set_label(label2
);
868 * If we're in a tight loop, we'll do this at the end of the TB to take
869 * advantage of direct block chaining.
871 if (!ctx
->is_tight_loop
) {
873 * if (hex_gpr[HEX_REG_LC0] > 1) {
874 * PC = hex_gpr[HEX_REG_SA0];
875 * hex_new_value[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1;
878 TCGLabel
*label3
= gen_new_label();
879 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC0
], 1, label3
);
881 TCGv lc0
= get_result_gpr(ctx
, HEX_REG_LC0
);
882 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA0
]);
883 tcg_gen_subi_tl(lc0
, hex_gpr
[HEX_REG_LC0
], 1);
885 gen_set_label(label3
);
889 static void gen_endloop1(DisasContext
*ctx
)
892 * if (hex_gpr[HEX_REG_LC1] > 1) {
893 * PC = hex_gpr[HEX_REG_SA1];
894 * hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1;
897 TCGLabel
*label
= gen_new_label();
898 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC1
], 1, label
);
900 TCGv lc1
= get_result_gpr(ctx
, HEX_REG_LC1
);
901 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA1
]);
902 tcg_gen_subi_tl(lc1
, hex_gpr
[HEX_REG_LC1
], 1);
904 gen_set_label(label
);
907 static void gen_endloop01(DisasContext
*ctx
)
909 TCGv lpcfg
= tcg_temp_new();
910 TCGLabel
*label1
= gen_new_label();
911 TCGLabel
*label2
= gen_new_label();
912 TCGLabel
*label3
= gen_new_label();
913 TCGLabel
*done
= gen_new_label();
915 GET_USR_FIELD(USR_LPCFG
, lpcfg
);
922 tcg_gen_brcondi_tl(TCG_COND_NE
, lpcfg
, 1, label1
);
924 gen_log_pred_write(ctx
, 3, tcg_constant_tl(0xff));
926 gen_set_label(label1
);
930 * SET_USR_FIELD(USR_LPCFG, lpcfg - 1);
933 tcg_gen_brcondi_tl(TCG_COND_EQ
, lpcfg
, 0, label2
);
935 tcg_gen_subi_tl(lpcfg
, lpcfg
, 1);
936 gen_set_usr_field(ctx
, USR_LPCFG
, lpcfg
);
938 gen_set_label(label2
);
941 * if (hex_gpr[HEX_REG_LC0] > 1) {
942 * PC = hex_gpr[HEX_REG_SA0];
943 * hex_new_value[HEX_REG_LC0] = hex_gpr[HEX_REG_LC0] - 1;
945 * if (hex_gpr[HEX_REG_LC1] > 1) {
946 * hex_next_pc = hex_gpr[HEX_REG_SA1];
947 * hex_new_value[HEX_REG_LC1] = hex_gpr[HEX_REG_LC1] - 1;
951 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC0
], 1, label3
);
953 TCGv lc0
= get_result_gpr(ctx
, HEX_REG_LC0
);
954 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA0
]);
955 tcg_gen_subi_tl(lc0
, hex_gpr
[HEX_REG_LC0
], 1);
958 gen_set_label(label3
);
959 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC1
], 1, done
);
961 TCGv lc1
= get_result_gpr(ctx
, HEX_REG_LC1
);
962 gen_jumpr(ctx
, hex_gpr
[HEX_REG_SA1
]);
963 tcg_gen_subi_tl(lc1
, hex_gpr
[HEX_REG_LC1
], 1);
968 static void gen_cmp_jumpnv(DisasContext
*ctx
,
969 TCGCond cond
, TCGv val
, TCGv src
, int pc_off
)
971 TCGv pred
= tcg_temp_new();
972 tcg_gen_setcond_tl(cond
, pred
, val
, src
);
973 gen_cond_jump(ctx
, TCG_COND_EQ
, pred
, pc_off
);
976 static void gen_cmpi_jumpnv(DisasContext
*ctx
,
977 TCGCond cond
, TCGv val
, int src
, int pc_off
)
979 TCGv pred
= tcg_temp_new();
980 tcg_gen_setcondi_tl(cond
, pred
, val
, src
);
981 gen_cond_jump(ctx
, TCG_COND_EQ
, pred
, pc_off
);
984 /* Shift left with saturation */
985 static void gen_shl_sat(DisasContext
*ctx
, TCGv dst
, TCGv src
, TCGv shift_amt
)
987 TCGv tmp
= tcg_temp_new(); /* In case dst == src */
988 TCGv usr
= get_result_gpr(ctx
, HEX_REG_USR
);
989 TCGv sh32
= tcg_temp_new();
990 TCGv dst_sar
= tcg_temp_new();
991 TCGv ovf
= tcg_temp_new();
992 TCGv satval
= tcg_temp_new();
993 TCGv min
= tcg_constant_tl(0x80000000);
994 TCGv max
= tcg_constant_tl(0x7fffffff);
997 * Possible values for shift_amt are 0 .. 64
998 * We need special handling for values above 31
1000 * sh32 = shift & 31;
1001 * dst = sh32 == shift ? src : 0;
1003 * dst_sar = dst >> sh32;
1004 * satval = src < 0 ? min : max;
1005 * if (dst_asr != src) {
1011 tcg_gen_andi_tl(sh32
, shift_amt
, 31);
1012 tcg_gen_movcond_tl(TCG_COND_EQ
, tmp
, sh32
, shift_amt
,
1013 src
, tcg_constant_tl(0));
1014 tcg_gen_shl_tl(tmp
, tmp
, sh32
);
1015 tcg_gen_sar_tl(dst_sar
, tmp
, sh32
);
1016 tcg_gen_movcond_tl(TCG_COND_LT
, satval
, src
, tcg_constant_tl(0), min
, max
);
1018 tcg_gen_setcond_tl(TCG_COND_NE
, ovf
, dst_sar
, src
);
1019 tcg_gen_shli_tl(ovf
, ovf
, reg_field_info
[USR_OVF
].offset
);
1020 tcg_gen_or_tl(usr
, usr
, ovf
);
1022 tcg_gen_movcond_tl(TCG_COND_EQ
, dst
, dst_sar
, src
, tmp
, satval
);
1025 static void gen_sar(TCGv dst
, TCGv src
, TCGv shift_amt
)
1028 * Shift arithmetic right
1029 * Robust when shift_amt is >31 bits
1031 TCGv tmp
= tcg_temp_new();
1032 tcg_gen_umin_tl(tmp
, shift_amt
, tcg_constant_tl(31));
1033 tcg_gen_sar_tl(dst
, src
, tmp
);
1036 /* Bidirectional shift right with saturation */
1037 static void gen_asr_r_r_sat(DisasContext
*ctx
, TCGv RdV
, TCGv RsV
, TCGv RtV
)
1039 TCGv shift_amt
= tcg_temp_new();
1040 TCGLabel
*positive
= gen_new_label();
1041 TCGLabel
*done
= gen_new_label();
1043 tcg_gen_sextract_i32(shift_amt
, RtV
, 0, 7);
1044 tcg_gen_brcondi_tl(TCG_COND_GE
, shift_amt
, 0, positive
);
1046 /* Negative shift amount => shift left */
1047 tcg_gen_neg_tl(shift_amt
, shift_amt
);
1048 gen_shl_sat(ctx
, RdV
, RsV
, shift_amt
);
1051 gen_set_label(positive
);
1052 /* Positive shift amount => shift right */
1053 gen_sar(RdV
, RsV
, shift_amt
);
1055 gen_set_label(done
);
1058 /* Bidirectional shift left with saturation */
1059 static void gen_asl_r_r_sat(DisasContext
*ctx
, TCGv RdV
, TCGv RsV
, TCGv RtV
)
1061 TCGv shift_amt
= tcg_temp_new();
1062 TCGLabel
*positive
= gen_new_label();
1063 TCGLabel
*done
= gen_new_label();
1065 tcg_gen_sextract_i32(shift_amt
, RtV
, 0, 7);
1066 tcg_gen_brcondi_tl(TCG_COND_GE
, shift_amt
, 0, positive
);
1068 /* Negative shift amount => shift right */
1069 tcg_gen_neg_tl(shift_amt
, shift_amt
);
1070 gen_sar(RdV
, RsV
, shift_amt
);
1073 gen_set_label(positive
);
1074 /* Positive shift amount => shift left */
1075 gen_shl_sat(ctx
, RdV
, RsV
, shift_amt
);
1077 gen_set_label(done
);
1080 static void gen_insert_rp(DisasContext
*ctx
, TCGv RxV
, TCGv RsV
, TCGv_i64 RttV
)
1083 * int width = fZXTN(6, 32, (fGETWORD(1, RttV)));
1084 * int offset = fSXTN(7, 32, (fGETWORD(0, RttV)));
1085 * size8u_t mask = ((fCONSTLL(1) << width) - 1);
1089 * RxV &= ~(mask << offset);
1090 * RxV |= ((RsV & mask) << offset);
1094 TCGv width
= tcg_temp_new();
1095 TCGv offset
= tcg_temp_new();
1096 TCGv_i64 mask
= tcg_temp_new_i64();
1097 TCGv_i64 result
= tcg_temp_new_i64();
1098 TCGv_i64 tmp
= tcg_temp_new_i64();
1099 TCGv_i64 offset64
= tcg_temp_new_i64();
1100 TCGLabel
*label
= gen_new_label();
1101 TCGLabel
*done
= gen_new_label();
1103 tcg_gen_extrh_i64_i32(width
, RttV
);
1104 tcg_gen_extract_tl(width
, width
, 0, 6);
1105 tcg_gen_extrl_i64_i32(offset
, RttV
);
1106 tcg_gen_sextract_tl(offset
, offset
, 0, 7);
1107 /* Possible values for offset are -64 .. 63 */
1108 tcg_gen_brcondi_tl(TCG_COND_GE
, offset
, 0, label
);
1109 /* For negative offsets, zero out the result */
1110 tcg_gen_movi_tl(RxV
, 0);
1112 gen_set_label(label
);
1113 /* At this point, possible values of offset are 0 .. 63 */
1114 tcg_gen_ext_i32_i64(mask
, width
);
1115 tcg_gen_shl_i64(mask
, tcg_constant_i64(1), mask
);
1116 tcg_gen_subi_i64(mask
, mask
, 1);
1117 tcg_gen_extu_i32_i64(result
, RxV
);
1118 tcg_gen_ext_i32_i64(tmp
, offset
);
1119 tcg_gen_shl_i64(tmp
, mask
, tmp
);
1120 tcg_gen_andc_i64(result
, result
, tmp
);
1121 tcg_gen_extu_i32_i64(tmp
, RsV
);
1122 tcg_gen_and_i64(tmp
, tmp
, mask
);
1123 tcg_gen_extu_i32_i64(offset64
, offset
);
1124 tcg_gen_shl_i64(tmp
, tmp
, offset64
);
1125 tcg_gen_or_i64(result
, result
, tmp
);
1126 tcg_gen_extrl_i64_i32(RxV
, result
);
1127 gen_set_label(done
);
1130 static void gen_asr_r_svw_trun(DisasContext
*ctx
, TCGv RdV
,
1131 TCGv_i64 RssV
, TCGv RtV
)
1134 * for (int i = 0; i < 2; i++) {
1135 * fSETHALF(i, RdV, fGETHALF(0, ((fSXTN(7, 32, RtV) > 0) ?
1136 * (fCAST4_8s(fGETWORD(i, RssV)) >> fSXTN(7, 32, RtV)) :
1137 * (fCAST4_8s(fGETWORD(i, RssV)) << -fSXTN(7, 32, RtV)))));
1140 TCGv shift_amt32
= tcg_temp_new();
1141 TCGv_i64 shift_amt64
= tcg_temp_new_i64();
1142 TCGv_i64 tmp64
= tcg_temp_new_i64();
1143 TCGv tmp32
= tcg_temp_new();
1144 TCGLabel
*label
= gen_new_label();
1145 TCGLabel
*zero
= gen_new_label();
1146 TCGLabel
*done
= gen_new_label();
1148 tcg_gen_sextract_tl(shift_amt32
, RtV
, 0, 7);
1149 /* Possible values of shift_amt32 are -64 .. 63 */
1150 tcg_gen_brcondi_tl(TCG_COND_LE
, shift_amt32
, 0, label
);
1151 /* After branch, possible values of shift_amt32 are 1 .. 63 */
1152 tcg_gen_ext_i32_i64(shift_amt64
, shift_amt32
);
1153 for (int i
= 0; i
< 2; i
++) {
1154 tcg_gen_sextract_i64(tmp64
, RssV
, i
* 32, 32);
1155 tcg_gen_sar_i64(tmp64
, tmp64
, shift_amt64
);
1156 tcg_gen_extrl_i64_i32(tmp32
, tmp64
);
1157 tcg_gen_deposit_tl(RdV
, RdV
, tmp32
, i
* 16, 16);
1160 gen_set_label(label
);
1161 tcg_gen_neg_tl(shift_amt32
, shift_amt32
);
1162 /*At this point, possible values of shift_amt32 are 0 .. 64 */
1163 tcg_gen_brcondi_tl(TCG_COND_GT
, shift_amt32
, 63, zero
);
1164 /*At this point, possible values of shift_amt32 are 0 .. 63 */
1165 tcg_gen_ext_i32_i64(shift_amt64
, shift_amt32
);
1166 for (int i
= 0; i
< 2; i
++) {
1167 tcg_gen_sextract_i64(tmp64
, RssV
, i
* 32, 32);
1168 tcg_gen_shl_i64(tmp64
, tmp64
, shift_amt64
);
1169 tcg_gen_extrl_i64_i32(tmp32
, tmp64
);
1170 tcg_gen_deposit_tl(RdV
, RdV
, tmp32
, i
* 16, 16);
1173 gen_set_label(zero
);
1174 /* When the shift_amt is 64, zero out the result */
1175 tcg_gen_movi_tl(RdV
, 0);
1176 gen_set_label(done
);
1179 static intptr_t vreg_src_off(DisasContext
*ctx
, int num
)
1181 intptr_t offset
= offsetof(CPUHexagonState
, VRegs
[num
]);
1183 if (test_bit(num
, ctx
->vregs_select
)) {
1184 offset
= ctx_future_vreg_off(ctx
, num
, 1, false);
1186 if (test_bit(num
, ctx
->vregs_updated_tmp
)) {
1187 offset
= ctx_tmp_vreg_off(ctx
, num
, 1, false);
1192 static void gen_log_vreg_write(DisasContext
*ctx
, intptr_t srcoff
, int num
,
1197 if (type
!= EXT_TMP
) {
1198 dstoff
= ctx_future_vreg_off(ctx
, num
, 1, true);
1199 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
,
1200 sizeof(MMVector
), sizeof(MMVector
));
1202 dstoff
= ctx_tmp_vreg_off(ctx
, num
, 1, false);
1203 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
,
1204 sizeof(MMVector
), sizeof(MMVector
));
1208 static void gen_log_vreg_write_pair(DisasContext
*ctx
, intptr_t srcoff
, int num
,
1211 gen_log_vreg_write(ctx
, srcoff
, num
^ 0, type
);
1212 srcoff
+= sizeof(MMVector
);
1213 gen_log_vreg_write(ctx
, srcoff
, num
^ 1, type
);
1216 static intptr_t get_result_qreg(DisasContext
*ctx
, int qnum
)
1218 if (ctx
->need_commit
) {
1219 return offsetof(CPUHexagonState
, future_QRegs
[qnum
]);
1221 return offsetof(CPUHexagonState
, QRegs
[qnum
]);
1225 static void gen_vreg_load(DisasContext
*ctx
, intptr_t dstoff
, TCGv src
,
1228 TCGv_i64 tmp
= tcg_temp_new_i64();
1230 tcg_gen_andi_tl(src
, src
, ~((int32_t)sizeof(MMVector
) - 1));
1232 for (int i
= 0; i
< sizeof(MMVector
) / 8; i
++) {
1233 tcg_gen_qemu_ld_i64(tmp
, src
, ctx
->mem_idx
, MO_TEUQ
);
1234 tcg_gen_addi_tl(src
, src
, 8);
1235 tcg_gen_st_i64(tmp
, cpu_env
, dstoff
+ i
* 8);
1239 static void gen_vreg_store(DisasContext
*ctx
, TCGv EA
, intptr_t srcoff
,
1240 int slot
, bool aligned
)
1242 intptr_t dstoff
= offsetof(CPUHexagonState
, vstore
[slot
].data
);
1243 intptr_t maskoff
= offsetof(CPUHexagonState
, vstore
[slot
].mask
);
1245 if (is_gather_store_insn(ctx
)) {
1246 TCGv sl
= tcg_constant_tl(slot
);
1247 gen_helper_gather_store(cpu_env
, EA
, sl
);
1251 tcg_gen_movi_tl(hex_vstore_pending
[slot
], 1);
1253 tcg_gen_andi_tl(hex_vstore_addr
[slot
], EA
,
1254 ~((int32_t)sizeof(MMVector
) - 1));
1256 tcg_gen_mov_tl(hex_vstore_addr
[slot
], EA
);
1258 tcg_gen_movi_tl(hex_vstore_size
[slot
], sizeof(MMVector
));
1260 /* Copy the data to the vstore buffer */
1261 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, sizeof(MMVector
), sizeof(MMVector
));
1262 /* Set the mask to all 1's */
1263 tcg_gen_gvec_dup_imm(MO_64
, maskoff
, sizeof(MMQReg
), sizeof(MMQReg
), ~0LL);
1266 static void gen_vreg_masked_store(DisasContext
*ctx
, TCGv EA
, intptr_t srcoff
,
1267 intptr_t bitsoff
, int slot
, bool invert
)
1269 intptr_t dstoff
= offsetof(CPUHexagonState
, vstore
[slot
].data
);
1270 intptr_t maskoff
= offsetof(CPUHexagonState
, vstore
[slot
].mask
);
1272 tcg_gen_movi_tl(hex_vstore_pending
[slot
], 1);
1273 tcg_gen_andi_tl(hex_vstore_addr
[slot
], EA
,
1274 ~((int32_t)sizeof(MMVector
) - 1));
1275 tcg_gen_movi_tl(hex_vstore_size
[slot
], sizeof(MMVector
));
1277 /* Copy the data to the vstore buffer */
1278 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, sizeof(MMVector
), sizeof(MMVector
));
1280 tcg_gen_gvec_mov(MO_64
, maskoff
, bitsoff
, sizeof(MMQReg
), sizeof(MMQReg
));
1282 tcg_gen_gvec_not(MO_64
, maskoff
, maskoff
,
1283 sizeof(MMQReg
), sizeof(MMQReg
));
1287 static void vec_to_qvec(size_t size
, intptr_t dstoff
, intptr_t srcoff
)
1289 TCGv_i64 tmp
= tcg_temp_new_i64();
1290 TCGv_i64 word
= tcg_temp_new_i64();
1291 TCGv_i64 bits
= tcg_temp_new_i64();
1292 TCGv_i64 mask
= tcg_temp_new_i64();
1293 TCGv_i64 zero
= tcg_constant_i64(0);
1294 TCGv_i64 ones
= tcg_constant_i64(~0);
1296 for (int i
= 0; i
< sizeof(MMVector
) / 8; i
++) {
1297 tcg_gen_ld_i64(tmp
, cpu_env
, srcoff
+ i
* 8);
1298 tcg_gen_movi_i64(mask
, 0);
1300 for (int j
= 0; j
< 8; j
+= size
) {
1301 tcg_gen_extract_i64(word
, tmp
, j
* 8, size
* 8);
1302 tcg_gen_movcond_i64(TCG_COND_NE
, bits
, word
, zero
, ones
, zero
);
1303 tcg_gen_deposit_i64(mask
, mask
, bits
, j
, size
);
1306 tcg_gen_st8_i64(mask
, cpu_env
, dstoff
+ i
);
1310 void probe_noshuf_load(TCGv va
, int s
, int mi
)
1312 TCGv size
= tcg_constant_tl(s
);
1313 TCGv mem_idx
= tcg_constant_tl(mi
);
1314 gen_helper_probe_noshuf_load(cpu_env
, va
, size
, mem_idx
);
1318 * Note: Since this function might branch, `val` is
1319 * required to be a `tcg_temp_local`.
1321 void gen_set_usr_field_if(DisasContext
*ctx
, int field
, TCGv val
)
1323 /* Sets the USR field if `val` is non-zero */
1324 if (reg_field_info
[field
].width
== 1) {
1325 TCGv usr
= get_result_gpr(ctx
, HEX_REG_USR
);
1326 TCGv tmp
= tcg_temp_new();
1327 tcg_gen_extract_tl(tmp
, val
, 0, reg_field_info
[field
].width
);
1328 tcg_gen_shli_tl(tmp
, tmp
, reg_field_info
[field
].offset
);
1329 tcg_gen_or_tl(usr
, usr
, tmp
);
1331 TCGLabel
*skip_label
= gen_new_label();
1332 tcg_gen_brcondi_tl(TCG_COND_EQ
, val
, 0, skip_label
);
1333 gen_set_usr_field(ctx
, field
, val
);
1334 gen_set_label(skip_label
);
1338 void gen_sat_i32(TCGv dest
, TCGv source
, int width
)
1340 TCGv max_val
= tcg_constant_tl((1 << (width
- 1)) - 1);
1341 TCGv min_val
= tcg_constant_tl(-(1 << (width
- 1)));
1342 tcg_gen_smin_tl(dest
, source
, max_val
);
1343 tcg_gen_smax_tl(dest
, dest
, min_val
);
1346 void gen_sat_i32_ovfl(TCGv ovfl
, TCGv dest
, TCGv source
, int width
)
1348 TCGv tmp
= tcg_temp_new(); /* In case dest == source */
1349 gen_sat_i32(tmp
, source
, width
);
1350 tcg_gen_setcond_tl(TCG_COND_NE
, ovfl
, source
, tmp
);
1351 tcg_gen_mov_tl(dest
, tmp
);
1354 void gen_satu_i32(TCGv dest
, TCGv source
, int width
)
1356 TCGv tmp
= tcg_temp_new(); /* In case dest == source */
1357 TCGv max_val
= tcg_constant_tl((1 << width
) - 1);
1358 TCGv zero
= tcg_constant_tl(0);
1359 tcg_gen_movcond_tl(TCG_COND_GTU
, tmp
, source
, max_val
, max_val
, source
);
1360 tcg_gen_movcond_tl(TCG_COND_LT
, tmp
, source
, zero
, zero
, tmp
);
1361 tcg_gen_mov_tl(dest
, tmp
);
1364 void gen_satu_i32_ovfl(TCGv ovfl
, TCGv dest
, TCGv source
, int width
)
1366 TCGv tmp
= tcg_temp_new(); /* In case dest == source */
1367 gen_satu_i32(tmp
, source
, width
);
1368 tcg_gen_setcond_tl(TCG_COND_NE
, ovfl
, source
, tmp
);
1369 tcg_gen_mov_tl(dest
, tmp
);
1372 void gen_sat_i64(TCGv_i64 dest
, TCGv_i64 source
, int width
)
1374 TCGv_i64 max_val
= tcg_constant_i64((1LL << (width
- 1)) - 1LL);
1375 TCGv_i64 min_val
= tcg_constant_i64(-(1LL << (width
- 1)));
1376 tcg_gen_smin_i64(dest
, source
, max_val
);
1377 tcg_gen_smax_i64(dest
, dest
, min_val
);
1380 void gen_sat_i64_ovfl(TCGv ovfl
, TCGv_i64 dest
, TCGv_i64 source
, int width
)
1382 TCGv_i64 tmp
= tcg_temp_new_i64(); /* In case dest == source */
1384 gen_sat_i64(tmp
, source
, width
);
1385 ovfl_64
= tcg_temp_new_i64();
1386 tcg_gen_setcond_i64(TCG_COND_NE
, ovfl_64
, tmp
, source
);
1387 tcg_gen_mov_i64(dest
, tmp
);
1388 tcg_gen_trunc_i64_tl(ovfl
, ovfl_64
);
1391 void gen_satu_i64(TCGv_i64 dest
, TCGv_i64 source
, int width
)
1393 TCGv_i64 tmp
= tcg_temp_new_i64(); /* In case dest == source */
1394 TCGv_i64 max_val
= tcg_constant_i64((1LL << width
) - 1LL);
1395 TCGv_i64 zero
= tcg_constant_i64(0);
1396 tcg_gen_movcond_i64(TCG_COND_GTU
, tmp
, source
, max_val
, max_val
, source
);
1397 tcg_gen_movcond_i64(TCG_COND_LT
, tmp
, source
, zero
, zero
, tmp
);
1398 tcg_gen_mov_i64(dest
, tmp
);
1401 void gen_satu_i64_ovfl(TCGv ovfl
, TCGv_i64 dest
, TCGv_i64 source
, int width
)
1403 TCGv_i64 tmp
= tcg_temp_new_i64(); /* In case dest == source */
1405 gen_satu_i64(tmp
, source
, width
);
1406 ovfl_64
= tcg_temp_new_i64();
1407 tcg_gen_setcond_i64(TCG_COND_NE
, ovfl_64
, tmp
, source
);
1408 tcg_gen_mov_i64(dest
, tmp
);
1409 tcg_gen_trunc_i64_tl(ovfl
, ovfl_64
);
1412 /* Implements the fADDSAT64 macro in TCG */
1413 void gen_add_sat_i64(DisasContext
*ctx
, TCGv_i64 ret
, TCGv_i64 a
, TCGv_i64 b
)
1415 TCGv_i64 sum
= tcg_temp_new_i64();
1416 TCGv_i64
xor = tcg_temp_new_i64();
1417 TCGv_i64 cond1
= tcg_temp_new_i64();
1418 TCGv_i64 cond2
= tcg_temp_new_i64();
1419 TCGv_i64 cond3
= tcg_temp_new_i64();
1420 TCGv_i64 mask
= tcg_constant_i64(0x8000000000000000ULL
);
1421 TCGv_i64 max_pos
= tcg_constant_i64(0x7FFFFFFFFFFFFFFFLL
);
1422 TCGv_i64 max_neg
= tcg_constant_i64(0x8000000000000000LL
);
1423 TCGv_i64 zero
= tcg_constant_i64(0);
1424 TCGLabel
*no_ovfl_label
= gen_new_label();
1425 TCGLabel
*ovfl_label
= gen_new_label();
1426 TCGLabel
*ret_label
= gen_new_label();
1428 tcg_gen_add_i64(sum
, a
, b
);
1429 tcg_gen_xor_i64(xor, a
, b
);
1431 /* if (xor & mask) */
1432 tcg_gen_and_i64(cond1
, xor, mask
);
1433 tcg_gen_brcondi_i64(TCG_COND_NE
, cond1
, 0, no_ovfl_label
);
1435 /* else if ((a ^ sum) & mask) */
1436 tcg_gen_xor_i64(cond2
, a
, sum
);
1437 tcg_gen_and_i64(cond2
, cond2
, mask
);
1438 tcg_gen_brcondi_i64(TCG_COND_NE
, cond2
, 0, ovfl_label
);
1439 /* fallthrough to no_ovfl_label branch */
1442 gen_set_label(no_ovfl_label
);
1443 tcg_gen_mov_i64(ret
, sum
);
1444 tcg_gen_br(ret_label
);
1446 /* else if branch */
1447 gen_set_label(ovfl_label
);
1448 tcg_gen_and_i64(cond3
, sum
, mask
);
1449 tcg_gen_movcond_i64(TCG_COND_NE
, ret
, cond3
, zero
, max_pos
, max_neg
);
1450 gen_set_usr_fieldi(ctx
, USR_OVF
, 1);
1452 gen_set_label(ret_label
);
1455 #include "tcg_funcs_generated.c.inc"
1456 #include "tcg_func_table_generated.c.inc"