target/hexagon/genptr.c

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "cpu.h"
  20 #include "internal.h"
  21 #include "tcg/tcg-op.h"
  22 #include "insn.h"
  23 #include "opcodes.h"
  24 #include "translate.h"
  25 #define QEMU_GENERATE       /* Used internally by macros.h */
  26 #include "macros.h"
  27 #undef QEMU_GENERATE
  28 #include "gen_tcg.h"
  29
  30 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
  31 {
  32     TCGv zero = tcg_const_tl(0);
  33     TCGv slot_mask = tcg_temp_new();
  34
  35     tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
  36     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
  37                            val, hex_new_value[rnum]);
  38     if (HEX_DEBUG) {
  39         /*
  40          * Do this so HELPER(debug_commit_end) will know
  41          *
  42          * Note that slot_mask indicates the value is not written
  43          * (i.e., slot was cancelled), so we create a true/false value before
  44          * or'ing with hex_reg_written[rnum].
  45          */
  46         tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
  47         tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
  48     }
  49
  50     tcg_temp_free(zero);
  51     tcg_temp_free(slot_mask);
  52 }
  53
  54 static inline void gen_log_reg_write(int rnum, TCGv val)
  55 {
  56     tcg_gen_mov_tl(hex_new_value[rnum], val);
  57     if (HEX_DEBUG) {
  58         /* Do this so HELPER(debug_commit_end) will know */
  59         tcg_gen_movi_tl(hex_reg_written[rnum], 1);
  60     }
  61 }
  62
  63 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
  64 {
  65     TCGv val32 = tcg_temp_new();
  66     TCGv zero = tcg_const_tl(0);
  67     TCGv slot_mask = tcg_temp_new();
  68
  69     tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
  70     /* Low word */
  71     tcg_gen_extrl_i64_i32(val32, val);
  72     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum],
  73                        slot_mask, zero,
  74                        val32, hex_new_value[rnum]);
  75     /* High word */
  76     tcg_gen_extrh_i64_i32(val32, val);
  77     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
  78                        slot_mask, zero,
  79                        val32, hex_new_value[rnum + 1]);
  80     if (HEX_DEBUG) {
  81         /*
  82          * Do this so HELPER(debug_commit_end) will know
  83          *
  84          * Note that slot_mask indicates the value is not written
  85          * (i.e., slot was cancelled), so we create a true/false value before
  86          * or'ing with hex_reg_written[rnum].
  87          */
  88         tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
  89         tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
  90         tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
  91                       slot_mask);
  92     }
  93
  94     tcg_temp_free(val32);
  95     tcg_temp_free(zero);
  96     tcg_temp_free(slot_mask);
  97 }
  98
  99 static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
 100 {
 101     /* Low word */
 102     tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
 103     if (HEX_DEBUG) {
 104         /* Do this so HELPER(debug_commit_end) will know */
 105         tcg_gen_movi_tl(hex_reg_written[rnum], 1);
 106     }
 107
 108     /* High word */
 109     tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
 110     if (HEX_DEBUG) {
 111         /* Do this so HELPER(debug_commit_end) will know */
 112         tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
 113     }
 114 }
 115
 116 static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
 117 {
 118     TCGv zero = tcg_const_tl(0);
 119     TCGv base_val = tcg_temp_new();
 120     TCGv and_val = tcg_temp_new();
 121     TCGv pred_written = tcg_temp_new();
 122
 123     tcg_gen_andi_tl(base_val, val, 0xff);
 124
 125     /*
 126      * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual
 127      *
 128      * Multiple writes to the same preg are and'ed together
 129      * If this is the first predicate write in the packet, do a
 130      * straight assignment.  Otherwise, do an and.
 131      */
 132     if (!test_bit(pnum, ctx->pregs_written)) {
 133         tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val);
 134     } else {
 135         tcg_gen_and_tl(hex_new_pred_value[pnum],
 136                        hex_new_pred_value[pnum], base_val);
 137     }
 138     tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
 139
 140     tcg_temp_free(zero);
 141     tcg_temp_free(base_val);
 142     tcg_temp_free(and_val);
 143     tcg_temp_free(pred_written);
 144 }
 145
 146 static inline void gen_read_p3_0(TCGv control_reg)
 147 {
 148     tcg_gen_movi_tl(control_reg, 0);
 149     for (int i = 0; i < NUM_PREGS; i++) {
 150         tcg_gen_deposit_tl(control_reg, control_reg, hex_pred[i], i * 8, 8);
 151     }
 152 }
 153
 154 /*
 155  * Certain control registers require special handling on read
 156  *     HEX_REG_P3_0          aliased to the predicate registers
 157  *                           -> concat the 4 predicate registers together
 158  *     HEX_REG_PC            actual value stored in DisasContext
 159  *                           -> assign from ctx->base.pc_next
 160  *     HEX_REG_QEMU_*_CNT    changes in current TB in DisasContext
 161  *                           -> add current TB changes to existing reg value
 162  */
 163 static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
 164                                      TCGv dest)
 165 {
 166     if (reg_num == HEX_REG_P3_0) {
 167         gen_read_p3_0(dest);
 168     } else if (reg_num == HEX_REG_PC) {
 169         tcg_gen_movi_tl(dest, ctx->base.pc_next);
 170     } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 171         tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_PKT_CNT],
 172                         ctx->num_packets);
 173     } else if (reg_num == HEX_REG_QEMU_INSN_CNT) {
 174         tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT],
 175                         ctx->num_insns);
 176     } else {
 177         tcg_gen_mov_tl(dest, hex_gpr[reg_num]);
 178     }
 179 }
 180
 181 static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
 182                                           TCGv_i64 dest)
 183 {
 184     if (reg_num == HEX_REG_P3_0) {
 185         TCGv p3_0 = tcg_temp_new();
 186         gen_read_p3_0(p3_0);
 187         tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
 188         tcg_temp_free(p3_0);
 189     } else if (reg_num == HEX_REG_PC - 1) {
 190         TCGv pc = tcg_const_tl(ctx->base.pc_next);
 191         tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc);
 192         tcg_temp_free(pc);
 193     } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 194         TCGv pkt_cnt = tcg_temp_new();
 195         TCGv insn_cnt = tcg_temp_new();
 196         tcg_gen_addi_tl(pkt_cnt, hex_gpr[HEX_REG_QEMU_PKT_CNT],
 197                         ctx->num_packets);
 198         tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT],
 199                         ctx->num_insns);
 200         tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt);
 201         tcg_temp_free(pkt_cnt);
 202         tcg_temp_free(insn_cnt);
 203     } else {
 204         tcg_gen_concat_i32_i64(dest,
 205             hex_gpr[reg_num],
 206             hex_gpr[reg_num + 1]);
 207     }
 208 }
 209
 210 static inline void gen_write_p3_0(TCGv control_reg)
 211 {
 212     for (int i = 0; i < NUM_PREGS; i++) {
 213         tcg_gen_extract_tl(hex_pred[i], control_reg, i * 8, 8);
 214     }
 215 }
 216
 217 /*
 218  * Certain control registers require special handling on write
 219  *     HEX_REG_P3_0          aliased to the predicate registers
 220  *                           -> break the value across 4 predicate registers
 221  *     HEX_REG_QEMU_*_CNT    changes in current TB in DisasContext
 222  *                            -> clear the changes
 223  */
 224 static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
 225                                       TCGv val)
 226 {
 227     if (reg_num == HEX_REG_P3_0) {
 228         gen_write_p3_0(val);
 229     } else {
 230         gen_log_reg_write(reg_num, val);
 231         ctx_log_reg_write(ctx, reg_num);
 232         if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 233             ctx->num_packets = 0;
 234         }
 235         if (reg_num == HEX_REG_QEMU_INSN_CNT) {
 236             ctx->num_insns = 0;
 237         }
 238     }
 239 }
 240
 241 static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
 242                                            TCGv_i64 val)
 243 {
 244     if (reg_num == HEX_REG_P3_0) {
 245         TCGv val32 = tcg_temp_new();
 246         tcg_gen_extrl_i64_i32(val32, val);
 247         gen_write_p3_0(val32);
 248         tcg_gen_extrh_i64_i32(val32, val);
 249         gen_log_reg_write(reg_num + 1, val32);
 250         tcg_temp_free(val32);
 251         ctx_log_reg_write(ctx, reg_num + 1);
 252     } else {
 253         gen_log_reg_write_pair(reg_num, val);
 254         ctx_log_reg_write_pair(ctx, reg_num);
 255         if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 256             ctx->num_packets = 0;
 257             ctx->num_insns = 0;
 258         }
 259     }
 260 }
 261
 262 static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
 263 {
 264     if (sign) {
 265         tcg_gen_sextract_tl(result, src, N * 8, 8);
 266     } else {
 267         tcg_gen_extract_tl(result, src, N * 8, 8);
 268     }
 269     return result;
 270 }
 271
 272 static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
 273 {
 274     TCGv_i64 res64 = tcg_temp_new_i64();
 275     if (sign) {
 276         tcg_gen_sextract_i64(res64, src, N * 8, 8);
 277     } else {
 278         tcg_gen_extract_i64(res64, src, N * 8, 8);
 279     }
 280     tcg_gen_extrl_i64_i32(result, res64);
 281     tcg_temp_free_i64(res64);
 282
 283     return result;
 284 }
 285
 286 static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
 287 {
 288     if (sign) {
 289         tcg_gen_sextract_tl(result, src, N * 16, 16);
 290     } else {
 291         tcg_gen_extract_tl(result, src, N * 16, 16);
 292     }
 293     return result;
 294 }
 295
 296 static inline void gen_set_half(int N, TCGv result, TCGv src)
 297 {
 298     tcg_gen_deposit_tl(result, result, src, N * 16, 16);
 299 }
 300
 301 static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
 302 {
 303     TCGv_i64 src64 = tcg_temp_new_i64();
 304     tcg_gen_extu_i32_i64(src64, src);
 305     tcg_gen_deposit_i64(result, result, src64, N * 16, 16);
 306     tcg_temp_free_i64(src64);
 307 }
 308
 309 static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
 310 {
 311     TCGv_i64 src64 = tcg_temp_new_i64();
 312     tcg_gen_extu_i32_i64(src64, src);
 313     tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
 314     tcg_temp_free_i64(src64);
 315 }
 316
 317 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
 318 {
 319     tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
 320     tcg_gen_mov_tl(hex_llsc_addr, vaddr);
 321     tcg_gen_mov_tl(hex_llsc_val, dest);
 322 }
 323
 324 static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
 325 {
 326     tcg_gen_qemu_ld64(dest, vaddr, mem_index);
 327     tcg_gen_mov_tl(hex_llsc_addr, vaddr);
 328     tcg_gen_mov_i64(hex_llsc_val_i64, dest);
 329 }
 330
 331 static inline void gen_store_conditional4(DisasContext *ctx,
 332                                           TCGv pred, TCGv vaddr, TCGv src)
 333 {
 334     TCGLabel *fail = gen_new_label();
 335     TCGLabel *done = gen_new_label();
 336     TCGv one, zero, tmp;
 337
 338     tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
 339
 340     one = tcg_const_tl(0xff);
 341     zero = tcg_const_tl(0);
 342     tmp = tcg_temp_new();
 343     tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
 344                               ctx->mem_idx, MO_32);
 345     tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val,
 346                        one, zero);
 347     tcg_temp_free(one);
 348     tcg_temp_free(zero);
 349     tcg_temp_free(tmp);
 350     tcg_gen_br(done);
 351
 352     gen_set_label(fail);
 353     tcg_gen_movi_tl(pred, 0);
 354
 355     gen_set_label(done);
 356     tcg_gen_movi_tl(hex_llsc_addr, ~0);
 357 }
 358
 359 static inline void gen_store_conditional8(DisasContext *ctx,
 360                                           TCGv pred, TCGv vaddr, TCGv_i64 src)
 361 {
 362     TCGLabel *fail = gen_new_label();
 363     TCGLabel *done = gen_new_label();
 364     TCGv_i64 one, zero, tmp;
 365
 366     tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
 367
 368     one = tcg_const_i64(0xff);
 369     zero = tcg_const_i64(0);
 370     tmp = tcg_temp_new_i64();
 371     tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src,
 372                                ctx->mem_idx, MO_64);
 373     tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
 374                         one, zero);
 375     tcg_gen_extrl_i64_i32(pred, tmp);
 376     tcg_temp_free_i64(one);
 377     tcg_temp_free_i64(zero);
 378     tcg_temp_free_i64(tmp);
 379     tcg_gen_br(done);
 380
 381     gen_set_label(fail);
 382     tcg_gen_movi_tl(pred, 0);
 383
 384     gen_set_label(done);
 385     tcg_gen_movi_tl(hex_llsc_addr, ~0);
 386 }
 387
 388 static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
 389 {
 390     tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 391     tcg_gen_movi_tl(hex_store_width[slot], width);
 392     tcg_gen_mov_tl(hex_store_val32[slot], src);
 393 }
 394
 395 static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
 396                               DisasContext *ctx, int slot)
 397 {
 398     gen_store32(vaddr, src, 1, slot);
 399     ctx->store_width[slot] = 1;
 400 }
 401
 402 static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
 403                                DisasContext *ctx, int slot)
 404 {
 405     TCGv tmp = tcg_const_tl(src);
 406     gen_store1(cpu_env, vaddr, tmp, ctx, slot);
 407     tcg_temp_free(tmp);
 408 }
 409
 410 static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
 411                               DisasContext *ctx, int slot)
 412 {
 413     gen_store32(vaddr, src, 2, slot);
 414     ctx->store_width[slot] = 2;
 415 }
 416
 417 static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
 418                                DisasContext *ctx, int slot)
 419 {
 420     TCGv tmp = tcg_const_tl(src);
 421     gen_store2(cpu_env, vaddr, tmp, ctx, slot);
 422     tcg_temp_free(tmp);
 423 }
 424
 425 static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
 426                               DisasContext *ctx, int slot)
 427 {
 428     gen_store32(vaddr, src, 4, slot);
 429     ctx->store_width[slot] = 4;
 430 }
 431
 432 static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
 433                                DisasContext *ctx, int slot)
 434 {
 435     TCGv tmp = tcg_const_tl(src);
 436     gen_store4(cpu_env, vaddr, tmp, ctx, slot);
 437     tcg_temp_free(tmp);
 438 }
 439
 440 static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
 441                               DisasContext *ctx, int slot)
 442 {
 443     tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 444     tcg_gen_movi_tl(hex_store_width[slot], 8);
 445     tcg_gen_mov_i64(hex_store_val64[slot], src);
 446     ctx->store_width[slot] = 8;
 447 }
 448
 449 static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
 450                                DisasContext *ctx, int slot)
 451 {
 452     TCGv_i64 tmp = tcg_const_i64(src);
 453     gen_store8(cpu_env, vaddr, tmp, ctx, slot);
 454     tcg_temp_free_i64(tmp);
 455 }
 456
 457 static TCGv gen_8bitsof(TCGv result, TCGv value)
 458 {
 459     TCGv zero = tcg_const_tl(0);
 460     TCGv ones = tcg_const_tl(0xff);
 461     tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero);
 462     tcg_temp_free(zero);
 463     tcg_temp_free(ones);
 464
 465     return result;
 466 }
 467
 468 #include "tcg_funcs_generated.c.inc"
 469 #include "tcg_func_table_generated.c.inc"