target/hexagon/genptr.c

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include "qemu/osdep.h"
  19 #include "cpu.h"
  20 #include "internal.h"
  21 #include "tcg/tcg-op.h"
  22 #include "insn.h"
  23 #include "opcodes.h"
  24 #include "translate.h"
  25 #define QEMU_GENERATE       /* Used internally by macros.h */
  26 #include "macros.h"
  27 #undef QEMU_GENERATE
  28 #include "gen_tcg.h"
  29
  30 static inline void gen_log_predicated_reg_write(int rnum, TCGv val, int slot)
  31 {
  32     TCGv zero = tcg_constant_tl(0);
  33     TCGv slot_mask = tcg_temp_new();
  34
  35     tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
  36     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero,
  37                            val, hex_new_value[rnum]);
  38     if (HEX_DEBUG) {
  39         /*
  40          * Do this so HELPER(debug_commit_end) will know
  41          *
  42          * Note that slot_mask indicates the value is not written
  43          * (i.e., slot was cancelled), so we create a true/false value before
  44          * or'ing with hex_reg_written[rnum].
  45          */
  46         tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
  47         tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
  48     }
  49
  50     tcg_temp_free(slot_mask);
  51 }
  52
  53 static inline void gen_log_reg_write(int rnum, TCGv val)
  54 {
  55     tcg_gen_mov_tl(hex_new_value[rnum], val);
  56     if (HEX_DEBUG) {
  57         /* Do this so HELPER(debug_commit_end) will know */
  58         tcg_gen_movi_tl(hex_reg_written[rnum], 1);
  59     }
  60 }
  61
  62 static void gen_log_predicated_reg_write_pair(int rnum, TCGv_i64 val, int slot)
  63 {
  64     TCGv val32 = tcg_temp_new();
  65     TCGv zero = tcg_constant_tl(0);
  66     TCGv slot_mask = tcg_temp_new();
  67
  68     tcg_gen_andi_tl(slot_mask, hex_slot_cancelled, 1 << slot);
  69     /* Low word */
  70     tcg_gen_extrl_i64_i32(val32, val);
  71     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum],
  72                        slot_mask, zero,
  73                        val32, hex_new_value[rnum]);
  74     /* High word */
  75     tcg_gen_extrh_i64_i32(val32, val);
  76     tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum + 1],
  77                        slot_mask, zero,
  78                        val32, hex_new_value[rnum + 1]);
  79     if (HEX_DEBUG) {
  80         /*
  81          * Do this so HELPER(debug_commit_end) will know
  82          *
  83          * Note that slot_mask indicates the value is not written
  84          * (i.e., slot was cancelled), so we create a true/false value before
  85          * or'ing with hex_reg_written[rnum].
  86          */
  87         tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero);
  88         tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask);
  89         tcg_gen_or_tl(hex_reg_written[rnum + 1], hex_reg_written[rnum + 1],
  90                       slot_mask);
  91     }
  92
  93     tcg_temp_free(val32);
  94     tcg_temp_free(slot_mask);
  95 }
  96
  97 static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
  98 {
  99     /* Low word */
 100     tcg_gen_extrl_i64_i32(hex_new_value[rnum], val);
 101     if (HEX_DEBUG) {
 102         /* Do this so HELPER(debug_commit_end) will know */
 103         tcg_gen_movi_tl(hex_reg_written[rnum], 1);
 104     }
 105
 106     /* High word */
 107     tcg_gen_extrh_i64_i32(hex_new_value[rnum + 1], val);
 108     if (HEX_DEBUG) {
 109         /* Do this so HELPER(debug_commit_end) will know */
 110         tcg_gen_movi_tl(hex_reg_written[rnum + 1], 1);
 111     }
 112 }
 113
 114 static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
 115 {
 116     TCGv base_val = tcg_temp_new();
 117
 118     tcg_gen_andi_tl(base_val, val, 0xff);
 119
 120     /*
 121      * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual
 122      *
 123      * Multiple writes to the same preg are and'ed together
 124      * If this is the first predicate write in the packet, do a
 125      * straight assignment.  Otherwise, do an and.
 126      */
 127     if (!test_bit(pnum, ctx->pregs_written)) {
 128         tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val);
 129     } else {
 130         tcg_gen_and_tl(hex_new_pred_value[pnum],
 131                        hex_new_pred_value[pnum], base_val);
 132     }
 133     tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum);
 134
 135     tcg_temp_free(base_val);
 136 }
 137
 138 static inline void gen_read_p3_0(TCGv control_reg)
 139 {
 140     tcg_gen_movi_tl(control_reg, 0);
 141     for (int i = 0; i < NUM_PREGS; i++) {
 142         tcg_gen_deposit_tl(control_reg, control_reg, hex_pred[i], i * 8, 8);
 143     }
 144 }
 145
 146 /*
 147  * Certain control registers require special handling on read
 148  *     HEX_REG_P3_0          aliased to the predicate registers
 149  *                           -> concat the 4 predicate registers together
 150  *     HEX_REG_PC            actual value stored in DisasContext
 151  *                           -> assign from ctx->base.pc_next
 152  *     HEX_REG_QEMU_*_CNT    changes in current TB in DisasContext
 153  *                           -> add current TB changes to existing reg value
 154  */
 155 static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
 156                                      TCGv dest)
 157 {
 158     if (reg_num == HEX_REG_P3_0) {
 159         gen_read_p3_0(dest);
 160     } else if (reg_num == HEX_REG_PC) {
 161         tcg_gen_movi_tl(dest, ctx->base.pc_next);
 162     } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 163         tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_PKT_CNT],
 164                         ctx->num_packets);
 165     } else if (reg_num == HEX_REG_QEMU_INSN_CNT) {
 166         tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_INSN_CNT],
 167                         ctx->num_insns);
 168     } else if (reg_num == HEX_REG_QEMU_HVX_CNT) {
 169         tcg_gen_addi_tl(dest, hex_gpr[HEX_REG_QEMU_HVX_CNT],
 170                         ctx->num_hvx_insns);
 171     } else {
 172         tcg_gen_mov_tl(dest, hex_gpr[reg_num]);
 173     }
 174 }
 175
 176 static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
 177                                           TCGv_i64 dest)
 178 {
 179     if (reg_num == HEX_REG_P3_0) {
 180         TCGv p3_0 = tcg_temp_new();
 181         gen_read_p3_0(p3_0);
 182         tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
 183         tcg_temp_free(p3_0);
 184     } else if (reg_num == HEX_REG_PC - 1) {
 185         TCGv pc = tcg_constant_tl(ctx->base.pc_next);
 186         tcg_gen_concat_i32_i64(dest, hex_gpr[reg_num], pc);
 187     } else if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 188         TCGv pkt_cnt = tcg_temp_new();
 189         TCGv insn_cnt = tcg_temp_new();
 190         tcg_gen_addi_tl(pkt_cnt, hex_gpr[HEX_REG_QEMU_PKT_CNT],
 191                         ctx->num_packets);
 192         tcg_gen_addi_tl(insn_cnt, hex_gpr[HEX_REG_QEMU_INSN_CNT],
 193                         ctx->num_insns);
 194         tcg_gen_concat_i32_i64(dest, pkt_cnt, insn_cnt);
 195         tcg_temp_free(pkt_cnt);
 196         tcg_temp_free(insn_cnt);
 197     } else if (reg_num == HEX_REG_QEMU_HVX_CNT) {
 198         TCGv hvx_cnt = tcg_temp_new();
 199         tcg_gen_addi_tl(hvx_cnt, hex_gpr[HEX_REG_QEMU_HVX_CNT],
 200                         ctx->num_hvx_insns);
 201         tcg_gen_concat_i32_i64(dest, hvx_cnt, hex_gpr[reg_num + 1]);
 202         tcg_temp_free(hvx_cnt);
 203     } else {
 204         tcg_gen_concat_i32_i64(dest,
 205             hex_gpr[reg_num],
 206             hex_gpr[reg_num + 1]);
 207     }
 208 }
 209
 210 static inline void gen_write_p3_0(TCGv control_reg)
 211 {
 212     for (int i = 0; i < NUM_PREGS; i++) {
 213         tcg_gen_extract_tl(hex_pred[i], control_reg, i * 8, 8);
 214     }
 215 }
 216
 217 /*
 218  * Certain control registers require special handling on write
 219  *     HEX_REG_P3_0          aliased to the predicate registers
 220  *                           -> break the value across 4 predicate registers
 221  *     HEX_REG_QEMU_*_CNT    changes in current TB in DisasContext
 222  *                            -> clear the changes
 223  */
 224 static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
 225                                       TCGv val)
 226 {
 227     if (reg_num == HEX_REG_P3_0) {
 228         gen_write_p3_0(val);
 229     } else {
 230         gen_log_reg_write(reg_num, val);
 231         ctx_log_reg_write(ctx, reg_num);
 232         if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 233             ctx->num_packets = 0;
 234         }
 235         if (reg_num == HEX_REG_QEMU_INSN_CNT) {
 236             ctx->num_insns = 0;
 237         }
 238         if (reg_num == HEX_REG_QEMU_HVX_CNT) {
 239             ctx->num_hvx_insns = 0;
 240         }
 241     }
 242 }
 243
 244 static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
 245                                            TCGv_i64 val)
 246 {
 247     if (reg_num == HEX_REG_P3_0) {
 248         TCGv val32 = tcg_temp_new();
 249         tcg_gen_extrl_i64_i32(val32, val);
 250         gen_write_p3_0(val32);
 251         tcg_gen_extrh_i64_i32(val32, val);
 252         gen_log_reg_write(reg_num + 1, val32);
 253         tcg_temp_free(val32);
 254         ctx_log_reg_write(ctx, reg_num + 1);
 255     } else {
 256         gen_log_reg_write_pair(reg_num, val);
 257         ctx_log_reg_write_pair(ctx, reg_num);
 258         if (reg_num == HEX_REG_QEMU_PKT_CNT) {
 259             ctx->num_packets = 0;
 260             ctx->num_insns = 0;
 261         }
 262         if (reg_num == HEX_REG_QEMU_HVX_CNT) {
 263             ctx->num_hvx_insns = 0;
 264         }
 265     }
 266 }
 267
 268 static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
 269 {
 270     if (sign) {
 271         tcg_gen_sextract_tl(result, src, N * 8, 8);
 272     } else {
 273         tcg_gen_extract_tl(result, src, N * 8, 8);
 274     }
 275     return result;
 276 }
 277
 278 static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
 279 {
 280     TCGv_i64 res64 = tcg_temp_new_i64();
 281     if (sign) {
 282         tcg_gen_sextract_i64(res64, src, N * 8, 8);
 283     } else {
 284         tcg_gen_extract_i64(res64, src, N * 8, 8);
 285     }
 286     tcg_gen_extrl_i64_i32(result, res64);
 287     tcg_temp_free_i64(res64);
 288
 289     return result;
 290 }
 291
 292 static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
 293 {
 294     if (sign) {
 295         tcg_gen_sextract_tl(result, src, N * 16, 16);
 296     } else {
 297         tcg_gen_extract_tl(result, src, N * 16, 16);
 298     }
 299     return result;
 300 }
 301
 302 static inline void gen_set_half(int N, TCGv result, TCGv src)
 303 {
 304     tcg_gen_deposit_tl(result, result, src, N * 16, 16);
 305 }
 306
 307 static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
 308 {
 309     TCGv_i64 src64 = tcg_temp_new_i64();
 310     tcg_gen_extu_i32_i64(src64, src);
 311     tcg_gen_deposit_i64(result, result, src64, N * 16, 16);
 312     tcg_temp_free_i64(src64);
 313 }
 314
 315 static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
 316 {
 317     TCGv_i64 src64 = tcg_temp_new_i64();
 318     tcg_gen_extu_i32_i64(src64, src);
 319     tcg_gen_deposit_i64(result, result, src64, N * 8, 8);
 320     tcg_temp_free_i64(src64);
 321 }
 322
 323 static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index)
 324 {
 325     tcg_gen_qemu_ld32u(dest, vaddr, mem_index);
 326     tcg_gen_mov_tl(hex_llsc_addr, vaddr);
 327     tcg_gen_mov_tl(hex_llsc_val, dest);
 328 }
 329
 330 static inline void gen_load_locked8u(TCGv_i64 dest, TCGv vaddr, int mem_index)
 331 {
 332     tcg_gen_qemu_ld64(dest, vaddr, mem_index);
 333     tcg_gen_mov_tl(hex_llsc_addr, vaddr);
 334     tcg_gen_mov_i64(hex_llsc_val_i64, dest);
 335 }
 336
 337 static inline void gen_store_conditional4(DisasContext *ctx,
 338                                           TCGv pred, TCGv vaddr, TCGv src)
 339 {
 340     TCGLabel *fail = gen_new_label();
 341     TCGLabel *done = gen_new_label();
 342     TCGv one, zero, tmp;
 343
 344     tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
 345
 346     one = tcg_constant_tl(0xff);
 347     zero = tcg_constant_tl(0);
 348     tmp = tcg_temp_new();
 349     tcg_gen_atomic_cmpxchg_tl(tmp, hex_llsc_addr, hex_llsc_val, src,
 350                               ctx->mem_idx, MO_32);
 351     tcg_gen_movcond_tl(TCG_COND_EQ, pred, tmp, hex_llsc_val,
 352                        one, zero);
 353     tcg_temp_free(tmp);
 354     tcg_gen_br(done);
 355
 356     gen_set_label(fail);
 357     tcg_gen_movi_tl(pred, 0);
 358
 359     gen_set_label(done);
 360     tcg_gen_movi_tl(hex_llsc_addr, ~0);
 361 }
 362
 363 static inline void gen_store_conditional8(DisasContext *ctx,
 364                                           TCGv pred, TCGv vaddr, TCGv_i64 src)
 365 {
 366     TCGLabel *fail = gen_new_label();
 367     TCGLabel *done = gen_new_label();
 368     TCGv_i64 one, zero, tmp;
 369
 370     tcg_gen_brcond_tl(TCG_COND_NE, vaddr, hex_llsc_addr, fail);
 371
 372     one = tcg_constant_i64(0xff);
 373     zero = tcg_constant_i64(0);
 374     tmp = tcg_temp_new_i64();
 375     tcg_gen_atomic_cmpxchg_i64(tmp, hex_llsc_addr, hex_llsc_val_i64, src,
 376                                ctx->mem_idx, MO_64);
 377     tcg_gen_movcond_i64(TCG_COND_EQ, tmp, tmp, hex_llsc_val_i64,
 378                         one, zero);
 379     tcg_gen_extrl_i64_i32(pred, tmp);
 380     tcg_temp_free_i64(tmp);
 381     tcg_gen_br(done);
 382
 383     gen_set_label(fail);
 384     tcg_gen_movi_tl(pred, 0);
 385
 386     gen_set_label(done);
 387     tcg_gen_movi_tl(hex_llsc_addr, ~0);
 388 }
 389
 390 static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot)
 391 {
 392     tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 393     tcg_gen_movi_tl(hex_store_width[slot], width);
 394     tcg_gen_mov_tl(hex_store_val32[slot], src);
 395 }
 396
 397 static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src,
 398                               DisasContext *ctx, int slot)
 399 {
 400     gen_store32(vaddr, src, 1, slot);
 401     ctx->store_width[slot] = 1;
 402 }
 403
 404 static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
 405                                DisasContext *ctx, int slot)
 406 {
 407     TCGv tmp = tcg_constant_tl(src);
 408     gen_store1(cpu_env, vaddr, tmp, ctx, slot);
 409 }
 410
 411 static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src,
 412                               DisasContext *ctx, int slot)
 413 {
 414     gen_store32(vaddr, src, 2, slot);
 415     ctx->store_width[slot] = 2;
 416 }
 417
 418 static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
 419                                DisasContext *ctx, int slot)
 420 {
 421     TCGv tmp = tcg_constant_tl(src);
 422     gen_store2(cpu_env, vaddr, tmp, ctx, slot);
 423 }
 424
 425 static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src,
 426                               DisasContext *ctx, int slot)
 427 {
 428     gen_store32(vaddr, src, 4, slot);
 429     ctx->store_width[slot] = 4;
 430 }
 431
 432 static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src,
 433                                DisasContext *ctx, int slot)
 434 {
 435     TCGv tmp = tcg_constant_tl(src);
 436     gen_store4(cpu_env, vaddr, tmp, ctx, slot);
 437 }
 438
 439 static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src,
 440                               DisasContext *ctx, int slot)
 441 {
 442     tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
 443     tcg_gen_movi_tl(hex_store_width[slot], 8);
 444     tcg_gen_mov_i64(hex_store_val64[slot], src);
 445     ctx->store_width[slot] = 8;
 446 }
 447
 448 static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src,
 449                                DisasContext *ctx, int slot)
 450 {
 451     TCGv_i64 tmp = tcg_constant_i64(src);
 452     gen_store8(cpu_env, vaddr, tmp, ctx, slot);
 453 }
 454
 455 static TCGv gen_8bitsof(TCGv result, TCGv value)
 456 {
 457     TCGv zero = tcg_constant_tl(0);
 458     TCGv ones = tcg_constant_tl(0xff);
 459     tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero);
 460
 461     return result;
 462 }
 463
 464 #include "tcg_funcs_generated.c.inc"
 465 #include "tcg_func_table_generated.c.inc"