target/hexagon/macros.h

   1 /*
   2  *  Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_MACROS_H
  19 #define HEXAGON_MACROS_H
  20
  21 #include "cpu.h"
  22 #include "hex_regs.h"
  23 #include "reg_fields.h"
  24
  25 #ifdef QEMU_GENERATE
  26 #define READ_REG(dest, NUM)              gen_read_reg(dest, NUM)
  27 #else
  28 #define READ_REG(NUM)                    (env->gpr[(NUM)])
  29 #define READ_PREG(NUM)                   (env->pred[NUM])
  30
  31 #define WRITE_RREG(NUM, VAL)             log_reg_write(env, NUM, VAL, slot)
  32 #define WRITE_PREG(NUM, VAL)             log_pred_write(env, NUM, VAL)
  33 #endif
  34
  35 #define PCALIGN 4
  36 #define PCALIGN_MASK (PCALIGN - 1)
  37
  38 #define GET_FIELD(FIELD, REGIN) \
  39     fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
  40                    reg_field_info[FIELD].offset)
  41
  42 #ifdef QEMU_GENERATE
  43 #define GET_USR_FIELD(FIELD, DST) \
  44     tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
  45                        reg_field_info[FIELD].offset, \
  46                        reg_field_info[FIELD].width)
  47
  48 #define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
  49 #define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
  50 #define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
  51
  52 #define SET_USR_FIELD_FUNC(X) \
  53     __builtin_choose_expr(TYPE_INT(X), \
  54         gen_set_usr_fieldi, \
  55         __builtin_choose_expr(TYPE_TCGV(X), \
  56             gen_set_usr_field, (void)0))
  57 #define SET_USR_FIELD(FIELD, VAL) \
  58     SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
  59 #else
  60 #define GET_USR_FIELD(FIELD) \
  61     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
  62                    reg_field_info[FIELD].offset)
  63
  64 #define SET_USR_FIELD(FIELD, VAL) \
  65     fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
  66                  reg_field_info[FIELD].offset, (VAL))
  67 #endif
  68
  69 #ifdef QEMU_GENERATE
  70 /*
  71  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
  72  *
  73  * Slot 1 store with slot 0 load
  74  * A slot 1 store operation with a slot 0 load operation can appear in a packet.
  75  * The packet attribute :mem_noshuf inhibits the instruction reordering that
  76  * would otherwise be done by the assembler. For example:
  77  *     {
  78  *         memw(R5) = R2 // slot 1 store
  79  *         R3 = memh(R6) // slot 0 load
  80  *     }:mem_noshuf
  81  * Unlike most packetized operations, these memory operations are not executed
  82  * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
  83  * effectively executes first, followed by the load instruction in Slot 0. If
  84  * the addresses of the two operations are overlapping, the load will receive
  85  * the newly stored data. This feature is supported in processor versions
  86  * V65 or greater.
  87  *
  88  *
  89  * For qemu, we look for a load in slot 0 when there is  a store in slot 1
  90  * in the same packet.  When we see this, we call a helper that probes the
  91  * load to make sure it doesn't fault.  Then, we process the store ahead of
  92  * the actual load.
  93
  94  */
  95 #define CHECK_NOSHUF(VA, SIZE) \
  96     do { \
  97         if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
  98             probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
  99             process_store(ctx, pkt, 1); \
 100         } \
 101     } while (0)
 102
 103 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
 104     do { \
 105         TCGLabel *label = gen_new_label(); \
 106         tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
 107         GET_EA; \
 108         if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
 109             probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
 110         } \
 111         gen_set_label(label); \
 112         if (insn->slot == 0 && pkt->pkt_has_store_s1) { \
 113             process_store(ctx, pkt, 1); \
 114         } \
 115     } while (0)
 116
 117 #define MEM_LOAD1s(DST, VA) \
 118     do { \
 119         CHECK_NOSHUF(VA, 1); \
 120         tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
 121     } while (0)
 122 #define MEM_LOAD1u(DST, VA) \
 123     do { \
 124         CHECK_NOSHUF(VA, 1); \
 125         tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
 126     } while (0)
 127 #define MEM_LOAD2s(DST, VA) \
 128     do { \
 129         CHECK_NOSHUF(VA, 2); \
 130         tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
 131     } while (0)
 132 #define MEM_LOAD2u(DST, VA) \
 133     do { \
 134         CHECK_NOSHUF(VA, 2); \
 135         tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
 136     } while (0)
 137 #define MEM_LOAD4s(DST, VA) \
 138     do { \
 139         CHECK_NOSHUF(VA, 4); \
 140         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 141     } while (0)
 142 #define MEM_LOAD4u(DST, VA) \
 143     do { \
 144         CHECK_NOSHUF(VA, 4); \
 145         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 146     } while (0)
 147 #define MEM_LOAD8u(DST, VA) \
 148     do { \
 149         CHECK_NOSHUF(VA, 8); \
 150         tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
 151     } while (0)
 152
 153 #define MEM_STORE1_FUNC(X) \
 154     __builtin_choose_expr(TYPE_INT(X), \
 155         gen_store1i, \
 156         __builtin_choose_expr(TYPE_TCGV(X), \
 157             gen_store1, (void)0))
 158 #define MEM_STORE1(VA, DATA, SLOT) \
 159     MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 160
 161 #define MEM_STORE2_FUNC(X) \
 162     __builtin_choose_expr(TYPE_INT(X), \
 163         gen_store2i, \
 164         __builtin_choose_expr(TYPE_TCGV(X), \
 165             gen_store2, (void)0))
 166 #define MEM_STORE2(VA, DATA, SLOT) \
 167     MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 168
 169 #define MEM_STORE4_FUNC(X) \
 170     __builtin_choose_expr(TYPE_INT(X), \
 171         gen_store4i, \
 172         __builtin_choose_expr(TYPE_TCGV(X), \
 173             gen_store4, (void)0))
 174 #define MEM_STORE4(VA, DATA, SLOT) \
 175     MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 176
 177 #define MEM_STORE8_FUNC(X) \
 178     __builtin_choose_expr(TYPE_INT(X), \
 179         gen_store8i, \
 180         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 181             gen_store8, (void)0))
 182 #define MEM_STORE8(VA, DATA, SLOT) \
 183     MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 184 #else
 185 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA))
 186 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA))
 187 #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA))
 188 #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA))
 189 #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA))
 190 #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA))
 191 #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA))
 192 #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA))
 193
 194 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
 195 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
 196 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
 197 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
 198 #endif
 199
 200 #define CANCEL cancel_slot(env, slot)
 201
 202 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 203
 204 #ifdef QEMU_GENERATE
 205 static inline void gen_pred_cancel(TCGv pred, int slot_num)
 206  {
 207     TCGv slot_mask = tcg_temp_new();
 208     TCGv tmp = tcg_temp_new();
 209     TCGv zero = tcg_constant_tl(0);
 210     tcg_gen_ori_tl(slot_mask, hex_slot_cancelled, 1 << slot_num);
 211     tcg_gen_andi_tl(tmp, pred, 1);
 212     tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, tmp, zero,
 213                        slot_mask, hex_slot_cancelled);
 214     tcg_temp_free(slot_mask);
 215     tcg_temp_free(tmp);
 216 }
 217 #define PRED_LOAD_CANCEL(PRED, EA) \
 218     gen_pred_cancel(PRED, insn->is_endloop ? 4 : insn->slot)
 219 #endif
 220
 221 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
 222
 223 #define fMAX(A, B) (((A) > (B)) ? (A) : (B))
 224
 225 #define fMIN(A, B) (((A) < (B)) ? (A) : (B))
 226
 227 #define fABS(A) (((A) < 0) ? (-(A)) : (A))
 228 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
 229     REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
 230 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
 231     ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
 232 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
 233     (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
 234 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
 235     (((HIBIT) - (LOWBIT) + 1) ? \
 236         extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
 237         0LL)
 238 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
 239     do { \
 240         int width = ((HIBIT) - (LOWBIT) + 1); \
 241         INREG = (width >= 0 ? \
 242             deposit64((INREG), (LOWBIT), width, (INVAL)) : \
 243             INREG); \
 244     } while (0)
 245
 246 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
 247
 248 #ifdef QEMU_GENERATE
 249 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
 250 #else
 251 #define fLSBOLD(VAL)  ((VAL) & 1)
 252 #endif
 253
 254 #ifdef QEMU_GENERATE
 255 #define fLSBNEW(PVAL)   tcg_gen_andi_tl(LSB, (PVAL), 1)
 256 #define fLSBNEW0        tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
 257 #define fLSBNEW1        tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
 258 #else
 259 #define fLSBNEW(PVAL)   ((PVAL) & 1)
 260 #define fLSBNEW0        (env->new_pred_value[0] & 1)
 261 #define fLSBNEW1        (env->new_pred_value[1] & 1)
 262 #endif
 263
 264 #ifdef QEMU_GENERATE
 265 #define fLSBOLDNOT(VAL) \
 266     do { \
 267         tcg_gen_andi_tl(LSB, (VAL), 1); \
 268         tcg_gen_xori_tl(LSB, LSB, 1); \
 269     } while (0)
 270 #define fLSBNEWNOT(PNUM) \
 271     do { \
 272         tcg_gen_andi_tl(LSB, (PNUM), 1); \
 273         tcg_gen_xori_tl(LSB, LSB, 1); \
 274     } while (0)
 275 #else
 276 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
 277 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
 278 #define fLSBNEW0NOT (!fLSBNEW0)
 279 #define fLSBNEW1NOT (!fLSBNEW1)
 280 #endif
 281
 282 #define fNEWREG(VAL) ((int32_t)(VAL))
 283
 284 #define fNEWREG_ST(VAL) (VAL)
 285
 286 #define fVSATUVALN(N, VAL) \
 287     ({ \
 288         (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \
 289     })
 290 #define fSATUVALN(N, VAL) \
 291     ({ \
 292         fSET_OVERFLOW(); \
 293         ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
 294     })
 295 #define fSATVALN(N, VAL) \
 296     ({ \
 297         fSET_OVERFLOW(); \
 298         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 299     })
 300 #define fVSATVALN(N, VAL) \
 301     ({ \
 302         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 303     })
 304 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
 305 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
 306 #define fSATN(N, VAL) \
 307     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
 308 #define fVSATN(N, VAL) \
 309     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL))
 310 #define fADDSAT64(DST, A, B) \
 311     do { \
 312         uint64_t __a = fCAST8u(A); \
 313         uint64_t __b = fCAST8u(B); \
 314         uint64_t __sum = __a + __b; \
 315         uint64_t __xor = __a ^ __b; \
 316         const uint64_t __mask = 0x8000000000000000ULL; \
 317         if (__xor & __mask) { \
 318             DST = __sum; \
 319         } \
 320         else if ((__a ^ __sum) & __mask) { \
 321             if (__sum & __mask) { \
 322                 DST = 0x7FFFFFFFFFFFFFFFLL; \
 323                 fSET_OVERFLOW(); \
 324             } else { \
 325                 DST = 0x8000000000000000LL; \
 326                 fSET_OVERFLOW(); \
 327             } \
 328         } else { \
 329             DST = __sum; \
 330         } \
 331     } while (0)
 332 #define fVSATUN(N, VAL) \
 333     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
 334 #define fSATUN(N, VAL) \
 335     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
 336 #define fSATH(VAL) (fSATN(16, VAL))
 337 #define fSATUH(VAL) (fSATUN(16, VAL))
 338 #define fVSATH(VAL) (fVSATN(16, VAL))
 339 #define fVSATUH(VAL) (fVSATUN(16, VAL))
 340 #define fSATUB(VAL) (fSATUN(8, VAL))
 341 #define fSATB(VAL) (fSATN(8, VAL))
 342 #define fVSATUB(VAL) (fVSATUN(8, VAL))
 343 #define fVSATB(VAL) (fVSATN(8, VAL))
 344 #define fIMMEXT(IMM) (IMM = IMM)
 345 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
 346
 347 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
 348
 349 #ifdef QEMU_GENERATE
 350 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 351 {
 352     /*
 353      * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
 354      *
 355      *  The "I" value from a modifier register is divided into two pieces
 356      *      LSB         bits 23:17
 357      *      MSB         bits 31:28
 358      * The value is signed
 359      *
 360      * At the end we shift the result according to the shift argument
 361      */
 362     TCGv msb = tcg_temp_new();
 363     TCGv lsb = tcg_temp_new();
 364
 365     tcg_gen_extract_tl(lsb, val, 17, 7);
 366     tcg_gen_sari_tl(msb, val, 21);
 367     tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
 368
 369     tcg_gen_shli_tl(result, result, shift);
 370
 371     tcg_temp_free(msb);
 372     tcg_temp_free(lsb);
 373
 374     return result;
 375 }
 376 #define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
 377 #else
 378 #define fREAD_IREG(VAL) \
 379     (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f)))
 380 #endif
 381
 382 #define fREAD_LR() (READ_REG(HEX_REG_LR))
 383
 384 #define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
 385 #define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
 386 #define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
 387
 388 #define fREAD_SP() (READ_REG(HEX_REG_SP))
 389 #define fREAD_LC0 (READ_REG(HEX_REG_LC0))
 390 #define fREAD_LC1 (READ_REG(HEX_REG_LC1))
 391 #define fREAD_SA0 (READ_REG(HEX_REG_SA0))
 392 #define fREAD_SA1 (READ_REG(HEX_REG_SA1))
 393 #define fREAD_FP() (READ_REG(HEX_REG_FP))
 394 #ifdef FIXME
 395 /* Figure out how to get insn->extension_valid to helper */
 396 #define fREAD_GP() \
 397     (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
 398 #else
 399 #define fREAD_GP() READ_REG(HEX_REG_GP)
 400 #endif
 401 #define fREAD_PC() (READ_REG(HEX_REG_PC))
 402
 403 #define fREAD_NPC() (env->next_PC & (0xfffffffe))
 404
 405 #define fREAD_P0() (READ_PREG(0))
 406 #define fREAD_P3() (READ_PREG(3))
 407
 408 #define fCHECK_PCALIGN(A)
 409
 410 #define fWRITE_NPC(A) write_new_pc(env, A)
 411
 412 #define fBRANCH(LOC, TYPE)          fWRITE_NPC(LOC)
 413 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
 414 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
 415 #define fCALL(A) \
 416     do { \
 417         fWRITE_LR(fREAD_NPC()); \
 418         fBRANCH(A, COF_TYPE_CALL); \
 419     } while (0)
 420 #define fCALLR(A) \
 421     do { \
 422         fWRITE_LR(fREAD_NPC()); \
 423         fBRANCH(A, COF_TYPE_CALLR); \
 424     } while (0)
 425 #define fWRITE_LOOP_REGS0(START, COUNT) \
 426     do { \
 427         WRITE_RREG(HEX_REG_LC0, COUNT);  \
 428         WRITE_RREG(HEX_REG_SA0, START); \
 429     } while (0)
 430 #define fWRITE_LOOP_REGS1(START, COUNT) \
 431     do { \
 432         WRITE_RREG(HEX_REG_LC1, COUNT);  \
 433         WRITE_RREG(HEX_REG_SA1, START);\
 434     } while (0)
 435 #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
 436 #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
 437
 438 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 439 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 440 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
 441 #define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
 442 #define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
 443 #define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
 444 #define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
 445 #define fPART1(WORK) if (part1) { WORK; return; }
 446 #define fCAST4u(A) ((uint32_t)(A))
 447 #define fCAST4s(A) ((int32_t)(A))
 448 #define fCAST8u(A) ((uint64_t)(A))
 449 #define fCAST8s(A) ((int64_t)(A))
 450 #define fCAST2_2s(A) ((int16_t)(A))
 451 #define fCAST2_2u(A) ((uint16_t)(A))
 452 #define fCAST4_4s(A) ((int32_t)(A))
 453 #define fCAST4_4u(A) ((uint32_t)(A))
 454 #define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
 455 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
 456 #define fCAST8_8s(A) ((int64_t)(A))
 457 #define fCAST8_8u(A) ((uint64_t)(A))
 458 #define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
 459 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
 460 #define fZE8_16(A) ((int16_t)((uint8_t)(A)))
 461 #define fSE8_16(A) ((int16_t)((int8_t)(A)))
 462 #define fSE16_32(A) ((int32_t)((int16_t)(A)))
 463 #define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
 464 #define fSE32_64(A) ((int64_t)((int32_t)(A)))
 465 #define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
 466 #define fSE8_32(A) ((int32_t)((int8_t)(A)))
 467 #define fZE8_32(A) ((int32_t)((uint8_t)(A)))
 468 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
 469 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
 470 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
 471 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
 472 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
 473 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
 474 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
 475 #define fMPY16US(A, B) fMPY16SU(B, A)
 476 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
 477 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
 478 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
 479 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
 480 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
 481 #define fROUND(A) (A + 0x8000)
 482 #define fCLIP(DST, SRC, U) \
 483     do { \
 484         int32_t maxv = (1 << U) - 1; \
 485         int32_t minv = -(1 << U); \
 486         DST = fMIN(maxv, fMAX(SRC, minv)); \
 487     } while (0)
 488 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
 489 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
 490 #define fCRNDN(A, N) (conv_round(A, N))
 491 #define fADD128(A, B) (int128_add(A, B))
 492 #define fSUB128(A, B) (int128_sub(A, B))
 493 #define fSHIFTR128(A, B) (int128_rshift(A, B))
 494 #define fSHIFTL128(A, B) (int128_lshift(A, B))
 495 #define fAND128(A, B) (int128_and(A, B))
 496 #define fCAST8S_16S(A) (int128_exts64(A))
 497 #define fCAST16S_8S(A) (int128_getlo(A))
 498
 499 #ifdef QEMU_GENERATE
 500 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
 501 #define fEA_RRs(REG, REG2, SCALE) \
 502     do { \
 503         TCGv tmp = tcg_temp_new(); \
 504         tcg_gen_shli_tl(tmp, REG2, SCALE); \
 505         tcg_gen_add_tl(EA, REG, tmp); \
 506         tcg_temp_free(tmp); \
 507     } while (0)
 508 #define fEA_IRs(IMM, REG, SCALE) \
 509     do { \
 510         tcg_gen_shli_tl(EA, REG, SCALE); \
 511         tcg_gen_addi_tl(EA, EA, IMM); \
 512     } while (0)
 513 #else
 514 #define fEA_RI(REG, IMM) \
 515     do { \
 516         EA = REG + IMM; \
 517     } while (0)
 518 #define fEA_RRs(REG, REG2, SCALE) \
 519     do { \
 520         EA = REG + (REG2 << SCALE); \
 521     } while (0)
 522 #define fEA_IRs(IMM, REG, SCALE) \
 523     do { \
 524         EA = IMM + (REG << SCALE); \
 525     } while (0)
 526 #endif
 527
 528 #ifdef QEMU_GENERATE
 529 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
 530 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
 531 #define fEA_BREVR(REG)      gen_helper_fbrev(EA, REG)
 532 #define fPM_I(REG, IMM)     tcg_gen_addi_tl(REG, REG, IMM)
 533 #define fPM_M(REG, MVAL)    tcg_gen_add_tl(REG, REG, MVAL)
 534 #define fPM_CIRI(REG, IMM, MVAL) \
 535     do { \
 536         TCGv tcgv_siV = tcg_constant_tl(siV); \
 537         gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
 538                             hex_gpr[HEX_REG_CS0 + MuN]); \
 539     } while (0)
 540 #else
 541 #define fEA_IMM(IMM)        do { EA = (IMM); } while (0)
 542 #define fEA_REG(REG)        do { EA = (REG); } while (0)
 543 #define fEA_GPI(IMM)        do { EA = (fREAD_GP() + (IMM)); } while (0)
 544 #define fPM_I(REG, IMM)     do { REG = REG + (IMM); } while (0)
 545 #define fPM_M(REG, MVAL)    do { REG = REG + (MVAL); } while (0)
 546 #endif
 547 #define fSCALE(N, A) (((int64_t)(A)) << N)
 548 #define fVSATW(A) fVSATN(32, ((long long)A))
 549 #define fSATW(A) fSATN(32, ((long long)A))
 550 #define fVSAT(A) fVSATN(32, (A))
 551 #define fSAT(A) fSATN(32, (A))
 552 #define fSAT_ORIG_SHL(A, ORIG_REG) \
 553     ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
 554         ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
 555         : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
 556                                             : fSAT(A)))
 557 #define fPASS(A) A
 558 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
 559     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 560                    : (fCAST##REGSTYPE(SRC) << (SHAMT)))
 561 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
 562     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
 563 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
 564     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
 565 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
 566     (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 567                    : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
 568 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
 569     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
 570                    : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
 571 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
 572     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
 573 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
 574     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
 575 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
 576     (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
 577                         << ((-(SHAMT)) - 1)) << 1, (SRC)) \
 578                    : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
 579 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
 580 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
 581     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
 582 #define fROTL(SRC, SHAMT, REGSTYPE) \
 583     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
 584                               ((fCAST##REGSTYPE##u(SRC) >> \
 585                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 586 #define fROTR(SRC, SHAMT, REGSTYPE) \
 587     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
 588                               ((fCAST##REGSTYPE##u(SRC) << \
 589                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 590 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \
 591     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
 592
 593 #ifdef QEMU_GENERATE
 594 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
 595 #else
 596 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
 597     DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
 598 #endif
 599
 600 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 601
 602 #define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
 603 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 604 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 605
 606 #ifdef CONFIG_USER_ONLY
 607 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
 608 #else
 609 /* System mode not implemented yet */
 610 #define fFRAMECHECK(ADDR, EA)  g_assert_not_reached();
 611 #endif
 612
 613 #ifdef QEMU_GENERATE
 614 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
 615     gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
 616 #endif
 617
 618 #ifdef QEMU_GENERATE
 619 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
 620 #else
 621 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
 622 #endif
 623
 624 #ifdef QEMU_GENERATE
 625 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
 626     gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
 627 #endif
 628
 629 #ifdef QEMU_GENERATE
 630 #define GETBYTE_FUNC(X) \
 631     __builtin_choose_expr(TYPE_TCGV(X), \
 632         gen_get_byte, \
 633         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 634             gen_get_byte_i64, (void)0))
 635 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
 636 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
 637 #else
 638 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
 639 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
 640 #endif
 641
 642 #define fSETBYTE(N, DST, VAL) \
 643     do { \
 644         DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
 645         (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
 646     } while (0)
 647
 648 #ifdef QEMU_GENERATE
 649 #define fGETHALF(N, SRC)  gen_get_half(HALF, N, SRC, true)
 650 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
 651 #else
 652 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
 653 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
 654 #endif
 655 #define fSETHALF(N, DST, VAL) \
 656     do { \
 657         DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
 658         (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
 659     } while (0)
 660 #define fSETHALFw fSETHALF
 661 #define fSETHALFd fSETHALF
 662
 663 #define fGETWORD(N, SRC) \
 664     ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 665 #define fGETUWORD(N, SRC) \
 666     ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 667
 668 #define fSETWORD(N, DST, VAL) \
 669     do { \
 670         DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
 671               (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
 672     } while (0)
 673
 674 #define fSETBIT(N, DST, VAL) \
 675     do { \
 676         DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
 677     } while (0)
 678
 679 #define fGETBIT(N, SRC) (((SRC) >> N) & 1)
 680 #define fSETBITS(HI, LO, DST, VAL) \
 681     do { \
 682         int j; \
 683         for (j = LO; j <= HI; j++) { \
 684             fSETBIT(j, DST, VAL); \
 685         } \
 686     } while (0)
 687 #define fCOUNTONES_2(VAL) ctpop16(VAL)
 688 #define fCOUNTONES_4(VAL) ctpop32(VAL)
 689 #define fCOUNTONES_8(VAL) ctpop64(VAL)
 690 #define fBREV_8(VAL) revbit64(VAL)
 691 #define fBREV_4(VAL) revbit32(VAL)
 692 #define fCL1_8(VAL) clo64(VAL)
 693 #define fCL1_4(VAL) clo32(VAL)
 694 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16)
 695 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
 696 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
 697 #define fHIDE(A) A
 698 #define fCONSTLL(A) A##LL
 699 #define fECHO(A) (A)
 700
 701 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
 702 #define fPAUSE(IMM)
 703
 704 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
 705     ((VAL) << reg_field_info[FIELD].offset)
 706 #define fGET_REG_FIELD_MASK(FIELD) \
 707     (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
 708 #define fREAD_REG_FIELD(REG, FIELD) \
 709     fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
 710                    reg_field_info[FIELD].width, \
 711                    reg_field_info[FIELD].offset)
 712 #define fGET_FIELD(VAL, FIELD)
 713 #define fSET_FIELD(VAL, FIELD, NEWVAL)
 714 #define fBARRIER()
 715 #define fSYNCH()
 716 #define fISYNC()
 717 #define fDCFETCH(REG) \
 718     do { (void)REG; } while (0) /* Nothing to do in qemu */
 719 #define fICINVA(REG) \
 720     do { (void)REG; } while (0) /* Nothing to do in qemu */
 721 #define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
 722 #define fDCCLEANA(REG) \
 723     do { (void)REG; } while (0) /* Nothing to do in qemu */
 724 #define fDCCLEANINVA(REG) \
 725     do { (void)REG; } while (0) /* Nothing to do in qemu */
 726
 727 #define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
 728
 729 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
 730                                 STRBITNUM) /* Nothing */
 731
 732
 733 #endif