target/hexagon/macros.h

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_MACROS_H
  19 #define HEXAGON_MACROS_H
  20
  21 #include "cpu.h"
  22 #include "hex_regs.h"
  23 #include "reg_fields.h"
  24
  25 #ifdef QEMU_GENERATE
  26 #define READ_REG(dest, NUM)              gen_read_reg(dest, NUM)
  27 #else
  28 #define READ_REG(NUM)                    (env->gpr[(NUM)])
  29 #define READ_PREG(NUM)                   (env->pred[NUM])
  30
  31 #define WRITE_RREG(NUM, VAL)             log_reg_write(env, NUM, VAL, slot)
  32 #define WRITE_PREG(NUM, VAL)             log_pred_write(env, NUM, VAL)
  33 #endif
  34
  35 #define PCALIGN 4
  36 #define PCALIGN_MASK (PCALIGN - 1)
  37
  38 #define GET_FIELD(FIELD, REGIN) \
  39     fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
  40                    reg_field_info[FIELD].offset)
  41
  42 #ifdef QEMU_GENERATE
  43 #define GET_USR_FIELD(FIELD, DST) \
  44     tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
  45                        reg_field_info[FIELD].offset, \
  46                        reg_field_info[FIELD].width)
  47
  48 #define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
  49 #define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
  50 #define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
  51
  52 #define SET_USR_FIELD_FUNC(X) \
  53     __builtin_choose_expr(TYPE_INT(X), \
  54         gen_set_usr_fieldi, \
  55         __builtin_choose_expr(TYPE_TCGV(X), \
  56             gen_set_usr_field, (void)0))
  57 #define SET_USR_FIELD(FIELD, VAL) \
  58     SET_USR_FIELD_FUNC(VAL)(FIELD, VAL)
  59 #else
  60 #define GET_USR_FIELD(FIELD) \
  61     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
  62                    reg_field_info[FIELD].offset)
  63
  64 #define SET_USR_FIELD(FIELD, VAL) \
  65     fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
  66                  reg_field_info[FIELD].offset, (VAL))
  67 #endif
  68
  69 #ifdef QEMU_GENERATE
  70 /*
  71  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
  72  *
  73  * Slot 1 store with slot 0 load
  74  * A slot 1 store operation with a slot 0 load operation can appear in a packet.
  75  * The packet attribute :mem_noshuf inhibits the instruction reordering that
  76  * would otherwise be done by the assembler. For example:
  77  *     {
  78  *         memw(R5) = R2 // slot 1 store
  79  *         R3 = memh(R6) // slot 0 load
  80  *     }:mem_noshuf
  81  * Unlike most packetized operations, these memory operations are not executed
  82  * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
  83  * effectively executes first, followed by the load instruction in Slot 0. If
  84  * the addresses of the two operations are overlapping, the load will receive
  85  * the newly stored data. This feature is supported in processor versions
  86  * V65 or greater.
  87  *
  88  *
  89  * For qemu, we look for a load in slot 0 when there is  a store in slot 1
  90  * in the same packet.  When we see this, we call a helper that probes the
  91  * load to make sure it doesn't fault.  Then, we process the store ahead of
  92  * the actual load.
  93
  94  */
  95 #define CHECK_NOSHUF(VA, SIZE) \
  96     do { \
  97         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
  98             probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
  99             process_store(ctx, 1); \
 100         } \
 101     } while (0)
 102
 103 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
 104     do { \
 105         TCGLabel *label = gen_new_label(); \
 106         tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
 107         GET_EA; \
 108         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
 109             probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
 110         } \
 111         gen_set_label(label); \
 112         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
 113             process_store(ctx, 1); \
 114         } \
 115     } while (0)
 116
 117 #define MEM_LOAD1s(DST, VA) \
 118     do { \
 119         CHECK_NOSHUF(VA, 1); \
 120         tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
 121     } while (0)
 122 #define MEM_LOAD1u(DST, VA) \
 123     do { \
 124         CHECK_NOSHUF(VA, 1); \
 125         tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
 126     } while (0)
 127 #define MEM_LOAD2s(DST, VA) \
 128     do { \
 129         CHECK_NOSHUF(VA, 2); \
 130         tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
 131     } while (0)
 132 #define MEM_LOAD2u(DST, VA) \
 133     do { \
 134         CHECK_NOSHUF(VA, 2); \
 135         tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
 136     } while (0)
 137 #define MEM_LOAD4s(DST, VA) \
 138     do { \
 139         CHECK_NOSHUF(VA, 4); \
 140         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 141     } while (0)
 142 #define MEM_LOAD4u(DST, VA) \
 143     do { \
 144         CHECK_NOSHUF(VA, 4); \
 145         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 146     } while (0)
 147 #define MEM_LOAD8u(DST, VA) \
 148     do { \
 149         CHECK_NOSHUF(VA, 8); \
 150         tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
 151     } while (0)
 152
 153 #define MEM_STORE1_FUNC(X) \
 154     __builtin_choose_expr(TYPE_INT(X), \
 155         gen_store1i, \
 156         __builtin_choose_expr(TYPE_TCGV(X), \
 157             gen_store1, (void)0))
 158 #define MEM_STORE1(VA, DATA, SLOT) \
 159     MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 160
 161 #define MEM_STORE2_FUNC(X) \
 162     __builtin_choose_expr(TYPE_INT(X), \
 163         gen_store2i, \
 164         __builtin_choose_expr(TYPE_TCGV(X), \
 165             gen_store2, (void)0))
 166 #define MEM_STORE2(VA, DATA, SLOT) \
 167     MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 168
 169 #define MEM_STORE4_FUNC(X) \
 170     __builtin_choose_expr(TYPE_INT(X), \
 171         gen_store4i, \
 172         __builtin_choose_expr(TYPE_TCGV(X), \
 173             gen_store4, (void)0))
 174 #define MEM_STORE4(VA, DATA, SLOT) \
 175     MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 176
 177 #define MEM_STORE8_FUNC(X) \
 178     __builtin_choose_expr(TYPE_INT(X), \
 179         gen_store8i, \
 180         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 181             gen_store8, (void)0))
 182 #define MEM_STORE8(VA, DATA, SLOT) \
 183     MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 184 #else
 185 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA))
 186 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA))
 187 #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA))
 188 #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA))
 189 #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA))
 190 #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA))
 191 #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA))
 192 #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA))
 193
 194 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
 195 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
 196 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
 197 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
 198 #endif
 199
 200 #ifdef QEMU_GENERATE
 201 static inline void gen_cancel(uint32_t slot)
 202 {
 203     tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
 204 }
 205
 206 #define CANCEL gen_cancel(slot);
 207 #else
 208 #define CANCEL do { } while (0)
 209 #endif
 210
 211 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 212
 213 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
 214
 215 #define fMAX(A, B) (((A) > (B)) ? (A) : (B))
 216
 217 #define fMIN(A, B) (((A) < (B)) ? (A) : (B))
 218
 219 #define fABS(A) (((A) < 0) ? (-(A)) : (A))
 220 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
 221     REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
 222 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
 223     ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
 224 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
 225     (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
 226 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
 227     (((HIBIT) - (LOWBIT) + 1) ? \
 228         extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
 229         0LL)
 230 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
 231     do { \
 232         int width = ((HIBIT) - (LOWBIT) + 1); \
 233         INREG = (width >= 0 ? \
 234             deposit64((INREG), (LOWBIT), width, (INVAL)) : \
 235             INREG); \
 236     } while (0)
 237
 238 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
 239
 240 #ifdef QEMU_GENERATE
 241 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
 242 #else
 243 #define fLSBOLD(VAL)  ((VAL) & 1)
 244 #endif
 245
 246 #ifdef QEMU_GENERATE
 247 #define fLSBNEW(PVAL)   tcg_gen_andi_tl(LSB, (PVAL), 1)
 248 #define fLSBNEW0        tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
 249 #define fLSBNEW1        tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
 250 #else
 251 #define fLSBNEW(PVAL)   ((PVAL) & 1)
 252 #define fLSBNEW0        (env->new_pred_value[0] & 1)
 253 #define fLSBNEW1        (env->new_pred_value[1] & 1)
 254 #endif
 255
 256 #ifdef QEMU_GENERATE
 257 #define fLSBOLDNOT(VAL) \
 258     do { \
 259         tcg_gen_andi_tl(LSB, (VAL), 1); \
 260         tcg_gen_xori_tl(LSB, LSB, 1); \
 261     } while (0)
 262 #define fLSBNEWNOT(PNUM) \
 263     do { \
 264         tcg_gen_andi_tl(LSB, (PNUM), 1); \
 265         tcg_gen_xori_tl(LSB, LSB, 1); \
 266     } while (0)
 267 #else
 268 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
 269 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
 270 #define fLSBNEW0NOT (!fLSBNEW0)
 271 #define fLSBNEW1NOT (!fLSBNEW1)
 272 #endif
 273
 274 #define fNEWREG(VAL) ((int32_t)(VAL))
 275
 276 #define fNEWREG_ST(VAL) (VAL)
 277
 278 #define fVSATUVALN(N, VAL) \
 279     ({ \
 280         (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \
 281     })
 282 #define fSATUVALN(N, VAL) \
 283     ({ \
 284         fSET_OVERFLOW(); \
 285         ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
 286     })
 287 #define fSATVALN(N, VAL) \
 288     ({ \
 289         fSET_OVERFLOW(); \
 290         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 291     })
 292 #define fVSATVALN(N, VAL) \
 293     ({ \
 294         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 295     })
 296 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
 297 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
 298 #define fSATN(N, VAL) \
 299     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
 300 #define fVSATN(N, VAL) \
 301     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL))
 302 #define fADDSAT64(DST, A, B) \
 303     do { \
 304         uint64_t __a = fCAST8u(A); \
 305         uint64_t __b = fCAST8u(B); \
 306         uint64_t __sum = __a + __b; \
 307         uint64_t __xor = __a ^ __b; \
 308         const uint64_t __mask = 0x8000000000000000ULL; \
 309         if (__xor & __mask) { \
 310             DST = __sum; \
 311         } \
 312         else if ((__a ^ __sum) & __mask) { \
 313             if (__sum & __mask) { \
 314                 DST = 0x7FFFFFFFFFFFFFFFLL; \
 315                 fSET_OVERFLOW(); \
 316             } else { \
 317                 DST = 0x8000000000000000LL; \
 318                 fSET_OVERFLOW(); \
 319             } \
 320         } else { \
 321             DST = __sum; \
 322         } \
 323     } while (0)
 324 #define fVSATUN(N, VAL) \
 325     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
 326 #define fSATUN(N, VAL) \
 327     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
 328 #define fSATH(VAL) (fSATN(16, VAL))
 329 #define fSATUH(VAL) (fSATUN(16, VAL))
 330 #define fVSATH(VAL) (fVSATN(16, VAL))
 331 #define fVSATUH(VAL) (fVSATUN(16, VAL))
 332 #define fSATUB(VAL) (fSATUN(8, VAL))
 333 #define fSATB(VAL) (fSATN(8, VAL))
 334 #define fVSATUB(VAL) (fVSATUN(8, VAL))
 335 #define fVSATB(VAL) (fVSATN(8, VAL))
 336 #define fIMMEXT(IMM) (IMM = IMM)
 337 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
 338
 339 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
 340
 341 #ifdef QEMU_GENERATE
 342 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 343 {
 344     /*
 345      * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
 346      *
 347      *  The "I" value from a modifier register is divided into two pieces
 348      *      LSB         bits 23:17
 349      *      MSB         bits 31:28
 350      * The value is signed
 351      *
 352      * At the end we shift the result according to the shift argument
 353      */
 354     TCGv msb = tcg_temp_new();
 355     TCGv lsb = tcg_temp_new();
 356
 357     tcg_gen_extract_tl(lsb, val, 17, 7);
 358     tcg_gen_sari_tl(msb, val, 21);
 359     tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
 360
 361     tcg_gen_shli_tl(result, result, shift);
 362     return result;
 363 }
 364 #define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT))
 365 #else
 366 #define fREAD_IREG(VAL) \
 367     (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f)))
 368 #endif
 369
 370 #define fREAD_LR() (READ_REG(HEX_REG_LR))
 371
 372 #define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A)
 373 #define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A)
 374 #define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A)
 375
 376 #define fREAD_SP() (READ_REG(HEX_REG_SP))
 377 #define fREAD_LC0 (READ_REG(HEX_REG_LC0))
 378 #define fREAD_LC1 (READ_REG(HEX_REG_LC1))
 379 #define fREAD_SA0 (READ_REG(HEX_REG_SA0))
 380 #define fREAD_SA1 (READ_REG(HEX_REG_SA1))
 381 #define fREAD_FP() (READ_REG(HEX_REG_FP))
 382 #ifdef FIXME
 383 /* Figure out how to get insn->extension_valid to helper */
 384 #define fREAD_GP() \
 385     (insn->extension_valid ? 0 : READ_REG(HEX_REG_GP))
 386 #else
 387 #define fREAD_GP() READ_REG(HEX_REG_GP)
 388 #endif
 389 #define fREAD_PC() (PC)
 390
 391 #define fREAD_NPC() (next_PC & (0xfffffffe))
 392
 393 #define fREAD_P0() (READ_PREG(0))
 394 #define fREAD_P3() (READ_PREG(3))
 395
 396 #define fCHECK_PCALIGN(A)
 397
 398 #define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A)
 399
 400 #define fBRANCH(LOC, TYPE)          fWRITE_NPC(LOC)
 401 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
 402 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
 403 #define fWRITE_LOOP_REGS0(START, COUNT) \
 404     do { \
 405         WRITE_RREG(HEX_REG_LC0, COUNT);  \
 406         WRITE_RREG(HEX_REG_SA0, START); \
 407     } while (0)
 408 #define fWRITE_LOOP_REGS1(START, COUNT) \
 409     do { \
 410         WRITE_RREG(HEX_REG_LC1, COUNT);  \
 411         WRITE_RREG(HEX_REG_SA1, START);\
 412     } while (0)
 413 #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL)
 414 #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL)
 415
 416 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 417 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 418 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
 419 #define fWRITE_P0(VAL) WRITE_PREG(0, VAL)
 420 #define fWRITE_P1(VAL) WRITE_PREG(1, VAL)
 421 #define fWRITE_P2(VAL) WRITE_PREG(2, VAL)
 422 #define fWRITE_P3(VAL) WRITE_PREG(3, VAL)
 423 #define fPART1(WORK) if (part1) { WORK; return; }
 424 #define fCAST4u(A) ((uint32_t)(A))
 425 #define fCAST4s(A) ((int32_t)(A))
 426 #define fCAST8u(A) ((uint64_t)(A))
 427 #define fCAST8s(A) ((int64_t)(A))
 428 #define fCAST2_2s(A) ((int16_t)(A))
 429 #define fCAST2_2u(A) ((uint16_t)(A))
 430 #define fCAST4_4s(A) ((int32_t)(A))
 431 #define fCAST4_4u(A) ((uint32_t)(A))
 432 #define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
 433 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
 434 #define fCAST8_8s(A) ((int64_t)(A))
 435 #define fCAST8_8u(A) ((uint64_t)(A))
 436 #define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
 437 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
 438 #define fZE8_16(A) ((int16_t)((uint8_t)(A)))
 439 #define fSE8_16(A) ((int16_t)((int8_t)(A)))
 440 #define fSE16_32(A) ((int32_t)((int16_t)(A)))
 441 #define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
 442 #define fSE32_64(A) ((int64_t)((int32_t)(A)))
 443 #define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
 444 #define fSE8_32(A) ((int32_t)((int8_t)(A)))
 445 #define fZE8_32(A) ((int32_t)((uint8_t)(A)))
 446 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
 447 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
 448 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
 449 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
 450 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
 451 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
 452 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
 453 #define fMPY16US(A, B) fMPY16SU(B, A)
 454 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
 455 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
 456 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
 457 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
 458 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
 459 #define fROUND(A) (A + 0x8000)
 460 #define fCLIP(DST, SRC, U) \
 461     do { \
 462         int32_t maxv = (1 << U) - 1; \
 463         int32_t minv = -(1 << U); \
 464         DST = fMIN(maxv, fMAX(SRC, minv)); \
 465     } while (0)
 466 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
 467 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
 468 #define fCRNDN(A, N) (conv_round(A, N))
 469 #define fADD128(A, B) (int128_add(A, B))
 470 #define fSUB128(A, B) (int128_sub(A, B))
 471 #define fSHIFTR128(A, B) (int128_rshift(A, B))
 472 #define fSHIFTL128(A, B) (int128_lshift(A, B))
 473 #define fAND128(A, B) (int128_and(A, B))
 474 #define fCAST8S_16S(A) (int128_exts64(A))
 475 #define fCAST16S_8S(A) (int128_getlo(A))
 476
 477 #ifdef QEMU_GENERATE
 478 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
 479 #define fEA_RRs(REG, REG2, SCALE) \
 480     do { \
 481         TCGv tmp = tcg_temp_new(); \
 482         tcg_gen_shli_tl(tmp, REG2, SCALE); \
 483         tcg_gen_add_tl(EA, REG, tmp); \
 484     } while (0)
 485 #define fEA_IRs(IMM, REG, SCALE) \
 486     do { \
 487         tcg_gen_shli_tl(EA, REG, SCALE); \
 488         tcg_gen_addi_tl(EA, EA, IMM); \
 489     } while (0)
 490 #else
 491 #define fEA_RI(REG, IMM) \
 492     do { \
 493         EA = REG + IMM; \
 494     } while (0)
 495 #define fEA_RRs(REG, REG2, SCALE) \
 496     do { \
 497         EA = REG + (REG2 << SCALE); \
 498     } while (0)
 499 #define fEA_IRs(IMM, REG, SCALE) \
 500     do { \
 501         EA = IMM + (REG << SCALE); \
 502     } while (0)
 503 #endif
 504
 505 #ifdef QEMU_GENERATE
 506 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
 507 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
 508 #define fEA_BREVR(REG)      gen_helper_fbrev(EA, REG)
 509 #define fPM_I(REG, IMM)     tcg_gen_addi_tl(REG, REG, IMM)
 510 #define fPM_M(REG, MVAL)    tcg_gen_add_tl(REG, REG, MVAL)
 511 #define fPM_CIRI(REG, IMM, MVAL) \
 512     do { \
 513         TCGv tcgv_siV = tcg_constant_tl(siV); \
 514         gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
 515                             hex_gpr[HEX_REG_CS0 + MuN]); \
 516     } while (0)
 517 #else
 518 #define fEA_IMM(IMM)        do { EA = (IMM); } while (0)
 519 #define fEA_REG(REG)        do { EA = (REG); } while (0)
 520 #define fEA_GPI(IMM)        do { EA = (fREAD_GP() + (IMM)); } while (0)
 521 #define fPM_I(REG, IMM)     do { REG = REG + (IMM); } while (0)
 522 #define fPM_M(REG, MVAL)    do { REG = REG + (MVAL); } while (0)
 523 #endif
 524 #define fSCALE(N, A) (((int64_t)(A)) << N)
 525 #define fVSATW(A) fVSATN(32, ((long long)A))
 526 #define fSATW(A) fSATN(32, ((long long)A))
 527 #define fVSAT(A) fVSATN(32, (A))
 528 #define fSAT(A) fSATN(32, (A))
 529 #define fSAT_ORIG_SHL(A, ORIG_REG) \
 530     ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
 531         ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
 532         : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
 533                                             : fSAT(A)))
 534 #define fPASS(A) A
 535 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
 536     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 537                    : (fCAST##REGSTYPE(SRC) << (SHAMT)))
 538 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
 539     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
 540 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
 541     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
 542 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
 543     (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 544                    : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
 545 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
 546     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
 547                    : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
 548 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
 549     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
 550 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
 551     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
 552 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
 553     (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
 554                         << ((-(SHAMT)) - 1)) << 1, (SRC)) \
 555                    : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
 556 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
 557 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
 558     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
 559 #define fROTL(SRC, SHAMT, REGSTYPE) \
 560     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
 561                               ((fCAST##REGSTYPE##u(SRC) >> \
 562                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 563 #define fROTR(SRC, SHAMT, REGSTYPE) \
 564     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
 565                               ((fCAST##REGSTYPE##u(SRC) << \
 566                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 567 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \
 568     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
 569
 570 #ifdef QEMU_GENERATE
 571 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
 572 #else
 573 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
 574     DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
 575 #endif
 576
 577 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 578
 579 #define fGET_FRAMEKEY() READ_REG(HEX_REG_FRAMEKEY)
 580 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 581 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 582
 583 #ifdef CONFIG_USER_ONLY
 584 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
 585 #else
 586 /* System mode not implemented yet */
 587 #define fFRAMECHECK(ADDR, EA)  g_assert_not_reached();
 588 #endif
 589
 590 #ifdef QEMU_GENERATE
 591 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
 592     gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
 593 #endif
 594
 595 #ifdef QEMU_GENERATE
 596 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
 597 #else
 598 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
 599 #endif
 600
 601 #ifdef QEMU_GENERATE
 602 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
 603     gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
 604 #endif
 605
 606 #ifdef QEMU_GENERATE
 607 #define GETBYTE_FUNC(X) \
 608     __builtin_choose_expr(TYPE_TCGV(X), \
 609         gen_get_byte, \
 610         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 611             gen_get_byte_i64, (void)0))
 612 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
 613 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
 614 #else
 615 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
 616 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
 617 #endif
 618
 619 #define fSETBYTE(N, DST, VAL) \
 620     do { \
 621         DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
 622         (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
 623     } while (0)
 624
 625 #ifdef QEMU_GENERATE
 626 #define fGETHALF(N, SRC)  gen_get_half(HALF, N, SRC, true)
 627 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
 628 #else
 629 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
 630 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
 631 #endif
 632 #define fSETHALF(N, DST, VAL) \
 633     do { \
 634         DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
 635         (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
 636     } while (0)
 637 #define fSETHALFw fSETHALF
 638 #define fSETHALFd fSETHALF
 639
 640 #define fGETWORD(N, SRC) \
 641     ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 642 #define fGETUWORD(N, SRC) \
 643     ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 644
 645 #define fSETWORD(N, DST, VAL) \
 646     do { \
 647         DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
 648               (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
 649     } while (0)
 650
 651 #define fSETBIT(N, DST, VAL) \
 652     do { \
 653         DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
 654     } while (0)
 655
 656 #define fGETBIT(N, SRC) (((SRC) >> N) & 1)
 657 #define fSETBITS(HI, LO, DST, VAL) \
 658     do { \
 659         int j; \
 660         for (j = LO; j <= HI; j++) { \
 661             fSETBIT(j, DST, VAL); \
 662         } \
 663     } while (0)
 664 #define fCOUNTONES_2(VAL) ctpop16(VAL)
 665 #define fCOUNTONES_4(VAL) ctpop32(VAL)
 666 #define fCOUNTONES_8(VAL) ctpop64(VAL)
 667 #define fBREV_8(VAL) revbit64(VAL)
 668 #define fBREV_4(VAL) revbit32(VAL)
 669 #define fCL1_8(VAL) clo64(VAL)
 670 #define fCL1_4(VAL) clo32(VAL)
 671 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16)
 672 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
 673 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
 674 #define fHIDE(A) A
 675 #define fCONSTLL(A) A##LL
 676 #define fECHO(A) (A)
 677
 678 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
 679 #define fPAUSE(IMM)
 680
 681 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
 682     ((VAL) << reg_field_info[FIELD].offset)
 683 #define fGET_REG_FIELD_MASK(FIELD) \
 684     (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
 685 #define fREAD_REG_FIELD(REG, FIELD) \
 686     fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
 687                    reg_field_info[FIELD].width, \
 688                    reg_field_info[FIELD].offset)
 689 #define fGET_FIELD(VAL, FIELD)
 690 #define fSET_FIELD(VAL, FIELD, NEWVAL)
 691 #define fBARRIER()
 692 #define fSYNCH()
 693 #define fISYNC()
 694 #define fDCFETCH(REG) \
 695     do { (void)REG; } while (0) /* Nothing to do in qemu */
 696 #define fICINVA(REG) \
 697     do { (void)REG; } while (0) /* Nothing to do in qemu */
 698 #define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
 699 #define fDCCLEANA(REG) \
 700     do { (void)REG; } while (0) /* Nothing to do in qemu */
 701 #define fDCCLEANINVA(REG) \
 702     do { (void)REG; } while (0) /* Nothing to do in qemu */
 703
 704 #define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
 705
 706 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
 707                                 STRBITNUM) /* Nothing */
 708
 709
 710 #endif