target/hexagon/macros.h

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_MACROS_H
  19 #define HEXAGON_MACROS_H
  20
  21 #include "cpu.h"
  22 #include "hex_regs.h"
  23 #include "reg_fields.h"
  24
  25 #define PCALIGN 4
  26 #define PCALIGN_MASK (PCALIGN - 1)
  27
  28 #define GET_FIELD(FIELD, REGIN) \
  29     fEXTRACTU_BITS(REGIN, reg_field_info[FIELD].width, \
  30                    reg_field_info[FIELD].offset)
  31
  32 #ifdef QEMU_GENERATE
  33 #define GET_USR_FIELD(FIELD, DST) \
  34     tcg_gen_extract_tl(DST, hex_gpr[HEX_REG_USR], \
  35                        reg_field_info[FIELD].offset, \
  36                        reg_field_info[FIELD].width)
  37
  38 #define TYPE_INT(X)          __builtin_types_compatible_p(typeof(X), int)
  39 #define TYPE_TCGV(X)         __builtin_types_compatible_p(typeof(X), TCGv)
  40 #define TYPE_TCGV_I64(X)     __builtin_types_compatible_p(typeof(X), TCGv_i64)
  41 #else
  42 #define GET_USR_FIELD(FIELD) \
  43     fEXTRACTU_BITS(env->gpr[HEX_REG_USR], reg_field_info[FIELD].width, \
  44                    reg_field_info[FIELD].offset)
  45
  46 #define SET_USR_FIELD(FIELD, VAL) \
  47     fINSERT_BITS(env->new_value[HEX_REG_USR], reg_field_info[FIELD].width, \
  48                  reg_field_info[FIELD].offset, (VAL))
  49 #endif
  50
  51 #ifdef QEMU_GENERATE
  52 /*
  53  * Section 5.5 of the Hexagon V67 Programmer's Reference Manual
  54  *
  55  * Slot 1 store with slot 0 load
  56  * A slot 1 store operation with a slot 0 load operation can appear in a packet.
  57  * The packet attribute :mem_noshuf inhibits the instruction reordering that
  58  * would otherwise be done by the assembler. For example:
  59  *     {
  60  *         memw(R5) = R2 // slot 1 store
  61  *         R3 = memh(R6) // slot 0 load
  62  *     }:mem_noshuf
  63  * Unlike most packetized operations, these memory operations are not executed
  64  * in parallel (Section 3.3.1). Instead, the store instruction in Slot 1
  65  * effectively executes first, followed by the load instruction in Slot 0. If
  66  * the addresses of the two operations are overlapping, the load will receive
  67  * the newly stored data. This feature is supported in processor versions
  68  * V65 or greater.
  69  *
  70  *
  71  * For qemu, we look for a load in slot 0 when there is  a store in slot 1
  72  * in the same packet.  When we see this, we call a helper that probes the
  73  * load to make sure it doesn't fault.  Then, we process the store ahead of
  74  * the actual load.
  75
  76  */
  77 #define CHECK_NOSHUF(VA, SIZE) \
  78     do { \
  79         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
  80             probe_noshuf_load(VA, SIZE, ctx->mem_idx); \
  81             process_store(ctx, 1); \
  82         } \
  83     } while (0)
  84
  85 #define CHECK_NOSHUF_PRED(GET_EA, SIZE, PRED) \
  86     do { \
  87         TCGLabel *label = gen_new_label(); \
  88         tcg_gen_brcondi_tl(TCG_COND_EQ, PRED, 0, label); \
  89         GET_EA; \
  90         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
  91             probe_noshuf_load(EA, SIZE, ctx->mem_idx); \
  92         } \
  93         gen_set_label(label); \
  94         if (insn->slot == 0 && ctx->pkt->pkt_has_store_s1) { \
  95             process_store(ctx, 1); \
  96         } \
  97     } while (0)
  98
  99 #define MEM_LOAD1s(DST, VA) \
 100     do { \
 101         CHECK_NOSHUF(VA, 1); \
 102         tcg_gen_qemu_ld8s(DST, VA, ctx->mem_idx); \
 103     } while (0)
 104 #define MEM_LOAD1u(DST, VA) \
 105     do { \
 106         CHECK_NOSHUF(VA, 1); \
 107         tcg_gen_qemu_ld8u(DST, VA, ctx->mem_idx); \
 108     } while (0)
 109 #define MEM_LOAD2s(DST, VA) \
 110     do { \
 111         CHECK_NOSHUF(VA, 2); \
 112         tcg_gen_qemu_ld16s(DST, VA, ctx->mem_idx); \
 113     } while (0)
 114 #define MEM_LOAD2u(DST, VA) \
 115     do { \
 116         CHECK_NOSHUF(VA, 2); \
 117         tcg_gen_qemu_ld16u(DST, VA, ctx->mem_idx); \
 118     } while (0)
 119 #define MEM_LOAD4s(DST, VA) \
 120     do { \
 121         CHECK_NOSHUF(VA, 4); \
 122         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 123     } while (0)
 124 #define MEM_LOAD4u(DST, VA) \
 125     do { \
 126         CHECK_NOSHUF(VA, 4); \
 127         tcg_gen_qemu_ld32s(DST, VA, ctx->mem_idx); \
 128     } while (0)
 129 #define MEM_LOAD8u(DST, VA) \
 130     do { \
 131         CHECK_NOSHUF(VA, 8); \
 132         tcg_gen_qemu_ld64(DST, VA, ctx->mem_idx); \
 133     } while (0)
 134
 135 #define MEM_STORE1_FUNC(X) \
 136     __builtin_choose_expr(TYPE_INT(X), \
 137         gen_store1i, \
 138         __builtin_choose_expr(TYPE_TCGV(X), \
 139             gen_store1, (void)0))
 140 #define MEM_STORE1(VA, DATA, SLOT) \
 141     MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 142
 143 #define MEM_STORE2_FUNC(X) \
 144     __builtin_choose_expr(TYPE_INT(X), \
 145         gen_store2i, \
 146         __builtin_choose_expr(TYPE_TCGV(X), \
 147             gen_store2, (void)0))
 148 #define MEM_STORE2(VA, DATA, SLOT) \
 149     MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 150
 151 #define MEM_STORE4_FUNC(X) \
 152     __builtin_choose_expr(TYPE_INT(X), \
 153         gen_store4i, \
 154         __builtin_choose_expr(TYPE_TCGV(X), \
 155             gen_store4, (void)0))
 156 #define MEM_STORE4(VA, DATA, SLOT) \
 157     MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 158
 159 #define MEM_STORE8_FUNC(X) \
 160     __builtin_choose_expr(TYPE_INT(X), \
 161         gen_store8i, \
 162         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 163             gen_store8, (void)0))
 164 #define MEM_STORE8(VA, DATA, SLOT) \
 165     MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
 166 #else
 167 #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA))
 168 #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA))
 169 #define MEM_LOAD2s(VA) ((int16_t)mem_load2(env, slot, VA))
 170 #define MEM_LOAD2u(VA) ((uint16_t)mem_load2(env, slot, VA))
 171 #define MEM_LOAD4s(VA) ((int32_t)mem_load4(env, slot, VA))
 172 #define MEM_LOAD4u(VA) ((uint32_t)mem_load4(env, slot, VA))
 173 #define MEM_LOAD8s(VA) ((int64_t)mem_load8(env, slot, VA))
 174 #define MEM_LOAD8u(VA) ((uint64_t)mem_load8(env, slot, VA))
 175
 176 #define MEM_STORE1(VA, DATA, SLOT) log_store32(env, VA, DATA, 1, SLOT)
 177 #define MEM_STORE2(VA, DATA, SLOT) log_store32(env, VA, DATA, 2, SLOT)
 178 #define MEM_STORE4(VA, DATA, SLOT) log_store32(env, VA, DATA, 4, SLOT)
 179 #define MEM_STORE8(VA, DATA, SLOT) log_store64(env, VA, DATA, 8, SLOT)
 180 #endif
 181
 182 #ifdef QEMU_GENERATE
 183 static inline void gen_cancel(uint32_t slot)
 184 {
 185     tcg_gen_ori_tl(hex_slot_cancelled, hex_slot_cancelled, 1 << slot);
 186 }
 187
 188 #define CANCEL gen_cancel(slot);
 189 #else
 190 #define CANCEL do { } while (0)
 191 #endif
 192
 193 #define LOAD_CANCEL(EA) do { CANCEL; } while (0)
 194
 195 #define STORE_CANCEL(EA) { env->slot_cancelled |= (1 << slot); }
 196
 197 #define fMAX(A, B) (((A) > (B)) ? (A) : (B))
 198
 199 #define fMIN(A, B) (((A) < (B)) ? (A) : (B))
 200
 201 #define fABS(A) (((A) < 0) ? (-(A)) : (A))
 202 #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \
 203     REG = ((WIDTH) ? deposit64(REG, (OFFSET), (WIDTH), (INVAL)) : REG)
 204 #define fEXTRACTU_BITS(INREG, WIDTH, OFFSET) \
 205     ((WIDTH) ? extract64((INREG), (OFFSET), (WIDTH)) : 0LL)
 206 #define fEXTRACTU_BIDIR(INREG, WIDTH, OFFSET) \
 207     (fZXTN(WIDTH, 32, fBIDIR_LSHIFTR((INREG), (OFFSET), 4_8)))
 208 #define fEXTRACTU_RANGE(INREG, HIBIT, LOWBIT) \
 209     (((HIBIT) - (LOWBIT) + 1) ? \
 210         extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \
 211         0LL)
 212 #define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \
 213     do { \
 214         int width = ((HIBIT) - (LOWBIT) + 1); \
 215         INREG = (width >= 0 ? \
 216             deposit64((INREG), (LOWBIT), width, (INVAL)) : \
 217             INREG); \
 218     } while (0)
 219
 220 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00)
 221
 222 #ifdef QEMU_GENERATE
 223 #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1)
 224 #else
 225 #define fLSBOLD(VAL)  ((VAL) & 1)
 226 #endif
 227
 228 #ifdef QEMU_GENERATE
 229 #define fLSBNEW(PVAL)   tcg_gen_andi_tl(LSB, (PVAL), 1)
 230 #define fLSBNEW0        tcg_gen_andi_tl(LSB, hex_new_pred_value[0], 1)
 231 #define fLSBNEW1        tcg_gen_andi_tl(LSB, hex_new_pred_value[1], 1)
 232 #else
 233 #define fLSBNEW(PVAL)   ((PVAL) & 1)
 234 #define fLSBNEW0        (env->new_pred_value[0] & 1)
 235 #define fLSBNEW1        (env->new_pred_value[1] & 1)
 236 #endif
 237
 238 #ifdef QEMU_GENERATE
 239 #define fLSBOLDNOT(VAL) \
 240     do { \
 241         tcg_gen_andi_tl(LSB, (VAL), 1); \
 242         tcg_gen_xori_tl(LSB, LSB, 1); \
 243     } while (0)
 244 #define fLSBNEWNOT(PNUM) \
 245     do { \
 246         tcg_gen_andi_tl(LSB, (PNUM), 1); \
 247         tcg_gen_xori_tl(LSB, LSB, 1); \
 248     } while (0)
 249 #else
 250 #define fLSBNEWNOT(PNUM) (!fLSBNEW(PNUM))
 251 #define fLSBOLDNOT(VAL) (!fLSBOLD(VAL))
 252 #define fLSBNEW0NOT (!fLSBNEW0)
 253 #define fLSBNEW1NOT (!fLSBNEW1)
 254 #endif
 255
 256 #define fNEWREG(VAL) ((int32_t)(VAL))
 257
 258 #define fNEWREG_ST(VAL) (VAL)
 259
 260 #define fVSATUVALN(N, VAL) \
 261     ({ \
 262         (((int64_t)(VAL)) < 0) ? 0 : ((1LL << (N)) - 1); \
 263     })
 264 #define fSATUVALN(N, VAL) \
 265     ({ \
 266         fSET_OVERFLOW(); \
 267         ((VAL) < 0) ? 0 : ((1LL << (N)) - 1); \
 268     })
 269 #define fSATVALN(N, VAL) \
 270     ({ \
 271         fSET_OVERFLOW(); \
 272         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 273     })
 274 #define fVSATVALN(N, VAL) \
 275     ({ \
 276         ((VAL) < 0) ? (-(1LL << ((N) - 1))) : ((1LL << ((N) - 1)) - 1); \
 277     })
 278 #define fZXTN(N, M, VAL) (((N) != 0) ? extract64((VAL), 0, (N)) : 0LL)
 279 #define fSXTN(N, M, VAL) (((N) != 0) ? sextract64((VAL), 0, (N)) : 0LL)
 280 #define fSATN(N, VAL) \
 281     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATVALN(N, VAL))
 282 #define fVSATN(N, VAL) \
 283     ((fSXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATVALN(N, VAL))
 284 #define fADDSAT64(DST, A, B) \
 285     do { \
 286         uint64_t __a = fCAST8u(A); \
 287         uint64_t __b = fCAST8u(B); \
 288         uint64_t __sum = __a + __b; \
 289         uint64_t __xor = __a ^ __b; \
 290         const uint64_t __mask = 0x8000000000000000ULL; \
 291         if (__xor & __mask) { \
 292             DST = __sum; \
 293         } \
 294         else if ((__a ^ __sum) & __mask) { \
 295             if (__sum & __mask) { \
 296                 DST = 0x7FFFFFFFFFFFFFFFLL; \
 297                 fSET_OVERFLOW(); \
 298             } else { \
 299                 DST = 0x8000000000000000LL; \
 300                 fSET_OVERFLOW(); \
 301             } \
 302         } else { \
 303             DST = __sum; \
 304         } \
 305     } while (0)
 306 #define fVSATUN(N, VAL) \
 307     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fVSATUVALN(N, VAL))
 308 #define fSATUN(N, VAL) \
 309     ((fZXTN(N, 64, VAL) == (VAL)) ? (VAL) : fSATUVALN(N, VAL))
 310 #define fSATH(VAL) (fSATN(16, VAL))
 311 #define fSATUH(VAL) (fSATUN(16, VAL))
 312 #define fVSATH(VAL) (fVSATN(16, VAL))
 313 #define fVSATUH(VAL) (fVSATUN(16, VAL))
 314 #define fSATUB(VAL) (fSATUN(8, VAL))
 315 #define fSATB(VAL) (fSATN(8, VAL))
 316 #define fVSATUB(VAL) (fVSATUN(8, VAL))
 317 #define fVSATB(VAL) (fVSATN(8, VAL))
 318 #define fIMMEXT(IMM) (IMM = IMM)
 319 #define fMUST_IMMEXT(IMM) fIMMEXT(IMM)
 320
 321 #define fPCALIGN(IMM) IMM = (IMM & ~PCALIGN_MASK)
 322
 323 #ifdef QEMU_GENERATE
 324 static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 325 {
 326     /*
 327      * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual
 328      *
 329      *  The "I" value from a modifier register is divided into two pieces
 330      *      LSB         bits 23:17
 331      *      MSB         bits 31:28
 332      * The value is signed
 333      *
 334      * At the end we shift the result according to the shift argument
 335      */
 336     TCGv msb = tcg_temp_new();
 337     TCGv lsb = tcg_temp_new();
 338
 339     tcg_gen_extract_tl(lsb, val, 17, 7);
 340     tcg_gen_sari_tl(msb, val, 21);
 341     tcg_gen_deposit_tl(result, msb, lsb, 0, 7);
 342
 343     tcg_gen_shli_tl(result, result, shift);
 344     return result;
 345 }
 346 #endif
 347
 348 #define fREAD_LR() (env->gpr[HEX_REG_LR])
 349
 350 #define fWRITE_LR(A) log_reg_write(env, HEX_REG_LR, A)
 351 #define fWRITE_FP(A) log_reg_write(env, HEX_REG_FP, A)
 352 #define fWRITE_SP(A) log_reg_write(env, HEX_REG_SP, A)
 353
 354 #define fREAD_SP() (env->gpr[HEX_REG_SP])
 355 #define fREAD_LC0 (env->gpr[HEX_REG_LC0])
 356 #define fREAD_LC1 (env->gpr[HEX_REG_LC1])
 357 #define fREAD_SA0 (env->gpr[HEX_REG_SA0])
 358 #define fREAD_SA1 (env->gpr[HEX_REG_SA1])
 359 #define fREAD_FP() (env->gpr[HEX_REG_FP])
 360 #ifdef FIXME
 361 /* Figure out how to get insn->extension_valid to helper */
 362 #define fREAD_GP() \
 363     (insn->extension_valid ? 0 : env->gpr[HEX_REG_GP])
 364 #else
 365 #define fREAD_GP() (env->gpr[HEX_REG_GP])
 366 #endif
 367 #define fREAD_PC() (PC)
 368
 369 #define fREAD_P0() (env->pred[0])
 370
 371 #define fCHECK_PCALIGN(A)
 372
 373 #define fWRITE_NPC(A) write_new_pc(env, pkt_has_multi_cof != 0, A)
 374
 375 #define fBRANCH(LOC, TYPE)          fWRITE_NPC(LOC)
 376 #define fJUMPR(REGNO, TARGET, TYPE) fBRANCH(TARGET, COF_TYPE_JUMPR)
 377 #define fHINTJR(TARGET) { /* Not modelled in qemu */}
 378 #define fWRITE_LOOP_REGS0(START, COUNT) \
 379     do { \
 380         log_reg_write(env, HEX_REG_LC0, COUNT);  \
 381         log_reg_write(env, HEX_REG_SA0, START); \
 382     } while (0)
 383 #define fWRITE_LOOP_REGS1(START, COUNT) \
 384     do { \
 385         log_reg_write(env, HEX_REG_LC1, COUNT);  \
 386         log_reg_write(env, HEX_REG_SA1, START);\
 387     } while (0)
 388
 389 #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1)
 390 #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL))
 391 #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG))
 392 #define fWRITE_P0(VAL) log_pred_write(env, 0, VAL)
 393 #define fWRITE_P1(VAL) log_pred_write(env, 1, VAL)
 394 #define fWRITE_P2(VAL) log_pred_write(env, 2, VAL)
 395 #define fWRITE_P3(VAL) log_pred_write(env, 3, VAL)
 396 #define fPART1(WORK) if (part1) { WORK; return; }
 397 #define fCAST4u(A) ((uint32_t)(A))
 398 #define fCAST4s(A) ((int32_t)(A))
 399 #define fCAST8u(A) ((uint64_t)(A))
 400 #define fCAST8s(A) ((int64_t)(A))
 401 #define fCAST2_2s(A) ((int16_t)(A))
 402 #define fCAST2_2u(A) ((uint16_t)(A))
 403 #define fCAST4_4s(A) ((int32_t)(A))
 404 #define fCAST4_4u(A) ((uint32_t)(A))
 405 #define fCAST4_8s(A) ((int64_t)((int32_t)(A)))
 406 #define fCAST4_8u(A) ((uint64_t)((uint32_t)(A)))
 407 #define fCAST8_8s(A) ((int64_t)(A))
 408 #define fCAST8_8u(A) ((uint64_t)(A))
 409 #define fCAST2_8s(A) ((int64_t)((int16_t)(A)))
 410 #define fCAST2_8u(A) ((uint64_t)((uint16_t)(A)))
 411 #define fZE8_16(A) ((int16_t)((uint8_t)(A)))
 412 #define fSE8_16(A) ((int16_t)((int8_t)(A)))
 413 #define fSE16_32(A) ((int32_t)((int16_t)(A)))
 414 #define fZE16_32(A) ((uint32_t)((uint16_t)(A)))
 415 #define fSE32_64(A) ((int64_t)((int32_t)(A)))
 416 #define fZE32_64(A) ((uint64_t)((uint32_t)(A)))
 417 #define fSE8_32(A) ((int32_t)((int8_t)(A)))
 418 #define fZE8_32(A) ((int32_t)((uint8_t)(A)))
 419 #define fMPY8UU(A, B) (int)(fZE8_16(A) * fZE8_16(B))
 420 #define fMPY8US(A, B) (int)(fZE8_16(A) * fSE8_16(B))
 421 #define fMPY8SU(A, B) (int)(fSE8_16(A) * fZE8_16(B))
 422 #define fMPY8SS(A, B) (int)((short)(A) * (short)(B))
 423 #define fMPY16SS(A, B) fSE32_64(fSE16_32(A) * fSE16_32(B))
 424 #define fMPY16UU(A, B) fZE32_64(fZE16_32(A) * fZE16_32(B))
 425 #define fMPY16SU(A, B) fSE32_64(fSE16_32(A) * fZE16_32(B))
 426 #define fMPY16US(A, B) fMPY16SU(B, A)
 427 #define fMPY32SS(A, B) (fSE32_64(A) * fSE32_64(B))
 428 #define fMPY32UU(A, B) (fZE32_64(A) * fZE32_64(B))
 429 #define fMPY32SU(A, B) (fSE32_64(A) * fZE32_64(B))
 430 #define fMPY3216SS(A, B) (fSE32_64(A) * fSXTN(16, 64, B))
 431 #define fMPY3216SU(A, B) (fSE32_64(A) * fZXTN(16, 64, B))
 432 #define fROUND(A) (A + 0x8000)
 433 #define fCLIP(DST, SRC, U) \
 434     do { \
 435         int32_t maxv = (1 << U) - 1; \
 436         int32_t minv = -(1 << U); \
 437         DST = fMIN(maxv, fMAX(SRC, minv)); \
 438     } while (0)
 439 #define fCRND(A) ((((A) & 0x3) == 0x3) ? ((A) + 1) : ((A)))
 440 #define fRNDN(A, N) ((((N) == 0) ? (A) : (((fSE32_64(A)) + (1 << ((N) - 1))))))
 441 #define fCRNDN(A, N) (conv_round(A, N))
 442 #define fADD128(A, B) (int128_add(A, B))
 443 #define fSUB128(A, B) (int128_sub(A, B))
 444 #define fSHIFTR128(A, B) (int128_rshift(A, B))
 445 #define fSHIFTL128(A, B) (int128_lshift(A, B))
 446 #define fAND128(A, B) (int128_and(A, B))
 447 #define fCAST8S_16S(A) (int128_exts64(A))
 448 #define fCAST16S_8S(A) (int128_getlo(A))
 449
 450 #ifdef QEMU_GENERATE
 451 #define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM)
 452 #define fEA_RRs(REG, REG2, SCALE) \
 453     do { \
 454         TCGv tmp = tcg_temp_new(); \
 455         tcg_gen_shli_tl(tmp, REG2, SCALE); \
 456         tcg_gen_add_tl(EA, REG, tmp); \
 457     } while (0)
 458 #define fEA_IRs(IMM, REG, SCALE) \
 459     do { \
 460         tcg_gen_shli_tl(EA, REG, SCALE); \
 461         tcg_gen_addi_tl(EA, EA, IMM); \
 462     } while (0)
 463 #else
 464 #define fEA_RI(REG, IMM) \
 465     do { \
 466         EA = REG + IMM; \
 467     } while (0)
 468 #define fEA_RRs(REG, REG2, SCALE) \
 469     do { \
 470         EA = REG + (REG2 << SCALE); \
 471     } while (0)
 472 #define fEA_IRs(IMM, REG, SCALE) \
 473     do { \
 474         EA = IMM + (REG << SCALE); \
 475     } while (0)
 476 #endif
 477
 478 #ifdef QEMU_GENERATE
 479 #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM)
 480 #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG)
 481 #define fEA_BREVR(REG)      gen_helper_fbrev(EA, REG)
 482 #define fPM_I(REG, IMM)     tcg_gen_addi_tl(REG, REG, IMM)
 483 #define fPM_M(REG, MVAL)    tcg_gen_add_tl(REG, REG, MVAL)
 484 #define fPM_CIRI(REG, IMM, MVAL) \
 485     do { \
 486         TCGv tcgv_siV = tcg_constant_tl(siV); \
 487         gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, \
 488                             hex_gpr[HEX_REG_CS0 + MuN]); \
 489     } while (0)
 490 #else
 491 #define fEA_IMM(IMM)        do { EA = (IMM); } while (0)
 492 #define fEA_REG(REG)        do { EA = (REG); } while (0)
 493 #define fEA_GPI(IMM)        do { EA = (fREAD_GP() + (IMM)); } while (0)
 494 #define fPM_I(REG, IMM)     do { REG = REG + (IMM); } while (0)
 495 #define fPM_M(REG, MVAL)    do { REG = REG + (MVAL); } while (0)
 496 #endif
 497 #define fSCALE(N, A) (((int64_t)(A)) << N)
 498 #define fVSATW(A) fVSATN(32, ((long long)A))
 499 #define fSATW(A) fSATN(32, ((long long)A))
 500 #define fVSAT(A) fVSATN(32, (A))
 501 #define fSAT(A) fSATN(32, (A))
 502 #define fSAT_ORIG_SHL(A, ORIG_REG) \
 503     ((((int32_t)((fSAT(A)) ^ ((int32_t)(ORIG_REG)))) < 0) \
 504         ? fSATVALN(32, ((int32_t)(ORIG_REG))) \
 505         : ((((ORIG_REG) > 0) && ((A) == 0)) ? fSATVALN(32, (ORIG_REG)) \
 506                                             : fSAT(A)))
 507 #define fPASS(A) A
 508 #define fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE) \
 509     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 510                    : (fCAST##REGSTYPE(SRC) << (SHAMT)))
 511 #define fBIDIR_ASHIFTL(SRC, SHAMT, REGSTYPE) \
 512     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##s)
 513 #define fBIDIR_LSHIFTL(SRC, SHAMT, REGSTYPE) \
 514     fBIDIR_SHIFTL(SRC, SHAMT, REGSTYPE##u)
 515 #define fBIDIR_ASHIFTL_SAT(SRC, SHAMT, REGSTYPE) \
 516     (((SHAMT) < 0) ? ((fCAST##REGSTYPE##s(SRC) >> ((-(SHAMT)) - 1)) >> 1) \
 517                    : fSAT_ORIG_SHL(fCAST##REGSTYPE##s(SRC) << (SHAMT), (SRC)))
 518 #define fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE) \
 519     (((SHAMT) < 0) ? ((fCAST##REGSTYPE(SRC) << ((-(SHAMT)) - 1)) << 1) \
 520                    : (fCAST##REGSTYPE(SRC) >> (SHAMT)))
 521 #define fBIDIR_ASHIFTR(SRC, SHAMT, REGSTYPE) \
 522     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##s)
 523 #define fBIDIR_LSHIFTR(SRC, SHAMT, REGSTYPE) \
 524     fBIDIR_SHIFTR(SRC, SHAMT, REGSTYPE##u)
 525 #define fBIDIR_ASHIFTR_SAT(SRC, SHAMT, REGSTYPE) \
 526     (((SHAMT) < 0) ? fSAT_ORIG_SHL((fCAST##REGSTYPE##s(SRC) \
 527                         << ((-(SHAMT)) - 1)) << 1, (SRC)) \
 528                    : (fCAST##REGSTYPE##s(SRC) >> (SHAMT)))
 529 #define fASHIFTR(SRC, SHAMT, REGSTYPE) (fCAST##REGSTYPE##s(SRC) >> (SHAMT))
 530 #define fLSHIFTR(SRC, SHAMT, REGSTYPE) \
 531     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##u(SRC) >> (SHAMT)))
 532 #define fROTL(SRC, SHAMT, REGSTYPE) \
 533     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) << (SHAMT)) | \
 534                               ((fCAST##REGSTYPE##u(SRC) >> \
 535                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 536 #define fROTR(SRC, SHAMT, REGSTYPE) \
 537     (((SHAMT) == 0) ? (SRC) : ((fCAST##REGSTYPE##u(SRC) >> (SHAMT)) | \
 538                               ((fCAST##REGSTYPE##u(SRC) << \
 539                                  ((sizeof(SRC) * 8) - (SHAMT))))))
 540 #define fASHIFTL(SRC, SHAMT, REGSTYPE) \
 541     (((SHAMT) >= (sizeof(SRC) * 8)) ? 0 : (fCAST##REGSTYPE##s(SRC) << (SHAMT)))
 542
 543 #ifdef QEMU_GENERATE
 544 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
 545 #else
 546 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
 547     DST = (size##SIZE##SIGN##_t)MEM_LOAD##SIZE##SIGN(EA)
 548 #endif
 549
 550 #define fMEMOP(NUM, SIZE, SIGN, EA, FNTYPE, VALUE)
 551
 552 #define fGET_FRAMEKEY() (env->gpr[HEX_REG_FRAMEKEY])
 553 #define fFRAME_SCRAMBLE(VAL) ((VAL) ^ (fCAST8u(fGET_FRAMEKEY()) << 32))
 554 #define fFRAME_UNSCRAMBLE(VAL) fFRAME_SCRAMBLE(VAL)
 555
 556 #ifdef CONFIG_USER_ONLY
 557 #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-user */
 558 #else
 559 /* System mode not implemented yet */
 560 #define fFRAMECHECK(ADDR, EA)  g_assert_not_reached();
 561 #endif
 562
 563 #ifdef QEMU_GENERATE
 564 #define fLOAD_LOCKED(NUM, SIZE, SIGN, EA, DST) \
 565     gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx);
 566 #endif
 567
 568 #ifdef QEMU_GENERATE
 569 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot)
 570 #else
 571 #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot)
 572 #endif
 573
 574 #ifdef QEMU_GENERATE
 575 #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \
 576     gen_store_conditional##SIZE(ctx, PRED, EA, SRC);
 577 #endif
 578
 579 #ifdef QEMU_GENERATE
 580 #define GETBYTE_FUNC(X) \
 581     __builtin_choose_expr(TYPE_TCGV(X), \
 582         gen_get_byte, \
 583         __builtin_choose_expr(TYPE_TCGV_I64(X), \
 584             gen_get_byte_i64, (void)0))
 585 #define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true)
 586 #define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false)
 587 #else
 588 #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff))
 589 #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff))
 590 #endif
 591
 592 #define fSETBYTE(N, DST, VAL) \
 593     do { \
 594         DST = (DST & ~(0x0ffLL << ((N) * 8))) | \
 595         (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \
 596     } while (0)
 597
 598 #ifdef QEMU_GENERATE
 599 #define fGETHALF(N, SRC)  gen_get_half(HALF, N, SRC, true)
 600 #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false)
 601 #else
 602 #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff))
 603 #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff))
 604 #endif
 605 #define fSETHALF(N, DST, VAL) \
 606     do { \
 607         DST = (DST & ~(0x0ffffLL << ((N) * 16))) | \
 608         (((uint64_t)((VAL) & 0x0ffff)) << ((N) * 16)); \
 609     } while (0)
 610 #define fSETHALFw fSETHALF
 611 #define fSETHALFd fSETHALF
 612
 613 #define fGETWORD(N, SRC) \
 614     ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 615 #define fGETUWORD(N, SRC) \
 616     ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL)))
 617
 618 #define fSETWORD(N, DST, VAL) \
 619     do { \
 620         DST = (DST & ~(0x0ffffffffLL << ((N) * 32))) | \
 621               (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \
 622     } while (0)
 623
 624 #define fSETBIT(N, DST, VAL) \
 625     do { \
 626         DST = (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \
 627     } while (0)
 628
 629 #define fGETBIT(N, SRC) (((SRC) >> N) & 1)
 630 #define fSETBITS(HI, LO, DST, VAL) \
 631     do { \
 632         int j; \
 633         for (j = LO; j <= HI; j++) { \
 634             fSETBIT(j, DST, VAL); \
 635         } \
 636     } while (0)
 637 #define fCOUNTONES_2(VAL) ctpop16(VAL)
 638 #define fCOUNTONES_4(VAL) ctpop32(VAL)
 639 #define fCOUNTONES_8(VAL) ctpop64(VAL)
 640 #define fBREV_8(VAL) revbit64(VAL)
 641 #define fBREV_4(VAL) revbit32(VAL)
 642 #define fCL1_8(VAL) clo64(VAL)
 643 #define fCL1_4(VAL) clo32(VAL)
 644 #define fCL1_2(VAL) (clz32(~(uint16_t)(VAL) & 0xffff) - 16)
 645 #define fINTERLEAVE(ODD, EVEN) interleave(ODD, EVEN)
 646 #define fDEINTERLEAVE(MIXED) deinterleave(MIXED)
 647 #define fHIDE(A) A
 648 #define fCONSTLL(A) A##LL
 649 #define fECHO(A) (A)
 650
 651 #define fTRAP(TRAPTYPE, IMM) helper_raise_exception(env, HEX_EXCP_TRAP0)
 652 #define fPAUSE(IMM)
 653
 654 #define fALIGN_REG_FIELD_VALUE(FIELD, VAL) \
 655     ((VAL) << reg_field_info[FIELD].offset)
 656 #define fGET_REG_FIELD_MASK(FIELD) \
 657     (((1 << reg_field_info[FIELD].width) - 1) << reg_field_info[FIELD].offset)
 658 #define fREAD_REG_FIELD(REG, FIELD) \
 659     fEXTRACTU_BITS(env->gpr[HEX_REG_##REG], \
 660                    reg_field_info[FIELD].width, \
 661                    reg_field_info[FIELD].offset)
 662 #define fBARRIER()
 663 #define fSYNCH()
 664 #define fISYNC()
 665 #define fDCFETCH(REG) \
 666     do { (void)REG; } while (0) /* Nothing to do in qemu */
 667 #define fICINVA(REG) \
 668     do { (void)REG; } while (0) /* Nothing to do in qemu */
 669 #define fL2FETCH(ADDR, HEIGHT, WIDTH, STRIDE, FLAGS)
 670 #define fDCCLEANA(REG) \
 671     do { (void)REG; } while (0) /* Nothing to do in qemu */
 672 #define fDCCLEANINVA(REG) \
 673     do { (void)REG; } while (0) /* Nothing to do in qemu */
 674
 675 #define fDCZEROA(REG) do { env->dczero_addr = (REG); } while (0)
 676
 677 #define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \
 678                                 STRBITNUM) /* Nothing */
 679
 680
 681 #endif