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Hexagon (iclass): update J4_hintjumpr slot constraints
[mirror_qemu.git] / target / hexagon / reg_fields_def.h.inc
1 /*
2 * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 /*
19 * For registers that have individual fields, explain them here
20 * DEF_REG_FIELD(tag,
21 * bit start offset,
22 * width
23 */
24
25 /* USR fields */
26 DEF_REG_FIELD(USR_OVF, 0, 1)
27 DEF_REG_FIELD(USR_FPINVF, 1, 1)
28 DEF_REG_FIELD(USR_FPDBZF, 2, 1)
29 DEF_REG_FIELD(USR_FPOVFF, 3, 1)
30 DEF_REG_FIELD(USR_FPUNFF, 4, 1)
31 DEF_REG_FIELD(USR_FPINPF, 5, 1)
32
33 DEF_REG_FIELD(USR_LPCFG, 8, 2)
34
35 DEF_REG_FIELD(USR_FPRND, 22, 2)
36
37 DEF_REG_FIELD(USR_FPINVE, 25, 1)
38 DEF_REG_FIELD(USR_FPDBZE, 26, 1)
39 DEF_REG_FIELD(USR_FPOVFE, 27, 1)
40 DEF_REG_FIELD(USR_FPUNFE, 28, 1)
41 DEF_REG_FIELD(USR_FPINPE, 29, 1)