2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
23 #include "exec/cpu_ldst.h"
29 #include "translate.h"
30 #include "printinsn.h"
32 TCGv hex_gpr
[TOTAL_PER_THREAD_REGS
];
33 TCGv hex_pred
[NUM_PREGS
];
35 TCGv hex_slot_cancelled
;
36 TCGv hex_branch_taken
;
37 TCGv hex_new_value
[TOTAL_PER_THREAD_REGS
];
38 TCGv hex_reg_written
[TOTAL_PER_THREAD_REGS
];
39 TCGv hex_new_pred_value
[NUM_PREGS
];
40 TCGv hex_pred_written
;
41 TCGv hex_store_addr
[STORES_MAX
];
42 TCGv hex_store_width
[STORES_MAX
];
43 TCGv hex_store_val32
[STORES_MAX
];
44 TCGv_i64 hex_store_val64
[STORES_MAX
];
45 TCGv hex_pkt_has_store_s1
;
49 TCGv_i64 hex_llsc_val_i64
;
50 TCGv hex_VRegs_updated
;
51 TCGv hex_QRegs_updated
;
52 TCGv hex_vstore_addr
[VSTORES_MAX
];
53 TCGv hex_vstore_size
[VSTORES_MAX
];
54 TCGv hex_vstore_pending
[VSTORES_MAX
];
56 static const char * const hexagon_prednames
[] = {
57 "p0", "p1", "p2", "p3"
60 intptr_t ctx_future_vreg_off(DisasContext
*ctx
, int regnum
,
61 int num
, bool alloc_ok
)
65 /* See if it is already allocated */
66 for (int i
= 0; i
< ctx
->future_vregs_idx
; i
++) {
67 if (ctx
->future_vregs_num
[i
] == regnum
) {
68 return offsetof(CPUHexagonState
, future_VRegs
[i
]);
73 offset
= offsetof(CPUHexagonState
, future_VRegs
[ctx
->future_vregs_idx
]);
74 for (int i
= 0; i
< num
; i
++) {
75 ctx
->future_vregs_num
[ctx
->future_vregs_idx
+ i
] = regnum
++;
77 ctx
->future_vregs_idx
+= num
;
78 g_assert(ctx
->future_vregs_idx
<= VECTOR_TEMPS_MAX
);
82 intptr_t ctx_tmp_vreg_off(DisasContext
*ctx
, int regnum
,
83 int num
, bool alloc_ok
)
87 /* See if it is already allocated */
88 for (int i
= 0; i
< ctx
->tmp_vregs_idx
; i
++) {
89 if (ctx
->tmp_vregs_num
[i
] == regnum
) {
90 return offsetof(CPUHexagonState
, tmp_VRegs
[i
]);
95 offset
= offsetof(CPUHexagonState
, tmp_VRegs
[ctx
->tmp_vregs_idx
]);
96 for (int i
= 0; i
< num
; i
++) {
97 ctx
->tmp_vregs_num
[ctx
->tmp_vregs_idx
+ i
] = regnum
++;
99 ctx
->tmp_vregs_idx
+= num
;
100 g_assert(ctx
->tmp_vregs_idx
<= VECTOR_TEMPS_MAX
);
104 static void gen_exception_raw(int excp
)
106 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
109 static void gen_exec_counters(DisasContext
*ctx
)
111 tcg_gen_addi_tl(hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
112 hex_gpr
[HEX_REG_QEMU_PKT_CNT
], ctx
->num_packets
);
113 tcg_gen_addi_tl(hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
114 hex_gpr
[HEX_REG_QEMU_INSN_CNT
], ctx
->num_insns
);
115 tcg_gen_addi_tl(hex_gpr
[HEX_REG_QEMU_HVX_CNT
],
116 hex_gpr
[HEX_REG_QEMU_HVX_CNT
], ctx
->num_hvx_insns
);
119 static bool use_goto_tb(DisasContext
*ctx
, target_ulong dest
)
121 return translator_use_goto_tb(&ctx
->base
, dest
);
124 static void gen_goto_tb(DisasContext
*ctx
, int idx
, target_ulong dest
)
126 if (use_goto_tb(ctx
, dest
)) {
127 tcg_gen_goto_tb(idx
);
128 tcg_gen_movi_tl(hex_gpr
[HEX_REG_PC
], dest
);
129 tcg_gen_exit_tb(ctx
->base
.tb
, idx
);
131 tcg_gen_movi_tl(hex_gpr
[HEX_REG_PC
], dest
);
132 tcg_gen_lookup_and_goto_ptr();
136 static void gen_end_tb(DisasContext
*ctx
)
138 Packet
*pkt
= ctx
->pkt
;
140 gen_exec_counters(ctx
);
142 if (ctx
->branch_cond
!= TCG_COND_NEVER
) {
143 if (ctx
->branch_cond
!= TCG_COND_ALWAYS
) {
144 TCGLabel
*skip
= gen_new_label();
145 tcg_gen_brcondi_tl(ctx
->branch_cond
, hex_branch_taken
, 0, skip
);
146 gen_goto_tb(ctx
, 0, ctx
->branch_dest
);
148 gen_goto_tb(ctx
, 1, ctx
->next_PC
);
150 gen_goto_tb(ctx
, 0, ctx
->branch_dest
);
152 } else if (ctx
->is_tight_loop
&&
153 pkt
->insn
[pkt
->num_insns
- 1].opcode
== J2_endloop0
) {
155 * When we're in a tight loop, we defer the endloop0 processing
156 * to take advantage of direct block chaining
158 TCGLabel
*skip
= gen_new_label();
159 tcg_gen_brcondi_tl(TCG_COND_LEU
, hex_gpr
[HEX_REG_LC0
], 1, skip
);
160 tcg_gen_subi_tl(hex_gpr
[HEX_REG_LC0
], hex_gpr
[HEX_REG_LC0
], 1);
161 gen_goto_tb(ctx
, 0, ctx
->base
.tb
->pc
);
163 gen_goto_tb(ctx
, 1, ctx
->next_PC
);
165 tcg_gen_lookup_and_goto_ptr();
168 ctx
->base
.is_jmp
= DISAS_NORETURN
;
171 static void gen_exception_end_tb(DisasContext
*ctx
, int excp
)
173 gen_exec_counters(ctx
);
174 tcg_gen_movi_tl(hex_gpr
[HEX_REG_PC
], ctx
->next_PC
);
175 gen_exception_raw(excp
);
176 ctx
->base
.is_jmp
= DISAS_NORETURN
;
180 #define PACKET_BUFFER_LEN 1028
181 static void print_pkt(Packet
*pkt
)
183 GString
*buf
= g_string_sized_new(PACKET_BUFFER_LEN
);
184 snprint_a_pkt_debug(buf
, pkt
);
185 HEX_DEBUG_LOG("%s", buf
->str
);
186 g_string_free(buf
, true);
188 #define HEX_DEBUG_PRINT_PKT(pkt) \
195 static int read_packet_words(CPUHexagonState
*env
, DisasContext
*ctx
,
198 bool found_end
= false;
199 int nwords
, max_words
;
201 memset(words
, 0, PACKET_WORDS_MAX
* sizeof(uint32_t));
202 for (nwords
= 0; !found_end
&& nwords
< PACKET_WORDS_MAX
; nwords
++) {
204 translator_ldl(env
, &ctx
->base
,
205 ctx
->base
.pc_next
+ nwords
* sizeof(uint32_t));
206 found_end
= is_packet_end(words
[nwords
]);
209 /* Read too many words without finding the end */
213 /* Check for page boundary crossing */
214 max_words
= -(ctx
->base
.pc_next
| TARGET_PAGE_MASK
) / sizeof(uint32_t);
215 if (nwords
> max_words
) {
216 /* We can only cross a page boundary at the beginning of a TB */
217 g_assert(ctx
->base
.num_insns
== 1);
220 HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx
->base
.pc_next
);
221 HEX_DEBUG_LOG(" words = { ");
222 for (int i
= 0; i
< nwords
; i
++) {
223 HEX_DEBUG_LOG("0x%x, ", words
[i
]);
225 HEX_DEBUG_LOG("}\n");
230 static bool check_for_attrib(Packet
*pkt
, int attrib
)
232 for (int i
= 0; i
< pkt
->num_insns
; i
++) {
233 if (GET_ATTRIB(pkt
->insn
[i
].opcode
, attrib
)) {
240 static bool need_slot_cancelled(Packet
*pkt
)
242 return check_for_attrib(pkt
, A_CONDEXEC
);
245 static bool need_pred_written(Packet
*pkt
)
247 return check_for_attrib(pkt
, A_WRITES_PRED_REG
);
250 static bool need_next_PC(DisasContext
*ctx
)
252 Packet
*pkt
= ctx
->pkt
;
254 /* Check for conditional control flow or HW loop end */
255 for (int i
= 0; i
< pkt
->num_insns
; i
++) {
256 uint16_t opcode
= pkt
->insn
[i
].opcode
;
257 if (GET_ATTRIB(opcode
, A_CONDEXEC
) && GET_ATTRIB(opcode
, A_COF
)) {
260 if (GET_ATTRIB(opcode
, A_HWLOOP0_END
) ||
261 GET_ATTRIB(opcode
, A_HWLOOP1_END
)) {
268 static void gen_start_packet(DisasContext
*ctx
)
270 Packet
*pkt
= ctx
->pkt
;
271 target_ulong next_PC
= ctx
->base
.pc_next
+ pkt
->encod_pkt_size_in_bytes
;
274 /* Clear out the disassembly context */
275 ctx
->next_PC
= next_PC
;
276 ctx
->reg_log_idx
= 0;
277 bitmap_zero(ctx
->regs_written
, TOTAL_PER_THREAD_REGS
);
278 ctx
->preg_log_idx
= 0;
279 bitmap_zero(ctx
->pregs_written
, NUM_PREGS
);
280 ctx
->future_vregs_idx
= 0;
281 ctx
->tmp_vregs_idx
= 0;
282 ctx
->vreg_log_idx
= 0;
283 bitmap_zero(ctx
->vregs_updated_tmp
, NUM_VREGS
);
284 bitmap_zero(ctx
->vregs_updated
, NUM_VREGS
);
285 bitmap_zero(ctx
->vregs_select
, NUM_VREGS
);
286 ctx
->qreg_log_idx
= 0;
287 for (i
= 0; i
< STORES_MAX
; i
++) {
288 ctx
->store_width
[i
] = 0;
290 tcg_gen_movi_tl(hex_pkt_has_store_s1
, pkt
->pkt_has_store_s1
);
291 ctx
->s1_store_processed
= false;
292 ctx
->pre_commit
= true;
295 /* Handy place to set a breakpoint before the packet executes */
296 gen_helper_debug_start_packet(cpu_env
);
297 tcg_gen_movi_tl(hex_this_PC
, ctx
->base
.pc_next
);
300 /* Initialize the runtime state for packet semantics */
301 if (need_slot_cancelled(pkt
)) {
302 tcg_gen_movi_tl(hex_slot_cancelled
, 0);
304 if (pkt
->pkt_has_cof
) {
305 if (pkt
->pkt_has_multi_cof
) {
306 tcg_gen_movi_tl(hex_branch_taken
, 0);
308 if (need_next_PC(ctx
)) {
309 tcg_gen_movi_tl(hex_gpr
[HEX_REG_PC
], next_PC
);
312 if (need_pred_written(pkt
)) {
313 tcg_gen_movi_tl(hex_pred_written
, 0);
316 if (pkt
->pkt_has_hvx
) {
317 tcg_gen_movi_tl(hex_VRegs_updated
, 0);
318 tcg_gen_movi_tl(hex_QRegs_updated
, 0);
322 bool is_gather_store_insn(DisasContext
*ctx
)
324 Packet
*pkt
= ctx
->pkt
;
325 Insn
*insn
= ctx
->insn
;
326 if (GET_ATTRIB(insn
->opcode
, A_CVI_NEW
) &&
327 insn
->new_value_producer_slot
== 1) {
328 /* Look for gather instruction */
329 for (int i
= 0; i
< pkt
->num_insns
; i
++) {
330 Insn
*in
= &pkt
->insn
[i
];
331 if (GET_ATTRIB(in
->opcode
, A_CVI_GATHER
) && in
->slot
== 1) {
340 * The LOG_*_WRITE macros mark most of the writes in a packet
341 * However, there are some implicit writes marked as attributes
342 * of the applicable instructions.
344 static void mark_implicit_reg_write(DisasContext
*ctx
, int attrib
, int rnum
)
346 uint16_t opcode
= ctx
->insn
->opcode
;
347 if (GET_ATTRIB(opcode
, attrib
)) {
349 * USR is used to set overflow and FP exceptions,
350 * so treat it as conditional
352 bool is_predicated
= GET_ATTRIB(opcode
, A_CONDEXEC
) ||
355 /* LC0/LC1 is conditionally written by endloop instructions */
356 if ((rnum
== HEX_REG_LC0
|| rnum
== HEX_REG_LC1
) &&
357 (opcode
== J2_endloop0
||
358 opcode
== J2_endloop1
||
359 opcode
== J2_endloop01
)) {
360 is_predicated
= true;
363 if (is_predicated
&& !is_preloaded(ctx
, rnum
)) {
364 tcg_gen_mov_tl(hex_new_value
[rnum
], hex_gpr
[rnum
]);
367 ctx_log_reg_write(ctx
, rnum
);
371 static void mark_implicit_pred_write(DisasContext
*ctx
, int attrib
, int pnum
)
373 if (GET_ATTRIB(ctx
->insn
->opcode
, attrib
)) {
374 ctx_log_pred_write(ctx
, pnum
);
378 static void mark_implicit_reg_writes(DisasContext
*ctx
)
380 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_FP
, HEX_REG_FP
);
381 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_SP
, HEX_REG_SP
);
382 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_LR
, HEX_REG_LR
);
383 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_LC0
, HEX_REG_LC0
);
384 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_SA0
, HEX_REG_SA0
);
385 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_LC1
, HEX_REG_LC1
);
386 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_SA1
, HEX_REG_SA1
);
387 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_USR
, HEX_REG_USR
);
388 mark_implicit_reg_write(ctx
, A_FPOP
, HEX_REG_USR
);
391 static void mark_implicit_pred_writes(DisasContext
*ctx
)
393 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P0
, 0);
394 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P1
, 1);
395 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P2
, 2);
396 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P3
, 3);
399 static void mark_store_width(DisasContext
*ctx
)
401 uint16_t opcode
= ctx
->insn
->opcode
;
402 uint32_t slot
= ctx
->insn
->slot
;
405 if (GET_ATTRIB(opcode
, A_SCALAR_STORE
)) {
406 if (GET_ATTRIB(opcode
, A_MEMSIZE_1B
)) {
409 if (GET_ATTRIB(opcode
, A_MEMSIZE_2B
)) {
412 if (GET_ATTRIB(opcode
, A_MEMSIZE_4B
)) {
415 if (GET_ATTRIB(opcode
, A_MEMSIZE_8B
)) {
418 tcg_debug_assert(is_power_of_2(width
));
419 ctx
->store_width
[slot
] = width
;
423 static void gen_insn(DisasContext
*ctx
)
425 if (ctx
->insn
->generate
) {
426 mark_implicit_reg_writes(ctx
);
427 ctx
->insn
->generate(ctx
);
428 mark_implicit_pred_writes(ctx
);
429 mark_store_width(ctx
);
431 gen_exception_end_tb(ctx
, HEX_EXCP_INVALID_OPCODE
);
436 * Helpers for generating the packet commit
438 static void gen_reg_writes(DisasContext
*ctx
)
442 for (i
= 0; i
< ctx
->reg_log_idx
; i
++) {
443 int reg_num
= ctx
->reg_log
[i
];
445 tcg_gen_mov_tl(hex_gpr
[reg_num
], hex_new_value
[reg_num
]);
448 * ctx->is_tight_loop is set when SA0 points to the beginning of the TB.
449 * If we write to SA0, we have to turn off tight loop handling.
451 if (reg_num
== HEX_REG_SA0
) {
452 ctx
->is_tight_loop
= false;
457 static void gen_pred_writes(DisasContext
*ctx
)
461 /* Early exit if the log is empty */
462 if (!ctx
->preg_log_idx
) {
467 * Only endloop instructions will conditionally
468 * write a predicate. If there are no endloop
469 * instructions, we can use the non-conditional
470 * write of the predicates.
472 if (ctx
->pkt
->pkt_has_endloop
) {
473 TCGv zero
= tcg_constant_tl(0);
474 TCGv pred_written
= tcg_temp_new();
475 for (i
= 0; i
< ctx
->preg_log_idx
; i
++) {
476 int pred_num
= ctx
->preg_log
[i
];
478 tcg_gen_andi_tl(pred_written
, hex_pred_written
, 1 << pred_num
);
479 tcg_gen_movcond_tl(TCG_COND_NE
, hex_pred
[pred_num
],
481 hex_new_pred_value
[pred_num
],
484 tcg_temp_free(pred_written
);
486 for (i
= 0; i
< ctx
->preg_log_idx
; i
++) {
487 int pred_num
= ctx
->preg_log
[i
];
488 tcg_gen_mov_tl(hex_pred
[pred_num
], hex_new_pred_value
[pred_num
]);
490 /* Do this so HELPER(debug_commit_end) will know */
491 tcg_gen_ori_tl(hex_pred_written
, hex_pred_written
,
498 static void gen_check_store_width(DisasContext
*ctx
, int slot_num
)
501 TCGv slot
= tcg_constant_tl(slot_num
);
502 TCGv check
= tcg_constant_tl(ctx
->store_width
[slot_num
]);
503 gen_helper_debug_check_store_width(cpu_env
, slot
, check
);
507 static bool slot_is_predicated(Packet
*pkt
, int slot_num
)
509 for (int i
= 0; i
< pkt
->num_insns
; i
++) {
510 if (pkt
->insn
[i
].slot
== slot_num
) {
511 return GET_ATTRIB(pkt
->insn
[i
].opcode
, A_CONDEXEC
);
514 /* If we get to here, we didn't find an instruction in the requested slot */
515 g_assert_not_reached();
518 void process_store(DisasContext
*ctx
, int slot_num
)
520 bool is_predicated
= slot_is_predicated(ctx
->pkt
, slot_num
);
521 TCGLabel
*label_end
= NULL
;
524 * We may have already processed this store
525 * See CHECK_NOSHUF in macros.h
527 if (slot_num
== 1 && ctx
->s1_store_processed
) {
530 ctx
->s1_store_processed
= true;
533 TCGv cancelled
= tcg_temp_new();
534 label_end
= gen_new_label();
536 /* Don't do anything if the slot was cancelled */
537 tcg_gen_extract_tl(cancelled
, hex_slot_cancelled
, slot_num
, 1);
538 tcg_gen_brcondi_tl(TCG_COND_NE
, cancelled
, 0, label_end
);
539 tcg_temp_free(cancelled
);
542 TCGv address
= tcg_temp_local_new();
543 tcg_gen_mov_tl(address
, hex_store_addr
[slot_num
]);
546 * If we know the width from the DisasContext, we can
547 * generate much cleaner code.
548 * Unfortunately, not all instructions execute the fSTORE
549 * macro during code generation. Anything that uses the
550 * generic helper will have this problem. Instructions
551 * that use fWRAP to generate proper TCG code will be OK.
553 switch (ctx
->store_width
[slot_num
]) {
555 gen_check_store_width(ctx
, slot_num
);
556 tcg_gen_qemu_st8(hex_store_val32
[slot_num
],
557 hex_store_addr
[slot_num
],
561 gen_check_store_width(ctx
, slot_num
);
562 tcg_gen_qemu_st16(hex_store_val32
[slot_num
],
563 hex_store_addr
[slot_num
],
567 gen_check_store_width(ctx
, slot_num
);
568 tcg_gen_qemu_st32(hex_store_val32
[slot_num
],
569 hex_store_addr
[slot_num
],
573 gen_check_store_width(ctx
, slot_num
);
574 tcg_gen_qemu_st64(hex_store_val64
[slot_num
],
575 hex_store_addr
[slot_num
],
581 * If we get to here, we don't know the width at
582 * TCG generation time, we'll use a helper to
583 * avoid branching based on the width at runtime.
585 TCGv slot
= tcg_constant_tl(slot_num
);
586 gen_helper_commit_store(cpu_env
, slot
);
589 tcg_temp_free(address
);
592 gen_set_label(label_end
);
596 static void process_store_log(DisasContext
*ctx
)
599 * When a packet has two stores, the hardware processes
600 * slot 1 and then slot 0. This will be important when
601 * the memory accesses overlap.
603 Packet
*pkt
= ctx
->pkt
;
604 if (pkt
->pkt_has_store_s1
) {
605 g_assert(!pkt
->pkt_has_dczeroa
);
606 process_store(ctx
, 1);
608 if (pkt
->pkt_has_store_s0
) {
609 g_assert(!pkt
->pkt_has_dczeroa
);
610 process_store(ctx
, 0);
614 /* Zero out a 32-bit cache line */
615 static void process_dczeroa(DisasContext
*ctx
)
617 if (ctx
->pkt
->pkt_has_dczeroa
) {
618 /* Store 32 bytes of zero starting at (addr & ~0x1f) */
619 TCGv addr
= tcg_temp_new();
620 TCGv_i64 zero
= tcg_constant_i64(0);
622 tcg_gen_andi_tl(addr
, hex_dczero_addr
, ~0x1f);
623 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
624 tcg_gen_addi_tl(addr
, addr
, 8);
625 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
626 tcg_gen_addi_tl(addr
, addr
, 8);
627 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
628 tcg_gen_addi_tl(addr
, addr
, 8);
629 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
635 static bool pkt_has_hvx_store(Packet
*pkt
)
638 for (i
= 0; i
< pkt
->num_insns
; i
++) {
639 int opcode
= pkt
->insn
[i
].opcode
;
640 if (GET_ATTRIB(opcode
, A_CVI
) && GET_ATTRIB(opcode
, A_STORE
)) {
647 static void gen_commit_hvx(DisasContext
*ctx
)
652 * for (i = 0; i < ctx->vreg_log_idx; i++) {
653 * int rnum = ctx->vreg_log[i];
654 * if (ctx->vreg_is_predicated[i]) {
655 * if (env->VRegs_updated & (1 << rnum)) {
656 * env->VRegs[rnum] = env->future_VRegs[rnum];
659 * env->VRegs[rnum] = env->future_VRegs[rnum];
663 for (i
= 0; i
< ctx
->vreg_log_idx
; i
++) {
664 int rnum
= ctx
->vreg_log
[i
];
665 bool is_predicated
= ctx
->vreg_is_predicated
[i
];
666 intptr_t dstoff
= offsetof(CPUHexagonState
, VRegs
[rnum
]);
667 intptr_t srcoff
= ctx_future_vreg_off(ctx
, rnum
, 1, false);
668 size_t size
= sizeof(MMVector
);
671 TCGv cmp
= tcg_temp_new();
672 TCGLabel
*label_skip
= gen_new_label();
674 tcg_gen_andi_tl(cmp
, hex_VRegs_updated
, 1 << rnum
);
675 tcg_gen_brcondi_tl(TCG_COND_EQ
, cmp
, 0, label_skip
);
677 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
678 gen_set_label(label_skip
);
680 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
685 * for (i = 0; i < ctx->qreg_log_idx; i++) {
686 * int rnum = ctx->qreg_log[i];
687 * if (ctx->qreg_is_predicated[i]) {
688 * if (env->QRegs_updated) & (1 << rnum)) {
689 * env->QRegs[rnum] = env->future_QRegs[rnum];
692 * env->QRegs[rnum] = env->future_QRegs[rnum];
696 for (i
= 0; i
< ctx
->qreg_log_idx
; i
++) {
697 int rnum
= ctx
->qreg_log
[i
];
698 bool is_predicated
= ctx
->qreg_is_predicated
[i
];
699 intptr_t dstoff
= offsetof(CPUHexagonState
, QRegs
[rnum
]);
700 intptr_t srcoff
= offsetof(CPUHexagonState
, future_QRegs
[rnum
]);
701 size_t size
= sizeof(MMQReg
);
704 TCGv cmp
= tcg_temp_new();
705 TCGLabel
*label_skip
= gen_new_label();
707 tcg_gen_andi_tl(cmp
, hex_QRegs_updated
, 1 << rnum
);
708 tcg_gen_brcondi_tl(TCG_COND_EQ
, cmp
, 0, label_skip
);
710 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
711 gen_set_label(label_skip
);
713 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
717 if (pkt_has_hvx_store(ctx
->pkt
)) {
718 gen_helper_commit_hvx_stores(cpu_env
);
722 static void update_exec_counters(DisasContext
*ctx
)
724 Packet
*pkt
= ctx
->pkt
;
725 int num_insns
= pkt
->num_insns
;
726 int num_real_insns
= 0;
727 int num_hvx_insns
= 0;
729 for (int i
= 0; i
< num_insns
; i
++) {
730 if (!pkt
->insn
[i
].is_endloop
&&
731 !pkt
->insn
[i
].part1
&&
732 !GET_ATTRIB(pkt
->insn
[i
].opcode
, A_IT_NOP
)) {
735 if (GET_ATTRIB(pkt
->insn
[i
].opcode
, A_CVI
)) {
741 ctx
->num_insns
+= num_real_insns
;
742 ctx
->num_hvx_insns
+= num_hvx_insns
;
745 static void gen_commit_packet(DisasContext
*ctx
)
748 * If there is more than one store in a packet, make sure they are all OK
749 * before proceeding with the rest of the packet commit.
751 * dczeroa has to be the only store operation in the packet, so we go
752 * ahead and process that first.
754 * When there is an HVX store, there can also be a scalar store in either
755 * slot 0 or slot1, so we create a mask for the helper to indicate what
758 * When there are two scalar stores, we probe the one in slot 0.
760 * Note that we don't call the probe helper for packets with only one
761 * store. Therefore, we call process_store_log before anything else
762 * involved in committing the packet.
764 Packet
*pkt
= ctx
->pkt
;
765 bool has_store_s0
= pkt
->pkt_has_store_s0
;
766 bool has_store_s1
= (pkt
->pkt_has_store_s1
&& !ctx
->s1_store_processed
);
767 bool has_hvx_store
= pkt_has_hvx_store(pkt
);
768 if (pkt
->pkt_has_dczeroa
) {
770 * The dczeroa will be the store in slot 0, check that we don't have
771 * a store in slot 1 or an HVX store.
773 g_assert(!has_store_s1
&& !has_hvx_store
);
774 process_dczeroa(ctx
);
775 } else if (has_hvx_store
) {
776 TCGv mem_idx
= tcg_constant_tl(ctx
->mem_idx
);
778 if (!has_store_s0
&& !has_store_s1
) {
779 gen_helper_probe_hvx_stores(cpu_env
, mem_idx
);
793 mask_tcgv
= tcg_constant_tl(mask
);
794 gen_helper_probe_pkt_scalar_hvx_stores(cpu_env
, mask_tcgv
, mem_idx
);
796 } else if (has_store_s0
&& has_store_s1
) {
798 * process_store_log will execute the slot 1 store first,
799 * so we only have to probe the store in slot 0
801 TCGv mem_idx
= tcg_constant_tl(ctx
->mem_idx
);
802 gen_helper_probe_pkt_scalar_store_s0(cpu_env
, mem_idx
);
805 process_store_log(ctx
);
808 gen_pred_writes(ctx
);
809 if (pkt
->pkt_has_hvx
) {
812 update_exec_counters(ctx
);
815 tcg_constant_tl(pkt
->pkt_has_store_s0
&& !pkt
->pkt_has_dczeroa
);
817 tcg_constant_tl(pkt
->pkt_has_store_s1
&& !pkt
->pkt_has_dczeroa
);
819 /* Handy place to set a breakpoint at the end of execution */
820 gen_helper_debug_commit_end(cpu_env
, has_st0
, has_st1
);
823 if (pkt
->vhist_insn
!= NULL
) {
824 ctx
->pre_commit
= false;
825 ctx
->insn
= pkt
->vhist_insn
;
826 pkt
->vhist_insn
->generate(ctx
);
829 if (pkt
->pkt_has_cof
) {
834 static void decode_and_translate_packet(CPUHexagonState
*env
, DisasContext
*ctx
)
836 uint32_t words
[PACKET_WORDS_MAX
];
841 nwords
= read_packet_words(env
, ctx
, words
);
843 gen_exception_end_tb(ctx
, HEX_EXCP_INVALID_PACKET
);
847 if (decode_packet(nwords
, words
, &pkt
, false) > 0) {
848 pkt
.pc
= ctx
->base
.pc_next
;
849 HEX_DEBUG_PRINT_PKT(&pkt
);
851 gen_start_packet(ctx
);
852 for (i
= 0; i
< pkt
.num_insns
; i
++) {
853 ctx
->insn
= &pkt
.insn
[i
];
856 gen_commit_packet(ctx
);
857 ctx
->base
.pc_next
+= pkt
.encod_pkt_size_in_bytes
;
859 gen_exception_end_tb(ctx
, HEX_EXCP_INVALID_PACKET
);
863 static void hexagon_tr_init_disas_context(DisasContextBase
*dcbase
,
866 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
867 uint32_t hex_flags
= dcbase
->tb
->flags
;
869 ctx
->mem_idx
= MMU_USER_IDX
;
870 ctx
->num_packets
= 0;
872 ctx
->num_hvx_insns
= 0;
873 ctx
->branch_cond
= TCG_COND_NEVER
;
874 ctx
->is_tight_loop
= FIELD_EX32(hex_flags
, TB_FLAGS
, IS_TIGHT_LOOP
);
877 static void hexagon_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
881 static void hexagon_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
883 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
885 tcg_gen_insn_start(ctx
->base
.pc_next
);
888 static bool pkt_crosses_page(CPUHexagonState
*env
, DisasContext
*ctx
)
890 target_ulong page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
891 bool found_end
= false;
894 for (nwords
= 0; !found_end
&& nwords
< PACKET_WORDS_MAX
; nwords
++) {
895 uint32_t word
= cpu_ldl_code(env
,
896 ctx
->base
.pc_next
+ nwords
* sizeof(uint32_t));
897 found_end
= is_packet_end(word
);
899 uint32_t next_ptr
= ctx
->base
.pc_next
+ nwords
* sizeof(uint32_t);
900 return found_end
&& next_ptr
- page_start
>= TARGET_PAGE_SIZE
;
903 static void hexagon_tr_translate_packet(DisasContextBase
*dcbase
, CPUState
*cpu
)
905 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
906 CPUHexagonState
*env
= cpu
->env_ptr
;
908 decode_and_translate_packet(env
, ctx
);
910 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
911 target_ulong page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
912 target_ulong bytes_max
= PACKET_WORDS_MAX
* sizeof(target_ulong
);
914 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
||
915 (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
- bytes_max
&&
916 pkt_crosses_page(env
, ctx
))) {
917 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
921 * The CPU log is used to compare against LLDB single stepping,
922 * so end the TLB after every packet.
924 HexagonCPU
*hex_cpu
= env_archcpu(env
);
925 if (hex_cpu
->lldb_compat
&& qemu_loglevel_mask(CPU_LOG_TB_CPU
)) {
926 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
931 static void hexagon_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
933 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
935 switch (ctx
->base
.is_jmp
) {
937 gen_exec_counters(ctx
);
938 tcg_gen_movi_tl(hex_gpr
[HEX_REG_PC
], ctx
->base
.pc_next
);
939 tcg_gen_exit_tb(NULL
, 0);
944 g_assert_not_reached();
948 static void hexagon_tr_disas_log(const DisasContextBase
*dcbase
,
949 CPUState
*cpu
, FILE *logfile
)
951 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
952 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
956 static const TranslatorOps hexagon_tr_ops
= {
957 .init_disas_context
= hexagon_tr_init_disas_context
,
958 .tb_start
= hexagon_tr_tb_start
,
959 .insn_start
= hexagon_tr_insn_start
,
960 .translate_insn
= hexagon_tr_translate_packet
,
961 .tb_stop
= hexagon_tr_tb_stop
,
962 .disas_log
= hexagon_tr_disas_log
,
965 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
966 target_ulong pc
, void *host_pc
)
970 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
,
971 &hexagon_tr_ops
, &ctx
.base
);
975 static char new_value_names
[TOTAL_PER_THREAD_REGS
][NAME_LEN
];
976 static char reg_written_names
[TOTAL_PER_THREAD_REGS
][NAME_LEN
];
977 static char new_pred_value_names
[NUM_PREGS
][NAME_LEN
];
978 static char store_addr_names
[STORES_MAX
][NAME_LEN
];
979 static char store_width_names
[STORES_MAX
][NAME_LEN
];
980 static char store_val32_names
[STORES_MAX
][NAME_LEN
];
981 static char store_val64_names
[STORES_MAX
][NAME_LEN
];
982 static char vstore_addr_names
[VSTORES_MAX
][NAME_LEN
];
983 static char vstore_size_names
[VSTORES_MAX
][NAME_LEN
];
984 static char vstore_pending_names
[VSTORES_MAX
][NAME_LEN
];
986 void hexagon_translate_init(void)
992 for (i
= 0; i
< TOTAL_PER_THREAD_REGS
; i
++) {
993 hex_gpr
[i
] = tcg_global_mem_new(cpu_env
,
994 offsetof(CPUHexagonState
, gpr
[i
]),
995 hexagon_regnames
[i
]);
997 snprintf(new_value_names
[i
], NAME_LEN
, "new_%s", hexagon_regnames
[i
]);
998 hex_new_value
[i
] = tcg_global_mem_new(cpu_env
,
999 offsetof(CPUHexagonState
, new_value
[i
]),
1000 new_value_names
[i
]);
1003 snprintf(reg_written_names
[i
], NAME_LEN
, "reg_written_%s",
1004 hexagon_regnames
[i
]);
1005 hex_reg_written
[i
] = tcg_global_mem_new(cpu_env
,
1006 offsetof(CPUHexagonState
, reg_written
[i
]),
1007 reg_written_names
[i
]);
1010 for (i
= 0; i
< NUM_PREGS
; i
++) {
1011 hex_pred
[i
] = tcg_global_mem_new(cpu_env
,
1012 offsetof(CPUHexagonState
, pred
[i
]),
1013 hexagon_prednames
[i
]);
1015 snprintf(new_pred_value_names
[i
], NAME_LEN
, "new_pred_%s",
1016 hexagon_prednames
[i
]);
1017 hex_new_pred_value
[i
] = tcg_global_mem_new(cpu_env
,
1018 offsetof(CPUHexagonState
, new_pred_value
[i
]),
1019 new_pred_value_names
[i
]);
1021 hex_pred_written
= tcg_global_mem_new(cpu_env
,
1022 offsetof(CPUHexagonState
, pred_written
), "pred_written");
1023 hex_this_PC
= tcg_global_mem_new(cpu_env
,
1024 offsetof(CPUHexagonState
, this_PC
), "this_PC");
1025 hex_slot_cancelled
= tcg_global_mem_new(cpu_env
,
1026 offsetof(CPUHexagonState
, slot_cancelled
), "slot_cancelled");
1027 hex_branch_taken
= tcg_global_mem_new(cpu_env
,
1028 offsetof(CPUHexagonState
, branch_taken
), "branch_taken");
1029 hex_pkt_has_store_s1
= tcg_global_mem_new(cpu_env
,
1030 offsetof(CPUHexagonState
, pkt_has_store_s1
), "pkt_has_store_s1");
1031 hex_dczero_addr
= tcg_global_mem_new(cpu_env
,
1032 offsetof(CPUHexagonState
, dczero_addr
), "dczero_addr");
1033 hex_llsc_addr
= tcg_global_mem_new(cpu_env
,
1034 offsetof(CPUHexagonState
, llsc_addr
), "llsc_addr");
1035 hex_llsc_val
= tcg_global_mem_new(cpu_env
,
1036 offsetof(CPUHexagonState
, llsc_val
), "llsc_val");
1037 hex_llsc_val_i64
= tcg_global_mem_new_i64(cpu_env
,
1038 offsetof(CPUHexagonState
, llsc_val_i64
), "llsc_val_i64");
1039 hex_VRegs_updated
= tcg_global_mem_new(cpu_env
,
1040 offsetof(CPUHexagonState
, VRegs_updated
), "VRegs_updated");
1041 hex_QRegs_updated
= tcg_global_mem_new(cpu_env
,
1042 offsetof(CPUHexagonState
, QRegs_updated
), "QRegs_updated");
1043 for (i
= 0; i
< STORES_MAX
; i
++) {
1044 snprintf(store_addr_names
[i
], NAME_LEN
, "store_addr_%d", i
);
1045 hex_store_addr
[i
] = tcg_global_mem_new(cpu_env
,
1046 offsetof(CPUHexagonState
, mem_log_stores
[i
].va
),
1047 store_addr_names
[i
]);
1049 snprintf(store_width_names
[i
], NAME_LEN
, "store_width_%d", i
);
1050 hex_store_width
[i
] = tcg_global_mem_new(cpu_env
,
1051 offsetof(CPUHexagonState
, mem_log_stores
[i
].width
),
1052 store_width_names
[i
]);
1054 snprintf(store_val32_names
[i
], NAME_LEN
, "store_val32_%d", i
);
1055 hex_store_val32
[i
] = tcg_global_mem_new(cpu_env
,
1056 offsetof(CPUHexagonState
, mem_log_stores
[i
].data32
),
1057 store_val32_names
[i
]);
1059 snprintf(store_val64_names
[i
], NAME_LEN
, "store_val64_%d", i
);
1060 hex_store_val64
[i
] = tcg_global_mem_new_i64(cpu_env
,
1061 offsetof(CPUHexagonState
, mem_log_stores
[i
].data64
),
1062 store_val64_names
[i
]);
1064 for (int i
= 0; i
< VSTORES_MAX
; i
++) {
1065 snprintf(vstore_addr_names
[i
], NAME_LEN
, "vstore_addr_%d", i
);
1066 hex_vstore_addr
[i
] = tcg_global_mem_new(cpu_env
,
1067 offsetof(CPUHexagonState
, vstore
[i
].va
),
1068 vstore_addr_names
[i
]);
1070 snprintf(vstore_size_names
[i
], NAME_LEN
, "vstore_size_%d", i
);
1071 hex_vstore_size
[i
] = tcg_global_mem_new(cpu_env
,
1072 offsetof(CPUHexagonState
, vstore
[i
].size
),
1073 vstore_size_names
[i
]);
1075 snprintf(vstore_pending_names
[i
], NAME_LEN
, "vstore_pending_%d", i
);
1076 hex_vstore_pending
[i
] = tcg_global_mem_new(cpu_env
,
1077 offsetof(CPUHexagonState
, vstore_pending
[i
]),
1078 vstore_pending_names
[i
]);