2 * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
21 #include "tcg/tcg-op.h"
22 #include "tcg/tcg-op-gvec.h"
23 #include "exec/cpu_ldst.h"
29 #include "translate.h"
30 #include "printinsn.h"
32 TCGv hex_gpr
[TOTAL_PER_THREAD_REGS
];
33 TCGv hex_pred
[NUM_PREGS
];
36 TCGv hex_slot_cancelled
;
37 TCGv hex_branch_taken
;
38 TCGv hex_new_value
[TOTAL_PER_THREAD_REGS
];
39 TCGv hex_reg_written
[TOTAL_PER_THREAD_REGS
];
40 TCGv hex_new_pred_value
[NUM_PREGS
];
41 TCGv hex_pred_written
;
42 TCGv hex_store_addr
[STORES_MAX
];
43 TCGv hex_store_width
[STORES_MAX
];
44 TCGv hex_store_val32
[STORES_MAX
];
45 TCGv_i64 hex_store_val64
[STORES_MAX
];
46 TCGv hex_pkt_has_store_s1
;
50 TCGv_i64 hex_llsc_val_i64
;
51 TCGv hex_VRegs_updated
;
52 TCGv hex_QRegs_updated
;
53 TCGv hex_vstore_addr
[VSTORES_MAX
];
54 TCGv hex_vstore_size
[VSTORES_MAX
];
55 TCGv hex_vstore_pending
[VSTORES_MAX
];
57 static const char * const hexagon_prednames
[] = {
58 "p0", "p1", "p2", "p3"
61 intptr_t ctx_future_vreg_off(DisasContext
*ctx
, int regnum
,
62 int num
, bool alloc_ok
)
66 /* See if it is already allocated */
67 for (int i
= 0; i
< ctx
->future_vregs_idx
; i
++) {
68 if (ctx
->future_vregs_num
[i
] == regnum
) {
69 return offsetof(CPUHexagonState
, future_VRegs
[i
]);
74 offset
= offsetof(CPUHexagonState
, future_VRegs
[ctx
->future_vregs_idx
]);
75 for (int i
= 0; i
< num
; i
++) {
76 ctx
->future_vregs_num
[ctx
->future_vregs_idx
+ i
] = regnum
++;
78 ctx
->future_vregs_idx
+= num
;
79 g_assert(ctx
->future_vregs_idx
<= VECTOR_TEMPS_MAX
);
83 intptr_t ctx_tmp_vreg_off(DisasContext
*ctx
, int regnum
,
84 int num
, bool alloc_ok
)
88 /* See if it is already allocated */
89 for (int i
= 0; i
< ctx
->tmp_vregs_idx
; i
++) {
90 if (ctx
->tmp_vregs_num
[i
] == regnum
) {
91 return offsetof(CPUHexagonState
, tmp_VRegs
[i
]);
96 offset
= offsetof(CPUHexagonState
, tmp_VRegs
[ctx
->tmp_vregs_idx
]);
97 for (int i
= 0; i
< num
; i
++) {
98 ctx
->tmp_vregs_num
[ctx
->tmp_vregs_idx
+ i
] = regnum
++;
100 ctx
->tmp_vregs_idx
+= num
;
101 g_assert(ctx
->tmp_vregs_idx
<= VECTOR_TEMPS_MAX
);
105 static void gen_exception_raw(int excp
)
107 gen_helper_raise_exception(cpu_env
, tcg_constant_i32(excp
));
110 static void gen_exec_counters(DisasContext
*ctx
)
112 tcg_gen_addi_tl(hex_gpr
[HEX_REG_QEMU_PKT_CNT
],
113 hex_gpr
[HEX_REG_QEMU_PKT_CNT
], ctx
->num_packets
);
114 tcg_gen_addi_tl(hex_gpr
[HEX_REG_QEMU_INSN_CNT
],
115 hex_gpr
[HEX_REG_QEMU_INSN_CNT
], ctx
->num_insns
);
116 tcg_gen_addi_tl(hex_gpr
[HEX_REG_QEMU_HVX_CNT
],
117 hex_gpr
[HEX_REG_QEMU_HVX_CNT
], ctx
->num_hvx_insns
);
120 static void gen_end_tb(DisasContext
*ctx
)
122 gen_exec_counters(ctx
);
123 tcg_gen_mov_tl(hex_gpr
[HEX_REG_PC
], hex_next_PC
);
124 tcg_gen_exit_tb(NULL
, 0);
125 ctx
->base
.is_jmp
= DISAS_NORETURN
;
128 static void gen_exception_end_tb(DisasContext
*ctx
, int excp
)
130 gen_exec_counters(ctx
);
131 tcg_gen_mov_tl(hex_gpr
[HEX_REG_PC
], hex_next_PC
);
132 gen_exception_raw(excp
);
133 ctx
->base
.is_jmp
= DISAS_NORETURN
;
137 #define PACKET_BUFFER_LEN 1028
138 static void print_pkt(Packet
*pkt
)
140 GString
*buf
= g_string_sized_new(PACKET_BUFFER_LEN
);
141 snprint_a_pkt_debug(buf
, pkt
);
142 HEX_DEBUG_LOG("%s", buf
->str
);
143 g_string_free(buf
, true);
145 #define HEX_DEBUG_PRINT_PKT(pkt) \
152 static int read_packet_words(CPUHexagonState
*env
, DisasContext
*ctx
,
155 bool found_end
= false;
156 int nwords
, max_words
;
158 memset(words
, 0, PACKET_WORDS_MAX
* sizeof(uint32_t));
159 for (nwords
= 0; !found_end
&& nwords
< PACKET_WORDS_MAX
; nwords
++) {
161 translator_ldl(env
, &ctx
->base
,
162 ctx
->base
.pc_next
+ nwords
* sizeof(uint32_t));
163 found_end
= is_packet_end(words
[nwords
]);
166 /* Read too many words without finding the end */
170 /* Check for page boundary crossing */
171 max_words
= -(ctx
->base
.pc_next
| TARGET_PAGE_MASK
) / sizeof(uint32_t);
172 if (nwords
> max_words
) {
173 /* We can only cross a page boundary at the beginning of a TB */
174 g_assert(ctx
->base
.num_insns
== 1);
177 HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx
->base
.pc_next
);
178 HEX_DEBUG_LOG(" words = { ");
179 for (int i
= 0; i
< nwords
; i
++) {
180 HEX_DEBUG_LOG("0x%x, ", words
[i
]);
182 HEX_DEBUG_LOG("}\n");
187 static bool check_for_attrib(Packet
*pkt
, int attrib
)
189 for (int i
= 0; i
< pkt
->num_insns
; i
++) {
190 if (GET_ATTRIB(pkt
->insn
[i
].opcode
, attrib
)) {
197 static bool need_slot_cancelled(Packet
*pkt
)
199 return check_for_attrib(pkt
, A_CONDEXEC
);
202 static bool need_pred_written(Packet
*pkt
)
204 return check_for_attrib(pkt
, A_WRITES_PRED_REG
);
207 static void gen_start_packet(DisasContext
*ctx
)
209 Packet
*pkt
= ctx
->pkt
;
210 target_ulong next_PC
= ctx
->base
.pc_next
+ pkt
->encod_pkt_size_in_bytes
;
213 /* Clear out the disassembly context */
214 ctx
->reg_log_idx
= 0;
215 bitmap_zero(ctx
->regs_written
, TOTAL_PER_THREAD_REGS
);
216 ctx
->preg_log_idx
= 0;
217 bitmap_zero(ctx
->pregs_written
, NUM_PREGS
);
218 ctx
->future_vregs_idx
= 0;
219 ctx
->tmp_vregs_idx
= 0;
220 ctx
->vreg_log_idx
= 0;
221 bitmap_zero(ctx
->vregs_updated_tmp
, NUM_VREGS
);
222 bitmap_zero(ctx
->vregs_updated
, NUM_VREGS
);
223 bitmap_zero(ctx
->vregs_select
, NUM_VREGS
);
224 ctx
->qreg_log_idx
= 0;
225 for (i
= 0; i
< STORES_MAX
; i
++) {
226 ctx
->store_width
[i
] = 0;
228 tcg_gen_movi_tl(hex_pkt_has_store_s1
, pkt
->pkt_has_store_s1
);
229 ctx
->s1_store_processed
= false;
230 ctx
->pre_commit
= true;
233 /* Handy place to set a breakpoint before the packet executes */
234 gen_helper_debug_start_packet(cpu_env
);
235 tcg_gen_movi_tl(hex_this_PC
, ctx
->base
.pc_next
);
238 /* Initialize the runtime state for packet semantics */
239 if (need_slot_cancelled(pkt
)) {
240 tcg_gen_movi_tl(hex_slot_cancelled
, 0);
242 if (pkt
->pkt_has_cof
) {
243 if (pkt
->pkt_has_multi_cof
) {
244 tcg_gen_movi_tl(hex_branch_taken
, 0);
246 tcg_gen_movi_tl(hex_next_PC
, next_PC
);
248 if (need_pred_written(pkt
)) {
249 tcg_gen_movi_tl(hex_pred_written
, 0);
252 if (pkt
->pkt_has_hvx
) {
253 tcg_gen_movi_tl(hex_VRegs_updated
, 0);
254 tcg_gen_movi_tl(hex_QRegs_updated
, 0);
258 bool is_gather_store_insn(DisasContext
*ctx
)
260 Packet
*pkt
= ctx
->pkt
;
261 Insn
*insn
= ctx
->insn
;
262 if (GET_ATTRIB(insn
->opcode
, A_CVI_NEW
) &&
263 insn
->new_value_producer_slot
== 1) {
264 /* Look for gather instruction */
265 for (int i
= 0; i
< pkt
->num_insns
; i
++) {
266 Insn
*in
= &pkt
->insn
[i
];
267 if (GET_ATTRIB(in
->opcode
, A_CVI_GATHER
) && in
->slot
== 1) {
276 * The LOG_*_WRITE macros mark most of the writes in a packet
277 * However, there are some implicit writes marked as attributes
278 * of the applicable instructions.
280 static void mark_implicit_reg_write(DisasContext
*ctx
, int attrib
, int rnum
)
282 uint16_t opcode
= ctx
->insn
->opcode
;
283 if (GET_ATTRIB(opcode
, attrib
)) {
285 * USR is used to set overflow and FP exceptions,
286 * so treat it as conditional
288 bool is_predicated
= GET_ATTRIB(opcode
, A_CONDEXEC
) ||
290 if (is_predicated
&& !is_preloaded(ctx
, rnum
)) {
291 tcg_gen_mov_tl(hex_new_value
[rnum
], hex_gpr
[rnum
]);
294 ctx_log_reg_write(ctx
, rnum
);
298 static void mark_implicit_pred_write(DisasContext
*ctx
, int attrib
, int pnum
)
300 if (GET_ATTRIB(ctx
->insn
->opcode
, attrib
)) {
301 ctx_log_pred_write(ctx
, pnum
);
305 static void mark_implicit_reg_writes(DisasContext
*ctx
)
307 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_FP
, HEX_REG_FP
);
308 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_SP
, HEX_REG_SP
);
309 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_LR
, HEX_REG_LR
);
310 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_LC0
, HEX_REG_LC0
);
311 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_SA0
, HEX_REG_SA0
);
312 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_LC1
, HEX_REG_LC1
);
313 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_SA1
, HEX_REG_SA1
);
314 mark_implicit_reg_write(ctx
, A_IMPLICIT_WRITES_USR
, HEX_REG_USR
);
315 mark_implicit_reg_write(ctx
, A_FPOP
, HEX_REG_USR
);
318 static void mark_implicit_pred_writes(DisasContext
*ctx
)
320 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P0
, 0);
321 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P1
, 1);
322 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P2
, 2);
323 mark_implicit_pred_write(ctx
, A_IMPLICIT_WRITES_P3
, 3);
326 static void mark_store_width(DisasContext
*ctx
)
328 uint16_t opcode
= ctx
->insn
->opcode
;
329 uint32_t slot
= ctx
->insn
->slot
;
332 if (GET_ATTRIB(opcode
, A_SCALAR_STORE
)) {
333 if (GET_ATTRIB(opcode
, A_MEMSIZE_1B
)) {
336 if (GET_ATTRIB(opcode
, A_MEMSIZE_2B
)) {
339 if (GET_ATTRIB(opcode
, A_MEMSIZE_4B
)) {
342 if (GET_ATTRIB(opcode
, A_MEMSIZE_8B
)) {
345 tcg_debug_assert(is_power_of_2(width
));
346 ctx
->store_width
[slot
] = width
;
350 static void gen_insn(DisasContext
*ctx
)
352 if (ctx
->insn
->generate
) {
353 mark_implicit_reg_writes(ctx
);
354 ctx
->insn
->generate(ctx
);
355 mark_implicit_pred_writes(ctx
);
356 mark_store_width(ctx
);
358 gen_exception_end_tb(ctx
, HEX_EXCP_INVALID_OPCODE
);
363 * Helpers for generating the packet commit
365 static void gen_reg_writes(DisasContext
*ctx
)
369 for (i
= 0; i
< ctx
->reg_log_idx
; i
++) {
370 int reg_num
= ctx
->reg_log
[i
];
372 tcg_gen_mov_tl(hex_gpr
[reg_num
], hex_new_value
[reg_num
]);
376 static void gen_pred_writes(DisasContext
*ctx
)
380 /* Early exit if the log is empty */
381 if (!ctx
->preg_log_idx
) {
386 * Only endloop instructions will conditionally
387 * write a predicate. If there are no endloop
388 * instructions, we can use the non-conditional
389 * write of the predicates.
391 if (ctx
->pkt
->pkt_has_endloop
) {
392 TCGv zero
= tcg_constant_tl(0);
393 TCGv pred_written
= tcg_temp_new();
394 for (i
= 0; i
< ctx
->preg_log_idx
; i
++) {
395 int pred_num
= ctx
->preg_log
[i
];
397 tcg_gen_andi_tl(pred_written
, hex_pred_written
, 1 << pred_num
);
398 tcg_gen_movcond_tl(TCG_COND_NE
, hex_pred
[pred_num
],
400 hex_new_pred_value
[pred_num
],
403 tcg_temp_free(pred_written
);
405 for (i
= 0; i
< ctx
->preg_log_idx
; i
++) {
406 int pred_num
= ctx
->preg_log
[i
];
407 tcg_gen_mov_tl(hex_pred
[pred_num
], hex_new_pred_value
[pred_num
]);
409 /* Do this so HELPER(debug_commit_end) will know */
410 tcg_gen_ori_tl(hex_pred_written
, hex_pred_written
,
417 static void gen_check_store_width(DisasContext
*ctx
, int slot_num
)
420 TCGv slot
= tcg_constant_tl(slot_num
);
421 TCGv check
= tcg_constant_tl(ctx
->store_width
[slot_num
]);
422 gen_helper_debug_check_store_width(cpu_env
, slot
, check
);
426 static bool slot_is_predicated(Packet
*pkt
, int slot_num
)
428 for (int i
= 0; i
< pkt
->num_insns
; i
++) {
429 if (pkt
->insn
[i
].slot
== slot_num
) {
430 return GET_ATTRIB(pkt
->insn
[i
].opcode
, A_CONDEXEC
);
433 /* If we get to here, we didn't find an instruction in the requested slot */
434 g_assert_not_reached();
437 void process_store(DisasContext
*ctx
, int slot_num
)
439 bool is_predicated
= slot_is_predicated(ctx
->pkt
, slot_num
);
440 TCGLabel
*label_end
= NULL
;
443 * We may have already processed this store
444 * See CHECK_NOSHUF in macros.h
446 if (slot_num
== 1 && ctx
->s1_store_processed
) {
449 ctx
->s1_store_processed
= true;
452 TCGv cancelled
= tcg_temp_new();
453 label_end
= gen_new_label();
455 /* Don't do anything if the slot was cancelled */
456 tcg_gen_extract_tl(cancelled
, hex_slot_cancelled
, slot_num
, 1);
457 tcg_gen_brcondi_tl(TCG_COND_NE
, cancelled
, 0, label_end
);
458 tcg_temp_free(cancelled
);
461 TCGv address
= tcg_temp_local_new();
462 tcg_gen_mov_tl(address
, hex_store_addr
[slot_num
]);
465 * If we know the width from the DisasContext, we can
466 * generate much cleaner code.
467 * Unfortunately, not all instructions execute the fSTORE
468 * macro during code generation. Anything that uses the
469 * generic helper will have this problem. Instructions
470 * that use fWRAP to generate proper TCG code will be OK.
472 switch (ctx
->store_width
[slot_num
]) {
474 gen_check_store_width(ctx
, slot_num
);
475 tcg_gen_qemu_st8(hex_store_val32
[slot_num
],
476 hex_store_addr
[slot_num
],
480 gen_check_store_width(ctx
, slot_num
);
481 tcg_gen_qemu_st16(hex_store_val32
[slot_num
],
482 hex_store_addr
[slot_num
],
486 gen_check_store_width(ctx
, slot_num
);
487 tcg_gen_qemu_st32(hex_store_val32
[slot_num
],
488 hex_store_addr
[slot_num
],
492 gen_check_store_width(ctx
, slot_num
);
493 tcg_gen_qemu_st64(hex_store_val64
[slot_num
],
494 hex_store_addr
[slot_num
],
500 * If we get to here, we don't know the width at
501 * TCG generation time, we'll use a helper to
502 * avoid branching based on the width at runtime.
504 TCGv slot
= tcg_constant_tl(slot_num
);
505 gen_helper_commit_store(cpu_env
, slot
);
508 tcg_temp_free(address
);
511 gen_set_label(label_end
);
515 static void process_store_log(DisasContext
*ctx
)
518 * When a packet has two stores, the hardware processes
519 * slot 1 and then slot 0. This will be important when
520 * the memory accesses overlap.
522 Packet
*pkt
= ctx
->pkt
;
523 if (pkt
->pkt_has_store_s1
) {
524 g_assert(!pkt
->pkt_has_dczeroa
);
525 process_store(ctx
, 1);
527 if (pkt
->pkt_has_store_s0
) {
528 g_assert(!pkt
->pkt_has_dczeroa
);
529 process_store(ctx
, 0);
533 /* Zero out a 32-bit cache line */
534 static void process_dczeroa(DisasContext
*ctx
)
536 if (ctx
->pkt
->pkt_has_dczeroa
) {
537 /* Store 32 bytes of zero starting at (addr & ~0x1f) */
538 TCGv addr
= tcg_temp_new();
539 TCGv_i64 zero
= tcg_constant_i64(0);
541 tcg_gen_andi_tl(addr
, hex_dczero_addr
, ~0x1f);
542 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
543 tcg_gen_addi_tl(addr
, addr
, 8);
544 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
545 tcg_gen_addi_tl(addr
, addr
, 8);
546 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
547 tcg_gen_addi_tl(addr
, addr
, 8);
548 tcg_gen_qemu_st64(zero
, addr
, ctx
->mem_idx
);
554 static bool pkt_has_hvx_store(Packet
*pkt
)
557 for (i
= 0; i
< pkt
->num_insns
; i
++) {
558 int opcode
= pkt
->insn
[i
].opcode
;
559 if (GET_ATTRIB(opcode
, A_CVI
) && GET_ATTRIB(opcode
, A_STORE
)) {
566 static void gen_commit_hvx(DisasContext
*ctx
)
571 * for (i = 0; i < ctx->vreg_log_idx; i++) {
572 * int rnum = ctx->vreg_log[i];
573 * if (ctx->vreg_is_predicated[i]) {
574 * if (env->VRegs_updated & (1 << rnum)) {
575 * env->VRegs[rnum] = env->future_VRegs[rnum];
578 * env->VRegs[rnum] = env->future_VRegs[rnum];
582 for (i
= 0; i
< ctx
->vreg_log_idx
; i
++) {
583 int rnum
= ctx
->vreg_log
[i
];
584 bool is_predicated
= ctx
->vreg_is_predicated
[i
];
585 intptr_t dstoff
= offsetof(CPUHexagonState
, VRegs
[rnum
]);
586 intptr_t srcoff
= ctx_future_vreg_off(ctx
, rnum
, 1, false);
587 size_t size
= sizeof(MMVector
);
590 TCGv cmp
= tcg_temp_new();
591 TCGLabel
*label_skip
= gen_new_label();
593 tcg_gen_andi_tl(cmp
, hex_VRegs_updated
, 1 << rnum
);
594 tcg_gen_brcondi_tl(TCG_COND_EQ
, cmp
, 0, label_skip
);
596 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
597 gen_set_label(label_skip
);
599 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
604 * for (i = 0; i < ctx->qreg_log_idx; i++) {
605 * int rnum = ctx->qreg_log[i];
606 * if (ctx->qreg_is_predicated[i]) {
607 * if (env->QRegs_updated) & (1 << rnum)) {
608 * env->QRegs[rnum] = env->future_QRegs[rnum];
611 * env->QRegs[rnum] = env->future_QRegs[rnum];
615 for (i
= 0; i
< ctx
->qreg_log_idx
; i
++) {
616 int rnum
= ctx
->qreg_log
[i
];
617 bool is_predicated
= ctx
->qreg_is_predicated
[i
];
618 intptr_t dstoff
= offsetof(CPUHexagonState
, QRegs
[rnum
]);
619 intptr_t srcoff
= offsetof(CPUHexagonState
, future_QRegs
[rnum
]);
620 size_t size
= sizeof(MMQReg
);
623 TCGv cmp
= tcg_temp_new();
624 TCGLabel
*label_skip
= gen_new_label();
626 tcg_gen_andi_tl(cmp
, hex_QRegs_updated
, 1 << rnum
);
627 tcg_gen_brcondi_tl(TCG_COND_EQ
, cmp
, 0, label_skip
);
629 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
630 gen_set_label(label_skip
);
632 tcg_gen_gvec_mov(MO_64
, dstoff
, srcoff
, size
, size
);
636 if (pkt_has_hvx_store(ctx
->pkt
)) {
637 gen_helper_commit_hvx_stores(cpu_env
);
641 static void update_exec_counters(DisasContext
*ctx
)
643 Packet
*pkt
= ctx
->pkt
;
644 int num_insns
= pkt
->num_insns
;
645 int num_real_insns
= 0;
646 int num_hvx_insns
= 0;
648 for (int i
= 0; i
< num_insns
; i
++) {
649 if (!pkt
->insn
[i
].is_endloop
&&
650 !pkt
->insn
[i
].part1
&&
651 !GET_ATTRIB(pkt
->insn
[i
].opcode
, A_IT_NOP
)) {
654 if (GET_ATTRIB(pkt
->insn
[i
].opcode
, A_CVI
)) {
660 ctx
->num_insns
+= num_real_insns
;
661 ctx
->num_hvx_insns
+= num_hvx_insns
;
664 static void gen_commit_packet(DisasContext
*ctx
)
667 * If there is more than one store in a packet, make sure they are all OK
668 * before proceeding with the rest of the packet commit.
670 * dczeroa has to be the only store operation in the packet, so we go
671 * ahead and process that first.
673 * When there is an HVX store, there can also be a scalar store in either
674 * slot 0 or slot1, so we create a mask for the helper to indicate what
677 * When there are two scalar stores, we probe the one in slot 0.
679 * Note that we don't call the probe helper for packets with only one
680 * store. Therefore, we call process_store_log before anything else
681 * involved in committing the packet.
683 Packet
*pkt
= ctx
->pkt
;
684 bool has_store_s0
= pkt
->pkt_has_store_s0
;
685 bool has_store_s1
= (pkt
->pkt_has_store_s1
&& !ctx
->s1_store_processed
);
686 bool has_hvx_store
= pkt_has_hvx_store(pkt
);
687 if (pkt
->pkt_has_dczeroa
) {
689 * The dczeroa will be the store in slot 0, check that we don't have
690 * a store in slot 1 or an HVX store.
692 g_assert(!has_store_s1
&& !has_hvx_store
);
693 process_dczeroa(ctx
);
694 } else if (has_hvx_store
) {
695 TCGv mem_idx
= tcg_constant_tl(ctx
->mem_idx
);
697 if (!has_store_s0
&& !has_store_s1
) {
698 gen_helper_probe_hvx_stores(cpu_env
, mem_idx
);
712 mask_tcgv
= tcg_constant_tl(mask
);
713 gen_helper_probe_pkt_scalar_hvx_stores(cpu_env
, mask_tcgv
, mem_idx
);
715 } else if (has_store_s0
&& has_store_s1
) {
717 * process_store_log will execute the slot 1 store first,
718 * so we only have to probe the store in slot 0
720 TCGv mem_idx
= tcg_constant_tl(ctx
->mem_idx
);
721 gen_helper_probe_pkt_scalar_store_s0(cpu_env
, mem_idx
);
724 process_store_log(ctx
);
727 gen_pred_writes(ctx
);
728 if (pkt
->pkt_has_hvx
) {
731 update_exec_counters(ctx
);
734 tcg_constant_tl(pkt
->pkt_has_store_s0
&& !pkt
->pkt_has_dczeroa
);
736 tcg_constant_tl(pkt
->pkt_has_store_s1
&& !pkt
->pkt_has_dczeroa
);
738 /* Handy place to set a breakpoint at the end of execution */
739 gen_helper_debug_commit_end(cpu_env
, has_st0
, has_st1
);
742 if (pkt
->vhist_insn
!= NULL
) {
743 ctx
->pre_commit
= false;
744 ctx
->insn
= pkt
->vhist_insn
;
745 pkt
->vhist_insn
->generate(ctx
);
748 if (pkt
->pkt_has_cof
) {
753 static void decode_and_translate_packet(CPUHexagonState
*env
, DisasContext
*ctx
)
755 uint32_t words
[PACKET_WORDS_MAX
];
760 nwords
= read_packet_words(env
, ctx
, words
);
762 gen_exception_end_tb(ctx
, HEX_EXCP_INVALID_PACKET
);
766 if (decode_packet(nwords
, words
, &pkt
, false) > 0) {
767 pkt
.pc
= ctx
->base
.pc_next
;
768 HEX_DEBUG_PRINT_PKT(&pkt
);
770 gen_start_packet(ctx
);
771 for (i
= 0; i
< pkt
.num_insns
; i
++) {
772 ctx
->insn
= &pkt
.insn
[i
];
775 gen_commit_packet(ctx
);
776 ctx
->base
.pc_next
+= pkt
.encod_pkt_size_in_bytes
;
778 gen_exception_end_tb(ctx
, HEX_EXCP_INVALID_PACKET
);
782 static void hexagon_tr_init_disas_context(DisasContextBase
*dcbase
,
785 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
787 ctx
->mem_idx
= MMU_USER_IDX
;
788 ctx
->num_packets
= 0;
790 ctx
->num_hvx_insns
= 0;
793 static void hexagon_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
797 static void hexagon_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
799 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
801 tcg_gen_insn_start(ctx
->base
.pc_next
);
804 static bool pkt_crosses_page(CPUHexagonState
*env
, DisasContext
*ctx
)
806 target_ulong page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
807 bool found_end
= false;
810 for (nwords
= 0; !found_end
&& nwords
< PACKET_WORDS_MAX
; nwords
++) {
811 uint32_t word
= cpu_ldl_code(env
,
812 ctx
->base
.pc_next
+ nwords
* sizeof(uint32_t));
813 found_end
= is_packet_end(word
);
815 uint32_t next_ptr
= ctx
->base
.pc_next
+ nwords
* sizeof(uint32_t);
816 return found_end
&& next_ptr
- page_start
>= TARGET_PAGE_SIZE
;
819 static void hexagon_tr_translate_packet(DisasContextBase
*dcbase
, CPUState
*cpu
)
821 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
822 CPUHexagonState
*env
= cpu
->env_ptr
;
824 decode_and_translate_packet(env
, ctx
);
826 if (ctx
->base
.is_jmp
== DISAS_NEXT
) {
827 target_ulong page_start
= ctx
->base
.pc_first
& TARGET_PAGE_MASK
;
828 target_ulong bytes_max
= PACKET_WORDS_MAX
* sizeof(target_ulong
);
830 if (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
||
831 (ctx
->base
.pc_next
- page_start
>= TARGET_PAGE_SIZE
- bytes_max
&&
832 pkt_crosses_page(env
, ctx
))) {
833 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
837 * The CPU log is used to compare against LLDB single stepping,
838 * so end the TLB after every packet.
840 HexagonCPU
*hex_cpu
= env_archcpu(env
);
841 if (hex_cpu
->lldb_compat
&& qemu_loglevel_mask(CPU_LOG_TB_CPU
)) {
842 ctx
->base
.is_jmp
= DISAS_TOO_MANY
;
847 static void hexagon_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
849 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
851 switch (ctx
->base
.is_jmp
) {
853 gen_exec_counters(ctx
);
854 tcg_gen_movi_tl(hex_gpr
[HEX_REG_PC
], ctx
->base
.pc_next
);
855 tcg_gen_exit_tb(NULL
, 0);
860 g_assert_not_reached();
864 static void hexagon_tr_disas_log(const DisasContextBase
*dcbase
,
865 CPUState
*cpu
, FILE *logfile
)
867 fprintf(logfile
, "IN: %s\n", lookup_symbol(dcbase
->pc_first
));
868 target_disas(logfile
, cpu
, dcbase
->pc_first
, dcbase
->tb
->size
);
872 static const TranslatorOps hexagon_tr_ops
= {
873 .init_disas_context
= hexagon_tr_init_disas_context
,
874 .tb_start
= hexagon_tr_tb_start
,
875 .insn_start
= hexagon_tr_insn_start
,
876 .translate_insn
= hexagon_tr_translate_packet
,
877 .tb_stop
= hexagon_tr_tb_stop
,
878 .disas_log
= hexagon_tr_disas_log
,
881 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
,
882 target_ulong pc
, void *host_pc
)
886 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
,
887 &hexagon_tr_ops
, &ctx
.base
);
891 static char new_value_names
[TOTAL_PER_THREAD_REGS
][NAME_LEN
];
892 static char reg_written_names
[TOTAL_PER_THREAD_REGS
][NAME_LEN
];
893 static char new_pred_value_names
[NUM_PREGS
][NAME_LEN
];
894 static char store_addr_names
[STORES_MAX
][NAME_LEN
];
895 static char store_width_names
[STORES_MAX
][NAME_LEN
];
896 static char store_val32_names
[STORES_MAX
][NAME_LEN
];
897 static char store_val64_names
[STORES_MAX
][NAME_LEN
];
898 static char vstore_addr_names
[VSTORES_MAX
][NAME_LEN
];
899 static char vstore_size_names
[VSTORES_MAX
][NAME_LEN
];
900 static char vstore_pending_names
[VSTORES_MAX
][NAME_LEN
];
902 void hexagon_translate_init(void)
908 for (i
= 0; i
< TOTAL_PER_THREAD_REGS
; i
++) {
909 hex_gpr
[i
] = tcg_global_mem_new(cpu_env
,
910 offsetof(CPUHexagonState
, gpr
[i
]),
911 hexagon_regnames
[i
]);
913 snprintf(new_value_names
[i
], NAME_LEN
, "new_%s", hexagon_regnames
[i
]);
914 hex_new_value
[i
] = tcg_global_mem_new(cpu_env
,
915 offsetof(CPUHexagonState
, new_value
[i
]),
919 snprintf(reg_written_names
[i
], NAME_LEN
, "reg_written_%s",
920 hexagon_regnames
[i
]);
921 hex_reg_written
[i
] = tcg_global_mem_new(cpu_env
,
922 offsetof(CPUHexagonState
, reg_written
[i
]),
923 reg_written_names
[i
]);
926 for (i
= 0; i
< NUM_PREGS
; i
++) {
927 hex_pred
[i
] = tcg_global_mem_new(cpu_env
,
928 offsetof(CPUHexagonState
, pred
[i
]),
929 hexagon_prednames
[i
]);
931 snprintf(new_pred_value_names
[i
], NAME_LEN
, "new_pred_%s",
932 hexagon_prednames
[i
]);
933 hex_new_pred_value
[i
] = tcg_global_mem_new(cpu_env
,
934 offsetof(CPUHexagonState
, new_pred_value
[i
]),
935 new_pred_value_names
[i
]);
937 hex_pred_written
= tcg_global_mem_new(cpu_env
,
938 offsetof(CPUHexagonState
, pred_written
), "pred_written");
939 hex_next_PC
= tcg_global_mem_new(cpu_env
,
940 offsetof(CPUHexagonState
, next_PC
), "next_PC");
941 hex_this_PC
= tcg_global_mem_new(cpu_env
,
942 offsetof(CPUHexagonState
, this_PC
), "this_PC");
943 hex_slot_cancelled
= tcg_global_mem_new(cpu_env
,
944 offsetof(CPUHexagonState
, slot_cancelled
), "slot_cancelled");
945 hex_branch_taken
= tcg_global_mem_new(cpu_env
,
946 offsetof(CPUHexagonState
, branch_taken
), "branch_taken");
947 hex_pkt_has_store_s1
= tcg_global_mem_new(cpu_env
,
948 offsetof(CPUHexagonState
, pkt_has_store_s1
), "pkt_has_store_s1");
949 hex_dczero_addr
= tcg_global_mem_new(cpu_env
,
950 offsetof(CPUHexagonState
, dczero_addr
), "dczero_addr");
951 hex_llsc_addr
= tcg_global_mem_new(cpu_env
,
952 offsetof(CPUHexagonState
, llsc_addr
), "llsc_addr");
953 hex_llsc_val
= tcg_global_mem_new(cpu_env
,
954 offsetof(CPUHexagonState
, llsc_val
), "llsc_val");
955 hex_llsc_val_i64
= tcg_global_mem_new_i64(cpu_env
,
956 offsetof(CPUHexagonState
, llsc_val_i64
), "llsc_val_i64");
957 hex_VRegs_updated
= tcg_global_mem_new(cpu_env
,
958 offsetof(CPUHexagonState
, VRegs_updated
), "VRegs_updated");
959 hex_QRegs_updated
= tcg_global_mem_new(cpu_env
,
960 offsetof(CPUHexagonState
, QRegs_updated
), "QRegs_updated");
961 for (i
= 0; i
< STORES_MAX
; i
++) {
962 snprintf(store_addr_names
[i
], NAME_LEN
, "store_addr_%d", i
);
963 hex_store_addr
[i
] = tcg_global_mem_new(cpu_env
,
964 offsetof(CPUHexagonState
, mem_log_stores
[i
].va
),
965 store_addr_names
[i
]);
967 snprintf(store_width_names
[i
], NAME_LEN
, "store_width_%d", i
);
968 hex_store_width
[i
] = tcg_global_mem_new(cpu_env
,
969 offsetof(CPUHexagonState
, mem_log_stores
[i
].width
),
970 store_width_names
[i
]);
972 snprintf(store_val32_names
[i
], NAME_LEN
, "store_val32_%d", i
);
973 hex_store_val32
[i
] = tcg_global_mem_new(cpu_env
,
974 offsetof(CPUHexagonState
, mem_log_stores
[i
].data32
),
975 store_val32_names
[i
]);
977 snprintf(store_val64_names
[i
], NAME_LEN
, "store_val64_%d", i
);
978 hex_store_val64
[i
] = tcg_global_mem_new_i64(cpu_env
,
979 offsetof(CPUHexagonState
, mem_log_stores
[i
].data64
),
980 store_val64_names
[i
]);
982 for (int i
= 0; i
< VSTORES_MAX
; i
++) {
983 snprintf(vstore_addr_names
[i
], NAME_LEN
, "vstore_addr_%d", i
);
984 hex_vstore_addr
[i
] = tcg_global_mem_new(cpu_env
,
985 offsetof(CPUHexagonState
, vstore
[i
].va
),
986 vstore_addr_names
[i
]);
988 snprintf(vstore_size_names
[i
], NAME_LEN
, "vstore_size_%d", i
);
989 hex_vstore_size
[i
] = tcg_global_mem_new(cpu_env
,
990 offsetof(CPUHexagonState
, vstore
[i
].size
),
991 vstore_size_names
[i
]);
993 snprintf(vstore_pending_names
[i
], NAME_LEN
, "vstore_pending_%d", i
);
994 hex_vstore_pending
[i
] = tcg_global_mem_new(cpu_env
,
995 offsetof(CPUHexagonState
, vstore_pending
[i
]),
996 vstore_pending_names
[i
]);