target/hexagon/translate.h

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_TRANSLATE_H
  19 #define HEXAGON_TRANSLATE_H
  20
  21 #include "qemu/bitmap.h"
  22 #include "qemu/log.h"
  23 #include "cpu.h"
  24 #include "exec/translator.h"
  25 #include "tcg/tcg-op.h"
  26 #include "insn.h"
  27 #include "internal.h"
  28
  29 typedef struct DisasContext {
  30     DisasContextBase base;
  31     Packet *pkt;
  32     Insn *insn;
  33     uint32_t next_PC;
  34     uint32_t mem_idx;
  35     uint32_t num_packets;
  36     uint32_t num_insns;
  37     uint32_t num_hvx_insns;
  38     int reg_log[REG_WRITES_MAX];
  39     int reg_log_idx;
  40     DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
  41     DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
  42     int preg_log[PRED_WRITES_MAX];
  43     int preg_log_idx;
  44     DECLARE_BITMAP(pregs_written, NUM_PREGS);
  45     uint8_t store_width[STORES_MAX];
  46     bool s1_store_processed;
  47     int future_vregs_idx;
  48     int future_vregs_num[VECTOR_TEMPS_MAX];
  49     int tmp_vregs_idx;
  50     int tmp_vregs_num[VECTOR_TEMPS_MAX];
  51     int vreg_log[NUM_VREGS];
  52     int vreg_log_idx;
  53     DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
  54     DECLARE_BITMAP(vregs_updated, NUM_VREGS);
  55     DECLARE_BITMAP(vregs_select, NUM_VREGS);
  56     DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
  57     DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
  58     int qreg_log[NUM_QREGS];
  59     int qreg_log_idx;
  60     bool pre_commit;
  61     TCGCond branch_cond;
  62     target_ulong branch_dest;
  63     bool is_tight_loop;
  64     bool need_pkt_has_store_s1;
  65 } DisasContext;
  66
  67 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
  68 {
  69     if (!test_bit(pnum, ctx->pregs_written)) {
  70         ctx->preg_log[ctx->preg_log_idx] = pnum;
  71         ctx->preg_log_idx++;
  72         set_bit(pnum, ctx->pregs_written);
  73     }
  74 }
  75
  76 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
  77                                      bool is_predicated)
  78 {
  79     if (rnum == HEX_REG_P3_0_ALIASED) {
  80         for (int i = 0; i < NUM_PREGS; i++) {
  81             ctx_log_pred_write(ctx, i);
  82         }
  83     } else {
  84         if (!test_bit(rnum, ctx->regs_written)) {
  85             ctx->reg_log[ctx->reg_log_idx] = rnum;
  86             ctx->reg_log_idx++;
  87             set_bit(rnum, ctx->regs_written);
  88         }
  89         if (is_predicated) {
  90             set_bit(rnum, ctx->predicated_regs);
  91         }
  92     }
  93 }
  94
  95 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
  96                                           bool is_predicated)
  97 {
  98     ctx_log_reg_write(ctx, rnum, is_predicated);
  99     ctx_log_reg_write(ctx, rnum + 1, is_predicated);
 100 }
 101
 102 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
 103                              int num, bool alloc_ok);
 104 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
 105                           int num, bool alloc_ok);
 106
 107 static inline void ctx_log_vreg_write(DisasContext *ctx,
 108                                       int rnum, VRegWriteType type,
 109                                       bool is_predicated)
 110 {
 111     if (type != EXT_TMP) {
 112         if (!test_bit(rnum, ctx->vregs_updated)) {
 113             ctx->vreg_log[ctx->vreg_log_idx] = rnum;
 114             ctx->vreg_log_idx++;
 115             set_bit(rnum, ctx->vregs_updated);
 116         }
 117
 118         set_bit(rnum, ctx->vregs_updated);
 119         if (is_predicated) {
 120             set_bit(rnum, ctx->predicated_future_vregs);
 121         }
 122     }
 123     if (type == EXT_NEW) {
 124         set_bit(rnum, ctx->vregs_select);
 125     }
 126     if (type == EXT_TMP) {
 127         set_bit(rnum, ctx->vregs_updated_tmp);
 128         if (is_predicated) {
 129             set_bit(rnum, ctx->predicated_tmp_vregs);
 130         }
 131     }
 132 }
 133
 134 static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
 135                                            int rnum, VRegWriteType type,
 136                                            bool is_predicated)
 137 {
 138     ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
 139     ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
 140 }
 141
 142 static inline void ctx_log_qreg_write(DisasContext *ctx,
 143                                       int rnum)
 144 {
 145     ctx->qreg_log[ctx->qreg_log_idx] = rnum;
 146     ctx->qreg_log_idx++;
 147 }
 148
 149 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
 150 extern TCGv hex_pred[NUM_PREGS];
 151 extern TCGv hex_this_PC;
 152 extern TCGv hex_slot_cancelled;
 153 extern TCGv hex_branch_taken;
 154 extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
 155 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
 156 extern TCGv hex_new_pred_value[NUM_PREGS];
 157 extern TCGv hex_pred_written;
 158 extern TCGv hex_store_addr[STORES_MAX];
 159 extern TCGv hex_store_width[STORES_MAX];
 160 extern TCGv hex_store_val32[STORES_MAX];
 161 extern TCGv_i64 hex_store_val64[STORES_MAX];
 162 extern TCGv hex_dczero_addr;
 163 extern TCGv hex_llsc_addr;
 164 extern TCGv hex_llsc_val;
 165 extern TCGv_i64 hex_llsc_val_i64;
 166 extern TCGv hex_vstore_addr[VSTORES_MAX];
 167 extern TCGv hex_vstore_size[VSTORES_MAX];
 168 extern TCGv hex_vstore_pending[VSTORES_MAX];
 169
 170 bool is_gather_store_insn(DisasContext *ctx);
 171 void process_store(DisasContext *ctx, int slot_num);
 172
 173 FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX,       0, 2)
 174 FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1)
 175
 176 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0,        0, 1)
 177 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1,        1, 1)
 178 FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
 179 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED,     3, 1)
 180 FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED,     4, 1)
 181
 182 #endif