target/hexagon/translate.h

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_TRANSLATE_H
  19 #define HEXAGON_TRANSLATE_H
  20
  21 #include "qemu/bitmap.h"
  22 #include "cpu.h"
  23 #include "exec/translator.h"
  24 #include "tcg/tcg-op.h"
  25 #include "internal.h"
  26
  27 typedef struct DisasContext {
  28     DisasContextBase base;
  29     uint32_t mem_idx;
  30     uint32_t num_packets;
  31     uint32_t num_insns;
  32     uint32_t num_hvx_insns;
  33     int reg_log[REG_WRITES_MAX];
  34     int reg_log_idx;
  35     DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
  36     int preg_log[PRED_WRITES_MAX];
  37     int preg_log_idx;
  38     DECLARE_BITMAP(pregs_written, NUM_PREGS);
  39     uint8_t store_width[STORES_MAX];
  40     bool s1_store_processed;
  41     int future_vregs_idx;
  42     int future_vregs_num[VECTOR_TEMPS_MAX];
  43     int tmp_vregs_idx;
  44     int tmp_vregs_num[VECTOR_TEMPS_MAX];
  45     int vreg_log[NUM_VREGS];
  46     bool vreg_is_predicated[NUM_VREGS];
  47     int vreg_log_idx;
  48     DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
  49     DECLARE_BITMAP(vregs_updated, NUM_VREGS);
  50     DECLARE_BITMAP(vregs_select, NUM_VREGS);
  51     int qreg_log[NUM_QREGS];
  52     bool qreg_is_predicated[NUM_QREGS];
  53     int qreg_log_idx;
  54     bool pre_commit;
  55 } DisasContext;
  56
  57 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
  58 {
  59     if (test_bit(rnum, ctx->regs_written)) {
  60         HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum);
  61     }
  62     ctx->reg_log[ctx->reg_log_idx] = rnum;
  63     ctx->reg_log_idx++;
  64     set_bit(rnum, ctx->regs_written);
  65 }
  66
  67 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum)
  68 {
  69     ctx_log_reg_write(ctx, rnum);
  70     ctx_log_reg_write(ctx, rnum + 1);
  71 }
  72
  73 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
  74 {
  75     ctx->preg_log[ctx->preg_log_idx] = pnum;
  76     ctx->preg_log_idx++;
  77     set_bit(pnum, ctx->pregs_written);
  78 }
  79
  80 static inline bool is_preloaded(DisasContext *ctx, int num)
  81 {
  82     return test_bit(num, ctx->regs_written);
  83 }
  84
  85 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
  86                              int num, bool alloc_ok);
  87 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
  88                           int num, bool alloc_ok);
  89
  90 static inline void ctx_log_vreg_write(DisasContext *ctx,
  91                                       int rnum, VRegWriteType type,
  92                                       bool is_predicated)
  93 {
  94     if (type != EXT_TMP) {
  95         ctx->vreg_log[ctx->vreg_log_idx] = rnum;
  96         ctx->vreg_is_predicated[ctx->vreg_log_idx] = is_predicated;
  97         ctx->vreg_log_idx++;
  98
  99         set_bit(rnum, ctx->vregs_updated);
 100     }
 101     if (type == EXT_NEW) {
 102         set_bit(rnum, ctx->vregs_select);
 103     }
 104     if (type == EXT_TMP) {
 105         set_bit(rnum, ctx->vregs_updated_tmp);
 106     }
 107 }
 108
 109 static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
 110                                            int rnum, VRegWriteType type,
 111                                            bool is_predicated)
 112 {
 113     ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
 114     ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
 115 }
 116
 117 static inline void ctx_log_qreg_write(DisasContext *ctx,
 118                                       int rnum, bool is_predicated)
 119 {
 120     ctx->qreg_log[ctx->qreg_log_idx] = rnum;
 121     ctx->qreg_is_predicated[ctx->qreg_log_idx] = is_predicated;
 122     ctx->qreg_log_idx++;
 123 }
 124
 125 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
 126 extern TCGv hex_pred[NUM_PREGS];
 127 extern TCGv hex_next_PC;
 128 extern TCGv hex_this_PC;
 129 extern TCGv hex_slot_cancelled;
 130 extern TCGv hex_branch_taken;
 131 extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
 132 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
 133 extern TCGv hex_new_pred_value[NUM_PREGS];
 134 extern TCGv hex_pred_written;
 135 extern TCGv hex_store_addr[STORES_MAX];
 136 extern TCGv hex_store_width[STORES_MAX];
 137 extern TCGv hex_store_val32[STORES_MAX];
 138 extern TCGv_i64 hex_store_val64[STORES_MAX];
 139 extern TCGv hex_dczero_addr;
 140 extern TCGv hex_llsc_addr;
 141 extern TCGv hex_llsc_val;
 142 extern TCGv_i64 hex_llsc_val_i64;
 143 extern TCGv hex_VRegs_updated;
 144 extern TCGv hex_QRegs_updated;
 145 extern TCGv hex_vstore_addr[VSTORES_MAX];
 146 extern TCGv hex_vstore_size[VSTORES_MAX];
 147 extern TCGv hex_vstore_pending[VSTORES_MAX];
 148
 149 bool is_gather_store_insn(Insn *insn, Packet *pkt);
 150 void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
 151 #endif