target/hexagon/translate.h

   1 /*
   2  *  Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_TRANSLATE_H
  19 #define HEXAGON_TRANSLATE_H
  20
  21 #include "qemu/bitmap.h"
  22 #include "qemu/log.h"
  23 #include "cpu.h"
  24 #include "exec/translator.h"
  25 #include "tcg/tcg-op.h"
  26 #include "insn.h"
  27 #include "internal.h"
  28
  29 typedef struct DisasContext {
  30     DisasContextBase base;
  31     Packet *pkt;
  32     Insn *insn;
  33     uint32_t next_PC;
  34     uint32_t mem_idx;
  35     uint32_t num_packets;
  36     uint32_t num_insns;
  37     uint32_t num_hvx_insns;
  38     int reg_log[REG_WRITES_MAX];
  39     int reg_log_idx;
  40     DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
  41     DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
  42     int preg_log[PRED_WRITES_MAX];
  43     int preg_log_idx;
  44     DECLARE_BITMAP(pregs_written, NUM_PREGS);
  45     uint8_t store_width[STORES_MAX];
  46     bool s1_store_processed;
  47     int future_vregs_idx;
  48     int future_vregs_num[VECTOR_TEMPS_MAX];
  49     int tmp_vregs_idx;
  50     int tmp_vregs_num[VECTOR_TEMPS_MAX];
  51     int vreg_log[NUM_VREGS];
  52     bool vreg_is_predicated[NUM_VREGS];
  53     int vreg_log_idx;
  54     DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
  55     DECLARE_BITMAP(vregs_updated, NUM_VREGS);
  56     DECLARE_BITMAP(vregs_select, NUM_VREGS);
  57     int qreg_log[NUM_QREGS];
  58     bool qreg_is_predicated[NUM_QREGS];
  59     int qreg_log_idx;
  60     bool pre_commit;
  61     TCGCond branch_cond;
  62     target_ulong branch_dest;
  63     bool is_tight_loop;
  64 } DisasContext;
  65
  66 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
  67 {
  68     if (!test_bit(pnum, ctx->pregs_written)) {
  69         ctx->preg_log[ctx->preg_log_idx] = pnum;
  70         ctx->preg_log_idx++;
  71         set_bit(pnum, ctx->pregs_written);
  72     }
  73 }
  74
  75 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
  76                                      bool is_predicated)
  77 {
  78     if (rnum == HEX_REG_P3_0_ALIASED) {
  79         for (int i = 0; i < NUM_PREGS; i++) {
  80             ctx_log_pred_write(ctx, i);
  81         }
  82     } else {
  83         if (!test_bit(rnum, ctx->regs_written)) {
  84             ctx->reg_log[ctx->reg_log_idx] = rnum;
  85             ctx->reg_log_idx++;
  86             set_bit(rnum, ctx->regs_written);
  87         }
  88         if (is_predicated) {
  89             set_bit(rnum, ctx->predicated_regs);
  90         }
  91     }
  92 }
  93
  94 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
  95                                           bool is_predicated)
  96 {
  97     ctx_log_reg_write(ctx, rnum, is_predicated);
  98     ctx_log_reg_write(ctx, rnum + 1, is_predicated);
  99 }
 100
 101 static inline bool is_vreg_preloaded(DisasContext *ctx, int num)
 102 {
 103     return test_bit(num, ctx->vregs_updated) ||
 104            test_bit(num, ctx->vregs_updated_tmp);
 105 }
 106
 107 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
 108                              int num, bool alloc_ok);
 109 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
 110                           int num, bool alloc_ok);
 111
 112 static inline void ctx_log_vreg_write(DisasContext *ctx,
 113                                       int rnum, VRegWriteType type,
 114                                       bool is_predicated)
 115 {
 116     if (type != EXT_TMP) {
 117         ctx->vreg_log[ctx->vreg_log_idx] = rnum;
 118         ctx->vreg_is_predicated[ctx->vreg_log_idx] = is_predicated;
 119         ctx->vreg_log_idx++;
 120
 121         set_bit(rnum, ctx->vregs_updated);
 122     }
 123     if (type == EXT_NEW) {
 124         set_bit(rnum, ctx->vregs_select);
 125     }
 126     if (type == EXT_TMP) {
 127         set_bit(rnum, ctx->vregs_updated_tmp);
 128     }
 129 }
 130
 131 static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
 132                                            int rnum, VRegWriteType type,
 133                                            bool is_predicated)
 134 {
 135     ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
 136     ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
 137 }
 138
 139 static inline void ctx_log_qreg_write(DisasContext *ctx,
 140                                       int rnum, bool is_predicated)
 141 {
 142     ctx->qreg_log[ctx->qreg_log_idx] = rnum;
 143     ctx->qreg_is_predicated[ctx->qreg_log_idx] = is_predicated;
 144     ctx->qreg_log_idx++;
 145 }
 146
 147 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
 148 extern TCGv hex_pred[NUM_PREGS];
 149 extern TCGv hex_this_PC;
 150 extern TCGv hex_slot_cancelled;
 151 extern TCGv hex_branch_taken;
 152 extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
 153 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
 154 extern TCGv hex_new_pred_value[NUM_PREGS];
 155 extern TCGv hex_pred_written;
 156 extern TCGv hex_store_addr[STORES_MAX];
 157 extern TCGv hex_store_width[STORES_MAX];
 158 extern TCGv hex_store_val32[STORES_MAX];
 159 extern TCGv_i64 hex_store_val64[STORES_MAX];
 160 extern TCGv hex_dczero_addr;
 161 extern TCGv hex_llsc_addr;
 162 extern TCGv hex_llsc_val;
 163 extern TCGv_i64 hex_llsc_val_i64;
 164 extern TCGv hex_VRegs_updated;
 165 extern TCGv hex_QRegs_updated;
 166 extern TCGv hex_vstore_addr[VSTORES_MAX];
 167 extern TCGv hex_vstore_size[VSTORES_MAX];
 168 extern TCGv hex_vstore_pending[VSTORES_MAX];
 169
 170 bool is_gather_store_insn(DisasContext *ctx);
 171 void process_store(DisasContext *ctx, int slot_num);
 172 #endif