target/hexagon/translate.h

   1 /*
   2  *  Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
   3  *
   4  *  This program is free software; you can redistribute it and/or modify
   5  *  it under the terms of the GNU General Public License as published by
   6  *  the Free Software Foundation; either version 2 of the License, or
   7  *  (at your option) any later version.
   8  *
   9  *  This program is distributed in the hope that it will be useful,
  10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  *  GNU General Public License for more details.
  13  *
  14  *  You should have received a copy of the GNU General Public License
  15  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #ifndef HEXAGON_TRANSLATE_H
  19 #define HEXAGON_TRANSLATE_H
  20
  21 #include "qemu/bitmap.h"
  22 #include "qemu/log.h"
  23 #include "cpu.h"
  24 #include "exec/translator.h"
  25 #include "tcg/tcg-op.h"
  26 #include "internal.h"
  27
  28 typedef struct DisasContext {
  29     DisasContextBase base;
  30     uint32_t mem_idx;
  31     uint32_t num_packets;
  32     uint32_t num_insns;
  33     uint32_t num_hvx_insns;
  34     int reg_log[REG_WRITES_MAX];
  35     int reg_log_idx;
  36     DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
  37     int preg_log[PRED_WRITES_MAX];
  38     int preg_log_idx;
  39     DECLARE_BITMAP(pregs_written, NUM_PREGS);
  40     uint8_t store_width[STORES_MAX];
  41     bool s1_store_processed;
  42     int future_vregs_idx;
  43     int future_vregs_num[VECTOR_TEMPS_MAX];
  44     int tmp_vregs_idx;
  45     int tmp_vregs_num[VECTOR_TEMPS_MAX];
  46     int vreg_log[NUM_VREGS];
  47     bool vreg_is_predicated[NUM_VREGS];
  48     int vreg_log_idx;
  49     DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
  50     DECLARE_BITMAP(vregs_updated, NUM_VREGS);
  51     DECLARE_BITMAP(vregs_select, NUM_VREGS);
  52     int qreg_log[NUM_QREGS];
  53     bool qreg_is_predicated[NUM_QREGS];
  54     int qreg_log_idx;
  55     bool pre_commit;
  56 } DisasContext;
  57
  58 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
  59 {
  60     if (test_bit(rnum, ctx->regs_written)) {
  61         HEX_DEBUG_LOG("WARNING: Multiple writes to r%d\n", rnum);
  62     }
  63     ctx->reg_log[ctx->reg_log_idx] = rnum;
  64     ctx->reg_log_idx++;
  65     set_bit(rnum, ctx->regs_written);
  66 }
  67
  68 static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum)
  69 {
  70     ctx_log_reg_write(ctx, rnum);
  71     ctx_log_reg_write(ctx, rnum + 1);
  72 }
  73
  74 static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
  75 {
  76     ctx->preg_log[ctx->preg_log_idx] = pnum;
  77     ctx->preg_log_idx++;
  78     set_bit(pnum, ctx->pregs_written);
  79 }
  80
  81 static inline bool is_preloaded(DisasContext *ctx, int num)
  82 {
  83     return test_bit(num, ctx->regs_written);
  84 }
  85
  86 intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
  87                              int num, bool alloc_ok);
  88 intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
  89                           int num, bool alloc_ok);
  90
  91 static inline void ctx_log_vreg_write(DisasContext *ctx,
  92                                       int rnum, VRegWriteType type,
  93                                       bool is_predicated)
  94 {
  95     if (type != EXT_TMP) {
  96         ctx->vreg_log[ctx->vreg_log_idx] = rnum;
  97         ctx->vreg_is_predicated[ctx->vreg_log_idx] = is_predicated;
  98         ctx->vreg_log_idx++;
  99
 100         set_bit(rnum, ctx->vregs_updated);
 101     }
 102     if (type == EXT_NEW) {
 103         set_bit(rnum, ctx->vregs_select);
 104     }
 105     if (type == EXT_TMP) {
 106         set_bit(rnum, ctx->vregs_updated_tmp);
 107     }
 108 }
 109
 110 static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
 111                                            int rnum, VRegWriteType type,
 112                                            bool is_predicated)
 113 {
 114     ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
 115     ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
 116 }
 117
 118 static inline void ctx_log_qreg_write(DisasContext *ctx,
 119                                       int rnum, bool is_predicated)
 120 {
 121     ctx->qreg_log[ctx->qreg_log_idx] = rnum;
 122     ctx->qreg_is_predicated[ctx->qreg_log_idx] = is_predicated;
 123     ctx->qreg_log_idx++;
 124 }
 125
 126 extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
 127 extern TCGv hex_pred[NUM_PREGS];
 128 extern TCGv hex_next_PC;
 129 extern TCGv hex_this_PC;
 130 extern TCGv hex_slot_cancelled;
 131 extern TCGv hex_branch_taken;
 132 extern TCGv hex_new_value[TOTAL_PER_THREAD_REGS];
 133 extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
 134 extern TCGv hex_new_pred_value[NUM_PREGS];
 135 extern TCGv hex_pred_written;
 136 extern TCGv hex_store_addr[STORES_MAX];
 137 extern TCGv hex_store_width[STORES_MAX];
 138 extern TCGv hex_store_val32[STORES_MAX];
 139 extern TCGv_i64 hex_store_val64[STORES_MAX];
 140 extern TCGv hex_dczero_addr;
 141 extern TCGv hex_llsc_addr;
 142 extern TCGv hex_llsc_val;
 143 extern TCGv_i64 hex_llsc_val_i64;
 144 extern TCGv hex_VRegs_updated;
 145 extern TCGv hex_QRegs_updated;
 146 extern TCGv hex_vstore_addr[VSTORES_MAX];
 147 extern TCGv hex_vstore_size[VSTORES_MAX];
 148 extern TCGv hex_vstore_pending[VSTORES_MAX];
 149
 150 bool is_gather_store_insn(Insn *insn, Packet *pkt);
 151 void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
 152 #endif