4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/qemu-print.h"
24 #include "qemu/timer.h"
26 #include "qemu/module.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat.h"
31 static void hppa_cpu_set_pc(CPUState
*cs
, vaddr value
)
33 HPPACPU
*cpu
= HPPA_CPU(cs
);
35 cpu
->env
.iaoq_f
= value
;
36 cpu
->env
.iaoq_b
= value
+ 4;
39 static vaddr
hppa_cpu_get_pc(CPUState
*cs
)
41 HPPACPU
*cpu
= HPPA_CPU(cs
);
43 return cpu
->env
.iaoq_f
;
46 static void hppa_cpu_synchronize_from_tb(CPUState
*cs
,
47 const TranslationBlock
*tb
)
49 HPPACPU
*cpu
= HPPA_CPU(cs
);
51 tcg_debug_assert(!(cs
->tcg_cflags
& CF_PCREL
));
53 #ifdef CONFIG_USER_ONLY
54 cpu
->env
.iaoq_f
= tb
->pc
;
55 cpu
->env
.iaoq_b
= tb
->cs_base
;
57 /* Recover the IAOQ values from the GVA + PRIV. */
58 uint32_t priv
= (tb
->flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
59 target_ulong cs_base
= tb
->cs_base
;
60 target_ulong iasq_f
= cs_base
& ~0xffffffffull
;
61 int32_t diff
= cs_base
;
63 cpu
->env
.iasq_f
= iasq_f
;
64 cpu
->env
.iaoq_f
= (tb
->pc
& ~iasq_f
) + priv
;
66 cpu
->env
.iaoq_b
= cpu
->env
.iaoq_f
+ diff
;
70 cpu
->env
.psw_n
= (tb
->flags
& PSW_N
) != 0;
73 static void hppa_restore_state_to_opc(CPUState
*cs
,
74 const TranslationBlock
*tb
,
77 HPPACPU
*cpu
= HPPA_CPU(cs
);
79 cpu
->env
.iaoq_f
= data
[0];
80 if (data
[1] != (target_ulong
)-1) {
81 cpu
->env
.iaoq_b
= data
[1];
83 cpu
->env
.unwind_breg
= data
[2];
85 * Since we were executing the instruction at IAOQ_F, and took some
86 * sort of action that provoked the cpu_restore_state, we can infer
87 * that the instruction was not nullified.
92 static bool hppa_cpu_has_work(CPUState
*cs
)
94 return cs
->interrupt_request
& (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_NMI
);
97 static void hppa_cpu_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
99 info
->mach
= bfd_mach_hppa20
;
100 info
->print_insn
= print_insn_hppa
;
103 #ifndef CONFIG_USER_ONLY
105 void hppa_cpu_do_unaligned_access(CPUState
*cs
, vaddr addr
,
106 MMUAccessType access_type
, int mmu_idx
,
109 HPPACPU
*cpu
= HPPA_CPU(cs
);
110 CPUHPPAState
*env
= &cpu
->env
;
112 cs
->exception_index
= EXCP_UNALIGN
;
113 hppa_set_ior_and_isr(env
, addr
, MMU_IDX_MMU_DISABLED(mmu_idx
));
115 cpu_loop_exit_restore(cs
, retaddr
);
117 #endif /* CONFIG_USER_ONLY */
119 static void hppa_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
121 CPUState
*cs
= CPU(dev
);
122 HPPACPUClass
*acc
= HPPA_CPU_GET_CLASS(dev
);
123 Error
*local_err
= NULL
;
125 cpu_exec_realizefn(cs
, &local_err
);
126 if (local_err
!= NULL
) {
127 error_propagate(errp
, local_err
);
132 acc
->parent_realize(dev
, errp
);
134 #ifndef CONFIG_USER_ONLY
136 HPPACPU
*cpu
= HPPA_CPU(cs
);
138 cpu
->alarm_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
139 hppa_cpu_alarm_timer
, cpu
);
140 hppa_ptlbe(&cpu
->env
);
145 static void hppa_cpu_initfn(Object
*obj
)
147 CPUState
*cs
= CPU(obj
);
148 HPPACPU
*cpu
= HPPA_CPU(obj
);
149 CPUHPPAState
*env
= &cpu
->env
;
151 cs
->exception_index
= -1;
152 cpu_hppa_loaded_fr0(env
);
153 cpu_hppa_put_psw(env
, PSW_W
);
156 static ObjectClass
*hppa_cpu_class_by_name(const char *cpu_model
)
158 g_autofree
char *typename
= g_strconcat(cpu_model
, "-cpu", NULL
);
160 return object_class_by_name(typename
);
163 #ifndef CONFIG_USER_ONLY
164 #include "hw/core/sysemu-cpu-ops.h"
166 static const struct SysemuCPUOps hppa_sysemu_ops
= {
167 .get_phys_page_debug
= hppa_cpu_get_phys_page_debug
,
171 #include "hw/core/tcg-cpu-ops.h"
173 static const struct TCGCPUOps hppa_tcg_ops
= {
174 .initialize
= hppa_translate_init
,
175 .synchronize_from_tb
= hppa_cpu_synchronize_from_tb
,
176 .restore_state_to_opc
= hppa_restore_state_to_opc
,
178 #ifndef CONFIG_USER_ONLY
179 .tlb_fill
= hppa_cpu_tlb_fill
,
180 .cpu_exec_interrupt
= hppa_cpu_exec_interrupt
,
181 .do_interrupt
= hppa_cpu_do_interrupt
,
182 .do_unaligned_access
= hppa_cpu_do_unaligned_access
,
183 #endif /* !CONFIG_USER_ONLY */
186 static void hppa_cpu_class_init(ObjectClass
*oc
, void *data
)
188 DeviceClass
*dc
= DEVICE_CLASS(oc
);
189 CPUClass
*cc
= CPU_CLASS(oc
);
190 HPPACPUClass
*acc
= HPPA_CPU_CLASS(oc
);
192 device_class_set_parent_realize(dc
, hppa_cpu_realizefn
,
193 &acc
->parent_realize
);
195 cc
->class_by_name
= hppa_cpu_class_by_name
;
196 cc
->has_work
= hppa_cpu_has_work
;
197 cc
->dump_state
= hppa_cpu_dump_state
;
198 cc
->set_pc
= hppa_cpu_set_pc
;
199 cc
->get_pc
= hppa_cpu_get_pc
;
200 cc
->gdb_read_register
= hppa_cpu_gdb_read_register
;
201 cc
->gdb_write_register
= hppa_cpu_gdb_write_register
;
202 #ifndef CONFIG_USER_ONLY
203 dc
->vmsd
= &vmstate_hppa_cpu
;
204 cc
->sysemu_ops
= &hppa_sysemu_ops
;
206 cc
->disas_set_info
= hppa_cpu_disas_set_info
;
207 cc
->gdb_num_core_regs
= 128;
208 cc
->tcg_ops
= &hppa_tcg_ops
;
211 static const TypeInfo hppa_cpu_type_infos
[] = {
213 .name
= TYPE_HPPA_CPU
,
215 .instance_size
= sizeof(HPPACPU
),
216 .instance_align
= __alignof(HPPACPU
),
217 .instance_init
= hppa_cpu_initfn
,
219 .class_size
= sizeof(HPPACPUClass
),
220 .class_init
= hppa_cpu_class_init
,
223 .name
= TYPE_HPPA64_CPU
,
224 .parent
= TYPE_HPPA_CPU
,
228 DEFINE_TYPES(hppa_cpu_type_infos
)