target/hppa/cpu.c

   1 /*
   2  * QEMU HPPA CPU
   3  *
   4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "cpu.h"
  24 #include "qemu-common.h"
  25 #include "exec/exec-all.h"
  26
  27
  28 static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     HPPACPU *cpu = HPPA_CPU(cs);
  31
  32     cpu->env.iaoq_f = value;
  33     cpu->env.iaoq_b = value + 4;
  34 }
  35
  36 static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  37 {
  38     HPPACPU *cpu = HPPA_CPU(cs);
  39
  40 #ifdef CONFIG_USER_ONLY
  41     cpu->env.iaoq_f = tb->pc;
  42     cpu->env.iaoq_b = tb->cs_base;
  43 #else
  44     /* Recover the IAOQ values from the GVA + PRIV.  */
  45     uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3;
  46     target_ulong cs_base = tb->cs_base;
  47     target_ulong iasq_f = cs_base & ~0xffffffffull;
  48     int32_t diff = cs_base;
  49
  50     cpu->env.iasq_f = iasq_f;
  51     cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
  52     if (diff) {
  53         cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
  54     }
  55 #endif
  56
  57     cpu->env.psw_n = (tb->flags & PSW_N) != 0;
  58 }
  59
  60 static bool hppa_cpu_has_work(CPUState *cs)
  61 {
  62     return cs->interrupt_request & CPU_INTERRUPT_HARD;
  63 }
  64
  65 static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
  66 {
  67     info->mach = bfd_mach_hppa20;
  68     info->print_insn = print_insn_hppa;
  69 }
  70
  71 static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
  72                                          MMUAccessType access_type,
  73                                          int mmu_idx, uintptr_t retaddr)
  74 {
  75     HPPACPU *cpu = HPPA_CPU(cs);
  76     CPUHPPAState *env = &cpu->env;
  77
  78     cs->exception_index = EXCP_UNALIGN;
  79     if (env->psw & PSW_Q) {
  80         /* ??? Needs tweaking for hppa64.  */
  81         env->cr[CR_IOR] = addr;
  82         env->cr[CR_ISR] = addr >> 32;
  83     }
  84
  85     cpu_loop_exit_restore(cs, retaddr);
  86 }
  87
  88 static void hppa_cpu_realizefn(DeviceState *dev, Error **errp)
  89 {
  90     CPUState *cs = CPU(dev);
  91     HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev);
  92     Error *local_err = NULL;
  93
  94     cpu_exec_realizefn(cs, &local_err);
  95     if (local_err != NULL) {
  96         error_propagate(errp, local_err);
  97         return;
  98     }
  99
 100     qemu_init_vcpu(cs);
 101     acc->parent_realize(dev, errp);
 102
 103 #ifndef CONFIG_USER_ONLY
 104     {
 105         HPPACPU *cpu = HPPA_CPU(cs);
 106         cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
 107                                         hppa_cpu_alarm_timer, cpu);
 108     }
 109 #endif
 110 }
 111
 112 /* Sort hppabetically by type name. */
 113 static gint hppa_cpu_list_compare(gconstpointer a, gconstpointer b)
 114 {
 115     ObjectClass *class_a = (ObjectClass *)a;
 116     ObjectClass *class_b = (ObjectClass *)b;
 117     const char *name_a, *name_b;
 118
 119     name_a = object_class_get_name(class_a);
 120     name_b = object_class_get_name(class_b);
 121     return strcmp(name_a, name_b);
 122 }
 123
 124 static void hppa_cpu_list_entry(gpointer data, gpointer user_data)
 125 {
 126     ObjectClass *oc = data;
 127     CPUListState *s = user_data;
 128
 129     (*s->cpu_fprintf)(s->file, "  %s\n", object_class_get_name(oc));
 130 }
 131
 132 void hppa_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 133 {
 134     CPUListState s = {
 135         .file = f,
 136         .cpu_fprintf = cpu_fprintf,
 137     };
 138     GSList *list;
 139
 140     list = object_class_get_list(TYPE_HPPA_CPU, false);
 141     list = g_slist_sort(list, hppa_cpu_list_compare);
 142     (*cpu_fprintf)(f, "Available CPUs:\n");
 143     g_slist_foreach(list, hppa_cpu_list_entry, &s);
 144     g_slist_free(list);
 145 }
 146
 147 static void hppa_cpu_initfn(Object *obj)
 148 {
 149     CPUState *cs = CPU(obj);
 150     HPPACPU *cpu = HPPA_CPU(obj);
 151     CPUHPPAState *env = &cpu->env;
 152
 153     cs->env_ptr = env;
 154     cs->exception_index = -1;
 155     cpu_hppa_loaded_fr0(env);
 156     set_snan_bit_is_one(true, &env->fp_status);
 157     cpu_hppa_put_psw(env, PSW_W);
 158 }
 159
 160 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model)
 161 {
 162     return object_class_by_name(TYPE_HPPA_CPU);
 163 }
 164
 165 static void hppa_cpu_class_init(ObjectClass *oc, void *data)
 166 {
 167     DeviceClass *dc = DEVICE_CLASS(oc);
 168     CPUClass *cc = CPU_CLASS(oc);
 169     HPPACPUClass *acc = HPPA_CPU_CLASS(oc);
 170
 171     device_class_set_parent_realize(dc, hppa_cpu_realizefn,
 172                                     &acc->parent_realize);
 173
 174     cc->class_by_name = hppa_cpu_class_by_name;
 175     cc->has_work = hppa_cpu_has_work;
 176     cc->do_interrupt = hppa_cpu_do_interrupt;
 177     cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt;
 178     cc->dump_state = hppa_cpu_dump_state;
 179     cc->set_pc = hppa_cpu_set_pc;
 180     cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb;
 181     cc->gdb_read_register = hppa_cpu_gdb_read_register;
 182     cc->gdb_write_register = hppa_cpu_gdb_write_register;
 183 #ifdef CONFIG_USER_ONLY
 184     cc->handle_mmu_fault = hppa_cpu_handle_mmu_fault;
 185 #else
 186     cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug;
 187     dc->vmsd = &vmstate_hppa_cpu;
 188 #endif
 189     cc->do_unaligned_access = hppa_cpu_do_unaligned_access;
 190     cc->disas_set_info = hppa_cpu_disas_set_info;
 191     cc->tcg_initialize = hppa_translate_init;
 192
 193     cc->gdb_num_core_regs = 128;
 194 }
 195
 196 static const TypeInfo hppa_cpu_type_info = {
 197     .name = TYPE_HPPA_CPU,
 198     .parent = TYPE_CPU,
 199     .instance_size = sizeof(HPPACPU),
 200     .instance_init = hppa_cpu_initfn,
 201     .abstract = false,
 202     .class_size = sizeof(HPPACPUClass),
 203     .class_init = hppa_cpu_class_init,
 204 };
 205
 206 static void hppa_cpu_register_types(void)
 207 {
 208     type_register_static(&hppa_cpu_type_info);
 209 }
 210
 211 type_init(hppa_cpu_register_types)