target/hppa/cpu.h

   1 /*
   2  * PA-RISC emulation cpu definitions for qemu.
   3  *
   4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HPPA_CPU_H
  21 #define HPPA_CPU_H
  22
  23 #include "cpu-qom.h"
  24 #include "exec/cpu-defs.h"
  25 #include "qemu/cpu-float.h"
  26
  27 /* PA-RISC 1.x processors have a strong memory model.  */
  28 /* ??? While we do not yet implement PA-RISC 2.0, those processors have
  29    a weak memory model, but with TLB bits that force ordering on a per-page
  30    basis.  It's probably easier to fall back to a strong memory model.  */
  31 #define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
  32
  33 #define MMU_KERNEL_IDX   0
  34 #define MMU_PL1_IDX      1
  35 #define MMU_PL2_IDX      2
  36 #define MMU_USER_IDX     3
  37 #define MMU_PHYS_IDX     4
  38
  39 #define PRIV_TO_MMU_IDX(priv)    (priv)
  40 #define MMU_IDX_TO_PRIV(mmu_idx) (mmu_idx)
  41
  42 #define TARGET_INSN_START_EXTRA_WORDS 1
  43
  44 /* Hardware exceptions, interrupts, faults, and traps.  */
  45 #define EXCP_HPMC                1  /* high priority machine check */
  46 #define EXCP_POWER_FAIL          2
  47 #define EXCP_RC                  3  /* recovery counter */
  48 #define EXCP_EXT_INTERRUPT       4  /* external interrupt */
  49 #define EXCP_LPMC                5  /* low priority machine check */
  50 #define EXCP_ITLB_MISS           6  /* itlb miss / instruction page fault */
  51 #define EXCP_IMP                 7  /* instruction memory protection trap */
  52 #define EXCP_ILL                 8  /* illegal instruction trap */
  53 #define EXCP_BREAK               9  /* break instruction */
  54 #define EXCP_PRIV_OPR            10 /* privileged operation trap */
  55 #define EXCP_PRIV_REG            11 /* privileged register trap */
  56 #define EXCP_OVERFLOW            12 /* signed overflow trap */
  57 #define EXCP_COND                13 /* trap-on-condition */
  58 #define EXCP_ASSIST              14 /* assist exception trap */
  59 #define EXCP_DTLB_MISS           15 /* dtlb miss / data page fault */
  60 #define EXCP_NA_ITLB_MISS        16 /* non-access itlb miss */
  61 #define EXCP_NA_DTLB_MISS        17 /* non-access dtlb miss */
  62 #define EXCP_DMP                 18 /* data memory protection trap */
  63 #define EXCP_DMB                 19 /* data memory break trap */
  64 #define EXCP_TLB_DIRTY           20 /* tlb dirty bit trap */
  65 #define EXCP_PAGE_REF            21 /* page reference trap */
  66 #define EXCP_ASSIST_EMU          22 /* assist emulation trap */
  67 #define EXCP_HPT                 23 /* high-privilege transfer trap */
  68 #define EXCP_LPT                 24 /* low-privilege transfer trap */
  69 #define EXCP_TB                  25 /* taken branch trap */
  70 #define EXCP_DMAR                26 /* data memory access rights trap */
  71 #define EXCP_DMPI                27 /* data memory protection id trap */
  72 #define EXCP_UNALIGN             28 /* unaligned data reference trap */
  73 #define EXCP_PER_INTERRUPT       29 /* performance monitor interrupt */
  74
  75 /* Exceptions for linux-user emulation.  */
  76 #define EXCP_SYSCALL             30
  77 #define EXCP_SYSCALL_LWS         31
  78
  79 /* Emulated hardware TOC button */
  80 #define EXCP_TOC                 32 /* TOC = Transfer of control (NMI) */
  81
  82 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3         /* TOC */
  83
  84 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
  85 #define PSW_I            0x00000001
  86 #define PSW_D            0x00000002
  87 #define PSW_P            0x00000004
  88 #define PSW_Q            0x00000008
  89 #define PSW_R            0x00000010
  90 #define PSW_F            0x00000020
  91 #define PSW_G            0x00000040 /* PA1.x only */
  92 #define PSW_O            0x00000080 /* PA2.0 only */
  93 #define PSW_CB           0x0000ff00
  94 #define PSW_M            0x00010000
  95 #define PSW_V            0x00020000
  96 #define PSW_C            0x00040000
  97 #define PSW_B            0x00080000
  98 #define PSW_X            0x00100000
  99 #define PSW_N            0x00200000
 100 #define PSW_L            0x00400000
 101 #define PSW_H            0x00800000
 102 #define PSW_T            0x01000000
 103 #define PSW_S            0x02000000
 104 #define PSW_E            0x04000000
 105 #ifdef TARGET_HPPA64
 106 #define PSW_W            0x08000000 /* PA2.0 only */
 107 #else
 108 #define PSW_W            0
 109 #endif
 110 #define PSW_Z            0x40000000 /* PA1.x only */
 111 #define PSW_Y            0x80000000 /* PA1.x only */
 112
 113 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
 114                | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
 115
 116 /* ssm/rsm instructions number PSW_W and PSW_E differently */
 117 #define PSW_SM_I         PSW_I      /* Enable External Interrupts */
 118 #define PSW_SM_D         PSW_D
 119 #define PSW_SM_P         PSW_P
 120 #define PSW_SM_Q         PSW_Q      /* Enable Interrupt State Collection */
 121 #define PSW_SM_R         PSW_R      /* Enable Recover Counter Trap */
 122 #ifdef TARGET_HPPA64
 123 #define PSW_SM_E         0x100
 124 #define PSW_SM_W         0x200      /* PA2.0 only : Enable Wide Mode */
 125 #else
 126 #define PSW_SM_E         0
 127 #define PSW_SM_W         0
 128 #endif
 129
 130 #define CR_RC            0
 131 #define CR_PID1          8
 132 #define CR_PID2          9
 133 #define CR_PID3          12
 134 #define CR_PID4          13
 135 #define CR_SCRCCR        10
 136 #define CR_SAR           11
 137 #define CR_IVA           14
 138 #define CR_EIEM          15
 139 #define CR_IT            16
 140 #define CR_IIASQ         17
 141 #define CR_IIAOQ         18
 142 #define CR_IIR           19
 143 #define CR_ISR           20
 144 #define CR_IOR           21
 145 #define CR_IPSW          22
 146 #define CR_EIRR          23
 147
 148 #if TARGET_REGISTER_BITS == 32
 149 typedef uint32_t target_ureg;
 150 typedef int32_t  target_sreg;
 151 #define TREG_FMT_lx   "%08"PRIx32
 152 #define TREG_FMT_ld   "%"PRId32
 153 #else
 154 typedef uint64_t target_ureg;
 155 typedef int64_t  target_sreg;
 156 #define TREG_FMT_lx   "%016"PRIx64
 157 #define TREG_FMT_ld   "%"PRId64
 158 #endif
 159
 160 typedef struct {
 161     uint64_t va_b;
 162     uint64_t va_e;
 163     target_ureg pa;
 164     unsigned u : 1;
 165     unsigned t : 1;
 166     unsigned d : 1;
 167     unsigned b : 1;
 168     unsigned page_size : 4;
 169     unsigned ar_type : 3;
 170     unsigned ar_pl1 : 2;
 171     unsigned ar_pl2 : 2;
 172     unsigned entry_valid : 1;
 173     unsigned access_id : 16;
 174 } hppa_tlb_entry;
 175
 176 typedef struct CPUArchState {
 177     target_ureg iaoq_f;      /* front */
 178     target_ureg iaoq_b;      /* back, aka next instruction */
 179
 180     target_ureg gr[32];
 181     uint64_t fr[32];
 182     uint64_t sr[8];          /* stored shifted into place for gva */
 183
 184     target_ureg psw;         /* All psw bits except the following:  */
 185     target_ureg psw_n;       /* boolean */
 186     target_sreg psw_v;       /* in most significant bit */
 187
 188     /* Splitting the carry-borrow field into the MSB and "the rest", allows
 189      * for "the rest" to be deleted when it is unused, but the MSB is in use.
 190      * In addition, it's easier to compute carry-in for bit B+1 than it is to
 191      * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
 192      * host has the appropriate add-with-carry insn to compute the msb).
 193      * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
 194      */
 195     target_ureg psw_cb;      /* in least significant bit of next nibble */
 196     target_ureg psw_cb_msb;  /* boolean */
 197
 198     uint64_t iasq_f;
 199     uint64_t iasq_b;
 200
 201     uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
 202     float_status fp_status;
 203
 204     target_ureg cr[32];      /* control registers */
 205     target_ureg cr_back[2];  /* back of cr17/cr18 */
 206     target_ureg shadow[7];   /* shadow registers */
 207
 208     /* ??? The number of entries isn't specified by the architecture.  */
 209 #define HPPA_TLB_ENTRIES        256
 210 #define HPPA_BTLB_ENTRIES       0
 211
 212     /* ??? Implement a unified itlb/dtlb for the moment.  */
 213     /* ??? We should use a more intelligent data structure.  */
 214     hppa_tlb_entry tlb[HPPA_TLB_ENTRIES];
 215     uint32_t tlb_last;
 216 } CPUHPPAState;
 217
 218 /**
 219  * HPPACPU:
 220  * @env: #CPUHPPAState
 221  *
 222  * An HPPA CPU.
 223  */
 224 struct ArchCPU {
 225     /*< private >*/
 226     CPUState parent_obj;
 227     /*< public >*/
 228
 229     CPUNegativeOffsetState neg;
 230     CPUHPPAState env;
 231     QEMUTimer *alarm_timer;
 232 };
 233
 234 #include "exec/cpu-all.h"
 235
 236 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
 237 {
 238 #ifdef CONFIG_USER_ONLY
 239     return MMU_USER_IDX;
 240 #else
 241     if (env->psw & (ifetch ? PSW_C : PSW_D)) {
 242         return PRIV_TO_MMU_IDX(env->iaoq_f & 3);
 243     }
 244     return MMU_PHYS_IDX;  /* mmu disabled */
 245 #endif
 246 }
 247
 248 void hppa_translate_init(void);
 249
 250 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
 251
 252 static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
 253                                              target_ureg off)
 254 {
 255 #ifdef CONFIG_USER_ONLY
 256     return off;
 257 #else
 258     off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
 259     return spc | off;
 260 #endif
 261 }
 262
 263 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
 264                                          target_ureg off)
 265 {
 266     return hppa_form_gva_psw(env->psw, spc, off);
 267 }
 268
 269 /*
 270  * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
 271  * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
 272  * same value.
 273  */
 274 #define TB_FLAG_SR_SAME     PSW_I
 275 #define TB_FLAG_PRIV_SHIFT  8
 276 #define TB_FLAG_UNALIGN     0x400
 277
 278 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
 279                                         uint64_t *cs_base, uint32_t *pflags)
 280 {
 281     uint32_t flags = env->psw_n * PSW_N;
 282
 283     /* TB lookup assumes that PC contains the complete virtual address.
 284        If we leave space+offset separate, we'll get ITLB misses to an
 285        incomplete virtual address.  This also means that we must separate
 286        out current cpu privilege from the low bits of IAOQ_F.  */
 287 #ifdef CONFIG_USER_ONLY
 288     *pc = env->iaoq_f & -4;
 289     *cs_base = env->iaoq_b & -4;
 290     flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
 291 #else
 292     /* ??? E, T, H, L, B, P bits need to be here, when implemented.  */
 293     flags |= env->psw & (PSW_W | PSW_C | PSW_D);
 294     flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
 295
 296     *pc = (env->psw & PSW_C
 297            ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
 298            : env->iaoq_f & -4);
 299     *cs_base = env->iasq_f;
 300
 301     /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
 302        low 32-bits of CS_BASE.  This will succeed for all direct branches,
 303        which is the primary case we care about -- using goto_tb within a page.
 304        Failure is indicated by a zero difference.  */
 305     if (env->iasq_f == env->iasq_b) {
 306         target_sreg diff = env->iaoq_b - env->iaoq_f;
 307         if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
 308             *cs_base |= (uint32_t)diff;
 309         }
 310     }
 311     if ((env->sr[4] == env->sr[5])
 312         & (env->sr[4] == env->sr[6])
 313         & (env->sr[4] == env->sr[7])) {
 314         flags |= TB_FLAG_SR_SAME;
 315     }
 316 #endif
 317
 318     *pflags = flags;
 319 }
 320
 321 target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
 322 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
 323 void cpu_hppa_loaded_fr0(CPUHPPAState *env);
 324
 325 #ifdef CONFIG_USER_ONLY
 326 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
 327 #else
 328 void cpu_hppa_change_prot_id(CPUHPPAState *env);
 329 #endif
 330
 331 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 332 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 333 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
 334 #ifndef CONFIG_USER_ONLY
 335 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
 336 bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 337                        MMUAccessType access_type, int mmu_idx,
 338                        bool probe, uintptr_t retaddr);
 339 void hppa_cpu_do_interrupt(CPUState *cpu);
 340 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
 341 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
 342                               int type, hwaddr *pphys, int *pprot);
 343 extern const MemoryRegionOps hppa_io_eir_ops;
 344 extern const VMStateDescription vmstate_hppa_cpu;
 345 void hppa_cpu_alarm_timer(void *);
 346 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
 347 #endif
 348 G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
 349
 350 #endif /* HPPA_CPU_H */