target/hppa/cpu.h

   1 /*
   2  * PA-RISC emulation cpu definitions for qemu.
   3  *
   4  * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef HPPA_CPU_H
  21 #define HPPA_CPU_H
  22
  23 #include "cpu-qom.h"
  24 #include "exec/cpu-defs.h"
  25 #include "qemu/cpu-float.h"
  26 #include "qemu/interval-tree.h"
  27
  28 /* PA-RISC 1.x processors have a strong memory model.  */
  29 /* ??? While we do not yet implement PA-RISC 2.0, those processors have
  30    a weak memory model, but with TLB bits that force ordering on a per-page
  31    basis.  It's probably easier to fall back to a strong memory model.  */
  32 #define TCG_GUEST_DEFAULT_MO        TCG_MO_ALL
  33
  34 #define MMU_KERNEL_IDX    7
  35 #define MMU_KERNEL_P_IDX  8
  36 #define MMU_PL1_IDX       9
  37 #define MMU_PL1_P_IDX     10
  38 #define MMU_PL2_IDX       11
  39 #define MMU_PL2_P_IDX     12
  40 #define MMU_USER_IDX      13
  41 #define MMU_USER_P_IDX    14
  42 #define MMU_PHYS_IDX      15
  43
  44 #define MMU_IDX_TO_PRIV(MIDX)       (((MIDX) - MMU_KERNEL_IDX) / 2)
  45 #define MMU_IDX_TO_P(MIDX)          (((MIDX) - MMU_KERNEL_IDX) & 1)
  46 #define PRIV_P_TO_MMU_IDX(PRIV, P)  ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX)
  47
  48 #define TARGET_INSN_START_EXTRA_WORDS 1
  49
  50 /* No need to flush MMU_PHYS_IDX  */
  51 #define HPPA_MMU_FLUSH_MASK                             \
  52         (1 << MMU_KERNEL_IDX | 1 << MMU_KERNEL_P_IDX |  \
  53          1 << MMU_PL1_IDX    | 1 << MMU_PL1_P_IDX    |  \
  54          1 << MMU_PL2_IDX    | 1 << MMU_PL2_P_IDX    |  \
  55          1 << MMU_USER_IDX   | 1 << MMU_USER_P_IDX)
  56
  57 /* Indicies to flush for access_id changes. */
  58 #define HPPA_MMU_FLUSH_P_MASK \
  59         (1 << MMU_KERNEL_P_IDX | 1 << MMU_PL1_P_IDX  |  \
  60          1 << MMU_PL2_P_IDX    | 1 << MMU_USER_P_IDX)
  61
  62 /* Hardware exceptions, interrupts, faults, and traps.  */
  63 #define EXCP_HPMC                1  /* high priority machine check */
  64 #define EXCP_POWER_FAIL          2
  65 #define EXCP_RC                  3  /* recovery counter */
  66 #define EXCP_EXT_INTERRUPT       4  /* external interrupt */
  67 #define EXCP_LPMC                5  /* low priority machine check */
  68 #define EXCP_ITLB_MISS           6  /* itlb miss / instruction page fault */
  69 #define EXCP_IMP                 7  /* instruction memory protection trap */
  70 #define EXCP_ILL                 8  /* illegal instruction trap */
  71 #define EXCP_BREAK               9  /* break instruction */
  72 #define EXCP_PRIV_OPR            10 /* privileged operation trap */
  73 #define EXCP_PRIV_REG            11 /* privileged register trap */
  74 #define EXCP_OVERFLOW            12 /* signed overflow trap */
  75 #define EXCP_COND                13 /* trap-on-condition */
  76 #define EXCP_ASSIST              14 /* assist exception trap */
  77 #define EXCP_DTLB_MISS           15 /* dtlb miss / data page fault */
  78 #define EXCP_NA_ITLB_MISS        16 /* non-access itlb miss */
  79 #define EXCP_NA_DTLB_MISS        17 /* non-access dtlb miss */
  80 #define EXCP_DMP                 18 /* data memory protection trap */
  81 #define EXCP_DMB                 19 /* data memory break trap */
  82 #define EXCP_TLB_DIRTY           20 /* tlb dirty bit trap */
  83 #define EXCP_PAGE_REF            21 /* page reference trap */
  84 #define EXCP_ASSIST_EMU          22 /* assist emulation trap */
  85 #define EXCP_HPT                 23 /* high-privilege transfer trap */
  86 #define EXCP_LPT                 24 /* low-privilege transfer trap */
  87 #define EXCP_TB                  25 /* taken branch trap */
  88 #define EXCP_DMAR                26 /* data memory access rights trap */
  89 #define EXCP_DMPI                27 /* data memory protection id trap */
  90 #define EXCP_UNALIGN             28 /* unaligned data reference trap */
  91 #define EXCP_PER_INTERRUPT       29 /* performance monitor interrupt */
  92
  93 /* Exceptions for linux-user emulation.  */
  94 #define EXCP_SYSCALL             30
  95 #define EXCP_SYSCALL_LWS         31
  96
  97 /* Emulated hardware TOC button */
  98 #define EXCP_TOC                 32 /* TOC = Transfer of control (NMI) */
  99
 100 #define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3         /* TOC */
 101
 102 /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
 103 #define PSW_I            0x00000001
 104 #define PSW_D            0x00000002
 105 #define PSW_P            0x00000004
 106 #define PSW_Q            0x00000008
 107 #define PSW_R            0x00000010
 108 #define PSW_F            0x00000020
 109 #define PSW_G            0x00000040 /* PA1.x only */
 110 #define PSW_O            0x00000080 /* PA2.0 only */
 111 #define PSW_CB           0x0000ff00
 112 #define PSW_M            0x00010000
 113 #define PSW_V            0x00020000
 114 #define PSW_C            0x00040000
 115 #define PSW_B            0x00080000
 116 #define PSW_X            0x00100000
 117 #define PSW_N            0x00200000
 118 #define PSW_L            0x00400000
 119 #define PSW_H            0x00800000
 120 #define PSW_T            0x01000000
 121 #define PSW_S            0x02000000
 122 #define PSW_E            0x04000000
 123 #ifdef TARGET_HPPA64
 124 #define PSW_W            0x08000000 /* PA2.0 only */
 125 #else
 126 #define PSW_W            0
 127 #endif
 128 #define PSW_Z            0x40000000 /* PA1.x only */
 129 #define PSW_Y            0x80000000 /* PA1.x only */
 130
 131 #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \
 132                | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I)
 133
 134 /* ssm/rsm instructions number PSW_W and PSW_E differently */
 135 #define PSW_SM_I         PSW_I      /* Enable External Interrupts */
 136 #define PSW_SM_D         PSW_D
 137 #define PSW_SM_P         PSW_P
 138 #define PSW_SM_Q         PSW_Q      /* Enable Interrupt State Collection */
 139 #define PSW_SM_R         PSW_R      /* Enable Recover Counter Trap */
 140 #ifdef TARGET_HPPA64
 141 #define PSW_SM_E         0x100
 142 #define PSW_SM_W         0x200      /* PA2.0 only : Enable Wide Mode */
 143 #else
 144 #define PSW_SM_E         0
 145 #define PSW_SM_W         0
 146 #endif
 147
 148 #define CR_RC            0
 149 #define CR_PID1          8
 150 #define CR_PID2          9
 151 #define CR_PID3          12
 152 #define CR_PID4          13
 153 #define CR_SCRCCR        10
 154 #define CR_SAR           11
 155 #define CR_IVA           14
 156 #define CR_EIEM          15
 157 #define CR_IT            16
 158 #define CR_IIASQ         17
 159 #define CR_IIAOQ         18
 160 #define CR_IIR           19
 161 #define CR_ISR           20
 162 #define CR_IOR           21
 163 #define CR_IPSW          22
 164 #define CR_EIRR          23
 165
 166 #if TARGET_REGISTER_BITS == 32
 167 typedef uint32_t target_ureg;
 168 typedef int32_t  target_sreg;
 169 #define TREG_FMT_lx   "%08"PRIx32
 170 #define TREG_FMT_ld   "%"PRId32
 171 #else
 172 typedef uint64_t target_ureg;
 173 typedef int64_t  target_sreg;
 174 #define TREG_FMT_lx   "%016"PRIx64
 175 #define TREG_FMT_ld   "%"PRId64
 176 #endif
 177
 178 typedef struct HPPATLBEntry {
 179     union {
 180         IntervalTreeNode itree;
 181         struct HPPATLBEntry *unused_next;
 182     };
 183
 184     target_ureg pa;
 185
 186     unsigned entry_valid : 1;
 187
 188     unsigned u : 1;
 189     unsigned t : 1;
 190     unsigned d : 1;
 191     unsigned b : 1;
 192     unsigned ar_type : 3;
 193     unsigned ar_pl1 : 2;
 194     unsigned ar_pl2 : 2;
 195     unsigned access_id : 16;
 196 } HPPATLBEntry;
 197
 198 typedef struct CPUArchState {
 199     target_ureg iaoq_f;      /* front */
 200     target_ureg iaoq_b;      /* back, aka next instruction */
 201
 202     target_ureg gr[32];
 203     uint64_t fr[32];
 204     uint64_t sr[8];          /* stored shifted into place for gva */
 205
 206     target_ureg psw;         /* All psw bits except the following:  */
 207     target_ureg psw_n;       /* boolean */
 208     target_sreg psw_v;       /* in most significant bit */
 209
 210     /* Splitting the carry-borrow field into the MSB and "the rest", allows
 211      * for "the rest" to be deleted when it is unused, but the MSB is in use.
 212      * In addition, it's easier to compute carry-in for bit B+1 than it is to
 213      * compute carry-out for bit B (3 vs 4 insns for addition, assuming the
 214      * host has the appropriate add-with-carry insn to compute the msb).
 215      * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110.
 216      */
 217     target_ureg psw_cb;      /* in least significant bit of next nibble */
 218     target_ureg psw_cb_msb;  /* boolean */
 219
 220     uint64_t iasq_f;
 221     uint64_t iasq_b;
 222
 223     uint32_t fr0_shadow;     /* flags, c, ca/cq, rm, d, enables */
 224     float_status fp_status;
 225
 226     target_ureg cr[32];      /* control registers */
 227     target_ureg cr_back[2];  /* back of cr17/cr18 */
 228     target_ureg shadow[7];   /* shadow registers */
 229
 230     /* ??? The number of entries isn't specified by the architecture.  */
 231 #ifdef TARGET_HPPA64
 232 #define HPPA_BTLB_FIXED         0       /* BTLBs are not supported in 64-bit machines */
 233 #else
 234 #define HPPA_BTLB_FIXED         16
 235 #endif
 236 #define HPPA_BTLB_VARIABLE      0
 237 #define HPPA_TLB_ENTRIES        256
 238 #define HPPA_BTLB_ENTRIES       (HPPA_BTLB_FIXED + HPPA_BTLB_VARIABLE)
 239
 240     /* Index for round-robin tlb eviction. */
 241     uint32_t tlb_last;
 242
 243     /*
 244      * For pa1.x, the partial initialized, still invalid tlb entry
 245      * which has had ITLBA performed, but not yet ITLBP.
 246      */
 247     HPPATLBEntry *tlb_partial;
 248
 249     /* Linked list of all invalid (unused) tlb entries. */
 250     HPPATLBEntry *tlb_unused;
 251
 252     /* Root of the search tree for all valid tlb entries. */
 253     IntervalTreeRoot tlb_root;
 254
 255     HPPATLBEntry tlb[HPPA_TLB_ENTRIES];
 256 } CPUHPPAState;
 257
 258 /**
 259  * HPPACPU:
 260  * @env: #CPUHPPAState
 261  *
 262  * An HPPA CPU.
 263  */
 264 struct ArchCPU {
 265     /*< private >*/
 266     CPUState parent_obj;
 267     /*< public >*/
 268
 269     CPUHPPAState env;
 270     QEMUTimer *alarm_timer;
 271 };
 272
 273 #include "exec/cpu-all.h"
 274
 275 static inline bool hppa_is_pa20(CPUHPPAState *env)
 276 {
 277     return object_dynamic_cast(OBJECT(env_cpu(env)), TYPE_HPPA64_CPU) != NULL;
 278 }
 279
 280 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
 281 {
 282 #ifdef CONFIG_USER_ONLY
 283     return MMU_USER_IDX;
 284 #else
 285     if (env->psw & (ifetch ? PSW_C : PSW_D)) {
 286         return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P);
 287     }
 288     return MMU_PHYS_IDX;  /* mmu disabled */
 289 #endif
 290 }
 291
 292 void hppa_translate_init(void);
 293
 294 #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
 295
 296 static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc,
 297                                              target_ureg off)
 298 {
 299 #ifdef CONFIG_USER_ONLY
 300     return off;
 301 #else
 302     off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull);
 303     return spc | off;
 304 #endif
 305 }
 306
 307 static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
 308                                          target_ureg off)
 309 {
 310     return hppa_form_gva_psw(env->psw, spc, off);
 311 }
 312
 313 /*
 314  * Since PSW_{I,CB} will never need to be in tb->flags, reuse them.
 315  * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the
 316  * same value.
 317  */
 318 #define TB_FLAG_SR_SAME     PSW_I
 319 #define TB_FLAG_PRIV_SHIFT  8
 320 #define TB_FLAG_UNALIGN     0x400
 321
 322 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
 323                                         uint64_t *cs_base, uint32_t *pflags)
 324 {
 325     uint32_t flags = env->psw_n * PSW_N;
 326
 327     /* TB lookup assumes that PC contains the complete virtual address.
 328        If we leave space+offset separate, we'll get ITLB misses to an
 329        incomplete virtual address.  This also means that we must separate
 330        out current cpu privilege from the low bits of IAOQ_F.  */
 331 #ifdef CONFIG_USER_ONLY
 332     *pc = env->iaoq_f & -4;
 333     *cs_base = env->iaoq_b & -4;
 334     flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
 335 #else
 336     /* ??? E, T, H, L, B bits need to be here, when implemented.  */
 337     flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P);
 338     flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
 339
 340     *pc = (env->psw & PSW_C
 341            ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
 342            : env->iaoq_f & -4);
 343     *cs_base = env->iasq_f;
 344
 345     /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
 346        low 32-bits of CS_BASE.  This will succeed for all direct branches,
 347        which is the primary case we care about -- using goto_tb within a page.
 348        Failure is indicated by a zero difference.  */
 349     if (env->iasq_f == env->iasq_b) {
 350         target_sreg diff = env->iaoq_b - env->iaoq_f;
 351         if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
 352             *cs_base |= (uint32_t)diff;
 353         }
 354     }
 355     if ((env->sr[4] == env->sr[5])
 356         & (env->sr[4] == env->sr[6])
 357         & (env->sr[4] == env->sr[7])) {
 358         flags |= TB_FLAG_SR_SAME;
 359     }
 360 #endif
 361
 362     *pflags = flags;
 363 }
 364
 365 target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
 366 void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
 367 void cpu_hppa_loaded_fr0(CPUHPPAState *env);
 368
 369 #ifdef CONFIG_USER_ONLY
 370 static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { }
 371 #else
 372 void cpu_hppa_change_prot_id(CPUHPPAState *env);
 373 #endif
 374
 375 int hppa_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 376 int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 377 void hppa_cpu_dump_state(CPUState *cs, FILE *f, int);
 378 #ifndef CONFIG_USER_ONLY
 379 void hppa_ptlbe(CPUHPPAState *env);
 380 hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr);
 381 bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
 382                        MMUAccessType access_type, int mmu_idx,
 383                        bool probe, uintptr_t retaddr);
 384 void hppa_cpu_do_interrupt(CPUState *cpu);
 385 bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req);
 386 int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
 387                               int type, hwaddr *pphys, int *pprot,
 388                               HPPATLBEntry **tlb_entry);
 389 extern const MemoryRegionOps hppa_io_eir_ops;
 390 extern const VMStateDescription vmstate_hppa_cpu;
 391 void hppa_cpu_alarm_timer(void *);
 392 int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
 393 #endif
 394 G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
 395
 396 #endif /* HPPA_CPU_H */