2 * Helpers for HPPA instructions.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "exec/cpu_ldst.h"
25 #include "sysemu/sysemu.h"
26 #include "qemu/timer.h"
27 #include "fpu/softfloat.h"
30 void QEMU_NORETURN
HELPER(excp
)(CPUHPPAState
*env
, int excp
)
32 HPPACPU
*cpu
= hppa_env_get_cpu(env
);
33 CPUState
*cs
= CPU(cpu
);
35 cs
->exception_index
= excp
;
39 void QEMU_NORETURN
hppa_dynamic_excp(CPUHPPAState
*env
, int excp
, uintptr_t ra
)
41 HPPACPU
*cpu
= hppa_env_get_cpu(env
);
42 CPUState
*cs
= CPU(cpu
);
44 cs
->exception_index
= excp
;
45 cpu_loop_exit_restore(cs
, ra
);
48 void HELPER(tsv
)(CPUHPPAState
*env
, target_ureg cond
)
50 if (unlikely((target_sreg
)cond
< 0)) {
51 hppa_dynamic_excp(env
, EXCP_OVERFLOW
, GETPC());
55 void HELPER(tcond
)(CPUHPPAState
*env
, target_ureg cond
)
58 hppa_dynamic_excp(env
, EXCP_COND
, GETPC());
62 static void atomic_store_3(CPUHPPAState
*env
, target_ulong addr
, uint32_t val
,
63 uint32_t mask
, uintptr_t ra
)
65 #ifdef CONFIG_USER_ONLY
66 uint32_t old
, new, cmp
;
68 uint32_t *haddr
= g2h(addr
- 1);
71 new = (old
& ~mask
) | (val
& mask
);
72 cmp
= atomic_cmpxchg(haddr
, old
, new);
79 /* FIXME -- we can do better. */
80 cpu_loop_exit_atomic(ENV_GET_CPU(env
), ra
);
84 static void do_stby_b(CPUHPPAState
*env
, target_ulong addr
, target_ureg val
,
85 bool parallel
, uintptr_t ra
)
89 cpu_stb_data_ra(env
, addr
, val
, ra
);
92 cpu_stw_data_ra(env
, addr
, val
, ra
);
95 /* The 3 byte store must appear atomic. */
97 atomic_store_3(env
, addr
, val
, 0x00ffffffu
, ra
);
99 cpu_stb_data_ra(env
, addr
, val
>> 16, ra
);
100 cpu_stw_data_ra(env
, addr
+ 1, val
, ra
);
104 cpu_stl_data_ra(env
, addr
, val
, ra
);
109 void HELPER(stby_b
)(CPUHPPAState
*env
, target_ulong addr
, target_ureg val
)
111 do_stby_b(env
, addr
, val
, false, GETPC());
114 void HELPER(stby_b_parallel
)(CPUHPPAState
*env
, target_ulong addr
,
117 do_stby_b(env
, addr
, val
, true, GETPC());
120 static void do_stby_e(CPUHPPAState
*env
, target_ulong addr
, target_ureg val
,
121 bool parallel
, uintptr_t ra
)
125 /* The 3 byte store must appear atomic. */
127 atomic_store_3(env
, addr
- 3, val
, 0xffffff00u
, ra
);
129 cpu_stw_data_ra(env
, addr
- 3, val
>> 16, ra
);
130 cpu_stb_data_ra(env
, addr
- 1, val
>> 8, ra
);
134 cpu_stw_data_ra(env
, addr
- 2, val
>> 16, ra
);
137 cpu_stb_data_ra(env
, addr
- 1, val
>> 24, ra
);
140 /* Nothing is stored, but protection is checked and the
141 cacheline is marked dirty. */
142 #ifndef CONFIG_USER_ONLY
143 probe_write(env
, addr
, 0, cpu_mmu_index(env
, 0), ra
);
149 void HELPER(stby_e
)(CPUHPPAState
*env
, target_ulong addr
, target_ureg val
)
151 do_stby_e(env
, addr
, val
, false, GETPC());
154 void HELPER(stby_e_parallel
)(CPUHPPAState
*env
, target_ulong addr
,
157 do_stby_e(env
, addr
, val
, true, GETPC());
160 target_ureg
HELPER(probe
)(CPUHPPAState
*env
, target_ulong addr
,
161 uint32_t level
, uint32_t want
)
163 #ifdef CONFIG_USER_ONLY
164 return page_check_range(addr
, 1, want
);
169 trace_hppa_tlb_probe(addr
, level
, want
);
170 /* Fail if the requested privilege level is higher than current. */
171 if (level
< (env
->iaoq_f
& 3)) {
175 excp
= hppa_get_physical_address(env
, addr
, level
, 0, &phys
, &prot
);
177 if (env
->psw
& PSW_Q
) {
178 /* ??? Needs tweaking for hppa64. */
179 env
->cr
[CR_IOR
] = addr
;
180 env
->cr
[CR_ISR
] = addr
>> 32;
182 if (excp
== EXCP_DTLB_MISS
) {
183 excp
= EXCP_NA_DTLB_MISS
;
185 hppa_dynamic_excp(env
, excp
, GETPC());
187 return (want
& prot
) != 0;
191 void HELPER(loaded_fr0
)(CPUHPPAState
*env
)
193 uint32_t shadow
= env
->fr
[0] >> 32;
196 env
->fr0_shadow
= shadow
;
198 switch (extract32(shadow
, 9, 2)) {
200 rm
= float_round_nearest_even
;
203 rm
= float_round_to_zero
;
209 rm
= float_round_down
;
212 set_float_rounding_mode(rm
, &env
->fp_status
);
214 d
= extract32(shadow
, 5, 1);
215 set_flush_to_zero(d
, &env
->fp_status
);
216 set_flush_inputs_to_zero(d
, &env
->fp_status
);
219 void cpu_hppa_loaded_fr0(CPUHPPAState
*env
)
221 helper_loaded_fr0(env
);
224 #define CONVERT_BIT(X, SRC, DST) \
226 ? (X) / ((SRC) / (DST)) & (DST) \
227 : ((X) & (SRC)) * ((DST) / (SRC)))
229 static void update_fr0_op(CPUHPPAState
*env
, uintptr_t ra
)
231 uint32_t soft_exp
= get_float_exception_flags(&env
->fp_status
);
232 uint32_t hard_exp
= 0;
233 uint32_t shadow
= env
->fr0_shadow
;
235 if (likely(soft_exp
== 0)) {
236 env
->fr
[0] = (uint64_t)shadow
<< 32;
239 set_float_exception_flags(0, &env
->fp_status
);
241 hard_exp
|= CONVERT_BIT(soft_exp
, float_flag_inexact
, 1u << 0);
242 hard_exp
|= CONVERT_BIT(soft_exp
, float_flag_underflow
, 1u << 1);
243 hard_exp
|= CONVERT_BIT(soft_exp
, float_flag_overflow
, 1u << 2);
244 hard_exp
|= CONVERT_BIT(soft_exp
, float_flag_divbyzero
, 1u << 3);
245 hard_exp
|= CONVERT_BIT(soft_exp
, float_flag_invalid
, 1u << 4);
246 shadow
|= hard_exp
<< (32 - 5);
247 env
->fr0_shadow
= shadow
;
248 env
->fr
[0] = (uint64_t)shadow
<< 32;
250 if (hard_exp
& shadow
) {
251 hppa_dynamic_excp(env
, EXCP_ASSIST
, ra
);
255 float32
HELPER(fsqrt_s
)(CPUHPPAState
*env
, float32 arg
)
257 float32 ret
= float32_sqrt(arg
, &env
->fp_status
);
258 update_fr0_op(env
, GETPC());
262 float32
HELPER(frnd_s
)(CPUHPPAState
*env
, float32 arg
)
264 float32 ret
= float32_round_to_int(arg
, &env
->fp_status
);
265 update_fr0_op(env
, GETPC());
269 float32
HELPER(fadd_s
)(CPUHPPAState
*env
, float32 a
, float32 b
)
271 float32 ret
= float32_add(a
, b
, &env
->fp_status
);
272 update_fr0_op(env
, GETPC());
276 float32
HELPER(fsub_s
)(CPUHPPAState
*env
, float32 a
, float32 b
)
278 float32 ret
= float32_sub(a
, b
, &env
->fp_status
);
279 update_fr0_op(env
, GETPC());
283 float32
HELPER(fmpy_s
)(CPUHPPAState
*env
, float32 a
, float32 b
)
285 float32 ret
= float32_mul(a
, b
, &env
->fp_status
);
286 update_fr0_op(env
, GETPC());
290 float32
HELPER(fdiv_s
)(CPUHPPAState
*env
, float32 a
, float32 b
)
292 float32 ret
= float32_div(a
, b
, &env
->fp_status
);
293 update_fr0_op(env
, GETPC());
297 float64
HELPER(fsqrt_d
)(CPUHPPAState
*env
, float64 arg
)
299 float64 ret
= float64_sqrt(arg
, &env
->fp_status
);
300 update_fr0_op(env
, GETPC());
304 float64
HELPER(frnd_d
)(CPUHPPAState
*env
, float64 arg
)
306 float64 ret
= float64_round_to_int(arg
, &env
->fp_status
);
307 update_fr0_op(env
, GETPC());
311 float64
HELPER(fadd_d
)(CPUHPPAState
*env
, float64 a
, float64 b
)
313 float64 ret
= float64_add(a
, b
, &env
->fp_status
);
314 update_fr0_op(env
, GETPC());
318 float64
HELPER(fsub_d
)(CPUHPPAState
*env
, float64 a
, float64 b
)
320 float64 ret
= float64_sub(a
, b
, &env
->fp_status
);
321 update_fr0_op(env
, GETPC());
325 float64
HELPER(fmpy_d
)(CPUHPPAState
*env
, float64 a
, float64 b
)
327 float64 ret
= float64_mul(a
, b
, &env
->fp_status
);
328 update_fr0_op(env
, GETPC());
332 float64
HELPER(fdiv_d
)(CPUHPPAState
*env
, float64 a
, float64 b
)
334 float64 ret
= float64_div(a
, b
, &env
->fp_status
);
335 update_fr0_op(env
, GETPC());
339 float64
HELPER(fcnv_s_d
)(CPUHPPAState
*env
, float32 arg
)
341 float64 ret
= float32_to_float64(arg
, &env
->fp_status
);
342 update_fr0_op(env
, GETPC());
346 float32
HELPER(fcnv_d_s
)(CPUHPPAState
*env
, float64 arg
)
348 float32 ret
= float64_to_float32(arg
, &env
->fp_status
);
349 update_fr0_op(env
, GETPC());
353 float32
HELPER(fcnv_w_s
)(CPUHPPAState
*env
, int32_t arg
)
355 float32 ret
= int32_to_float32(arg
, &env
->fp_status
);
356 update_fr0_op(env
, GETPC());
360 float32
HELPER(fcnv_dw_s
)(CPUHPPAState
*env
, int64_t arg
)
362 float32 ret
= int64_to_float32(arg
, &env
->fp_status
);
363 update_fr0_op(env
, GETPC());
367 float64
HELPER(fcnv_w_d
)(CPUHPPAState
*env
, int32_t arg
)
369 float64 ret
= int32_to_float64(arg
, &env
->fp_status
);
370 update_fr0_op(env
, GETPC());
374 float64
HELPER(fcnv_dw_d
)(CPUHPPAState
*env
, int64_t arg
)
376 float64 ret
= int64_to_float64(arg
, &env
->fp_status
);
377 update_fr0_op(env
, GETPC());
381 int32_t HELPER(fcnv_s_w
)(CPUHPPAState
*env
, float32 arg
)
383 int32_t ret
= float32_to_int32(arg
, &env
->fp_status
);
384 update_fr0_op(env
, GETPC());
388 int32_t HELPER(fcnv_d_w
)(CPUHPPAState
*env
, float64 arg
)
390 int32_t ret
= float64_to_int32(arg
, &env
->fp_status
);
391 update_fr0_op(env
, GETPC());
395 int64_t HELPER(fcnv_s_dw
)(CPUHPPAState
*env
, float32 arg
)
397 int64_t ret
= float32_to_int64(arg
, &env
->fp_status
);
398 update_fr0_op(env
, GETPC());
402 int64_t HELPER(fcnv_d_dw
)(CPUHPPAState
*env
, float64 arg
)
404 int64_t ret
= float64_to_int64(arg
, &env
->fp_status
);
405 update_fr0_op(env
, GETPC());
409 int32_t HELPER(fcnv_t_s_w
)(CPUHPPAState
*env
, float32 arg
)
411 int32_t ret
= float32_to_int32_round_to_zero(arg
, &env
->fp_status
);
412 update_fr0_op(env
, GETPC());
416 int32_t HELPER(fcnv_t_d_w
)(CPUHPPAState
*env
, float64 arg
)
418 int32_t ret
= float64_to_int32_round_to_zero(arg
, &env
->fp_status
);
419 update_fr0_op(env
, GETPC());
423 int64_t HELPER(fcnv_t_s_dw
)(CPUHPPAState
*env
, float32 arg
)
425 int64_t ret
= float32_to_int64_round_to_zero(arg
, &env
->fp_status
);
426 update_fr0_op(env
, GETPC());
430 int64_t HELPER(fcnv_t_d_dw
)(CPUHPPAState
*env
, float64 arg
)
432 int64_t ret
= float64_to_int64_round_to_zero(arg
, &env
->fp_status
);
433 update_fr0_op(env
, GETPC());
437 float32
HELPER(fcnv_uw_s
)(CPUHPPAState
*env
, uint32_t arg
)
439 float32 ret
= uint32_to_float32(arg
, &env
->fp_status
);
440 update_fr0_op(env
, GETPC());
444 float32
HELPER(fcnv_udw_s
)(CPUHPPAState
*env
, uint64_t arg
)
446 float32 ret
= uint64_to_float32(arg
, &env
->fp_status
);
447 update_fr0_op(env
, GETPC());
451 float64
HELPER(fcnv_uw_d
)(CPUHPPAState
*env
, uint32_t arg
)
453 float64 ret
= uint32_to_float64(arg
, &env
->fp_status
);
454 update_fr0_op(env
, GETPC());
458 float64
HELPER(fcnv_udw_d
)(CPUHPPAState
*env
, uint64_t arg
)
460 float64 ret
= uint64_to_float64(arg
, &env
->fp_status
);
461 update_fr0_op(env
, GETPC());
465 uint32_t HELPER(fcnv_s_uw
)(CPUHPPAState
*env
, float32 arg
)
467 uint32_t ret
= float32_to_uint32(arg
, &env
->fp_status
);
468 update_fr0_op(env
, GETPC());
472 uint32_t HELPER(fcnv_d_uw
)(CPUHPPAState
*env
, float64 arg
)
474 uint32_t ret
= float64_to_uint32(arg
, &env
->fp_status
);
475 update_fr0_op(env
, GETPC());
479 uint64_t HELPER(fcnv_s_udw
)(CPUHPPAState
*env
, float32 arg
)
481 uint64_t ret
= float32_to_uint64(arg
, &env
->fp_status
);
482 update_fr0_op(env
, GETPC());
486 uint64_t HELPER(fcnv_d_udw
)(CPUHPPAState
*env
, float64 arg
)
488 uint64_t ret
= float64_to_uint64(arg
, &env
->fp_status
);
489 update_fr0_op(env
, GETPC());
493 uint32_t HELPER(fcnv_t_s_uw
)(CPUHPPAState
*env
, float32 arg
)
495 uint32_t ret
= float32_to_uint32_round_to_zero(arg
, &env
->fp_status
);
496 update_fr0_op(env
, GETPC());
500 uint32_t HELPER(fcnv_t_d_uw
)(CPUHPPAState
*env
, float64 arg
)
502 uint32_t ret
= float64_to_uint32_round_to_zero(arg
, &env
->fp_status
);
503 update_fr0_op(env
, GETPC());
507 uint64_t HELPER(fcnv_t_s_udw
)(CPUHPPAState
*env
, float32 arg
)
509 uint64_t ret
= float32_to_uint64_round_to_zero(arg
, &env
->fp_status
);
510 update_fr0_op(env
, GETPC());
514 uint64_t HELPER(fcnv_t_d_udw
)(CPUHPPAState
*env
, float64 arg
)
516 uint64_t ret
= float64_to_uint64_round_to_zero(arg
, &env
->fp_status
);
517 update_fr0_op(env
, GETPC());
521 static void update_fr0_cmp(CPUHPPAState
*env
, uint32_t y
, uint32_t c
, int r
)
523 uint32_t shadow
= env
->fr0_shadow
;
526 case float_relation_greater
:
527 c
= extract32(c
, 4, 1);
529 case float_relation_less
:
530 c
= extract32(c
, 3, 1);
532 case float_relation_equal
:
533 c
= extract32(c
, 2, 1);
535 case float_relation_unordered
:
536 c
= extract32(c
, 1, 1);
539 g_assert_not_reached();
543 /* targeted comparison */
544 /* set fpsr[ca[y - 1]] to current compare */
545 shadow
= deposit32(shadow
, 21 - (y
- 1), 1, c
);
547 /* queued comparison */
548 /* shift cq right by one place */
549 shadow
= deposit32(shadow
, 11, 10, extract32(shadow
, 12, 10));
550 /* move fpsr[c] to fpsr[cq[0]] */
551 shadow
= deposit32(shadow
, 21, 1, extract32(shadow
, 26, 1));
552 /* set fpsr[c] to current compare */
553 shadow
= deposit32(shadow
, 26, 1, c
);
556 env
->fr0_shadow
= shadow
;
557 env
->fr
[0] = (uint64_t)shadow
<< 32;
560 void HELPER(fcmp_s
)(CPUHPPAState
*env
, float32 a
, float32 b
,
561 uint32_t y
, uint32_t c
)
565 r
= float32_compare(a
, b
, &env
->fp_status
);
567 r
= float32_compare_quiet(a
, b
, &env
->fp_status
);
569 update_fr0_op(env
, GETPC());
570 update_fr0_cmp(env
, y
, c
, r
);
573 void HELPER(fcmp_d
)(CPUHPPAState
*env
, float64 a
, float64 b
,
574 uint32_t y
, uint32_t c
)
578 r
= float64_compare(a
, b
, &env
->fp_status
);
580 r
= float64_compare_quiet(a
, b
, &env
->fp_status
);
582 update_fr0_op(env
, GETPC());
583 update_fr0_cmp(env
, y
, c
, r
);
586 float32
HELPER(fmpyfadd_s
)(CPUHPPAState
*env
, float32 a
, float32 b
, float32 c
)
588 float32 ret
= float32_muladd(a
, b
, c
, 0, &env
->fp_status
);
589 update_fr0_op(env
, GETPC());
593 float32
HELPER(fmpynfadd_s
)(CPUHPPAState
*env
, float32 a
, float32 b
, float32 c
)
595 float32 ret
= float32_muladd(a
, b
, c
, float_muladd_negate_product
,
597 update_fr0_op(env
, GETPC());
601 float64
HELPER(fmpyfadd_d
)(CPUHPPAState
*env
, float64 a
, float64 b
, float64 c
)
603 float64 ret
= float64_muladd(a
, b
, c
, 0, &env
->fp_status
);
604 update_fr0_op(env
, GETPC());
608 float64
HELPER(fmpynfadd_d
)(CPUHPPAState
*env
, float64 a
, float64 b
, float64 c
)
610 float64 ret
= float64_muladd(a
, b
, c
, float_muladd_negate_product
,
612 update_fr0_op(env
, GETPC());
616 target_ureg
HELPER(read_interval_timer
)(void)
618 #ifdef CONFIG_USER_ONLY
619 /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist.
620 Just pass through the host cpu clock ticks. */
621 return cpu_get_host_ticks();
623 /* In system mode we have access to a decent high-resolution clock.
624 In order to make OS-level time accounting work with the cr16,
625 present it with a well-timed clock fixed at 250MHz. */
626 return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) >> 2;
630 #ifndef CONFIG_USER_ONLY
631 void HELPER(write_interval_timer
)(CPUHPPAState
*env
, target_ureg val
)
633 HPPACPU
*cpu
= hppa_env_get_cpu(env
);
634 uint64_t current
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
637 /* Even in 64-bit mode, the comparator is always 32-bit. But the
638 value we expose to the guest is 1/4 of the speed of the clock,
639 so moosh in 34 bits. */
640 timeout
= deposit64(current
, 0, 34, (uint64_t)val
<< 2);
642 /* If the mooshing puts the clock in the past, advance to next round. */
643 if (timeout
< current
+ 1000) {
644 timeout
+= 1ULL << 34;
647 cpu
->env
.cr
[CR_IT
] = timeout
;
648 timer_mod(cpu
->alarm_timer
, timeout
);
651 void HELPER(halt
)(CPUHPPAState
*env
)
653 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
654 helper_excp(env
, EXCP_HLT
);
657 void HELPER(reset
)(CPUHPPAState
*env
)
659 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
660 helper_excp(env
, EXCP_HLT
);
663 target_ureg
HELPER(swap_system_mask
)(CPUHPPAState
*env
, target_ureg nsm
)
665 target_ulong psw
= env
->psw
;
667 * Setting the PSW Q bit to 1, if it was not already 1, is an
668 * undefined operation.
670 * However, HP-UX 10.20 does this with the SSM instruction.
671 * Tested this on HP9000/712 and HP9000/785/C3750 and both
672 * machines set the Q bit from 0 to 1 without an exception,
673 * so let this go without comment.
675 env
->psw
= (psw
& ~PSW_SM
) | (nsm
& PSW_SM
);
679 void HELPER(rfi
)(CPUHPPAState
*env
)
681 env
->iasq_f
= (uint64_t)env
->cr
[CR_IIASQ
] << 32;
682 env
->iasq_b
= (uint64_t)env
->cr_back
[0] << 32;
683 env
->iaoq_f
= env
->cr
[CR_IIAOQ
];
684 env
->iaoq_b
= env
->cr_back
[1];
685 cpu_hppa_put_psw(env
, env
->cr
[CR_IPSW
]);
688 void HELPER(rfi_r
)(CPUHPPAState
*env
)
690 env
->gr
[1] = env
->shadow
[0];
691 env
->gr
[8] = env
->shadow
[1];
692 env
->gr
[9] = env
->shadow
[2];
693 env
->gr
[16] = env
->shadow
[3];
694 env
->gr
[17] = env
->shadow
[4];
695 env
->gr
[24] = env
->shadow
[5];
696 env
->gr
[25] = env
->shadow
[6];