2 * HPPA emulation cpu translation for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "disas/disas.h"
23 #include "qemu/host-utils.h"
24 #include "exec/exec-all.h"
26 #include "exec/cpu_ldst.h"
27 #include "exec/helper-proto.h"
28 #include "exec/helper-gen.h"
29 #include "exec/translator.h"
30 #include "trace-tcg.h"
33 /* Since we have a distinction between register size and address size,
34 we need to redefine all of these. */
38 #undef tcg_global_reg_new
39 #undef tcg_global_mem_new
40 #undef tcg_temp_local_new
43 #if TARGET_LONG_BITS == 64
44 #define TCGv_tl TCGv_i64
45 #define tcg_temp_new_tl tcg_temp_new_i64
46 #define tcg_temp_free_tl tcg_temp_free_i64
47 #if TARGET_REGISTER_BITS == 64
48 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64
50 #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
53 #define TCGv_tl TCGv_i32
54 #define tcg_temp_new_tl tcg_temp_new_i32
55 #define tcg_temp_free_tl tcg_temp_free_i32
56 #define tcg_gen_extu_reg_tl tcg_gen_mov_i32
59 #if TARGET_REGISTER_BITS == 64
60 #define TCGv_reg TCGv_i64
62 #define tcg_temp_new tcg_temp_new_i64
63 #define tcg_global_reg_new tcg_global_reg_new_i64
64 #define tcg_global_mem_new tcg_global_mem_new_i64
65 #define tcg_temp_local_new tcg_temp_local_new_i64
66 #define tcg_temp_free tcg_temp_free_i64
68 #define tcg_gen_movi_reg tcg_gen_movi_i64
69 #define tcg_gen_mov_reg tcg_gen_mov_i64
70 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
71 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
72 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
73 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
74 #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
75 #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
76 #define tcg_gen_ld_reg tcg_gen_ld_i64
77 #define tcg_gen_st8_reg tcg_gen_st8_i64
78 #define tcg_gen_st16_reg tcg_gen_st16_i64
79 #define tcg_gen_st32_reg tcg_gen_st32_i64
80 #define tcg_gen_st_reg tcg_gen_st_i64
81 #define tcg_gen_add_reg tcg_gen_add_i64
82 #define tcg_gen_addi_reg tcg_gen_addi_i64
83 #define tcg_gen_sub_reg tcg_gen_sub_i64
84 #define tcg_gen_neg_reg tcg_gen_neg_i64
85 #define tcg_gen_subfi_reg tcg_gen_subfi_i64
86 #define tcg_gen_subi_reg tcg_gen_subi_i64
87 #define tcg_gen_and_reg tcg_gen_and_i64
88 #define tcg_gen_andi_reg tcg_gen_andi_i64
89 #define tcg_gen_or_reg tcg_gen_or_i64
90 #define tcg_gen_ori_reg tcg_gen_ori_i64
91 #define tcg_gen_xor_reg tcg_gen_xor_i64
92 #define tcg_gen_xori_reg tcg_gen_xori_i64
93 #define tcg_gen_not_reg tcg_gen_not_i64
94 #define tcg_gen_shl_reg tcg_gen_shl_i64
95 #define tcg_gen_shli_reg tcg_gen_shli_i64
96 #define tcg_gen_shr_reg tcg_gen_shr_i64
97 #define tcg_gen_shri_reg tcg_gen_shri_i64
98 #define tcg_gen_sar_reg tcg_gen_sar_i64
99 #define tcg_gen_sari_reg tcg_gen_sari_i64
100 #define tcg_gen_brcond_reg tcg_gen_brcond_i64
101 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
102 #define tcg_gen_setcond_reg tcg_gen_setcond_i64
103 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
104 #define tcg_gen_mul_reg tcg_gen_mul_i64
105 #define tcg_gen_muli_reg tcg_gen_muli_i64
106 #define tcg_gen_div_reg tcg_gen_div_i64
107 #define tcg_gen_rem_reg tcg_gen_rem_i64
108 #define tcg_gen_divu_reg tcg_gen_divu_i64
109 #define tcg_gen_remu_reg tcg_gen_remu_i64
110 #define tcg_gen_discard_reg tcg_gen_discard_i64
111 #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
112 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
113 #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
114 #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
115 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
116 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
117 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
118 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
119 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
120 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
121 #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
122 #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
123 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
124 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
125 #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
126 #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
127 #define tcg_gen_andc_reg tcg_gen_andc_i64
128 #define tcg_gen_eqv_reg tcg_gen_eqv_i64
129 #define tcg_gen_nand_reg tcg_gen_nand_i64
130 #define tcg_gen_nor_reg tcg_gen_nor_i64
131 #define tcg_gen_orc_reg tcg_gen_orc_i64
132 #define tcg_gen_clz_reg tcg_gen_clz_i64
133 #define tcg_gen_ctz_reg tcg_gen_ctz_i64
134 #define tcg_gen_clzi_reg tcg_gen_clzi_i64
135 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
136 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
137 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
138 #define tcg_gen_rotl_reg tcg_gen_rotl_i64
139 #define tcg_gen_rotli_reg tcg_gen_rotli_i64
140 #define tcg_gen_rotr_reg tcg_gen_rotr_i64
141 #define tcg_gen_rotri_reg tcg_gen_rotri_i64
142 #define tcg_gen_deposit_reg tcg_gen_deposit_i64
143 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
144 #define tcg_gen_extract_reg tcg_gen_extract_i64
145 #define tcg_gen_sextract_reg tcg_gen_sextract_i64
146 #define tcg_const_reg tcg_const_i64
147 #define tcg_const_local_reg tcg_const_local_i64
148 #define tcg_gen_movcond_reg tcg_gen_movcond_i64
149 #define tcg_gen_add2_reg tcg_gen_add2_i64
150 #define tcg_gen_sub2_reg tcg_gen_sub2_i64
151 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
152 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
153 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
154 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
156 #define TCGv_reg TCGv_i32
157 #define tcg_temp_new tcg_temp_new_i32
158 #define tcg_global_reg_new tcg_global_reg_new_i32
159 #define tcg_global_mem_new tcg_global_mem_new_i32
160 #define tcg_temp_local_new tcg_temp_local_new_i32
161 #define tcg_temp_free tcg_temp_free_i32
163 #define tcg_gen_movi_reg tcg_gen_movi_i32
164 #define tcg_gen_mov_reg tcg_gen_mov_i32
165 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
166 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
167 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
168 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
169 #define tcg_gen_ld32u_reg tcg_gen_ld_i32
170 #define tcg_gen_ld32s_reg tcg_gen_ld_i32
171 #define tcg_gen_ld_reg tcg_gen_ld_i32
172 #define tcg_gen_st8_reg tcg_gen_st8_i32
173 #define tcg_gen_st16_reg tcg_gen_st16_i32
174 #define tcg_gen_st32_reg tcg_gen_st32_i32
175 #define tcg_gen_st_reg tcg_gen_st_i32
176 #define tcg_gen_add_reg tcg_gen_add_i32
177 #define tcg_gen_addi_reg tcg_gen_addi_i32
178 #define tcg_gen_sub_reg tcg_gen_sub_i32
179 #define tcg_gen_neg_reg tcg_gen_neg_i32
180 #define tcg_gen_subfi_reg tcg_gen_subfi_i32
181 #define tcg_gen_subi_reg tcg_gen_subi_i32
182 #define tcg_gen_and_reg tcg_gen_and_i32
183 #define tcg_gen_andi_reg tcg_gen_andi_i32
184 #define tcg_gen_or_reg tcg_gen_or_i32
185 #define tcg_gen_ori_reg tcg_gen_ori_i32
186 #define tcg_gen_xor_reg tcg_gen_xor_i32
187 #define tcg_gen_xori_reg tcg_gen_xori_i32
188 #define tcg_gen_not_reg tcg_gen_not_i32
189 #define tcg_gen_shl_reg tcg_gen_shl_i32
190 #define tcg_gen_shli_reg tcg_gen_shli_i32
191 #define tcg_gen_shr_reg tcg_gen_shr_i32
192 #define tcg_gen_shri_reg tcg_gen_shri_i32
193 #define tcg_gen_sar_reg tcg_gen_sar_i32
194 #define tcg_gen_sari_reg tcg_gen_sari_i32
195 #define tcg_gen_brcond_reg tcg_gen_brcond_i32
196 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
197 #define tcg_gen_setcond_reg tcg_gen_setcond_i32
198 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
199 #define tcg_gen_mul_reg tcg_gen_mul_i32
200 #define tcg_gen_muli_reg tcg_gen_muli_i32
201 #define tcg_gen_div_reg tcg_gen_div_i32
202 #define tcg_gen_rem_reg tcg_gen_rem_i32
203 #define tcg_gen_divu_reg tcg_gen_divu_i32
204 #define tcg_gen_remu_reg tcg_gen_remu_i32
205 #define tcg_gen_discard_reg tcg_gen_discard_i32
206 #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
207 #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
208 #define tcg_gen_extu_i32_reg tcg_gen_mov_i32
209 #define tcg_gen_ext_i32_reg tcg_gen_mov_i32
210 #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
211 #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
212 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
213 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
214 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
215 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
216 #define tcg_gen_ext32u_reg tcg_gen_mov_i32
217 #define tcg_gen_ext32s_reg tcg_gen_mov_i32
218 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
219 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
220 #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
221 #define tcg_gen_andc_reg tcg_gen_andc_i32
222 #define tcg_gen_eqv_reg tcg_gen_eqv_i32
223 #define tcg_gen_nand_reg tcg_gen_nand_i32
224 #define tcg_gen_nor_reg tcg_gen_nor_i32
225 #define tcg_gen_orc_reg tcg_gen_orc_i32
226 #define tcg_gen_clz_reg tcg_gen_clz_i32
227 #define tcg_gen_ctz_reg tcg_gen_ctz_i32
228 #define tcg_gen_clzi_reg tcg_gen_clzi_i32
229 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
230 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
231 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
232 #define tcg_gen_rotl_reg tcg_gen_rotl_i32
233 #define tcg_gen_rotli_reg tcg_gen_rotli_i32
234 #define tcg_gen_rotr_reg tcg_gen_rotr_i32
235 #define tcg_gen_rotri_reg tcg_gen_rotri_i32
236 #define tcg_gen_deposit_reg tcg_gen_deposit_i32
237 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
238 #define tcg_gen_extract_reg tcg_gen_extract_i32
239 #define tcg_gen_sextract_reg tcg_gen_sextract_i32
240 #define tcg_const_reg tcg_const_i32
241 #define tcg_const_local_reg tcg_const_local_i32
242 #define tcg_gen_movcond_reg tcg_gen_movcond_i32
243 #define tcg_gen_add2_reg tcg_gen_add2_i32
244 #define tcg_gen_sub2_reg tcg_gen_sub2_i32
245 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
246 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
247 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
248 #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
249 #endif /* TARGET_REGISTER_BITS */
251 typedef struct DisasCond
{
258 typedef struct DisasContext
{
259 DisasContextBase base
;
281 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
282 static int expand_sm_imm(DisasContext
*ctx
, int val
)
284 if (val
& PSW_SM_E
) {
285 val
= (val
& ~PSW_SM_E
) | PSW_E
;
287 if (val
& PSW_SM_W
) {
288 val
= (val
& ~PSW_SM_W
) | PSW_W
;
293 /* Inverted space register indicates 0 means sr0 not inferred from base. */
294 static int expand_sr3x(DisasContext
*ctx
, int val
)
299 /* Convert the M:A bits within a memory insn to the tri-state value
300 we use for the final M. */
301 static int ma_to_m(DisasContext
*ctx
, int val
)
303 return val
& 2 ? (val
& 1 ? -1 : 1) : 0;
306 /* Convert the sign of the displacement to a pre or post-modify. */
307 static int pos_to_m(DisasContext
*ctx
, int val
)
312 static int neg_to_m(DisasContext
*ctx
, int val
)
317 /* Used for branch targets and fp memory ops. */
318 static int expand_shl2(DisasContext
*ctx
, int val
)
323 /* Used for fp memory ops. */
324 static int expand_shl3(DisasContext
*ctx
, int val
)
329 /* Used for assemble_21. */
330 static int expand_shl11(DisasContext
*ctx
, int val
)
336 /* Include the auto-generated decoder. */
337 #include "decode.inc.c"
339 /* We are not using a goto_tb (for whatever reason), but have updated
340 the iaq (for whatever reason), so don't do it again on exit. */
341 #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0
343 /* We are exiting the TB, but have neither emitted a goto_tb, nor
344 updated the iaq for the next instruction to be executed. */
345 #define DISAS_IAQ_N_STALE DISAS_TARGET_1
347 /* Similarly, but we want to return to the main loop immediately
348 to recognize unmasked interrupts. */
349 #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2
350 #define DISAS_EXIT DISAS_TARGET_3
352 /* global register indexes */
353 static TCGv_reg cpu_gr
[32];
354 static TCGv_i64 cpu_sr
[4];
355 static TCGv_i64 cpu_srH
;
356 static TCGv_reg cpu_iaoq_f
;
357 static TCGv_reg cpu_iaoq_b
;
358 static TCGv_i64 cpu_iasq_f
;
359 static TCGv_i64 cpu_iasq_b
;
360 static TCGv_reg cpu_sar
;
361 static TCGv_reg cpu_psw_n
;
362 static TCGv_reg cpu_psw_v
;
363 static TCGv_reg cpu_psw_cb
;
364 static TCGv_reg cpu_psw_cb_msb
;
366 #include "exec/gen-icount.h"
368 void hppa_translate_init(void)
370 #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
372 typedef struct { TCGv_reg
*var
; const char *name
; int ofs
; } GlobalVar
;
373 static const GlobalVar vars
[] = {
374 { &cpu_sar
, "sar", offsetof(CPUHPPAState
, cr
[CR_SAR
]) },
385 /* Use the symbolic register names that match the disassembler. */
386 static const char gr_names
[32][4] = {
387 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
388 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
389 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
390 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
392 /* SR[4-7] are not global registers so that we can index them. */
393 static const char sr_names
[5][4] = {
394 "sr0", "sr1", "sr2", "sr3", "srH"
400 for (i
= 1; i
< 32; i
++) {
401 cpu_gr
[i
] = tcg_global_mem_new(cpu_env
,
402 offsetof(CPUHPPAState
, gr
[i
]),
405 for (i
= 0; i
< 4; i
++) {
406 cpu_sr
[i
] = tcg_global_mem_new_i64(cpu_env
,
407 offsetof(CPUHPPAState
, sr
[i
]),
410 cpu_srH
= tcg_global_mem_new_i64(cpu_env
,
411 offsetof(CPUHPPAState
, sr
[4]),
414 for (i
= 0; i
< ARRAY_SIZE(vars
); ++i
) {
415 const GlobalVar
*v
= &vars
[i
];
416 *v
->var
= tcg_global_mem_new(cpu_env
, v
->ofs
, v
->name
);
419 cpu_iasq_f
= tcg_global_mem_new_i64(cpu_env
,
420 offsetof(CPUHPPAState
, iasq_f
),
422 cpu_iasq_b
= tcg_global_mem_new_i64(cpu_env
,
423 offsetof(CPUHPPAState
, iasq_b
),
427 static DisasCond
cond_make_f(void)
436 static DisasCond
cond_make_t(void)
439 .c
= TCG_COND_ALWAYS
,
445 static DisasCond
cond_make_n(void)
456 static DisasCond
cond_make_0_tmp(TCGCond c
, TCGv_reg a0
)
458 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
460 .c
= c
, .a0
= a0
, .a1_is_0
= true
464 static DisasCond
cond_make_0(TCGCond c
, TCGv_reg a0
)
466 TCGv_reg tmp
= tcg_temp_new();
467 tcg_gen_mov_reg(tmp
, a0
);
468 return cond_make_0_tmp(c
, tmp
);
471 static DisasCond
cond_make(TCGCond c
, TCGv_reg a0
, TCGv_reg a1
)
473 DisasCond r
= { .c
= c
};
475 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
476 r
.a0
= tcg_temp_new();
477 tcg_gen_mov_reg(r
.a0
, a0
);
478 r
.a1
= tcg_temp_new();
479 tcg_gen_mov_reg(r
.a1
, a1
);
484 static void cond_prep(DisasCond
*cond
)
487 cond
->a1_is_0
= false;
488 cond
->a1
= tcg_const_reg(0);
492 static void cond_free(DisasCond
*cond
)
496 if (!cond
->a0_is_n
) {
497 tcg_temp_free(cond
->a0
);
499 if (!cond
->a1_is_0
) {
500 tcg_temp_free(cond
->a1
);
502 cond
->a0_is_n
= false;
503 cond
->a1_is_0
= false;
507 case TCG_COND_ALWAYS
:
508 cond
->c
= TCG_COND_NEVER
;
515 static TCGv_reg
get_temp(DisasContext
*ctx
)
517 unsigned i
= ctx
->ntempr
++;
518 g_assert(i
< ARRAY_SIZE(ctx
->tempr
));
519 return ctx
->tempr
[i
] = tcg_temp_new();
522 #ifndef CONFIG_USER_ONLY
523 static TCGv_tl
get_temp_tl(DisasContext
*ctx
)
525 unsigned i
= ctx
->ntempl
++;
526 g_assert(i
< ARRAY_SIZE(ctx
->templ
));
527 return ctx
->templ
[i
] = tcg_temp_new_tl();
531 static TCGv_reg
load_const(DisasContext
*ctx
, target_sreg v
)
533 TCGv_reg t
= get_temp(ctx
);
534 tcg_gen_movi_reg(t
, v
);
538 static TCGv_reg
load_gpr(DisasContext
*ctx
, unsigned reg
)
541 TCGv_reg t
= get_temp(ctx
);
542 tcg_gen_movi_reg(t
, 0);
549 static TCGv_reg
dest_gpr(DisasContext
*ctx
, unsigned reg
)
551 if (reg
== 0 || ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
552 return get_temp(ctx
);
558 static void save_or_nullify(DisasContext
*ctx
, TCGv_reg dest
, TCGv_reg t
)
560 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
561 cond_prep(&ctx
->null_cond
);
562 tcg_gen_movcond_reg(ctx
->null_cond
.c
, dest
, ctx
->null_cond
.a0
,
563 ctx
->null_cond
.a1
, dest
, t
);
565 tcg_gen_mov_reg(dest
, t
);
569 static void save_gpr(DisasContext
*ctx
, unsigned reg
, TCGv_reg t
)
572 save_or_nullify(ctx
, cpu_gr
[reg
], t
);
576 #ifdef HOST_WORDS_BIGENDIAN
584 static TCGv_i32
load_frw_i32(unsigned rt
)
586 TCGv_i32 ret
= tcg_temp_new_i32();
587 tcg_gen_ld_i32(ret
, cpu_env
,
588 offsetof(CPUHPPAState
, fr
[rt
& 31])
589 + (rt
& 32 ? LO_OFS
: HI_OFS
));
593 static TCGv_i32
load_frw0_i32(unsigned rt
)
596 return tcg_const_i32(0);
598 return load_frw_i32(rt
);
602 static TCGv_i64
load_frw0_i64(unsigned rt
)
605 return tcg_const_i64(0);
607 TCGv_i64 ret
= tcg_temp_new_i64();
608 tcg_gen_ld32u_i64(ret
, cpu_env
,
609 offsetof(CPUHPPAState
, fr
[rt
& 31])
610 + (rt
& 32 ? LO_OFS
: HI_OFS
));
615 static void save_frw_i32(unsigned rt
, TCGv_i32 val
)
617 tcg_gen_st_i32(val
, cpu_env
,
618 offsetof(CPUHPPAState
, fr
[rt
& 31])
619 + (rt
& 32 ? LO_OFS
: HI_OFS
));
625 static TCGv_i64
load_frd(unsigned rt
)
627 TCGv_i64 ret
= tcg_temp_new_i64();
628 tcg_gen_ld_i64(ret
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
632 static TCGv_i64
load_frd0(unsigned rt
)
635 return tcg_const_i64(0);
641 static void save_frd(unsigned rt
, TCGv_i64 val
)
643 tcg_gen_st_i64(val
, cpu_env
, offsetof(CPUHPPAState
, fr
[rt
]));
646 static void load_spr(DisasContext
*ctx
, TCGv_i64 dest
, unsigned reg
)
648 #ifdef CONFIG_USER_ONLY
649 tcg_gen_movi_i64(dest
, 0);
652 tcg_gen_mov_i64(dest
, cpu_sr
[reg
]);
653 } else if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
654 tcg_gen_mov_i64(dest
, cpu_srH
);
656 tcg_gen_ld_i64(dest
, cpu_env
, offsetof(CPUHPPAState
, sr
[reg
]));
661 /* Skip over the implementation of an insn that has been nullified.
662 Use this when the insn is too complex for a conditional move. */
663 static void nullify_over(DisasContext
*ctx
)
665 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
666 /* The always condition should have been handled in the main loop. */
667 assert(ctx
->null_cond
.c
!= TCG_COND_ALWAYS
);
669 ctx
->null_lab
= gen_new_label();
670 cond_prep(&ctx
->null_cond
);
672 /* If we're using PSW[N], copy it to a temp because... */
673 if (ctx
->null_cond
.a0_is_n
) {
674 ctx
->null_cond
.a0_is_n
= false;
675 ctx
->null_cond
.a0
= tcg_temp_new();
676 tcg_gen_mov_reg(ctx
->null_cond
.a0
, cpu_psw_n
);
678 /* ... we clear it before branching over the implementation,
679 so that (1) it's clear after nullifying this insn and
680 (2) if this insn nullifies the next, PSW[N] is valid. */
681 if (ctx
->psw_n_nonzero
) {
682 ctx
->psw_n_nonzero
= false;
683 tcg_gen_movi_reg(cpu_psw_n
, 0);
686 tcg_gen_brcond_reg(ctx
->null_cond
.c
, ctx
->null_cond
.a0
,
687 ctx
->null_cond
.a1
, ctx
->null_lab
);
688 cond_free(&ctx
->null_cond
);
692 /* Save the current nullification state to PSW[N]. */
693 static void nullify_save(DisasContext
*ctx
)
695 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
696 if (ctx
->psw_n_nonzero
) {
697 tcg_gen_movi_reg(cpu_psw_n
, 0);
701 if (!ctx
->null_cond
.a0_is_n
) {
702 cond_prep(&ctx
->null_cond
);
703 tcg_gen_setcond_reg(ctx
->null_cond
.c
, cpu_psw_n
,
704 ctx
->null_cond
.a0
, ctx
->null_cond
.a1
);
705 ctx
->psw_n_nonzero
= true;
707 cond_free(&ctx
->null_cond
);
710 /* Set a PSW[N] to X. The intention is that this is used immediately
711 before a goto_tb/exit_tb, so that there is no fallthru path to other
712 code within the TB. Therefore we do not update psw_n_nonzero. */
713 static void nullify_set(DisasContext
*ctx
, bool x
)
715 if (ctx
->psw_n_nonzero
|| x
) {
716 tcg_gen_movi_reg(cpu_psw_n
, x
);
720 /* Mark the end of an instruction that may have been nullified.
721 This is the pair to nullify_over. Always returns true so that
722 it may be tail-called from a translate function. */
723 static bool nullify_end(DisasContext
*ctx
)
725 TCGLabel
*null_lab
= ctx
->null_lab
;
726 DisasJumpType status
= ctx
->base
.is_jmp
;
728 /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
729 For UPDATED, we cannot update on the nullified path. */
730 assert(status
!= DISAS_IAQ_N_UPDATED
);
732 if (likely(null_lab
== NULL
)) {
733 /* The current insn wasn't conditional or handled the condition
734 applied to it without a branch, so the (new) setting of
735 NULL_COND can be applied directly to the next insn. */
738 ctx
->null_lab
= NULL
;
740 if (likely(ctx
->null_cond
.c
== TCG_COND_NEVER
)) {
741 /* The next instruction will be unconditional,
742 and NULL_COND already reflects that. */
743 gen_set_label(null_lab
);
745 /* The insn that we just executed is itself nullifying the next
746 instruction. Store the condition in the PSW[N] global.
747 We asserted PSW[N] = 0 in nullify_over, so that after the
748 label we have the proper value in place. */
750 gen_set_label(null_lab
);
751 ctx
->null_cond
= cond_make_n();
753 if (status
== DISAS_NORETURN
) {
754 ctx
->base
.is_jmp
= DISAS_NEXT
;
759 static void copy_iaoq_entry(TCGv_reg dest
, target_ureg ival
, TCGv_reg vval
)
761 if (unlikely(ival
== -1)) {
762 tcg_gen_mov_reg(dest
, vval
);
764 tcg_gen_movi_reg(dest
, ival
);
768 static inline target_ureg
iaoq_dest(DisasContext
*ctx
, target_sreg disp
)
770 return ctx
->iaoq_f
+ disp
+ 8;
773 static void gen_excp_1(int exception
)
775 TCGv_i32 t
= tcg_const_i32(exception
);
776 gen_helper_excp(cpu_env
, t
);
777 tcg_temp_free_i32(t
);
780 static void gen_excp(DisasContext
*ctx
, int exception
)
782 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
783 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
785 gen_excp_1(exception
);
786 ctx
->base
.is_jmp
= DISAS_NORETURN
;
789 static bool gen_excp_iir(DisasContext
*ctx
, int exc
)
794 tmp
= tcg_const_reg(ctx
->insn
);
795 tcg_gen_st_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[CR_IIR
]));
798 return nullify_end(ctx
);
801 static bool gen_illegal(DisasContext
*ctx
)
803 return gen_excp_iir(ctx
, EXCP_ILL
);
806 #ifdef CONFIG_USER_ONLY
807 #define CHECK_MOST_PRIVILEGED(EXCP) \
808 return gen_excp_iir(ctx, EXCP)
810 #define CHECK_MOST_PRIVILEGED(EXCP) \
812 if (ctx->privilege != 0) { \
813 return gen_excp_iir(ctx, EXCP); \
818 static bool use_goto_tb(DisasContext
*ctx
, target_ureg dest
)
820 /* Suppress goto_tb for page crossing, IO, or single-steping. */
821 return !(((ctx
->base
.pc_first
^ dest
) & TARGET_PAGE_MASK
)
822 || (tb_cflags(ctx
->base
.tb
) & CF_LAST_IO
)
823 || ctx
->base
.singlestep_enabled
);
826 /* If the next insn is to be nullified, and it's on the same page,
827 and we're not attempting to set a breakpoint on it, then we can
828 totally skip the nullified insn. This avoids creating and
829 executing a TB that merely branches to the next TB. */
830 static bool use_nullify_skip(DisasContext
*ctx
)
832 return (((ctx
->iaoq_b
^ ctx
->iaoq_f
) & TARGET_PAGE_MASK
) == 0
833 && !cpu_breakpoint_test(ctx
->cs
, ctx
->iaoq_b
, BP_ANY
));
836 static void gen_goto_tb(DisasContext
*ctx
, int which
,
837 target_ureg f
, target_ureg b
)
839 if (f
!= -1 && b
!= -1 && use_goto_tb(ctx
, f
)) {
840 tcg_gen_goto_tb(which
);
841 tcg_gen_movi_reg(cpu_iaoq_f
, f
);
842 tcg_gen_movi_reg(cpu_iaoq_b
, b
);
843 tcg_gen_exit_tb(ctx
->base
.tb
, which
);
845 copy_iaoq_entry(cpu_iaoq_f
, f
, cpu_iaoq_b
);
846 copy_iaoq_entry(cpu_iaoq_b
, b
, ctx
->iaoq_n_var
);
847 if (ctx
->base
.singlestep_enabled
) {
848 gen_excp_1(EXCP_DEBUG
);
850 tcg_gen_lookup_and_goto_ptr();
855 static bool cond_need_sv(int c
)
857 return c
== 2 || c
== 3 || c
== 6;
860 static bool cond_need_cb(int c
)
862 return c
== 4 || c
== 5;
866 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
867 * the Parisc 1.1 Architecture Reference Manual for details.
870 static DisasCond
do_cond(unsigned cf
, TCGv_reg res
,
871 TCGv_reg cb_msb
, TCGv_reg sv
)
877 case 0: /* Never / TR (0 / 1) */
878 cond
= cond_make_f();
880 case 1: /* = / <> (Z / !Z) */
881 cond
= cond_make_0(TCG_COND_EQ
, res
);
883 case 2: /* < / >= (N ^ V / !(N ^ V) */
884 tmp
= tcg_temp_new();
885 tcg_gen_xor_reg(tmp
, res
, sv
);
886 cond
= cond_make_0_tmp(TCG_COND_LT
, tmp
);
888 case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
892 * ((res < 0) ^ (sv < 0)) | !res
893 * ((res ^ sv) < 0) | !res
894 * (~(res ^ sv) >= 0) | !res
895 * !(~(res ^ sv) >> 31) | !res
896 * !(~(res ^ sv) >> 31 & res)
898 tmp
= tcg_temp_new();
899 tcg_gen_eqv_reg(tmp
, res
, sv
);
900 tcg_gen_sari_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
901 tcg_gen_and_reg(tmp
, tmp
, res
);
902 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
904 case 4: /* NUV / UV (!C / C) */
905 cond
= cond_make_0(TCG_COND_EQ
, cb_msb
);
907 case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
908 tmp
= tcg_temp_new();
909 tcg_gen_neg_reg(tmp
, cb_msb
);
910 tcg_gen_and_reg(tmp
, tmp
, res
);
911 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
913 case 6: /* SV / NSV (V / !V) */
914 cond
= cond_make_0(TCG_COND_LT
, sv
);
916 case 7: /* OD / EV */
917 tmp
= tcg_temp_new();
918 tcg_gen_andi_reg(tmp
, res
, 1);
919 cond
= cond_make_0_tmp(TCG_COND_NE
, tmp
);
922 g_assert_not_reached();
925 cond
.c
= tcg_invert_cond(cond
.c
);
931 /* Similar, but for the special case of subtraction without borrow, we
932 can use the inputs directly. This can allow other computation to be
933 deleted as unused. */
935 static DisasCond
do_sub_cond(unsigned cf
, TCGv_reg res
,
936 TCGv_reg in1
, TCGv_reg in2
, TCGv_reg sv
)
942 cond
= cond_make(TCG_COND_EQ
, in1
, in2
);
945 cond
= cond_make(TCG_COND_LT
, in1
, in2
);
948 cond
= cond_make(TCG_COND_LE
, in1
, in2
);
950 case 4: /* << / >>= */
951 cond
= cond_make(TCG_COND_LTU
, in1
, in2
);
953 case 5: /* <<= / >> */
954 cond
= cond_make(TCG_COND_LEU
, in1
, in2
);
957 return do_cond(cf
, res
, NULL
, sv
);
960 cond
.c
= tcg_invert_cond(cond
.c
);
967 * Similar, but for logicals, where the carry and overflow bits are not
968 * computed, and use of them is undefined.
970 * Undefined or not, hardware does not trap. It seems reasonable to
971 * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
972 * how cases c={2,3} are treated.
975 static DisasCond
do_log_cond(unsigned cf
, TCGv_reg res
)
979 case 9: /* undef, C */
980 case 11: /* undef, C & !Z */
981 case 12: /* undef, V */
982 return cond_make_f();
985 case 8: /* undef, !C */
986 case 10: /* undef, !C | Z */
987 case 13: /* undef, !V */
988 return cond_make_t();
991 return cond_make_0(TCG_COND_EQ
, res
);
993 return cond_make_0(TCG_COND_NE
, res
);
995 return cond_make_0(TCG_COND_LT
, res
);
997 return cond_make_0(TCG_COND_GE
, res
);
999 return cond_make_0(TCG_COND_LE
, res
);
1001 return cond_make_0(TCG_COND_GT
, res
);
1005 return do_cond(cf
, res
, NULL
, NULL
);
1008 g_assert_not_reached();
1012 /* Similar, but for shift/extract/deposit conditions. */
1014 static DisasCond
do_sed_cond(unsigned orig
, TCGv_reg res
)
1018 /* Convert the compressed condition codes to standard.
1019 0-2 are the same as logicals (nv,<,<=), while 3 is OD.
1020 4-7 are the reverse of 0-3. */
1027 return do_log_cond(c
* 2 + f
, res
);
1030 /* Similar, but for unit conditions. */
1032 static DisasCond
do_unit_cond(unsigned cf
, TCGv_reg res
,
1033 TCGv_reg in1
, TCGv_reg in2
)
1036 TCGv_reg tmp
, cb
= NULL
;
1039 /* Since we want to test lots of carry-out bits all at once, do not
1040 * do our normal thing and compute carry-in of bit B+1 since that
1041 * leaves us with carry bits spread across two words.
1043 cb
= tcg_temp_new();
1044 tmp
= tcg_temp_new();
1045 tcg_gen_or_reg(cb
, in1
, in2
);
1046 tcg_gen_and_reg(tmp
, in1
, in2
);
1047 tcg_gen_andc_reg(cb
, cb
, res
);
1048 tcg_gen_or_reg(cb
, cb
, tmp
);
1053 case 0: /* never / TR */
1054 case 1: /* undefined */
1055 case 5: /* undefined */
1056 cond
= cond_make_f();
1059 case 2: /* SBZ / NBZ */
1060 /* See hasless(v,1) from
1061 * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
1063 tmp
= tcg_temp_new();
1064 tcg_gen_subi_reg(tmp
, res
, 0x01010101u
);
1065 tcg_gen_andc_reg(tmp
, tmp
, res
);
1066 tcg_gen_andi_reg(tmp
, tmp
, 0x80808080u
);
1067 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1071 case 3: /* SHZ / NHZ */
1072 tmp
= tcg_temp_new();
1073 tcg_gen_subi_reg(tmp
, res
, 0x00010001u
);
1074 tcg_gen_andc_reg(tmp
, tmp
, res
);
1075 tcg_gen_andi_reg(tmp
, tmp
, 0x80008000u
);
1076 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1080 case 4: /* SDC / NDC */
1081 tcg_gen_andi_reg(cb
, cb
, 0x88888888u
);
1082 cond
= cond_make_0(TCG_COND_NE
, cb
);
1085 case 6: /* SBC / NBC */
1086 tcg_gen_andi_reg(cb
, cb
, 0x80808080u
);
1087 cond
= cond_make_0(TCG_COND_NE
, cb
);
1090 case 7: /* SHC / NHC */
1091 tcg_gen_andi_reg(cb
, cb
, 0x80008000u
);
1092 cond
= cond_make_0(TCG_COND_NE
, cb
);
1096 g_assert_not_reached();
1102 cond
.c
= tcg_invert_cond(cond
.c
);
1108 /* Compute signed overflow for addition. */
1109 static TCGv_reg
do_add_sv(DisasContext
*ctx
, TCGv_reg res
,
1110 TCGv_reg in1
, TCGv_reg in2
)
1112 TCGv_reg sv
= get_temp(ctx
);
1113 TCGv_reg tmp
= tcg_temp_new();
1115 tcg_gen_xor_reg(sv
, res
, in1
);
1116 tcg_gen_xor_reg(tmp
, in1
, in2
);
1117 tcg_gen_andc_reg(sv
, sv
, tmp
);
1123 /* Compute signed overflow for subtraction. */
1124 static TCGv_reg
do_sub_sv(DisasContext
*ctx
, TCGv_reg res
,
1125 TCGv_reg in1
, TCGv_reg in2
)
1127 TCGv_reg sv
= get_temp(ctx
);
1128 TCGv_reg tmp
= tcg_temp_new();
1130 tcg_gen_xor_reg(sv
, res
, in1
);
1131 tcg_gen_xor_reg(tmp
, in1
, in2
);
1132 tcg_gen_and_reg(sv
, sv
, tmp
);
1138 static void do_add(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1139 TCGv_reg in2
, unsigned shift
, bool is_l
,
1140 bool is_tsv
, bool is_tc
, bool is_c
, unsigned cf
)
1142 TCGv_reg dest
, cb
, cb_msb
, sv
, tmp
;
1143 unsigned c
= cf
>> 1;
1146 dest
= tcg_temp_new();
1151 tmp
= get_temp(ctx
);
1152 tcg_gen_shli_reg(tmp
, in1
, shift
);
1156 if (!is_l
|| cond_need_cb(c
)) {
1157 TCGv_reg zero
= tcg_const_reg(0);
1158 cb_msb
= get_temp(ctx
);
1159 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, in2
, zero
);
1161 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cpu_psw_cb_msb
, zero
);
1163 tcg_temp_free(zero
);
1166 tcg_gen_xor_reg(cb
, in1
, in2
);
1167 tcg_gen_xor_reg(cb
, cb
, dest
);
1170 tcg_gen_add_reg(dest
, in1
, in2
);
1172 tcg_gen_add_reg(dest
, dest
, cpu_psw_cb_msb
);
1176 /* Compute signed overflow if required. */
1178 if (is_tsv
|| cond_need_sv(c
)) {
1179 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
1181 /* ??? Need to include overflow from shift. */
1182 gen_helper_tsv(cpu_env
, sv
);
1186 /* Emit any conditional trap before any writeback. */
1187 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1190 tmp
= tcg_temp_new();
1191 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1192 gen_helper_tcond(cpu_env
, tmp
);
1196 /* Write back the result. */
1198 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1199 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1201 save_gpr(ctx
, rt
, dest
);
1202 tcg_temp_free(dest
);
1204 /* Install the new nullification. */
1205 cond_free(&ctx
->null_cond
);
1206 ctx
->null_cond
= cond
;
1209 static bool do_add_reg(DisasContext
*ctx
, arg_rrr_cf_sh
*a
,
1210 bool is_l
, bool is_tsv
, bool is_tc
, bool is_c
)
1212 TCGv_reg tcg_r1
, tcg_r2
;
1217 tcg_r1
= load_gpr(ctx
, a
->r1
);
1218 tcg_r2
= load_gpr(ctx
, a
->r2
);
1219 do_add(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->sh
, is_l
, is_tsv
, is_tc
, is_c
, a
->cf
);
1220 return nullify_end(ctx
);
1223 static bool do_add_imm(DisasContext
*ctx
, arg_rri_cf
*a
,
1224 bool is_tsv
, bool is_tc
)
1226 TCGv_reg tcg_im
, tcg_r2
;
1231 tcg_im
= load_const(ctx
, a
->i
);
1232 tcg_r2
= load_gpr(ctx
, a
->r
);
1233 do_add(ctx
, a
->t
, tcg_im
, tcg_r2
, 0, 0, is_tsv
, is_tc
, 0, a
->cf
);
1234 return nullify_end(ctx
);
1237 static void do_sub(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1238 TCGv_reg in2
, bool is_tsv
, bool is_b
,
1239 bool is_tc
, unsigned cf
)
1241 TCGv_reg dest
, sv
, cb
, cb_msb
, zero
, tmp
;
1242 unsigned c
= cf
>> 1;
1245 dest
= tcg_temp_new();
1246 cb
= tcg_temp_new();
1247 cb_msb
= tcg_temp_new();
1249 zero
= tcg_const_reg(0);
1251 /* DEST,C = IN1 + ~IN2 + C. */
1252 tcg_gen_not_reg(cb
, in2
);
1253 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, cpu_psw_cb_msb
, zero
);
1254 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cb
, zero
);
1255 tcg_gen_xor_reg(cb
, cb
, in1
);
1256 tcg_gen_xor_reg(cb
, cb
, dest
);
1258 /* DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
1259 operations by seeding the high word with 1 and subtracting. */
1260 tcg_gen_movi_reg(cb_msb
, 1);
1261 tcg_gen_sub2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, zero
);
1262 tcg_gen_eqv_reg(cb
, in1
, in2
);
1263 tcg_gen_xor_reg(cb
, cb
, dest
);
1265 tcg_temp_free(zero
);
1267 /* Compute signed overflow if required. */
1269 if (is_tsv
|| cond_need_sv(c
)) {
1270 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1272 gen_helper_tsv(cpu_env
, sv
);
1276 /* Compute the condition. We cannot use the special case for borrow. */
1278 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1280 cond
= do_cond(cf
, dest
, cb_msb
, sv
);
1283 /* Emit any conditional trap before any writeback. */
1286 tmp
= tcg_temp_new();
1287 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1288 gen_helper_tcond(cpu_env
, tmp
);
1292 /* Write back the result. */
1293 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1294 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1295 save_gpr(ctx
, rt
, dest
);
1296 tcg_temp_free(dest
);
1298 /* Install the new nullification. */
1299 cond_free(&ctx
->null_cond
);
1300 ctx
->null_cond
= cond
;
1303 static bool do_sub_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1304 bool is_tsv
, bool is_b
, bool is_tc
)
1306 TCGv_reg tcg_r1
, tcg_r2
;
1311 tcg_r1
= load_gpr(ctx
, a
->r1
);
1312 tcg_r2
= load_gpr(ctx
, a
->r2
);
1313 do_sub(ctx
, a
->t
, tcg_r1
, tcg_r2
, is_tsv
, is_b
, is_tc
, a
->cf
);
1314 return nullify_end(ctx
);
1317 static bool do_sub_imm(DisasContext
*ctx
, arg_rri_cf
*a
, bool is_tsv
)
1319 TCGv_reg tcg_im
, tcg_r2
;
1324 tcg_im
= load_const(ctx
, a
->i
);
1325 tcg_r2
= load_gpr(ctx
, a
->r
);
1326 do_sub(ctx
, a
->t
, tcg_im
, tcg_r2
, is_tsv
, 0, 0, a
->cf
);
1327 return nullify_end(ctx
);
1330 static void do_cmpclr(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1331 TCGv_reg in2
, unsigned cf
)
1336 dest
= tcg_temp_new();
1337 tcg_gen_sub_reg(dest
, in1
, in2
);
1339 /* Compute signed overflow if required. */
1341 if (cond_need_sv(cf
>> 1)) {
1342 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1345 /* Form the condition for the compare. */
1346 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1349 tcg_gen_movi_reg(dest
, 0);
1350 save_gpr(ctx
, rt
, dest
);
1351 tcg_temp_free(dest
);
1353 /* Install the new nullification. */
1354 cond_free(&ctx
->null_cond
);
1355 ctx
->null_cond
= cond
;
1358 static void do_log(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1359 TCGv_reg in2
, unsigned cf
,
1360 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1362 TCGv_reg dest
= dest_gpr(ctx
, rt
);
1364 /* Perform the operation, and writeback. */
1366 save_gpr(ctx
, rt
, dest
);
1368 /* Install the new nullification. */
1369 cond_free(&ctx
->null_cond
);
1371 ctx
->null_cond
= do_log_cond(cf
, dest
);
1375 static bool do_log_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1376 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1378 TCGv_reg tcg_r1
, tcg_r2
;
1383 tcg_r1
= load_gpr(ctx
, a
->r1
);
1384 tcg_r2
= load_gpr(ctx
, a
->r2
);
1385 do_log(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, fn
);
1386 return nullify_end(ctx
);
1389 static void do_unit(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1390 TCGv_reg in2
, unsigned cf
, bool is_tc
,
1391 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1397 dest
= dest_gpr(ctx
, rt
);
1399 save_gpr(ctx
, rt
, dest
);
1400 cond_free(&ctx
->null_cond
);
1402 dest
= tcg_temp_new();
1405 cond
= do_unit_cond(cf
, dest
, in1
, in2
);
1408 TCGv_reg tmp
= tcg_temp_new();
1410 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1411 gen_helper_tcond(cpu_env
, tmp
);
1414 save_gpr(ctx
, rt
, dest
);
1416 cond_free(&ctx
->null_cond
);
1417 ctx
->null_cond
= cond
;
1421 #ifndef CONFIG_USER_ONLY
1422 /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
1423 from the top 2 bits of the base register. There are a few system
1424 instructions that have a 3-bit space specifier, for which SR0 is
1425 not special. To handle this, pass ~SP. */
1426 static TCGv_i64
space_select(DisasContext
*ctx
, int sp
, TCGv_reg base
)
1436 spc
= get_temp_tl(ctx
);
1437 load_spr(ctx
, spc
, sp
);
1440 if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
1444 ptr
= tcg_temp_new_ptr();
1445 tmp
= tcg_temp_new();
1446 spc
= get_temp_tl(ctx
);
1448 tcg_gen_shri_reg(tmp
, base
, TARGET_REGISTER_BITS
- 5);
1449 tcg_gen_andi_reg(tmp
, tmp
, 030);
1450 tcg_gen_trunc_reg_ptr(ptr
, tmp
);
1453 tcg_gen_add_ptr(ptr
, ptr
, cpu_env
);
1454 tcg_gen_ld_i64(spc
, ptr
, offsetof(CPUHPPAState
, sr
[4]));
1455 tcg_temp_free_ptr(ptr
);
1461 static void form_gva(DisasContext
*ctx
, TCGv_tl
*pgva
, TCGv_reg
*pofs
,
1462 unsigned rb
, unsigned rx
, int scale
, target_sreg disp
,
1463 unsigned sp
, int modify
, bool is_phys
)
1465 TCGv_reg base
= load_gpr(ctx
, rb
);
1468 /* Note that RX is mutually exclusive with DISP. */
1470 ofs
= get_temp(ctx
);
1471 tcg_gen_shli_reg(ofs
, cpu_gr
[rx
], scale
);
1472 tcg_gen_add_reg(ofs
, ofs
, base
);
1473 } else if (disp
|| modify
) {
1474 ofs
= get_temp(ctx
);
1475 tcg_gen_addi_reg(ofs
, base
, disp
);
1481 #ifdef CONFIG_USER_ONLY
1482 *pgva
= (modify
<= 0 ? ofs
: base
);
1484 TCGv_tl addr
= get_temp_tl(ctx
);
1485 tcg_gen_extu_reg_tl(addr
, modify
<= 0 ? ofs
: base
);
1486 if (ctx
->tb_flags
& PSW_W
) {
1487 tcg_gen_andi_tl(addr
, addr
, 0x3fffffffffffffffull
);
1490 tcg_gen_or_tl(addr
, addr
, space_select(ctx
, sp
, base
));
1496 /* Emit a memory load. The modify parameter should be
1497 * < 0 for pre-modify,
1498 * > 0 for post-modify,
1499 * = 0 for no base register update.
1501 static void do_load_32(DisasContext
*ctx
, TCGv_i32 dest
, unsigned rb
,
1502 unsigned rx
, int scale
, target_sreg disp
,
1503 unsigned sp
, int modify
, TCGMemOp mop
)
1508 /* Caller uses nullify_over/nullify_end. */
1509 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1511 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1512 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1513 tcg_gen_qemu_ld_reg(dest
, addr
, ctx
->mmu_idx
, mop
);
1515 save_gpr(ctx
, rb
, ofs
);
1519 static void do_load_64(DisasContext
*ctx
, TCGv_i64 dest
, unsigned rb
,
1520 unsigned rx
, int scale
, target_sreg disp
,
1521 unsigned sp
, int modify
, TCGMemOp mop
)
1526 /* Caller uses nullify_over/nullify_end. */
1527 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1529 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1530 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1531 tcg_gen_qemu_ld_i64(dest
, addr
, ctx
->mmu_idx
, mop
);
1533 save_gpr(ctx
, rb
, ofs
);
1537 static void do_store_32(DisasContext
*ctx
, TCGv_i32 src
, unsigned rb
,
1538 unsigned rx
, int scale
, target_sreg disp
,
1539 unsigned sp
, int modify
, TCGMemOp mop
)
1544 /* Caller uses nullify_over/nullify_end. */
1545 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1547 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1548 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1549 tcg_gen_qemu_st_i32(src
, addr
, ctx
->mmu_idx
, mop
);
1551 save_gpr(ctx
, rb
, ofs
);
1555 static void do_store_64(DisasContext
*ctx
, TCGv_i64 src
, unsigned rb
,
1556 unsigned rx
, int scale
, target_sreg disp
,
1557 unsigned sp
, int modify
, TCGMemOp mop
)
1562 /* Caller uses nullify_over/nullify_end. */
1563 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1565 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1566 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1567 tcg_gen_qemu_st_i64(src
, addr
, ctx
->mmu_idx
, mop
);
1569 save_gpr(ctx
, rb
, ofs
);
1573 #if TARGET_REGISTER_BITS == 64
1574 #define do_load_reg do_load_64
1575 #define do_store_reg do_store_64
1577 #define do_load_reg do_load_32
1578 #define do_store_reg do_store_32
1581 static bool do_load(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1582 unsigned rx
, int scale
, target_sreg disp
,
1583 unsigned sp
, int modify
, TCGMemOp mop
)
1590 /* No base register update. */
1591 dest
= dest_gpr(ctx
, rt
);
1593 /* Make sure if RT == RB, we see the result of the load. */
1594 dest
= get_temp(ctx
);
1596 do_load_reg(ctx
, dest
, rb
, rx
, scale
, disp
, sp
, modify
, mop
);
1597 save_gpr(ctx
, rt
, dest
);
1599 return nullify_end(ctx
);
1602 static bool do_floadw(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1603 unsigned rx
, int scale
, target_sreg disp
,
1604 unsigned sp
, int modify
)
1610 tmp
= tcg_temp_new_i32();
1611 do_load_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1612 save_frw_i32(rt
, tmp
);
1613 tcg_temp_free_i32(tmp
);
1616 gen_helper_loaded_fr0(cpu_env
);
1619 return nullify_end(ctx
);
1622 static bool trans_fldw(DisasContext
*ctx
, arg_ldst
*a
)
1624 return do_floadw(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1625 a
->disp
, a
->sp
, a
->m
);
1628 static bool do_floadd(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1629 unsigned rx
, int scale
, target_sreg disp
,
1630 unsigned sp
, int modify
)
1636 tmp
= tcg_temp_new_i64();
1637 do_load_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEQ
);
1639 tcg_temp_free_i64(tmp
);
1642 gen_helper_loaded_fr0(cpu_env
);
1645 return nullify_end(ctx
);
1648 static bool trans_fldd(DisasContext
*ctx
, arg_ldst
*a
)
1650 return do_floadd(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1651 a
->disp
, a
->sp
, a
->m
);
1654 static bool do_store(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1655 target_sreg disp
, unsigned sp
,
1656 int modify
, TCGMemOp mop
)
1659 do_store_reg(ctx
, load_gpr(ctx
, rt
), rb
, 0, 0, disp
, sp
, modify
, mop
);
1660 return nullify_end(ctx
);
1663 static bool do_fstorew(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1664 unsigned rx
, int scale
, target_sreg disp
,
1665 unsigned sp
, int modify
)
1671 tmp
= load_frw_i32(rt
);
1672 do_store_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1673 tcg_temp_free_i32(tmp
);
1675 return nullify_end(ctx
);
1678 static bool trans_fstw(DisasContext
*ctx
, arg_ldst
*a
)
1680 return do_fstorew(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1681 a
->disp
, a
->sp
, a
->m
);
1684 static bool do_fstored(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1685 unsigned rx
, int scale
, target_sreg disp
,
1686 unsigned sp
, int modify
)
1693 do_store_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEQ
);
1694 tcg_temp_free_i64(tmp
);
1696 return nullify_end(ctx
);
1699 static bool trans_fstd(DisasContext
*ctx
, arg_ldst
*a
)
1701 return do_fstored(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1702 a
->disp
, a
->sp
, a
->m
);
1705 static bool do_fop_wew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1706 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
))
1711 tmp
= load_frw0_i32(ra
);
1713 func(tmp
, cpu_env
, tmp
);
1715 save_frw_i32(rt
, tmp
);
1716 tcg_temp_free_i32(tmp
);
1717 return nullify_end(ctx
);
1720 static bool do_fop_wed(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1721 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i64
))
1728 dst
= tcg_temp_new_i32();
1730 func(dst
, cpu_env
, src
);
1732 tcg_temp_free_i64(src
);
1733 save_frw_i32(rt
, dst
);
1734 tcg_temp_free_i32(dst
);
1735 return nullify_end(ctx
);
1738 static bool do_fop_ded(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1739 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
1744 tmp
= load_frd0(ra
);
1746 func(tmp
, cpu_env
, tmp
);
1749 tcg_temp_free_i64(tmp
);
1750 return nullify_end(ctx
);
1753 static bool do_fop_dew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1754 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i32
))
1760 src
= load_frw0_i32(ra
);
1761 dst
= tcg_temp_new_i64();
1763 func(dst
, cpu_env
, src
);
1765 tcg_temp_free_i32(src
);
1767 tcg_temp_free_i64(dst
);
1768 return nullify_end(ctx
);
1771 static bool do_fop_weww(DisasContext
*ctx
, unsigned rt
,
1772 unsigned ra
, unsigned rb
,
1773 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
1778 a
= load_frw0_i32(ra
);
1779 b
= load_frw0_i32(rb
);
1781 func(a
, cpu_env
, a
, b
);
1783 tcg_temp_free_i32(b
);
1784 save_frw_i32(rt
, a
);
1785 tcg_temp_free_i32(a
);
1786 return nullify_end(ctx
);
1789 static bool do_fop_dedd(DisasContext
*ctx
, unsigned rt
,
1790 unsigned ra
, unsigned rb
,
1791 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
1799 func(a
, cpu_env
, a
, b
);
1801 tcg_temp_free_i64(b
);
1803 tcg_temp_free_i64(a
);
1804 return nullify_end(ctx
);
1807 /* Emit an unconditional branch to a direct target, which may or may not
1808 have already had nullification handled. */
1809 static bool do_dbranch(DisasContext
*ctx
, target_ureg dest
,
1810 unsigned link
, bool is_n
)
1812 if (ctx
->null_cond
.c
== TCG_COND_NEVER
&& ctx
->null_lab
== NULL
) {
1814 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1818 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1824 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1827 if (is_n
&& use_nullify_skip(ctx
)) {
1828 nullify_set(ctx
, 0);
1829 gen_goto_tb(ctx
, 0, dest
, dest
+ 4);
1831 nullify_set(ctx
, is_n
);
1832 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, dest
);
1837 nullify_set(ctx
, 0);
1838 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, ctx
->iaoq_n
);
1839 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1844 /* Emit a conditional branch to a direct target. If the branch itself
1845 is nullified, we should have already used nullify_over. */
1846 static bool do_cbranch(DisasContext
*ctx
, target_sreg disp
, bool is_n
,
1849 target_ureg dest
= iaoq_dest(ctx
, disp
);
1850 TCGLabel
*taken
= NULL
;
1851 TCGCond c
= cond
->c
;
1854 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1856 /* Handle TRUE and NEVER as direct branches. */
1857 if (c
== TCG_COND_ALWAYS
) {
1858 return do_dbranch(ctx
, dest
, 0, is_n
&& disp
>= 0);
1860 if (c
== TCG_COND_NEVER
) {
1861 return do_dbranch(ctx
, ctx
->iaoq_n
, 0, is_n
&& disp
< 0);
1864 taken
= gen_new_label();
1866 tcg_gen_brcond_reg(c
, cond
->a0
, cond
->a1
, taken
);
1869 /* Not taken: Condition not satisfied; nullify on backward branches. */
1870 n
= is_n
&& disp
< 0;
1871 if (n
&& use_nullify_skip(ctx
)) {
1872 nullify_set(ctx
, 0);
1873 gen_goto_tb(ctx
, 0, ctx
->iaoq_n
, ctx
->iaoq_n
+ 4);
1875 if (!n
&& ctx
->null_lab
) {
1876 gen_set_label(ctx
->null_lab
);
1877 ctx
->null_lab
= NULL
;
1879 nullify_set(ctx
, n
);
1880 if (ctx
->iaoq_n
== -1) {
1881 /* The temporary iaoq_n_var died at the branch above.
1882 Regenerate it here instead of saving it. */
1883 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
1885 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
1888 gen_set_label(taken
);
1890 /* Taken: Condition satisfied; nullify on forward branches. */
1891 n
= is_n
&& disp
>= 0;
1892 if (n
&& use_nullify_skip(ctx
)) {
1893 nullify_set(ctx
, 0);
1894 gen_goto_tb(ctx
, 1, dest
, dest
+ 4);
1896 nullify_set(ctx
, n
);
1897 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, dest
);
1900 /* Not taken: the branch itself was nullified. */
1901 if (ctx
->null_lab
) {
1902 gen_set_label(ctx
->null_lab
);
1903 ctx
->null_lab
= NULL
;
1904 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
1906 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1911 /* Emit an unconditional branch to an indirect target. This handles
1912 nullification of the branch itself. */
1913 static bool do_ibranch(DisasContext
*ctx
, TCGv_reg dest
,
1914 unsigned link
, bool is_n
)
1916 TCGv_reg a0
, a1
, next
, tmp
;
1919 assert(ctx
->null_lab
== NULL
);
1921 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
1923 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1925 next
= get_temp(ctx
);
1926 tcg_gen_mov_reg(next
, dest
);
1928 if (use_nullify_skip(ctx
)) {
1929 tcg_gen_mov_reg(cpu_iaoq_f
, next
);
1930 tcg_gen_addi_reg(cpu_iaoq_b
, next
, 4);
1931 nullify_set(ctx
, 0);
1932 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
1935 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1938 ctx
->iaoq_n_var
= next
;
1939 } else if (is_n
&& use_nullify_skip(ctx
)) {
1940 /* The (conditional) branch, B, nullifies the next insn, N,
1941 and we're allowed to skip execution N (no single-step or
1942 tracepoint in effect). Since the goto_ptr that we must use
1943 for the indirect branch consumes no special resources, we
1944 can (conditionally) skip B and continue execution. */
1945 /* The use_nullify_skip test implies we have a known control path. */
1946 tcg_debug_assert(ctx
->iaoq_b
!= -1);
1947 tcg_debug_assert(ctx
->iaoq_n
!= -1);
1949 /* We do have to handle the non-local temporary, DEST, before
1950 branching. Since IOAQ_F is not really live at this point, we
1951 can simply store DEST optimistically. Similarly with IAOQ_B. */
1952 tcg_gen_mov_reg(cpu_iaoq_f
, dest
);
1953 tcg_gen_addi_reg(cpu_iaoq_b
, dest
, 4);
1957 tcg_gen_movi_reg(cpu_gr
[link
], ctx
->iaoq_n
);
1959 tcg_gen_lookup_and_goto_ptr();
1960 return nullify_end(ctx
);
1962 cond_prep(&ctx
->null_cond
);
1963 c
= ctx
->null_cond
.c
;
1964 a0
= ctx
->null_cond
.a0
;
1965 a1
= ctx
->null_cond
.a1
;
1967 tmp
= tcg_temp_new();
1968 next
= get_temp(ctx
);
1970 copy_iaoq_entry(tmp
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1971 tcg_gen_movcond_reg(c
, next
, a0
, a1
, tmp
, dest
);
1973 ctx
->iaoq_n_var
= next
;
1976 tcg_gen_movcond_reg(c
, cpu_gr
[link
], a0
, a1
, cpu_gr
[link
], tmp
);
1980 /* The branch nullifies the next insn, which means the state of N
1981 after the branch is the inverse of the state of N that applied
1983 tcg_gen_setcond_reg(tcg_invert_cond(c
), cpu_psw_n
, a0
, a1
);
1984 cond_free(&ctx
->null_cond
);
1985 ctx
->null_cond
= cond_make_n();
1986 ctx
->psw_n_nonzero
= true;
1988 cond_free(&ctx
->null_cond
);
1995 * if (IAOQ_Front{30..31} < GR[b]{30..31})
1996 * IAOQ_Next{30..31} ← GR[b]{30..31};
1998 * IAOQ_Next{30..31} ← IAOQ_Front{30..31};
1999 * which keeps the privilege level from being increased.
2001 static TCGv_reg
do_ibranch_priv(DisasContext
*ctx
, TCGv_reg offset
)
2004 switch (ctx
->privilege
) {
2006 /* Privilege 0 is maximum and is allowed to decrease. */
2009 /* Privilege 3 is minimum and is never allowed to increase. */
2010 dest
= get_temp(ctx
);
2011 tcg_gen_ori_reg(dest
, offset
, 3);
2014 dest
= get_temp(ctx
);
2015 tcg_gen_andi_reg(dest
, offset
, -4);
2016 tcg_gen_ori_reg(dest
, dest
, ctx
->privilege
);
2017 tcg_gen_movcond_reg(TCG_COND_GTU
, dest
, dest
, offset
, dest
, offset
);
2023 #ifdef CONFIG_USER_ONLY
2024 /* On Linux, page zero is normally marked execute only + gateway.
2025 Therefore normal read or write is supposed to fail, but specific
2026 offsets have kernel code mapped to raise permissions to implement
2027 system calls. Handling this via an explicit check here, rather
2028 in than the "be disp(sr2,r0)" instruction that probably sent us
2029 here, is the easiest way to handle the branch delay slot on the
2030 aforementioned BE. */
2031 static void do_page_zero(DisasContext
*ctx
)
2033 /* If by some means we get here with PSW[N]=1, that implies that
2034 the B,GATE instruction would be skipped, and we'd fault on the
2035 next insn within the privilaged page. */
2036 switch (ctx
->null_cond
.c
) {
2037 case TCG_COND_NEVER
:
2039 case TCG_COND_ALWAYS
:
2040 tcg_gen_movi_reg(cpu_psw_n
, 0);
2043 /* Since this is always the first (and only) insn within the
2044 TB, we should know the state of PSW[N] from TB->FLAGS. */
2045 g_assert_not_reached();
2048 /* Check that we didn't arrive here via some means that allowed
2049 non-sequential instruction execution. Normally the PSW[B] bit
2050 detects this by disallowing the B,GATE instruction to execute
2051 under such conditions. */
2052 if (ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
2056 switch (ctx
->iaoq_f
& -4) {
2057 case 0x00: /* Null pointer call */
2058 gen_excp_1(EXCP_IMP
);
2059 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2062 case 0xb0: /* LWS */
2063 gen_excp_1(EXCP_SYSCALL_LWS
);
2064 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2067 case 0xe0: /* SET_THREAD_POINTER */
2068 tcg_gen_st_reg(cpu_gr
[26], cpu_env
, offsetof(CPUHPPAState
, cr
[27]));
2069 tcg_gen_ori_reg(cpu_iaoq_f
, cpu_gr
[31], 3);
2070 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
2071 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
2074 case 0x100: /* SYSCALL */
2075 gen_excp_1(EXCP_SYSCALL
);
2076 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2081 gen_excp_1(EXCP_ILL
);
2082 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2088 static bool trans_nop(DisasContext
*ctx
, arg_nop
*a
)
2090 cond_free(&ctx
->null_cond
);
2094 static bool trans_break(DisasContext
*ctx
, arg_break
*a
)
2096 return gen_excp_iir(ctx
, EXCP_BREAK
);
2099 static bool trans_sync(DisasContext
*ctx
, arg_sync
*a
)
2101 /* No point in nullifying the memory barrier. */
2102 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
2104 cond_free(&ctx
->null_cond
);
2108 static bool trans_mfia(DisasContext
*ctx
, arg_mfia
*a
)
2111 TCGv_reg tmp
= dest_gpr(ctx
, rt
);
2112 tcg_gen_movi_reg(tmp
, ctx
->iaoq_f
);
2113 save_gpr(ctx
, rt
, tmp
);
2115 cond_free(&ctx
->null_cond
);
2119 static bool trans_mfsp(DisasContext
*ctx
, arg_mfsp
*a
)
2122 unsigned rs
= a
->sp
;
2123 TCGv_i64 t0
= tcg_temp_new_i64();
2124 TCGv_reg t1
= tcg_temp_new();
2126 load_spr(ctx
, t0
, rs
);
2127 tcg_gen_shri_i64(t0
, t0
, 32);
2128 tcg_gen_trunc_i64_reg(t1
, t0
);
2130 save_gpr(ctx
, rt
, t1
);
2132 tcg_temp_free_i64(t0
);
2134 cond_free(&ctx
->null_cond
);
2138 static bool trans_mfctl(DisasContext
*ctx
, arg_mfctl
*a
)
2141 unsigned ctl
= a
->r
;
2146 #ifdef TARGET_HPPA64
2148 /* MFSAR without ,W masks low 5 bits. */
2149 tmp
= dest_gpr(ctx
, rt
);
2150 tcg_gen_andi_reg(tmp
, cpu_sar
, 31);
2151 save_gpr(ctx
, rt
, tmp
);
2155 save_gpr(ctx
, rt
, cpu_sar
);
2157 case CR_IT
: /* Interval Timer */
2158 /* FIXME: Respect PSW_S bit. */
2160 tmp
= dest_gpr(ctx
, rt
);
2161 if (tb_cflags(ctx
->base
.tb
) & CF_USE_ICOUNT
) {
2163 gen_helper_read_interval_timer(tmp
);
2164 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2166 gen_helper_read_interval_timer(tmp
);
2168 save_gpr(ctx
, rt
, tmp
);
2169 return nullify_end(ctx
);
2174 /* All other control registers are privileged. */
2175 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2179 tmp
= get_temp(ctx
);
2180 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2181 save_gpr(ctx
, rt
, tmp
);
2184 cond_free(&ctx
->null_cond
);
2188 static bool trans_mtsp(DisasContext
*ctx
, arg_mtsp
*a
)
2191 unsigned rs
= a
->sp
;
2195 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2199 t64
= tcg_temp_new_i64();
2200 tcg_gen_extu_reg_i64(t64
, load_gpr(ctx
, rr
));
2201 tcg_gen_shli_i64(t64
, t64
, 32);
2204 tcg_gen_st_i64(t64
, cpu_env
, offsetof(CPUHPPAState
, sr
[rs
]));
2205 ctx
->tb_flags
&= ~TB_FLAG_SR_SAME
;
2207 tcg_gen_mov_i64(cpu_sr
[rs
], t64
);
2209 tcg_temp_free_i64(t64
);
2211 return nullify_end(ctx
);
2214 static bool trans_mtctl(DisasContext
*ctx
, arg_mtctl
*a
)
2216 unsigned ctl
= a
->t
;
2217 TCGv_reg reg
= load_gpr(ctx
, a
->r
);
2220 if (ctl
== CR_SAR
) {
2221 tmp
= tcg_temp_new();
2222 tcg_gen_andi_reg(tmp
, reg
, TARGET_REGISTER_BITS
- 1);
2223 save_or_nullify(ctx
, cpu_sar
, tmp
);
2226 cond_free(&ctx
->null_cond
);
2230 /* All other control registers are privileged or read-only. */
2231 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2233 #ifndef CONFIG_USER_ONLY
2237 gen_helper_write_interval_timer(cpu_env
, reg
);
2240 gen_helper_write_eirr(cpu_env
, reg
);
2243 gen_helper_write_eiem(cpu_env
, reg
);
2244 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2249 /* FIXME: Respect PSW_Q bit */
2250 /* The write advances the queue and stores to the back element. */
2251 tmp
= get_temp(ctx
);
2252 tcg_gen_ld_reg(tmp
, cpu_env
,
2253 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2254 tcg_gen_st_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2255 tcg_gen_st_reg(reg
, cpu_env
,
2256 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2263 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2264 #ifndef CONFIG_USER_ONLY
2265 gen_helper_change_prot_id(cpu_env
);
2270 tcg_gen_st_reg(reg
, cpu_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2273 return nullify_end(ctx
);
2277 static bool trans_mtsarcm(DisasContext
*ctx
, arg_mtsarcm
*a
)
2279 TCGv_reg tmp
= tcg_temp_new();
2281 tcg_gen_not_reg(tmp
, load_gpr(ctx
, a
->r
));
2282 tcg_gen_andi_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
2283 save_or_nullify(ctx
, cpu_sar
, tmp
);
2286 cond_free(&ctx
->null_cond
);
2290 static bool trans_ldsid(DisasContext
*ctx
, arg_ldsid
*a
)
2292 TCGv_reg dest
= dest_gpr(ctx
, a
->t
);
2294 #ifdef CONFIG_USER_ONLY
2295 /* We don't implement space registers in user mode. */
2296 tcg_gen_movi_reg(dest
, 0);
2298 TCGv_i64 t0
= tcg_temp_new_i64();
2300 tcg_gen_mov_i64(t0
, space_select(ctx
, a
->sp
, load_gpr(ctx
, a
->b
)));
2301 tcg_gen_shri_i64(t0
, t0
, 32);
2302 tcg_gen_trunc_i64_reg(dest
, t0
);
2304 tcg_temp_free_i64(t0
);
2306 save_gpr(ctx
, a
->t
, dest
);
2308 cond_free(&ctx
->null_cond
);
2312 static bool trans_rsm(DisasContext
*ctx
, arg_rsm
*a
)
2314 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2315 #ifndef CONFIG_USER_ONLY
2320 tmp
= get_temp(ctx
);
2321 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2322 tcg_gen_andi_reg(tmp
, tmp
, ~a
->i
);
2323 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2324 save_gpr(ctx
, a
->t
, tmp
);
2326 /* Exit the TB to recognize new interrupts, e.g. PSW_M. */
2327 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2328 return nullify_end(ctx
);
2332 static bool trans_ssm(DisasContext
*ctx
, arg_ssm
*a
)
2334 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2335 #ifndef CONFIG_USER_ONLY
2340 tmp
= get_temp(ctx
);
2341 tcg_gen_ld_reg(tmp
, cpu_env
, offsetof(CPUHPPAState
, psw
));
2342 tcg_gen_ori_reg(tmp
, tmp
, a
->i
);
2343 gen_helper_swap_system_mask(tmp
, cpu_env
, tmp
);
2344 save_gpr(ctx
, a
->t
, tmp
);
2346 /* Exit the TB to recognize new interrupts, e.g. PSW_I. */
2347 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2348 return nullify_end(ctx
);
2352 static bool trans_mtsm(DisasContext
*ctx
, arg_mtsm
*a
)
2354 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2355 #ifndef CONFIG_USER_ONLY
2359 reg
= load_gpr(ctx
, a
->r
);
2360 tmp
= get_temp(ctx
);
2361 gen_helper_swap_system_mask(tmp
, cpu_env
, reg
);
2363 /* Exit the TB to recognize new interrupts. */
2364 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2365 return nullify_end(ctx
);
2369 static bool do_rfi(DisasContext
*ctx
, bool rfi_r
)
2371 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2372 #ifndef CONFIG_USER_ONLY
2376 gen_helper_rfi_r(cpu_env
);
2378 gen_helper_rfi(cpu_env
);
2380 /* Exit the TB to recognize new interrupts. */
2381 if (ctx
->base
.singlestep_enabled
) {
2382 gen_excp_1(EXCP_DEBUG
);
2384 tcg_gen_exit_tb(NULL
, 0);
2386 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2388 return nullify_end(ctx
);
2392 static bool trans_rfi(DisasContext
*ctx
, arg_rfi
*a
)
2394 return do_rfi(ctx
, false);
2397 static bool trans_rfi_r(DisasContext
*ctx
, arg_rfi_r
*a
)
2399 return do_rfi(ctx
, true);
2402 static bool trans_halt(DisasContext
*ctx
, arg_halt
*a
)
2404 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2405 #ifndef CONFIG_USER_ONLY
2407 gen_helper_halt(cpu_env
);
2408 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2409 return nullify_end(ctx
);
2413 static bool trans_reset(DisasContext
*ctx
, arg_reset
*a
)
2415 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2416 #ifndef CONFIG_USER_ONLY
2418 gen_helper_reset(cpu_env
);
2419 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2420 return nullify_end(ctx
);
2424 static bool trans_nop_addrx(DisasContext
*ctx
, arg_ldst
*a
)
2427 TCGv_reg dest
= dest_gpr(ctx
, a
->b
);
2428 TCGv_reg src1
= load_gpr(ctx
, a
->b
);
2429 TCGv_reg src2
= load_gpr(ctx
, a
->x
);
2431 /* The only thing we need to do is the base register modification. */
2432 tcg_gen_add_reg(dest
, src1
, src2
);
2433 save_gpr(ctx
, a
->b
, dest
);
2435 cond_free(&ctx
->null_cond
);
2439 static bool trans_probe(DisasContext
*ctx
, arg_probe
*a
)
2442 TCGv_i32 level
, want
;
2447 dest
= dest_gpr(ctx
, a
->t
);
2448 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2451 level
= tcg_const_i32(a
->ri
);
2453 level
= tcg_temp_new_i32();
2454 tcg_gen_trunc_reg_i32(level
, load_gpr(ctx
, a
->ri
));
2455 tcg_gen_andi_i32(level
, level
, 3);
2457 want
= tcg_const_i32(a
->write
? PAGE_WRITE
: PAGE_READ
);
2459 gen_helper_probe(dest
, cpu_env
, addr
, level
, want
);
2461 tcg_temp_free_i32(want
);
2462 tcg_temp_free_i32(level
);
2464 save_gpr(ctx
, a
->t
, dest
);
2465 return nullify_end(ctx
);
2468 static bool trans_ixtlbx(DisasContext
*ctx
, arg_ixtlbx
*a
)
2470 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2471 #ifndef CONFIG_USER_ONLY
2477 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2478 reg
= load_gpr(ctx
, a
->r
);
2480 gen_helper_itlba(cpu_env
, addr
, reg
);
2482 gen_helper_itlbp(cpu_env
, addr
, reg
);
2485 /* Exit TB for TLB change if mmu is enabled. */
2486 if (ctx
->tb_flags
& PSW_C
) {
2487 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2489 return nullify_end(ctx
);
2493 static bool trans_pxtlbx(DisasContext
*ctx
, arg_pxtlbx
*a
)
2495 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2496 #ifndef CONFIG_USER_ONLY
2502 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2504 save_gpr(ctx
, a
->b
, ofs
);
2507 gen_helper_ptlbe(cpu_env
);
2509 gen_helper_ptlb(cpu_env
, addr
);
2512 /* Exit TB for TLB change if mmu is enabled. */
2513 if (ctx
->tb_flags
& PSW_C
) {
2514 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2516 return nullify_end(ctx
);
2521 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2523 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2524 * page 13-9 (195/206)
2526 static bool trans_ixtlbxf(DisasContext
*ctx
, arg_ixtlbxf
*a
)
2528 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2529 #ifndef CONFIG_USER_ONLY
2530 TCGv_tl addr
, atl
, stl
;
2537 * if (not (pcxl or pcxl2))
2538 * return gen_illegal(ctx);
2540 * Note for future: these are 32-bit systems; no hppa64.
2543 atl
= tcg_temp_new_tl();
2544 stl
= tcg_temp_new_tl();
2545 addr
= tcg_temp_new_tl();
2547 tcg_gen_ld32u_i64(stl
, cpu_env
,
2548 a
->data
? offsetof(CPUHPPAState
, cr
[CR_ISR
])
2549 : offsetof(CPUHPPAState
, cr
[CR_IIASQ
]));
2550 tcg_gen_ld32u_i64(atl
, cpu_env
,
2551 a
->data
? offsetof(CPUHPPAState
, cr
[CR_IOR
])
2552 : offsetof(CPUHPPAState
, cr
[CR_IIAOQ
]));
2553 tcg_gen_shli_i64(stl
, stl
, 32);
2554 tcg_gen_or_tl(addr
, atl
, stl
);
2555 tcg_temp_free_tl(atl
);
2556 tcg_temp_free_tl(stl
);
2558 reg
= load_gpr(ctx
, a
->r
);
2560 gen_helper_itlba(cpu_env
, addr
, reg
);
2562 gen_helper_itlbp(cpu_env
, addr
, reg
);
2564 tcg_temp_free_tl(addr
);
2566 /* Exit TB for TLB change if mmu is enabled. */
2567 if (ctx
->tb_flags
& PSW_C
) {
2568 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2570 return nullify_end(ctx
);
2574 static bool trans_lpa(DisasContext
*ctx
, arg_ldst
*a
)
2576 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2577 #ifndef CONFIG_USER_ONLY
2579 TCGv_reg ofs
, paddr
;
2583 form_gva(ctx
, &vaddr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2585 paddr
= tcg_temp_new();
2586 gen_helper_lpa(paddr
, cpu_env
, vaddr
);
2588 /* Note that physical address result overrides base modification. */
2590 save_gpr(ctx
, a
->b
, ofs
);
2592 save_gpr(ctx
, a
->t
, paddr
);
2593 tcg_temp_free(paddr
);
2595 return nullify_end(ctx
);
2599 static bool trans_lci(DisasContext
*ctx
, arg_lci
*a
)
2603 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2605 /* The Coherence Index is an implementation-defined function of the
2606 physical address. Two addresses with the same CI have a coherent
2607 view of the cache. Our implementation is to return 0 for all,
2608 since the entire address space is coherent. */
2609 ci
= tcg_const_reg(0);
2610 save_gpr(ctx
, a
->t
, ci
);
2613 cond_free(&ctx
->null_cond
);
2617 static bool trans_add(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2619 return do_add_reg(ctx
, a
, false, false, false, false);
2622 static bool trans_add_l(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2624 return do_add_reg(ctx
, a
, true, false, false, false);
2627 static bool trans_add_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2629 return do_add_reg(ctx
, a
, false, true, false, false);
2632 static bool trans_add_c(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2634 return do_add_reg(ctx
, a
, false, false, false, true);
2637 static bool trans_add_c_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2639 return do_add_reg(ctx
, a
, false, true, false, true);
2642 static bool trans_sub(DisasContext
*ctx
, arg_rrr_cf
*a
)
2644 return do_sub_reg(ctx
, a
, false, false, false);
2647 static bool trans_sub_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2649 return do_sub_reg(ctx
, a
, true, false, false);
2652 static bool trans_sub_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2654 return do_sub_reg(ctx
, a
, false, false, true);
2657 static bool trans_sub_tsv_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2659 return do_sub_reg(ctx
, a
, true, false, true);
2662 static bool trans_sub_b(DisasContext
*ctx
, arg_rrr_cf
*a
)
2664 return do_sub_reg(ctx
, a
, false, true, false);
2667 static bool trans_sub_b_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2669 return do_sub_reg(ctx
, a
, true, true, false);
2672 static bool trans_andcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2674 return do_log_reg(ctx
, a
, tcg_gen_andc_reg
);
2677 static bool trans_and(DisasContext
*ctx
, arg_rrr_cf
*a
)
2679 return do_log_reg(ctx
, a
, tcg_gen_and_reg
);
2682 static bool trans_or(DisasContext
*ctx
, arg_rrr_cf
*a
)
2685 unsigned r2
= a
->r2
;
2686 unsigned r1
= a
->r1
;
2689 if (rt
== 0) { /* NOP */
2690 cond_free(&ctx
->null_cond
);
2693 if (r2
== 0) { /* COPY */
2695 TCGv_reg dest
= dest_gpr(ctx
, rt
);
2696 tcg_gen_movi_reg(dest
, 0);
2697 save_gpr(ctx
, rt
, dest
);
2699 save_gpr(ctx
, rt
, cpu_gr
[r1
]);
2701 cond_free(&ctx
->null_cond
);
2704 #ifndef CONFIG_USER_ONLY
2705 /* These are QEMU extensions and are nops in the real architecture:
2707 * or %r10,%r10,%r10 -- idle loop; wait for interrupt
2708 * or %r31,%r31,%r31 -- death loop; offline cpu
2709 * currently implemented as idle.
2711 if ((rt
== 10 || rt
== 31) && r1
== rt
&& r2
== rt
) { /* PAUSE */
2714 /* No need to check for supervisor, as userland can only pause
2715 until the next timer interrupt. */
2718 /* Advance the instruction queue. */
2719 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
2720 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
2721 nullify_set(ctx
, 0);
2723 /* Tell the qemu main loop to halt until this cpu has work. */
2724 tmp
= tcg_const_i32(1);
2725 tcg_gen_st_i32(tmp
, cpu_env
, -offsetof(HPPACPU
, env
) +
2726 offsetof(CPUState
, halted
));
2727 tcg_temp_free_i32(tmp
);
2728 gen_excp_1(EXCP_HALTED
);
2729 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2731 return nullify_end(ctx
);
2735 return do_log_reg(ctx
, a
, tcg_gen_or_reg
);
2738 static bool trans_xor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2740 return do_log_reg(ctx
, a
, tcg_gen_xor_reg
);
2743 static bool trans_cmpclr(DisasContext
*ctx
, arg_rrr_cf
*a
)
2745 TCGv_reg tcg_r1
, tcg_r2
;
2750 tcg_r1
= load_gpr(ctx
, a
->r1
);
2751 tcg_r2
= load_gpr(ctx
, a
->r2
);
2752 do_cmpclr(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
);
2753 return nullify_end(ctx
);
2756 static bool trans_uxor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2758 TCGv_reg tcg_r1
, tcg_r2
;
2763 tcg_r1
= load_gpr(ctx
, a
->r1
);
2764 tcg_r2
= load_gpr(ctx
, a
->r2
);
2765 do_unit(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, false, tcg_gen_xor_reg
);
2766 return nullify_end(ctx
);
2769 static bool do_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
, bool is_tc
)
2771 TCGv_reg tcg_r1
, tcg_r2
, tmp
;
2776 tcg_r1
= load_gpr(ctx
, a
->r1
);
2777 tcg_r2
= load_gpr(ctx
, a
->r2
);
2778 tmp
= get_temp(ctx
);
2779 tcg_gen_not_reg(tmp
, tcg_r2
);
2780 do_unit(ctx
, a
->t
, tcg_r1
, tmp
, a
->cf
, is_tc
, tcg_gen_add_reg
);
2781 return nullify_end(ctx
);
2784 static bool trans_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2786 return do_uaddcm(ctx
, a
, false);
2789 static bool trans_uaddcm_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2791 return do_uaddcm(ctx
, a
, true);
2794 static bool do_dcor(DisasContext
*ctx
, arg_rr_cf
*a
, bool is_i
)
2800 tmp
= get_temp(ctx
);
2801 tcg_gen_shri_reg(tmp
, cpu_psw_cb
, 3);
2803 tcg_gen_not_reg(tmp
, tmp
);
2805 tcg_gen_andi_reg(tmp
, tmp
, 0x11111111);
2806 tcg_gen_muli_reg(tmp
, tmp
, 6);
2807 do_unit(ctx
, a
->t
, load_gpr(ctx
, a
->r
), tmp
, a
->cf
, false,
2808 is_i
? tcg_gen_add_reg
: tcg_gen_sub_reg
);
2809 return nullify_end(ctx
);
2812 static bool trans_dcor(DisasContext
*ctx
, arg_rr_cf
*a
)
2814 return do_dcor(ctx
, a
, false);
2817 static bool trans_dcor_i(DisasContext
*ctx
, arg_rr_cf
*a
)
2819 return do_dcor(ctx
, a
, true);
2822 static bool trans_ds(DisasContext
*ctx
, arg_rrr_cf
*a
)
2824 TCGv_reg dest
, add1
, add2
, addc
, zero
, in1
, in2
;
2828 in1
= load_gpr(ctx
, a
->r1
);
2829 in2
= load_gpr(ctx
, a
->r2
);
2831 add1
= tcg_temp_new();
2832 add2
= tcg_temp_new();
2833 addc
= tcg_temp_new();
2834 dest
= tcg_temp_new();
2835 zero
= tcg_const_reg(0);
2837 /* Form R1 << 1 | PSW[CB]{8}. */
2838 tcg_gen_add_reg(add1
, in1
, in1
);
2839 tcg_gen_add_reg(add1
, add1
, cpu_psw_cb_msb
);
2841 /* Add or subtract R2, depending on PSW[V]. Proper computation of
2842 carry{8} requires that we subtract via + ~R2 + 1, as described in
2843 the manual. By extracting and masking V, we can produce the
2844 proper inputs to the addition without movcond. */
2845 tcg_gen_sari_reg(addc
, cpu_psw_v
, TARGET_REGISTER_BITS
- 1);
2846 tcg_gen_xor_reg(add2
, in2
, addc
);
2847 tcg_gen_andi_reg(addc
, addc
, 1);
2848 /* ??? This is only correct for 32-bit. */
2849 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, add1
, zero
, add2
, zero
);
2850 tcg_gen_add2_i32(dest
, cpu_psw_cb_msb
, dest
, cpu_psw_cb_msb
, addc
, zero
);
2852 tcg_temp_free(addc
);
2853 tcg_temp_free(zero
);
2855 /* Write back the result register. */
2856 save_gpr(ctx
, a
->t
, dest
);
2858 /* Write back PSW[CB]. */
2859 tcg_gen_xor_reg(cpu_psw_cb
, add1
, add2
);
2860 tcg_gen_xor_reg(cpu_psw_cb
, cpu_psw_cb
, dest
);
2862 /* Write back PSW[V] for the division step. */
2863 tcg_gen_neg_reg(cpu_psw_v
, cpu_psw_cb_msb
);
2864 tcg_gen_xor_reg(cpu_psw_v
, cpu_psw_v
, in2
);
2866 /* Install the new nullification. */
2869 if (cond_need_sv(a
->cf
>> 1)) {
2870 /* ??? The lshift is supposed to contribute to overflow. */
2871 sv
= do_add_sv(ctx
, dest
, add1
, add2
);
2873 ctx
->null_cond
= do_cond(a
->cf
, dest
, cpu_psw_cb_msb
, sv
);
2876 tcg_temp_free(add1
);
2877 tcg_temp_free(add2
);
2878 tcg_temp_free(dest
);
2880 return nullify_end(ctx
);
2883 static bool trans_addi(DisasContext
*ctx
, arg_rri_cf
*a
)
2885 return do_add_imm(ctx
, a
, false, false);
2888 static bool trans_addi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2890 return do_add_imm(ctx
, a
, true, false);
2893 static bool trans_addi_tc(DisasContext
*ctx
, arg_rri_cf
*a
)
2895 return do_add_imm(ctx
, a
, false, true);
2898 static bool trans_addi_tc_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2900 return do_add_imm(ctx
, a
, true, true);
2903 static bool trans_subi(DisasContext
*ctx
, arg_rri_cf
*a
)
2905 return do_sub_imm(ctx
, a
, false);
2908 static bool trans_subi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2910 return do_sub_imm(ctx
, a
, true);
2913 static bool trans_cmpiclr(DisasContext
*ctx
, arg_rri_cf
*a
)
2915 TCGv_reg tcg_im
, tcg_r2
;
2921 tcg_im
= load_const(ctx
, a
->i
);
2922 tcg_r2
= load_gpr(ctx
, a
->r
);
2923 do_cmpclr(ctx
, a
->t
, tcg_im
, tcg_r2
, a
->cf
);
2925 return nullify_end(ctx
);
2928 static bool trans_ld(DisasContext
*ctx
, arg_ldst
*a
)
2930 return do_load(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2931 a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2934 static bool trans_st(DisasContext
*ctx
, arg_ldst
*a
)
2936 assert(a
->x
== 0 && a
->scale
== 0);
2937 return do_store(ctx
, a
->t
, a
->b
, a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2940 static bool trans_ldc(DisasContext
*ctx
, arg_ldst
*a
)
2942 TCGMemOp mop
= MO_TEUL
| MO_ALIGN_16
| a
->size
;
2943 TCGv_reg zero
, dest
, ofs
;
2949 /* Base register modification. Make sure if RT == RB,
2950 we see the result of the load. */
2951 dest
= get_temp(ctx
);
2953 dest
= dest_gpr(ctx
, a
->t
);
2956 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2957 a
->disp
, a
->sp
, a
->m
, ctx
->mmu_idx
== MMU_PHYS_IDX
);
2958 zero
= tcg_const_reg(0);
2959 tcg_gen_atomic_xchg_reg(dest
, addr
, zero
, ctx
->mmu_idx
, mop
);
2961 save_gpr(ctx
, a
->b
, ofs
);
2963 save_gpr(ctx
, a
->t
, dest
);
2965 return nullify_end(ctx
);
2968 static bool trans_stby(DisasContext
*ctx
, arg_stby
*a
)
2975 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, a
->disp
, a
->sp
, a
->m
,
2976 ctx
->mmu_idx
== MMU_PHYS_IDX
);
2977 val
= load_gpr(ctx
, a
->r
);
2979 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2980 gen_helper_stby_e_parallel(cpu_env
, addr
, val
);
2982 gen_helper_stby_e(cpu_env
, addr
, val
);
2985 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2986 gen_helper_stby_b_parallel(cpu_env
, addr
, val
);
2988 gen_helper_stby_b(cpu_env
, addr
, val
);
2992 tcg_gen_andi_reg(ofs
, ofs
, ~3);
2993 save_gpr(ctx
, a
->b
, ofs
);
2996 return nullify_end(ctx
);
2999 static bool trans_lda(DisasContext
*ctx
, arg_ldst
*a
)
3001 int hold_mmu_idx
= ctx
->mmu_idx
;
3003 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
3004 ctx
->mmu_idx
= MMU_PHYS_IDX
;
3006 ctx
->mmu_idx
= hold_mmu_idx
;
3010 static bool trans_sta(DisasContext
*ctx
, arg_ldst
*a
)
3012 int hold_mmu_idx
= ctx
->mmu_idx
;
3014 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
3015 ctx
->mmu_idx
= MMU_PHYS_IDX
;
3017 ctx
->mmu_idx
= hold_mmu_idx
;
3021 static bool trans_ldil(DisasContext
*ctx
, arg_ldil
*a
)
3023 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
3025 tcg_gen_movi_reg(tcg_rt
, a
->i
);
3026 save_gpr(ctx
, a
->t
, tcg_rt
);
3027 cond_free(&ctx
->null_cond
);
3031 static bool trans_addil(DisasContext
*ctx
, arg_addil
*a
)
3033 TCGv_reg tcg_rt
= load_gpr(ctx
, a
->r
);
3034 TCGv_reg tcg_r1
= dest_gpr(ctx
, 1);
3036 tcg_gen_addi_reg(tcg_r1
, tcg_rt
, a
->i
);
3037 save_gpr(ctx
, 1, tcg_r1
);
3038 cond_free(&ctx
->null_cond
);
3042 static bool trans_ldo(DisasContext
*ctx
, arg_ldo
*a
)
3044 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
3046 /* Special case rb == 0, for the LDI pseudo-op.
3047 The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
3049 tcg_gen_movi_reg(tcg_rt
, a
->i
);
3051 tcg_gen_addi_reg(tcg_rt
, cpu_gr
[a
->b
], a
->i
);
3053 save_gpr(ctx
, a
->t
, tcg_rt
);
3054 cond_free(&ctx
->null_cond
);
3058 static bool do_cmpb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3059 unsigned c
, unsigned f
, unsigned n
, int disp
)
3061 TCGv_reg dest
, in2
, sv
;
3064 in2
= load_gpr(ctx
, r
);
3065 dest
= get_temp(ctx
);
3067 tcg_gen_sub_reg(dest
, in1
, in2
);
3070 if (cond_need_sv(c
)) {
3071 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
3074 cond
= do_sub_cond(c
* 2 + f
, dest
, in1
, in2
, sv
);
3075 return do_cbranch(ctx
, disp
, n
, &cond
);
3078 static bool trans_cmpb(DisasContext
*ctx
, arg_cmpb
*a
)
3081 return do_cmpb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3084 static bool trans_cmpbi(DisasContext
*ctx
, arg_cmpbi
*a
)
3087 return do_cmpb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3090 static bool do_addb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3091 unsigned c
, unsigned f
, unsigned n
, int disp
)
3093 TCGv_reg dest
, in2
, sv
, cb_msb
;
3096 in2
= load_gpr(ctx
, r
);
3097 dest
= tcg_temp_new();
3101 if (cond_need_cb(c
)) {
3102 cb_msb
= get_temp(ctx
);
3103 tcg_gen_movi_reg(cb_msb
, 0);
3104 tcg_gen_add2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, cb_msb
);
3106 tcg_gen_add_reg(dest
, in1
, in2
);
3108 if (cond_need_sv(c
)) {
3109 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
3112 cond
= do_cond(c
* 2 + f
, dest
, cb_msb
, sv
);
3113 save_gpr(ctx
, r
, dest
);
3114 tcg_temp_free(dest
);
3115 return do_cbranch(ctx
, disp
, n
, &cond
);
3118 static bool trans_addb(DisasContext
*ctx
, arg_addb
*a
)
3121 return do_addb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3124 static bool trans_addbi(DisasContext
*ctx
, arg_addbi
*a
)
3127 return do_addb(ctx
, a
->r
, load_const(ctx
, a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3130 static bool trans_bb_sar(DisasContext
*ctx
, arg_bb_sar
*a
)
3132 TCGv_reg tmp
, tcg_r
;
3137 tmp
= tcg_temp_new();
3138 tcg_r
= load_gpr(ctx
, a
->r
);
3139 tcg_gen_shl_reg(tmp
, tcg_r
, cpu_sar
);
3141 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3143 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3146 static bool trans_bb_imm(DisasContext
*ctx
, arg_bb_imm
*a
)
3148 TCGv_reg tmp
, tcg_r
;
3153 tmp
= tcg_temp_new();
3154 tcg_r
= load_gpr(ctx
, a
->r
);
3155 tcg_gen_shli_reg(tmp
, tcg_r
, a
->p
);
3157 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3159 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3162 static bool trans_movb(DisasContext
*ctx
, arg_movb
*a
)
3169 dest
= dest_gpr(ctx
, a
->r2
);
3171 tcg_gen_movi_reg(dest
, 0);
3173 tcg_gen_mov_reg(dest
, cpu_gr
[a
->r1
]);
3176 cond
= do_sed_cond(a
->c
, dest
);
3177 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3180 static bool trans_movbi(DisasContext
*ctx
, arg_movbi
*a
)
3187 dest
= dest_gpr(ctx
, a
->r
);
3188 tcg_gen_movi_reg(dest
, a
->i
);
3190 cond
= do_sed_cond(a
->c
, dest
);
3191 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3194 static bool trans_shrpw_sar(DisasContext
*ctx
, arg_shrpw_sar
*a
)
3202 dest
= dest_gpr(ctx
, a
->t
);
3204 tcg_gen_ext32u_reg(dest
, load_gpr(ctx
, a
->r2
));
3205 tcg_gen_shr_reg(dest
, dest
, cpu_sar
);
3206 } else if (a
->r1
== a
->r2
) {
3207 TCGv_i32 t32
= tcg_temp_new_i32();
3208 tcg_gen_trunc_reg_i32(t32
, load_gpr(ctx
, a
->r2
));
3209 tcg_gen_rotr_i32(t32
, t32
, cpu_sar
);
3210 tcg_gen_extu_i32_reg(dest
, t32
);
3211 tcg_temp_free_i32(t32
);
3213 TCGv_i64 t
= tcg_temp_new_i64();
3214 TCGv_i64 s
= tcg_temp_new_i64();
3216 tcg_gen_concat_reg_i64(t
, load_gpr(ctx
, a
->r2
), load_gpr(ctx
, a
->r1
));
3217 tcg_gen_extu_reg_i64(s
, cpu_sar
);
3218 tcg_gen_shr_i64(t
, t
, s
);
3219 tcg_gen_trunc_i64_reg(dest
, t
);
3221 tcg_temp_free_i64(t
);
3222 tcg_temp_free_i64(s
);
3224 save_gpr(ctx
, a
->t
, dest
);
3226 /* Install the new nullification. */
3227 cond_free(&ctx
->null_cond
);
3229 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3231 return nullify_end(ctx
);
3234 static bool trans_shrpw_imm(DisasContext
*ctx
, arg_shrpw_imm
*a
)
3236 unsigned sa
= 31 - a
->cpos
;
3243 dest
= dest_gpr(ctx
, a
->t
);
3244 t2
= load_gpr(ctx
, a
->r2
);
3245 if (a
->r1
== a
->r2
) {
3246 TCGv_i32 t32
= tcg_temp_new_i32();
3247 tcg_gen_trunc_reg_i32(t32
, t2
);
3248 tcg_gen_rotri_i32(t32
, t32
, sa
);
3249 tcg_gen_extu_i32_reg(dest
, t32
);
3250 tcg_temp_free_i32(t32
);
3251 } else if (a
->r1
== 0) {
3252 tcg_gen_extract_reg(dest
, t2
, sa
, 32 - sa
);
3254 TCGv_reg t0
= tcg_temp_new();
3255 tcg_gen_extract_reg(t0
, t2
, sa
, 32 - sa
);
3256 tcg_gen_deposit_reg(dest
, t0
, cpu_gr
[a
->r1
], 32 - sa
, sa
);
3259 save_gpr(ctx
, a
->t
, dest
);
3261 /* Install the new nullification. */
3262 cond_free(&ctx
->null_cond
);
3264 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3266 return nullify_end(ctx
);
3269 static bool trans_extrw_sar(DisasContext
*ctx
, arg_extrw_sar
*a
)
3271 unsigned len
= 32 - a
->clen
;
3272 TCGv_reg dest
, src
, tmp
;
3278 dest
= dest_gpr(ctx
, a
->t
);
3279 src
= load_gpr(ctx
, a
->r
);
3280 tmp
= tcg_temp_new();
3282 /* Recall that SAR is using big-endian bit numbering. */
3283 tcg_gen_xori_reg(tmp
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3285 tcg_gen_sar_reg(dest
, src
, tmp
);
3286 tcg_gen_sextract_reg(dest
, dest
, 0, len
);
3288 tcg_gen_shr_reg(dest
, src
, tmp
);
3289 tcg_gen_extract_reg(dest
, dest
, 0, len
);
3292 save_gpr(ctx
, a
->t
, dest
);
3294 /* Install the new nullification. */
3295 cond_free(&ctx
->null_cond
);
3297 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3299 return nullify_end(ctx
);
3302 static bool trans_extrw_imm(DisasContext
*ctx
, arg_extrw_imm
*a
)
3304 unsigned len
= 32 - a
->clen
;
3305 unsigned cpos
= 31 - a
->pos
;
3312 dest
= dest_gpr(ctx
, a
->t
);
3313 src
= load_gpr(ctx
, a
->r
);
3315 tcg_gen_sextract_reg(dest
, src
, cpos
, len
);
3317 tcg_gen_extract_reg(dest
, src
, cpos
, len
);
3319 save_gpr(ctx
, a
->t
, dest
);
3321 /* Install the new nullification. */
3322 cond_free(&ctx
->null_cond
);
3324 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3326 return nullify_end(ctx
);
3329 static bool trans_depwi_imm(DisasContext
*ctx
, arg_depwi_imm
*a
)
3331 unsigned len
= 32 - a
->clen
;
3332 target_sreg mask0
, mask1
;
3338 if (a
->cpos
+ len
> 32) {
3342 dest
= dest_gpr(ctx
, a
->t
);
3343 mask0
= deposit64(0, a
->cpos
, len
, a
->i
);
3344 mask1
= deposit64(-1, a
->cpos
, len
, a
->i
);
3347 TCGv_reg src
= load_gpr(ctx
, a
->t
);
3349 tcg_gen_andi_reg(dest
, src
, mask1
);
3352 tcg_gen_ori_reg(dest
, src
, mask0
);
3354 tcg_gen_movi_reg(dest
, mask0
);
3356 save_gpr(ctx
, a
->t
, dest
);
3358 /* Install the new nullification. */
3359 cond_free(&ctx
->null_cond
);
3361 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3363 return nullify_end(ctx
);
3366 static bool trans_depw_imm(DisasContext
*ctx
, arg_depw_imm
*a
)
3368 unsigned rs
= a
->nz
? a
->t
: 0;
3369 unsigned len
= 32 - a
->clen
;
3375 if (a
->cpos
+ len
> 32) {
3379 dest
= dest_gpr(ctx
, a
->t
);
3380 val
= load_gpr(ctx
, a
->r
);
3382 tcg_gen_deposit_z_reg(dest
, val
, a
->cpos
, len
);
3384 tcg_gen_deposit_reg(dest
, cpu_gr
[rs
], val
, a
->cpos
, len
);
3386 save_gpr(ctx
, a
->t
, dest
);
3388 /* Install the new nullification. */
3389 cond_free(&ctx
->null_cond
);
3391 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3393 return nullify_end(ctx
);
3396 static bool do_depw_sar(DisasContext
*ctx
, unsigned rt
, unsigned c
,
3397 unsigned nz
, unsigned clen
, TCGv_reg val
)
3399 unsigned rs
= nz
? rt
: 0;
3400 unsigned len
= 32 - clen
;
3401 TCGv_reg mask
, tmp
, shift
, dest
;
3402 unsigned msb
= 1U << (len
- 1);
3408 dest
= dest_gpr(ctx
, rt
);
3409 shift
= tcg_temp_new();
3410 tmp
= tcg_temp_new();
3412 /* Convert big-endian bit numbering in SAR to left-shift. */
3413 tcg_gen_xori_reg(shift
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3415 mask
= tcg_const_reg(msb
+ (msb
- 1));
3416 tcg_gen_and_reg(tmp
, val
, mask
);
3418 tcg_gen_shl_reg(mask
, mask
, shift
);
3419 tcg_gen_shl_reg(tmp
, tmp
, shift
);
3420 tcg_gen_andc_reg(dest
, cpu_gr
[rs
], mask
);
3421 tcg_gen_or_reg(dest
, dest
, tmp
);
3423 tcg_gen_shl_reg(dest
, tmp
, shift
);
3425 tcg_temp_free(shift
);
3426 tcg_temp_free(mask
);
3428 save_gpr(ctx
, rt
, dest
);
3430 /* Install the new nullification. */
3431 cond_free(&ctx
->null_cond
);
3433 ctx
->null_cond
= do_sed_cond(c
, dest
);
3435 return nullify_end(ctx
);
3438 static bool trans_depw_sar(DisasContext
*ctx
, arg_depw_sar
*a
)
3440 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_gpr(ctx
, a
->r
));
3443 static bool trans_depwi_sar(DisasContext
*ctx
, arg_depwi_sar
*a
)
3445 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_const(ctx
, a
->i
));
3448 static bool trans_be(DisasContext
*ctx
, arg_be
*a
)
3452 #ifdef CONFIG_USER_ONLY
3453 /* ??? It seems like there should be a good way of using
3454 "be disp(sr2, r0)", the canonical gateway entry mechanism
3455 to our advantage. But that appears to be inconvenient to
3456 manage along side branch delay slots. Therefore we handle
3457 entry into the gateway page via absolute address. */
3458 /* Since we don't implement spaces, just branch. Do notice the special
3459 case of "be disp(*,r0)" using a direct branch to disp, so that we can
3460 goto_tb to the TB containing the syscall. */
3462 return do_dbranch(ctx
, a
->disp
, a
->l
, a
->n
);
3468 tmp
= get_temp(ctx
);
3469 tcg_gen_addi_reg(tmp
, load_gpr(ctx
, a
->b
), a
->disp
);
3470 tmp
= do_ibranch_priv(ctx
, tmp
);
3472 #ifdef CONFIG_USER_ONLY
3473 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3475 TCGv_i64 new_spc
= tcg_temp_new_i64();
3477 load_spr(ctx
, new_spc
, a
->sp
);
3479 copy_iaoq_entry(cpu_gr
[31], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3480 tcg_gen_mov_i64(cpu_sr
[0], cpu_iasq_f
);
3482 if (a
->n
&& use_nullify_skip(ctx
)) {
3483 tcg_gen_mov_reg(cpu_iaoq_f
, tmp
);
3484 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
3485 tcg_gen_mov_i64(cpu_iasq_f
, new_spc
);
3486 tcg_gen_mov_i64(cpu_iasq_b
, cpu_iasq_f
);
3488 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3489 if (ctx
->iaoq_b
== -1) {
3490 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3492 tcg_gen_mov_reg(cpu_iaoq_b
, tmp
);
3493 tcg_gen_mov_i64(cpu_iasq_b
, new_spc
);
3494 nullify_set(ctx
, a
->n
);
3496 tcg_temp_free_i64(new_spc
);
3497 tcg_gen_lookup_and_goto_ptr();
3498 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3499 return nullify_end(ctx
);
3503 static bool trans_bl(DisasContext
*ctx
, arg_bl
*a
)
3505 return do_dbranch(ctx
, iaoq_dest(ctx
, a
->disp
), a
->l
, a
->n
);
3508 static bool trans_b_gate(DisasContext
*ctx
, arg_b_gate
*a
)
3510 target_ureg dest
= iaoq_dest(ctx
, a
->disp
);
3514 /* Make sure the caller hasn't done something weird with the queue.
3515 * ??? This is not quite the same as the PSW[B] bit, which would be
3516 * expensive to track. Real hardware will trap for
3518 * b gateway+4 (in delay slot of first branch)
3519 * However, checking for a non-sequential instruction queue *will*
3520 * diagnose the security hole
3523 * in which instructions at evil would run with increased privs.
3525 if (ctx
->iaoq_b
== -1 || ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
3526 return gen_illegal(ctx
);
3529 #ifndef CONFIG_USER_ONLY
3530 if (ctx
->tb_flags
& PSW_C
) {
3531 CPUHPPAState
*env
= ctx
->cs
->env_ptr
;
3532 int type
= hppa_artype_for_page(env
, ctx
->base
.pc_next
);
3533 /* If we could not find a TLB entry, then we need to generate an
3534 ITLB miss exception so the kernel will provide it.
3535 The resulting TLB fill operation will invalidate this TB and
3536 we will re-translate, at which point we *will* be able to find
3537 the TLB entry and determine if this is in fact a gateway page. */
3539 gen_excp(ctx
, EXCP_ITLB_MISS
);
3542 /* No change for non-gateway pages or for priv decrease. */
3543 if (type
>= 4 && type
- 4 < ctx
->privilege
) {
3544 dest
= deposit32(dest
, 0, 2, type
- 4);
3547 dest
&= -4; /* priv = 0 */
3552 TCGv_reg tmp
= dest_gpr(ctx
, a
->l
);
3553 if (ctx
->privilege
< 3) {
3554 tcg_gen_andi_reg(tmp
, tmp
, -4);
3556 tcg_gen_ori_reg(tmp
, tmp
, ctx
->privilege
);
3557 save_gpr(ctx
, a
->l
, tmp
);
3560 return do_dbranch(ctx
, dest
, 0, a
->n
);
3563 static bool trans_blr(DisasContext
*ctx
, arg_blr
*a
)
3566 TCGv_reg tmp
= get_temp(ctx
);
3567 tcg_gen_shli_reg(tmp
, load_gpr(ctx
, a
->x
), 3);
3568 tcg_gen_addi_reg(tmp
, tmp
, ctx
->iaoq_f
+ 8);
3569 /* The computation here never changes privilege level. */
3570 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3572 /* BLR R0,RX is a good way to load PC+8 into RX. */
3573 return do_dbranch(ctx
, ctx
->iaoq_f
+ 8, a
->l
, a
->n
);
3577 static bool trans_bv(DisasContext
*ctx
, arg_bv
*a
)
3582 dest
= load_gpr(ctx
, a
->b
);
3584 dest
= get_temp(ctx
);
3585 tcg_gen_shli_reg(dest
, load_gpr(ctx
, a
->x
), 3);
3586 tcg_gen_add_reg(dest
, dest
, load_gpr(ctx
, a
->b
));
3588 dest
= do_ibranch_priv(ctx
, dest
);
3589 return do_ibranch(ctx
, dest
, 0, a
->n
);
3592 static bool trans_bve(DisasContext
*ctx
, arg_bve
*a
)
3596 #ifdef CONFIG_USER_ONLY
3597 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3598 return do_ibranch(ctx
, dest
, a
->l
, a
->n
);
3601 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3603 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3604 if (ctx
->iaoq_b
== -1) {
3605 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3607 copy_iaoq_entry(cpu_iaoq_b
, -1, dest
);
3608 tcg_gen_mov_i64(cpu_iasq_b
, space_select(ctx
, 0, dest
));
3610 copy_iaoq_entry(cpu_gr
[a
->l
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3612 nullify_set(ctx
, a
->n
);
3613 tcg_gen_lookup_and_goto_ptr();
3614 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3615 return nullify_end(ctx
);
3623 static void gen_fcpy_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3625 tcg_gen_mov_i32(dst
, src
);
3628 static bool trans_fcpy_f(DisasContext
*ctx
, arg_fclass01
*a
)
3630 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fcpy_f
);
3633 static void gen_fcpy_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3635 tcg_gen_mov_i64(dst
, src
);
3638 static bool trans_fcpy_d(DisasContext
*ctx
, arg_fclass01
*a
)
3640 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fcpy_d
);
3643 static void gen_fabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3645 tcg_gen_andi_i32(dst
, src
, INT32_MAX
);
3648 static bool trans_fabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3650 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fabs_f
);
3653 static void gen_fabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3655 tcg_gen_andi_i64(dst
, src
, INT64_MAX
);
3658 static bool trans_fabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3660 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fabs_d
);
3663 static bool trans_fsqrt_f(DisasContext
*ctx
, arg_fclass01
*a
)
3665 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_s
);
3668 static bool trans_fsqrt_d(DisasContext
*ctx
, arg_fclass01
*a
)
3670 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_d
);
3673 static bool trans_frnd_f(DisasContext
*ctx
, arg_fclass01
*a
)
3675 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_frnd_s
);
3678 static bool trans_frnd_d(DisasContext
*ctx
, arg_fclass01
*a
)
3680 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_frnd_d
);
3683 static void gen_fneg_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3685 tcg_gen_xori_i32(dst
, src
, INT32_MIN
);
3688 static bool trans_fneg_f(DisasContext
*ctx
, arg_fclass01
*a
)
3690 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fneg_f
);
3693 static void gen_fneg_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3695 tcg_gen_xori_i64(dst
, src
, INT64_MIN
);
3698 static bool trans_fneg_d(DisasContext
*ctx
, arg_fclass01
*a
)
3700 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fneg_d
);
3703 static void gen_fnegabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3705 tcg_gen_ori_i32(dst
, src
, INT32_MIN
);
3708 static bool trans_fnegabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3710 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fnegabs_f
);
3713 static void gen_fnegabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3715 tcg_gen_ori_i64(dst
, src
, INT64_MIN
);
3718 static bool trans_fnegabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3720 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fnegabs_d
);
3727 static bool trans_fcnv_d_f(DisasContext
*ctx
, arg_fclass01
*a
)
3729 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_s
);
3732 static bool trans_fcnv_f_d(DisasContext
*ctx
, arg_fclass01
*a
)
3734 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_d
);
3737 static bool trans_fcnv_w_f(DisasContext
*ctx
, arg_fclass01
*a
)
3739 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_s
);
3742 static bool trans_fcnv_q_f(DisasContext
*ctx
, arg_fclass01
*a
)
3744 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_s
);
3747 static bool trans_fcnv_w_d(DisasContext
*ctx
, arg_fclass01
*a
)
3749 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_d
);
3752 static bool trans_fcnv_q_d(DisasContext
*ctx
, arg_fclass01
*a
)
3754 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_d
);
3757 static bool trans_fcnv_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3759 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_w
);
3762 static bool trans_fcnv_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3764 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_w
);
3767 static bool trans_fcnv_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3769 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_dw
);
3772 static bool trans_fcnv_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3774 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_dw
);
3777 static bool trans_fcnv_t_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3779 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_w
);
3782 static bool trans_fcnv_t_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3784 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_w
);
3787 static bool trans_fcnv_t_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3789 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_dw
);
3792 static bool trans_fcnv_t_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3794 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_dw
);
3797 static bool trans_fcnv_uw_f(DisasContext
*ctx
, arg_fclass01
*a
)
3799 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_s
);
3802 static bool trans_fcnv_uq_f(DisasContext
*ctx
, arg_fclass01
*a
)
3804 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_s
);
3807 static bool trans_fcnv_uw_d(DisasContext
*ctx
, arg_fclass01
*a
)
3809 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_d
);
3812 static bool trans_fcnv_uq_d(DisasContext
*ctx
, arg_fclass01
*a
)
3814 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_d
);
3817 static bool trans_fcnv_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3819 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_uw
);
3822 static bool trans_fcnv_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3824 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_uw
);
3827 static bool trans_fcnv_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3829 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_udw
);
3832 static bool trans_fcnv_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3834 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_udw
);
3837 static bool trans_fcnv_t_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3839 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_uw
);
3842 static bool trans_fcnv_t_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3844 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_uw
);
3847 static bool trans_fcnv_t_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3849 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_udw
);
3852 static bool trans_fcnv_t_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3854 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_udw
);
3861 static bool trans_fcmp_f(DisasContext
*ctx
, arg_fclass2
*a
)
3863 TCGv_i32 ta
, tb
, tc
, ty
;
3867 ta
= load_frw0_i32(a
->r1
);
3868 tb
= load_frw0_i32(a
->r2
);
3869 ty
= tcg_const_i32(a
->y
);
3870 tc
= tcg_const_i32(a
->c
);
3872 gen_helper_fcmp_s(cpu_env
, ta
, tb
, ty
, tc
);
3874 tcg_temp_free_i32(ta
);
3875 tcg_temp_free_i32(tb
);
3876 tcg_temp_free_i32(ty
);
3877 tcg_temp_free_i32(tc
);
3879 return nullify_end(ctx
);
3882 static bool trans_fcmp_d(DisasContext
*ctx
, arg_fclass2
*a
)
3889 ta
= load_frd0(a
->r1
);
3890 tb
= load_frd0(a
->r2
);
3891 ty
= tcg_const_i32(a
->y
);
3892 tc
= tcg_const_i32(a
->c
);
3894 gen_helper_fcmp_d(cpu_env
, ta
, tb
, ty
, tc
);
3896 tcg_temp_free_i64(ta
);
3897 tcg_temp_free_i64(tb
);
3898 tcg_temp_free_i32(ty
);
3899 tcg_temp_free_i32(tc
);
3901 return nullify_end(ctx
);
3904 static bool trans_ftest(DisasContext
*ctx
, arg_ftest
*a
)
3911 tcg_gen_ld32u_reg(t
, cpu_env
, offsetof(CPUHPPAState
, fr0_shadow
));
3918 case 0: /* simple */
3919 tcg_gen_andi_reg(t
, t
, 0x4000000);
3920 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3948 TCGv_reg c
= load_const(ctx
, mask
);
3949 tcg_gen_or_reg(t
, t
, c
);
3950 ctx
->null_cond
= cond_make(TCG_COND_EQ
, t
, c
);
3952 tcg_gen_andi_reg(t
, t
, mask
);
3953 ctx
->null_cond
= cond_make_0(TCG_COND_EQ
, t
);
3956 unsigned cbit
= (a
->y
^ 1) - 1;
3958 tcg_gen_extract_reg(t
, t
, 21 - cbit
, 1);
3959 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3964 return nullify_end(ctx
);
3971 static bool trans_fadd_f(DisasContext
*ctx
, arg_fclass3
*a
)
3973 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_s
);
3976 static bool trans_fadd_d(DisasContext
*ctx
, arg_fclass3
*a
)
3978 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_d
);
3981 static bool trans_fsub_f(DisasContext
*ctx
, arg_fclass3
*a
)
3983 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_s
);
3986 static bool trans_fsub_d(DisasContext
*ctx
, arg_fclass3
*a
)
3988 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_d
);
3991 static bool trans_fmpy_f(DisasContext
*ctx
, arg_fclass3
*a
)
3993 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_s
);
3996 static bool trans_fmpy_d(DisasContext
*ctx
, arg_fclass3
*a
)
3998 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_d
);
4001 static bool trans_fdiv_f(DisasContext
*ctx
, arg_fclass3
*a
)
4003 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_s
);
4006 static bool trans_fdiv_d(DisasContext
*ctx
, arg_fclass3
*a
)
4008 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_d
);
4011 static bool trans_xmpyu(DisasContext
*ctx
, arg_xmpyu
*a
)
4017 x
= load_frw0_i64(a
->r1
);
4018 y
= load_frw0_i64(a
->r2
);
4019 tcg_gen_mul_i64(x
, x
, y
);
4021 tcg_temp_free_i64(x
);
4022 tcg_temp_free_i64(y
);
4024 return nullify_end(ctx
);
4027 /* Convert the fmpyadd single-precision register encodings to standard. */
4028 static inline int fmpyadd_s_reg(unsigned r
)
4030 return (r
& 16) * 2 + 16 + (r
& 15);
4033 static bool do_fmpyadd_s(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4035 int tm
= fmpyadd_s_reg(a
->tm
);
4036 int ra
= fmpyadd_s_reg(a
->ra
);
4037 int ta
= fmpyadd_s_reg(a
->ta
);
4038 int rm2
= fmpyadd_s_reg(a
->rm2
);
4039 int rm1
= fmpyadd_s_reg(a
->rm1
);
4043 do_fop_weww(ctx
, tm
, rm1
, rm2
, gen_helper_fmpy_s
);
4044 do_fop_weww(ctx
, ta
, ta
, ra
,
4045 is_sub
? gen_helper_fsub_s
: gen_helper_fadd_s
);
4047 return nullify_end(ctx
);
4050 static bool trans_fmpyadd_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4052 return do_fmpyadd_s(ctx
, a
, false);
4055 static bool trans_fmpysub_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4057 return do_fmpyadd_s(ctx
, a
, true);
4060 static bool do_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4064 do_fop_dedd(ctx
, a
->tm
, a
->rm1
, a
->rm2
, gen_helper_fmpy_d
);
4065 do_fop_dedd(ctx
, a
->ta
, a
->ta
, a
->ra
,
4066 is_sub
? gen_helper_fsub_d
: gen_helper_fadd_d
);
4068 return nullify_end(ctx
);
4071 static bool trans_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4073 return do_fmpyadd_d(ctx
, a
, false);
4076 static bool trans_fmpysub_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4078 return do_fmpyadd_d(ctx
, a
, true);
4081 static bool trans_fmpyfadd_f(DisasContext
*ctx
, arg_fmpyfadd_f
*a
)
4086 x
= load_frw0_i32(a
->rm1
);
4087 y
= load_frw0_i32(a
->rm2
);
4088 z
= load_frw0_i32(a
->ra3
);
4091 gen_helper_fmpynfadd_s(x
, cpu_env
, x
, y
, z
);
4093 gen_helper_fmpyfadd_s(x
, cpu_env
, x
, y
, z
);
4096 tcg_temp_free_i32(y
);
4097 tcg_temp_free_i32(z
);
4098 save_frw_i32(a
->t
, x
);
4099 tcg_temp_free_i32(x
);
4100 return nullify_end(ctx
);
4103 static bool trans_fmpyfadd_d(DisasContext
*ctx
, arg_fmpyfadd_d
*a
)
4108 x
= load_frd0(a
->rm1
);
4109 y
= load_frd0(a
->rm2
);
4110 z
= load_frd0(a
->ra3
);
4113 gen_helper_fmpynfadd_d(x
, cpu_env
, x
, y
, z
);
4115 gen_helper_fmpyfadd_d(x
, cpu_env
, x
, y
, z
);
4118 tcg_temp_free_i64(y
);
4119 tcg_temp_free_i64(z
);
4121 tcg_temp_free_i64(x
);
4122 return nullify_end(ctx
);
4125 static bool trans_diag(DisasContext
*ctx
, arg_diag
*a
)
4127 qemu_log_mask(LOG_UNIMP
, "DIAG opcode ignored\n");
4128 cond_free(&ctx
->null_cond
);
4132 static void hppa_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
4134 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4138 ctx
->tb_flags
= ctx
->base
.tb
->flags
;
4140 #ifdef CONFIG_USER_ONLY
4141 ctx
->privilege
= MMU_USER_IDX
;
4142 ctx
->mmu_idx
= MMU_USER_IDX
;
4143 ctx
->iaoq_f
= ctx
->base
.pc_first
| MMU_USER_IDX
;
4144 ctx
->iaoq_b
= ctx
->base
.tb
->cs_base
| MMU_USER_IDX
;
4146 ctx
->privilege
= (ctx
->tb_flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
4147 ctx
->mmu_idx
= (ctx
->tb_flags
& PSW_D
? ctx
->privilege
: MMU_PHYS_IDX
);
4149 /* Recover the IAOQ values from the GVA + PRIV. */
4150 uint64_t cs_base
= ctx
->base
.tb
->cs_base
;
4151 uint64_t iasq_f
= cs_base
& ~0xffffffffull
;
4152 int32_t diff
= cs_base
;
4154 ctx
->iaoq_f
= (ctx
->base
.pc_first
& ~iasq_f
) + ctx
->privilege
;
4155 ctx
->iaoq_b
= (diff
? ctx
->iaoq_f
+ diff
: -1);
4158 ctx
->iaoq_n_var
= NULL
;
4160 /* Bound the number of instructions by those left on the page. */
4161 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
4162 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
4166 memset(ctx
->tempr
, 0, sizeof(ctx
->tempr
));
4167 memset(ctx
->templ
, 0, sizeof(ctx
->templ
));
4170 static void hppa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4172 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4174 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */
4175 ctx
->null_cond
= cond_make_f();
4176 ctx
->psw_n_nonzero
= false;
4177 if (ctx
->tb_flags
& PSW_N
) {
4178 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
4179 ctx
->psw_n_nonzero
= true;
4181 ctx
->null_lab
= NULL
;
4184 static void hppa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4186 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4188 tcg_gen_insn_start(ctx
->iaoq_f
, ctx
->iaoq_b
);
4191 static bool hppa_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cs
,
4192 const CPUBreakpoint
*bp
)
4194 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4196 gen_excp(ctx
, EXCP_DEBUG
);
4197 ctx
->base
.pc_next
+= 4;
4201 static void hppa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
4203 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4204 CPUHPPAState
*env
= cs
->env_ptr
;
4208 /* Execute one insn. */
4209 #ifdef CONFIG_USER_ONLY
4210 if (ctx
->base
.pc_next
< TARGET_PAGE_SIZE
) {
4212 ret
= ctx
->base
.is_jmp
;
4213 assert(ret
!= DISAS_NEXT
);
4217 /* Always fetch the insn, even if nullified, so that we check
4218 the page permissions for execute. */
4219 uint32_t insn
= cpu_ldl_code(env
, ctx
->base
.pc_next
);
4221 /* Set up the IA queue for the next insn.
4222 This will be overwritten by a branch. */
4223 if (ctx
->iaoq_b
== -1) {
4225 ctx
->iaoq_n_var
= get_temp(ctx
);
4226 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
4228 ctx
->iaoq_n
= ctx
->iaoq_b
+ 4;
4229 ctx
->iaoq_n_var
= NULL
;
4232 if (unlikely(ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4233 ctx
->null_cond
.c
= TCG_COND_NEVER
;
4237 if (!decode(ctx
, insn
)) {
4240 ret
= ctx
->base
.is_jmp
;
4241 assert(ctx
->null_lab
== NULL
);
4245 /* Free any temporaries allocated. */
4246 for (i
= 0, n
= ctx
->ntempr
; i
< n
; ++i
) {
4247 tcg_temp_free(ctx
->tempr
[i
]);
4248 ctx
->tempr
[i
] = NULL
;
4250 for (i
= 0, n
= ctx
->ntempl
; i
< n
; ++i
) {
4251 tcg_temp_free_tl(ctx
->templ
[i
]);
4252 ctx
->templ
[i
] = NULL
;
4257 /* Advance the insn queue. Note that this check also detects
4258 a priority change within the instruction queue. */
4259 if (ret
== DISAS_NEXT
&& ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
4260 if (ctx
->iaoq_b
!= -1 && ctx
->iaoq_n
!= -1
4261 && use_goto_tb(ctx
, ctx
->iaoq_b
)
4262 && (ctx
->null_cond
.c
== TCG_COND_NEVER
4263 || ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4264 nullify_set(ctx
, ctx
->null_cond
.c
== TCG_COND_ALWAYS
);
4265 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
4266 ctx
->base
.is_jmp
= ret
= DISAS_NORETURN
;
4268 ctx
->base
.is_jmp
= ret
= DISAS_IAQ_N_STALE
;
4271 ctx
->iaoq_f
= ctx
->iaoq_b
;
4272 ctx
->iaoq_b
= ctx
->iaoq_n
;
4273 ctx
->base
.pc_next
+= 4;
4276 case DISAS_NORETURN
:
4277 case DISAS_IAQ_N_UPDATED
:
4281 case DISAS_IAQ_N_STALE
:
4282 case DISAS_IAQ_N_STALE_EXIT
:
4283 if (ctx
->iaoq_f
== -1) {
4284 tcg_gen_mov_reg(cpu_iaoq_f
, cpu_iaoq_b
);
4285 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
4286 #ifndef CONFIG_USER_ONLY
4287 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
4290 ctx
->base
.is_jmp
= (ret
== DISAS_IAQ_N_STALE_EXIT
4292 : DISAS_IAQ_N_UPDATED
);
4293 } else if (ctx
->iaoq_b
== -1) {
4294 tcg_gen_mov_reg(cpu_iaoq_b
, ctx
->iaoq_n_var
);
4299 g_assert_not_reached();
4303 static void hppa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
4305 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4306 DisasJumpType is_jmp
= ctx
->base
.is_jmp
;
4309 case DISAS_NORETURN
:
4311 case DISAS_TOO_MANY
:
4312 case DISAS_IAQ_N_STALE
:
4313 case DISAS_IAQ_N_STALE_EXIT
:
4314 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
4315 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
4318 case DISAS_IAQ_N_UPDATED
:
4319 if (ctx
->base
.singlestep_enabled
) {
4320 gen_excp_1(EXCP_DEBUG
);
4321 } else if (is_jmp
!= DISAS_IAQ_N_STALE_EXIT
) {
4322 tcg_gen_lookup_and_goto_ptr();
4326 tcg_gen_exit_tb(NULL
, 0);
4329 g_assert_not_reached();
4333 static void hppa_tr_disas_log(const DisasContextBase
*dcbase
, CPUState
*cs
)
4335 target_ulong pc
= dcbase
->pc_first
;
4337 #ifdef CONFIG_USER_ONLY
4340 qemu_log("IN:\n0x00000000: (null)\n");
4343 qemu_log("IN:\n0x000000b0: light-weight-syscall\n");
4346 qemu_log("IN:\n0x000000e0: set-thread-pointer-syscall\n");
4349 qemu_log("IN:\n0x00000100: syscall\n");
4354 qemu_log("IN: %s\n", lookup_symbol(pc
));
4355 log_target_disas(cs
, pc
, dcbase
->tb
->size
);
4358 static const TranslatorOps hppa_tr_ops
= {
4359 .init_disas_context
= hppa_tr_init_disas_context
,
4360 .tb_start
= hppa_tr_tb_start
,
4361 .insn_start
= hppa_tr_insn_start
,
4362 .breakpoint_check
= hppa_tr_breakpoint_check
,
4363 .translate_insn
= hppa_tr_translate_insn
,
4364 .tb_stop
= hppa_tr_tb_stop
,
4365 .disas_log
= hppa_tr_disas_log
,
4368 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int max_insns
)
4371 translator_loop(&hppa_tr_ops
, &ctx
.base
, cs
, tb
, max_insns
);
4374 void restore_state_to_opc(CPUHPPAState
*env
, TranslationBlock
*tb
,
4377 env
->iaoq_f
= data
[0];
4378 if (data
[1] != (target_ureg
)-1) {
4379 env
->iaoq_b
= data
[1];
4381 /* Since we were executing the instruction at IAOQ_F, and took some
4382 sort of action that provoked the cpu_restore_state, we can infer
4383 that the instruction was not nullified. */