2 * HPPA emulation cpu translation for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "disas/disas.h"
23 #include "qemu/host-utils.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28 #include "exec/translator.h"
31 #define HELPER_H "helper.h"
32 #include "exec/helper-info.c.inc"
36 /* Since we have a distinction between register size and address size,
37 we need to redefine all of these. */
41 #undef tcg_global_mem_new
43 #if TARGET_LONG_BITS == 64
44 #define TCGv_tl TCGv_i64
45 #define tcg_temp_new_tl tcg_temp_new_i64
46 #if TARGET_REGISTER_BITS == 64
47 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64
49 #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
52 #define TCGv_tl TCGv_i32
53 #define tcg_temp_new_tl tcg_temp_new_i32
54 #define tcg_gen_extu_reg_tl tcg_gen_mov_i32
57 #if TARGET_REGISTER_BITS == 64
58 #define TCGv_reg TCGv_i64
60 #define tcg_temp_new tcg_temp_new_i64
61 #define tcg_global_mem_new tcg_global_mem_new_i64
63 #define tcg_gen_movi_reg tcg_gen_movi_i64
64 #define tcg_gen_mov_reg tcg_gen_mov_i64
65 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
66 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
67 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
68 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
69 #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
70 #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
71 #define tcg_gen_ld_reg tcg_gen_ld_i64
72 #define tcg_gen_st8_reg tcg_gen_st8_i64
73 #define tcg_gen_st16_reg tcg_gen_st16_i64
74 #define tcg_gen_st32_reg tcg_gen_st32_i64
75 #define tcg_gen_st_reg tcg_gen_st_i64
76 #define tcg_gen_add_reg tcg_gen_add_i64
77 #define tcg_gen_addi_reg tcg_gen_addi_i64
78 #define tcg_gen_sub_reg tcg_gen_sub_i64
79 #define tcg_gen_neg_reg tcg_gen_neg_i64
80 #define tcg_gen_subfi_reg tcg_gen_subfi_i64
81 #define tcg_gen_subi_reg tcg_gen_subi_i64
82 #define tcg_gen_and_reg tcg_gen_and_i64
83 #define tcg_gen_andi_reg tcg_gen_andi_i64
84 #define tcg_gen_or_reg tcg_gen_or_i64
85 #define tcg_gen_ori_reg tcg_gen_ori_i64
86 #define tcg_gen_xor_reg tcg_gen_xor_i64
87 #define tcg_gen_xori_reg tcg_gen_xori_i64
88 #define tcg_gen_not_reg tcg_gen_not_i64
89 #define tcg_gen_shl_reg tcg_gen_shl_i64
90 #define tcg_gen_shli_reg tcg_gen_shli_i64
91 #define tcg_gen_shr_reg tcg_gen_shr_i64
92 #define tcg_gen_shri_reg tcg_gen_shri_i64
93 #define tcg_gen_sar_reg tcg_gen_sar_i64
94 #define tcg_gen_sari_reg tcg_gen_sari_i64
95 #define tcg_gen_brcond_reg tcg_gen_brcond_i64
96 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
97 #define tcg_gen_setcond_reg tcg_gen_setcond_i64
98 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
99 #define tcg_gen_mul_reg tcg_gen_mul_i64
100 #define tcg_gen_muli_reg tcg_gen_muli_i64
101 #define tcg_gen_div_reg tcg_gen_div_i64
102 #define tcg_gen_rem_reg tcg_gen_rem_i64
103 #define tcg_gen_divu_reg tcg_gen_divu_i64
104 #define tcg_gen_remu_reg tcg_gen_remu_i64
105 #define tcg_gen_discard_reg tcg_gen_discard_i64
106 #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
107 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
108 #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
109 #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
110 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
111 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
112 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
113 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
114 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
115 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
116 #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
117 #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
118 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
119 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
120 #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
121 #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
122 #define tcg_gen_andc_reg tcg_gen_andc_i64
123 #define tcg_gen_eqv_reg tcg_gen_eqv_i64
124 #define tcg_gen_nand_reg tcg_gen_nand_i64
125 #define tcg_gen_nor_reg tcg_gen_nor_i64
126 #define tcg_gen_orc_reg tcg_gen_orc_i64
127 #define tcg_gen_clz_reg tcg_gen_clz_i64
128 #define tcg_gen_ctz_reg tcg_gen_ctz_i64
129 #define tcg_gen_clzi_reg tcg_gen_clzi_i64
130 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
131 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
132 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
133 #define tcg_gen_rotl_reg tcg_gen_rotl_i64
134 #define tcg_gen_rotli_reg tcg_gen_rotli_i64
135 #define tcg_gen_rotr_reg tcg_gen_rotr_i64
136 #define tcg_gen_rotri_reg tcg_gen_rotri_i64
137 #define tcg_gen_deposit_reg tcg_gen_deposit_i64
138 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
139 #define tcg_gen_extract_reg tcg_gen_extract_i64
140 #define tcg_gen_sextract_reg tcg_gen_sextract_i64
141 #define tcg_gen_extract2_reg tcg_gen_extract2_i64
142 #define tcg_constant_reg tcg_constant_i64
143 #define tcg_gen_movcond_reg tcg_gen_movcond_i64
144 #define tcg_gen_add2_reg tcg_gen_add2_i64
145 #define tcg_gen_sub2_reg tcg_gen_sub2_i64
146 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
147 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
148 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
149 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
151 #define TCGv_reg TCGv_i32
152 #define tcg_temp_new tcg_temp_new_i32
153 #define tcg_global_mem_new tcg_global_mem_new_i32
155 #define tcg_gen_movi_reg tcg_gen_movi_i32
156 #define tcg_gen_mov_reg tcg_gen_mov_i32
157 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
158 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
159 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
160 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
161 #define tcg_gen_ld32u_reg tcg_gen_ld_i32
162 #define tcg_gen_ld32s_reg tcg_gen_ld_i32
163 #define tcg_gen_ld_reg tcg_gen_ld_i32
164 #define tcg_gen_st8_reg tcg_gen_st8_i32
165 #define tcg_gen_st16_reg tcg_gen_st16_i32
166 #define tcg_gen_st32_reg tcg_gen_st32_i32
167 #define tcg_gen_st_reg tcg_gen_st_i32
168 #define tcg_gen_add_reg tcg_gen_add_i32
169 #define tcg_gen_addi_reg tcg_gen_addi_i32
170 #define tcg_gen_sub_reg tcg_gen_sub_i32
171 #define tcg_gen_neg_reg tcg_gen_neg_i32
172 #define tcg_gen_subfi_reg tcg_gen_subfi_i32
173 #define tcg_gen_subi_reg tcg_gen_subi_i32
174 #define tcg_gen_and_reg tcg_gen_and_i32
175 #define tcg_gen_andi_reg tcg_gen_andi_i32
176 #define tcg_gen_or_reg tcg_gen_or_i32
177 #define tcg_gen_ori_reg tcg_gen_ori_i32
178 #define tcg_gen_xor_reg tcg_gen_xor_i32
179 #define tcg_gen_xori_reg tcg_gen_xori_i32
180 #define tcg_gen_not_reg tcg_gen_not_i32
181 #define tcg_gen_shl_reg tcg_gen_shl_i32
182 #define tcg_gen_shli_reg tcg_gen_shli_i32
183 #define tcg_gen_shr_reg tcg_gen_shr_i32
184 #define tcg_gen_shri_reg tcg_gen_shri_i32
185 #define tcg_gen_sar_reg tcg_gen_sar_i32
186 #define tcg_gen_sari_reg tcg_gen_sari_i32
187 #define tcg_gen_brcond_reg tcg_gen_brcond_i32
188 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
189 #define tcg_gen_setcond_reg tcg_gen_setcond_i32
190 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
191 #define tcg_gen_mul_reg tcg_gen_mul_i32
192 #define tcg_gen_muli_reg tcg_gen_muli_i32
193 #define tcg_gen_div_reg tcg_gen_div_i32
194 #define tcg_gen_rem_reg tcg_gen_rem_i32
195 #define tcg_gen_divu_reg tcg_gen_divu_i32
196 #define tcg_gen_remu_reg tcg_gen_remu_i32
197 #define tcg_gen_discard_reg tcg_gen_discard_i32
198 #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
199 #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
200 #define tcg_gen_extu_i32_reg tcg_gen_mov_i32
201 #define tcg_gen_ext_i32_reg tcg_gen_mov_i32
202 #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
203 #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
204 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
205 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
206 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
207 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
208 #define tcg_gen_ext32u_reg tcg_gen_mov_i32
209 #define tcg_gen_ext32s_reg tcg_gen_mov_i32
210 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
211 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
212 #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
213 #define tcg_gen_andc_reg tcg_gen_andc_i32
214 #define tcg_gen_eqv_reg tcg_gen_eqv_i32
215 #define tcg_gen_nand_reg tcg_gen_nand_i32
216 #define tcg_gen_nor_reg tcg_gen_nor_i32
217 #define tcg_gen_orc_reg tcg_gen_orc_i32
218 #define tcg_gen_clz_reg tcg_gen_clz_i32
219 #define tcg_gen_ctz_reg tcg_gen_ctz_i32
220 #define tcg_gen_clzi_reg tcg_gen_clzi_i32
221 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
222 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
223 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
224 #define tcg_gen_rotl_reg tcg_gen_rotl_i32
225 #define tcg_gen_rotli_reg tcg_gen_rotli_i32
226 #define tcg_gen_rotr_reg tcg_gen_rotr_i32
227 #define tcg_gen_rotri_reg tcg_gen_rotri_i32
228 #define tcg_gen_deposit_reg tcg_gen_deposit_i32
229 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
230 #define tcg_gen_extract_reg tcg_gen_extract_i32
231 #define tcg_gen_sextract_reg tcg_gen_sextract_i32
232 #define tcg_gen_extract2_reg tcg_gen_extract2_i32
233 #define tcg_constant_reg tcg_constant_i32
234 #define tcg_gen_movcond_reg tcg_gen_movcond_i32
235 #define tcg_gen_add2_reg tcg_gen_add2_i32
236 #define tcg_gen_sub2_reg tcg_gen_sub2_i32
237 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
238 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
239 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
240 #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
241 #endif /* TARGET_REGISTER_BITS */
243 typedef struct DisasCond
{
248 typedef struct DisasContext
{
249 DisasContextBase base
;
267 #ifdef CONFIG_USER_ONLY
272 #ifdef CONFIG_USER_ONLY
273 #define UNALIGN(C) (C)->unalign
275 #define UNALIGN(C) MO_ALIGN
278 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
279 static int expand_sm_imm(DisasContext
*ctx
, int val
)
281 if (val
& PSW_SM_E
) {
282 val
= (val
& ~PSW_SM_E
) | PSW_E
;
284 if (val
& PSW_SM_W
) {
285 val
= (val
& ~PSW_SM_W
) | PSW_W
;
290 /* Inverted space register indicates 0 means sr0 not inferred from base. */
291 static int expand_sr3x(DisasContext
*ctx
, int val
)
296 /* Convert the M:A bits within a memory insn to the tri-state value
297 we use for the final M. */
298 static int ma_to_m(DisasContext
*ctx
, int val
)
300 return val
& 2 ? (val
& 1 ? -1 : 1) : 0;
303 /* Convert the sign of the displacement to a pre or post-modify. */
304 static int pos_to_m(DisasContext
*ctx
, int val
)
309 static int neg_to_m(DisasContext
*ctx
, int val
)
314 /* Used for branch targets and fp memory ops. */
315 static int expand_shl2(DisasContext
*ctx
, int val
)
320 /* Used for fp memory ops. */
321 static int expand_shl3(DisasContext
*ctx
, int val
)
326 /* Used for assemble_21. */
327 static int expand_shl11(DisasContext
*ctx
, int val
)
333 /* Include the auto-generated decoder. */
334 #include "decode-insns.c.inc"
336 /* We are not using a goto_tb (for whatever reason), but have updated
337 the iaq (for whatever reason), so don't do it again on exit. */
338 #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0
340 /* We are exiting the TB, but have neither emitted a goto_tb, nor
341 updated the iaq for the next instruction to be executed. */
342 #define DISAS_IAQ_N_STALE DISAS_TARGET_1
344 /* Similarly, but we want to return to the main loop immediately
345 to recognize unmasked interrupts. */
346 #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2
347 #define DISAS_EXIT DISAS_TARGET_3
349 /* global register indexes */
350 static TCGv_reg cpu_gr
[32];
351 static TCGv_i64 cpu_sr
[4];
352 static TCGv_i64 cpu_srH
;
353 static TCGv_reg cpu_iaoq_f
;
354 static TCGv_reg cpu_iaoq_b
;
355 static TCGv_i64 cpu_iasq_f
;
356 static TCGv_i64 cpu_iasq_b
;
357 static TCGv_reg cpu_sar
;
358 static TCGv_reg cpu_psw_n
;
359 static TCGv_reg cpu_psw_v
;
360 static TCGv_reg cpu_psw_cb
;
361 static TCGv_reg cpu_psw_cb_msb
;
363 void hppa_translate_init(void)
365 #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
367 typedef struct { TCGv_reg
*var
; const char *name
; int ofs
; } GlobalVar
;
368 static const GlobalVar vars
[] = {
369 { &cpu_sar
, "sar", offsetof(CPUHPPAState
, cr
[CR_SAR
]) },
380 /* Use the symbolic register names that match the disassembler. */
381 static const char gr_names
[32][4] = {
382 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
383 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
384 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
385 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
387 /* SR[4-7] are not global registers so that we can index them. */
388 static const char sr_names
[5][4] = {
389 "sr0", "sr1", "sr2", "sr3", "srH"
395 for (i
= 1; i
< 32; i
++) {
396 cpu_gr
[i
] = tcg_global_mem_new(tcg_env
,
397 offsetof(CPUHPPAState
, gr
[i
]),
400 for (i
= 0; i
< 4; i
++) {
401 cpu_sr
[i
] = tcg_global_mem_new_i64(tcg_env
,
402 offsetof(CPUHPPAState
, sr
[i
]),
405 cpu_srH
= tcg_global_mem_new_i64(tcg_env
,
406 offsetof(CPUHPPAState
, sr
[4]),
409 for (i
= 0; i
< ARRAY_SIZE(vars
); ++i
) {
410 const GlobalVar
*v
= &vars
[i
];
411 *v
->var
= tcg_global_mem_new(tcg_env
, v
->ofs
, v
->name
);
414 cpu_iasq_f
= tcg_global_mem_new_i64(tcg_env
,
415 offsetof(CPUHPPAState
, iasq_f
),
417 cpu_iasq_b
= tcg_global_mem_new_i64(tcg_env
,
418 offsetof(CPUHPPAState
, iasq_b
),
422 static DisasCond
cond_make_f(void)
431 static DisasCond
cond_make_t(void)
434 .c
= TCG_COND_ALWAYS
,
440 static DisasCond
cond_make_n(void)
445 .a1
= tcg_constant_reg(0)
449 static DisasCond
cond_make_0_tmp(TCGCond c
, TCGv_reg a0
)
451 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
453 .c
= c
, .a0
= a0
, .a1
= tcg_constant_reg(0)
457 static DisasCond
cond_make_0(TCGCond c
, TCGv_reg a0
)
459 TCGv_reg tmp
= tcg_temp_new();
460 tcg_gen_mov_reg(tmp
, a0
);
461 return cond_make_0_tmp(c
, tmp
);
464 static DisasCond
cond_make(TCGCond c
, TCGv_reg a0
, TCGv_reg a1
)
466 DisasCond r
= { .c
= c
};
468 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
469 r
.a0
= tcg_temp_new();
470 tcg_gen_mov_reg(r
.a0
, a0
);
471 r
.a1
= tcg_temp_new();
472 tcg_gen_mov_reg(r
.a1
, a1
);
477 static void cond_free(DisasCond
*cond
)
484 case TCG_COND_ALWAYS
:
485 cond
->c
= TCG_COND_NEVER
;
492 static TCGv_reg
load_gpr(DisasContext
*ctx
, unsigned reg
)
495 TCGv_reg t
= tcg_temp_new();
496 tcg_gen_movi_reg(t
, 0);
503 static TCGv_reg
dest_gpr(DisasContext
*ctx
, unsigned reg
)
505 if (reg
== 0 || ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
506 return tcg_temp_new();
512 static void save_or_nullify(DisasContext
*ctx
, TCGv_reg dest
, TCGv_reg t
)
514 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
515 tcg_gen_movcond_reg(ctx
->null_cond
.c
, dest
, ctx
->null_cond
.a0
,
516 ctx
->null_cond
.a1
, dest
, t
);
518 tcg_gen_mov_reg(dest
, t
);
522 static void save_gpr(DisasContext
*ctx
, unsigned reg
, TCGv_reg t
)
525 save_or_nullify(ctx
, cpu_gr
[reg
], t
);
537 static TCGv_i32
load_frw_i32(unsigned rt
)
539 TCGv_i32 ret
= tcg_temp_new_i32();
540 tcg_gen_ld_i32(ret
, tcg_env
,
541 offsetof(CPUHPPAState
, fr
[rt
& 31])
542 + (rt
& 32 ? LO_OFS
: HI_OFS
));
546 static TCGv_i32
load_frw0_i32(unsigned rt
)
549 TCGv_i32 ret
= tcg_temp_new_i32();
550 tcg_gen_movi_i32(ret
, 0);
553 return load_frw_i32(rt
);
557 static TCGv_i64
load_frw0_i64(unsigned rt
)
559 TCGv_i64 ret
= tcg_temp_new_i64();
561 tcg_gen_movi_i64(ret
, 0);
563 tcg_gen_ld32u_i64(ret
, tcg_env
,
564 offsetof(CPUHPPAState
, fr
[rt
& 31])
565 + (rt
& 32 ? LO_OFS
: HI_OFS
));
570 static void save_frw_i32(unsigned rt
, TCGv_i32 val
)
572 tcg_gen_st_i32(val
, tcg_env
,
573 offsetof(CPUHPPAState
, fr
[rt
& 31])
574 + (rt
& 32 ? LO_OFS
: HI_OFS
));
580 static TCGv_i64
load_frd(unsigned rt
)
582 TCGv_i64 ret
= tcg_temp_new_i64();
583 tcg_gen_ld_i64(ret
, tcg_env
, offsetof(CPUHPPAState
, fr
[rt
]));
587 static TCGv_i64
load_frd0(unsigned rt
)
590 TCGv_i64 ret
= tcg_temp_new_i64();
591 tcg_gen_movi_i64(ret
, 0);
598 static void save_frd(unsigned rt
, TCGv_i64 val
)
600 tcg_gen_st_i64(val
, tcg_env
, offsetof(CPUHPPAState
, fr
[rt
]));
603 static void load_spr(DisasContext
*ctx
, TCGv_i64 dest
, unsigned reg
)
605 #ifdef CONFIG_USER_ONLY
606 tcg_gen_movi_i64(dest
, 0);
609 tcg_gen_mov_i64(dest
, cpu_sr
[reg
]);
610 } else if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
611 tcg_gen_mov_i64(dest
, cpu_srH
);
613 tcg_gen_ld_i64(dest
, tcg_env
, offsetof(CPUHPPAState
, sr
[reg
]));
618 /* Skip over the implementation of an insn that has been nullified.
619 Use this when the insn is too complex for a conditional move. */
620 static void nullify_over(DisasContext
*ctx
)
622 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
623 /* The always condition should have been handled in the main loop. */
624 assert(ctx
->null_cond
.c
!= TCG_COND_ALWAYS
);
626 ctx
->null_lab
= gen_new_label();
628 /* If we're using PSW[N], copy it to a temp because... */
629 if (ctx
->null_cond
.a0
== cpu_psw_n
) {
630 ctx
->null_cond
.a0
= tcg_temp_new();
631 tcg_gen_mov_reg(ctx
->null_cond
.a0
, cpu_psw_n
);
633 /* ... we clear it before branching over the implementation,
634 so that (1) it's clear after nullifying this insn and
635 (2) if this insn nullifies the next, PSW[N] is valid. */
636 if (ctx
->psw_n_nonzero
) {
637 ctx
->psw_n_nonzero
= false;
638 tcg_gen_movi_reg(cpu_psw_n
, 0);
641 tcg_gen_brcond_reg(ctx
->null_cond
.c
, ctx
->null_cond
.a0
,
642 ctx
->null_cond
.a1
, ctx
->null_lab
);
643 cond_free(&ctx
->null_cond
);
647 /* Save the current nullification state to PSW[N]. */
648 static void nullify_save(DisasContext
*ctx
)
650 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
651 if (ctx
->psw_n_nonzero
) {
652 tcg_gen_movi_reg(cpu_psw_n
, 0);
656 if (ctx
->null_cond
.a0
!= cpu_psw_n
) {
657 tcg_gen_setcond_reg(ctx
->null_cond
.c
, cpu_psw_n
,
658 ctx
->null_cond
.a0
, ctx
->null_cond
.a1
);
659 ctx
->psw_n_nonzero
= true;
661 cond_free(&ctx
->null_cond
);
664 /* Set a PSW[N] to X. The intention is that this is used immediately
665 before a goto_tb/exit_tb, so that there is no fallthru path to other
666 code within the TB. Therefore we do not update psw_n_nonzero. */
667 static void nullify_set(DisasContext
*ctx
, bool x
)
669 if (ctx
->psw_n_nonzero
|| x
) {
670 tcg_gen_movi_reg(cpu_psw_n
, x
);
674 /* Mark the end of an instruction that may have been nullified.
675 This is the pair to nullify_over. Always returns true so that
676 it may be tail-called from a translate function. */
677 static bool nullify_end(DisasContext
*ctx
)
679 TCGLabel
*null_lab
= ctx
->null_lab
;
680 DisasJumpType status
= ctx
->base
.is_jmp
;
682 /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
683 For UPDATED, we cannot update on the nullified path. */
684 assert(status
!= DISAS_IAQ_N_UPDATED
);
686 if (likely(null_lab
== NULL
)) {
687 /* The current insn wasn't conditional or handled the condition
688 applied to it without a branch, so the (new) setting of
689 NULL_COND can be applied directly to the next insn. */
692 ctx
->null_lab
= NULL
;
694 if (likely(ctx
->null_cond
.c
== TCG_COND_NEVER
)) {
695 /* The next instruction will be unconditional,
696 and NULL_COND already reflects that. */
697 gen_set_label(null_lab
);
699 /* The insn that we just executed is itself nullifying the next
700 instruction. Store the condition in the PSW[N] global.
701 We asserted PSW[N] = 0 in nullify_over, so that after the
702 label we have the proper value in place. */
704 gen_set_label(null_lab
);
705 ctx
->null_cond
= cond_make_n();
707 if (status
== DISAS_NORETURN
) {
708 ctx
->base
.is_jmp
= DISAS_NEXT
;
713 static target_ureg
gva_offset_mask(DisasContext
*ctx
)
715 return (ctx
->tb_flags
& PSW_W
716 ? MAKE_64BIT_MASK(0, 62)
717 : MAKE_64BIT_MASK(0, 32));
720 static void copy_iaoq_entry(DisasContext
*ctx
, TCGv_reg dest
,
721 target_ureg ival
, TCGv_reg vval
)
723 if (unlikely(ival
== -1)) {
724 tcg_gen_mov_reg(dest
, vval
);
726 tcg_gen_movi_reg(dest
, ival
);
730 static inline target_ureg
iaoq_dest(DisasContext
*ctx
, target_sreg disp
)
732 return ctx
->iaoq_f
+ disp
+ 8;
735 static void gen_excp_1(int exception
)
737 gen_helper_excp(tcg_env
, tcg_constant_i32(exception
));
740 static void gen_excp(DisasContext
*ctx
, int exception
)
742 copy_iaoq_entry(ctx
, cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
743 copy_iaoq_entry(ctx
, cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
745 gen_excp_1(exception
);
746 ctx
->base
.is_jmp
= DISAS_NORETURN
;
749 static bool gen_excp_iir(DisasContext
*ctx
, int exc
)
752 tcg_gen_st_reg(tcg_constant_reg(ctx
->insn
),
753 tcg_env
, offsetof(CPUHPPAState
, cr
[CR_IIR
]));
755 return nullify_end(ctx
);
758 static bool gen_illegal(DisasContext
*ctx
)
760 return gen_excp_iir(ctx
, EXCP_ILL
);
763 #ifdef CONFIG_USER_ONLY
764 #define CHECK_MOST_PRIVILEGED(EXCP) \
765 return gen_excp_iir(ctx, EXCP)
767 #define CHECK_MOST_PRIVILEGED(EXCP) \
769 if (ctx->privilege != 0) { \
770 return gen_excp_iir(ctx, EXCP); \
775 static bool use_goto_tb(DisasContext
*ctx
, target_ureg dest
)
777 return translator_use_goto_tb(&ctx
->base
, dest
);
780 /* If the next insn is to be nullified, and it's on the same page,
781 and we're not attempting to set a breakpoint on it, then we can
782 totally skip the nullified insn. This avoids creating and
783 executing a TB that merely branches to the next TB. */
784 static bool use_nullify_skip(DisasContext
*ctx
)
786 return (((ctx
->iaoq_b
^ ctx
->iaoq_f
) & TARGET_PAGE_MASK
) == 0
787 && !cpu_breakpoint_test(ctx
->cs
, ctx
->iaoq_b
, BP_ANY
));
790 static void gen_goto_tb(DisasContext
*ctx
, int which
,
791 target_ureg f
, target_ureg b
)
793 if (f
!= -1 && b
!= -1 && use_goto_tb(ctx
, f
)) {
794 tcg_gen_goto_tb(which
);
795 copy_iaoq_entry(ctx
, cpu_iaoq_f
, f
, NULL
);
796 copy_iaoq_entry(ctx
, cpu_iaoq_b
, b
, NULL
);
797 tcg_gen_exit_tb(ctx
->base
.tb
, which
);
799 copy_iaoq_entry(ctx
, cpu_iaoq_f
, f
, cpu_iaoq_b
);
800 copy_iaoq_entry(ctx
, cpu_iaoq_b
, b
, ctx
->iaoq_n_var
);
801 tcg_gen_lookup_and_goto_ptr();
805 static bool cond_need_sv(int c
)
807 return c
== 2 || c
== 3 || c
== 6;
810 static bool cond_need_cb(int c
)
812 return c
== 4 || c
== 5;
815 /* Need extensions from TCGv_i32 to TCGv_reg. */
816 static bool cond_need_ext(DisasContext
*ctx
, bool d
)
818 return TARGET_REGISTER_BITS
== 64 && !d
;
822 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
823 * the Parisc 1.1 Architecture Reference Manual for details.
826 static DisasCond
do_cond(unsigned cf
, TCGv_reg res
,
827 TCGv_reg cb_msb
, TCGv_reg sv
)
833 case 0: /* Never / TR (0 / 1) */
834 cond
= cond_make_f();
836 case 1: /* = / <> (Z / !Z) */
837 cond
= cond_make_0(TCG_COND_EQ
, res
);
839 case 2: /* < / >= (N ^ V / !(N ^ V) */
840 tmp
= tcg_temp_new();
841 tcg_gen_xor_reg(tmp
, res
, sv
);
842 cond
= cond_make_0_tmp(TCG_COND_LT
, tmp
);
844 case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
848 * ((res < 0) ^ (sv < 0)) | !res
849 * ((res ^ sv) < 0) | !res
850 * (~(res ^ sv) >= 0) | !res
851 * !(~(res ^ sv) >> 31) | !res
852 * !(~(res ^ sv) >> 31 & res)
854 tmp
= tcg_temp_new();
855 tcg_gen_eqv_reg(tmp
, res
, sv
);
856 tcg_gen_sari_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
857 tcg_gen_and_reg(tmp
, tmp
, res
);
858 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
860 case 4: /* NUV / UV (!C / C) */
861 cond
= cond_make_0(TCG_COND_EQ
, cb_msb
);
863 case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
864 tmp
= tcg_temp_new();
865 tcg_gen_neg_reg(tmp
, cb_msb
);
866 tcg_gen_and_reg(tmp
, tmp
, res
);
867 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
869 case 6: /* SV / NSV (V / !V) */
870 cond
= cond_make_0(TCG_COND_LT
, sv
);
872 case 7: /* OD / EV */
873 tmp
= tcg_temp_new();
874 tcg_gen_andi_reg(tmp
, res
, 1);
875 cond
= cond_make_0_tmp(TCG_COND_NE
, tmp
);
878 g_assert_not_reached();
881 cond
.c
= tcg_invert_cond(cond
.c
);
887 /* Similar, but for the special case of subtraction without borrow, we
888 can use the inputs directly. This can allow other computation to be
889 deleted as unused. */
891 static DisasCond
do_sub_cond(unsigned cf
, TCGv_reg res
,
892 TCGv_reg in1
, TCGv_reg in2
, TCGv_reg sv
)
898 cond
= cond_make(TCG_COND_EQ
, in1
, in2
);
901 cond
= cond_make(TCG_COND_LT
, in1
, in2
);
904 cond
= cond_make(TCG_COND_LE
, in1
, in2
);
906 case 4: /* << / >>= */
907 cond
= cond_make(TCG_COND_LTU
, in1
, in2
);
909 case 5: /* <<= / >> */
910 cond
= cond_make(TCG_COND_LEU
, in1
, in2
);
913 return do_cond(cf
, res
, NULL
, sv
);
916 cond
.c
= tcg_invert_cond(cond
.c
);
923 * Similar, but for logicals, where the carry and overflow bits are not
924 * computed, and use of them is undefined.
926 * Undefined or not, hardware does not trap. It seems reasonable to
927 * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
928 * how cases c={2,3} are treated.
931 static DisasCond
do_log_cond(unsigned cf
, TCGv_reg res
)
935 case 9: /* undef, C */
936 case 11: /* undef, C & !Z */
937 case 12: /* undef, V */
938 return cond_make_f();
941 case 8: /* undef, !C */
942 case 10: /* undef, !C | Z */
943 case 13: /* undef, !V */
944 return cond_make_t();
947 return cond_make_0(TCG_COND_EQ
, res
);
949 return cond_make_0(TCG_COND_NE
, res
);
951 return cond_make_0(TCG_COND_LT
, res
);
953 return cond_make_0(TCG_COND_GE
, res
);
955 return cond_make_0(TCG_COND_LE
, res
);
957 return cond_make_0(TCG_COND_GT
, res
);
961 return do_cond(cf
, res
, NULL
, NULL
);
964 g_assert_not_reached();
968 /* Similar, but for shift/extract/deposit conditions. */
970 static DisasCond
do_sed_cond(unsigned orig
, TCGv_reg res
)
974 /* Convert the compressed condition codes to standard.
975 0-2 are the same as logicals (nv,<,<=), while 3 is OD.
976 4-7 are the reverse of 0-3. */
983 return do_log_cond(c
* 2 + f
, res
);
986 /* Similar, but for unit conditions. */
988 static DisasCond
do_unit_cond(unsigned cf
, TCGv_reg res
,
989 TCGv_reg in1
, TCGv_reg in2
)
992 TCGv_reg tmp
, cb
= NULL
;
995 /* Since we want to test lots of carry-out bits all at once, do not
996 * do our normal thing and compute carry-in of bit B+1 since that
997 * leaves us with carry bits spread across two words.
1000 tmp
= tcg_temp_new();
1001 tcg_gen_or_reg(cb
, in1
, in2
);
1002 tcg_gen_and_reg(tmp
, in1
, in2
);
1003 tcg_gen_andc_reg(cb
, cb
, res
);
1004 tcg_gen_or_reg(cb
, cb
, tmp
);
1008 case 0: /* never / TR */
1009 case 1: /* undefined */
1010 case 5: /* undefined */
1011 cond
= cond_make_f();
1014 case 2: /* SBZ / NBZ */
1015 /* See hasless(v,1) from
1016 * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
1018 tmp
= tcg_temp_new();
1019 tcg_gen_subi_reg(tmp
, res
, 0x01010101u
);
1020 tcg_gen_andc_reg(tmp
, tmp
, res
);
1021 tcg_gen_andi_reg(tmp
, tmp
, 0x80808080u
);
1022 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1025 case 3: /* SHZ / NHZ */
1026 tmp
= tcg_temp_new();
1027 tcg_gen_subi_reg(tmp
, res
, 0x00010001u
);
1028 tcg_gen_andc_reg(tmp
, tmp
, res
);
1029 tcg_gen_andi_reg(tmp
, tmp
, 0x80008000u
);
1030 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1033 case 4: /* SDC / NDC */
1034 tcg_gen_andi_reg(cb
, cb
, 0x88888888u
);
1035 cond
= cond_make_0(TCG_COND_NE
, cb
);
1038 case 6: /* SBC / NBC */
1039 tcg_gen_andi_reg(cb
, cb
, 0x80808080u
);
1040 cond
= cond_make_0(TCG_COND_NE
, cb
);
1043 case 7: /* SHC / NHC */
1044 tcg_gen_andi_reg(cb
, cb
, 0x80008000u
);
1045 cond
= cond_make_0(TCG_COND_NE
, cb
);
1049 g_assert_not_reached();
1052 cond
.c
= tcg_invert_cond(cond
.c
);
1058 static TCGv_reg
get_carry(DisasContext
*ctx
, bool d
,
1059 TCGv_reg cb
, TCGv_reg cb_msb
)
1061 if (cond_need_ext(ctx
, d
)) {
1062 TCGv_reg t
= tcg_temp_new();
1063 tcg_gen_extract_reg(t
, cb
, 32, 1);
1069 static TCGv_reg
get_psw_carry(DisasContext
*ctx
, bool d
)
1071 return get_carry(ctx
, d
, cpu_psw_cb
, cpu_psw_cb_msb
);
1074 /* Compute signed overflow for addition. */
1075 static TCGv_reg
do_add_sv(DisasContext
*ctx
, TCGv_reg res
,
1076 TCGv_reg in1
, TCGv_reg in2
)
1078 TCGv_reg sv
= tcg_temp_new();
1079 TCGv_reg tmp
= tcg_temp_new();
1081 tcg_gen_xor_reg(sv
, res
, in1
);
1082 tcg_gen_xor_reg(tmp
, in1
, in2
);
1083 tcg_gen_andc_reg(sv
, sv
, tmp
);
1088 /* Compute signed overflow for subtraction. */
1089 static TCGv_reg
do_sub_sv(DisasContext
*ctx
, TCGv_reg res
,
1090 TCGv_reg in1
, TCGv_reg in2
)
1092 TCGv_reg sv
= tcg_temp_new();
1093 TCGv_reg tmp
= tcg_temp_new();
1095 tcg_gen_xor_reg(sv
, res
, in1
);
1096 tcg_gen_xor_reg(tmp
, in1
, in2
);
1097 tcg_gen_and_reg(sv
, sv
, tmp
);
1102 static void do_add(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1103 TCGv_reg in2
, unsigned shift
, bool is_l
,
1104 bool is_tsv
, bool is_tc
, bool is_c
, unsigned cf
)
1106 TCGv_reg dest
, cb
, cb_msb
, cb_cond
, sv
, tmp
;
1107 unsigned c
= cf
>> 1;
1111 dest
= tcg_temp_new();
1117 tmp
= tcg_temp_new();
1118 tcg_gen_shli_reg(tmp
, in1
, shift
);
1122 if (!is_l
|| cond_need_cb(c
)) {
1123 TCGv_reg zero
= tcg_constant_reg(0);
1124 cb_msb
= tcg_temp_new();
1125 cb
= tcg_temp_new();
1127 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, in2
, zero
);
1129 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
,
1130 get_psw_carry(ctx
, d
), zero
);
1132 tcg_gen_xor_reg(cb
, in1
, in2
);
1133 tcg_gen_xor_reg(cb
, cb
, dest
);
1134 if (cond_need_cb(c
)) {
1135 cb_cond
= get_carry(ctx
, d
, cb
, cb_msb
);
1138 tcg_gen_add_reg(dest
, in1
, in2
);
1140 tcg_gen_add_reg(dest
, dest
, get_psw_carry(ctx
, d
));
1144 /* Compute signed overflow if required. */
1146 if (is_tsv
|| cond_need_sv(c
)) {
1147 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
1149 /* ??? Need to include overflow from shift. */
1150 gen_helper_tsv(tcg_env
, sv
);
1154 /* Emit any conditional trap before any writeback. */
1155 cond
= do_cond(cf
, dest
, cb_cond
, sv
);
1157 tmp
= tcg_temp_new();
1158 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1159 gen_helper_tcond(tcg_env
, tmp
);
1162 /* Write back the result. */
1164 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1165 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1167 save_gpr(ctx
, rt
, dest
);
1169 /* Install the new nullification. */
1170 cond_free(&ctx
->null_cond
);
1171 ctx
->null_cond
= cond
;
1174 static bool do_add_reg(DisasContext
*ctx
, arg_rrr_cf_sh
*a
,
1175 bool is_l
, bool is_tsv
, bool is_tc
, bool is_c
)
1177 TCGv_reg tcg_r1
, tcg_r2
;
1182 tcg_r1
= load_gpr(ctx
, a
->r1
);
1183 tcg_r2
= load_gpr(ctx
, a
->r2
);
1184 do_add(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->sh
, is_l
, is_tsv
, is_tc
, is_c
, a
->cf
);
1185 return nullify_end(ctx
);
1188 static bool do_add_imm(DisasContext
*ctx
, arg_rri_cf
*a
,
1189 bool is_tsv
, bool is_tc
)
1191 TCGv_reg tcg_im
, tcg_r2
;
1196 tcg_im
= tcg_constant_reg(a
->i
);
1197 tcg_r2
= load_gpr(ctx
, a
->r
);
1198 do_add(ctx
, a
->t
, tcg_im
, tcg_r2
, 0, 0, is_tsv
, is_tc
, 0, a
->cf
);
1199 return nullify_end(ctx
);
1202 static void do_sub(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1203 TCGv_reg in2
, bool is_tsv
, bool is_b
,
1204 bool is_tc
, unsigned cf
)
1206 TCGv_reg dest
, sv
, cb
, cb_msb
, zero
, tmp
;
1207 unsigned c
= cf
>> 1;
1211 dest
= tcg_temp_new();
1212 cb
= tcg_temp_new();
1213 cb_msb
= tcg_temp_new();
1215 zero
= tcg_constant_reg(0);
1217 /* DEST,C = IN1 + ~IN2 + C. */
1218 tcg_gen_not_reg(cb
, in2
);
1219 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, get_psw_carry(ctx
, d
), zero
);
1220 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cb
, zero
);
1221 tcg_gen_xor_reg(cb
, cb
, in1
);
1222 tcg_gen_xor_reg(cb
, cb
, dest
);
1225 * DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
1226 * operations by seeding the high word with 1 and subtracting.
1228 TCGv_reg one
= tcg_constant_reg(1);
1229 tcg_gen_sub2_reg(dest
, cb_msb
, in1
, one
, in2
, zero
);
1230 tcg_gen_eqv_reg(cb
, in1
, in2
);
1231 tcg_gen_xor_reg(cb
, cb
, dest
);
1234 /* Compute signed overflow if required. */
1236 if (is_tsv
|| cond_need_sv(c
)) {
1237 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1239 gen_helper_tsv(tcg_env
, sv
);
1243 /* Compute the condition. We cannot use the special case for borrow. */
1245 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1247 cond
= do_cond(cf
, dest
, get_carry(ctx
, d
, cb
, cb_msb
), sv
);
1250 /* Emit any conditional trap before any writeback. */
1252 tmp
= tcg_temp_new();
1253 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1254 gen_helper_tcond(tcg_env
, tmp
);
1257 /* Write back the result. */
1258 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1259 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1260 save_gpr(ctx
, rt
, dest
);
1262 /* Install the new nullification. */
1263 cond_free(&ctx
->null_cond
);
1264 ctx
->null_cond
= cond
;
1267 static bool do_sub_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1268 bool is_tsv
, bool is_b
, bool is_tc
)
1270 TCGv_reg tcg_r1
, tcg_r2
;
1275 tcg_r1
= load_gpr(ctx
, a
->r1
);
1276 tcg_r2
= load_gpr(ctx
, a
->r2
);
1277 do_sub(ctx
, a
->t
, tcg_r1
, tcg_r2
, is_tsv
, is_b
, is_tc
, a
->cf
);
1278 return nullify_end(ctx
);
1281 static bool do_sub_imm(DisasContext
*ctx
, arg_rri_cf
*a
, bool is_tsv
)
1283 TCGv_reg tcg_im
, tcg_r2
;
1288 tcg_im
= tcg_constant_reg(a
->i
);
1289 tcg_r2
= load_gpr(ctx
, a
->r
);
1290 do_sub(ctx
, a
->t
, tcg_im
, tcg_r2
, is_tsv
, 0, 0, a
->cf
);
1291 return nullify_end(ctx
);
1294 static void do_cmpclr(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1295 TCGv_reg in2
, unsigned cf
)
1300 dest
= tcg_temp_new();
1301 tcg_gen_sub_reg(dest
, in1
, in2
);
1303 /* Compute signed overflow if required. */
1305 if (cond_need_sv(cf
>> 1)) {
1306 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1309 /* Form the condition for the compare. */
1310 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1313 tcg_gen_movi_reg(dest
, 0);
1314 save_gpr(ctx
, rt
, dest
);
1316 /* Install the new nullification. */
1317 cond_free(&ctx
->null_cond
);
1318 ctx
->null_cond
= cond
;
1321 static void do_log(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1322 TCGv_reg in2
, unsigned cf
,
1323 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1325 TCGv_reg dest
= dest_gpr(ctx
, rt
);
1327 /* Perform the operation, and writeback. */
1329 save_gpr(ctx
, rt
, dest
);
1331 /* Install the new nullification. */
1332 cond_free(&ctx
->null_cond
);
1334 ctx
->null_cond
= do_log_cond(cf
, dest
);
1338 static bool do_log_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1339 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1341 TCGv_reg tcg_r1
, tcg_r2
;
1346 tcg_r1
= load_gpr(ctx
, a
->r1
);
1347 tcg_r2
= load_gpr(ctx
, a
->r2
);
1348 do_log(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, fn
);
1349 return nullify_end(ctx
);
1352 static void do_unit(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1353 TCGv_reg in2
, unsigned cf
, bool is_tc
,
1354 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1360 dest
= dest_gpr(ctx
, rt
);
1362 save_gpr(ctx
, rt
, dest
);
1363 cond_free(&ctx
->null_cond
);
1365 dest
= tcg_temp_new();
1368 cond
= do_unit_cond(cf
, dest
, in1
, in2
);
1371 TCGv_reg tmp
= tcg_temp_new();
1372 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1373 gen_helper_tcond(tcg_env
, tmp
);
1375 save_gpr(ctx
, rt
, dest
);
1377 cond_free(&ctx
->null_cond
);
1378 ctx
->null_cond
= cond
;
1382 #ifndef CONFIG_USER_ONLY
1383 /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
1384 from the top 2 bits of the base register. There are a few system
1385 instructions that have a 3-bit space specifier, for which SR0 is
1386 not special. To handle this, pass ~SP. */
1387 static TCGv_i64
space_select(DisasContext
*ctx
, int sp
, TCGv_reg base
)
1397 spc
= tcg_temp_new_tl();
1398 load_spr(ctx
, spc
, sp
);
1401 if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
1405 ptr
= tcg_temp_new_ptr();
1406 tmp
= tcg_temp_new();
1407 spc
= tcg_temp_new_tl();
1409 /* Extract top 2 bits of the address, shift left 3 for uint64_t index. */
1410 tcg_gen_shri_reg(tmp
, base
, (ctx
->tb_flags
& PSW_W
? 64 : 32) - 5);
1411 tcg_gen_andi_reg(tmp
, tmp
, 030);
1412 tcg_gen_trunc_reg_ptr(ptr
, tmp
);
1414 tcg_gen_add_ptr(ptr
, ptr
, tcg_env
);
1415 tcg_gen_ld_i64(spc
, ptr
, offsetof(CPUHPPAState
, sr
[4]));
1421 static void form_gva(DisasContext
*ctx
, TCGv_tl
*pgva
, TCGv_reg
*pofs
,
1422 unsigned rb
, unsigned rx
, int scale
, target_sreg disp
,
1423 unsigned sp
, int modify
, bool is_phys
)
1425 TCGv_reg base
= load_gpr(ctx
, rb
);
1429 /* Note that RX is mutually exclusive with DISP. */
1431 ofs
= tcg_temp_new();
1432 tcg_gen_shli_reg(ofs
, cpu_gr
[rx
], scale
);
1433 tcg_gen_add_reg(ofs
, ofs
, base
);
1434 } else if (disp
|| modify
) {
1435 ofs
= tcg_temp_new();
1436 tcg_gen_addi_reg(ofs
, base
, disp
);
1442 *pgva
= addr
= tcg_temp_new_tl();
1443 tcg_gen_extu_reg_tl(addr
, modify
<= 0 ? ofs
: base
);
1444 tcg_gen_andi_tl(addr
, addr
, gva_offset_mask(ctx
));
1445 #ifndef CONFIG_USER_ONLY
1447 tcg_gen_or_tl(addr
, addr
, space_select(ctx
, sp
, base
));
1452 /* Emit a memory load. The modify parameter should be
1453 * < 0 for pre-modify,
1454 * > 0 for post-modify,
1455 * = 0 for no base register update.
1457 static void do_load_32(DisasContext
*ctx
, TCGv_i32 dest
, unsigned rb
,
1458 unsigned rx
, int scale
, target_sreg disp
,
1459 unsigned sp
, int modify
, MemOp mop
)
1464 /* Caller uses nullify_over/nullify_end. */
1465 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1467 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1468 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1469 tcg_gen_qemu_ld_i32(dest
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1471 save_gpr(ctx
, rb
, ofs
);
1475 static void do_load_64(DisasContext
*ctx
, TCGv_i64 dest
, unsigned rb
,
1476 unsigned rx
, int scale
, target_sreg disp
,
1477 unsigned sp
, int modify
, MemOp mop
)
1482 /* Caller uses nullify_over/nullify_end. */
1483 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1485 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1486 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1487 tcg_gen_qemu_ld_i64(dest
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1489 save_gpr(ctx
, rb
, ofs
);
1493 static void do_store_32(DisasContext
*ctx
, TCGv_i32 src
, unsigned rb
,
1494 unsigned rx
, int scale
, target_sreg disp
,
1495 unsigned sp
, int modify
, MemOp mop
)
1500 /* Caller uses nullify_over/nullify_end. */
1501 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1503 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1504 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1505 tcg_gen_qemu_st_i32(src
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1507 save_gpr(ctx
, rb
, ofs
);
1511 static void do_store_64(DisasContext
*ctx
, TCGv_i64 src
, unsigned rb
,
1512 unsigned rx
, int scale
, target_sreg disp
,
1513 unsigned sp
, int modify
, MemOp mop
)
1518 /* Caller uses nullify_over/nullify_end. */
1519 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1521 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1522 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1523 tcg_gen_qemu_st_i64(src
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1525 save_gpr(ctx
, rb
, ofs
);
1529 #if TARGET_REGISTER_BITS == 64
1530 #define do_load_reg do_load_64
1531 #define do_store_reg do_store_64
1533 #define do_load_reg do_load_32
1534 #define do_store_reg do_store_32
1537 static bool do_load(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1538 unsigned rx
, int scale
, target_sreg disp
,
1539 unsigned sp
, int modify
, MemOp mop
)
1546 /* No base register update. */
1547 dest
= dest_gpr(ctx
, rt
);
1549 /* Make sure if RT == RB, we see the result of the load. */
1550 dest
= tcg_temp_new();
1552 do_load_reg(ctx
, dest
, rb
, rx
, scale
, disp
, sp
, modify
, mop
);
1553 save_gpr(ctx
, rt
, dest
);
1555 return nullify_end(ctx
);
1558 static bool do_floadw(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1559 unsigned rx
, int scale
, target_sreg disp
,
1560 unsigned sp
, int modify
)
1566 tmp
= tcg_temp_new_i32();
1567 do_load_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1568 save_frw_i32(rt
, tmp
);
1571 gen_helper_loaded_fr0(tcg_env
);
1574 return nullify_end(ctx
);
1577 static bool trans_fldw(DisasContext
*ctx
, arg_ldst
*a
)
1579 return do_floadw(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1580 a
->disp
, a
->sp
, a
->m
);
1583 static bool do_floadd(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1584 unsigned rx
, int scale
, target_sreg disp
,
1585 unsigned sp
, int modify
)
1591 tmp
= tcg_temp_new_i64();
1592 do_load_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUQ
);
1596 gen_helper_loaded_fr0(tcg_env
);
1599 return nullify_end(ctx
);
1602 static bool trans_fldd(DisasContext
*ctx
, arg_ldst
*a
)
1604 return do_floadd(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1605 a
->disp
, a
->sp
, a
->m
);
1608 static bool do_store(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1609 target_sreg disp
, unsigned sp
,
1610 int modify
, MemOp mop
)
1613 do_store_reg(ctx
, load_gpr(ctx
, rt
), rb
, 0, 0, disp
, sp
, modify
, mop
);
1614 return nullify_end(ctx
);
1617 static bool do_fstorew(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1618 unsigned rx
, int scale
, target_sreg disp
,
1619 unsigned sp
, int modify
)
1625 tmp
= load_frw_i32(rt
);
1626 do_store_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1628 return nullify_end(ctx
);
1631 static bool trans_fstw(DisasContext
*ctx
, arg_ldst
*a
)
1633 return do_fstorew(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1634 a
->disp
, a
->sp
, a
->m
);
1637 static bool do_fstored(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1638 unsigned rx
, int scale
, target_sreg disp
,
1639 unsigned sp
, int modify
)
1646 do_store_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUQ
);
1648 return nullify_end(ctx
);
1651 static bool trans_fstd(DisasContext
*ctx
, arg_ldst
*a
)
1653 return do_fstored(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1654 a
->disp
, a
->sp
, a
->m
);
1657 static bool do_fop_wew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1658 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
))
1663 tmp
= load_frw0_i32(ra
);
1665 func(tmp
, tcg_env
, tmp
);
1667 save_frw_i32(rt
, tmp
);
1668 return nullify_end(ctx
);
1671 static bool do_fop_wed(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1672 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i64
))
1679 dst
= tcg_temp_new_i32();
1681 func(dst
, tcg_env
, src
);
1683 save_frw_i32(rt
, dst
);
1684 return nullify_end(ctx
);
1687 static bool do_fop_ded(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1688 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
1693 tmp
= load_frd0(ra
);
1695 func(tmp
, tcg_env
, tmp
);
1698 return nullify_end(ctx
);
1701 static bool do_fop_dew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1702 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i32
))
1708 src
= load_frw0_i32(ra
);
1709 dst
= tcg_temp_new_i64();
1711 func(dst
, tcg_env
, src
);
1714 return nullify_end(ctx
);
1717 static bool do_fop_weww(DisasContext
*ctx
, unsigned rt
,
1718 unsigned ra
, unsigned rb
,
1719 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
1724 a
= load_frw0_i32(ra
);
1725 b
= load_frw0_i32(rb
);
1727 func(a
, tcg_env
, a
, b
);
1729 save_frw_i32(rt
, a
);
1730 return nullify_end(ctx
);
1733 static bool do_fop_dedd(DisasContext
*ctx
, unsigned rt
,
1734 unsigned ra
, unsigned rb
,
1735 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
1743 func(a
, tcg_env
, a
, b
);
1746 return nullify_end(ctx
);
1749 /* Emit an unconditional branch to a direct target, which may or may not
1750 have already had nullification handled. */
1751 static bool do_dbranch(DisasContext
*ctx
, target_ureg dest
,
1752 unsigned link
, bool is_n
)
1754 if (ctx
->null_cond
.c
== TCG_COND_NEVER
&& ctx
->null_lab
== NULL
) {
1756 copy_iaoq_entry(ctx
, cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1760 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1766 copy_iaoq_entry(ctx
, cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1769 if (is_n
&& use_nullify_skip(ctx
)) {
1770 nullify_set(ctx
, 0);
1771 gen_goto_tb(ctx
, 0, dest
, dest
+ 4);
1773 nullify_set(ctx
, is_n
);
1774 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, dest
);
1779 nullify_set(ctx
, 0);
1780 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, ctx
->iaoq_n
);
1781 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1786 /* Emit a conditional branch to a direct target. If the branch itself
1787 is nullified, we should have already used nullify_over. */
1788 static bool do_cbranch(DisasContext
*ctx
, target_sreg disp
, bool is_n
,
1791 target_ureg dest
= iaoq_dest(ctx
, disp
);
1792 TCGLabel
*taken
= NULL
;
1793 TCGCond c
= cond
->c
;
1796 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1798 /* Handle TRUE and NEVER as direct branches. */
1799 if (c
== TCG_COND_ALWAYS
) {
1800 return do_dbranch(ctx
, dest
, 0, is_n
&& disp
>= 0);
1802 if (c
== TCG_COND_NEVER
) {
1803 return do_dbranch(ctx
, ctx
->iaoq_n
, 0, is_n
&& disp
< 0);
1806 taken
= gen_new_label();
1807 tcg_gen_brcond_reg(c
, cond
->a0
, cond
->a1
, taken
);
1810 /* Not taken: Condition not satisfied; nullify on backward branches. */
1811 n
= is_n
&& disp
< 0;
1812 if (n
&& use_nullify_skip(ctx
)) {
1813 nullify_set(ctx
, 0);
1814 gen_goto_tb(ctx
, 0, ctx
->iaoq_n
, ctx
->iaoq_n
+ 4);
1816 if (!n
&& ctx
->null_lab
) {
1817 gen_set_label(ctx
->null_lab
);
1818 ctx
->null_lab
= NULL
;
1820 nullify_set(ctx
, n
);
1821 if (ctx
->iaoq_n
== -1) {
1822 /* The temporary iaoq_n_var died at the branch above.
1823 Regenerate it here instead of saving it. */
1824 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
1826 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
1829 gen_set_label(taken
);
1831 /* Taken: Condition satisfied; nullify on forward branches. */
1832 n
= is_n
&& disp
>= 0;
1833 if (n
&& use_nullify_skip(ctx
)) {
1834 nullify_set(ctx
, 0);
1835 gen_goto_tb(ctx
, 1, dest
, dest
+ 4);
1837 nullify_set(ctx
, n
);
1838 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, dest
);
1841 /* Not taken: the branch itself was nullified. */
1842 if (ctx
->null_lab
) {
1843 gen_set_label(ctx
->null_lab
);
1844 ctx
->null_lab
= NULL
;
1845 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
1847 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1852 /* Emit an unconditional branch to an indirect target. This handles
1853 nullification of the branch itself. */
1854 static bool do_ibranch(DisasContext
*ctx
, TCGv_reg dest
,
1855 unsigned link
, bool is_n
)
1857 TCGv_reg a0
, a1
, next
, tmp
;
1860 assert(ctx
->null_lab
== NULL
);
1862 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
1864 copy_iaoq_entry(ctx
, cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1866 next
= tcg_temp_new();
1867 tcg_gen_mov_reg(next
, dest
);
1869 if (use_nullify_skip(ctx
)) {
1870 copy_iaoq_entry(ctx
, cpu_iaoq_f
, -1, next
);
1871 tcg_gen_addi_reg(next
, next
, 4);
1872 copy_iaoq_entry(ctx
, cpu_iaoq_b
, -1, next
);
1873 nullify_set(ctx
, 0);
1874 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
1877 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1880 ctx
->iaoq_n_var
= next
;
1881 } else if (is_n
&& use_nullify_skip(ctx
)) {
1882 /* The (conditional) branch, B, nullifies the next insn, N,
1883 and we're allowed to skip execution N (no single-step or
1884 tracepoint in effect). Since the goto_ptr that we must use
1885 for the indirect branch consumes no special resources, we
1886 can (conditionally) skip B and continue execution. */
1887 /* The use_nullify_skip test implies we have a known control path. */
1888 tcg_debug_assert(ctx
->iaoq_b
!= -1);
1889 tcg_debug_assert(ctx
->iaoq_n
!= -1);
1891 /* We do have to handle the non-local temporary, DEST, before
1892 branching. Since IOAQ_F is not really live at this point, we
1893 can simply store DEST optimistically. Similarly with IAOQ_B. */
1894 copy_iaoq_entry(ctx
, cpu_iaoq_f
, -1, dest
);
1895 next
= tcg_temp_new();
1896 tcg_gen_addi_reg(next
, dest
, 4);
1897 copy_iaoq_entry(ctx
, cpu_iaoq_b
, -1, next
);
1901 copy_iaoq_entry(ctx
, cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1903 tcg_gen_lookup_and_goto_ptr();
1904 return nullify_end(ctx
);
1906 c
= ctx
->null_cond
.c
;
1907 a0
= ctx
->null_cond
.a0
;
1908 a1
= ctx
->null_cond
.a1
;
1910 tmp
= tcg_temp_new();
1911 next
= tcg_temp_new();
1913 copy_iaoq_entry(ctx
, tmp
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1914 tcg_gen_movcond_reg(c
, next
, a0
, a1
, tmp
, dest
);
1916 ctx
->iaoq_n_var
= next
;
1919 tcg_gen_movcond_reg(c
, cpu_gr
[link
], a0
, a1
, cpu_gr
[link
], tmp
);
1923 /* The branch nullifies the next insn, which means the state of N
1924 after the branch is the inverse of the state of N that applied
1926 tcg_gen_setcond_reg(tcg_invert_cond(c
), cpu_psw_n
, a0
, a1
);
1927 cond_free(&ctx
->null_cond
);
1928 ctx
->null_cond
= cond_make_n();
1929 ctx
->psw_n_nonzero
= true;
1931 cond_free(&ctx
->null_cond
);
1938 * if (IAOQ_Front{30..31} < GR[b]{30..31})
1939 * IAOQ_Next{30..31} ← GR[b]{30..31};
1941 * IAOQ_Next{30..31} ← IAOQ_Front{30..31};
1942 * which keeps the privilege level from being increased.
1944 static TCGv_reg
do_ibranch_priv(DisasContext
*ctx
, TCGv_reg offset
)
1947 switch (ctx
->privilege
) {
1949 /* Privilege 0 is maximum and is allowed to decrease. */
1952 /* Privilege 3 is minimum and is never allowed to increase. */
1953 dest
= tcg_temp_new();
1954 tcg_gen_ori_reg(dest
, offset
, 3);
1957 dest
= tcg_temp_new();
1958 tcg_gen_andi_reg(dest
, offset
, -4);
1959 tcg_gen_ori_reg(dest
, dest
, ctx
->privilege
);
1960 tcg_gen_movcond_reg(TCG_COND_GTU
, dest
, dest
, offset
, dest
, offset
);
1966 #ifdef CONFIG_USER_ONLY
1967 /* On Linux, page zero is normally marked execute only + gateway.
1968 Therefore normal read or write is supposed to fail, but specific
1969 offsets have kernel code mapped to raise permissions to implement
1970 system calls. Handling this via an explicit check here, rather
1971 in than the "be disp(sr2,r0)" instruction that probably sent us
1972 here, is the easiest way to handle the branch delay slot on the
1973 aforementioned BE. */
1974 static void do_page_zero(DisasContext
*ctx
)
1978 /* If by some means we get here with PSW[N]=1, that implies that
1979 the B,GATE instruction would be skipped, and we'd fault on the
1980 next insn within the privileged page. */
1981 switch (ctx
->null_cond
.c
) {
1982 case TCG_COND_NEVER
:
1984 case TCG_COND_ALWAYS
:
1985 tcg_gen_movi_reg(cpu_psw_n
, 0);
1988 /* Since this is always the first (and only) insn within the
1989 TB, we should know the state of PSW[N] from TB->FLAGS. */
1990 g_assert_not_reached();
1993 /* Check that we didn't arrive here via some means that allowed
1994 non-sequential instruction execution. Normally the PSW[B] bit
1995 detects this by disallowing the B,GATE instruction to execute
1996 under such conditions. */
1997 if (ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
2001 switch (ctx
->iaoq_f
& -4) {
2002 case 0x00: /* Null pointer call */
2003 gen_excp_1(EXCP_IMP
);
2004 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2007 case 0xb0: /* LWS */
2008 gen_excp_1(EXCP_SYSCALL_LWS
);
2009 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2012 case 0xe0: /* SET_THREAD_POINTER */
2013 tcg_gen_st_reg(cpu_gr
[26], tcg_env
, offsetof(CPUHPPAState
, cr
[27]));
2014 tmp
= tcg_temp_new();
2015 tcg_gen_ori_reg(tmp
, cpu_gr
[31], 3);
2016 copy_iaoq_entry(ctx
, cpu_iaoq_f
, -1, tmp
);
2017 tcg_gen_addi_reg(tmp
, tmp
, 4);
2018 copy_iaoq_entry(ctx
, cpu_iaoq_b
, -1, tmp
);
2019 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
2022 case 0x100: /* SYSCALL */
2023 gen_excp_1(EXCP_SYSCALL
);
2024 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2029 gen_excp_1(EXCP_ILL
);
2030 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2036 static bool trans_nop(DisasContext
*ctx
, arg_nop
*a
)
2038 cond_free(&ctx
->null_cond
);
2042 static bool trans_break(DisasContext
*ctx
, arg_break
*a
)
2044 return gen_excp_iir(ctx
, EXCP_BREAK
);
2047 static bool trans_sync(DisasContext
*ctx
, arg_sync
*a
)
2049 /* No point in nullifying the memory barrier. */
2050 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
2052 cond_free(&ctx
->null_cond
);
2056 static bool trans_mfia(DisasContext
*ctx
, arg_mfia
*a
)
2059 TCGv_reg tmp
= dest_gpr(ctx
, rt
);
2060 tcg_gen_movi_reg(tmp
, ctx
->iaoq_f
);
2061 save_gpr(ctx
, rt
, tmp
);
2063 cond_free(&ctx
->null_cond
);
2067 static bool trans_mfsp(DisasContext
*ctx
, arg_mfsp
*a
)
2070 unsigned rs
= a
->sp
;
2071 TCGv_i64 t0
= tcg_temp_new_i64();
2072 TCGv_reg t1
= tcg_temp_new();
2074 load_spr(ctx
, t0
, rs
);
2075 tcg_gen_shri_i64(t0
, t0
, 32);
2076 tcg_gen_trunc_i64_reg(t1
, t0
);
2078 save_gpr(ctx
, rt
, t1
);
2080 cond_free(&ctx
->null_cond
);
2084 static bool trans_mfctl(DisasContext
*ctx
, arg_mfctl
*a
)
2087 unsigned ctl
= a
->r
;
2092 #ifdef TARGET_HPPA64
2094 /* MFSAR without ,W masks low 5 bits. */
2095 tmp
= dest_gpr(ctx
, rt
);
2096 tcg_gen_andi_reg(tmp
, cpu_sar
, 31);
2097 save_gpr(ctx
, rt
, tmp
);
2101 save_gpr(ctx
, rt
, cpu_sar
);
2103 case CR_IT
: /* Interval Timer */
2104 /* FIXME: Respect PSW_S bit. */
2106 tmp
= dest_gpr(ctx
, rt
);
2107 if (translator_io_start(&ctx
->base
)) {
2108 gen_helper_read_interval_timer(tmp
);
2109 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2111 gen_helper_read_interval_timer(tmp
);
2113 save_gpr(ctx
, rt
, tmp
);
2114 return nullify_end(ctx
);
2119 /* All other control registers are privileged. */
2120 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2124 tmp
= tcg_temp_new();
2125 tcg_gen_ld_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2126 save_gpr(ctx
, rt
, tmp
);
2129 cond_free(&ctx
->null_cond
);
2133 static bool trans_mtsp(DisasContext
*ctx
, arg_mtsp
*a
)
2136 unsigned rs
= a
->sp
;
2140 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2144 t64
= tcg_temp_new_i64();
2145 tcg_gen_extu_reg_i64(t64
, load_gpr(ctx
, rr
));
2146 tcg_gen_shli_i64(t64
, t64
, 32);
2149 tcg_gen_st_i64(t64
, tcg_env
, offsetof(CPUHPPAState
, sr
[rs
]));
2150 ctx
->tb_flags
&= ~TB_FLAG_SR_SAME
;
2152 tcg_gen_mov_i64(cpu_sr
[rs
], t64
);
2155 return nullify_end(ctx
);
2158 static bool trans_mtctl(DisasContext
*ctx
, arg_mtctl
*a
)
2160 unsigned ctl
= a
->t
;
2164 if (ctl
== CR_SAR
) {
2165 reg
= load_gpr(ctx
, a
->r
);
2166 tmp
= tcg_temp_new();
2167 tcg_gen_andi_reg(tmp
, reg
, TARGET_REGISTER_BITS
- 1);
2168 save_or_nullify(ctx
, cpu_sar
, tmp
);
2170 cond_free(&ctx
->null_cond
);
2174 /* All other control registers are privileged or read-only. */
2175 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2177 #ifndef CONFIG_USER_ONLY
2179 reg
= load_gpr(ctx
, a
->r
);
2183 gen_helper_write_interval_timer(tcg_env
, reg
);
2186 gen_helper_write_eirr(tcg_env
, reg
);
2189 gen_helper_write_eiem(tcg_env
, reg
);
2190 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2195 /* FIXME: Respect PSW_Q bit */
2196 /* The write advances the queue and stores to the back element. */
2197 tmp
= tcg_temp_new();
2198 tcg_gen_ld_reg(tmp
, tcg_env
,
2199 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2200 tcg_gen_st_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2201 tcg_gen_st_reg(reg
, tcg_env
,
2202 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2209 tcg_gen_st_reg(reg
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2210 #ifndef CONFIG_USER_ONLY
2211 gen_helper_change_prot_id(tcg_env
);
2216 tcg_gen_st_reg(reg
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2219 return nullify_end(ctx
);
2223 static bool trans_mtsarcm(DisasContext
*ctx
, arg_mtsarcm
*a
)
2225 TCGv_reg tmp
= tcg_temp_new();
2227 tcg_gen_not_reg(tmp
, load_gpr(ctx
, a
->r
));
2228 tcg_gen_andi_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
2229 save_or_nullify(ctx
, cpu_sar
, tmp
);
2231 cond_free(&ctx
->null_cond
);
2235 static bool trans_ldsid(DisasContext
*ctx
, arg_ldsid
*a
)
2237 TCGv_reg dest
= dest_gpr(ctx
, a
->t
);
2239 #ifdef CONFIG_USER_ONLY
2240 /* We don't implement space registers in user mode. */
2241 tcg_gen_movi_reg(dest
, 0);
2243 TCGv_i64 t0
= tcg_temp_new_i64();
2245 tcg_gen_mov_i64(t0
, space_select(ctx
, a
->sp
, load_gpr(ctx
, a
->b
)));
2246 tcg_gen_shri_i64(t0
, t0
, 32);
2247 tcg_gen_trunc_i64_reg(dest
, t0
);
2249 save_gpr(ctx
, a
->t
, dest
);
2251 cond_free(&ctx
->null_cond
);
2255 static bool trans_rsm(DisasContext
*ctx
, arg_rsm
*a
)
2257 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2258 #ifndef CONFIG_USER_ONLY
2263 tmp
= tcg_temp_new();
2264 tcg_gen_ld_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, psw
));
2265 tcg_gen_andi_reg(tmp
, tmp
, ~a
->i
);
2266 gen_helper_swap_system_mask(tmp
, tcg_env
, tmp
);
2267 save_gpr(ctx
, a
->t
, tmp
);
2269 /* Exit the TB to recognize new interrupts, e.g. PSW_M. */
2270 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2271 return nullify_end(ctx
);
2275 static bool trans_ssm(DisasContext
*ctx
, arg_ssm
*a
)
2277 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2278 #ifndef CONFIG_USER_ONLY
2283 tmp
= tcg_temp_new();
2284 tcg_gen_ld_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, psw
));
2285 tcg_gen_ori_reg(tmp
, tmp
, a
->i
);
2286 gen_helper_swap_system_mask(tmp
, tcg_env
, tmp
);
2287 save_gpr(ctx
, a
->t
, tmp
);
2289 /* Exit the TB to recognize new interrupts, e.g. PSW_I. */
2290 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2291 return nullify_end(ctx
);
2295 static bool trans_mtsm(DisasContext
*ctx
, arg_mtsm
*a
)
2297 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2298 #ifndef CONFIG_USER_ONLY
2302 reg
= load_gpr(ctx
, a
->r
);
2303 tmp
= tcg_temp_new();
2304 gen_helper_swap_system_mask(tmp
, tcg_env
, reg
);
2306 /* Exit the TB to recognize new interrupts. */
2307 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2308 return nullify_end(ctx
);
2312 static bool do_rfi(DisasContext
*ctx
, bool rfi_r
)
2314 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2315 #ifndef CONFIG_USER_ONLY
2319 gen_helper_rfi_r(tcg_env
);
2321 gen_helper_rfi(tcg_env
);
2323 /* Exit the TB to recognize new interrupts. */
2324 tcg_gen_exit_tb(NULL
, 0);
2325 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2327 return nullify_end(ctx
);
2331 static bool trans_rfi(DisasContext
*ctx
, arg_rfi
*a
)
2333 return do_rfi(ctx
, false);
2336 static bool trans_rfi_r(DisasContext
*ctx
, arg_rfi_r
*a
)
2338 return do_rfi(ctx
, true);
2341 static bool trans_halt(DisasContext
*ctx
, arg_halt
*a
)
2343 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2344 #ifndef CONFIG_USER_ONLY
2346 gen_helper_halt(tcg_env
);
2347 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2348 return nullify_end(ctx
);
2352 static bool trans_reset(DisasContext
*ctx
, arg_reset
*a
)
2354 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2355 #ifndef CONFIG_USER_ONLY
2357 gen_helper_reset(tcg_env
);
2358 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2359 return nullify_end(ctx
);
2363 static bool trans_getshadowregs(DisasContext
*ctx
, arg_getshadowregs
*a
)
2365 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2366 #ifndef CONFIG_USER_ONLY
2368 gen_helper_getshadowregs(tcg_env
);
2369 return nullify_end(ctx
);
2373 static bool trans_nop_addrx(DisasContext
*ctx
, arg_ldst
*a
)
2376 TCGv_reg dest
= dest_gpr(ctx
, a
->b
);
2377 TCGv_reg src1
= load_gpr(ctx
, a
->b
);
2378 TCGv_reg src2
= load_gpr(ctx
, a
->x
);
2380 /* The only thing we need to do is the base register modification. */
2381 tcg_gen_add_reg(dest
, src1
, src2
);
2382 save_gpr(ctx
, a
->b
, dest
);
2384 cond_free(&ctx
->null_cond
);
2388 static bool trans_probe(DisasContext
*ctx
, arg_probe
*a
)
2391 TCGv_i32 level
, want
;
2396 dest
= dest_gpr(ctx
, a
->t
);
2397 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2400 level
= tcg_constant_i32(a
->ri
);
2402 level
= tcg_temp_new_i32();
2403 tcg_gen_trunc_reg_i32(level
, load_gpr(ctx
, a
->ri
));
2404 tcg_gen_andi_i32(level
, level
, 3);
2406 want
= tcg_constant_i32(a
->write
? PAGE_WRITE
: PAGE_READ
);
2408 gen_helper_probe(dest
, tcg_env
, addr
, level
, want
);
2410 save_gpr(ctx
, a
->t
, dest
);
2411 return nullify_end(ctx
);
2414 static bool trans_ixtlbx(DisasContext
*ctx
, arg_ixtlbx
*a
)
2416 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2417 #ifndef CONFIG_USER_ONLY
2423 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2424 reg
= load_gpr(ctx
, a
->r
);
2426 gen_helper_itlba(tcg_env
, addr
, reg
);
2428 gen_helper_itlbp(tcg_env
, addr
, reg
);
2431 /* Exit TB for TLB change if mmu is enabled. */
2432 if (ctx
->tb_flags
& PSW_C
) {
2433 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2435 return nullify_end(ctx
);
2439 static bool trans_pxtlbx(DisasContext
*ctx
, arg_pxtlbx
*a
)
2441 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2442 #ifndef CONFIG_USER_ONLY
2448 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2450 save_gpr(ctx
, a
->b
, ofs
);
2453 gen_helper_ptlbe(tcg_env
);
2455 gen_helper_ptlb(tcg_env
, addr
);
2458 /* Exit TB for TLB change if mmu is enabled. */
2459 if (ctx
->tb_flags
& PSW_C
) {
2460 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2462 return nullify_end(ctx
);
2467 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2469 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2470 * page 13-9 (195/206)
2472 static bool trans_ixtlbxf(DisasContext
*ctx
, arg_ixtlbxf
*a
)
2474 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2475 #ifndef CONFIG_USER_ONLY
2476 TCGv_tl addr
, atl
, stl
;
2483 * if (not (pcxl or pcxl2))
2484 * return gen_illegal(ctx);
2486 * Note for future: these are 32-bit systems; no hppa64.
2489 atl
= tcg_temp_new_tl();
2490 stl
= tcg_temp_new_tl();
2491 addr
= tcg_temp_new_tl();
2493 tcg_gen_ld32u_i64(stl
, tcg_env
,
2494 a
->data
? offsetof(CPUHPPAState
, cr
[CR_ISR
])
2495 : offsetof(CPUHPPAState
, cr
[CR_IIASQ
]));
2496 tcg_gen_ld32u_i64(atl
, tcg_env
,
2497 a
->data
? offsetof(CPUHPPAState
, cr
[CR_IOR
])
2498 : offsetof(CPUHPPAState
, cr
[CR_IIAOQ
]));
2499 tcg_gen_shli_i64(stl
, stl
, 32);
2500 tcg_gen_or_tl(addr
, atl
, stl
);
2502 reg
= load_gpr(ctx
, a
->r
);
2504 gen_helper_itlba(tcg_env
, addr
, reg
);
2506 gen_helper_itlbp(tcg_env
, addr
, reg
);
2509 /* Exit TB for TLB change if mmu is enabled. */
2510 if (ctx
->tb_flags
& PSW_C
) {
2511 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2513 return nullify_end(ctx
);
2517 static bool trans_lpa(DisasContext
*ctx
, arg_ldst
*a
)
2519 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2520 #ifndef CONFIG_USER_ONLY
2522 TCGv_reg ofs
, paddr
;
2526 form_gva(ctx
, &vaddr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2528 paddr
= tcg_temp_new();
2529 gen_helper_lpa(paddr
, tcg_env
, vaddr
);
2531 /* Note that physical address result overrides base modification. */
2533 save_gpr(ctx
, a
->b
, ofs
);
2535 save_gpr(ctx
, a
->t
, paddr
);
2537 return nullify_end(ctx
);
2541 static bool trans_lci(DisasContext
*ctx
, arg_lci
*a
)
2543 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2545 /* The Coherence Index is an implementation-defined function of the
2546 physical address. Two addresses with the same CI have a coherent
2547 view of the cache. Our implementation is to return 0 for all,
2548 since the entire address space is coherent. */
2549 save_gpr(ctx
, a
->t
, tcg_constant_reg(0));
2551 cond_free(&ctx
->null_cond
);
2555 static bool trans_add(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2557 return do_add_reg(ctx
, a
, false, false, false, false);
2560 static bool trans_add_l(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2562 return do_add_reg(ctx
, a
, true, false, false, false);
2565 static bool trans_add_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2567 return do_add_reg(ctx
, a
, false, true, false, false);
2570 static bool trans_add_c(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2572 return do_add_reg(ctx
, a
, false, false, false, true);
2575 static bool trans_add_c_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2577 return do_add_reg(ctx
, a
, false, true, false, true);
2580 static bool trans_sub(DisasContext
*ctx
, arg_rrr_cf
*a
)
2582 return do_sub_reg(ctx
, a
, false, false, false);
2585 static bool trans_sub_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2587 return do_sub_reg(ctx
, a
, true, false, false);
2590 static bool trans_sub_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2592 return do_sub_reg(ctx
, a
, false, false, true);
2595 static bool trans_sub_tsv_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2597 return do_sub_reg(ctx
, a
, true, false, true);
2600 static bool trans_sub_b(DisasContext
*ctx
, arg_rrr_cf
*a
)
2602 return do_sub_reg(ctx
, a
, false, true, false);
2605 static bool trans_sub_b_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2607 return do_sub_reg(ctx
, a
, true, true, false);
2610 static bool trans_andcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2612 return do_log_reg(ctx
, a
, tcg_gen_andc_reg
);
2615 static bool trans_and(DisasContext
*ctx
, arg_rrr_cf
*a
)
2617 return do_log_reg(ctx
, a
, tcg_gen_and_reg
);
2620 static bool trans_or(DisasContext
*ctx
, arg_rrr_cf
*a
)
2623 unsigned r2
= a
->r2
;
2624 unsigned r1
= a
->r1
;
2627 if (rt
== 0) { /* NOP */
2628 cond_free(&ctx
->null_cond
);
2631 if (r2
== 0) { /* COPY */
2633 TCGv_reg dest
= dest_gpr(ctx
, rt
);
2634 tcg_gen_movi_reg(dest
, 0);
2635 save_gpr(ctx
, rt
, dest
);
2637 save_gpr(ctx
, rt
, cpu_gr
[r1
]);
2639 cond_free(&ctx
->null_cond
);
2642 #ifndef CONFIG_USER_ONLY
2643 /* These are QEMU extensions and are nops in the real architecture:
2645 * or %r10,%r10,%r10 -- idle loop; wait for interrupt
2646 * or %r31,%r31,%r31 -- death loop; offline cpu
2647 * currently implemented as idle.
2649 if ((rt
== 10 || rt
== 31) && r1
== rt
&& r2
== rt
) { /* PAUSE */
2650 /* No need to check for supervisor, as userland can only pause
2651 until the next timer interrupt. */
2654 /* Advance the instruction queue. */
2655 copy_iaoq_entry(ctx
, cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
2656 copy_iaoq_entry(ctx
, cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
2657 nullify_set(ctx
, 0);
2659 /* Tell the qemu main loop to halt until this cpu has work. */
2660 tcg_gen_st_i32(tcg_constant_i32(1), tcg_env
,
2661 offsetof(CPUState
, halted
) - offsetof(HPPACPU
, env
));
2662 gen_excp_1(EXCP_HALTED
);
2663 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2665 return nullify_end(ctx
);
2669 return do_log_reg(ctx
, a
, tcg_gen_or_reg
);
2672 static bool trans_xor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2674 return do_log_reg(ctx
, a
, tcg_gen_xor_reg
);
2677 static bool trans_cmpclr(DisasContext
*ctx
, arg_rrr_cf
*a
)
2679 TCGv_reg tcg_r1
, tcg_r2
;
2684 tcg_r1
= load_gpr(ctx
, a
->r1
);
2685 tcg_r2
= load_gpr(ctx
, a
->r2
);
2686 do_cmpclr(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
);
2687 return nullify_end(ctx
);
2690 static bool trans_uxor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2692 TCGv_reg tcg_r1
, tcg_r2
;
2697 tcg_r1
= load_gpr(ctx
, a
->r1
);
2698 tcg_r2
= load_gpr(ctx
, a
->r2
);
2699 do_unit(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, false, tcg_gen_xor_reg
);
2700 return nullify_end(ctx
);
2703 static bool do_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
, bool is_tc
)
2705 TCGv_reg tcg_r1
, tcg_r2
, tmp
;
2710 tcg_r1
= load_gpr(ctx
, a
->r1
);
2711 tcg_r2
= load_gpr(ctx
, a
->r2
);
2712 tmp
= tcg_temp_new();
2713 tcg_gen_not_reg(tmp
, tcg_r2
);
2714 do_unit(ctx
, a
->t
, tcg_r1
, tmp
, a
->cf
, is_tc
, tcg_gen_add_reg
);
2715 return nullify_end(ctx
);
2718 static bool trans_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2720 return do_uaddcm(ctx
, a
, false);
2723 static bool trans_uaddcm_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2725 return do_uaddcm(ctx
, a
, true);
2728 static bool do_dcor(DisasContext
*ctx
, arg_rr_cf
*a
, bool is_i
)
2734 tmp
= tcg_temp_new();
2735 tcg_gen_shri_reg(tmp
, cpu_psw_cb
, 3);
2737 tcg_gen_not_reg(tmp
, tmp
);
2739 tcg_gen_andi_reg(tmp
, tmp
, 0x11111111);
2740 tcg_gen_muli_reg(tmp
, tmp
, 6);
2741 do_unit(ctx
, a
->t
, load_gpr(ctx
, a
->r
), tmp
, a
->cf
, false,
2742 is_i
? tcg_gen_add_reg
: tcg_gen_sub_reg
);
2743 return nullify_end(ctx
);
2746 static bool trans_dcor(DisasContext
*ctx
, arg_rr_cf
*a
)
2748 return do_dcor(ctx
, a
, false);
2751 static bool trans_dcor_i(DisasContext
*ctx
, arg_rr_cf
*a
)
2753 return do_dcor(ctx
, a
, true);
2756 static bool trans_ds(DisasContext
*ctx
, arg_rrr_cf
*a
)
2758 TCGv_reg dest
, add1
, add2
, addc
, zero
, in1
, in2
;
2763 in1
= load_gpr(ctx
, a
->r1
);
2764 in2
= load_gpr(ctx
, a
->r2
);
2766 add1
= tcg_temp_new();
2767 add2
= tcg_temp_new();
2768 addc
= tcg_temp_new();
2769 dest
= tcg_temp_new();
2770 zero
= tcg_constant_reg(0);
2772 /* Form R1 << 1 | PSW[CB]{8}. */
2773 tcg_gen_add_reg(add1
, in1
, in1
);
2774 tcg_gen_add_reg(add1
, add1
, get_psw_carry(ctx
, false));
2777 * Add or subtract R2, depending on PSW[V]. Proper computation of
2778 * carry requires that we subtract via + ~R2 + 1, as described in
2779 * the manual. By extracting and masking V, we can produce the
2780 * proper inputs to the addition without movcond.
2782 tcg_gen_sextract_reg(addc
, cpu_psw_v
, 31, 1);
2783 tcg_gen_xor_reg(add2
, in2
, addc
);
2784 tcg_gen_andi_reg(addc
, addc
, 1);
2786 tcg_gen_add2_reg(dest
, cpu_psw_cb_msb
, add1
, zero
, add2
, zero
);
2787 tcg_gen_add2_reg(dest
, cpu_psw_cb_msb
, dest
, cpu_psw_cb_msb
, addc
, zero
);
2789 /* Write back the result register. */
2790 save_gpr(ctx
, a
->t
, dest
);
2792 /* Write back PSW[CB]. */
2793 tcg_gen_xor_reg(cpu_psw_cb
, add1
, add2
);
2794 tcg_gen_xor_reg(cpu_psw_cb
, cpu_psw_cb
, dest
);
2796 /* Write back PSW[V] for the division step. */
2797 cout
= get_psw_carry(ctx
, false);
2798 tcg_gen_neg_reg(cpu_psw_v
, cout
);
2799 tcg_gen_xor_reg(cpu_psw_v
, cpu_psw_v
, in2
);
2801 /* Install the new nullification. */
2804 if (cond_need_sv(a
->cf
>> 1)) {
2805 /* ??? The lshift is supposed to contribute to overflow. */
2806 sv
= do_add_sv(ctx
, dest
, add1
, add2
);
2808 ctx
->null_cond
= do_cond(a
->cf
, dest
, cout
, sv
);
2811 return nullify_end(ctx
);
2814 static bool trans_addi(DisasContext
*ctx
, arg_rri_cf
*a
)
2816 return do_add_imm(ctx
, a
, false, false);
2819 static bool trans_addi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2821 return do_add_imm(ctx
, a
, true, false);
2824 static bool trans_addi_tc(DisasContext
*ctx
, arg_rri_cf
*a
)
2826 return do_add_imm(ctx
, a
, false, true);
2829 static bool trans_addi_tc_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2831 return do_add_imm(ctx
, a
, true, true);
2834 static bool trans_subi(DisasContext
*ctx
, arg_rri_cf
*a
)
2836 return do_sub_imm(ctx
, a
, false);
2839 static bool trans_subi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2841 return do_sub_imm(ctx
, a
, true);
2844 static bool trans_cmpiclr(DisasContext
*ctx
, arg_rri_cf
*a
)
2846 TCGv_reg tcg_im
, tcg_r2
;
2852 tcg_im
= tcg_constant_reg(a
->i
);
2853 tcg_r2
= load_gpr(ctx
, a
->r
);
2854 do_cmpclr(ctx
, a
->t
, tcg_im
, tcg_r2
, a
->cf
);
2856 return nullify_end(ctx
);
2859 static bool trans_ld(DisasContext
*ctx
, arg_ldst
*a
)
2861 if (unlikely(TARGET_REGISTER_BITS
== 32 && a
->size
> MO_32
)) {
2862 return gen_illegal(ctx
);
2864 return do_load(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2865 a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2869 static bool trans_st(DisasContext
*ctx
, arg_ldst
*a
)
2871 assert(a
->x
== 0 && a
->scale
== 0);
2872 if (unlikely(TARGET_REGISTER_BITS
== 32 && a
->size
> MO_32
)) {
2873 return gen_illegal(ctx
);
2875 return do_store(ctx
, a
->t
, a
->b
, a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2879 static bool trans_ldc(DisasContext
*ctx
, arg_ldst
*a
)
2881 MemOp mop
= MO_TE
| MO_ALIGN
| a
->size
;
2882 TCGv_reg zero
, dest
, ofs
;
2888 /* Base register modification. Make sure if RT == RB,
2889 we see the result of the load. */
2890 dest
= tcg_temp_new();
2892 dest
= dest_gpr(ctx
, a
->t
);
2895 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2896 a
->disp
, a
->sp
, a
->m
, ctx
->mmu_idx
== MMU_PHYS_IDX
);
2899 * For hppa1.1, LDCW is undefined unless aligned mod 16.
2900 * However actual hardware succeeds with aligned mod 4.
2901 * Detect this case and log a GUEST_ERROR.
2903 * TODO: HPPA64 relaxes the over-alignment requirement
2904 * with the ,co completer.
2906 gen_helper_ldc_check(addr
);
2908 zero
= tcg_constant_reg(0);
2909 tcg_gen_atomic_xchg_reg(dest
, addr
, zero
, ctx
->mmu_idx
, mop
);
2912 save_gpr(ctx
, a
->b
, ofs
);
2914 save_gpr(ctx
, a
->t
, dest
);
2916 return nullify_end(ctx
);
2919 static bool trans_stby(DisasContext
*ctx
, arg_stby
*a
)
2926 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, a
->disp
, a
->sp
, a
->m
,
2927 ctx
->mmu_idx
== MMU_PHYS_IDX
);
2928 val
= load_gpr(ctx
, a
->r
);
2930 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2931 gen_helper_stby_e_parallel(tcg_env
, addr
, val
);
2933 gen_helper_stby_e(tcg_env
, addr
, val
);
2936 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2937 gen_helper_stby_b_parallel(tcg_env
, addr
, val
);
2939 gen_helper_stby_b(tcg_env
, addr
, val
);
2943 tcg_gen_andi_reg(ofs
, ofs
, ~3);
2944 save_gpr(ctx
, a
->b
, ofs
);
2947 return nullify_end(ctx
);
2950 static bool trans_lda(DisasContext
*ctx
, arg_ldst
*a
)
2952 int hold_mmu_idx
= ctx
->mmu_idx
;
2954 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2955 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2957 ctx
->mmu_idx
= hold_mmu_idx
;
2961 static bool trans_sta(DisasContext
*ctx
, arg_ldst
*a
)
2963 int hold_mmu_idx
= ctx
->mmu_idx
;
2965 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2966 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2968 ctx
->mmu_idx
= hold_mmu_idx
;
2972 static bool trans_ldil(DisasContext
*ctx
, arg_ldil
*a
)
2974 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
2976 tcg_gen_movi_reg(tcg_rt
, a
->i
);
2977 save_gpr(ctx
, a
->t
, tcg_rt
);
2978 cond_free(&ctx
->null_cond
);
2982 static bool trans_addil(DisasContext
*ctx
, arg_addil
*a
)
2984 TCGv_reg tcg_rt
= load_gpr(ctx
, a
->r
);
2985 TCGv_reg tcg_r1
= dest_gpr(ctx
, 1);
2987 tcg_gen_addi_reg(tcg_r1
, tcg_rt
, a
->i
);
2988 save_gpr(ctx
, 1, tcg_r1
);
2989 cond_free(&ctx
->null_cond
);
2993 static bool trans_ldo(DisasContext
*ctx
, arg_ldo
*a
)
2995 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
2997 /* Special case rb == 0, for the LDI pseudo-op.
2998 The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
3000 tcg_gen_movi_reg(tcg_rt
, a
->i
);
3002 tcg_gen_addi_reg(tcg_rt
, cpu_gr
[a
->b
], a
->i
);
3004 save_gpr(ctx
, a
->t
, tcg_rt
);
3005 cond_free(&ctx
->null_cond
);
3009 static bool do_cmpb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3010 unsigned c
, unsigned f
, unsigned n
, int disp
)
3012 TCGv_reg dest
, in2
, sv
;
3015 in2
= load_gpr(ctx
, r
);
3016 dest
= tcg_temp_new();
3018 tcg_gen_sub_reg(dest
, in1
, in2
);
3021 if (cond_need_sv(c
)) {
3022 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
3025 cond
= do_sub_cond(c
* 2 + f
, dest
, in1
, in2
, sv
);
3026 return do_cbranch(ctx
, disp
, n
, &cond
);
3029 static bool trans_cmpb(DisasContext
*ctx
, arg_cmpb
*a
)
3032 return do_cmpb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3035 static bool trans_cmpbi(DisasContext
*ctx
, arg_cmpbi
*a
)
3038 return do_cmpb(ctx
, a
->r
, tcg_constant_reg(a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3041 static bool do_addb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3042 unsigned c
, unsigned f
, unsigned n
, int disp
)
3044 TCGv_reg dest
, in2
, sv
, cb_cond
;
3048 in2
= load_gpr(ctx
, r
);
3049 dest
= tcg_temp_new();
3053 if (cond_need_cb(c
)) {
3054 TCGv_reg cb
= tcg_temp_new();
3055 TCGv_reg cb_msb
= tcg_temp_new();
3057 tcg_gen_movi_reg(cb_msb
, 0);
3058 tcg_gen_add2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, cb_msb
);
3059 tcg_gen_xor_reg(cb
, in1
, in2
);
3060 tcg_gen_xor_reg(cb
, cb
, dest
);
3061 cb_cond
= get_carry(ctx
, d
, cb
, cb_msb
);
3063 tcg_gen_add_reg(dest
, in1
, in2
);
3065 if (cond_need_sv(c
)) {
3066 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
3069 cond
= do_cond(c
* 2 + f
, dest
, cb_cond
, sv
);
3070 save_gpr(ctx
, r
, dest
);
3071 return do_cbranch(ctx
, disp
, n
, &cond
);
3074 static bool trans_addb(DisasContext
*ctx
, arg_addb
*a
)
3077 return do_addb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3080 static bool trans_addbi(DisasContext
*ctx
, arg_addbi
*a
)
3083 return do_addb(ctx
, a
->r
, tcg_constant_reg(a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3086 static bool trans_bb_sar(DisasContext
*ctx
, arg_bb_sar
*a
)
3088 TCGv_reg tmp
, tcg_r
;
3094 tmp
= tcg_temp_new();
3095 tcg_r
= load_gpr(ctx
, a
->r
);
3096 if (cond_need_ext(ctx
, d
)) {
3097 /* Force shift into [32,63] */
3098 tcg_gen_ori_reg(tmp
, cpu_sar
, 32);
3099 tcg_gen_shl_reg(tmp
, tcg_r
, tmp
);
3101 tcg_gen_shl_reg(tmp
, tcg_r
, cpu_sar
);
3104 cond
= cond_make_0_tmp(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3105 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3108 static bool trans_bb_imm(DisasContext
*ctx
, arg_bb_imm
*a
)
3110 TCGv_reg tmp
, tcg_r
;
3117 tmp
= tcg_temp_new();
3118 tcg_r
= load_gpr(ctx
, a
->r
);
3119 p
= a
->p
| (cond_need_ext(ctx
, d
) ? 32 : 0);
3120 tcg_gen_shli_reg(tmp
, tcg_r
, p
);
3122 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3123 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3126 static bool trans_movb(DisasContext
*ctx
, arg_movb
*a
)
3133 dest
= dest_gpr(ctx
, a
->r2
);
3135 tcg_gen_movi_reg(dest
, 0);
3137 tcg_gen_mov_reg(dest
, cpu_gr
[a
->r1
]);
3140 cond
= do_sed_cond(a
->c
, dest
);
3141 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3144 static bool trans_movbi(DisasContext
*ctx
, arg_movbi
*a
)
3151 dest
= dest_gpr(ctx
, a
->r
);
3152 tcg_gen_movi_reg(dest
, a
->i
);
3154 cond
= do_sed_cond(a
->c
, dest
);
3155 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3158 static bool trans_shrpw_sar(DisasContext
*ctx
, arg_shrpw_sar
*a
)
3166 dest
= dest_gpr(ctx
, a
->t
);
3168 tcg_gen_ext32u_reg(dest
, load_gpr(ctx
, a
->r2
));
3169 tcg_gen_shr_reg(dest
, dest
, cpu_sar
);
3170 } else if (a
->r1
== a
->r2
) {
3171 TCGv_i32 t32
= tcg_temp_new_i32();
3172 TCGv_i32 s32
= tcg_temp_new_i32();
3174 tcg_gen_trunc_reg_i32(t32
, load_gpr(ctx
, a
->r2
));
3175 tcg_gen_trunc_reg_i32(s32
, cpu_sar
);
3176 tcg_gen_rotr_i32(t32
, t32
, s32
);
3177 tcg_gen_extu_i32_reg(dest
, t32
);
3179 TCGv_i64 t
= tcg_temp_new_i64();
3180 TCGv_i64 s
= tcg_temp_new_i64();
3182 tcg_gen_concat_reg_i64(t
, load_gpr(ctx
, a
->r2
), load_gpr(ctx
, a
->r1
));
3183 tcg_gen_extu_reg_i64(s
, cpu_sar
);
3184 tcg_gen_shr_i64(t
, t
, s
);
3185 tcg_gen_trunc_i64_reg(dest
, t
);
3187 save_gpr(ctx
, a
->t
, dest
);
3189 /* Install the new nullification. */
3190 cond_free(&ctx
->null_cond
);
3192 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3194 return nullify_end(ctx
);
3197 static bool trans_shrpw_imm(DisasContext
*ctx
, arg_shrpw_imm
*a
)
3199 unsigned sa
= 31 - a
->cpos
;
3206 dest
= dest_gpr(ctx
, a
->t
);
3207 t2
= load_gpr(ctx
, a
->r2
);
3209 tcg_gen_extract_reg(dest
, t2
, sa
, 32 - sa
);
3210 } else if (TARGET_REGISTER_BITS
== 32) {
3211 tcg_gen_extract2_reg(dest
, t2
, cpu_gr
[a
->r1
], sa
);
3212 } else if (a
->r1
== a
->r2
) {
3213 TCGv_i32 t32
= tcg_temp_new_i32();
3214 tcg_gen_trunc_reg_i32(t32
, t2
);
3215 tcg_gen_rotri_i32(t32
, t32
, sa
);
3216 tcg_gen_extu_i32_reg(dest
, t32
);
3218 TCGv_i64 t64
= tcg_temp_new_i64();
3219 tcg_gen_concat_reg_i64(t64
, t2
, cpu_gr
[a
->r1
]);
3220 tcg_gen_shri_i64(t64
, t64
, sa
);
3221 tcg_gen_trunc_i64_reg(dest
, t64
);
3223 save_gpr(ctx
, a
->t
, dest
);
3225 /* Install the new nullification. */
3226 cond_free(&ctx
->null_cond
);
3228 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3230 return nullify_end(ctx
);
3233 static bool trans_extrw_sar(DisasContext
*ctx
, arg_extrw_sar
*a
)
3235 unsigned len
= 32 - a
->clen
;
3236 TCGv_reg dest
, src
, tmp
;
3242 dest
= dest_gpr(ctx
, a
->t
);
3243 src
= load_gpr(ctx
, a
->r
);
3244 tmp
= tcg_temp_new();
3246 /* Recall that SAR is using big-endian bit numbering. */
3247 tcg_gen_andi_reg(tmp
, cpu_sar
, 31);
3248 tcg_gen_xori_reg(tmp
, tmp
, 31);
3251 tcg_gen_sar_reg(dest
, src
, tmp
);
3252 tcg_gen_sextract_reg(dest
, dest
, 0, len
);
3254 tcg_gen_shr_reg(dest
, src
, tmp
);
3255 tcg_gen_extract_reg(dest
, dest
, 0, len
);
3257 save_gpr(ctx
, a
->t
, dest
);
3259 /* Install the new nullification. */
3260 cond_free(&ctx
->null_cond
);
3262 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3264 return nullify_end(ctx
);
3267 static bool trans_extrw_imm(DisasContext
*ctx
, arg_extrw_imm
*a
)
3269 unsigned len
= 32 - a
->clen
;
3270 unsigned cpos
= 31 - a
->pos
;
3277 dest
= dest_gpr(ctx
, a
->t
);
3278 src
= load_gpr(ctx
, a
->r
);
3280 tcg_gen_sextract_reg(dest
, src
, cpos
, len
);
3282 tcg_gen_extract_reg(dest
, src
, cpos
, len
);
3284 save_gpr(ctx
, a
->t
, dest
);
3286 /* Install the new nullification. */
3287 cond_free(&ctx
->null_cond
);
3289 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3291 return nullify_end(ctx
);
3294 static bool trans_depwi_imm(DisasContext
*ctx
, arg_depwi_imm
*a
)
3296 unsigned len
= 32 - a
->clen
;
3297 target_sreg mask0
, mask1
;
3303 if (a
->cpos
+ len
> 32) {
3307 dest
= dest_gpr(ctx
, a
->t
);
3308 mask0
= deposit64(0, a
->cpos
, len
, a
->i
);
3309 mask1
= deposit64(-1, a
->cpos
, len
, a
->i
);
3312 TCGv_reg src
= load_gpr(ctx
, a
->t
);
3314 tcg_gen_andi_reg(dest
, src
, mask1
);
3317 tcg_gen_ori_reg(dest
, src
, mask0
);
3319 tcg_gen_movi_reg(dest
, mask0
);
3321 save_gpr(ctx
, a
->t
, dest
);
3323 /* Install the new nullification. */
3324 cond_free(&ctx
->null_cond
);
3326 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3328 return nullify_end(ctx
);
3331 static bool trans_depw_imm(DisasContext
*ctx
, arg_depw_imm
*a
)
3333 unsigned rs
= a
->nz
? a
->t
: 0;
3334 unsigned len
= 32 - a
->clen
;
3340 if (a
->cpos
+ len
> 32) {
3344 dest
= dest_gpr(ctx
, a
->t
);
3345 val
= load_gpr(ctx
, a
->r
);
3347 tcg_gen_deposit_z_reg(dest
, val
, a
->cpos
, len
);
3349 tcg_gen_deposit_reg(dest
, cpu_gr
[rs
], val
, a
->cpos
, len
);
3351 save_gpr(ctx
, a
->t
, dest
);
3353 /* Install the new nullification. */
3354 cond_free(&ctx
->null_cond
);
3356 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3358 return nullify_end(ctx
);
3361 static bool do_depw_sar(DisasContext
*ctx
, unsigned rt
, unsigned c
,
3362 unsigned nz
, unsigned clen
, TCGv_reg val
)
3364 unsigned rs
= nz
? rt
: 0;
3365 unsigned len
= 32 - clen
;
3366 TCGv_reg mask
, tmp
, shift
, dest
;
3367 unsigned msb
= 1U << (len
- 1);
3369 dest
= dest_gpr(ctx
, rt
);
3370 shift
= tcg_temp_new();
3371 tmp
= tcg_temp_new();
3373 /* Convert big-endian bit numbering in SAR to left-shift. */
3374 tcg_gen_andi_reg(shift
, cpu_sar
, 31);
3375 tcg_gen_xori_reg(shift
, shift
, 31);
3377 mask
= tcg_temp_new();
3378 tcg_gen_movi_reg(mask
, msb
+ (msb
- 1));
3379 tcg_gen_and_reg(tmp
, val
, mask
);
3381 tcg_gen_shl_reg(mask
, mask
, shift
);
3382 tcg_gen_shl_reg(tmp
, tmp
, shift
);
3383 tcg_gen_andc_reg(dest
, cpu_gr
[rs
], mask
);
3384 tcg_gen_or_reg(dest
, dest
, tmp
);
3386 tcg_gen_shl_reg(dest
, tmp
, shift
);
3388 save_gpr(ctx
, rt
, dest
);
3390 /* Install the new nullification. */
3391 cond_free(&ctx
->null_cond
);
3393 ctx
->null_cond
= do_sed_cond(c
, dest
);
3395 return nullify_end(ctx
);
3398 static bool trans_depw_sar(DisasContext
*ctx
, arg_depw_sar
*a
)
3403 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_gpr(ctx
, a
->r
));
3406 static bool trans_depwi_sar(DisasContext
*ctx
, arg_depwi_sar
*a
)
3411 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, tcg_constant_reg(a
->i
));
3414 static bool trans_be(DisasContext
*ctx
, arg_be
*a
)
3418 #ifdef CONFIG_USER_ONLY
3419 /* ??? It seems like there should be a good way of using
3420 "be disp(sr2, r0)", the canonical gateway entry mechanism
3421 to our advantage. But that appears to be inconvenient to
3422 manage along side branch delay slots. Therefore we handle
3423 entry into the gateway page via absolute address. */
3424 /* Since we don't implement spaces, just branch. Do notice the special
3425 case of "be disp(*,r0)" using a direct branch to disp, so that we can
3426 goto_tb to the TB containing the syscall. */
3428 return do_dbranch(ctx
, a
->disp
, a
->l
, a
->n
);
3434 tmp
= tcg_temp_new();
3435 tcg_gen_addi_reg(tmp
, load_gpr(ctx
, a
->b
), a
->disp
);
3436 tmp
= do_ibranch_priv(ctx
, tmp
);
3438 #ifdef CONFIG_USER_ONLY
3439 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3441 TCGv_i64 new_spc
= tcg_temp_new_i64();
3443 load_spr(ctx
, new_spc
, a
->sp
);
3445 copy_iaoq_entry(ctx
, cpu_gr
[31], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3446 tcg_gen_mov_i64(cpu_sr
[0], cpu_iasq_f
);
3448 if (a
->n
&& use_nullify_skip(ctx
)) {
3449 copy_iaoq_entry(ctx
, cpu_iaoq_f
, -1, tmp
);
3450 tcg_gen_addi_reg(tmp
, tmp
, 4);
3451 copy_iaoq_entry(ctx
, cpu_iaoq_b
, -1, tmp
);
3452 tcg_gen_mov_i64(cpu_iasq_f
, new_spc
);
3453 tcg_gen_mov_i64(cpu_iasq_b
, cpu_iasq_f
);
3455 copy_iaoq_entry(ctx
, cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3456 if (ctx
->iaoq_b
== -1) {
3457 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3459 copy_iaoq_entry(ctx
, cpu_iaoq_b
, -1, tmp
);
3460 tcg_gen_mov_i64(cpu_iasq_b
, new_spc
);
3461 nullify_set(ctx
, a
->n
);
3463 tcg_gen_lookup_and_goto_ptr();
3464 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3465 return nullify_end(ctx
);
3469 static bool trans_bl(DisasContext
*ctx
, arg_bl
*a
)
3471 return do_dbranch(ctx
, iaoq_dest(ctx
, a
->disp
), a
->l
, a
->n
);
3474 static bool trans_b_gate(DisasContext
*ctx
, arg_b_gate
*a
)
3476 target_ureg dest
= iaoq_dest(ctx
, a
->disp
);
3480 /* Make sure the caller hasn't done something weird with the queue.
3481 * ??? This is not quite the same as the PSW[B] bit, which would be
3482 * expensive to track. Real hardware will trap for
3484 * b gateway+4 (in delay slot of first branch)
3485 * However, checking for a non-sequential instruction queue *will*
3486 * diagnose the security hole
3489 * in which instructions at evil would run with increased privs.
3491 if (ctx
->iaoq_b
== -1 || ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
3492 return gen_illegal(ctx
);
3495 #ifndef CONFIG_USER_ONLY
3496 if (ctx
->tb_flags
& PSW_C
) {
3497 CPUHPPAState
*env
= cpu_env(ctx
->cs
);
3498 int type
= hppa_artype_for_page(env
, ctx
->base
.pc_next
);
3499 /* If we could not find a TLB entry, then we need to generate an
3500 ITLB miss exception so the kernel will provide it.
3501 The resulting TLB fill operation will invalidate this TB and
3502 we will re-translate, at which point we *will* be able to find
3503 the TLB entry and determine if this is in fact a gateway page. */
3505 gen_excp(ctx
, EXCP_ITLB_MISS
);
3508 /* No change for non-gateway pages or for priv decrease. */
3509 if (type
>= 4 && type
- 4 < ctx
->privilege
) {
3510 dest
= deposit32(dest
, 0, 2, type
- 4);
3513 dest
&= -4; /* priv = 0 */
3518 TCGv_reg tmp
= dest_gpr(ctx
, a
->l
);
3519 if (ctx
->privilege
< 3) {
3520 tcg_gen_andi_reg(tmp
, tmp
, -4);
3522 tcg_gen_ori_reg(tmp
, tmp
, ctx
->privilege
);
3523 save_gpr(ctx
, a
->l
, tmp
);
3526 return do_dbranch(ctx
, dest
, 0, a
->n
);
3529 static bool trans_blr(DisasContext
*ctx
, arg_blr
*a
)
3532 TCGv_reg tmp
= tcg_temp_new();
3533 tcg_gen_shli_reg(tmp
, load_gpr(ctx
, a
->x
), 3);
3534 tcg_gen_addi_reg(tmp
, tmp
, ctx
->iaoq_f
+ 8);
3535 /* The computation here never changes privilege level. */
3536 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3538 /* BLR R0,RX is a good way to load PC+8 into RX. */
3539 return do_dbranch(ctx
, ctx
->iaoq_f
+ 8, a
->l
, a
->n
);
3543 static bool trans_bv(DisasContext
*ctx
, arg_bv
*a
)
3548 dest
= load_gpr(ctx
, a
->b
);
3550 dest
= tcg_temp_new();
3551 tcg_gen_shli_reg(dest
, load_gpr(ctx
, a
->x
), 3);
3552 tcg_gen_add_reg(dest
, dest
, load_gpr(ctx
, a
->b
));
3554 dest
= do_ibranch_priv(ctx
, dest
);
3555 return do_ibranch(ctx
, dest
, 0, a
->n
);
3558 static bool trans_bve(DisasContext
*ctx
, arg_bve
*a
)
3562 #ifdef CONFIG_USER_ONLY
3563 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3564 return do_ibranch(ctx
, dest
, a
->l
, a
->n
);
3567 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3569 copy_iaoq_entry(ctx
, cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3570 if (ctx
->iaoq_b
== -1) {
3571 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3573 copy_iaoq_entry(ctx
, cpu_iaoq_b
, -1, dest
);
3574 tcg_gen_mov_i64(cpu_iasq_b
, space_select(ctx
, 0, dest
));
3576 copy_iaoq_entry(ctx
, cpu_gr
[a
->l
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3578 nullify_set(ctx
, a
->n
);
3579 tcg_gen_lookup_and_goto_ptr();
3580 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3581 return nullify_end(ctx
);
3589 static void gen_fcpy_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3591 tcg_gen_mov_i32(dst
, src
);
3594 static bool trans_fid_f(DisasContext
*ctx
, arg_fid_f
*a
)
3598 if (TARGET_REGISTER_BITS
== 64) {
3599 ret
= 0x13080000000000ULL
; /* PA8700 (PCX-W2) */
3601 ret
= 0x0f080000000000ULL
; /* PA7300LC (PCX-L2) */
3605 save_frd(0, tcg_constant_i64(ret
));
3606 return nullify_end(ctx
);
3609 static bool trans_fcpy_f(DisasContext
*ctx
, arg_fclass01
*a
)
3611 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fcpy_f
);
3614 static void gen_fcpy_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3616 tcg_gen_mov_i64(dst
, src
);
3619 static bool trans_fcpy_d(DisasContext
*ctx
, arg_fclass01
*a
)
3621 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fcpy_d
);
3624 static void gen_fabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3626 tcg_gen_andi_i32(dst
, src
, INT32_MAX
);
3629 static bool trans_fabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3631 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fabs_f
);
3634 static void gen_fabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3636 tcg_gen_andi_i64(dst
, src
, INT64_MAX
);
3639 static bool trans_fabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3641 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fabs_d
);
3644 static bool trans_fsqrt_f(DisasContext
*ctx
, arg_fclass01
*a
)
3646 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_s
);
3649 static bool trans_fsqrt_d(DisasContext
*ctx
, arg_fclass01
*a
)
3651 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_d
);
3654 static bool trans_frnd_f(DisasContext
*ctx
, arg_fclass01
*a
)
3656 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_frnd_s
);
3659 static bool trans_frnd_d(DisasContext
*ctx
, arg_fclass01
*a
)
3661 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_frnd_d
);
3664 static void gen_fneg_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3666 tcg_gen_xori_i32(dst
, src
, INT32_MIN
);
3669 static bool trans_fneg_f(DisasContext
*ctx
, arg_fclass01
*a
)
3671 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fneg_f
);
3674 static void gen_fneg_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3676 tcg_gen_xori_i64(dst
, src
, INT64_MIN
);
3679 static bool trans_fneg_d(DisasContext
*ctx
, arg_fclass01
*a
)
3681 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fneg_d
);
3684 static void gen_fnegabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3686 tcg_gen_ori_i32(dst
, src
, INT32_MIN
);
3689 static bool trans_fnegabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3691 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fnegabs_f
);
3694 static void gen_fnegabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3696 tcg_gen_ori_i64(dst
, src
, INT64_MIN
);
3699 static bool trans_fnegabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3701 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fnegabs_d
);
3708 static bool trans_fcnv_d_f(DisasContext
*ctx
, arg_fclass01
*a
)
3710 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_s
);
3713 static bool trans_fcnv_f_d(DisasContext
*ctx
, arg_fclass01
*a
)
3715 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_d
);
3718 static bool trans_fcnv_w_f(DisasContext
*ctx
, arg_fclass01
*a
)
3720 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_s
);
3723 static bool trans_fcnv_q_f(DisasContext
*ctx
, arg_fclass01
*a
)
3725 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_s
);
3728 static bool trans_fcnv_w_d(DisasContext
*ctx
, arg_fclass01
*a
)
3730 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_d
);
3733 static bool trans_fcnv_q_d(DisasContext
*ctx
, arg_fclass01
*a
)
3735 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_d
);
3738 static bool trans_fcnv_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3740 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_w
);
3743 static bool trans_fcnv_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3745 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_w
);
3748 static bool trans_fcnv_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3750 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_dw
);
3753 static bool trans_fcnv_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3755 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_dw
);
3758 static bool trans_fcnv_t_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3760 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_w
);
3763 static bool trans_fcnv_t_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3765 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_w
);
3768 static bool trans_fcnv_t_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3770 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_dw
);
3773 static bool trans_fcnv_t_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3775 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_dw
);
3778 static bool trans_fcnv_uw_f(DisasContext
*ctx
, arg_fclass01
*a
)
3780 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_s
);
3783 static bool trans_fcnv_uq_f(DisasContext
*ctx
, arg_fclass01
*a
)
3785 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_s
);
3788 static bool trans_fcnv_uw_d(DisasContext
*ctx
, arg_fclass01
*a
)
3790 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_d
);
3793 static bool trans_fcnv_uq_d(DisasContext
*ctx
, arg_fclass01
*a
)
3795 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_d
);
3798 static bool trans_fcnv_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3800 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_uw
);
3803 static bool trans_fcnv_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3805 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_uw
);
3808 static bool trans_fcnv_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3810 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_udw
);
3813 static bool trans_fcnv_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3815 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_udw
);
3818 static bool trans_fcnv_t_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3820 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_uw
);
3823 static bool trans_fcnv_t_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3825 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_uw
);
3828 static bool trans_fcnv_t_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3830 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_udw
);
3833 static bool trans_fcnv_t_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3835 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_udw
);
3842 static bool trans_fcmp_f(DisasContext
*ctx
, arg_fclass2
*a
)
3844 TCGv_i32 ta
, tb
, tc
, ty
;
3848 ta
= load_frw0_i32(a
->r1
);
3849 tb
= load_frw0_i32(a
->r2
);
3850 ty
= tcg_constant_i32(a
->y
);
3851 tc
= tcg_constant_i32(a
->c
);
3853 gen_helper_fcmp_s(tcg_env
, ta
, tb
, ty
, tc
);
3855 return nullify_end(ctx
);
3858 static bool trans_fcmp_d(DisasContext
*ctx
, arg_fclass2
*a
)
3865 ta
= load_frd0(a
->r1
);
3866 tb
= load_frd0(a
->r2
);
3867 ty
= tcg_constant_i32(a
->y
);
3868 tc
= tcg_constant_i32(a
->c
);
3870 gen_helper_fcmp_d(tcg_env
, ta
, tb
, ty
, tc
);
3872 return nullify_end(ctx
);
3875 static bool trans_ftest(DisasContext
*ctx
, arg_ftest
*a
)
3882 tcg_gen_ld32u_reg(t
, tcg_env
, offsetof(CPUHPPAState
, fr0_shadow
));
3889 case 0: /* simple */
3890 tcg_gen_andi_reg(t
, t
, 0x4000000);
3891 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3919 TCGv_reg c
= tcg_constant_reg(mask
);
3920 tcg_gen_or_reg(t
, t
, c
);
3921 ctx
->null_cond
= cond_make(TCG_COND_EQ
, t
, c
);
3923 tcg_gen_andi_reg(t
, t
, mask
);
3924 ctx
->null_cond
= cond_make_0(TCG_COND_EQ
, t
);
3927 unsigned cbit
= (a
->y
^ 1) - 1;
3929 tcg_gen_extract_reg(t
, t
, 21 - cbit
, 1);
3930 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3934 return nullify_end(ctx
);
3941 static bool trans_fadd_f(DisasContext
*ctx
, arg_fclass3
*a
)
3943 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_s
);
3946 static bool trans_fadd_d(DisasContext
*ctx
, arg_fclass3
*a
)
3948 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_d
);
3951 static bool trans_fsub_f(DisasContext
*ctx
, arg_fclass3
*a
)
3953 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_s
);
3956 static bool trans_fsub_d(DisasContext
*ctx
, arg_fclass3
*a
)
3958 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_d
);
3961 static bool trans_fmpy_f(DisasContext
*ctx
, arg_fclass3
*a
)
3963 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_s
);
3966 static bool trans_fmpy_d(DisasContext
*ctx
, arg_fclass3
*a
)
3968 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_d
);
3971 static bool trans_fdiv_f(DisasContext
*ctx
, arg_fclass3
*a
)
3973 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_s
);
3976 static bool trans_fdiv_d(DisasContext
*ctx
, arg_fclass3
*a
)
3978 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_d
);
3981 static bool trans_xmpyu(DisasContext
*ctx
, arg_xmpyu
*a
)
3987 x
= load_frw0_i64(a
->r1
);
3988 y
= load_frw0_i64(a
->r2
);
3989 tcg_gen_mul_i64(x
, x
, y
);
3992 return nullify_end(ctx
);
3995 /* Convert the fmpyadd single-precision register encodings to standard. */
3996 static inline int fmpyadd_s_reg(unsigned r
)
3998 return (r
& 16) * 2 + 16 + (r
& 15);
4001 static bool do_fmpyadd_s(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4003 int tm
= fmpyadd_s_reg(a
->tm
);
4004 int ra
= fmpyadd_s_reg(a
->ra
);
4005 int ta
= fmpyadd_s_reg(a
->ta
);
4006 int rm2
= fmpyadd_s_reg(a
->rm2
);
4007 int rm1
= fmpyadd_s_reg(a
->rm1
);
4011 do_fop_weww(ctx
, tm
, rm1
, rm2
, gen_helper_fmpy_s
);
4012 do_fop_weww(ctx
, ta
, ta
, ra
,
4013 is_sub
? gen_helper_fsub_s
: gen_helper_fadd_s
);
4015 return nullify_end(ctx
);
4018 static bool trans_fmpyadd_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4020 return do_fmpyadd_s(ctx
, a
, false);
4023 static bool trans_fmpysub_f(DisasContext
*ctx
, arg_mpyadd
*a
)
4025 return do_fmpyadd_s(ctx
, a
, true);
4028 static bool do_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4032 do_fop_dedd(ctx
, a
->tm
, a
->rm1
, a
->rm2
, gen_helper_fmpy_d
);
4033 do_fop_dedd(ctx
, a
->ta
, a
->ta
, a
->ra
,
4034 is_sub
? gen_helper_fsub_d
: gen_helper_fadd_d
);
4036 return nullify_end(ctx
);
4039 static bool trans_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4041 return do_fmpyadd_d(ctx
, a
, false);
4044 static bool trans_fmpysub_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4046 return do_fmpyadd_d(ctx
, a
, true);
4049 static bool trans_fmpyfadd_f(DisasContext
*ctx
, arg_fmpyfadd_f
*a
)
4054 x
= load_frw0_i32(a
->rm1
);
4055 y
= load_frw0_i32(a
->rm2
);
4056 z
= load_frw0_i32(a
->ra3
);
4059 gen_helper_fmpynfadd_s(x
, tcg_env
, x
, y
, z
);
4061 gen_helper_fmpyfadd_s(x
, tcg_env
, x
, y
, z
);
4064 save_frw_i32(a
->t
, x
);
4065 return nullify_end(ctx
);
4068 static bool trans_fmpyfadd_d(DisasContext
*ctx
, arg_fmpyfadd_d
*a
)
4073 x
= load_frd0(a
->rm1
);
4074 y
= load_frd0(a
->rm2
);
4075 z
= load_frd0(a
->ra3
);
4078 gen_helper_fmpynfadd_d(x
, tcg_env
, x
, y
, z
);
4080 gen_helper_fmpyfadd_d(x
, tcg_env
, x
, y
, z
);
4084 return nullify_end(ctx
);
4087 static bool trans_diag(DisasContext
*ctx
, arg_diag
*a
)
4089 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
4090 #ifndef CONFIG_USER_ONLY
4091 if (a
->i
== 0x100) {
4092 /* emulate PDC BTLB, called by SeaBIOS-hppa */
4094 gen_helper_diag_btlb(tcg_env
);
4095 return nullify_end(ctx
);
4098 qemu_log_mask(LOG_UNIMP
, "DIAG opcode 0x%04x ignored\n", a
->i
);
4102 static void hppa_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
4104 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4108 ctx
->tb_flags
= ctx
->base
.tb
->flags
;
4109 ctx
->is_pa20
= hppa_is_pa20(cpu_env(cs
));
4111 #ifdef CONFIG_USER_ONLY
4112 ctx
->privilege
= MMU_IDX_TO_PRIV(MMU_USER_IDX
);
4113 ctx
->mmu_idx
= MMU_USER_IDX
;
4114 ctx
->iaoq_f
= ctx
->base
.pc_first
| ctx
->privilege
;
4115 ctx
->iaoq_b
= ctx
->base
.tb
->cs_base
| ctx
->privilege
;
4116 ctx
->unalign
= (ctx
->tb_flags
& TB_FLAG_UNALIGN
? MO_UNALN
: MO_ALIGN
);
4118 ctx
->privilege
= (ctx
->tb_flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
4119 ctx
->mmu_idx
= (ctx
->tb_flags
& PSW_D
4120 ? PRIV_P_TO_MMU_IDX(ctx
->privilege
, ctx
->tb_flags
& PSW_P
)
4123 /* Recover the IAOQ values from the GVA + PRIV. */
4124 uint64_t cs_base
= ctx
->base
.tb
->cs_base
;
4125 uint64_t iasq_f
= cs_base
& ~0xffffffffull
;
4126 int32_t diff
= cs_base
;
4128 ctx
->iaoq_f
= (ctx
->base
.pc_first
& ~iasq_f
) + ctx
->privilege
;
4129 ctx
->iaoq_b
= (diff
? ctx
->iaoq_f
+ diff
: -1);
4132 ctx
->iaoq_n_var
= NULL
;
4134 /* Bound the number of instructions by those left on the page. */
4135 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
4136 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
4139 static void hppa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4141 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4143 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */
4144 ctx
->null_cond
= cond_make_f();
4145 ctx
->psw_n_nonzero
= false;
4146 if (ctx
->tb_flags
& PSW_N
) {
4147 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
4148 ctx
->psw_n_nonzero
= true;
4150 ctx
->null_lab
= NULL
;
4153 static void hppa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4155 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4157 tcg_gen_insn_start(ctx
->iaoq_f
, ctx
->iaoq_b
);
4160 static void hppa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
4162 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4163 CPUHPPAState
*env
= cpu_env(cs
);
4166 /* Execute one insn. */
4167 #ifdef CONFIG_USER_ONLY
4168 if (ctx
->base
.pc_next
< TARGET_PAGE_SIZE
) {
4170 ret
= ctx
->base
.is_jmp
;
4171 assert(ret
!= DISAS_NEXT
);
4175 /* Always fetch the insn, even if nullified, so that we check
4176 the page permissions for execute. */
4177 uint32_t insn
= translator_ldl(env
, &ctx
->base
, ctx
->base
.pc_next
);
4179 /* Set up the IA queue for the next insn.
4180 This will be overwritten by a branch. */
4181 if (ctx
->iaoq_b
== -1) {
4183 ctx
->iaoq_n_var
= tcg_temp_new();
4184 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
4186 ctx
->iaoq_n
= ctx
->iaoq_b
+ 4;
4187 ctx
->iaoq_n_var
= NULL
;
4190 if (unlikely(ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4191 ctx
->null_cond
.c
= TCG_COND_NEVER
;
4195 if (!decode(ctx
, insn
)) {
4198 ret
= ctx
->base
.is_jmp
;
4199 assert(ctx
->null_lab
== NULL
);
4203 /* Advance the insn queue. Note that this check also detects
4204 a priority change within the instruction queue. */
4205 if (ret
== DISAS_NEXT
&& ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
4206 if (ctx
->iaoq_b
!= -1 && ctx
->iaoq_n
!= -1
4207 && use_goto_tb(ctx
, ctx
->iaoq_b
)
4208 && (ctx
->null_cond
.c
== TCG_COND_NEVER
4209 || ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4210 nullify_set(ctx
, ctx
->null_cond
.c
== TCG_COND_ALWAYS
);
4211 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
4212 ctx
->base
.is_jmp
= ret
= DISAS_NORETURN
;
4214 ctx
->base
.is_jmp
= ret
= DISAS_IAQ_N_STALE
;
4217 ctx
->iaoq_f
= ctx
->iaoq_b
;
4218 ctx
->iaoq_b
= ctx
->iaoq_n
;
4219 ctx
->base
.pc_next
+= 4;
4222 case DISAS_NORETURN
:
4223 case DISAS_IAQ_N_UPDATED
:
4227 case DISAS_IAQ_N_STALE
:
4228 case DISAS_IAQ_N_STALE_EXIT
:
4229 if (ctx
->iaoq_f
== -1) {
4230 copy_iaoq_entry(ctx
, cpu_iaoq_f
, -1, cpu_iaoq_b
);
4231 copy_iaoq_entry(ctx
, cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
4232 #ifndef CONFIG_USER_ONLY
4233 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
4236 ctx
->base
.is_jmp
= (ret
== DISAS_IAQ_N_STALE_EXIT
4238 : DISAS_IAQ_N_UPDATED
);
4239 } else if (ctx
->iaoq_b
== -1) {
4240 copy_iaoq_entry(ctx
, cpu_iaoq_b
, -1, ctx
->iaoq_n_var
);
4245 g_assert_not_reached();
4249 static void hppa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
4251 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4252 DisasJumpType is_jmp
= ctx
->base
.is_jmp
;
4255 case DISAS_NORETURN
:
4257 case DISAS_TOO_MANY
:
4258 case DISAS_IAQ_N_STALE
:
4259 case DISAS_IAQ_N_STALE_EXIT
:
4260 copy_iaoq_entry(ctx
, cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
4261 copy_iaoq_entry(ctx
, cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
4264 case DISAS_IAQ_N_UPDATED
:
4265 if (is_jmp
!= DISAS_IAQ_N_STALE_EXIT
) {
4266 tcg_gen_lookup_and_goto_ptr();
4271 tcg_gen_exit_tb(NULL
, 0);
4274 g_assert_not_reached();
4278 static void hppa_tr_disas_log(const DisasContextBase
*dcbase
,
4279 CPUState
*cs
, FILE *logfile
)
4281 target_ulong pc
= dcbase
->pc_first
;
4283 #ifdef CONFIG_USER_ONLY
4286 fprintf(logfile
, "IN:\n0x00000000: (null)\n");
4289 fprintf(logfile
, "IN:\n0x000000b0: light-weight-syscall\n");
4292 fprintf(logfile
, "IN:\n0x000000e0: set-thread-pointer-syscall\n");
4295 fprintf(logfile
, "IN:\n0x00000100: syscall\n");
4300 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc
));
4301 target_disas(logfile
, cs
, pc
, dcbase
->tb
->size
);
4304 static const TranslatorOps hppa_tr_ops
= {
4305 .init_disas_context
= hppa_tr_init_disas_context
,
4306 .tb_start
= hppa_tr_tb_start
,
4307 .insn_start
= hppa_tr_insn_start
,
4308 .translate_insn
= hppa_tr_translate_insn
,
4309 .tb_stop
= hppa_tr_tb_stop
,
4310 .disas_log
= hppa_tr_disas_log
,
4313 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
4314 target_ulong pc
, void *host_pc
)
4317 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &hppa_tr_ops
, &ctx
.base
);