2 * HPPA emulation cpu translation for qemu.
4 * Copyright (c) 2016 Richard Henderson <rth@twiddle.net>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
22 #include "disas/disas.h"
23 #include "qemu/host-utils.h"
24 #include "exec/exec-all.h"
25 #include "tcg/tcg-op.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28 #include "exec/translator.h"
31 #define HELPER_H "helper.h"
32 #include "exec/helper-info.c.inc"
36 /* Since we have a distinction between register size and address size,
37 we need to redefine all of these. */
41 #undef tcg_global_mem_new
43 #if TARGET_LONG_BITS == 64
44 #define TCGv_tl TCGv_i64
45 #define tcg_temp_new_tl tcg_temp_new_i64
46 #if TARGET_REGISTER_BITS == 64
47 #define tcg_gen_extu_reg_tl tcg_gen_mov_i64
49 #define tcg_gen_extu_reg_tl tcg_gen_extu_i32_i64
52 #define TCGv_tl TCGv_i32
53 #define tcg_temp_new_tl tcg_temp_new_i32
54 #define tcg_gen_extu_reg_tl tcg_gen_mov_i32
57 #if TARGET_REGISTER_BITS == 64
58 #define TCGv_reg TCGv_i64
60 #define tcg_temp_new tcg_temp_new_i64
61 #define tcg_global_mem_new tcg_global_mem_new_i64
63 #define tcg_gen_movi_reg tcg_gen_movi_i64
64 #define tcg_gen_mov_reg tcg_gen_mov_i64
65 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i64
66 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i64
67 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i64
68 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i64
69 #define tcg_gen_ld32u_reg tcg_gen_ld32u_i64
70 #define tcg_gen_ld32s_reg tcg_gen_ld32s_i64
71 #define tcg_gen_ld_reg tcg_gen_ld_i64
72 #define tcg_gen_st8_reg tcg_gen_st8_i64
73 #define tcg_gen_st16_reg tcg_gen_st16_i64
74 #define tcg_gen_st32_reg tcg_gen_st32_i64
75 #define tcg_gen_st_reg tcg_gen_st_i64
76 #define tcg_gen_add_reg tcg_gen_add_i64
77 #define tcg_gen_addi_reg tcg_gen_addi_i64
78 #define tcg_gen_sub_reg tcg_gen_sub_i64
79 #define tcg_gen_neg_reg tcg_gen_neg_i64
80 #define tcg_gen_subfi_reg tcg_gen_subfi_i64
81 #define tcg_gen_subi_reg tcg_gen_subi_i64
82 #define tcg_gen_and_reg tcg_gen_and_i64
83 #define tcg_gen_andi_reg tcg_gen_andi_i64
84 #define tcg_gen_or_reg tcg_gen_or_i64
85 #define tcg_gen_ori_reg tcg_gen_ori_i64
86 #define tcg_gen_xor_reg tcg_gen_xor_i64
87 #define tcg_gen_xori_reg tcg_gen_xori_i64
88 #define tcg_gen_not_reg tcg_gen_not_i64
89 #define tcg_gen_shl_reg tcg_gen_shl_i64
90 #define tcg_gen_shli_reg tcg_gen_shli_i64
91 #define tcg_gen_shr_reg tcg_gen_shr_i64
92 #define tcg_gen_shri_reg tcg_gen_shri_i64
93 #define tcg_gen_sar_reg tcg_gen_sar_i64
94 #define tcg_gen_sari_reg tcg_gen_sari_i64
95 #define tcg_gen_brcond_reg tcg_gen_brcond_i64
96 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i64
97 #define tcg_gen_setcond_reg tcg_gen_setcond_i64
98 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i64
99 #define tcg_gen_mul_reg tcg_gen_mul_i64
100 #define tcg_gen_muli_reg tcg_gen_muli_i64
101 #define tcg_gen_div_reg tcg_gen_div_i64
102 #define tcg_gen_rem_reg tcg_gen_rem_i64
103 #define tcg_gen_divu_reg tcg_gen_divu_i64
104 #define tcg_gen_remu_reg tcg_gen_remu_i64
105 #define tcg_gen_discard_reg tcg_gen_discard_i64
106 #define tcg_gen_trunc_reg_i32 tcg_gen_extrl_i64_i32
107 #define tcg_gen_trunc_i64_reg tcg_gen_mov_i64
108 #define tcg_gen_extu_i32_reg tcg_gen_extu_i32_i64
109 #define tcg_gen_ext_i32_reg tcg_gen_ext_i32_i64
110 #define tcg_gen_extu_reg_i64 tcg_gen_mov_i64
111 #define tcg_gen_ext_reg_i64 tcg_gen_mov_i64
112 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i64
113 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i64
114 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i64
115 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i64
116 #define tcg_gen_ext32u_reg tcg_gen_ext32u_i64
117 #define tcg_gen_ext32s_reg tcg_gen_ext32s_i64
118 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i64
119 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i64
120 #define tcg_gen_bswap64_reg tcg_gen_bswap64_i64
121 #define tcg_gen_concat_reg_i64 tcg_gen_concat32_i64
122 #define tcg_gen_andc_reg tcg_gen_andc_i64
123 #define tcg_gen_eqv_reg tcg_gen_eqv_i64
124 #define tcg_gen_nand_reg tcg_gen_nand_i64
125 #define tcg_gen_nor_reg tcg_gen_nor_i64
126 #define tcg_gen_orc_reg tcg_gen_orc_i64
127 #define tcg_gen_clz_reg tcg_gen_clz_i64
128 #define tcg_gen_ctz_reg tcg_gen_ctz_i64
129 #define tcg_gen_clzi_reg tcg_gen_clzi_i64
130 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i64
131 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i64
132 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i64
133 #define tcg_gen_rotl_reg tcg_gen_rotl_i64
134 #define tcg_gen_rotli_reg tcg_gen_rotli_i64
135 #define tcg_gen_rotr_reg tcg_gen_rotr_i64
136 #define tcg_gen_rotri_reg tcg_gen_rotri_i64
137 #define tcg_gen_deposit_reg tcg_gen_deposit_i64
138 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i64
139 #define tcg_gen_extract_reg tcg_gen_extract_i64
140 #define tcg_gen_sextract_reg tcg_gen_sextract_i64
141 #define tcg_gen_extract2_reg tcg_gen_extract2_i64
142 #define tcg_constant_reg tcg_constant_i64
143 #define tcg_gen_movcond_reg tcg_gen_movcond_i64
144 #define tcg_gen_add2_reg tcg_gen_add2_i64
145 #define tcg_gen_sub2_reg tcg_gen_sub2_i64
146 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i64
147 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i64
148 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i64
149 #define tcg_gen_trunc_reg_ptr tcg_gen_trunc_i64_ptr
151 #define TCGv_reg TCGv_i32
152 #define tcg_temp_new tcg_temp_new_i32
153 #define tcg_global_mem_new tcg_global_mem_new_i32
155 #define tcg_gen_movi_reg tcg_gen_movi_i32
156 #define tcg_gen_mov_reg tcg_gen_mov_i32
157 #define tcg_gen_ld8u_reg tcg_gen_ld8u_i32
158 #define tcg_gen_ld8s_reg tcg_gen_ld8s_i32
159 #define tcg_gen_ld16u_reg tcg_gen_ld16u_i32
160 #define tcg_gen_ld16s_reg tcg_gen_ld16s_i32
161 #define tcg_gen_ld32u_reg tcg_gen_ld_i32
162 #define tcg_gen_ld32s_reg tcg_gen_ld_i32
163 #define tcg_gen_ld_reg tcg_gen_ld_i32
164 #define tcg_gen_st8_reg tcg_gen_st8_i32
165 #define tcg_gen_st16_reg tcg_gen_st16_i32
166 #define tcg_gen_st32_reg tcg_gen_st32_i32
167 #define tcg_gen_st_reg tcg_gen_st_i32
168 #define tcg_gen_add_reg tcg_gen_add_i32
169 #define tcg_gen_addi_reg tcg_gen_addi_i32
170 #define tcg_gen_sub_reg tcg_gen_sub_i32
171 #define tcg_gen_neg_reg tcg_gen_neg_i32
172 #define tcg_gen_subfi_reg tcg_gen_subfi_i32
173 #define tcg_gen_subi_reg tcg_gen_subi_i32
174 #define tcg_gen_and_reg tcg_gen_and_i32
175 #define tcg_gen_andi_reg tcg_gen_andi_i32
176 #define tcg_gen_or_reg tcg_gen_or_i32
177 #define tcg_gen_ori_reg tcg_gen_ori_i32
178 #define tcg_gen_xor_reg tcg_gen_xor_i32
179 #define tcg_gen_xori_reg tcg_gen_xori_i32
180 #define tcg_gen_not_reg tcg_gen_not_i32
181 #define tcg_gen_shl_reg tcg_gen_shl_i32
182 #define tcg_gen_shli_reg tcg_gen_shli_i32
183 #define tcg_gen_shr_reg tcg_gen_shr_i32
184 #define tcg_gen_shri_reg tcg_gen_shri_i32
185 #define tcg_gen_sar_reg tcg_gen_sar_i32
186 #define tcg_gen_sari_reg tcg_gen_sari_i32
187 #define tcg_gen_brcond_reg tcg_gen_brcond_i32
188 #define tcg_gen_brcondi_reg tcg_gen_brcondi_i32
189 #define tcg_gen_setcond_reg tcg_gen_setcond_i32
190 #define tcg_gen_setcondi_reg tcg_gen_setcondi_i32
191 #define tcg_gen_mul_reg tcg_gen_mul_i32
192 #define tcg_gen_muli_reg tcg_gen_muli_i32
193 #define tcg_gen_div_reg tcg_gen_div_i32
194 #define tcg_gen_rem_reg tcg_gen_rem_i32
195 #define tcg_gen_divu_reg tcg_gen_divu_i32
196 #define tcg_gen_remu_reg tcg_gen_remu_i32
197 #define tcg_gen_discard_reg tcg_gen_discard_i32
198 #define tcg_gen_trunc_reg_i32 tcg_gen_mov_i32
199 #define tcg_gen_trunc_i64_reg tcg_gen_extrl_i64_i32
200 #define tcg_gen_extu_i32_reg tcg_gen_mov_i32
201 #define tcg_gen_ext_i32_reg tcg_gen_mov_i32
202 #define tcg_gen_extu_reg_i64 tcg_gen_extu_i32_i64
203 #define tcg_gen_ext_reg_i64 tcg_gen_ext_i32_i64
204 #define tcg_gen_ext8u_reg tcg_gen_ext8u_i32
205 #define tcg_gen_ext8s_reg tcg_gen_ext8s_i32
206 #define tcg_gen_ext16u_reg tcg_gen_ext16u_i32
207 #define tcg_gen_ext16s_reg tcg_gen_ext16s_i32
208 #define tcg_gen_ext32u_reg tcg_gen_mov_i32
209 #define tcg_gen_ext32s_reg tcg_gen_mov_i32
210 #define tcg_gen_bswap16_reg tcg_gen_bswap16_i32
211 #define tcg_gen_bswap32_reg tcg_gen_bswap32_i32
212 #define tcg_gen_concat_reg_i64 tcg_gen_concat_i32_i64
213 #define tcg_gen_andc_reg tcg_gen_andc_i32
214 #define tcg_gen_eqv_reg tcg_gen_eqv_i32
215 #define tcg_gen_nand_reg tcg_gen_nand_i32
216 #define tcg_gen_nor_reg tcg_gen_nor_i32
217 #define tcg_gen_orc_reg tcg_gen_orc_i32
218 #define tcg_gen_clz_reg tcg_gen_clz_i32
219 #define tcg_gen_ctz_reg tcg_gen_ctz_i32
220 #define tcg_gen_clzi_reg tcg_gen_clzi_i32
221 #define tcg_gen_ctzi_reg tcg_gen_ctzi_i32
222 #define tcg_gen_clrsb_reg tcg_gen_clrsb_i32
223 #define tcg_gen_ctpop_reg tcg_gen_ctpop_i32
224 #define tcg_gen_rotl_reg tcg_gen_rotl_i32
225 #define tcg_gen_rotli_reg tcg_gen_rotli_i32
226 #define tcg_gen_rotr_reg tcg_gen_rotr_i32
227 #define tcg_gen_rotri_reg tcg_gen_rotri_i32
228 #define tcg_gen_deposit_reg tcg_gen_deposit_i32
229 #define tcg_gen_deposit_z_reg tcg_gen_deposit_z_i32
230 #define tcg_gen_extract_reg tcg_gen_extract_i32
231 #define tcg_gen_sextract_reg tcg_gen_sextract_i32
232 #define tcg_gen_extract2_reg tcg_gen_extract2_i32
233 #define tcg_constant_reg tcg_constant_i32
234 #define tcg_gen_movcond_reg tcg_gen_movcond_i32
235 #define tcg_gen_add2_reg tcg_gen_add2_i32
236 #define tcg_gen_sub2_reg tcg_gen_sub2_i32
237 #define tcg_gen_qemu_ld_reg tcg_gen_qemu_ld_i32
238 #define tcg_gen_qemu_st_reg tcg_gen_qemu_st_i32
239 #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
240 #define tcg_gen_trunc_reg_ptr tcg_gen_ext_i32_ptr
241 #endif /* TARGET_REGISTER_BITS */
243 typedef struct DisasCond
{
248 typedef struct DisasContext
{
249 DisasContextBase base
;
266 #ifdef CONFIG_USER_ONLY
271 #ifdef CONFIG_USER_ONLY
272 #define UNALIGN(C) (C)->unalign
274 #define UNALIGN(C) MO_ALIGN
277 /* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */
278 static int expand_sm_imm(DisasContext
*ctx
, int val
)
280 if (val
& PSW_SM_E
) {
281 val
= (val
& ~PSW_SM_E
) | PSW_E
;
283 if (val
& PSW_SM_W
) {
284 val
= (val
& ~PSW_SM_W
) | PSW_W
;
289 /* Inverted space register indicates 0 means sr0 not inferred from base. */
290 static int expand_sr3x(DisasContext
*ctx
, int val
)
295 /* Convert the M:A bits within a memory insn to the tri-state value
296 we use for the final M. */
297 static int ma_to_m(DisasContext
*ctx
, int val
)
299 return val
& 2 ? (val
& 1 ? -1 : 1) : 0;
302 /* Convert the sign of the displacement to a pre or post-modify. */
303 static int pos_to_m(DisasContext
*ctx
, int val
)
308 static int neg_to_m(DisasContext
*ctx
, int val
)
313 /* Used for branch targets and fp memory ops. */
314 static int expand_shl2(DisasContext
*ctx
, int val
)
319 /* Used for fp memory ops. */
320 static int expand_shl3(DisasContext
*ctx
, int val
)
325 /* Used for assemble_21. */
326 static int expand_shl11(DisasContext
*ctx
, int val
)
332 /* Include the auto-generated decoder. */
333 #include "decode-insns.c.inc"
335 /* We are not using a goto_tb (for whatever reason), but have updated
336 the iaq (for whatever reason), so don't do it again on exit. */
337 #define DISAS_IAQ_N_UPDATED DISAS_TARGET_0
339 /* We are exiting the TB, but have neither emitted a goto_tb, nor
340 updated the iaq for the next instruction to be executed. */
341 #define DISAS_IAQ_N_STALE DISAS_TARGET_1
343 /* Similarly, but we want to return to the main loop immediately
344 to recognize unmasked interrupts. */
345 #define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2
346 #define DISAS_EXIT DISAS_TARGET_3
348 /* global register indexes */
349 static TCGv_reg cpu_gr
[32];
350 static TCGv_i64 cpu_sr
[4];
351 static TCGv_i64 cpu_srH
;
352 static TCGv_reg cpu_iaoq_f
;
353 static TCGv_reg cpu_iaoq_b
;
354 static TCGv_i64 cpu_iasq_f
;
355 static TCGv_i64 cpu_iasq_b
;
356 static TCGv_reg cpu_sar
;
357 static TCGv_reg cpu_psw_n
;
358 static TCGv_reg cpu_psw_v
;
359 static TCGv_reg cpu_psw_cb
;
360 static TCGv_reg cpu_psw_cb_msb
;
362 void hppa_translate_init(void)
364 #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) }
366 typedef struct { TCGv_reg
*var
; const char *name
; int ofs
; } GlobalVar
;
367 static const GlobalVar vars
[] = {
368 { &cpu_sar
, "sar", offsetof(CPUHPPAState
, cr
[CR_SAR
]) },
379 /* Use the symbolic register names that match the disassembler. */
380 static const char gr_names
[32][4] = {
381 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
382 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
383 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
384 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
386 /* SR[4-7] are not global registers so that we can index them. */
387 static const char sr_names
[5][4] = {
388 "sr0", "sr1", "sr2", "sr3", "srH"
394 for (i
= 1; i
< 32; i
++) {
395 cpu_gr
[i
] = tcg_global_mem_new(tcg_env
,
396 offsetof(CPUHPPAState
, gr
[i
]),
399 for (i
= 0; i
< 4; i
++) {
400 cpu_sr
[i
] = tcg_global_mem_new_i64(tcg_env
,
401 offsetof(CPUHPPAState
, sr
[i
]),
404 cpu_srH
= tcg_global_mem_new_i64(tcg_env
,
405 offsetof(CPUHPPAState
, sr
[4]),
408 for (i
= 0; i
< ARRAY_SIZE(vars
); ++i
) {
409 const GlobalVar
*v
= &vars
[i
];
410 *v
->var
= tcg_global_mem_new(tcg_env
, v
->ofs
, v
->name
);
413 cpu_iasq_f
= tcg_global_mem_new_i64(tcg_env
,
414 offsetof(CPUHPPAState
, iasq_f
),
416 cpu_iasq_b
= tcg_global_mem_new_i64(tcg_env
,
417 offsetof(CPUHPPAState
, iasq_b
),
421 static DisasCond
cond_make_f(void)
430 static DisasCond
cond_make_t(void)
433 .c
= TCG_COND_ALWAYS
,
439 static DisasCond
cond_make_n(void)
444 .a1
= tcg_constant_reg(0)
448 static DisasCond
cond_make_0_tmp(TCGCond c
, TCGv_reg a0
)
450 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
452 .c
= c
, .a0
= a0
, .a1
= tcg_constant_reg(0)
456 static DisasCond
cond_make_0(TCGCond c
, TCGv_reg a0
)
458 TCGv_reg tmp
= tcg_temp_new();
459 tcg_gen_mov_reg(tmp
, a0
);
460 return cond_make_0_tmp(c
, tmp
);
463 static DisasCond
cond_make(TCGCond c
, TCGv_reg a0
, TCGv_reg a1
)
465 DisasCond r
= { .c
= c
};
467 assert (c
!= TCG_COND_NEVER
&& c
!= TCG_COND_ALWAYS
);
468 r
.a0
= tcg_temp_new();
469 tcg_gen_mov_reg(r
.a0
, a0
);
470 r
.a1
= tcg_temp_new();
471 tcg_gen_mov_reg(r
.a1
, a1
);
476 static void cond_free(DisasCond
*cond
)
483 case TCG_COND_ALWAYS
:
484 cond
->c
= TCG_COND_NEVER
;
491 static TCGv_reg
load_gpr(DisasContext
*ctx
, unsigned reg
)
494 TCGv_reg t
= tcg_temp_new();
495 tcg_gen_movi_reg(t
, 0);
502 static TCGv_reg
dest_gpr(DisasContext
*ctx
, unsigned reg
)
504 if (reg
== 0 || ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
505 return tcg_temp_new();
511 static void save_or_nullify(DisasContext
*ctx
, TCGv_reg dest
, TCGv_reg t
)
513 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
514 tcg_gen_movcond_reg(ctx
->null_cond
.c
, dest
, ctx
->null_cond
.a0
,
515 ctx
->null_cond
.a1
, dest
, t
);
517 tcg_gen_mov_reg(dest
, t
);
521 static void save_gpr(DisasContext
*ctx
, unsigned reg
, TCGv_reg t
)
524 save_or_nullify(ctx
, cpu_gr
[reg
], t
);
536 static TCGv_i32
load_frw_i32(unsigned rt
)
538 TCGv_i32 ret
= tcg_temp_new_i32();
539 tcg_gen_ld_i32(ret
, tcg_env
,
540 offsetof(CPUHPPAState
, fr
[rt
& 31])
541 + (rt
& 32 ? LO_OFS
: HI_OFS
));
545 static TCGv_i32
load_frw0_i32(unsigned rt
)
548 TCGv_i32 ret
= tcg_temp_new_i32();
549 tcg_gen_movi_i32(ret
, 0);
552 return load_frw_i32(rt
);
556 static TCGv_i64
load_frw0_i64(unsigned rt
)
558 TCGv_i64 ret
= tcg_temp_new_i64();
560 tcg_gen_movi_i64(ret
, 0);
562 tcg_gen_ld32u_i64(ret
, tcg_env
,
563 offsetof(CPUHPPAState
, fr
[rt
& 31])
564 + (rt
& 32 ? LO_OFS
: HI_OFS
));
569 static void save_frw_i32(unsigned rt
, TCGv_i32 val
)
571 tcg_gen_st_i32(val
, tcg_env
,
572 offsetof(CPUHPPAState
, fr
[rt
& 31])
573 + (rt
& 32 ? LO_OFS
: HI_OFS
));
579 static TCGv_i64
load_frd(unsigned rt
)
581 TCGv_i64 ret
= tcg_temp_new_i64();
582 tcg_gen_ld_i64(ret
, tcg_env
, offsetof(CPUHPPAState
, fr
[rt
]));
586 static TCGv_i64
load_frd0(unsigned rt
)
589 TCGv_i64 ret
= tcg_temp_new_i64();
590 tcg_gen_movi_i64(ret
, 0);
597 static void save_frd(unsigned rt
, TCGv_i64 val
)
599 tcg_gen_st_i64(val
, tcg_env
, offsetof(CPUHPPAState
, fr
[rt
]));
602 static void load_spr(DisasContext
*ctx
, TCGv_i64 dest
, unsigned reg
)
604 #ifdef CONFIG_USER_ONLY
605 tcg_gen_movi_i64(dest
, 0);
608 tcg_gen_mov_i64(dest
, cpu_sr
[reg
]);
609 } else if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
610 tcg_gen_mov_i64(dest
, cpu_srH
);
612 tcg_gen_ld_i64(dest
, tcg_env
, offsetof(CPUHPPAState
, sr
[reg
]));
617 /* Skip over the implementation of an insn that has been nullified.
618 Use this when the insn is too complex for a conditional move. */
619 static void nullify_over(DisasContext
*ctx
)
621 if (ctx
->null_cond
.c
!= TCG_COND_NEVER
) {
622 /* The always condition should have been handled in the main loop. */
623 assert(ctx
->null_cond
.c
!= TCG_COND_ALWAYS
);
625 ctx
->null_lab
= gen_new_label();
627 /* If we're using PSW[N], copy it to a temp because... */
628 if (ctx
->null_cond
.a0
== cpu_psw_n
) {
629 ctx
->null_cond
.a0
= tcg_temp_new();
630 tcg_gen_mov_reg(ctx
->null_cond
.a0
, cpu_psw_n
);
632 /* ... we clear it before branching over the implementation,
633 so that (1) it's clear after nullifying this insn and
634 (2) if this insn nullifies the next, PSW[N] is valid. */
635 if (ctx
->psw_n_nonzero
) {
636 ctx
->psw_n_nonzero
= false;
637 tcg_gen_movi_reg(cpu_psw_n
, 0);
640 tcg_gen_brcond_reg(ctx
->null_cond
.c
, ctx
->null_cond
.a0
,
641 ctx
->null_cond
.a1
, ctx
->null_lab
);
642 cond_free(&ctx
->null_cond
);
646 /* Save the current nullification state to PSW[N]. */
647 static void nullify_save(DisasContext
*ctx
)
649 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
650 if (ctx
->psw_n_nonzero
) {
651 tcg_gen_movi_reg(cpu_psw_n
, 0);
655 if (ctx
->null_cond
.a0
!= cpu_psw_n
) {
656 tcg_gen_setcond_reg(ctx
->null_cond
.c
, cpu_psw_n
,
657 ctx
->null_cond
.a0
, ctx
->null_cond
.a1
);
658 ctx
->psw_n_nonzero
= true;
660 cond_free(&ctx
->null_cond
);
663 /* Set a PSW[N] to X. The intention is that this is used immediately
664 before a goto_tb/exit_tb, so that there is no fallthru path to other
665 code within the TB. Therefore we do not update psw_n_nonzero. */
666 static void nullify_set(DisasContext
*ctx
, bool x
)
668 if (ctx
->psw_n_nonzero
|| x
) {
669 tcg_gen_movi_reg(cpu_psw_n
, x
);
673 /* Mark the end of an instruction that may have been nullified.
674 This is the pair to nullify_over. Always returns true so that
675 it may be tail-called from a translate function. */
676 static bool nullify_end(DisasContext
*ctx
)
678 TCGLabel
*null_lab
= ctx
->null_lab
;
679 DisasJumpType status
= ctx
->base
.is_jmp
;
681 /* For NEXT, NORETURN, STALE, we can easily continue (or exit).
682 For UPDATED, we cannot update on the nullified path. */
683 assert(status
!= DISAS_IAQ_N_UPDATED
);
685 if (likely(null_lab
== NULL
)) {
686 /* The current insn wasn't conditional or handled the condition
687 applied to it without a branch, so the (new) setting of
688 NULL_COND can be applied directly to the next insn. */
691 ctx
->null_lab
= NULL
;
693 if (likely(ctx
->null_cond
.c
== TCG_COND_NEVER
)) {
694 /* The next instruction will be unconditional,
695 and NULL_COND already reflects that. */
696 gen_set_label(null_lab
);
698 /* The insn that we just executed is itself nullifying the next
699 instruction. Store the condition in the PSW[N] global.
700 We asserted PSW[N] = 0 in nullify_over, so that after the
701 label we have the proper value in place. */
703 gen_set_label(null_lab
);
704 ctx
->null_cond
= cond_make_n();
706 if (status
== DISAS_NORETURN
) {
707 ctx
->base
.is_jmp
= DISAS_NEXT
;
712 static void copy_iaoq_entry(TCGv_reg dest
, target_ureg ival
, TCGv_reg vval
)
714 if (unlikely(ival
== -1)) {
715 tcg_gen_mov_reg(dest
, vval
);
717 tcg_gen_movi_reg(dest
, ival
);
721 static inline target_ureg
iaoq_dest(DisasContext
*ctx
, target_sreg disp
)
723 return ctx
->iaoq_f
+ disp
+ 8;
726 static void gen_excp_1(int exception
)
728 gen_helper_excp(tcg_env
, tcg_constant_i32(exception
));
731 static void gen_excp(DisasContext
*ctx
, int exception
)
733 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
734 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
736 gen_excp_1(exception
);
737 ctx
->base
.is_jmp
= DISAS_NORETURN
;
740 static bool gen_excp_iir(DisasContext
*ctx
, int exc
)
743 tcg_gen_st_reg(tcg_constant_reg(ctx
->insn
),
744 tcg_env
, offsetof(CPUHPPAState
, cr
[CR_IIR
]));
746 return nullify_end(ctx
);
749 static bool gen_illegal(DisasContext
*ctx
)
751 return gen_excp_iir(ctx
, EXCP_ILL
);
754 #ifdef CONFIG_USER_ONLY
755 #define CHECK_MOST_PRIVILEGED(EXCP) \
756 return gen_excp_iir(ctx, EXCP)
758 #define CHECK_MOST_PRIVILEGED(EXCP) \
760 if (ctx->privilege != 0) { \
761 return gen_excp_iir(ctx, EXCP); \
766 static bool use_goto_tb(DisasContext
*ctx
, target_ureg dest
)
768 return translator_use_goto_tb(&ctx
->base
, dest
);
771 /* If the next insn is to be nullified, and it's on the same page,
772 and we're not attempting to set a breakpoint on it, then we can
773 totally skip the nullified insn. This avoids creating and
774 executing a TB that merely branches to the next TB. */
775 static bool use_nullify_skip(DisasContext
*ctx
)
777 return (((ctx
->iaoq_b
^ ctx
->iaoq_f
) & TARGET_PAGE_MASK
) == 0
778 && !cpu_breakpoint_test(ctx
->cs
, ctx
->iaoq_b
, BP_ANY
));
781 static void gen_goto_tb(DisasContext
*ctx
, int which
,
782 target_ureg f
, target_ureg b
)
784 if (f
!= -1 && b
!= -1 && use_goto_tb(ctx
, f
)) {
785 tcg_gen_goto_tb(which
);
786 tcg_gen_movi_reg(cpu_iaoq_f
, f
);
787 tcg_gen_movi_reg(cpu_iaoq_b
, b
);
788 tcg_gen_exit_tb(ctx
->base
.tb
, which
);
790 copy_iaoq_entry(cpu_iaoq_f
, f
, cpu_iaoq_b
);
791 copy_iaoq_entry(cpu_iaoq_b
, b
, ctx
->iaoq_n_var
);
792 tcg_gen_lookup_and_goto_ptr();
796 static bool cond_need_sv(int c
)
798 return c
== 2 || c
== 3 || c
== 6;
801 static bool cond_need_cb(int c
)
803 return c
== 4 || c
== 5;
806 /* Need extensions from TCGv_i32 to TCGv_reg. */
807 static bool cond_need_ext(DisasContext
*ctx
, bool d
)
809 return TARGET_REGISTER_BITS
== 64 && !d
;
813 * Compute conditional for arithmetic. See Page 5-3, Table 5-1, of
814 * the Parisc 1.1 Architecture Reference Manual for details.
817 static DisasCond
do_cond(unsigned cf
, TCGv_reg res
,
818 TCGv_reg cb_msb
, TCGv_reg sv
)
824 case 0: /* Never / TR (0 / 1) */
825 cond
= cond_make_f();
827 case 1: /* = / <> (Z / !Z) */
828 cond
= cond_make_0(TCG_COND_EQ
, res
);
830 case 2: /* < / >= (N ^ V / !(N ^ V) */
831 tmp
= tcg_temp_new();
832 tcg_gen_xor_reg(tmp
, res
, sv
);
833 cond
= cond_make_0_tmp(TCG_COND_LT
, tmp
);
835 case 3: /* <= / > (N ^ V) | Z / !((N ^ V) | Z) */
839 * ((res < 0) ^ (sv < 0)) | !res
840 * ((res ^ sv) < 0) | !res
841 * (~(res ^ sv) >= 0) | !res
842 * !(~(res ^ sv) >> 31) | !res
843 * !(~(res ^ sv) >> 31 & res)
845 tmp
= tcg_temp_new();
846 tcg_gen_eqv_reg(tmp
, res
, sv
);
847 tcg_gen_sari_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
848 tcg_gen_and_reg(tmp
, tmp
, res
);
849 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
851 case 4: /* NUV / UV (!C / C) */
852 cond
= cond_make_0(TCG_COND_EQ
, cb_msb
);
854 case 5: /* ZNV / VNZ (!C | Z / C & !Z) */
855 tmp
= tcg_temp_new();
856 tcg_gen_neg_reg(tmp
, cb_msb
);
857 tcg_gen_and_reg(tmp
, tmp
, res
);
858 cond
= cond_make_0_tmp(TCG_COND_EQ
, tmp
);
860 case 6: /* SV / NSV (V / !V) */
861 cond
= cond_make_0(TCG_COND_LT
, sv
);
863 case 7: /* OD / EV */
864 tmp
= tcg_temp_new();
865 tcg_gen_andi_reg(tmp
, res
, 1);
866 cond
= cond_make_0_tmp(TCG_COND_NE
, tmp
);
869 g_assert_not_reached();
872 cond
.c
= tcg_invert_cond(cond
.c
);
878 /* Similar, but for the special case of subtraction without borrow, we
879 can use the inputs directly. This can allow other computation to be
880 deleted as unused. */
882 static DisasCond
do_sub_cond(unsigned cf
, TCGv_reg res
,
883 TCGv_reg in1
, TCGv_reg in2
, TCGv_reg sv
)
889 cond
= cond_make(TCG_COND_EQ
, in1
, in2
);
892 cond
= cond_make(TCG_COND_LT
, in1
, in2
);
895 cond
= cond_make(TCG_COND_LE
, in1
, in2
);
897 case 4: /* << / >>= */
898 cond
= cond_make(TCG_COND_LTU
, in1
, in2
);
900 case 5: /* <<= / >> */
901 cond
= cond_make(TCG_COND_LEU
, in1
, in2
);
904 return do_cond(cf
, res
, NULL
, sv
);
907 cond
.c
= tcg_invert_cond(cond
.c
);
914 * Similar, but for logicals, where the carry and overflow bits are not
915 * computed, and use of them is undefined.
917 * Undefined or not, hardware does not trap. It seems reasonable to
918 * assume hardware treats cases c={4,5,6} as if C=0 & V=0, since that's
919 * how cases c={2,3} are treated.
922 static DisasCond
do_log_cond(unsigned cf
, TCGv_reg res
)
926 case 9: /* undef, C */
927 case 11: /* undef, C & !Z */
928 case 12: /* undef, V */
929 return cond_make_f();
932 case 8: /* undef, !C */
933 case 10: /* undef, !C | Z */
934 case 13: /* undef, !V */
935 return cond_make_t();
938 return cond_make_0(TCG_COND_EQ
, res
);
940 return cond_make_0(TCG_COND_NE
, res
);
942 return cond_make_0(TCG_COND_LT
, res
);
944 return cond_make_0(TCG_COND_GE
, res
);
946 return cond_make_0(TCG_COND_LE
, res
);
948 return cond_make_0(TCG_COND_GT
, res
);
952 return do_cond(cf
, res
, NULL
, NULL
);
955 g_assert_not_reached();
959 /* Similar, but for shift/extract/deposit conditions. */
961 static DisasCond
do_sed_cond(unsigned orig
, TCGv_reg res
)
965 /* Convert the compressed condition codes to standard.
966 0-2 are the same as logicals (nv,<,<=), while 3 is OD.
967 4-7 are the reverse of 0-3. */
974 return do_log_cond(c
* 2 + f
, res
);
977 /* Similar, but for unit conditions. */
979 static DisasCond
do_unit_cond(unsigned cf
, TCGv_reg res
,
980 TCGv_reg in1
, TCGv_reg in2
)
983 TCGv_reg tmp
, cb
= NULL
;
986 /* Since we want to test lots of carry-out bits all at once, do not
987 * do our normal thing and compute carry-in of bit B+1 since that
988 * leaves us with carry bits spread across two words.
991 tmp
= tcg_temp_new();
992 tcg_gen_or_reg(cb
, in1
, in2
);
993 tcg_gen_and_reg(tmp
, in1
, in2
);
994 tcg_gen_andc_reg(cb
, cb
, res
);
995 tcg_gen_or_reg(cb
, cb
, tmp
);
999 case 0: /* never / TR */
1000 case 1: /* undefined */
1001 case 5: /* undefined */
1002 cond
= cond_make_f();
1005 case 2: /* SBZ / NBZ */
1006 /* See hasless(v,1) from
1007 * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
1009 tmp
= tcg_temp_new();
1010 tcg_gen_subi_reg(tmp
, res
, 0x01010101u
);
1011 tcg_gen_andc_reg(tmp
, tmp
, res
);
1012 tcg_gen_andi_reg(tmp
, tmp
, 0x80808080u
);
1013 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1016 case 3: /* SHZ / NHZ */
1017 tmp
= tcg_temp_new();
1018 tcg_gen_subi_reg(tmp
, res
, 0x00010001u
);
1019 tcg_gen_andc_reg(tmp
, tmp
, res
);
1020 tcg_gen_andi_reg(tmp
, tmp
, 0x80008000u
);
1021 cond
= cond_make_0(TCG_COND_NE
, tmp
);
1024 case 4: /* SDC / NDC */
1025 tcg_gen_andi_reg(cb
, cb
, 0x88888888u
);
1026 cond
= cond_make_0(TCG_COND_NE
, cb
);
1029 case 6: /* SBC / NBC */
1030 tcg_gen_andi_reg(cb
, cb
, 0x80808080u
);
1031 cond
= cond_make_0(TCG_COND_NE
, cb
);
1034 case 7: /* SHC / NHC */
1035 tcg_gen_andi_reg(cb
, cb
, 0x80008000u
);
1036 cond
= cond_make_0(TCG_COND_NE
, cb
);
1040 g_assert_not_reached();
1043 cond
.c
= tcg_invert_cond(cond
.c
);
1049 static TCGv_reg
get_carry(DisasContext
*ctx
, bool d
,
1050 TCGv_reg cb
, TCGv_reg cb_msb
)
1052 if (cond_need_ext(ctx
, d
)) {
1053 TCGv_reg t
= tcg_temp_new();
1054 tcg_gen_extract_reg(t
, cb
, 32, 1);
1060 static TCGv_reg
get_psw_carry(DisasContext
*ctx
, bool d
)
1062 return get_carry(ctx
, d
, cpu_psw_cb
, cpu_psw_cb_msb
);
1065 /* Compute signed overflow for addition. */
1066 static TCGv_reg
do_add_sv(DisasContext
*ctx
, TCGv_reg res
,
1067 TCGv_reg in1
, TCGv_reg in2
)
1069 TCGv_reg sv
= tcg_temp_new();
1070 TCGv_reg tmp
= tcg_temp_new();
1072 tcg_gen_xor_reg(sv
, res
, in1
);
1073 tcg_gen_xor_reg(tmp
, in1
, in2
);
1074 tcg_gen_andc_reg(sv
, sv
, tmp
);
1079 /* Compute signed overflow for subtraction. */
1080 static TCGv_reg
do_sub_sv(DisasContext
*ctx
, TCGv_reg res
,
1081 TCGv_reg in1
, TCGv_reg in2
)
1083 TCGv_reg sv
= tcg_temp_new();
1084 TCGv_reg tmp
= tcg_temp_new();
1086 tcg_gen_xor_reg(sv
, res
, in1
);
1087 tcg_gen_xor_reg(tmp
, in1
, in2
);
1088 tcg_gen_and_reg(sv
, sv
, tmp
);
1093 static void do_add(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1094 TCGv_reg in2
, unsigned shift
, bool is_l
,
1095 bool is_tsv
, bool is_tc
, bool is_c
, unsigned cf
)
1097 TCGv_reg dest
, cb
, cb_msb
, cb_cond
, sv
, tmp
;
1098 unsigned c
= cf
>> 1;
1102 dest
= tcg_temp_new();
1108 tmp
= tcg_temp_new();
1109 tcg_gen_shli_reg(tmp
, in1
, shift
);
1113 if (!is_l
|| cond_need_cb(c
)) {
1114 TCGv_reg zero
= tcg_constant_reg(0);
1115 cb_msb
= tcg_temp_new();
1116 cb
= tcg_temp_new();
1118 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, in2
, zero
);
1120 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
,
1121 get_psw_carry(ctx
, d
), zero
);
1123 tcg_gen_xor_reg(cb
, in1
, in2
);
1124 tcg_gen_xor_reg(cb
, cb
, dest
);
1125 if (cond_need_cb(c
)) {
1126 cb_cond
= get_carry(ctx
, d
, cb
, cb_msb
);
1129 tcg_gen_add_reg(dest
, in1
, in2
);
1131 tcg_gen_add_reg(dest
, dest
, get_psw_carry(ctx
, d
));
1135 /* Compute signed overflow if required. */
1137 if (is_tsv
|| cond_need_sv(c
)) {
1138 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
1140 /* ??? Need to include overflow from shift. */
1141 gen_helper_tsv(tcg_env
, sv
);
1145 /* Emit any conditional trap before any writeback. */
1146 cond
= do_cond(cf
, dest
, cb_cond
, sv
);
1148 tmp
= tcg_temp_new();
1149 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1150 gen_helper_tcond(tcg_env
, tmp
);
1153 /* Write back the result. */
1155 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1156 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1158 save_gpr(ctx
, rt
, dest
);
1160 /* Install the new nullification. */
1161 cond_free(&ctx
->null_cond
);
1162 ctx
->null_cond
= cond
;
1165 static bool do_add_reg(DisasContext
*ctx
, arg_rrr_cf_sh
*a
,
1166 bool is_l
, bool is_tsv
, bool is_tc
, bool is_c
)
1168 TCGv_reg tcg_r1
, tcg_r2
;
1173 tcg_r1
= load_gpr(ctx
, a
->r1
);
1174 tcg_r2
= load_gpr(ctx
, a
->r2
);
1175 do_add(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->sh
, is_l
, is_tsv
, is_tc
, is_c
, a
->cf
);
1176 return nullify_end(ctx
);
1179 static bool do_add_imm(DisasContext
*ctx
, arg_rri_cf
*a
,
1180 bool is_tsv
, bool is_tc
)
1182 TCGv_reg tcg_im
, tcg_r2
;
1187 tcg_im
= tcg_constant_reg(a
->i
);
1188 tcg_r2
= load_gpr(ctx
, a
->r
);
1189 do_add(ctx
, a
->t
, tcg_im
, tcg_r2
, 0, 0, is_tsv
, is_tc
, 0, a
->cf
);
1190 return nullify_end(ctx
);
1193 static void do_sub(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1194 TCGv_reg in2
, bool is_tsv
, bool is_b
,
1195 bool is_tc
, unsigned cf
)
1197 TCGv_reg dest
, sv
, cb
, cb_msb
, zero
, tmp
;
1198 unsigned c
= cf
>> 1;
1202 dest
= tcg_temp_new();
1203 cb
= tcg_temp_new();
1204 cb_msb
= tcg_temp_new();
1206 zero
= tcg_constant_reg(0);
1208 /* DEST,C = IN1 + ~IN2 + C. */
1209 tcg_gen_not_reg(cb
, in2
);
1210 tcg_gen_add2_reg(dest
, cb_msb
, in1
, zero
, get_psw_carry(ctx
, d
), zero
);
1211 tcg_gen_add2_reg(dest
, cb_msb
, dest
, cb_msb
, cb
, zero
);
1212 tcg_gen_xor_reg(cb
, cb
, in1
);
1213 tcg_gen_xor_reg(cb
, cb
, dest
);
1216 * DEST,C = IN1 + ~IN2 + 1. We can produce the same result in fewer
1217 * operations by seeding the high word with 1 and subtracting.
1219 TCGv_reg one
= tcg_constant_reg(1);
1220 tcg_gen_sub2_reg(dest
, cb_msb
, in1
, one
, in2
, zero
);
1221 tcg_gen_eqv_reg(cb
, in1
, in2
);
1222 tcg_gen_xor_reg(cb
, cb
, dest
);
1225 /* Compute signed overflow if required. */
1227 if (is_tsv
|| cond_need_sv(c
)) {
1228 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1230 gen_helper_tsv(tcg_env
, sv
);
1234 /* Compute the condition. We cannot use the special case for borrow. */
1236 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1238 cond
= do_cond(cf
, dest
, get_carry(ctx
, d
, cb
, cb_msb
), sv
);
1241 /* Emit any conditional trap before any writeback. */
1243 tmp
= tcg_temp_new();
1244 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1245 gen_helper_tcond(tcg_env
, tmp
);
1248 /* Write back the result. */
1249 save_or_nullify(ctx
, cpu_psw_cb
, cb
);
1250 save_or_nullify(ctx
, cpu_psw_cb_msb
, cb_msb
);
1251 save_gpr(ctx
, rt
, dest
);
1253 /* Install the new nullification. */
1254 cond_free(&ctx
->null_cond
);
1255 ctx
->null_cond
= cond
;
1258 static bool do_sub_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1259 bool is_tsv
, bool is_b
, bool is_tc
)
1261 TCGv_reg tcg_r1
, tcg_r2
;
1266 tcg_r1
= load_gpr(ctx
, a
->r1
);
1267 tcg_r2
= load_gpr(ctx
, a
->r2
);
1268 do_sub(ctx
, a
->t
, tcg_r1
, tcg_r2
, is_tsv
, is_b
, is_tc
, a
->cf
);
1269 return nullify_end(ctx
);
1272 static bool do_sub_imm(DisasContext
*ctx
, arg_rri_cf
*a
, bool is_tsv
)
1274 TCGv_reg tcg_im
, tcg_r2
;
1279 tcg_im
= tcg_constant_reg(a
->i
);
1280 tcg_r2
= load_gpr(ctx
, a
->r
);
1281 do_sub(ctx
, a
->t
, tcg_im
, tcg_r2
, is_tsv
, 0, 0, a
->cf
);
1282 return nullify_end(ctx
);
1285 static void do_cmpclr(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1286 TCGv_reg in2
, unsigned cf
)
1291 dest
= tcg_temp_new();
1292 tcg_gen_sub_reg(dest
, in1
, in2
);
1294 /* Compute signed overflow if required. */
1296 if (cond_need_sv(cf
>> 1)) {
1297 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
1300 /* Form the condition for the compare. */
1301 cond
= do_sub_cond(cf
, dest
, in1
, in2
, sv
);
1304 tcg_gen_movi_reg(dest
, 0);
1305 save_gpr(ctx
, rt
, dest
);
1307 /* Install the new nullification. */
1308 cond_free(&ctx
->null_cond
);
1309 ctx
->null_cond
= cond
;
1312 static void do_log(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1313 TCGv_reg in2
, unsigned cf
,
1314 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1316 TCGv_reg dest
= dest_gpr(ctx
, rt
);
1318 /* Perform the operation, and writeback. */
1320 save_gpr(ctx
, rt
, dest
);
1322 /* Install the new nullification. */
1323 cond_free(&ctx
->null_cond
);
1325 ctx
->null_cond
= do_log_cond(cf
, dest
);
1329 static bool do_log_reg(DisasContext
*ctx
, arg_rrr_cf
*a
,
1330 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1332 TCGv_reg tcg_r1
, tcg_r2
;
1337 tcg_r1
= load_gpr(ctx
, a
->r1
);
1338 tcg_r2
= load_gpr(ctx
, a
->r2
);
1339 do_log(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, fn
);
1340 return nullify_end(ctx
);
1343 static void do_unit(DisasContext
*ctx
, unsigned rt
, TCGv_reg in1
,
1344 TCGv_reg in2
, unsigned cf
, bool is_tc
,
1345 void (*fn
)(TCGv_reg
, TCGv_reg
, TCGv_reg
))
1351 dest
= dest_gpr(ctx
, rt
);
1353 save_gpr(ctx
, rt
, dest
);
1354 cond_free(&ctx
->null_cond
);
1356 dest
= tcg_temp_new();
1359 cond
= do_unit_cond(cf
, dest
, in1
, in2
);
1362 TCGv_reg tmp
= tcg_temp_new();
1363 tcg_gen_setcond_reg(cond
.c
, tmp
, cond
.a0
, cond
.a1
);
1364 gen_helper_tcond(tcg_env
, tmp
);
1366 save_gpr(ctx
, rt
, dest
);
1368 cond_free(&ctx
->null_cond
);
1369 ctx
->null_cond
= cond
;
1373 #ifndef CONFIG_USER_ONLY
1374 /* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
1375 from the top 2 bits of the base register. There are a few system
1376 instructions that have a 3-bit space specifier, for which SR0 is
1377 not special. To handle this, pass ~SP. */
1378 static TCGv_i64
space_select(DisasContext
*ctx
, int sp
, TCGv_reg base
)
1388 spc
= tcg_temp_new_tl();
1389 load_spr(ctx
, spc
, sp
);
1392 if (ctx
->tb_flags
& TB_FLAG_SR_SAME
) {
1396 ptr
= tcg_temp_new_ptr();
1397 tmp
= tcg_temp_new();
1398 spc
= tcg_temp_new_tl();
1400 tcg_gen_shri_reg(tmp
, base
, TARGET_REGISTER_BITS
- 5);
1401 tcg_gen_andi_reg(tmp
, tmp
, 030);
1402 tcg_gen_trunc_reg_ptr(ptr
, tmp
);
1404 tcg_gen_add_ptr(ptr
, ptr
, tcg_env
);
1405 tcg_gen_ld_i64(spc
, ptr
, offsetof(CPUHPPAState
, sr
[4]));
1411 static void form_gva(DisasContext
*ctx
, TCGv_tl
*pgva
, TCGv_reg
*pofs
,
1412 unsigned rb
, unsigned rx
, int scale
, target_sreg disp
,
1413 unsigned sp
, int modify
, bool is_phys
)
1415 TCGv_reg base
= load_gpr(ctx
, rb
);
1418 /* Note that RX is mutually exclusive with DISP. */
1420 ofs
= tcg_temp_new();
1421 tcg_gen_shli_reg(ofs
, cpu_gr
[rx
], scale
);
1422 tcg_gen_add_reg(ofs
, ofs
, base
);
1423 } else if (disp
|| modify
) {
1424 ofs
= tcg_temp_new();
1425 tcg_gen_addi_reg(ofs
, base
, disp
);
1431 #ifdef CONFIG_USER_ONLY
1432 *pgva
= (modify
<= 0 ? ofs
: base
);
1434 TCGv_tl addr
= tcg_temp_new_tl();
1435 tcg_gen_extu_reg_tl(addr
, modify
<= 0 ? ofs
: base
);
1436 if (ctx
->tb_flags
& PSW_W
) {
1437 tcg_gen_andi_tl(addr
, addr
, 0x3fffffffffffffffull
);
1440 tcg_gen_or_tl(addr
, addr
, space_select(ctx
, sp
, base
));
1446 /* Emit a memory load. The modify parameter should be
1447 * < 0 for pre-modify,
1448 * > 0 for post-modify,
1449 * = 0 for no base register update.
1451 static void do_load_32(DisasContext
*ctx
, TCGv_i32 dest
, unsigned rb
,
1452 unsigned rx
, int scale
, target_sreg disp
,
1453 unsigned sp
, int modify
, MemOp mop
)
1458 /* Caller uses nullify_over/nullify_end. */
1459 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1461 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1462 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1463 tcg_gen_qemu_ld_i32(dest
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1465 save_gpr(ctx
, rb
, ofs
);
1469 static void do_load_64(DisasContext
*ctx
, TCGv_i64 dest
, unsigned rb
,
1470 unsigned rx
, int scale
, target_sreg disp
,
1471 unsigned sp
, int modify
, MemOp mop
)
1476 /* Caller uses nullify_over/nullify_end. */
1477 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1479 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1480 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1481 tcg_gen_qemu_ld_i64(dest
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1483 save_gpr(ctx
, rb
, ofs
);
1487 static void do_store_32(DisasContext
*ctx
, TCGv_i32 src
, unsigned rb
,
1488 unsigned rx
, int scale
, target_sreg disp
,
1489 unsigned sp
, int modify
, MemOp mop
)
1494 /* Caller uses nullify_over/nullify_end. */
1495 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1497 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1498 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1499 tcg_gen_qemu_st_i32(src
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1501 save_gpr(ctx
, rb
, ofs
);
1505 static void do_store_64(DisasContext
*ctx
, TCGv_i64 src
, unsigned rb
,
1506 unsigned rx
, int scale
, target_sreg disp
,
1507 unsigned sp
, int modify
, MemOp mop
)
1512 /* Caller uses nullify_over/nullify_end. */
1513 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1515 form_gva(ctx
, &addr
, &ofs
, rb
, rx
, scale
, disp
, sp
, modify
,
1516 ctx
->mmu_idx
== MMU_PHYS_IDX
);
1517 tcg_gen_qemu_st_i64(src
, addr
, ctx
->mmu_idx
, mop
| UNALIGN(ctx
));
1519 save_gpr(ctx
, rb
, ofs
);
1523 #if TARGET_REGISTER_BITS == 64
1524 #define do_load_reg do_load_64
1525 #define do_store_reg do_store_64
1527 #define do_load_reg do_load_32
1528 #define do_store_reg do_store_32
1531 static bool do_load(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1532 unsigned rx
, int scale
, target_sreg disp
,
1533 unsigned sp
, int modify
, MemOp mop
)
1540 /* No base register update. */
1541 dest
= dest_gpr(ctx
, rt
);
1543 /* Make sure if RT == RB, we see the result of the load. */
1544 dest
= tcg_temp_new();
1546 do_load_reg(ctx
, dest
, rb
, rx
, scale
, disp
, sp
, modify
, mop
);
1547 save_gpr(ctx
, rt
, dest
);
1549 return nullify_end(ctx
);
1552 static bool do_floadw(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1553 unsigned rx
, int scale
, target_sreg disp
,
1554 unsigned sp
, int modify
)
1560 tmp
= tcg_temp_new_i32();
1561 do_load_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1562 save_frw_i32(rt
, tmp
);
1565 gen_helper_loaded_fr0(tcg_env
);
1568 return nullify_end(ctx
);
1571 static bool trans_fldw(DisasContext
*ctx
, arg_ldst
*a
)
1573 return do_floadw(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1574 a
->disp
, a
->sp
, a
->m
);
1577 static bool do_floadd(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1578 unsigned rx
, int scale
, target_sreg disp
,
1579 unsigned sp
, int modify
)
1585 tmp
= tcg_temp_new_i64();
1586 do_load_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUQ
);
1590 gen_helper_loaded_fr0(tcg_env
);
1593 return nullify_end(ctx
);
1596 static bool trans_fldd(DisasContext
*ctx
, arg_ldst
*a
)
1598 return do_floadd(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1599 a
->disp
, a
->sp
, a
->m
);
1602 static bool do_store(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1603 target_sreg disp
, unsigned sp
,
1604 int modify
, MemOp mop
)
1607 do_store_reg(ctx
, load_gpr(ctx
, rt
), rb
, 0, 0, disp
, sp
, modify
, mop
);
1608 return nullify_end(ctx
);
1611 static bool do_fstorew(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1612 unsigned rx
, int scale
, target_sreg disp
,
1613 unsigned sp
, int modify
)
1619 tmp
= load_frw_i32(rt
);
1620 do_store_32(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUL
);
1622 return nullify_end(ctx
);
1625 static bool trans_fstw(DisasContext
*ctx
, arg_ldst
*a
)
1627 return do_fstorew(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 2 : 0,
1628 a
->disp
, a
->sp
, a
->m
);
1631 static bool do_fstored(DisasContext
*ctx
, unsigned rt
, unsigned rb
,
1632 unsigned rx
, int scale
, target_sreg disp
,
1633 unsigned sp
, int modify
)
1640 do_store_64(ctx
, tmp
, rb
, rx
, scale
, disp
, sp
, modify
, MO_TEUQ
);
1642 return nullify_end(ctx
);
1645 static bool trans_fstd(DisasContext
*ctx
, arg_ldst
*a
)
1647 return do_fstored(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? 3 : 0,
1648 a
->disp
, a
->sp
, a
->m
);
1651 static bool do_fop_wew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1652 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
))
1657 tmp
= load_frw0_i32(ra
);
1659 func(tmp
, tcg_env
, tmp
);
1661 save_frw_i32(rt
, tmp
);
1662 return nullify_end(ctx
);
1665 static bool do_fop_wed(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1666 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i64
))
1673 dst
= tcg_temp_new_i32();
1675 func(dst
, tcg_env
, src
);
1677 save_frw_i32(rt
, dst
);
1678 return nullify_end(ctx
);
1681 static bool do_fop_ded(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1682 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
))
1687 tmp
= load_frd0(ra
);
1689 func(tmp
, tcg_env
, tmp
);
1692 return nullify_end(ctx
);
1695 static bool do_fop_dew(DisasContext
*ctx
, unsigned rt
, unsigned ra
,
1696 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i32
))
1702 src
= load_frw0_i32(ra
);
1703 dst
= tcg_temp_new_i64();
1705 func(dst
, tcg_env
, src
);
1708 return nullify_end(ctx
);
1711 static bool do_fop_weww(DisasContext
*ctx
, unsigned rt
,
1712 unsigned ra
, unsigned rb
,
1713 void (*func
)(TCGv_i32
, TCGv_env
, TCGv_i32
, TCGv_i32
))
1718 a
= load_frw0_i32(ra
);
1719 b
= load_frw0_i32(rb
);
1721 func(a
, tcg_env
, a
, b
);
1723 save_frw_i32(rt
, a
);
1724 return nullify_end(ctx
);
1727 static bool do_fop_dedd(DisasContext
*ctx
, unsigned rt
,
1728 unsigned ra
, unsigned rb
,
1729 void (*func
)(TCGv_i64
, TCGv_env
, TCGv_i64
, TCGv_i64
))
1737 func(a
, tcg_env
, a
, b
);
1740 return nullify_end(ctx
);
1743 /* Emit an unconditional branch to a direct target, which may or may not
1744 have already had nullification handled. */
1745 static bool do_dbranch(DisasContext
*ctx
, target_ureg dest
,
1746 unsigned link
, bool is_n
)
1748 if (ctx
->null_cond
.c
== TCG_COND_NEVER
&& ctx
->null_lab
== NULL
) {
1750 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1754 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1760 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1763 if (is_n
&& use_nullify_skip(ctx
)) {
1764 nullify_set(ctx
, 0);
1765 gen_goto_tb(ctx
, 0, dest
, dest
+ 4);
1767 nullify_set(ctx
, is_n
);
1768 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, dest
);
1773 nullify_set(ctx
, 0);
1774 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, ctx
->iaoq_n
);
1775 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1780 /* Emit a conditional branch to a direct target. If the branch itself
1781 is nullified, we should have already used nullify_over. */
1782 static bool do_cbranch(DisasContext
*ctx
, target_sreg disp
, bool is_n
,
1785 target_ureg dest
= iaoq_dest(ctx
, disp
);
1786 TCGLabel
*taken
= NULL
;
1787 TCGCond c
= cond
->c
;
1790 assert(ctx
->null_cond
.c
== TCG_COND_NEVER
);
1792 /* Handle TRUE and NEVER as direct branches. */
1793 if (c
== TCG_COND_ALWAYS
) {
1794 return do_dbranch(ctx
, dest
, 0, is_n
&& disp
>= 0);
1796 if (c
== TCG_COND_NEVER
) {
1797 return do_dbranch(ctx
, ctx
->iaoq_n
, 0, is_n
&& disp
< 0);
1800 taken
= gen_new_label();
1801 tcg_gen_brcond_reg(c
, cond
->a0
, cond
->a1
, taken
);
1804 /* Not taken: Condition not satisfied; nullify on backward branches. */
1805 n
= is_n
&& disp
< 0;
1806 if (n
&& use_nullify_skip(ctx
)) {
1807 nullify_set(ctx
, 0);
1808 gen_goto_tb(ctx
, 0, ctx
->iaoq_n
, ctx
->iaoq_n
+ 4);
1810 if (!n
&& ctx
->null_lab
) {
1811 gen_set_label(ctx
->null_lab
);
1812 ctx
->null_lab
= NULL
;
1814 nullify_set(ctx
, n
);
1815 if (ctx
->iaoq_n
== -1) {
1816 /* The temporary iaoq_n_var died at the branch above.
1817 Regenerate it here instead of saving it. */
1818 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
1820 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
1823 gen_set_label(taken
);
1825 /* Taken: Condition satisfied; nullify on forward branches. */
1826 n
= is_n
&& disp
>= 0;
1827 if (n
&& use_nullify_skip(ctx
)) {
1828 nullify_set(ctx
, 0);
1829 gen_goto_tb(ctx
, 1, dest
, dest
+ 4);
1831 nullify_set(ctx
, n
);
1832 gen_goto_tb(ctx
, 1, ctx
->iaoq_b
, dest
);
1835 /* Not taken: the branch itself was nullified. */
1836 if (ctx
->null_lab
) {
1837 gen_set_label(ctx
->null_lab
);
1838 ctx
->null_lab
= NULL
;
1839 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
1841 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1846 /* Emit an unconditional branch to an indirect target. This handles
1847 nullification of the branch itself. */
1848 static bool do_ibranch(DisasContext
*ctx
, TCGv_reg dest
,
1849 unsigned link
, bool is_n
)
1851 TCGv_reg a0
, a1
, next
, tmp
;
1854 assert(ctx
->null_lab
== NULL
);
1856 if (ctx
->null_cond
.c
== TCG_COND_NEVER
) {
1858 copy_iaoq_entry(cpu_gr
[link
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1860 next
= tcg_temp_new();
1861 tcg_gen_mov_reg(next
, dest
);
1863 if (use_nullify_skip(ctx
)) {
1864 tcg_gen_mov_reg(cpu_iaoq_f
, next
);
1865 tcg_gen_addi_reg(cpu_iaoq_b
, next
, 4);
1866 nullify_set(ctx
, 0);
1867 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
1870 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
1873 ctx
->iaoq_n_var
= next
;
1874 } else if (is_n
&& use_nullify_skip(ctx
)) {
1875 /* The (conditional) branch, B, nullifies the next insn, N,
1876 and we're allowed to skip execution N (no single-step or
1877 tracepoint in effect). Since the goto_ptr that we must use
1878 for the indirect branch consumes no special resources, we
1879 can (conditionally) skip B and continue execution. */
1880 /* The use_nullify_skip test implies we have a known control path. */
1881 tcg_debug_assert(ctx
->iaoq_b
!= -1);
1882 tcg_debug_assert(ctx
->iaoq_n
!= -1);
1884 /* We do have to handle the non-local temporary, DEST, before
1885 branching. Since IOAQ_F is not really live at this point, we
1886 can simply store DEST optimistically. Similarly with IAOQ_B. */
1887 tcg_gen_mov_reg(cpu_iaoq_f
, dest
);
1888 tcg_gen_addi_reg(cpu_iaoq_b
, dest
, 4);
1892 tcg_gen_movi_reg(cpu_gr
[link
], ctx
->iaoq_n
);
1894 tcg_gen_lookup_and_goto_ptr();
1895 return nullify_end(ctx
);
1897 c
= ctx
->null_cond
.c
;
1898 a0
= ctx
->null_cond
.a0
;
1899 a1
= ctx
->null_cond
.a1
;
1901 tmp
= tcg_temp_new();
1902 next
= tcg_temp_new();
1904 copy_iaoq_entry(tmp
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
1905 tcg_gen_movcond_reg(c
, next
, a0
, a1
, tmp
, dest
);
1907 ctx
->iaoq_n_var
= next
;
1910 tcg_gen_movcond_reg(c
, cpu_gr
[link
], a0
, a1
, cpu_gr
[link
], tmp
);
1914 /* The branch nullifies the next insn, which means the state of N
1915 after the branch is the inverse of the state of N that applied
1917 tcg_gen_setcond_reg(tcg_invert_cond(c
), cpu_psw_n
, a0
, a1
);
1918 cond_free(&ctx
->null_cond
);
1919 ctx
->null_cond
= cond_make_n();
1920 ctx
->psw_n_nonzero
= true;
1922 cond_free(&ctx
->null_cond
);
1929 * if (IAOQ_Front{30..31} < GR[b]{30..31})
1930 * IAOQ_Next{30..31} ← GR[b]{30..31};
1932 * IAOQ_Next{30..31} ← IAOQ_Front{30..31};
1933 * which keeps the privilege level from being increased.
1935 static TCGv_reg
do_ibranch_priv(DisasContext
*ctx
, TCGv_reg offset
)
1938 switch (ctx
->privilege
) {
1940 /* Privilege 0 is maximum and is allowed to decrease. */
1943 /* Privilege 3 is minimum and is never allowed to increase. */
1944 dest
= tcg_temp_new();
1945 tcg_gen_ori_reg(dest
, offset
, 3);
1948 dest
= tcg_temp_new();
1949 tcg_gen_andi_reg(dest
, offset
, -4);
1950 tcg_gen_ori_reg(dest
, dest
, ctx
->privilege
);
1951 tcg_gen_movcond_reg(TCG_COND_GTU
, dest
, dest
, offset
, dest
, offset
);
1957 #ifdef CONFIG_USER_ONLY
1958 /* On Linux, page zero is normally marked execute only + gateway.
1959 Therefore normal read or write is supposed to fail, but specific
1960 offsets have kernel code mapped to raise permissions to implement
1961 system calls. Handling this via an explicit check here, rather
1962 in than the "be disp(sr2,r0)" instruction that probably sent us
1963 here, is the easiest way to handle the branch delay slot on the
1964 aforementioned BE. */
1965 static void do_page_zero(DisasContext
*ctx
)
1967 /* If by some means we get here with PSW[N]=1, that implies that
1968 the B,GATE instruction would be skipped, and we'd fault on the
1969 next insn within the privileged page. */
1970 switch (ctx
->null_cond
.c
) {
1971 case TCG_COND_NEVER
:
1973 case TCG_COND_ALWAYS
:
1974 tcg_gen_movi_reg(cpu_psw_n
, 0);
1977 /* Since this is always the first (and only) insn within the
1978 TB, we should know the state of PSW[N] from TB->FLAGS. */
1979 g_assert_not_reached();
1982 /* Check that we didn't arrive here via some means that allowed
1983 non-sequential instruction execution. Normally the PSW[B] bit
1984 detects this by disallowing the B,GATE instruction to execute
1985 under such conditions. */
1986 if (ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
1990 switch (ctx
->iaoq_f
& -4) {
1991 case 0x00: /* Null pointer call */
1992 gen_excp_1(EXCP_IMP
);
1993 ctx
->base
.is_jmp
= DISAS_NORETURN
;
1996 case 0xb0: /* LWS */
1997 gen_excp_1(EXCP_SYSCALL_LWS
);
1998 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2001 case 0xe0: /* SET_THREAD_POINTER */
2002 tcg_gen_st_reg(cpu_gr
[26], tcg_env
, offsetof(CPUHPPAState
, cr
[27]));
2003 tcg_gen_ori_reg(cpu_iaoq_f
, cpu_gr
[31], 3);
2004 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
2005 ctx
->base
.is_jmp
= DISAS_IAQ_N_UPDATED
;
2008 case 0x100: /* SYSCALL */
2009 gen_excp_1(EXCP_SYSCALL
);
2010 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2015 gen_excp_1(EXCP_ILL
);
2016 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2022 static bool trans_nop(DisasContext
*ctx
, arg_nop
*a
)
2024 cond_free(&ctx
->null_cond
);
2028 static bool trans_break(DisasContext
*ctx
, arg_break
*a
)
2030 return gen_excp_iir(ctx
, EXCP_BREAK
);
2033 static bool trans_sync(DisasContext
*ctx
, arg_sync
*a
)
2035 /* No point in nullifying the memory barrier. */
2036 tcg_gen_mb(TCG_BAR_SC
| TCG_MO_ALL
);
2038 cond_free(&ctx
->null_cond
);
2042 static bool trans_mfia(DisasContext
*ctx
, arg_mfia
*a
)
2045 TCGv_reg tmp
= dest_gpr(ctx
, rt
);
2046 tcg_gen_movi_reg(tmp
, ctx
->iaoq_f
);
2047 save_gpr(ctx
, rt
, tmp
);
2049 cond_free(&ctx
->null_cond
);
2053 static bool trans_mfsp(DisasContext
*ctx
, arg_mfsp
*a
)
2056 unsigned rs
= a
->sp
;
2057 TCGv_i64 t0
= tcg_temp_new_i64();
2058 TCGv_reg t1
= tcg_temp_new();
2060 load_spr(ctx
, t0
, rs
);
2061 tcg_gen_shri_i64(t0
, t0
, 32);
2062 tcg_gen_trunc_i64_reg(t1
, t0
);
2064 save_gpr(ctx
, rt
, t1
);
2066 cond_free(&ctx
->null_cond
);
2070 static bool trans_mfctl(DisasContext
*ctx
, arg_mfctl
*a
)
2073 unsigned ctl
= a
->r
;
2078 #ifdef TARGET_HPPA64
2080 /* MFSAR without ,W masks low 5 bits. */
2081 tmp
= dest_gpr(ctx
, rt
);
2082 tcg_gen_andi_reg(tmp
, cpu_sar
, 31);
2083 save_gpr(ctx
, rt
, tmp
);
2087 save_gpr(ctx
, rt
, cpu_sar
);
2089 case CR_IT
: /* Interval Timer */
2090 /* FIXME: Respect PSW_S bit. */
2092 tmp
= dest_gpr(ctx
, rt
);
2093 if (translator_io_start(&ctx
->base
)) {
2094 gen_helper_read_interval_timer(tmp
);
2095 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2097 gen_helper_read_interval_timer(tmp
);
2099 save_gpr(ctx
, rt
, tmp
);
2100 return nullify_end(ctx
);
2105 /* All other control registers are privileged. */
2106 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2110 tmp
= tcg_temp_new();
2111 tcg_gen_ld_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2112 save_gpr(ctx
, rt
, tmp
);
2115 cond_free(&ctx
->null_cond
);
2119 static bool trans_mtsp(DisasContext
*ctx
, arg_mtsp
*a
)
2122 unsigned rs
= a
->sp
;
2126 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2130 t64
= tcg_temp_new_i64();
2131 tcg_gen_extu_reg_i64(t64
, load_gpr(ctx
, rr
));
2132 tcg_gen_shli_i64(t64
, t64
, 32);
2135 tcg_gen_st_i64(t64
, tcg_env
, offsetof(CPUHPPAState
, sr
[rs
]));
2136 ctx
->tb_flags
&= ~TB_FLAG_SR_SAME
;
2138 tcg_gen_mov_i64(cpu_sr
[rs
], t64
);
2141 return nullify_end(ctx
);
2144 static bool trans_mtctl(DisasContext
*ctx
, arg_mtctl
*a
)
2146 unsigned ctl
= a
->t
;
2150 if (ctl
== CR_SAR
) {
2151 reg
= load_gpr(ctx
, a
->r
);
2152 tmp
= tcg_temp_new();
2153 tcg_gen_andi_reg(tmp
, reg
, TARGET_REGISTER_BITS
- 1);
2154 save_or_nullify(ctx
, cpu_sar
, tmp
);
2156 cond_free(&ctx
->null_cond
);
2160 /* All other control registers are privileged or read-only. */
2161 CHECK_MOST_PRIVILEGED(EXCP_PRIV_REG
);
2163 #ifndef CONFIG_USER_ONLY
2165 reg
= load_gpr(ctx
, a
->r
);
2169 gen_helper_write_interval_timer(tcg_env
, reg
);
2172 gen_helper_write_eirr(tcg_env
, reg
);
2175 gen_helper_write_eiem(tcg_env
, reg
);
2176 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2181 /* FIXME: Respect PSW_Q bit */
2182 /* The write advances the queue and stores to the back element. */
2183 tmp
= tcg_temp_new();
2184 tcg_gen_ld_reg(tmp
, tcg_env
,
2185 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2186 tcg_gen_st_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2187 tcg_gen_st_reg(reg
, tcg_env
,
2188 offsetof(CPUHPPAState
, cr_back
[ctl
- CR_IIASQ
]));
2195 tcg_gen_st_reg(reg
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2196 #ifndef CONFIG_USER_ONLY
2197 gen_helper_change_prot_id(tcg_env
);
2202 tcg_gen_st_reg(reg
, tcg_env
, offsetof(CPUHPPAState
, cr
[ctl
]));
2205 return nullify_end(ctx
);
2209 static bool trans_mtsarcm(DisasContext
*ctx
, arg_mtsarcm
*a
)
2211 TCGv_reg tmp
= tcg_temp_new();
2213 tcg_gen_not_reg(tmp
, load_gpr(ctx
, a
->r
));
2214 tcg_gen_andi_reg(tmp
, tmp
, TARGET_REGISTER_BITS
- 1);
2215 save_or_nullify(ctx
, cpu_sar
, tmp
);
2217 cond_free(&ctx
->null_cond
);
2221 static bool trans_ldsid(DisasContext
*ctx
, arg_ldsid
*a
)
2223 TCGv_reg dest
= dest_gpr(ctx
, a
->t
);
2225 #ifdef CONFIG_USER_ONLY
2226 /* We don't implement space registers in user mode. */
2227 tcg_gen_movi_reg(dest
, 0);
2229 TCGv_i64 t0
= tcg_temp_new_i64();
2231 tcg_gen_mov_i64(t0
, space_select(ctx
, a
->sp
, load_gpr(ctx
, a
->b
)));
2232 tcg_gen_shri_i64(t0
, t0
, 32);
2233 tcg_gen_trunc_i64_reg(dest
, t0
);
2235 save_gpr(ctx
, a
->t
, dest
);
2237 cond_free(&ctx
->null_cond
);
2241 static bool trans_rsm(DisasContext
*ctx
, arg_rsm
*a
)
2243 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2244 #ifndef CONFIG_USER_ONLY
2249 tmp
= tcg_temp_new();
2250 tcg_gen_ld_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, psw
));
2251 tcg_gen_andi_reg(tmp
, tmp
, ~a
->i
);
2252 gen_helper_swap_system_mask(tmp
, tcg_env
, tmp
);
2253 save_gpr(ctx
, a
->t
, tmp
);
2255 /* Exit the TB to recognize new interrupts, e.g. PSW_M. */
2256 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2257 return nullify_end(ctx
);
2261 static bool trans_ssm(DisasContext
*ctx
, arg_ssm
*a
)
2263 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2264 #ifndef CONFIG_USER_ONLY
2269 tmp
= tcg_temp_new();
2270 tcg_gen_ld_reg(tmp
, tcg_env
, offsetof(CPUHPPAState
, psw
));
2271 tcg_gen_ori_reg(tmp
, tmp
, a
->i
);
2272 gen_helper_swap_system_mask(tmp
, tcg_env
, tmp
);
2273 save_gpr(ctx
, a
->t
, tmp
);
2275 /* Exit the TB to recognize new interrupts, e.g. PSW_I. */
2276 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2277 return nullify_end(ctx
);
2281 static bool trans_mtsm(DisasContext
*ctx
, arg_mtsm
*a
)
2283 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2284 #ifndef CONFIG_USER_ONLY
2288 reg
= load_gpr(ctx
, a
->r
);
2289 tmp
= tcg_temp_new();
2290 gen_helper_swap_system_mask(tmp
, tcg_env
, reg
);
2292 /* Exit the TB to recognize new interrupts. */
2293 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE_EXIT
;
2294 return nullify_end(ctx
);
2298 static bool do_rfi(DisasContext
*ctx
, bool rfi_r
)
2300 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2301 #ifndef CONFIG_USER_ONLY
2305 gen_helper_rfi_r(tcg_env
);
2307 gen_helper_rfi(tcg_env
);
2309 /* Exit the TB to recognize new interrupts. */
2310 tcg_gen_exit_tb(NULL
, 0);
2311 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2313 return nullify_end(ctx
);
2317 static bool trans_rfi(DisasContext
*ctx
, arg_rfi
*a
)
2319 return do_rfi(ctx
, false);
2322 static bool trans_rfi_r(DisasContext
*ctx
, arg_rfi_r
*a
)
2324 return do_rfi(ctx
, true);
2327 static bool trans_halt(DisasContext
*ctx
, arg_halt
*a
)
2329 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2330 #ifndef CONFIG_USER_ONLY
2332 gen_helper_halt(tcg_env
);
2333 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2334 return nullify_end(ctx
);
2338 static bool trans_reset(DisasContext
*ctx
, arg_reset
*a
)
2340 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2341 #ifndef CONFIG_USER_ONLY
2343 gen_helper_reset(tcg_env
);
2344 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2345 return nullify_end(ctx
);
2349 static bool trans_getshadowregs(DisasContext
*ctx
, arg_getshadowregs
*a
)
2351 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2352 #ifndef CONFIG_USER_ONLY
2354 gen_helper_getshadowregs(tcg_env
);
2355 return nullify_end(ctx
);
2359 static bool trans_nop_addrx(DisasContext
*ctx
, arg_ldst
*a
)
2362 TCGv_reg dest
= dest_gpr(ctx
, a
->b
);
2363 TCGv_reg src1
= load_gpr(ctx
, a
->b
);
2364 TCGv_reg src2
= load_gpr(ctx
, a
->x
);
2366 /* The only thing we need to do is the base register modification. */
2367 tcg_gen_add_reg(dest
, src1
, src2
);
2368 save_gpr(ctx
, a
->b
, dest
);
2370 cond_free(&ctx
->null_cond
);
2374 static bool trans_probe(DisasContext
*ctx
, arg_probe
*a
)
2377 TCGv_i32 level
, want
;
2382 dest
= dest_gpr(ctx
, a
->t
);
2383 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2386 level
= tcg_constant_i32(a
->ri
);
2388 level
= tcg_temp_new_i32();
2389 tcg_gen_trunc_reg_i32(level
, load_gpr(ctx
, a
->ri
));
2390 tcg_gen_andi_i32(level
, level
, 3);
2392 want
= tcg_constant_i32(a
->write
? PAGE_WRITE
: PAGE_READ
);
2394 gen_helper_probe(dest
, tcg_env
, addr
, level
, want
);
2396 save_gpr(ctx
, a
->t
, dest
);
2397 return nullify_end(ctx
);
2400 static bool trans_ixtlbx(DisasContext
*ctx
, arg_ixtlbx
*a
)
2402 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2403 #ifndef CONFIG_USER_ONLY
2409 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, 0, a
->sp
, 0, false);
2410 reg
= load_gpr(ctx
, a
->r
);
2412 gen_helper_itlba(tcg_env
, addr
, reg
);
2414 gen_helper_itlbp(tcg_env
, addr
, reg
);
2417 /* Exit TB for TLB change if mmu is enabled. */
2418 if (ctx
->tb_flags
& PSW_C
) {
2419 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2421 return nullify_end(ctx
);
2425 static bool trans_pxtlbx(DisasContext
*ctx
, arg_pxtlbx
*a
)
2427 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2428 #ifndef CONFIG_USER_ONLY
2434 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2436 save_gpr(ctx
, a
->b
, ofs
);
2439 gen_helper_ptlbe(tcg_env
);
2441 gen_helper_ptlb(tcg_env
, addr
);
2444 /* Exit TB for TLB change if mmu is enabled. */
2445 if (ctx
->tb_flags
& PSW_C
) {
2446 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2448 return nullify_end(ctx
);
2453 * Implement the pcxl and pcxl2 Fast TLB Insert instructions.
2455 * https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
2456 * page 13-9 (195/206)
2458 static bool trans_ixtlbxf(DisasContext
*ctx
, arg_ixtlbxf
*a
)
2460 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2461 #ifndef CONFIG_USER_ONLY
2462 TCGv_tl addr
, atl
, stl
;
2469 * if (not (pcxl or pcxl2))
2470 * return gen_illegal(ctx);
2472 * Note for future: these are 32-bit systems; no hppa64.
2475 atl
= tcg_temp_new_tl();
2476 stl
= tcg_temp_new_tl();
2477 addr
= tcg_temp_new_tl();
2479 tcg_gen_ld32u_i64(stl
, tcg_env
,
2480 a
->data
? offsetof(CPUHPPAState
, cr
[CR_ISR
])
2481 : offsetof(CPUHPPAState
, cr
[CR_IIASQ
]));
2482 tcg_gen_ld32u_i64(atl
, tcg_env
,
2483 a
->data
? offsetof(CPUHPPAState
, cr
[CR_IOR
])
2484 : offsetof(CPUHPPAState
, cr
[CR_IIAOQ
]));
2485 tcg_gen_shli_i64(stl
, stl
, 32);
2486 tcg_gen_or_tl(addr
, atl
, stl
);
2488 reg
= load_gpr(ctx
, a
->r
);
2490 gen_helper_itlba(tcg_env
, addr
, reg
);
2492 gen_helper_itlbp(tcg_env
, addr
, reg
);
2495 /* Exit TB for TLB change if mmu is enabled. */
2496 if (ctx
->tb_flags
& PSW_C
) {
2497 ctx
->base
.is_jmp
= DISAS_IAQ_N_STALE
;
2499 return nullify_end(ctx
);
2503 static bool trans_lpa(DisasContext
*ctx
, arg_ldst
*a
)
2505 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2506 #ifndef CONFIG_USER_ONLY
2508 TCGv_reg ofs
, paddr
;
2512 form_gva(ctx
, &vaddr
, &ofs
, a
->b
, a
->x
, 0, 0, a
->sp
, a
->m
, false);
2514 paddr
= tcg_temp_new();
2515 gen_helper_lpa(paddr
, tcg_env
, vaddr
);
2517 /* Note that physical address result overrides base modification. */
2519 save_gpr(ctx
, a
->b
, ofs
);
2521 save_gpr(ctx
, a
->t
, paddr
);
2523 return nullify_end(ctx
);
2527 static bool trans_lci(DisasContext
*ctx
, arg_lci
*a
)
2529 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2531 /* The Coherence Index is an implementation-defined function of the
2532 physical address. Two addresses with the same CI have a coherent
2533 view of the cache. Our implementation is to return 0 for all,
2534 since the entire address space is coherent. */
2535 save_gpr(ctx
, a
->t
, tcg_constant_reg(0));
2537 cond_free(&ctx
->null_cond
);
2541 static bool trans_add(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2543 return do_add_reg(ctx
, a
, false, false, false, false);
2546 static bool trans_add_l(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2548 return do_add_reg(ctx
, a
, true, false, false, false);
2551 static bool trans_add_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2553 return do_add_reg(ctx
, a
, false, true, false, false);
2556 static bool trans_add_c(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2558 return do_add_reg(ctx
, a
, false, false, false, true);
2561 static bool trans_add_c_tsv(DisasContext
*ctx
, arg_rrr_cf_sh
*a
)
2563 return do_add_reg(ctx
, a
, false, true, false, true);
2566 static bool trans_sub(DisasContext
*ctx
, arg_rrr_cf
*a
)
2568 return do_sub_reg(ctx
, a
, false, false, false);
2571 static bool trans_sub_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2573 return do_sub_reg(ctx
, a
, true, false, false);
2576 static bool trans_sub_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2578 return do_sub_reg(ctx
, a
, false, false, true);
2581 static bool trans_sub_tsv_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2583 return do_sub_reg(ctx
, a
, true, false, true);
2586 static bool trans_sub_b(DisasContext
*ctx
, arg_rrr_cf
*a
)
2588 return do_sub_reg(ctx
, a
, false, true, false);
2591 static bool trans_sub_b_tsv(DisasContext
*ctx
, arg_rrr_cf
*a
)
2593 return do_sub_reg(ctx
, a
, true, true, false);
2596 static bool trans_andcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2598 return do_log_reg(ctx
, a
, tcg_gen_andc_reg
);
2601 static bool trans_and(DisasContext
*ctx
, arg_rrr_cf
*a
)
2603 return do_log_reg(ctx
, a
, tcg_gen_and_reg
);
2606 static bool trans_or(DisasContext
*ctx
, arg_rrr_cf
*a
)
2609 unsigned r2
= a
->r2
;
2610 unsigned r1
= a
->r1
;
2613 if (rt
== 0) { /* NOP */
2614 cond_free(&ctx
->null_cond
);
2617 if (r2
== 0) { /* COPY */
2619 TCGv_reg dest
= dest_gpr(ctx
, rt
);
2620 tcg_gen_movi_reg(dest
, 0);
2621 save_gpr(ctx
, rt
, dest
);
2623 save_gpr(ctx
, rt
, cpu_gr
[r1
]);
2625 cond_free(&ctx
->null_cond
);
2628 #ifndef CONFIG_USER_ONLY
2629 /* These are QEMU extensions and are nops in the real architecture:
2631 * or %r10,%r10,%r10 -- idle loop; wait for interrupt
2632 * or %r31,%r31,%r31 -- death loop; offline cpu
2633 * currently implemented as idle.
2635 if ((rt
== 10 || rt
== 31) && r1
== rt
&& r2
== rt
) { /* PAUSE */
2636 /* No need to check for supervisor, as userland can only pause
2637 until the next timer interrupt. */
2640 /* Advance the instruction queue. */
2641 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
2642 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
2643 nullify_set(ctx
, 0);
2645 /* Tell the qemu main loop to halt until this cpu has work. */
2646 tcg_gen_st_i32(tcg_constant_i32(1), tcg_env
,
2647 offsetof(CPUState
, halted
) - offsetof(HPPACPU
, env
));
2648 gen_excp_1(EXCP_HALTED
);
2649 ctx
->base
.is_jmp
= DISAS_NORETURN
;
2651 return nullify_end(ctx
);
2655 return do_log_reg(ctx
, a
, tcg_gen_or_reg
);
2658 static bool trans_xor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2660 return do_log_reg(ctx
, a
, tcg_gen_xor_reg
);
2663 static bool trans_cmpclr(DisasContext
*ctx
, arg_rrr_cf
*a
)
2665 TCGv_reg tcg_r1
, tcg_r2
;
2670 tcg_r1
= load_gpr(ctx
, a
->r1
);
2671 tcg_r2
= load_gpr(ctx
, a
->r2
);
2672 do_cmpclr(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
);
2673 return nullify_end(ctx
);
2676 static bool trans_uxor(DisasContext
*ctx
, arg_rrr_cf
*a
)
2678 TCGv_reg tcg_r1
, tcg_r2
;
2683 tcg_r1
= load_gpr(ctx
, a
->r1
);
2684 tcg_r2
= load_gpr(ctx
, a
->r2
);
2685 do_unit(ctx
, a
->t
, tcg_r1
, tcg_r2
, a
->cf
, false, tcg_gen_xor_reg
);
2686 return nullify_end(ctx
);
2689 static bool do_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
, bool is_tc
)
2691 TCGv_reg tcg_r1
, tcg_r2
, tmp
;
2696 tcg_r1
= load_gpr(ctx
, a
->r1
);
2697 tcg_r2
= load_gpr(ctx
, a
->r2
);
2698 tmp
= tcg_temp_new();
2699 tcg_gen_not_reg(tmp
, tcg_r2
);
2700 do_unit(ctx
, a
->t
, tcg_r1
, tmp
, a
->cf
, is_tc
, tcg_gen_add_reg
);
2701 return nullify_end(ctx
);
2704 static bool trans_uaddcm(DisasContext
*ctx
, arg_rrr_cf
*a
)
2706 return do_uaddcm(ctx
, a
, false);
2709 static bool trans_uaddcm_tc(DisasContext
*ctx
, arg_rrr_cf
*a
)
2711 return do_uaddcm(ctx
, a
, true);
2714 static bool do_dcor(DisasContext
*ctx
, arg_rr_cf
*a
, bool is_i
)
2720 tmp
= tcg_temp_new();
2721 tcg_gen_shri_reg(tmp
, cpu_psw_cb
, 3);
2723 tcg_gen_not_reg(tmp
, tmp
);
2725 tcg_gen_andi_reg(tmp
, tmp
, 0x11111111);
2726 tcg_gen_muli_reg(tmp
, tmp
, 6);
2727 do_unit(ctx
, a
->t
, load_gpr(ctx
, a
->r
), tmp
, a
->cf
, false,
2728 is_i
? tcg_gen_add_reg
: tcg_gen_sub_reg
);
2729 return nullify_end(ctx
);
2732 static bool trans_dcor(DisasContext
*ctx
, arg_rr_cf
*a
)
2734 return do_dcor(ctx
, a
, false);
2737 static bool trans_dcor_i(DisasContext
*ctx
, arg_rr_cf
*a
)
2739 return do_dcor(ctx
, a
, true);
2742 static bool trans_ds(DisasContext
*ctx
, arg_rrr_cf
*a
)
2744 TCGv_reg dest
, add1
, add2
, addc
, zero
, in1
, in2
;
2749 in1
= load_gpr(ctx
, a
->r1
);
2750 in2
= load_gpr(ctx
, a
->r2
);
2752 add1
= tcg_temp_new();
2753 add2
= tcg_temp_new();
2754 addc
= tcg_temp_new();
2755 dest
= tcg_temp_new();
2756 zero
= tcg_constant_reg(0);
2758 /* Form R1 << 1 | PSW[CB]{8}. */
2759 tcg_gen_add_reg(add1
, in1
, in1
);
2760 tcg_gen_add_reg(add1
, add1
, get_psw_carry(ctx
, false));
2763 * Add or subtract R2, depending on PSW[V]. Proper computation of
2764 * carry requires that we subtract via + ~R2 + 1, as described in
2765 * the manual. By extracting and masking V, we can produce the
2766 * proper inputs to the addition without movcond.
2768 tcg_gen_sextract_reg(addc
, cpu_psw_v
, 31, 1);
2769 tcg_gen_xor_reg(add2
, in2
, addc
);
2770 tcg_gen_andi_reg(addc
, addc
, 1);
2772 tcg_gen_add2_reg(dest
, cpu_psw_cb_msb
, add1
, zero
, add2
, zero
);
2773 tcg_gen_add2_reg(dest
, cpu_psw_cb_msb
, dest
, cpu_psw_cb_msb
, addc
, zero
);
2775 /* Write back the result register. */
2776 save_gpr(ctx
, a
->t
, dest
);
2778 /* Write back PSW[CB]. */
2779 tcg_gen_xor_reg(cpu_psw_cb
, add1
, add2
);
2780 tcg_gen_xor_reg(cpu_psw_cb
, cpu_psw_cb
, dest
);
2782 /* Write back PSW[V] for the division step. */
2783 cout
= get_psw_carry(ctx
, false);
2784 tcg_gen_neg_reg(cpu_psw_v
, cout
);
2785 tcg_gen_xor_reg(cpu_psw_v
, cpu_psw_v
, in2
);
2787 /* Install the new nullification. */
2790 if (cond_need_sv(a
->cf
>> 1)) {
2791 /* ??? The lshift is supposed to contribute to overflow. */
2792 sv
= do_add_sv(ctx
, dest
, add1
, add2
);
2794 ctx
->null_cond
= do_cond(a
->cf
, dest
, cout
, sv
);
2797 return nullify_end(ctx
);
2800 static bool trans_addi(DisasContext
*ctx
, arg_rri_cf
*a
)
2802 return do_add_imm(ctx
, a
, false, false);
2805 static bool trans_addi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2807 return do_add_imm(ctx
, a
, true, false);
2810 static bool trans_addi_tc(DisasContext
*ctx
, arg_rri_cf
*a
)
2812 return do_add_imm(ctx
, a
, false, true);
2815 static bool trans_addi_tc_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2817 return do_add_imm(ctx
, a
, true, true);
2820 static bool trans_subi(DisasContext
*ctx
, arg_rri_cf
*a
)
2822 return do_sub_imm(ctx
, a
, false);
2825 static bool trans_subi_tsv(DisasContext
*ctx
, arg_rri_cf
*a
)
2827 return do_sub_imm(ctx
, a
, true);
2830 static bool trans_cmpiclr(DisasContext
*ctx
, arg_rri_cf
*a
)
2832 TCGv_reg tcg_im
, tcg_r2
;
2838 tcg_im
= tcg_constant_reg(a
->i
);
2839 tcg_r2
= load_gpr(ctx
, a
->r
);
2840 do_cmpclr(ctx
, a
->t
, tcg_im
, tcg_r2
, a
->cf
);
2842 return nullify_end(ctx
);
2845 static bool trans_ld(DisasContext
*ctx
, arg_ldst
*a
)
2847 if (unlikely(TARGET_REGISTER_BITS
== 32 && a
->size
> MO_32
)) {
2848 return gen_illegal(ctx
);
2850 return do_load(ctx
, a
->t
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2851 a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2855 static bool trans_st(DisasContext
*ctx
, arg_ldst
*a
)
2857 assert(a
->x
== 0 && a
->scale
== 0);
2858 if (unlikely(TARGET_REGISTER_BITS
== 32 && a
->size
> MO_32
)) {
2859 return gen_illegal(ctx
);
2861 return do_store(ctx
, a
->t
, a
->b
, a
->disp
, a
->sp
, a
->m
, a
->size
| MO_TE
);
2865 static bool trans_ldc(DisasContext
*ctx
, arg_ldst
*a
)
2867 MemOp mop
= MO_TE
| MO_ALIGN
| a
->size
;
2868 TCGv_reg zero
, dest
, ofs
;
2874 /* Base register modification. Make sure if RT == RB,
2875 we see the result of the load. */
2876 dest
= tcg_temp_new();
2878 dest
= dest_gpr(ctx
, a
->t
);
2881 form_gva(ctx
, &addr
, &ofs
, a
->b
, a
->x
, a
->scale
? a
->size
: 0,
2882 a
->disp
, a
->sp
, a
->m
, ctx
->mmu_idx
== MMU_PHYS_IDX
);
2885 * For hppa1.1, LDCW is undefined unless aligned mod 16.
2886 * However actual hardware succeeds with aligned mod 4.
2887 * Detect this case and log a GUEST_ERROR.
2889 * TODO: HPPA64 relaxes the over-alignment requirement
2890 * with the ,co completer.
2892 gen_helper_ldc_check(addr
);
2894 zero
= tcg_constant_reg(0);
2895 tcg_gen_atomic_xchg_reg(dest
, addr
, zero
, ctx
->mmu_idx
, mop
);
2898 save_gpr(ctx
, a
->b
, ofs
);
2900 save_gpr(ctx
, a
->t
, dest
);
2902 return nullify_end(ctx
);
2905 static bool trans_stby(DisasContext
*ctx
, arg_stby
*a
)
2912 form_gva(ctx
, &addr
, &ofs
, a
->b
, 0, 0, a
->disp
, a
->sp
, a
->m
,
2913 ctx
->mmu_idx
== MMU_PHYS_IDX
);
2914 val
= load_gpr(ctx
, a
->r
);
2916 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2917 gen_helper_stby_e_parallel(tcg_env
, addr
, val
);
2919 gen_helper_stby_e(tcg_env
, addr
, val
);
2922 if (tb_cflags(ctx
->base
.tb
) & CF_PARALLEL
) {
2923 gen_helper_stby_b_parallel(tcg_env
, addr
, val
);
2925 gen_helper_stby_b(tcg_env
, addr
, val
);
2929 tcg_gen_andi_reg(ofs
, ofs
, ~3);
2930 save_gpr(ctx
, a
->b
, ofs
);
2933 return nullify_end(ctx
);
2936 static bool trans_lda(DisasContext
*ctx
, arg_ldst
*a
)
2938 int hold_mmu_idx
= ctx
->mmu_idx
;
2940 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2941 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2943 ctx
->mmu_idx
= hold_mmu_idx
;
2947 static bool trans_sta(DisasContext
*ctx
, arg_ldst
*a
)
2949 int hold_mmu_idx
= ctx
->mmu_idx
;
2951 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
2952 ctx
->mmu_idx
= MMU_PHYS_IDX
;
2954 ctx
->mmu_idx
= hold_mmu_idx
;
2958 static bool trans_ldil(DisasContext
*ctx
, arg_ldil
*a
)
2960 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
2962 tcg_gen_movi_reg(tcg_rt
, a
->i
);
2963 save_gpr(ctx
, a
->t
, tcg_rt
);
2964 cond_free(&ctx
->null_cond
);
2968 static bool trans_addil(DisasContext
*ctx
, arg_addil
*a
)
2970 TCGv_reg tcg_rt
= load_gpr(ctx
, a
->r
);
2971 TCGv_reg tcg_r1
= dest_gpr(ctx
, 1);
2973 tcg_gen_addi_reg(tcg_r1
, tcg_rt
, a
->i
);
2974 save_gpr(ctx
, 1, tcg_r1
);
2975 cond_free(&ctx
->null_cond
);
2979 static bool trans_ldo(DisasContext
*ctx
, arg_ldo
*a
)
2981 TCGv_reg tcg_rt
= dest_gpr(ctx
, a
->t
);
2983 /* Special case rb == 0, for the LDI pseudo-op.
2984 The COPY pseudo-op is handled for free within tcg_gen_addi_tl. */
2986 tcg_gen_movi_reg(tcg_rt
, a
->i
);
2988 tcg_gen_addi_reg(tcg_rt
, cpu_gr
[a
->b
], a
->i
);
2990 save_gpr(ctx
, a
->t
, tcg_rt
);
2991 cond_free(&ctx
->null_cond
);
2995 static bool do_cmpb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
2996 unsigned c
, unsigned f
, unsigned n
, int disp
)
2998 TCGv_reg dest
, in2
, sv
;
3001 in2
= load_gpr(ctx
, r
);
3002 dest
= tcg_temp_new();
3004 tcg_gen_sub_reg(dest
, in1
, in2
);
3007 if (cond_need_sv(c
)) {
3008 sv
= do_sub_sv(ctx
, dest
, in1
, in2
);
3011 cond
= do_sub_cond(c
* 2 + f
, dest
, in1
, in2
, sv
);
3012 return do_cbranch(ctx
, disp
, n
, &cond
);
3015 static bool trans_cmpb(DisasContext
*ctx
, arg_cmpb
*a
)
3018 return do_cmpb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3021 static bool trans_cmpbi(DisasContext
*ctx
, arg_cmpbi
*a
)
3024 return do_cmpb(ctx
, a
->r
, tcg_constant_reg(a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3027 static bool do_addb(DisasContext
*ctx
, unsigned r
, TCGv_reg in1
,
3028 unsigned c
, unsigned f
, unsigned n
, int disp
)
3030 TCGv_reg dest
, in2
, sv
, cb_cond
;
3034 in2
= load_gpr(ctx
, r
);
3035 dest
= tcg_temp_new();
3039 if (cond_need_cb(c
)) {
3040 TCGv_reg cb
= tcg_temp_new();
3041 TCGv_reg cb_msb
= tcg_temp_new();
3043 tcg_gen_movi_reg(cb_msb
, 0);
3044 tcg_gen_add2_reg(dest
, cb_msb
, in1
, cb_msb
, in2
, cb_msb
);
3045 tcg_gen_xor_reg(cb
, in1
, in2
);
3046 tcg_gen_xor_reg(cb
, cb
, dest
);
3047 cb_cond
= get_carry(ctx
, d
, cb
, cb_msb
);
3049 tcg_gen_add_reg(dest
, in1
, in2
);
3051 if (cond_need_sv(c
)) {
3052 sv
= do_add_sv(ctx
, dest
, in1
, in2
);
3055 cond
= do_cond(c
* 2 + f
, dest
, cb_cond
, sv
);
3056 save_gpr(ctx
, r
, dest
);
3057 return do_cbranch(ctx
, disp
, n
, &cond
);
3060 static bool trans_addb(DisasContext
*ctx
, arg_addb
*a
)
3063 return do_addb(ctx
, a
->r2
, load_gpr(ctx
, a
->r1
), a
->c
, a
->f
, a
->n
, a
->disp
);
3066 static bool trans_addbi(DisasContext
*ctx
, arg_addbi
*a
)
3069 return do_addb(ctx
, a
->r
, tcg_constant_reg(a
->i
), a
->c
, a
->f
, a
->n
, a
->disp
);
3072 static bool trans_bb_sar(DisasContext
*ctx
, arg_bb_sar
*a
)
3074 TCGv_reg tmp
, tcg_r
;
3079 tmp
= tcg_temp_new();
3080 tcg_r
= load_gpr(ctx
, a
->r
);
3081 tcg_gen_shl_reg(tmp
, tcg_r
, cpu_sar
);
3083 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3084 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3087 static bool trans_bb_imm(DisasContext
*ctx
, arg_bb_imm
*a
)
3089 TCGv_reg tmp
, tcg_r
;
3094 tmp
= tcg_temp_new();
3095 tcg_r
= load_gpr(ctx
, a
->r
);
3096 tcg_gen_shli_reg(tmp
, tcg_r
, a
->p
);
3098 cond
= cond_make_0(a
->c
? TCG_COND_GE
: TCG_COND_LT
, tmp
);
3099 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3102 static bool trans_movb(DisasContext
*ctx
, arg_movb
*a
)
3109 dest
= dest_gpr(ctx
, a
->r2
);
3111 tcg_gen_movi_reg(dest
, 0);
3113 tcg_gen_mov_reg(dest
, cpu_gr
[a
->r1
]);
3116 cond
= do_sed_cond(a
->c
, dest
);
3117 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3120 static bool trans_movbi(DisasContext
*ctx
, arg_movbi
*a
)
3127 dest
= dest_gpr(ctx
, a
->r
);
3128 tcg_gen_movi_reg(dest
, a
->i
);
3130 cond
= do_sed_cond(a
->c
, dest
);
3131 return do_cbranch(ctx
, a
->disp
, a
->n
, &cond
);
3134 static bool trans_shrpw_sar(DisasContext
*ctx
, arg_shrpw_sar
*a
)
3142 dest
= dest_gpr(ctx
, a
->t
);
3144 tcg_gen_ext32u_reg(dest
, load_gpr(ctx
, a
->r2
));
3145 tcg_gen_shr_reg(dest
, dest
, cpu_sar
);
3146 } else if (a
->r1
== a
->r2
) {
3147 TCGv_i32 t32
= tcg_temp_new_i32();
3148 TCGv_i32 s32
= tcg_temp_new_i32();
3150 tcg_gen_trunc_reg_i32(t32
, load_gpr(ctx
, a
->r2
));
3151 tcg_gen_trunc_reg_i32(s32
, cpu_sar
);
3152 tcg_gen_rotr_i32(t32
, t32
, s32
);
3153 tcg_gen_extu_i32_reg(dest
, t32
);
3155 TCGv_i64 t
= tcg_temp_new_i64();
3156 TCGv_i64 s
= tcg_temp_new_i64();
3158 tcg_gen_concat_reg_i64(t
, load_gpr(ctx
, a
->r2
), load_gpr(ctx
, a
->r1
));
3159 tcg_gen_extu_reg_i64(s
, cpu_sar
);
3160 tcg_gen_shr_i64(t
, t
, s
);
3161 tcg_gen_trunc_i64_reg(dest
, t
);
3163 save_gpr(ctx
, a
->t
, dest
);
3165 /* Install the new nullification. */
3166 cond_free(&ctx
->null_cond
);
3168 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3170 return nullify_end(ctx
);
3173 static bool trans_shrpw_imm(DisasContext
*ctx
, arg_shrpw_imm
*a
)
3175 unsigned sa
= 31 - a
->cpos
;
3182 dest
= dest_gpr(ctx
, a
->t
);
3183 t2
= load_gpr(ctx
, a
->r2
);
3185 tcg_gen_extract_reg(dest
, t2
, sa
, 32 - sa
);
3186 } else if (TARGET_REGISTER_BITS
== 32) {
3187 tcg_gen_extract2_reg(dest
, t2
, cpu_gr
[a
->r1
], sa
);
3188 } else if (a
->r1
== a
->r2
) {
3189 TCGv_i32 t32
= tcg_temp_new_i32();
3190 tcg_gen_trunc_reg_i32(t32
, t2
);
3191 tcg_gen_rotri_i32(t32
, t32
, sa
);
3192 tcg_gen_extu_i32_reg(dest
, t32
);
3194 TCGv_i64 t64
= tcg_temp_new_i64();
3195 tcg_gen_concat_reg_i64(t64
, t2
, cpu_gr
[a
->r1
]);
3196 tcg_gen_shri_i64(t64
, t64
, sa
);
3197 tcg_gen_trunc_i64_reg(dest
, t64
);
3199 save_gpr(ctx
, a
->t
, dest
);
3201 /* Install the new nullification. */
3202 cond_free(&ctx
->null_cond
);
3204 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3206 return nullify_end(ctx
);
3209 static bool trans_extrw_sar(DisasContext
*ctx
, arg_extrw_sar
*a
)
3211 unsigned len
= 32 - a
->clen
;
3212 TCGv_reg dest
, src
, tmp
;
3218 dest
= dest_gpr(ctx
, a
->t
);
3219 src
= load_gpr(ctx
, a
->r
);
3220 tmp
= tcg_temp_new();
3222 /* Recall that SAR is using big-endian bit numbering. */
3223 tcg_gen_xori_reg(tmp
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3225 tcg_gen_sar_reg(dest
, src
, tmp
);
3226 tcg_gen_sextract_reg(dest
, dest
, 0, len
);
3228 tcg_gen_shr_reg(dest
, src
, tmp
);
3229 tcg_gen_extract_reg(dest
, dest
, 0, len
);
3231 save_gpr(ctx
, a
->t
, dest
);
3233 /* Install the new nullification. */
3234 cond_free(&ctx
->null_cond
);
3236 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3238 return nullify_end(ctx
);
3241 static bool trans_extrw_imm(DisasContext
*ctx
, arg_extrw_imm
*a
)
3243 unsigned len
= 32 - a
->clen
;
3244 unsigned cpos
= 31 - a
->pos
;
3251 dest
= dest_gpr(ctx
, a
->t
);
3252 src
= load_gpr(ctx
, a
->r
);
3254 tcg_gen_sextract_reg(dest
, src
, cpos
, len
);
3256 tcg_gen_extract_reg(dest
, src
, cpos
, len
);
3258 save_gpr(ctx
, a
->t
, dest
);
3260 /* Install the new nullification. */
3261 cond_free(&ctx
->null_cond
);
3263 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3265 return nullify_end(ctx
);
3268 static bool trans_depwi_imm(DisasContext
*ctx
, arg_depwi_imm
*a
)
3270 unsigned len
= 32 - a
->clen
;
3271 target_sreg mask0
, mask1
;
3277 if (a
->cpos
+ len
> 32) {
3281 dest
= dest_gpr(ctx
, a
->t
);
3282 mask0
= deposit64(0, a
->cpos
, len
, a
->i
);
3283 mask1
= deposit64(-1, a
->cpos
, len
, a
->i
);
3286 TCGv_reg src
= load_gpr(ctx
, a
->t
);
3288 tcg_gen_andi_reg(dest
, src
, mask1
);
3291 tcg_gen_ori_reg(dest
, src
, mask0
);
3293 tcg_gen_movi_reg(dest
, mask0
);
3295 save_gpr(ctx
, a
->t
, dest
);
3297 /* Install the new nullification. */
3298 cond_free(&ctx
->null_cond
);
3300 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3302 return nullify_end(ctx
);
3305 static bool trans_depw_imm(DisasContext
*ctx
, arg_depw_imm
*a
)
3307 unsigned rs
= a
->nz
? a
->t
: 0;
3308 unsigned len
= 32 - a
->clen
;
3314 if (a
->cpos
+ len
> 32) {
3318 dest
= dest_gpr(ctx
, a
->t
);
3319 val
= load_gpr(ctx
, a
->r
);
3321 tcg_gen_deposit_z_reg(dest
, val
, a
->cpos
, len
);
3323 tcg_gen_deposit_reg(dest
, cpu_gr
[rs
], val
, a
->cpos
, len
);
3325 save_gpr(ctx
, a
->t
, dest
);
3327 /* Install the new nullification. */
3328 cond_free(&ctx
->null_cond
);
3330 ctx
->null_cond
= do_sed_cond(a
->c
, dest
);
3332 return nullify_end(ctx
);
3335 static bool do_depw_sar(DisasContext
*ctx
, unsigned rt
, unsigned c
,
3336 unsigned nz
, unsigned clen
, TCGv_reg val
)
3338 unsigned rs
= nz
? rt
: 0;
3339 unsigned len
= 32 - clen
;
3340 TCGv_reg mask
, tmp
, shift
, dest
;
3341 unsigned msb
= 1U << (len
- 1);
3343 dest
= dest_gpr(ctx
, rt
);
3344 shift
= tcg_temp_new();
3345 tmp
= tcg_temp_new();
3347 /* Convert big-endian bit numbering in SAR to left-shift. */
3348 tcg_gen_xori_reg(shift
, cpu_sar
, TARGET_REGISTER_BITS
- 1);
3350 mask
= tcg_temp_new();
3351 tcg_gen_movi_reg(mask
, msb
+ (msb
- 1));
3352 tcg_gen_and_reg(tmp
, val
, mask
);
3354 tcg_gen_shl_reg(mask
, mask
, shift
);
3355 tcg_gen_shl_reg(tmp
, tmp
, shift
);
3356 tcg_gen_andc_reg(dest
, cpu_gr
[rs
], mask
);
3357 tcg_gen_or_reg(dest
, dest
, tmp
);
3359 tcg_gen_shl_reg(dest
, tmp
, shift
);
3361 save_gpr(ctx
, rt
, dest
);
3363 /* Install the new nullification. */
3364 cond_free(&ctx
->null_cond
);
3366 ctx
->null_cond
= do_sed_cond(c
, dest
);
3368 return nullify_end(ctx
);
3371 static bool trans_depw_sar(DisasContext
*ctx
, arg_depw_sar
*a
)
3376 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, load_gpr(ctx
, a
->r
));
3379 static bool trans_depwi_sar(DisasContext
*ctx
, arg_depwi_sar
*a
)
3384 return do_depw_sar(ctx
, a
->t
, a
->c
, a
->nz
, a
->clen
, tcg_constant_reg(a
->i
));
3387 static bool trans_be(DisasContext
*ctx
, arg_be
*a
)
3391 #ifdef CONFIG_USER_ONLY
3392 /* ??? It seems like there should be a good way of using
3393 "be disp(sr2, r0)", the canonical gateway entry mechanism
3394 to our advantage. But that appears to be inconvenient to
3395 manage along side branch delay slots. Therefore we handle
3396 entry into the gateway page via absolute address. */
3397 /* Since we don't implement spaces, just branch. Do notice the special
3398 case of "be disp(*,r0)" using a direct branch to disp, so that we can
3399 goto_tb to the TB containing the syscall. */
3401 return do_dbranch(ctx
, a
->disp
, a
->l
, a
->n
);
3407 tmp
= tcg_temp_new();
3408 tcg_gen_addi_reg(tmp
, load_gpr(ctx
, a
->b
), a
->disp
);
3409 tmp
= do_ibranch_priv(ctx
, tmp
);
3411 #ifdef CONFIG_USER_ONLY
3412 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3414 TCGv_i64 new_spc
= tcg_temp_new_i64();
3416 load_spr(ctx
, new_spc
, a
->sp
);
3418 copy_iaoq_entry(cpu_gr
[31], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3419 tcg_gen_mov_i64(cpu_sr
[0], cpu_iasq_f
);
3421 if (a
->n
&& use_nullify_skip(ctx
)) {
3422 tcg_gen_mov_reg(cpu_iaoq_f
, tmp
);
3423 tcg_gen_addi_reg(cpu_iaoq_b
, cpu_iaoq_f
, 4);
3424 tcg_gen_mov_i64(cpu_iasq_f
, new_spc
);
3425 tcg_gen_mov_i64(cpu_iasq_b
, cpu_iasq_f
);
3427 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3428 if (ctx
->iaoq_b
== -1) {
3429 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3431 tcg_gen_mov_reg(cpu_iaoq_b
, tmp
);
3432 tcg_gen_mov_i64(cpu_iasq_b
, new_spc
);
3433 nullify_set(ctx
, a
->n
);
3435 tcg_gen_lookup_and_goto_ptr();
3436 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3437 return nullify_end(ctx
);
3441 static bool trans_bl(DisasContext
*ctx
, arg_bl
*a
)
3443 return do_dbranch(ctx
, iaoq_dest(ctx
, a
->disp
), a
->l
, a
->n
);
3446 static bool trans_b_gate(DisasContext
*ctx
, arg_b_gate
*a
)
3448 target_ureg dest
= iaoq_dest(ctx
, a
->disp
);
3452 /* Make sure the caller hasn't done something weird with the queue.
3453 * ??? This is not quite the same as the PSW[B] bit, which would be
3454 * expensive to track. Real hardware will trap for
3456 * b gateway+4 (in delay slot of first branch)
3457 * However, checking for a non-sequential instruction queue *will*
3458 * diagnose the security hole
3461 * in which instructions at evil would run with increased privs.
3463 if (ctx
->iaoq_b
== -1 || ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
3464 return gen_illegal(ctx
);
3467 #ifndef CONFIG_USER_ONLY
3468 if (ctx
->tb_flags
& PSW_C
) {
3469 CPUHPPAState
*env
= cpu_env(ctx
->cs
);
3470 int type
= hppa_artype_for_page(env
, ctx
->base
.pc_next
);
3471 /* If we could not find a TLB entry, then we need to generate an
3472 ITLB miss exception so the kernel will provide it.
3473 The resulting TLB fill operation will invalidate this TB and
3474 we will re-translate, at which point we *will* be able to find
3475 the TLB entry and determine if this is in fact a gateway page. */
3477 gen_excp(ctx
, EXCP_ITLB_MISS
);
3480 /* No change for non-gateway pages or for priv decrease. */
3481 if (type
>= 4 && type
- 4 < ctx
->privilege
) {
3482 dest
= deposit32(dest
, 0, 2, type
- 4);
3485 dest
&= -4; /* priv = 0 */
3490 TCGv_reg tmp
= dest_gpr(ctx
, a
->l
);
3491 if (ctx
->privilege
< 3) {
3492 tcg_gen_andi_reg(tmp
, tmp
, -4);
3494 tcg_gen_ori_reg(tmp
, tmp
, ctx
->privilege
);
3495 save_gpr(ctx
, a
->l
, tmp
);
3498 return do_dbranch(ctx
, dest
, 0, a
->n
);
3501 static bool trans_blr(DisasContext
*ctx
, arg_blr
*a
)
3504 TCGv_reg tmp
= tcg_temp_new();
3505 tcg_gen_shli_reg(tmp
, load_gpr(ctx
, a
->x
), 3);
3506 tcg_gen_addi_reg(tmp
, tmp
, ctx
->iaoq_f
+ 8);
3507 /* The computation here never changes privilege level. */
3508 return do_ibranch(ctx
, tmp
, a
->l
, a
->n
);
3510 /* BLR R0,RX is a good way to load PC+8 into RX. */
3511 return do_dbranch(ctx
, ctx
->iaoq_f
+ 8, a
->l
, a
->n
);
3515 static bool trans_bv(DisasContext
*ctx
, arg_bv
*a
)
3520 dest
= load_gpr(ctx
, a
->b
);
3522 dest
= tcg_temp_new();
3523 tcg_gen_shli_reg(dest
, load_gpr(ctx
, a
->x
), 3);
3524 tcg_gen_add_reg(dest
, dest
, load_gpr(ctx
, a
->b
));
3526 dest
= do_ibranch_priv(ctx
, dest
);
3527 return do_ibranch(ctx
, dest
, 0, a
->n
);
3530 static bool trans_bve(DisasContext
*ctx
, arg_bve
*a
)
3534 #ifdef CONFIG_USER_ONLY
3535 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3536 return do_ibranch(ctx
, dest
, a
->l
, a
->n
);
3539 dest
= do_ibranch_priv(ctx
, load_gpr(ctx
, a
->b
));
3541 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_b
, cpu_iaoq_b
);
3542 if (ctx
->iaoq_b
== -1) {
3543 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
3545 copy_iaoq_entry(cpu_iaoq_b
, -1, dest
);
3546 tcg_gen_mov_i64(cpu_iasq_b
, space_select(ctx
, 0, dest
));
3548 copy_iaoq_entry(cpu_gr
[a
->l
], ctx
->iaoq_n
, ctx
->iaoq_n_var
);
3550 nullify_set(ctx
, a
->n
);
3551 tcg_gen_lookup_and_goto_ptr();
3552 ctx
->base
.is_jmp
= DISAS_NORETURN
;
3553 return nullify_end(ctx
);
3561 static void gen_fcpy_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3563 tcg_gen_mov_i32(dst
, src
);
3566 static bool trans_fid_f(DisasContext
*ctx
, arg_fid_f
*a
)
3570 if (TARGET_REGISTER_BITS
== 64) {
3571 ret
= 0x13080000000000ULL
; /* PA8700 (PCX-W2) */
3573 ret
= 0x0f080000000000ULL
; /* PA7300LC (PCX-L2) */
3577 save_frd(0, tcg_constant_i64(ret
));
3578 return nullify_end(ctx
);
3581 static bool trans_fcpy_f(DisasContext
*ctx
, arg_fclass01
*a
)
3583 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fcpy_f
);
3586 static void gen_fcpy_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3588 tcg_gen_mov_i64(dst
, src
);
3591 static bool trans_fcpy_d(DisasContext
*ctx
, arg_fclass01
*a
)
3593 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fcpy_d
);
3596 static void gen_fabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3598 tcg_gen_andi_i32(dst
, src
, INT32_MAX
);
3601 static bool trans_fabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3603 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fabs_f
);
3606 static void gen_fabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3608 tcg_gen_andi_i64(dst
, src
, INT64_MAX
);
3611 static bool trans_fabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3613 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fabs_d
);
3616 static bool trans_fsqrt_f(DisasContext
*ctx
, arg_fclass01
*a
)
3618 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_s
);
3621 static bool trans_fsqrt_d(DisasContext
*ctx
, arg_fclass01
*a
)
3623 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fsqrt_d
);
3626 static bool trans_frnd_f(DisasContext
*ctx
, arg_fclass01
*a
)
3628 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_frnd_s
);
3631 static bool trans_frnd_d(DisasContext
*ctx
, arg_fclass01
*a
)
3633 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_frnd_d
);
3636 static void gen_fneg_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3638 tcg_gen_xori_i32(dst
, src
, INT32_MIN
);
3641 static bool trans_fneg_f(DisasContext
*ctx
, arg_fclass01
*a
)
3643 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fneg_f
);
3646 static void gen_fneg_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3648 tcg_gen_xori_i64(dst
, src
, INT64_MIN
);
3651 static bool trans_fneg_d(DisasContext
*ctx
, arg_fclass01
*a
)
3653 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fneg_d
);
3656 static void gen_fnegabs_f(TCGv_i32 dst
, TCGv_env unused
, TCGv_i32 src
)
3658 tcg_gen_ori_i32(dst
, src
, INT32_MIN
);
3661 static bool trans_fnegabs_f(DisasContext
*ctx
, arg_fclass01
*a
)
3663 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_fnegabs_f
);
3666 static void gen_fnegabs_d(TCGv_i64 dst
, TCGv_env unused
, TCGv_i64 src
)
3668 tcg_gen_ori_i64(dst
, src
, INT64_MIN
);
3671 static bool trans_fnegabs_d(DisasContext
*ctx
, arg_fclass01
*a
)
3673 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_fnegabs_d
);
3680 static bool trans_fcnv_d_f(DisasContext
*ctx
, arg_fclass01
*a
)
3682 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_s
);
3685 static bool trans_fcnv_f_d(DisasContext
*ctx
, arg_fclass01
*a
)
3687 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_d
);
3690 static bool trans_fcnv_w_f(DisasContext
*ctx
, arg_fclass01
*a
)
3692 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_s
);
3695 static bool trans_fcnv_q_f(DisasContext
*ctx
, arg_fclass01
*a
)
3697 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_s
);
3700 static bool trans_fcnv_w_d(DisasContext
*ctx
, arg_fclass01
*a
)
3702 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_w_d
);
3705 static bool trans_fcnv_q_d(DisasContext
*ctx
, arg_fclass01
*a
)
3707 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_dw_d
);
3710 static bool trans_fcnv_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3712 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_w
);
3715 static bool trans_fcnv_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3717 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_w
);
3720 static bool trans_fcnv_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3722 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_dw
);
3725 static bool trans_fcnv_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3727 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_dw
);
3730 static bool trans_fcnv_t_f_w(DisasContext
*ctx
, arg_fclass01
*a
)
3732 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_w
);
3735 static bool trans_fcnv_t_d_w(DisasContext
*ctx
, arg_fclass01
*a
)
3737 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_w
);
3740 static bool trans_fcnv_t_f_q(DisasContext
*ctx
, arg_fclass01
*a
)
3742 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_dw
);
3745 static bool trans_fcnv_t_d_q(DisasContext
*ctx
, arg_fclass01
*a
)
3747 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_dw
);
3750 static bool trans_fcnv_uw_f(DisasContext
*ctx
, arg_fclass01
*a
)
3752 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_s
);
3755 static bool trans_fcnv_uq_f(DisasContext
*ctx
, arg_fclass01
*a
)
3757 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_s
);
3760 static bool trans_fcnv_uw_d(DisasContext
*ctx
, arg_fclass01
*a
)
3762 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_uw_d
);
3765 static bool trans_fcnv_uq_d(DisasContext
*ctx
, arg_fclass01
*a
)
3767 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_udw_d
);
3770 static bool trans_fcnv_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3772 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_uw
);
3775 static bool trans_fcnv_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3777 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_uw
);
3780 static bool trans_fcnv_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3782 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_s_udw
);
3785 static bool trans_fcnv_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3787 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_d_udw
);
3790 static bool trans_fcnv_t_f_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3792 return do_fop_wew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_uw
);
3795 static bool trans_fcnv_t_d_uw(DisasContext
*ctx
, arg_fclass01
*a
)
3797 return do_fop_wed(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_uw
);
3800 static bool trans_fcnv_t_f_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3802 return do_fop_dew(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_s_udw
);
3805 static bool trans_fcnv_t_d_uq(DisasContext
*ctx
, arg_fclass01
*a
)
3807 return do_fop_ded(ctx
, a
->t
, a
->r
, gen_helper_fcnv_t_d_udw
);
3814 static bool trans_fcmp_f(DisasContext
*ctx
, arg_fclass2
*a
)
3816 TCGv_i32 ta
, tb
, tc
, ty
;
3820 ta
= load_frw0_i32(a
->r1
);
3821 tb
= load_frw0_i32(a
->r2
);
3822 ty
= tcg_constant_i32(a
->y
);
3823 tc
= tcg_constant_i32(a
->c
);
3825 gen_helper_fcmp_s(tcg_env
, ta
, tb
, ty
, tc
);
3827 return nullify_end(ctx
);
3830 static bool trans_fcmp_d(DisasContext
*ctx
, arg_fclass2
*a
)
3837 ta
= load_frd0(a
->r1
);
3838 tb
= load_frd0(a
->r2
);
3839 ty
= tcg_constant_i32(a
->y
);
3840 tc
= tcg_constant_i32(a
->c
);
3842 gen_helper_fcmp_d(tcg_env
, ta
, tb
, ty
, tc
);
3844 return nullify_end(ctx
);
3847 static bool trans_ftest(DisasContext
*ctx
, arg_ftest
*a
)
3854 tcg_gen_ld32u_reg(t
, tcg_env
, offsetof(CPUHPPAState
, fr0_shadow
));
3861 case 0: /* simple */
3862 tcg_gen_andi_reg(t
, t
, 0x4000000);
3863 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3891 TCGv_reg c
= tcg_constant_reg(mask
);
3892 tcg_gen_or_reg(t
, t
, c
);
3893 ctx
->null_cond
= cond_make(TCG_COND_EQ
, t
, c
);
3895 tcg_gen_andi_reg(t
, t
, mask
);
3896 ctx
->null_cond
= cond_make_0(TCG_COND_EQ
, t
);
3899 unsigned cbit
= (a
->y
^ 1) - 1;
3901 tcg_gen_extract_reg(t
, t
, 21 - cbit
, 1);
3902 ctx
->null_cond
= cond_make_0(TCG_COND_NE
, t
);
3906 return nullify_end(ctx
);
3913 static bool trans_fadd_f(DisasContext
*ctx
, arg_fclass3
*a
)
3915 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_s
);
3918 static bool trans_fadd_d(DisasContext
*ctx
, arg_fclass3
*a
)
3920 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fadd_d
);
3923 static bool trans_fsub_f(DisasContext
*ctx
, arg_fclass3
*a
)
3925 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_s
);
3928 static bool trans_fsub_d(DisasContext
*ctx
, arg_fclass3
*a
)
3930 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fsub_d
);
3933 static bool trans_fmpy_f(DisasContext
*ctx
, arg_fclass3
*a
)
3935 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_s
);
3938 static bool trans_fmpy_d(DisasContext
*ctx
, arg_fclass3
*a
)
3940 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fmpy_d
);
3943 static bool trans_fdiv_f(DisasContext
*ctx
, arg_fclass3
*a
)
3945 return do_fop_weww(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_s
);
3948 static bool trans_fdiv_d(DisasContext
*ctx
, arg_fclass3
*a
)
3950 return do_fop_dedd(ctx
, a
->t
, a
->r1
, a
->r2
, gen_helper_fdiv_d
);
3953 static bool trans_xmpyu(DisasContext
*ctx
, arg_xmpyu
*a
)
3959 x
= load_frw0_i64(a
->r1
);
3960 y
= load_frw0_i64(a
->r2
);
3961 tcg_gen_mul_i64(x
, x
, y
);
3964 return nullify_end(ctx
);
3967 /* Convert the fmpyadd single-precision register encodings to standard. */
3968 static inline int fmpyadd_s_reg(unsigned r
)
3970 return (r
& 16) * 2 + 16 + (r
& 15);
3973 static bool do_fmpyadd_s(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
3975 int tm
= fmpyadd_s_reg(a
->tm
);
3976 int ra
= fmpyadd_s_reg(a
->ra
);
3977 int ta
= fmpyadd_s_reg(a
->ta
);
3978 int rm2
= fmpyadd_s_reg(a
->rm2
);
3979 int rm1
= fmpyadd_s_reg(a
->rm1
);
3983 do_fop_weww(ctx
, tm
, rm1
, rm2
, gen_helper_fmpy_s
);
3984 do_fop_weww(ctx
, ta
, ta
, ra
,
3985 is_sub
? gen_helper_fsub_s
: gen_helper_fadd_s
);
3987 return nullify_end(ctx
);
3990 static bool trans_fmpyadd_f(DisasContext
*ctx
, arg_mpyadd
*a
)
3992 return do_fmpyadd_s(ctx
, a
, false);
3995 static bool trans_fmpysub_f(DisasContext
*ctx
, arg_mpyadd
*a
)
3997 return do_fmpyadd_s(ctx
, a
, true);
4000 static bool do_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
, bool is_sub
)
4004 do_fop_dedd(ctx
, a
->tm
, a
->rm1
, a
->rm2
, gen_helper_fmpy_d
);
4005 do_fop_dedd(ctx
, a
->ta
, a
->ta
, a
->ra
,
4006 is_sub
? gen_helper_fsub_d
: gen_helper_fadd_d
);
4008 return nullify_end(ctx
);
4011 static bool trans_fmpyadd_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4013 return do_fmpyadd_d(ctx
, a
, false);
4016 static bool trans_fmpysub_d(DisasContext
*ctx
, arg_mpyadd
*a
)
4018 return do_fmpyadd_d(ctx
, a
, true);
4021 static bool trans_fmpyfadd_f(DisasContext
*ctx
, arg_fmpyfadd_f
*a
)
4026 x
= load_frw0_i32(a
->rm1
);
4027 y
= load_frw0_i32(a
->rm2
);
4028 z
= load_frw0_i32(a
->ra3
);
4031 gen_helper_fmpynfadd_s(x
, tcg_env
, x
, y
, z
);
4033 gen_helper_fmpyfadd_s(x
, tcg_env
, x
, y
, z
);
4036 save_frw_i32(a
->t
, x
);
4037 return nullify_end(ctx
);
4040 static bool trans_fmpyfadd_d(DisasContext
*ctx
, arg_fmpyfadd_d
*a
)
4045 x
= load_frd0(a
->rm1
);
4046 y
= load_frd0(a
->rm2
);
4047 z
= load_frd0(a
->ra3
);
4050 gen_helper_fmpynfadd_d(x
, tcg_env
, x
, y
, z
);
4052 gen_helper_fmpyfadd_d(x
, tcg_env
, x
, y
, z
);
4056 return nullify_end(ctx
);
4059 static bool trans_diag(DisasContext
*ctx
, arg_diag
*a
)
4061 CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR
);
4062 #ifndef CONFIG_USER_ONLY
4063 if (a
->i
== 0x100) {
4064 /* emulate PDC BTLB, called by SeaBIOS-hppa */
4066 gen_helper_diag_btlb(tcg_env
);
4067 return nullify_end(ctx
);
4070 qemu_log_mask(LOG_UNIMP
, "DIAG opcode 0x%04x ignored\n", a
->i
);
4074 static void hppa_tr_init_disas_context(DisasContextBase
*dcbase
, CPUState
*cs
)
4076 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4080 ctx
->tb_flags
= ctx
->base
.tb
->flags
;
4082 #ifdef CONFIG_USER_ONLY
4083 ctx
->privilege
= MMU_IDX_TO_PRIV(MMU_USER_IDX
);
4084 ctx
->mmu_idx
= MMU_USER_IDX
;
4085 ctx
->iaoq_f
= ctx
->base
.pc_first
| ctx
->privilege
;
4086 ctx
->iaoq_b
= ctx
->base
.tb
->cs_base
| ctx
->privilege
;
4087 ctx
->unalign
= (ctx
->tb_flags
& TB_FLAG_UNALIGN
? MO_UNALN
: MO_ALIGN
);
4089 ctx
->privilege
= (ctx
->tb_flags
>> TB_FLAG_PRIV_SHIFT
) & 3;
4090 ctx
->mmu_idx
= (ctx
->tb_flags
& PSW_D
4091 ? PRIV_P_TO_MMU_IDX(ctx
->privilege
, ctx
->tb_flags
& PSW_P
)
4094 /* Recover the IAOQ values from the GVA + PRIV. */
4095 uint64_t cs_base
= ctx
->base
.tb
->cs_base
;
4096 uint64_t iasq_f
= cs_base
& ~0xffffffffull
;
4097 int32_t diff
= cs_base
;
4099 ctx
->iaoq_f
= (ctx
->base
.pc_first
& ~iasq_f
) + ctx
->privilege
;
4100 ctx
->iaoq_b
= (diff
? ctx
->iaoq_f
+ diff
: -1);
4103 ctx
->iaoq_n_var
= NULL
;
4105 /* Bound the number of instructions by those left on the page. */
4106 bound
= -(ctx
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
4107 ctx
->base
.max_insns
= MIN(ctx
->base
.max_insns
, bound
);
4110 static void hppa_tr_tb_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4112 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4114 /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */
4115 ctx
->null_cond
= cond_make_f();
4116 ctx
->psw_n_nonzero
= false;
4117 if (ctx
->tb_flags
& PSW_N
) {
4118 ctx
->null_cond
.c
= TCG_COND_ALWAYS
;
4119 ctx
->psw_n_nonzero
= true;
4121 ctx
->null_lab
= NULL
;
4124 static void hppa_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cs
)
4126 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4128 tcg_gen_insn_start(ctx
->iaoq_f
, ctx
->iaoq_b
);
4131 static void hppa_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cs
)
4133 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4134 CPUHPPAState
*env
= cpu_env(cs
);
4137 /* Execute one insn. */
4138 #ifdef CONFIG_USER_ONLY
4139 if (ctx
->base
.pc_next
< TARGET_PAGE_SIZE
) {
4141 ret
= ctx
->base
.is_jmp
;
4142 assert(ret
!= DISAS_NEXT
);
4146 /* Always fetch the insn, even if nullified, so that we check
4147 the page permissions for execute. */
4148 uint32_t insn
= translator_ldl(env
, &ctx
->base
, ctx
->base
.pc_next
);
4150 /* Set up the IA queue for the next insn.
4151 This will be overwritten by a branch. */
4152 if (ctx
->iaoq_b
== -1) {
4154 ctx
->iaoq_n_var
= tcg_temp_new();
4155 tcg_gen_addi_reg(ctx
->iaoq_n_var
, cpu_iaoq_b
, 4);
4157 ctx
->iaoq_n
= ctx
->iaoq_b
+ 4;
4158 ctx
->iaoq_n_var
= NULL
;
4161 if (unlikely(ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4162 ctx
->null_cond
.c
= TCG_COND_NEVER
;
4166 if (!decode(ctx
, insn
)) {
4169 ret
= ctx
->base
.is_jmp
;
4170 assert(ctx
->null_lab
== NULL
);
4174 /* Advance the insn queue. Note that this check also detects
4175 a priority change within the instruction queue. */
4176 if (ret
== DISAS_NEXT
&& ctx
->iaoq_b
!= ctx
->iaoq_f
+ 4) {
4177 if (ctx
->iaoq_b
!= -1 && ctx
->iaoq_n
!= -1
4178 && use_goto_tb(ctx
, ctx
->iaoq_b
)
4179 && (ctx
->null_cond
.c
== TCG_COND_NEVER
4180 || ctx
->null_cond
.c
== TCG_COND_ALWAYS
)) {
4181 nullify_set(ctx
, ctx
->null_cond
.c
== TCG_COND_ALWAYS
);
4182 gen_goto_tb(ctx
, 0, ctx
->iaoq_b
, ctx
->iaoq_n
);
4183 ctx
->base
.is_jmp
= ret
= DISAS_NORETURN
;
4185 ctx
->base
.is_jmp
= ret
= DISAS_IAQ_N_STALE
;
4188 ctx
->iaoq_f
= ctx
->iaoq_b
;
4189 ctx
->iaoq_b
= ctx
->iaoq_n
;
4190 ctx
->base
.pc_next
+= 4;
4193 case DISAS_NORETURN
:
4194 case DISAS_IAQ_N_UPDATED
:
4198 case DISAS_IAQ_N_STALE
:
4199 case DISAS_IAQ_N_STALE_EXIT
:
4200 if (ctx
->iaoq_f
== -1) {
4201 tcg_gen_mov_reg(cpu_iaoq_f
, cpu_iaoq_b
);
4202 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_n
, ctx
->iaoq_n_var
);
4203 #ifndef CONFIG_USER_ONLY
4204 tcg_gen_mov_i64(cpu_iasq_f
, cpu_iasq_b
);
4207 ctx
->base
.is_jmp
= (ret
== DISAS_IAQ_N_STALE_EXIT
4209 : DISAS_IAQ_N_UPDATED
);
4210 } else if (ctx
->iaoq_b
== -1) {
4211 tcg_gen_mov_reg(cpu_iaoq_b
, ctx
->iaoq_n_var
);
4216 g_assert_not_reached();
4220 static void hppa_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cs
)
4222 DisasContext
*ctx
= container_of(dcbase
, DisasContext
, base
);
4223 DisasJumpType is_jmp
= ctx
->base
.is_jmp
;
4226 case DISAS_NORETURN
:
4228 case DISAS_TOO_MANY
:
4229 case DISAS_IAQ_N_STALE
:
4230 case DISAS_IAQ_N_STALE_EXIT
:
4231 copy_iaoq_entry(cpu_iaoq_f
, ctx
->iaoq_f
, cpu_iaoq_f
);
4232 copy_iaoq_entry(cpu_iaoq_b
, ctx
->iaoq_b
, cpu_iaoq_b
);
4235 case DISAS_IAQ_N_UPDATED
:
4236 if (is_jmp
!= DISAS_IAQ_N_STALE_EXIT
) {
4237 tcg_gen_lookup_and_goto_ptr();
4242 tcg_gen_exit_tb(NULL
, 0);
4245 g_assert_not_reached();
4249 static void hppa_tr_disas_log(const DisasContextBase
*dcbase
,
4250 CPUState
*cs
, FILE *logfile
)
4252 target_ulong pc
= dcbase
->pc_first
;
4254 #ifdef CONFIG_USER_ONLY
4257 fprintf(logfile
, "IN:\n0x00000000: (null)\n");
4260 fprintf(logfile
, "IN:\n0x000000b0: light-weight-syscall\n");
4263 fprintf(logfile
, "IN:\n0x000000e0: set-thread-pointer-syscall\n");
4266 fprintf(logfile
, "IN:\n0x00000100: syscall\n");
4271 fprintf(logfile
, "IN: %s\n", lookup_symbol(pc
));
4272 target_disas(logfile
, cs
, pc
, dcbase
->tb
->size
);
4275 static const TranslatorOps hppa_tr_ops
= {
4276 .init_disas_context
= hppa_tr_init_disas_context
,
4277 .tb_start
= hppa_tr_tb_start
,
4278 .insn_start
= hppa_tr_insn_start
,
4279 .translate_insn
= hppa_tr_translate_insn
,
4280 .tb_stop
= hppa_tr_tb_stop
,
4281 .disas_log
= hppa_tr_disas_log
,
4284 void gen_intermediate_code(CPUState
*cs
, TranslationBlock
*tb
, int *max_insns
,
4285 target_ulong pc
, void *host_pc
)
4288 translator_loop(cs
, tb
, max_insns
, pc
, host_pc
, &hppa_tr_ops
, &ctx
.base
);