2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/cpus.h"
28 #include "qemu/error-report.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32 #include "qapi/qmp/types.h"
34 #include "qapi-types.h"
35 #include "qapi-visit.h"
36 #include "qapi/visitor.h"
37 #include "qom/qom-qobject.h"
38 #include "sysemu/arch_init.h"
40 #if defined(CONFIG_KVM)
41 #include <linux/kvm_para.h>
44 #include "sysemu/sysemu.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/i386/topology.h"
47 #ifndef CONFIG_USER_ONLY
48 #include "exec/address-spaces.h"
50 #include "hw/xen/xen.h"
51 #include "hw/i386/apic_internal.h"
55 /* Cache topology CPUID constants: */
57 /* CPUID Leaf 2 Descriptors */
59 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
60 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
61 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
62 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
65 /* CPUID Leaf 4 constants: */
68 #define CPUID_4_TYPE_DCACHE 1
69 #define CPUID_4_TYPE_ICACHE 2
70 #define CPUID_4_TYPE_UNIFIED 3
72 #define CPUID_4_LEVEL(l) ((l) << 5)
74 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
75 #define CPUID_4_FULLY_ASSOC (1 << 9)
78 #define CPUID_4_NO_INVD_SHARING (1 << 0)
79 #define CPUID_4_INCLUSIVE (1 << 1)
80 #define CPUID_4_COMPLEX_IDX (1 << 2)
82 #define ASSOC_FULL 0xFF
84 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
85 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
95 a == ASSOC_FULL ? 0xF : \
96 0 /* invalid value */)
99 /* Definitions of the hardcoded cache entries we expose: */
102 #define L1D_LINE_SIZE 64
103 #define L1D_ASSOCIATIVITY 8
105 #define L1D_PARTITIONS 1
106 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
107 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
108 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
109 #define L1D_LINES_PER_TAG 1
110 #define L1D_SIZE_KB_AMD 64
111 #define L1D_ASSOCIATIVITY_AMD 2
113 /* L1 instruction cache: */
114 #define L1I_LINE_SIZE 64
115 #define L1I_ASSOCIATIVITY 8
117 #define L1I_PARTITIONS 1
118 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
119 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
120 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
121 #define L1I_LINES_PER_TAG 1
122 #define L1I_SIZE_KB_AMD 64
123 #define L1I_ASSOCIATIVITY_AMD 2
125 /* Level 2 unified cache: */
126 #define L2_LINE_SIZE 64
127 #define L2_ASSOCIATIVITY 16
129 #define L2_PARTITIONS 1
130 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
131 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
132 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
133 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
134 #define L2_LINES_PER_TAG 1
135 #define L2_SIZE_KB_AMD 512
137 /* Level 3 unified cache: */
138 #define L3_SIZE_KB 0 /* disabled */
139 #define L3_ASSOCIATIVITY 0 /* disabled */
140 #define L3_LINES_PER_TAG 0 /* disabled */
141 #define L3_LINE_SIZE 0 /* disabled */
142 #define L3_N_LINE_SIZE 64
143 #define L3_N_ASSOCIATIVITY 16
144 #define L3_N_SETS 16384
145 #define L3_N_PARTITIONS 1
146 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
147 #define L3_N_LINES_PER_TAG 1
148 #define L3_N_SIZE_KB_AMD 16384
150 /* TLB definitions: */
152 #define L1_DTLB_2M_ASSOC 1
153 #define L1_DTLB_2M_ENTRIES 255
154 #define L1_DTLB_4K_ASSOC 1
155 #define L1_DTLB_4K_ENTRIES 255
157 #define L1_ITLB_2M_ASSOC 1
158 #define L1_ITLB_2M_ENTRIES 255
159 #define L1_ITLB_4K_ASSOC 1
160 #define L1_ITLB_4K_ENTRIES 255
162 #define L2_DTLB_2M_ASSOC 0 /* disabled */
163 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
164 #define L2_DTLB_4K_ASSOC 4
165 #define L2_DTLB_4K_ENTRIES 512
167 #define L2_ITLB_2M_ASSOC 0 /* disabled */
168 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
169 #define L2_ITLB_4K_ASSOC 4
170 #define L2_ITLB_4K_ENTRIES 512
174 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
175 uint32_t vendor2
, uint32_t vendor3
)
178 for (i
= 0; i
< 4; i
++) {
179 dst
[i
] = vendor1
>> (8 * i
);
180 dst
[i
+ 4] = vendor2
>> (8 * i
);
181 dst
[i
+ 8] = vendor3
>> (8 * i
);
183 dst
[CPUID_VENDOR_SZ
] = '\0';
186 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
187 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
188 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
189 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
190 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
191 CPUID_PSE36 | CPUID_FXSR)
192 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
193 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
194 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
195 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
196 CPUID_PAE | CPUID_SEP | CPUID_APIC)
198 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
199 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
200 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
201 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
202 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
203 /* partly implemented:
204 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
206 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
207 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
208 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
209 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
210 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
211 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
213 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
214 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
215 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
216 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
217 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
220 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
222 #define TCG_EXT2_X86_64_FEATURES 0
225 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
226 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
227 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
228 TCG_EXT2_X86_64_FEATURES)
229 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
230 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
231 #define TCG_EXT4_FEATURES 0
232 #define TCG_SVM_FEATURES 0
233 #define TCG_KVM_FEATURES 0
234 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
235 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
236 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
237 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
240 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
241 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
242 CPUID_7_0_EBX_RDSEED */
243 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
245 #define TCG_7_0_EDX_FEATURES 0
246 #define TCG_APM_FEATURES 0
247 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
248 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
250 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
252 typedef struct FeatureWordInfo
{
253 /* feature flags names are taken from "Intel Processor Identification and
254 * the CPUID Instruction" and AMD's "CPUID Specification".
255 * In cases of disagreement between feature naming conventions,
256 * aliases may be added.
258 const char *feat_names
[32];
259 uint32_t cpuid_eax
; /* Input EAX for CPUID */
260 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
261 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
262 int cpuid_reg
; /* output register (R_* constant) */
263 uint32_t tcg_features
; /* Feature flags supported by TCG */
264 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
265 uint32_t migratable_flags
; /* Feature flags known to be migratable */
268 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
271 "fpu", "vme", "de", "pse",
272 "tsc", "msr", "pae", "mce",
273 "cx8", "apic", NULL
, "sep",
274 "mtrr", "pge", "mca", "cmov",
275 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
276 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
277 "fxsr", "sse", "sse2", "ss",
278 "ht" /* Intel htt */, "tm", "ia64", "pbe",
280 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
281 .tcg_features
= TCG_FEATURES
,
285 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
286 "ds-cpl", "vmx", "smx", "est",
287 "tm2", "ssse3", "cid", NULL
,
288 "fma", "cx16", "xtpr", "pdcm",
289 NULL
, "pcid", "dca", "sse4.1",
290 "sse4.2", "x2apic", "movbe", "popcnt",
291 "tsc-deadline", "aes", "xsave", "osxsave",
292 "avx", "f16c", "rdrand", "hypervisor",
294 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
295 .tcg_features
= TCG_EXT_FEATURES
,
297 /* Feature names that are already defined on feature_name[] but
298 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
299 * names on feat_names below. They are copied automatically
300 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
302 [FEAT_8000_0001_EDX
] = {
304 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
305 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
306 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
307 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
308 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
309 "nx", NULL
, "mmxext", NULL
/* mmx */,
310 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
311 NULL
, "lm", "3dnowext", "3dnow",
313 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
314 .tcg_features
= TCG_EXT2_FEATURES
,
316 [FEAT_8000_0001_ECX
] = {
318 "lahf-lm", "cmp-legacy", "svm", "extapic",
319 "cr8legacy", "abm", "sse4a", "misalignsse",
320 "3dnowprefetch", "osvw", "ibs", "xop",
321 "skinit", "wdt", NULL
, "lwp",
322 "fma4", "tce", NULL
, "nodeid-msr",
323 NULL
, "tbm", "topoext", "perfctr-core",
324 "perfctr-nb", NULL
, NULL
, NULL
,
325 NULL
, NULL
, NULL
, NULL
,
327 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
328 .tcg_features
= TCG_EXT3_FEATURES
,
330 [FEAT_C000_0001_EDX
] = {
332 NULL
, NULL
, "xstore", "xstore-en",
333 NULL
, NULL
, "xcrypt", "xcrypt-en",
334 "ace2", "ace2-en", "phe", "phe-en",
335 "pmm", "pmm-en", NULL
, NULL
,
336 NULL
, NULL
, NULL
, NULL
,
337 NULL
, NULL
, NULL
, NULL
,
338 NULL
, NULL
, NULL
, NULL
,
339 NULL
, NULL
, NULL
, NULL
,
341 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
342 .tcg_features
= TCG_EXT4_FEATURES
,
346 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
347 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
348 NULL
, NULL
, NULL
, NULL
,
349 NULL
, NULL
, NULL
, NULL
,
350 NULL
, NULL
, NULL
, NULL
,
351 NULL
, NULL
, NULL
, NULL
,
352 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
353 NULL
, NULL
, NULL
, NULL
,
355 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
356 .tcg_features
= TCG_KVM_FEATURES
,
358 [FEAT_HYPERV_EAX
] = {
360 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
361 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
362 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
363 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
364 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
365 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
366 NULL
, NULL
, NULL
, NULL
,
367 NULL
, NULL
, NULL
, NULL
,
368 NULL
, NULL
, NULL
, NULL
,
369 NULL
, NULL
, NULL
, NULL
,
370 NULL
, NULL
, NULL
, NULL
,
372 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EAX
,
374 [FEAT_HYPERV_EBX
] = {
376 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
377 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
378 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
379 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
380 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
381 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
383 NULL
, NULL
, NULL
, NULL
,
384 NULL
, NULL
, NULL
, NULL
,
385 NULL
, NULL
, NULL
, NULL
,
386 NULL
, NULL
, NULL
, NULL
,
388 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EBX
,
390 [FEAT_HYPERV_EDX
] = {
392 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
393 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
394 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
396 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
397 NULL
, NULL
, NULL
, NULL
,
398 NULL
, NULL
, NULL
, NULL
,
399 NULL
, NULL
, NULL
, NULL
,
400 NULL
, NULL
, NULL
, NULL
,
401 NULL
, NULL
, NULL
, NULL
,
403 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EDX
,
407 "npt", "lbrv", "svm-lock", "nrip-save",
408 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
409 NULL
, NULL
, "pause-filter", NULL
,
410 "pfthreshold", NULL
, NULL
, NULL
,
411 NULL
, NULL
, NULL
, NULL
,
412 NULL
, NULL
, NULL
, NULL
,
413 NULL
, NULL
, NULL
, NULL
,
414 NULL
, NULL
, NULL
, NULL
,
416 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
417 .tcg_features
= TCG_SVM_FEATURES
,
421 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
422 "hle", "avx2", NULL
, "smep",
423 "bmi2", "erms", "invpcid", "rtm",
424 NULL
, NULL
, "mpx", NULL
,
425 "avx512f", "avx512dq", "rdseed", "adx",
426 "smap", "avx512ifma", "pcommit", "clflushopt",
427 "clwb", NULL
, "avx512pf", "avx512er",
428 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
431 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
433 .tcg_features
= TCG_7_0_EBX_FEATURES
,
437 NULL
, "avx512vbmi", "umip", "pku",
438 "ospke", NULL
, NULL
, NULL
,
439 NULL
, NULL
, NULL
, NULL
,
440 NULL
, NULL
, "avx512-vpopcntdq", NULL
,
441 "la57", NULL
, NULL
, NULL
,
442 NULL
, NULL
, "rdpid", NULL
,
443 NULL
, NULL
, NULL
, NULL
,
444 NULL
, NULL
, NULL
, NULL
,
447 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
449 .tcg_features
= TCG_7_0_ECX_FEATURES
,
453 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
454 NULL
, NULL
, NULL
, NULL
,
455 NULL
, NULL
, NULL
, NULL
,
456 NULL
, NULL
, NULL
, NULL
,
457 NULL
, NULL
, NULL
, NULL
,
458 NULL
, NULL
, NULL
, NULL
,
459 NULL
, NULL
, NULL
, NULL
,
460 NULL
, NULL
, NULL
, NULL
,
463 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
465 .tcg_features
= TCG_7_0_EDX_FEATURES
,
467 [FEAT_8000_0007_EDX
] = {
469 NULL
, NULL
, NULL
, NULL
,
470 NULL
, NULL
, NULL
, NULL
,
471 "invtsc", NULL
, NULL
, NULL
,
472 NULL
, NULL
, NULL
, NULL
,
473 NULL
, NULL
, NULL
, NULL
,
474 NULL
, NULL
, NULL
, NULL
,
475 NULL
, NULL
, NULL
, NULL
,
476 NULL
, NULL
, NULL
, NULL
,
478 .cpuid_eax
= 0x80000007,
480 .tcg_features
= TCG_APM_FEATURES
,
481 .unmigratable_flags
= CPUID_APM_INVTSC
,
485 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
486 NULL
, NULL
, NULL
, NULL
,
487 NULL
, NULL
, NULL
, NULL
,
488 NULL
, NULL
, NULL
, NULL
,
489 NULL
, NULL
, NULL
, NULL
,
490 NULL
, NULL
, NULL
, NULL
,
491 NULL
, NULL
, NULL
, NULL
,
492 NULL
, NULL
, NULL
, NULL
,
495 .cpuid_needs_ecx
= true, .cpuid_ecx
= 1,
497 .tcg_features
= TCG_XSAVE_FEATURES
,
501 NULL
, NULL
, "arat", NULL
,
502 NULL
, NULL
, NULL
, NULL
,
503 NULL
, NULL
, NULL
, NULL
,
504 NULL
, NULL
, NULL
, NULL
,
505 NULL
, NULL
, NULL
, NULL
,
506 NULL
, NULL
, NULL
, NULL
,
507 NULL
, NULL
, NULL
, NULL
,
508 NULL
, NULL
, NULL
, NULL
,
510 .cpuid_eax
= 6, .cpuid_reg
= R_EAX
,
511 .tcg_features
= TCG_6_EAX_FEATURES
,
513 [FEAT_XSAVE_COMP_LO
] = {
515 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
518 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
519 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
520 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
523 [FEAT_XSAVE_COMP_HI
] = {
525 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
531 typedef struct X86RegisterInfo32
{
532 /* Name of register */
534 /* QAPI enum value register */
535 X86CPURegister32 qapi_enum
;
538 #define REGISTER(reg) \
539 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
540 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
552 typedef struct ExtSaveArea
{
553 uint32_t feature
, bits
;
554 uint32_t offset
, size
;
557 static const ExtSaveArea x86_ext_save_areas
[] = {
559 /* x87 FP state component is always enabled if XSAVE is supported */
560 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
561 /* x87 state is in the legacy region of the XSAVE area */
563 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
566 /* SSE state component is always enabled if XSAVE is supported */
567 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
568 /* SSE state is in the legacy region of the XSAVE area */
570 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
573 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
574 .offset
= offsetof(X86XSaveArea
, avx_state
),
575 .size
= sizeof(XSaveAVX
) },
576 [XSTATE_BNDREGS_BIT
] =
577 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
578 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
579 .size
= sizeof(XSaveBNDREG
) },
580 [XSTATE_BNDCSR_BIT
] =
581 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
582 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
583 .size
= sizeof(XSaveBNDCSR
) },
584 [XSTATE_OPMASK_BIT
] =
585 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
586 .offset
= offsetof(X86XSaveArea
, opmask_state
),
587 .size
= sizeof(XSaveOpmask
) },
588 [XSTATE_ZMM_Hi256_BIT
] =
589 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
590 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
591 .size
= sizeof(XSaveZMM_Hi256
) },
592 [XSTATE_Hi16_ZMM_BIT
] =
593 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
594 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
595 .size
= sizeof(XSaveHi16_ZMM
) },
597 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
598 .offset
= offsetof(X86XSaveArea
, pkru_state
),
599 .size
= sizeof(XSavePKRU
) },
602 static uint32_t xsave_area_size(uint64_t mask
)
607 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
608 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
609 if ((mask
>> i
) & 1) {
610 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
616 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
618 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
619 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
622 const char *get_register_name_32(unsigned int reg
)
624 if (reg
>= CPU_NB_REGS32
) {
627 return x86_reg_info_32
[reg
].name
;
631 * Returns the set of feature flags that are supported and migratable by
632 * QEMU, for a given FeatureWord.
634 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
636 FeatureWordInfo
*wi
= &feature_word_info
[w
];
640 for (i
= 0; i
< 32; i
++) {
641 uint32_t f
= 1U << i
;
643 /* If the feature name is known, it is implicitly considered migratable,
644 * unless it is explicitly set in unmigratable_flags */
645 if ((wi
->migratable_flags
& f
) ||
646 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
653 void host_cpuid(uint32_t function
, uint32_t count
,
654 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
660 : "=a"(vec
[0]), "=b"(vec
[1]),
661 "=c"(vec
[2]), "=d"(vec
[3])
662 : "0"(function
), "c"(count
) : "cc");
663 #elif defined(__i386__)
664 asm volatile("pusha \n\t"
666 "mov %%eax, 0(%2) \n\t"
667 "mov %%ebx, 4(%2) \n\t"
668 "mov %%ecx, 8(%2) \n\t"
669 "mov %%edx, 12(%2) \n\t"
671 : : "a"(function
), "c"(count
), "S"(vec
)
687 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
)
689 uint32_t eax
, ebx
, ecx
, edx
;
691 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
692 x86_cpu_vendor_words2str(vendor
, ebx
, edx
, ecx
);
694 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
696 *family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
699 *model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
702 *stepping
= eax
& 0x0F;
706 /* CPU class name definitions: */
708 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
709 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
711 /* Return type name for a given CPU model name
712 * Caller is responsible for freeing the returned string.
714 static char *x86_cpu_type_name(const char *model_name
)
716 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
719 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
724 if (cpu_model
== NULL
) {
728 typename
= x86_cpu_type_name(cpu_model
);
729 oc
= object_class_by_name(typename
);
734 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
736 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
737 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
738 return g_strndup(class_name
,
739 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
742 struct X86CPUDefinition
{
746 /* vendor is zero-terminated, 12 character ASCII string */
747 char vendor
[CPUID_VENDOR_SZ
+ 1];
751 FeatureWordArray features
;
755 static X86CPUDefinition builtin_x86_defs
[] = {
759 .vendor
= CPUID_VENDOR_AMD
,
763 .features
[FEAT_1_EDX
] =
765 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
767 .features
[FEAT_1_ECX
] =
768 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
769 .features
[FEAT_8000_0001_EDX
] =
770 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
771 .features
[FEAT_8000_0001_ECX
] =
772 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
773 .xlevel
= 0x8000000A,
774 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
779 .vendor
= CPUID_VENDOR_AMD
,
783 /* Missing: CPUID_HT */
784 .features
[FEAT_1_EDX
] =
786 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
787 CPUID_PSE36
| CPUID_VME
,
788 .features
[FEAT_1_ECX
] =
789 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
791 .features
[FEAT_8000_0001_EDX
] =
792 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
793 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
794 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
795 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
797 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
798 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
799 .features
[FEAT_8000_0001_ECX
] =
800 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
801 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
802 /* Missing: CPUID_SVM_LBRV */
803 .features
[FEAT_SVM
] =
805 .xlevel
= 0x8000001A,
806 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
811 .vendor
= CPUID_VENDOR_INTEL
,
815 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
816 .features
[FEAT_1_EDX
] =
818 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
819 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
820 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
821 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
822 .features
[FEAT_1_ECX
] =
823 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
825 .features
[FEAT_8000_0001_EDX
] =
826 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
827 .features
[FEAT_8000_0001_ECX
] =
829 .xlevel
= 0x80000008,
830 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
835 .vendor
= CPUID_VENDOR_INTEL
,
839 /* Missing: CPUID_HT */
840 .features
[FEAT_1_EDX
] =
841 PPRO_FEATURES
| CPUID_VME
|
842 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
844 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
845 .features
[FEAT_1_ECX
] =
846 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
847 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
848 .features
[FEAT_8000_0001_EDX
] =
849 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
850 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
851 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
852 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
853 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
854 .features
[FEAT_8000_0001_ECX
] =
856 .xlevel
= 0x80000008,
857 .model_id
= "Common KVM processor"
862 .vendor
= CPUID_VENDOR_INTEL
,
866 .features
[FEAT_1_EDX
] =
868 .features
[FEAT_1_ECX
] =
870 .xlevel
= 0x80000004,
871 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
876 .vendor
= CPUID_VENDOR_INTEL
,
880 .features
[FEAT_1_EDX
] =
881 PPRO_FEATURES
| CPUID_VME
|
882 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
883 .features
[FEAT_1_ECX
] =
885 .features
[FEAT_8000_0001_ECX
] =
887 .xlevel
= 0x80000008,
888 .model_id
= "Common 32-bit KVM processor"
893 .vendor
= CPUID_VENDOR_INTEL
,
897 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
898 .features
[FEAT_1_EDX
] =
899 PPRO_FEATURES
| CPUID_VME
|
900 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
902 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
903 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
904 .features
[FEAT_1_ECX
] =
905 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
906 .features
[FEAT_8000_0001_EDX
] =
908 .xlevel
= 0x80000008,
909 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
914 .vendor
= CPUID_VENDOR_INTEL
,
918 .features
[FEAT_1_EDX
] =
925 .vendor
= CPUID_VENDOR_INTEL
,
929 .features
[FEAT_1_EDX
] =
936 .vendor
= CPUID_VENDOR_INTEL
,
940 .features
[FEAT_1_EDX
] =
947 .vendor
= CPUID_VENDOR_INTEL
,
951 .features
[FEAT_1_EDX
] =
958 .vendor
= CPUID_VENDOR_AMD
,
962 .features
[FEAT_1_EDX
] =
963 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
965 .features
[FEAT_8000_0001_EDX
] =
966 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
967 .xlevel
= 0x80000008,
968 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
973 .vendor
= CPUID_VENDOR_INTEL
,
977 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
978 .features
[FEAT_1_EDX
] =
980 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
981 CPUID_ACPI
| CPUID_SS
,
982 /* Some CPUs got no CPUID_SEP */
983 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
985 .features
[FEAT_1_ECX
] =
986 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
988 .features
[FEAT_8000_0001_EDX
] =
990 .features
[FEAT_8000_0001_ECX
] =
992 .xlevel
= 0x80000008,
993 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
998 .vendor
= CPUID_VENDOR_INTEL
,
1002 .features
[FEAT_1_EDX
] =
1003 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1004 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1005 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1006 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1007 CPUID_DE
| CPUID_FP87
,
1008 .features
[FEAT_1_ECX
] =
1009 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1010 .features
[FEAT_8000_0001_EDX
] =
1011 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1012 .features
[FEAT_8000_0001_ECX
] =
1014 .xlevel
= 0x80000008,
1015 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1020 .vendor
= CPUID_VENDOR_INTEL
,
1024 .features
[FEAT_1_EDX
] =
1025 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1026 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1027 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1028 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1029 CPUID_DE
| CPUID_FP87
,
1030 .features
[FEAT_1_ECX
] =
1031 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1033 .features
[FEAT_8000_0001_EDX
] =
1034 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1035 .features
[FEAT_8000_0001_ECX
] =
1037 .xlevel
= 0x80000008,
1038 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1043 .vendor
= CPUID_VENDOR_INTEL
,
1047 .features
[FEAT_1_EDX
] =
1048 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1049 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1050 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1051 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1052 CPUID_DE
| CPUID_FP87
,
1053 .features
[FEAT_1_ECX
] =
1054 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1055 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1056 .features
[FEAT_8000_0001_EDX
] =
1057 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1058 .features
[FEAT_8000_0001_ECX
] =
1060 .xlevel
= 0x80000008,
1061 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
1066 .vendor
= CPUID_VENDOR_INTEL
,
1070 .features
[FEAT_1_EDX
] =
1071 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1072 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1073 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1074 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1075 CPUID_DE
| CPUID_FP87
,
1076 .features
[FEAT_1_ECX
] =
1077 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1078 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1079 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1080 .features
[FEAT_8000_0001_EDX
] =
1081 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1082 .features
[FEAT_8000_0001_ECX
] =
1084 .features
[FEAT_6_EAX
] =
1086 .xlevel
= 0x80000008,
1087 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1090 .name
= "SandyBridge",
1092 .vendor
= CPUID_VENDOR_INTEL
,
1096 .features
[FEAT_1_EDX
] =
1097 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1098 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1099 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1100 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1101 CPUID_DE
| CPUID_FP87
,
1102 .features
[FEAT_1_ECX
] =
1103 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1104 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1105 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1106 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1108 .features
[FEAT_8000_0001_EDX
] =
1109 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1111 .features
[FEAT_8000_0001_ECX
] =
1113 .features
[FEAT_XSAVE
] =
1114 CPUID_XSAVE_XSAVEOPT
,
1115 .features
[FEAT_6_EAX
] =
1117 .xlevel
= 0x80000008,
1118 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1121 .name
= "IvyBridge",
1123 .vendor
= CPUID_VENDOR_INTEL
,
1127 .features
[FEAT_1_EDX
] =
1128 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1129 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1130 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1131 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1132 CPUID_DE
| CPUID_FP87
,
1133 .features
[FEAT_1_ECX
] =
1134 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1135 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1136 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1137 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1138 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1139 .features
[FEAT_7_0_EBX
] =
1140 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1142 .features
[FEAT_8000_0001_EDX
] =
1143 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1145 .features
[FEAT_8000_0001_ECX
] =
1147 .features
[FEAT_XSAVE
] =
1148 CPUID_XSAVE_XSAVEOPT
,
1149 .features
[FEAT_6_EAX
] =
1151 .xlevel
= 0x80000008,
1152 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1155 .name
= "Haswell-noTSX",
1157 .vendor
= CPUID_VENDOR_INTEL
,
1161 .features
[FEAT_1_EDX
] =
1162 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1163 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1164 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1165 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1166 CPUID_DE
| CPUID_FP87
,
1167 .features
[FEAT_1_ECX
] =
1168 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1169 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1170 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1171 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1172 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1173 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1174 .features
[FEAT_8000_0001_EDX
] =
1175 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1177 .features
[FEAT_8000_0001_ECX
] =
1178 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1179 .features
[FEAT_7_0_EBX
] =
1180 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1181 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1182 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1183 .features
[FEAT_XSAVE
] =
1184 CPUID_XSAVE_XSAVEOPT
,
1185 .features
[FEAT_6_EAX
] =
1187 .xlevel
= 0x80000008,
1188 .model_id
= "Intel Core Processor (Haswell, no TSX)",
1192 .vendor
= CPUID_VENDOR_INTEL
,
1196 .features
[FEAT_1_EDX
] =
1197 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1198 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1199 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1200 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1201 CPUID_DE
| CPUID_FP87
,
1202 .features
[FEAT_1_ECX
] =
1203 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1204 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1205 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1206 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1207 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1208 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1209 .features
[FEAT_8000_0001_EDX
] =
1210 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1212 .features
[FEAT_8000_0001_ECX
] =
1213 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1214 .features
[FEAT_7_0_EBX
] =
1215 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1216 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1217 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1219 .features
[FEAT_XSAVE
] =
1220 CPUID_XSAVE_XSAVEOPT
,
1221 .features
[FEAT_6_EAX
] =
1223 .xlevel
= 0x80000008,
1224 .model_id
= "Intel Core Processor (Haswell)",
1227 .name
= "Broadwell-noTSX",
1229 .vendor
= CPUID_VENDOR_INTEL
,
1233 .features
[FEAT_1_EDX
] =
1234 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1235 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1236 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1237 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1238 CPUID_DE
| CPUID_FP87
,
1239 .features
[FEAT_1_ECX
] =
1240 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1241 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1242 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1243 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1244 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1245 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1246 .features
[FEAT_8000_0001_EDX
] =
1247 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1249 .features
[FEAT_8000_0001_ECX
] =
1250 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1251 .features
[FEAT_7_0_EBX
] =
1252 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1253 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1254 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1255 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1257 .features
[FEAT_XSAVE
] =
1258 CPUID_XSAVE_XSAVEOPT
,
1259 .features
[FEAT_6_EAX
] =
1261 .xlevel
= 0x80000008,
1262 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
1265 .name
= "Broadwell",
1267 .vendor
= CPUID_VENDOR_INTEL
,
1271 .features
[FEAT_1_EDX
] =
1272 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1273 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1274 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1275 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1276 CPUID_DE
| CPUID_FP87
,
1277 .features
[FEAT_1_ECX
] =
1278 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1279 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1280 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1281 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1282 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1283 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1284 .features
[FEAT_8000_0001_EDX
] =
1285 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1287 .features
[FEAT_8000_0001_ECX
] =
1288 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1289 .features
[FEAT_7_0_EBX
] =
1290 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1291 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1292 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1293 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1295 .features
[FEAT_XSAVE
] =
1296 CPUID_XSAVE_XSAVEOPT
,
1297 .features
[FEAT_6_EAX
] =
1299 .xlevel
= 0x80000008,
1300 .model_id
= "Intel Core Processor (Broadwell)",
1303 .name
= "Skylake-Client",
1305 .vendor
= CPUID_VENDOR_INTEL
,
1309 .features
[FEAT_1_EDX
] =
1310 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1311 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1312 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1313 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1314 CPUID_DE
| CPUID_FP87
,
1315 .features
[FEAT_1_ECX
] =
1316 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1317 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1318 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1319 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1320 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1321 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1322 .features
[FEAT_8000_0001_EDX
] =
1323 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1325 .features
[FEAT_8000_0001_ECX
] =
1326 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1327 .features
[FEAT_7_0_EBX
] =
1328 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1329 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1330 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1331 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1332 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
,
1333 /* Missing: XSAVES (not supported by some Linux versions,
1334 * including v4.1 to v4.12).
1335 * KVM doesn't yet expose any XSAVES state save component,
1336 * and the only one defined in Skylake (processor tracing)
1337 * probably will block migration anyway.
1339 .features
[FEAT_XSAVE
] =
1340 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1341 CPUID_XSAVE_XGETBV1
,
1342 .features
[FEAT_6_EAX
] =
1344 .xlevel
= 0x80000008,
1345 .model_id
= "Intel Core Processor (Skylake)",
1348 .name
= "Skylake-Server",
1350 .vendor
= CPUID_VENDOR_INTEL
,
1354 .features
[FEAT_1_EDX
] =
1355 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1356 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1357 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1358 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1359 CPUID_DE
| CPUID_FP87
,
1360 .features
[FEAT_1_ECX
] =
1361 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1362 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1363 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1364 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1365 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1366 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1367 .features
[FEAT_8000_0001_EDX
] =
1368 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
1369 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1370 .features
[FEAT_8000_0001_ECX
] =
1371 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1372 .features
[FEAT_7_0_EBX
] =
1373 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1374 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1375 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1376 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1377 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_CLWB
|
1378 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
1379 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
1380 CPUID_7_0_EBX_AVX512VL
,
1381 /* Missing: XSAVES (not supported by some Linux versions,
1382 * including v4.1 to v4.12).
1383 * KVM doesn't yet expose any XSAVES state save component,
1384 * and the only one defined in Skylake (processor tracing)
1385 * probably will block migration anyway.
1387 .features
[FEAT_XSAVE
] =
1388 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1389 CPUID_XSAVE_XGETBV1
,
1390 .features
[FEAT_6_EAX
] =
1392 .xlevel
= 0x80000008,
1393 .model_id
= "Intel Xeon Processor (Skylake)",
1396 .name
= "Opteron_G1",
1398 .vendor
= CPUID_VENDOR_AMD
,
1402 .features
[FEAT_1_EDX
] =
1403 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1404 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1405 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1406 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1407 CPUID_DE
| CPUID_FP87
,
1408 .features
[FEAT_1_ECX
] =
1410 .features
[FEAT_8000_0001_EDX
] =
1411 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1412 .xlevel
= 0x80000008,
1413 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1416 .name
= "Opteron_G2",
1418 .vendor
= CPUID_VENDOR_AMD
,
1422 .features
[FEAT_1_EDX
] =
1423 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1424 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1425 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1426 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1427 CPUID_DE
| CPUID_FP87
,
1428 .features
[FEAT_1_ECX
] =
1429 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1430 /* Missing: CPUID_EXT2_RDTSCP */
1431 .features
[FEAT_8000_0001_EDX
] =
1432 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1433 .features
[FEAT_8000_0001_ECX
] =
1434 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1435 .xlevel
= 0x80000008,
1436 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1439 .name
= "Opteron_G3",
1441 .vendor
= CPUID_VENDOR_AMD
,
1445 .features
[FEAT_1_EDX
] =
1446 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1447 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1448 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1449 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1450 CPUID_DE
| CPUID_FP87
,
1451 .features
[FEAT_1_ECX
] =
1452 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1454 /* Missing: CPUID_EXT2_RDTSCP */
1455 .features
[FEAT_8000_0001_EDX
] =
1456 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1457 .features
[FEAT_8000_0001_ECX
] =
1458 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1459 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1460 .xlevel
= 0x80000008,
1461 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1464 .name
= "Opteron_G4",
1466 .vendor
= CPUID_VENDOR_AMD
,
1470 .features
[FEAT_1_EDX
] =
1471 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1472 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1473 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1474 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1475 CPUID_DE
| CPUID_FP87
,
1476 .features
[FEAT_1_ECX
] =
1477 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1478 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1479 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1481 /* Missing: CPUID_EXT2_RDTSCP */
1482 .features
[FEAT_8000_0001_EDX
] =
1483 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1485 .features
[FEAT_8000_0001_ECX
] =
1486 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1487 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1488 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1491 .xlevel
= 0x8000001A,
1492 .model_id
= "AMD Opteron 62xx class CPU",
1495 .name
= "Opteron_G5",
1497 .vendor
= CPUID_VENDOR_AMD
,
1501 .features
[FEAT_1_EDX
] =
1502 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1503 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1504 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1505 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1506 CPUID_DE
| CPUID_FP87
,
1507 .features
[FEAT_1_ECX
] =
1508 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1509 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1510 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1511 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1512 /* Missing: CPUID_EXT2_RDTSCP */
1513 .features
[FEAT_8000_0001_EDX
] =
1514 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1516 .features
[FEAT_8000_0001_ECX
] =
1517 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1518 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1519 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1522 .xlevel
= 0x8000001A,
1523 .model_id
= "AMD Opteron 63xx class CPU",
1528 .vendor
= CPUID_VENDOR_AMD
,
1532 .features
[FEAT_1_EDX
] =
1533 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
1534 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
1535 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
1536 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
1537 CPUID_VME
| CPUID_FP87
,
1538 .features
[FEAT_1_ECX
] =
1539 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
1540 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
1541 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1542 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
1543 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1544 .features
[FEAT_8000_0001_EDX
] =
1545 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
1546 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
1548 .features
[FEAT_8000_0001_ECX
] =
1549 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
1550 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
1551 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1552 .features
[FEAT_7_0_EBX
] =
1553 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
1554 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
1555 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
1556 CPUID_7_0_EBX_SHA_NI
,
1557 /* Missing: XSAVES (not supported by some Linux versions,
1558 * including v4.1 to v4.12).
1559 * KVM doesn't yet expose any XSAVES state save component.
1561 .features
[FEAT_XSAVE
] =
1562 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1563 CPUID_XSAVE_XGETBV1
,
1564 .features
[FEAT_6_EAX
] =
1566 .xlevel
= 0x8000000A,
1567 .model_id
= "AMD EPYC Processor",
1571 typedef struct PropValue
{
1572 const char *prop
, *value
;
1575 /* KVM-specific features that are automatically added/removed
1576 * from all CPU models when KVM is enabled.
1578 static PropValue kvm_default_props
[] = {
1579 { "kvmclock", "on" },
1580 { "kvm-nopiodelay", "on" },
1581 { "kvm-asyncpf", "on" },
1582 { "kvm-steal-time", "on" },
1583 { "kvm-pv-eoi", "on" },
1584 { "kvmclock-stable-bit", "on" },
1587 { "monitor", "off" },
1592 /* TCG-specific defaults that override all CPU models when using TCG
1594 static PropValue tcg_default_props
[] = {
1600 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
1603 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
1604 if (!strcmp(pv
->prop
, prop
)) {
1610 /* It is valid to call this function only for properties that
1611 * are already present in the kvm_default_props table.
1616 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1617 bool migratable_only
);
1619 static bool lmce_supported(void)
1621 uint64_t mce_cap
= 0;
1624 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
1629 return !!(mce_cap
& MCG_LMCE_P
);
1632 #define CPUID_MODEL_ID_SZ 48
1635 * cpu_x86_fill_model_id:
1636 * Get CPUID model ID string from host CPU.
1638 * @str should have at least CPUID_MODEL_ID_SZ bytes
1640 * The function does NOT add a null terminator to the string
1643 static int cpu_x86_fill_model_id(char *str
)
1645 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1648 for (i
= 0; i
< 3; i
++) {
1649 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1650 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1651 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1652 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1653 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1658 static Property max_x86_cpu_properties
[] = {
1659 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
1660 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
1661 DEFINE_PROP_END_OF_LIST()
1664 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1666 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1667 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1671 xcc
->model_description
=
1672 "Enables all features supported by the accelerator in the current host";
1674 dc
->props
= max_x86_cpu_properties
;
1677 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
);
1679 static void max_x86_cpu_initfn(Object
*obj
)
1681 X86CPU
*cpu
= X86_CPU(obj
);
1682 CPUX86State
*env
= &cpu
->env
;
1683 KVMState
*s
= kvm_state
;
1685 /* We can't fill the features array here because we don't know yet if
1686 * "migratable" is true or false.
1688 cpu
->max_features
= true;
1690 if (kvm_enabled()) {
1691 char vendor
[CPUID_VENDOR_SZ
+ 1] = { 0 };
1692 char model_id
[CPUID_MODEL_ID_SZ
+ 1] = { 0 };
1693 int family
, model
, stepping
;
1695 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
1697 cpu_x86_fill_model_id(model_id
);
1699 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", &error_abort
);
1700 object_property_set_int(OBJECT(cpu
), family
, "family", &error_abort
);
1701 object_property_set_int(OBJECT(cpu
), model
, "model", &error_abort
);
1702 object_property_set_int(OBJECT(cpu
), stepping
, "stepping",
1704 object_property_set_str(OBJECT(cpu
), model_id
, "model-id",
1707 env
->cpuid_min_level
=
1708 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1709 env
->cpuid_min_xlevel
=
1710 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1711 env
->cpuid_min_xlevel2
=
1712 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1714 if (lmce_supported()) {
1715 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
1718 object_property_set_str(OBJECT(cpu
), CPUID_VENDOR_AMD
,
1719 "vendor", &error_abort
);
1720 object_property_set_int(OBJECT(cpu
), 6, "family", &error_abort
);
1721 object_property_set_int(OBJECT(cpu
), 6, "model", &error_abort
);
1722 object_property_set_int(OBJECT(cpu
), 3, "stepping", &error_abort
);
1723 object_property_set_str(OBJECT(cpu
),
1724 "QEMU TCG CPU version " QEMU_HW_VERSION
,
1725 "model-id", &error_abort
);
1728 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1731 static const TypeInfo max_x86_cpu_type_info
= {
1732 .name
= X86_CPU_TYPE_NAME("max"),
1733 .parent
= TYPE_X86_CPU
,
1734 .instance_init
= max_x86_cpu_initfn
,
1735 .class_init
= max_x86_cpu_class_init
,
1740 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1742 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1744 xcc
->kvm_required
= true;
1747 xcc
->model_description
=
1748 "KVM processor with all supported host features "
1749 "(only available in KVM mode)";
1752 static const TypeInfo host_x86_cpu_type_info
= {
1753 .name
= X86_CPU_TYPE_NAME("host"),
1754 .parent
= X86_CPU_TYPE_NAME("max"),
1755 .class_init
= host_x86_cpu_class_init
,
1760 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
1762 FeatureWordInfo
*f
= &feature_word_info
[w
];
1765 for (i
= 0; i
< 32; ++i
) {
1766 if ((1UL << i
) & mask
) {
1767 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1769 warn_report("%s doesn't support requested feature: "
1770 "CPUID.%02XH:%s%s%s [bit %d]",
1771 kvm_enabled() ? "host" : "TCG",
1773 f
->feat_names
[i
] ? "." : "",
1774 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1779 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
1780 const char *name
, void *opaque
,
1783 X86CPU
*cpu
= X86_CPU(obj
);
1784 CPUX86State
*env
= &cpu
->env
;
1787 value
= (env
->cpuid_version
>> 8) & 0xf;
1789 value
+= (env
->cpuid_version
>> 20) & 0xff;
1791 visit_type_int(v
, name
, &value
, errp
);
1794 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
1795 const char *name
, void *opaque
,
1798 X86CPU
*cpu
= X86_CPU(obj
);
1799 CPUX86State
*env
= &cpu
->env
;
1800 const int64_t min
= 0;
1801 const int64_t max
= 0xff + 0xf;
1802 Error
*local_err
= NULL
;
1805 visit_type_int(v
, name
, &value
, &local_err
);
1807 error_propagate(errp
, local_err
);
1810 if (value
< min
|| value
> max
) {
1811 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1812 name
? name
: "null", value
, min
, max
);
1816 env
->cpuid_version
&= ~0xff00f00;
1818 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1820 env
->cpuid_version
|= value
<< 8;
1824 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
1825 const char *name
, void *opaque
,
1828 X86CPU
*cpu
= X86_CPU(obj
);
1829 CPUX86State
*env
= &cpu
->env
;
1832 value
= (env
->cpuid_version
>> 4) & 0xf;
1833 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1834 visit_type_int(v
, name
, &value
, errp
);
1837 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
1838 const char *name
, void *opaque
,
1841 X86CPU
*cpu
= X86_CPU(obj
);
1842 CPUX86State
*env
= &cpu
->env
;
1843 const int64_t min
= 0;
1844 const int64_t max
= 0xff;
1845 Error
*local_err
= NULL
;
1848 visit_type_int(v
, name
, &value
, &local_err
);
1850 error_propagate(errp
, local_err
);
1853 if (value
< min
|| value
> max
) {
1854 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1855 name
? name
: "null", value
, min
, max
);
1859 env
->cpuid_version
&= ~0xf00f0;
1860 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1863 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1864 const char *name
, void *opaque
,
1867 X86CPU
*cpu
= X86_CPU(obj
);
1868 CPUX86State
*env
= &cpu
->env
;
1871 value
= env
->cpuid_version
& 0xf;
1872 visit_type_int(v
, name
, &value
, errp
);
1875 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1876 const char *name
, void *opaque
,
1879 X86CPU
*cpu
= X86_CPU(obj
);
1880 CPUX86State
*env
= &cpu
->env
;
1881 const int64_t min
= 0;
1882 const int64_t max
= 0xf;
1883 Error
*local_err
= NULL
;
1886 visit_type_int(v
, name
, &value
, &local_err
);
1888 error_propagate(errp
, local_err
);
1891 if (value
< min
|| value
> max
) {
1892 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1893 name
? name
: "null", value
, min
, max
);
1897 env
->cpuid_version
&= ~0xf;
1898 env
->cpuid_version
|= value
& 0xf;
1901 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1903 X86CPU
*cpu
= X86_CPU(obj
);
1904 CPUX86State
*env
= &cpu
->env
;
1907 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
1908 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1909 env
->cpuid_vendor3
);
1913 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1916 X86CPU
*cpu
= X86_CPU(obj
);
1917 CPUX86State
*env
= &cpu
->env
;
1920 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1921 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
1925 env
->cpuid_vendor1
= 0;
1926 env
->cpuid_vendor2
= 0;
1927 env
->cpuid_vendor3
= 0;
1928 for (i
= 0; i
< 4; i
++) {
1929 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1930 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1931 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1935 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1937 X86CPU
*cpu
= X86_CPU(obj
);
1938 CPUX86State
*env
= &cpu
->env
;
1942 value
= g_malloc(48 + 1);
1943 for (i
= 0; i
< 48; i
++) {
1944 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1950 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1953 X86CPU
*cpu
= X86_CPU(obj
);
1954 CPUX86State
*env
= &cpu
->env
;
1957 if (model_id
== NULL
) {
1960 len
= strlen(model_id
);
1961 memset(env
->cpuid_model
, 0, 48);
1962 for (i
= 0; i
< 48; i
++) {
1966 c
= (uint8_t)model_id
[i
];
1968 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1972 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
1973 void *opaque
, Error
**errp
)
1975 X86CPU
*cpu
= X86_CPU(obj
);
1978 value
= cpu
->env
.tsc_khz
* 1000;
1979 visit_type_int(v
, name
, &value
, errp
);
1982 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
1983 void *opaque
, Error
**errp
)
1985 X86CPU
*cpu
= X86_CPU(obj
);
1986 const int64_t min
= 0;
1987 const int64_t max
= INT64_MAX
;
1988 Error
*local_err
= NULL
;
1991 visit_type_int(v
, name
, &value
, &local_err
);
1993 error_propagate(errp
, local_err
);
1996 if (value
< min
|| value
> max
) {
1997 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1998 name
? name
: "null", value
, min
, max
);
2002 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
2005 /* Generic getter for "feature-words" and "filtered-features" properties */
2006 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
2007 const char *name
, void *opaque
,
2010 uint32_t *array
= (uint32_t *)opaque
;
2012 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
2013 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
2014 X86CPUFeatureWordInfoList
*list
= NULL
;
2016 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2017 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2018 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
2019 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
2020 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
2021 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
2022 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
2023 qwi
->features
= array
[w
];
2025 /* List will be in reverse order, but order shouldn't matter */
2026 list_entries
[w
].next
= list
;
2027 list_entries
[w
].value
= &word_infos
[w
];
2028 list
= &list_entries
[w
];
2031 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
2034 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2035 void *opaque
, Error
**errp
)
2037 X86CPU
*cpu
= X86_CPU(obj
);
2038 int64_t value
= cpu
->hyperv_spinlock_attempts
;
2040 visit_type_int(v
, name
, &value
, errp
);
2043 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2044 void *opaque
, Error
**errp
)
2046 const int64_t min
= 0xFFF;
2047 const int64_t max
= UINT_MAX
;
2048 X86CPU
*cpu
= X86_CPU(obj
);
2052 visit_type_int(v
, name
, &value
, &err
);
2054 error_propagate(errp
, err
);
2058 if (value
< min
|| value
> max
) {
2059 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
2060 " (minimum: %" PRId64
", maximum: %" PRId64
")",
2061 object_get_typename(obj
), name
? name
: "null",
2065 cpu
->hyperv_spinlock_attempts
= value
;
2068 static const PropertyInfo qdev_prop_spinlocks
= {
2070 .get
= x86_get_hv_spinlocks
,
2071 .set
= x86_set_hv_spinlocks
,
2074 /* Convert all '_' in a feature string option name to '-', to make feature
2075 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2077 static inline void feat2prop(char *s
)
2079 while ((s
= strchr(s
, '_'))) {
2084 /* Return the feature property name for a feature flag bit */
2085 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
2087 /* XSAVE components are automatically enabled by other features,
2088 * so return the original feature name instead
2090 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
2091 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
2093 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
2094 x86_ext_save_areas
[comp
].bits
) {
2095 w
= x86_ext_save_areas
[comp
].feature
;
2096 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
2101 assert(w
< FEATURE_WORDS
);
2102 return feature_word_info
[w
].feat_names
[bitnr
];
2105 /* Compatibily hack to maintain legacy +-feat semantic,
2106 * where +-feat overwrites any feature set by
2107 * feat=on|feat even if the later is parsed after +-feat
2108 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2110 static GList
*plus_features
, *minus_features
;
2112 static gint
compare_string(gconstpointer a
, gconstpointer b
)
2114 return g_strcmp0(a
, b
);
2117 /* Parse "+feature,-feature,feature=foo" CPU feature string
2119 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
2122 char *featurestr
; /* Single 'key=value" string being parsed */
2123 static bool cpu_globals_initialized
;
2124 bool ambiguous
= false;
2126 if (cpu_globals_initialized
) {
2129 cpu_globals_initialized
= true;
2135 for (featurestr
= strtok(features
, ",");
2137 featurestr
= strtok(NULL
, ",")) {
2139 const char *val
= NULL
;
2142 GlobalProperty
*prop
;
2144 /* Compatibility syntax: */
2145 if (featurestr
[0] == '+') {
2146 plus_features
= g_list_append(plus_features
,
2147 g_strdup(featurestr
+ 1));
2149 } else if (featurestr
[0] == '-') {
2150 minus_features
= g_list_append(minus_features
,
2151 g_strdup(featurestr
+ 1));
2155 eq
= strchr(featurestr
, '=');
2163 feat2prop(featurestr
);
2166 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
2167 warn_report("Ambiguous CPU model string. "
2168 "Don't mix both \"+%s\" and \"%s=%s\"",
2172 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
2173 warn_report("Ambiguous CPU model string. "
2174 "Don't mix both \"-%s\" and \"%s=%s\"",
2180 if (!strcmp(name
, "tsc-freq")) {
2184 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
2185 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
2186 error_setg(errp
, "bad numerical value %s", val
);
2189 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
2191 name
= "tsc-frequency";
2194 prop
= g_new0(typeof(*prop
), 1);
2195 prop
->driver
= typename
;
2196 prop
->property
= g_strdup(name
);
2197 prop
->value
= g_strdup(val
);
2198 prop
->errp
= &error_fatal
;
2199 qdev_prop_register_global(prop
);
2203 warn_report("Compatibility of ambiguous CPU model "
2204 "strings won't be kept on future QEMU versions");
2208 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
);
2209 static int x86_cpu_filter_features(X86CPU
*cpu
);
2211 /* Check for missing features that may prevent the CPU class from
2212 * running using the current machine and accelerator.
2214 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
2215 strList
**missing_feats
)
2220 strList
**next
= missing_feats
;
2222 if (xcc
->kvm_required
&& !kvm_enabled()) {
2223 strList
*new = g_new0(strList
, 1);
2224 new->value
= g_strdup("kvm");;
2225 *missing_feats
= new;
2229 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
2231 x86_cpu_expand_features(xc
, &err
);
2233 /* Errors at x86_cpu_expand_features should never happen,
2234 * but in case it does, just report the model as not
2235 * runnable at all using the "type" property.
2237 strList
*new = g_new0(strList
, 1);
2238 new->value
= g_strdup("type");
2243 x86_cpu_filter_features(xc
);
2245 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2246 uint32_t filtered
= xc
->filtered_features
[w
];
2248 for (i
= 0; i
< 32; i
++) {
2249 if (filtered
& (1UL << i
)) {
2250 strList
*new = g_new0(strList
, 1);
2251 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
2258 object_unref(OBJECT(xc
));
2261 /* Print all cpuid feature names in featureset
2263 static void listflags(FILE *f
, fprintf_function print
, const char **featureset
)
2268 for (bit
= 0; bit
< 32; bit
++) {
2269 if (featureset
[bit
]) {
2270 print(f
, "%s%s", first
? "" : " ", featureset
[bit
]);
2276 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
2277 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2279 ObjectClass
*class_a
= (ObjectClass
*)a
;
2280 ObjectClass
*class_b
= (ObjectClass
*)b
;
2281 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
2282 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
2283 const char *name_a
, *name_b
;
2285 if (cc_a
->ordering
!= cc_b
->ordering
) {
2286 return cc_a
->ordering
- cc_b
->ordering
;
2288 name_a
= object_class_get_name(class_a
);
2289 name_b
= object_class_get_name(class_b
);
2290 return strcmp(name_a
, name_b
);
2294 static GSList
*get_sorted_cpu_model_list(void)
2296 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
2297 list
= g_slist_sort(list
, x86_cpu_list_compare
);
2301 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
2303 ObjectClass
*oc
= data
;
2304 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2305 CPUListState
*s
= user_data
;
2306 char *name
= x86_cpu_class_get_model_name(cc
);
2307 const char *desc
= cc
->model_description
;
2308 if (!desc
&& cc
->cpu_def
) {
2309 desc
= cc
->cpu_def
->model_id
;
2312 (*s
->cpu_fprintf
)(s
->file
, "x86 %16s %-48s\n",
2317 /* list available CPU models and flags */
2318 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2323 .cpu_fprintf
= cpu_fprintf
,
2327 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2328 list
= get_sorted_cpu_model_list();
2329 g_slist_foreach(list
, x86_cpu_list_entry
, &s
);
2332 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
2333 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
2334 FeatureWordInfo
*fw
= &feature_word_info
[i
];
2336 (*cpu_fprintf
)(f
, " ");
2337 listflags(f
, cpu_fprintf
, fw
->feat_names
);
2338 (*cpu_fprintf
)(f
, "\n");
2342 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
2344 ObjectClass
*oc
= data
;
2345 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2346 CpuDefinitionInfoList
**cpu_list
= user_data
;
2347 CpuDefinitionInfoList
*entry
;
2348 CpuDefinitionInfo
*info
;
2350 info
= g_malloc0(sizeof(*info
));
2351 info
->name
= x86_cpu_class_get_model_name(cc
);
2352 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
2353 info
->has_unavailable_features
= true;
2354 info
->q_typename
= g_strdup(object_class_get_name(oc
));
2355 info
->migration_safe
= cc
->migration_safe
;
2356 info
->has_migration_safe
= true;
2357 info
->q_static
= cc
->static_model
;
2359 entry
= g_malloc0(sizeof(*entry
));
2360 entry
->value
= info
;
2361 entry
->next
= *cpu_list
;
2365 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2367 CpuDefinitionInfoList
*cpu_list
= NULL
;
2368 GSList
*list
= get_sorted_cpu_model_list();
2369 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
2374 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2375 bool migratable_only
)
2377 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2380 if (kvm_enabled()) {
2381 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
2384 } else if (tcg_enabled()) {
2385 r
= wi
->tcg_features
;
2389 if (migratable_only
) {
2390 r
&= x86_cpu_get_migratable_flags(w
);
2395 static void x86_cpu_report_filtered_features(X86CPU
*cpu
)
2399 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2400 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
2404 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
2407 for (pv
= props
; pv
->prop
; pv
++) {
2411 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
2416 /* Load data from X86CPUDefinition into a X86CPU object
2418 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
2420 CPUX86State
*env
= &cpu
->env
;
2422 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
2425 /*NOTE: any property set by this function should be returned by
2426 * x86_cpu_static_props(), so static expansion of
2427 * query-cpu-model-expansion is always complete.
2430 /* CPU models only set _minimum_ values for level/xlevel: */
2431 object_property_set_uint(OBJECT(cpu
), def
->level
, "min-level", errp
);
2432 object_property_set_uint(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
2434 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
2435 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
2436 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
2437 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
2438 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2439 env
->features
[w
] = def
->features
[w
];
2442 /* Special cases not set in the X86CPUDefinition structs: */
2443 if (kvm_enabled()) {
2444 if (!kvm_irqchip_in_kernel()) {
2445 x86_cpu_change_kvm_default("x2apic", "off");
2448 x86_cpu_apply_props(cpu
, kvm_default_props
);
2449 } else if (tcg_enabled()) {
2450 x86_cpu_apply_props(cpu
, tcg_default_props
);
2453 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2455 /* sysenter isn't supported in compatibility mode on AMD,
2456 * syscall isn't supported in compatibility mode on Intel.
2457 * Normally we advertise the actual CPU vendor, but you can
2458 * override this using the 'vendor' property if you want to use
2459 * KVM's sysenter/syscall emulation in compatibility mode and
2460 * when doing cross vendor migration
2462 vendor
= def
->vendor
;
2463 if (kvm_enabled()) {
2464 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2465 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2466 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2467 vendor
= host_vendor
;
2470 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2474 /* Return a QDict containing keys for all properties that can be included
2475 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2476 * must be included in the dictionary.
2478 static QDict
*x86_cpu_static_props(void)
2482 static const char *props
[] = {
2500 for (i
= 0; props
[i
]; i
++) {
2501 qdict_put_null(d
, props
[i
]);
2504 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2505 FeatureWordInfo
*fi
= &feature_word_info
[w
];
2507 for (bit
= 0; bit
< 32; bit
++) {
2508 if (!fi
->feat_names
[bit
]) {
2511 qdict_put_null(d
, fi
->feat_names
[bit
]);
2518 /* Add an entry to @props dict, with the value for property. */
2519 static void x86_cpu_expand_prop(X86CPU
*cpu
, QDict
*props
, const char *prop
)
2521 QObject
*value
= object_property_get_qobject(OBJECT(cpu
), prop
,
2524 qdict_put_obj(props
, prop
, value
);
2527 /* Convert CPU model data from X86CPU object to a property dictionary
2528 * that can recreate exactly the same CPU model.
2530 static void x86_cpu_to_dict(X86CPU
*cpu
, QDict
*props
)
2532 QDict
*sprops
= x86_cpu_static_props();
2533 const QDictEntry
*e
;
2535 for (e
= qdict_first(sprops
); e
; e
= qdict_next(sprops
, e
)) {
2536 const char *prop
= qdict_entry_key(e
);
2537 x86_cpu_expand_prop(cpu
, props
, prop
);
2541 /* Convert CPU model data from X86CPU object to a property dictionary
2542 * that can recreate exactly the same CPU model, including every
2543 * writeable QOM property.
2545 static void x86_cpu_to_dict_full(X86CPU
*cpu
, QDict
*props
)
2547 ObjectPropertyIterator iter
;
2548 ObjectProperty
*prop
;
2550 object_property_iter_init(&iter
, OBJECT(cpu
));
2551 while ((prop
= object_property_iter_next(&iter
))) {
2552 /* skip read-only or write-only properties */
2553 if (!prop
->get
|| !prop
->set
) {
2557 /* "hotplugged" is the only property that is configurable
2558 * on the command-line but will be set differently on CPUs
2559 * created using "-cpu ... -smp ..." and by CPUs created
2560 * on the fly by x86_cpu_from_model() for querying. Skip it.
2562 if (!strcmp(prop
->name
, "hotplugged")) {
2565 x86_cpu_expand_prop(cpu
, props
, prop
->name
);
2569 static void object_apply_props(Object
*obj
, QDict
*props
, Error
**errp
)
2571 const QDictEntry
*prop
;
2574 for (prop
= qdict_first(props
); prop
; prop
= qdict_next(props
, prop
)) {
2575 object_property_set_qobject(obj
, qdict_entry_value(prop
),
2576 qdict_entry_key(prop
), &err
);
2582 error_propagate(errp
, err
);
2585 /* Create X86CPU object according to model+props specification */
2586 static X86CPU
*x86_cpu_from_model(const char *model
, QDict
*props
, Error
**errp
)
2592 xcc
= X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU
, model
));
2594 error_setg(&err
, "CPU model '%s' not found", model
);
2598 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
2600 object_apply_props(OBJECT(xc
), props
, &err
);
2606 x86_cpu_expand_features(xc
, &err
);
2613 error_propagate(errp
, err
);
2614 object_unref(OBJECT(xc
));
2620 CpuModelExpansionInfo
*
2621 arch_query_cpu_model_expansion(CpuModelExpansionType type
,
2622 CpuModelInfo
*model
,
2627 CpuModelExpansionInfo
*ret
= g_new0(CpuModelExpansionInfo
, 1);
2628 QDict
*props
= NULL
;
2629 const char *base_name
;
2631 xc
= x86_cpu_from_model(model
->name
,
2633 qobject_to_qdict(model
->props
) :
2639 props
= qdict_new();
2642 case CPU_MODEL_EXPANSION_TYPE_STATIC
:
2643 /* Static expansion will be based on "base" only */
2645 x86_cpu_to_dict(xc
, props
);
2647 case CPU_MODEL_EXPANSION_TYPE_FULL
:
2648 /* As we don't return every single property, full expansion needs
2649 * to keep the original model name+props, and add extra
2650 * properties on top of that.
2652 base_name
= model
->name
;
2653 x86_cpu_to_dict_full(xc
, props
);
2656 error_setg(&err
, "Unsupportted expansion type");
2661 props
= qdict_new();
2663 x86_cpu_to_dict(xc
, props
);
2665 ret
->model
= g_new0(CpuModelInfo
, 1);
2666 ret
->model
->name
= g_strdup(base_name
);
2667 ret
->model
->props
= QOBJECT(props
);
2668 ret
->model
->has_props
= true;
2671 object_unref(OBJECT(xc
));
2673 error_propagate(errp
, err
);
2674 qapi_free_CpuModelExpansionInfo(ret
);
2680 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
2682 #ifdef TARGET_X86_64
2683 return g_strdup("i386:x86-64");
2685 return g_strdup("i386");
2689 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
2691 X86CPUDefinition
*cpudef
= data
;
2692 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2694 xcc
->cpu_def
= cpudef
;
2695 xcc
->migration_safe
= true;
2698 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
2700 char *typename
= x86_cpu_type_name(def
->name
);
2703 .parent
= TYPE_X86_CPU
,
2704 .class_init
= x86_cpu_cpudef_class_init
,
2708 /* AMD aliases are handled at runtime based on CPUID vendor, so
2709 * they shouldn't be set on the CPU model table.
2711 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
2717 #if !defined(CONFIG_USER_ONLY)
2719 void cpu_clear_apic_feature(CPUX86State
*env
)
2721 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
2724 #endif /* !CONFIG_USER_ONLY */
2726 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2727 uint32_t *eax
, uint32_t *ebx
,
2728 uint32_t *ecx
, uint32_t *edx
)
2730 X86CPU
*cpu
= x86_env_get_cpu(env
);
2731 CPUState
*cs
= CPU(cpu
);
2732 uint32_t pkg_offset
;
2734 uint32_t signature
[3];
2736 /* Calculate & apply limits for different index ranges */
2737 if (index
>= 0xC0000000) {
2738 limit
= env
->cpuid_xlevel2
;
2739 } else if (index
>= 0x80000000) {
2740 limit
= env
->cpuid_xlevel
;
2741 } else if (index
>= 0x40000000) {
2744 limit
= env
->cpuid_level
;
2747 if (index
> limit
) {
2748 /* Intel documentation states that invalid EAX input will
2749 * return the same information as EAX=cpuid_level
2750 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2752 index
= env
->cpuid_level
;
2757 *eax
= env
->cpuid_level
;
2758 *ebx
= env
->cpuid_vendor1
;
2759 *edx
= env
->cpuid_vendor2
;
2760 *ecx
= env
->cpuid_vendor3
;
2763 *eax
= env
->cpuid_version
;
2764 *ebx
= (cpu
->apic_id
<< 24) |
2765 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2766 *ecx
= env
->features
[FEAT_1_ECX
];
2767 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
2768 *ecx
|= CPUID_EXT_OSXSAVE
;
2770 *edx
= env
->features
[FEAT_1_EDX
];
2771 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2772 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2777 /* cache info: needed for Pentium Pro compatibility */
2778 if (cpu
->cache_info_passthrough
) {
2779 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2782 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2784 if (!cpu
->enable_l3_cache
) {
2787 *ecx
= L3_N_DESCRIPTOR
;
2789 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2790 (L1I_DESCRIPTOR
<< 8) | \
2794 /* cache info: needed for Core compatibility */
2795 if (cpu
->cache_info_passthrough
) {
2796 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2797 *eax
&= ~0xFC000000;
2801 case 0: /* L1 dcache info */
2802 *eax
|= CPUID_4_TYPE_DCACHE
| \
2803 CPUID_4_LEVEL(1) | \
2804 CPUID_4_SELF_INIT_LEVEL
;
2805 *ebx
= (L1D_LINE_SIZE
- 1) | \
2806 ((L1D_PARTITIONS
- 1) << 12) | \
2807 ((L1D_ASSOCIATIVITY
- 1) << 22);
2808 *ecx
= L1D_SETS
- 1;
2809 *edx
= CPUID_4_NO_INVD_SHARING
;
2811 case 1: /* L1 icache info */
2812 *eax
|= CPUID_4_TYPE_ICACHE
| \
2813 CPUID_4_LEVEL(1) | \
2814 CPUID_4_SELF_INIT_LEVEL
;
2815 *ebx
= (L1I_LINE_SIZE
- 1) | \
2816 ((L1I_PARTITIONS
- 1) << 12) | \
2817 ((L1I_ASSOCIATIVITY
- 1) << 22);
2818 *ecx
= L1I_SETS
- 1;
2819 *edx
= CPUID_4_NO_INVD_SHARING
;
2821 case 2: /* L2 cache info */
2822 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2823 CPUID_4_LEVEL(2) | \
2824 CPUID_4_SELF_INIT_LEVEL
;
2825 if (cs
->nr_threads
> 1) {
2826 *eax
|= (cs
->nr_threads
- 1) << 14;
2828 *ebx
= (L2_LINE_SIZE
- 1) | \
2829 ((L2_PARTITIONS
- 1) << 12) | \
2830 ((L2_ASSOCIATIVITY
- 1) << 22);
2832 *edx
= CPUID_4_NO_INVD_SHARING
;
2834 case 3: /* L3 cache info */
2835 if (!cpu
->enable_l3_cache
) {
2842 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2843 CPUID_4_LEVEL(3) | \
2844 CPUID_4_SELF_INIT_LEVEL
;
2845 pkg_offset
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
2846 *eax
|= ((1 << pkg_offset
) - 1) << 14;
2847 *ebx
= (L3_N_LINE_SIZE
- 1) | \
2848 ((L3_N_PARTITIONS
- 1) << 12) | \
2849 ((L3_N_ASSOCIATIVITY
- 1) << 22);
2850 *ecx
= L3_N_SETS
- 1;
2851 *edx
= CPUID_4_INCLUSIVE
| CPUID_4_COMPLEX_IDX
;
2853 default: /* end of info */
2862 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2863 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2864 *eax
|= (cs
->nr_cores
- 1) << 26;
2868 /* mwait info: needed for Core compatibility */
2869 *eax
= 0; /* Smallest monitor-line size in bytes */
2870 *ebx
= 0; /* Largest monitor-line size in bytes */
2871 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2875 /* Thermal and Power Leaf */
2876 *eax
= env
->features
[FEAT_6_EAX
];
2882 /* Structured Extended Feature Flags Enumeration Leaf */
2884 *eax
= 0; /* Maximum ECX value for sub-leaves */
2885 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2886 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
2887 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
2888 *ecx
|= CPUID_7_0_ECX_OSPKE
;
2890 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
2899 /* Direct Cache Access Information Leaf */
2900 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2906 /* Architectural Performance Monitoring Leaf */
2907 if (kvm_enabled() && cpu
->enable_pmu
) {
2908 KVMState
*s
= cs
->kvm_state
;
2910 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2911 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2912 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2913 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2922 /* Extended Topology Enumeration Leaf */
2923 if (!cpu
->enable_cpuid_0xb
) {
2924 *eax
= *ebx
= *ecx
= *edx
= 0;
2928 *ecx
= count
& 0xff;
2929 *edx
= cpu
->apic_id
;
2933 *eax
= apicid_core_offset(cs
->nr_cores
, cs
->nr_threads
);
2934 *ebx
= cs
->nr_threads
;
2935 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
2938 *eax
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
2939 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
2940 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
2945 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
2948 assert(!(*eax
& ~0x1f));
2949 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
2952 /* Processor Extended State */
2957 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
2962 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
2963 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
2964 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
2966 } else if (count
== 1) {
2967 *eax
= env
->features
[FEAT_XSAVE
];
2968 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
2969 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
2970 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
2979 * CPUID code in kvm_arch_init_vcpu() ignores stuff
2980 * set here, but we restrict to TCG none the less.
2982 if (tcg_enabled() && cpu
->expose_tcg
) {
2983 memcpy(signature
, "TCGTCGTCGTCG", 12);
2985 *ebx
= signature
[0];
2986 *ecx
= signature
[1];
2987 *edx
= signature
[2];
3002 *eax
= env
->cpuid_xlevel
;
3003 *ebx
= env
->cpuid_vendor1
;
3004 *edx
= env
->cpuid_vendor2
;
3005 *ecx
= env
->cpuid_vendor3
;
3008 *eax
= env
->cpuid_version
;
3010 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
3011 *edx
= env
->features
[FEAT_8000_0001_EDX
];
3013 /* The Linux kernel checks for the CMPLegacy bit and
3014 * discards multiple thread information if it is set.
3015 * So don't set it here for Intel to make Linux guests happy.
3017 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3018 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
3019 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
3020 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
3021 *ecx
|= 1 << 1; /* CmpLegacy bit */
3028 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
3029 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
3030 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
3031 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
3034 /* cache info (L1 cache) */
3035 if (cpu
->cache_info_passthrough
) {
3036 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3039 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
3040 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
3041 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
3042 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
3043 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
3044 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
3045 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
3046 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
3049 /* cache info (L2 cache) */
3050 if (cpu
->cache_info_passthrough
) {
3051 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3054 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
3055 (L2_DTLB_2M_ENTRIES
<< 16) | \
3056 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
3057 (L2_ITLB_2M_ENTRIES
);
3058 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
3059 (L2_DTLB_4K_ENTRIES
<< 16) | \
3060 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
3061 (L2_ITLB_4K_ENTRIES
);
3062 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
3063 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
3064 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
3065 if (!cpu
->enable_l3_cache
) {
3066 *edx
= ((L3_SIZE_KB
/ 512) << 18) | \
3067 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
3068 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
3070 *edx
= ((L3_N_SIZE_KB_AMD
/ 512) << 18) | \
3071 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY
) << 12) | \
3072 (L3_N_LINES_PER_TAG
<< 8) | (L3_N_LINE_SIZE
);
3079 *edx
= env
->features
[FEAT_8000_0007_EDX
];
3082 /* virtual & phys address size in low 2 bytes. */
3083 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
3084 /* 64 bit processor */
3085 *eax
= cpu
->phys_bits
; /* configurable physical bits */
3086 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
3087 *eax
|= 0x00003900; /* 57 bits virtual */
3089 *eax
|= 0x00003000; /* 48 bits virtual */
3092 *eax
= cpu
->phys_bits
;
3097 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3098 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
3102 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
3103 *eax
= 0x00000001; /* SVM Revision */
3104 *ebx
= 0x00000010; /* nr of ASIDs */
3106 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
3115 *eax
= env
->cpuid_xlevel2
;
3121 /* Support for VIA CPU's CPUID instruction */
3122 *eax
= env
->cpuid_version
;
3125 *edx
= env
->features
[FEAT_C000_0001_EDX
];
3130 /* Reserved for the future, and now filled with zero */
3137 /* reserved values: zero */
3146 /* CPUClass::reset() */
3147 static void x86_cpu_reset(CPUState
*s
)
3149 X86CPU
*cpu
= X86_CPU(s
);
3150 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
3151 CPUX86State
*env
= &cpu
->env
;
3156 xcc
->parent_reset(s
);
3158 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
3160 env
->old_exception
= -1;
3162 /* init to reset state */
3164 env
->hflags2
|= HF2_GIF_MASK
;
3166 cpu_x86_update_cr0(env
, 0x60000010);
3167 env
->a20_mask
= ~0x0;
3168 env
->smbase
= 0x30000;
3170 env
->idt
.limit
= 0xffff;
3171 env
->gdt
.limit
= 0xffff;
3172 env
->ldt
.limit
= 0xffff;
3173 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
3174 env
->tr
.limit
= 0xffff;
3175 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
3177 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
3178 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
3179 DESC_R_MASK
| DESC_A_MASK
);
3180 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
3181 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3183 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
3184 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3186 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
3187 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3189 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
3190 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3192 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
3193 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3197 env
->regs
[R_EDX
] = env
->cpuid_version
;
3202 for (i
= 0; i
< 8; i
++) {
3205 cpu_set_fpuc(env
, 0x37f);
3207 env
->mxcsr
= 0x1f80;
3208 /* All units are in INIT state. */
3211 env
->pat
= 0x0007040600070406ULL
;
3212 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
3214 memset(env
->dr
, 0, sizeof(env
->dr
));
3215 env
->dr
[6] = DR6_FIXED_1
;
3216 env
->dr
[7] = DR7_FIXED_1
;
3217 cpu_breakpoint_remove_all(s
, BP_CPU
);
3218 cpu_watchpoint_remove_all(s
, BP_CPU
);
3221 xcr0
= XSTATE_FP_MASK
;
3223 #ifdef CONFIG_USER_ONLY
3224 /* Enable all the features for user-mode. */
3225 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
3226 xcr0
|= XSTATE_SSE_MASK
;
3228 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3229 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3230 if (env
->features
[esa
->feature
] & esa
->bits
) {
3235 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
3236 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
3238 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
3239 cr4
|= CR4_FSGSBASE_MASK
;
3244 cpu_x86_update_cr4(env
, cr4
);
3247 * SDM 11.11.5 requires:
3248 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3249 * - IA32_MTRR_PHYSMASKn.V = 0
3250 * All other bits are undefined. For simplification, zero it all.
3252 env
->mtrr_deftype
= 0;
3253 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
3254 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
3256 #if !defined(CONFIG_USER_ONLY)
3257 /* We hard-wire the BSP to the first CPU. */
3258 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
3260 s
->halted
= !cpu_is_bsp(cpu
);
3262 if (kvm_enabled()) {
3263 kvm_arch_reset_vcpu(cpu
);
3268 #ifndef CONFIG_USER_ONLY
3269 bool cpu_is_bsp(X86CPU
*cpu
)
3271 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
3274 /* TODO: remove me, when reset over QOM tree is implemented */
3275 static void x86_cpu_machine_reset_cb(void *opaque
)
3277 X86CPU
*cpu
= opaque
;
3278 cpu_reset(CPU(cpu
));
3282 static void mce_init(X86CPU
*cpu
)
3284 CPUX86State
*cenv
= &cpu
->env
;
3287 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
3288 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
3289 (CPUID_MCE
| CPUID_MCA
)) {
3290 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
3291 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
3292 cenv
->mcg_ctl
= ~(uint64_t)0;
3293 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
3294 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
3299 #ifndef CONFIG_USER_ONLY
3300 APICCommonClass
*apic_get_class(void)
3302 const char *apic_type
= "apic";
3304 if (kvm_apic_in_kernel()) {
3305 apic_type
= "kvm-apic";
3306 } else if (xen_enabled()) {
3307 apic_type
= "xen-apic";
3310 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
3313 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
3315 APICCommonState
*apic
;
3316 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
3318 cpu
->apic_state
= DEVICE(object_new(object_class_get_name(apic_class
)));
3320 object_property_add_child(OBJECT(cpu
), "lapic",
3321 OBJECT(cpu
->apic_state
), &error_abort
);
3322 object_unref(OBJECT(cpu
->apic_state
));
3324 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
3325 /* TODO: convert to link<> */
3326 apic
= APIC_COMMON(cpu
->apic_state
);
3328 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
3331 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3333 APICCommonState
*apic
;
3334 static bool apic_mmio_map_once
;
3336 if (cpu
->apic_state
== NULL
) {
3339 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
3342 /* Map APIC MMIO area */
3343 apic
= APIC_COMMON(cpu
->apic_state
);
3344 if (!apic_mmio_map_once
) {
3345 memory_region_add_subregion_overlap(get_system_memory(),
3347 MSR_IA32_APICBASE_BASE
,
3350 apic_mmio_map_once
= true;
3354 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
3356 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
3357 MemoryRegion
*smram
=
3358 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
3361 cpu
->smram
= g_new(MemoryRegion
, 1);
3362 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
3363 smram
, 0, 1ull << 32);
3364 memory_region_set_enabled(cpu
->smram
, true);
3365 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
3369 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3374 /* Note: Only safe for use on x86(-64) hosts */
3375 static uint32_t x86_host_phys_bits(void)
3378 uint32_t host_phys_bits
;
3380 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
3381 if (eax
>= 0x80000008) {
3382 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
3383 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3384 * at 23:16 that can specify a maximum physical address bits for
3385 * the guest that can override this value; but I've not seen
3386 * anything with that set.
3388 host_phys_bits
= eax
& 0xff;
3390 /* It's an odd 64 bit machine that doesn't have the leaf for
3391 * physical address bits; fall back to 36 that's most older
3394 host_phys_bits
= 36;
3397 return host_phys_bits
;
3400 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
3407 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3408 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
3410 CPUX86State
*env
= &cpu
->env
;
3411 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3412 uint32_t eax
= fi
->cpuid_eax
;
3413 uint32_t region
= eax
& 0xF0000000;
3415 if (!env
->features
[w
]) {
3421 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
3424 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
3427 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
3432 /* Calculate XSAVE components based on the configured CPU feature flags */
3433 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
3435 CPUX86State
*env
= &cpu
->env
;
3439 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
3444 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3445 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3446 if (env
->features
[esa
->feature
] & esa
->bits
) {
3447 mask
|= (1ULL << i
);
3451 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
3452 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
3455 /***** Steps involved on loading and filtering CPUID data
3457 * When initializing and realizing a CPU object, the steps
3458 * involved in setting up CPUID data are:
3460 * 1) Loading CPU model definition (X86CPUDefinition). This is
3461 * implemented by x86_cpu_load_def() and should be completely
3462 * transparent, as it is done automatically by instance_init.
3463 * No code should need to look at X86CPUDefinition structs
3464 * outside instance_init.
3466 * 2) CPU expansion. This is done by realize before CPUID
3467 * filtering, and will make sure host/accelerator data is
3468 * loaded for CPU models that depend on host capabilities
3469 * (e.g. "host"). Done by x86_cpu_expand_features().
3471 * 3) CPUID filtering. This initializes extra data related to
3472 * CPUID, and checks if the host supports all capabilities
3473 * required by the CPU. Runnability of a CPU model is
3474 * determined at this step. Done by x86_cpu_filter_features().
3476 * Some operations don't require all steps to be performed.
3479 * - CPU instance creation (instance_init) will run only CPU
3480 * model loading. CPU expansion can't run at instance_init-time
3481 * because host/accelerator data may be not available yet.
3482 * - CPU realization will perform both CPU model expansion and CPUID
3483 * filtering, and return an error in case one of them fails.
3484 * - query-cpu-definitions needs to run all 3 steps. It needs
3485 * to run CPUID filtering, as the 'unavailable-features'
3486 * field is set based on the filtering results.
3487 * - The query-cpu-model-expansion QMP command only needs to run
3488 * CPU model loading and CPU expansion. It should not filter
3489 * any CPUID data based on host capabilities.
3492 /* Expand CPU configuration data, based on configured features
3493 * and host/accelerator capabilities when appropriate.
3495 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
3497 CPUX86State
*env
= &cpu
->env
;
3500 Error
*local_err
= NULL
;
3502 /*TODO: Now cpu->max_features doesn't overwrite features
3503 * set using QOM properties, and we can convert
3504 * plus_features & minus_features to global properties
3505 * inside x86_cpu_parse_featurestr() too.
3507 if (cpu
->max_features
) {
3508 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3509 /* Override only features that weren't set explicitly
3513 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
3514 ~env
->user_features
[w
];
3518 for (l
= plus_features
; l
; l
= l
->next
) {
3519 const char *prop
= l
->data
;
3520 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
3526 for (l
= minus_features
; l
; l
= l
->next
) {
3527 const char *prop
= l
->data
;
3528 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
3534 if (!kvm_enabled() || !cpu
->expose_kvm
) {
3535 env
->features
[FEAT_KVM
] = 0;
3538 x86_cpu_enable_xsave_components(cpu
);
3540 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3541 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
3542 if (cpu
->full_cpuid_auto_level
) {
3543 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
3544 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
3545 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
3546 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
3547 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
3548 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
3549 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
3550 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
3551 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
3552 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
3553 /* SVM requires CPUID[0x8000000A] */
3554 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
3555 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
3559 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3560 if (env
->cpuid_level
== UINT32_MAX
) {
3561 env
->cpuid_level
= env
->cpuid_min_level
;
3563 if (env
->cpuid_xlevel
== UINT32_MAX
) {
3564 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
3566 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
3567 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
3571 if (local_err
!= NULL
) {
3572 error_propagate(errp
, local_err
);
3577 * Finishes initialization of CPUID data, filters CPU feature
3578 * words based on host availability of each feature.
3580 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
3582 static int x86_cpu_filter_features(X86CPU
*cpu
)
3584 CPUX86State
*env
= &cpu
->env
;
3588 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3589 uint32_t host_feat
=
3590 x86_cpu_get_supported_feature_word(w
, false);
3591 uint32_t requested_features
= env
->features
[w
];
3592 env
->features
[w
] &= host_feat
;
3593 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
3594 if (cpu
->filtered_features
[w
]) {
3602 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3603 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3604 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3605 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3606 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3607 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3608 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
3610 CPUState
*cs
= CPU(dev
);
3611 X86CPU
*cpu
= X86_CPU(dev
);
3612 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
3613 CPUX86State
*env
= &cpu
->env
;
3614 Error
*local_err
= NULL
;
3615 static bool ht_warned
;
3617 if (xcc
->kvm_required
&& !kvm_enabled()) {
3618 char *name
= x86_cpu_class_get_model_name(xcc
);
3619 error_setg(&local_err
, "CPU model '%s' requires KVM", name
);
3624 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
3625 error_setg(errp
, "apic-id property was not initialized properly");
3629 x86_cpu_expand_features(cpu
, &local_err
);
3634 if (x86_cpu_filter_features(cpu
) &&
3635 (cpu
->check_cpuid
|| cpu
->enforce_cpuid
)) {
3636 x86_cpu_report_filtered_features(cpu
);
3637 if (cpu
->enforce_cpuid
) {
3638 error_setg(&local_err
,
3640 "Host doesn't support requested features" :
3641 "TCG doesn't support requested features");
3646 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3649 if (IS_AMD_CPU(env
)) {
3650 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
3651 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
3652 & CPUID_EXT2_AMD_ALIASES
);
3655 /* For 64bit systems think about the number of physical bits to present.
3656 * ideally this should be the same as the host; anything other than matching
3657 * the host can cause incorrect guest behaviour.
3658 * QEMU used to pick the magic value of 40 bits that corresponds to
3659 * consumer AMD devices but nothing else.
3661 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
3662 if (kvm_enabled()) {
3663 uint32_t host_phys_bits
= x86_host_phys_bits();
3666 if (cpu
->host_phys_bits
) {
3667 /* The user asked for us to use the host physical bits */
3668 cpu
->phys_bits
= host_phys_bits
;
3671 /* Print a warning if the user set it to a value that's not the
3674 if (cpu
->phys_bits
!= host_phys_bits
&& cpu
->phys_bits
!= 0 &&
3676 warn_report("Host physical bits (%u)"
3677 " does not match phys-bits property (%u)",
3678 host_phys_bits
, cpu
->phys_bits
);
3682 if (cpu
->phys_bits
&&
3683 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
3684 cpu
->phys_bits
< 32)) {
3685 error_setg(errp
, "phys-bits should be between 32 and %u "
3687 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
3691 if (cpu
->phys_bits
&& cpu
->phys_bits
!= TCG_PHYS_ADDR_BITS
) {
3692 error_setg(errp
, "TCG only supports phys-bits=%u",
3693 TCG_PHYS_ADDR_BITS
);
3697 /* 0 means it was not explicitly set by the user (or by machine
3698 * compat_props or by the host code above). In this case, the default
3699 * is the value used by TCG (40).
3701 if (cpu
->phys_bits
== 0) {
3702 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
3705 /* For 32 bit systems don't use the user set value, but keep
3706 * phys_bits consistent with what we tell the guest.
3708 if (cpu
->phys_bits
!= 0) {
3709 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
3713 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
3714 cpu
->phys_bits
= 36;
3716 cpu
->phys_bits
= 32;
3719 cpu_exec_realizefn(cs
, &local_err
);
3720 if (local_err
!= NULL
) {
3721 error_propagate(errp
, local_err
);
3725 if (tcg_enabled()) {
3729 #ifndef CONFIG_USER_ONLY
3730 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
3732 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
3733 x86_cpu_apic_create(cpu
, &local_err
);
3734 if (local_err
!= NULL
) {
3742 #ifndef CONFIG_USER_ONLY
3743 if (tcg_enabled()) {
3744 AddressSpace
*as_normal
= address_space_init_shareable(cs
->memory
,
3746 AddressSpace
*as_smm
= g_new(AddressSpace
, 1);
3748 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
3749 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
3751 /* Outer container... */
3752 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
3753 memory_region_set_enabled(cpu
->cpu_as_root
, true);
3755 /* ... with two regions inside: normal system memory with low
3758 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
3759 get_system_memory(), 0, ~0ull);
3760 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
3761 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
3762 address_space_init(as_smm
, cpu
->cpu_as_root
, "CPU");
3765 cpu_address_space_init(cs
, as_normal
, 0);
3766 cpu_address_space_init(cs
, as_smm
, 1);
3768 /* ... SMRAM with higher priority, linked from /machine/smram. */
3769 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
3770 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
3776 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3777 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3778 * based on inputs (sockets,cores,threads), it is still better to gives
3781 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3782 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3784 if (!IS_INTEL_CPU(env
) && cs
->nr_threads
> 1 && !ht_warned
) {
3785 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3786 " -smp options properly.");
3790 x86_cpu_apic_realize(cpu
, &local_err
);
3791 if (local_err
!= NULL
) {
3796 xcc
->parent_realize(dev
, &local_err
);
3799 if (local_err
!= NULL
) {
3800 error_propagate(errp
, local_err
);
3805 static void x86_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
3807 X86CPU
*cpu
= X86_CPU(dev
);
3808 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
3809 Error
*local_err
= NULL
;
3811 #ifndef CONFIG_USER_ONLY
3812 cpu_remove_sync(CPU(dev
));
3813 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
3816 if (cpu
->apic_state
) {
3817 object_unparent(OBJECT(cpu
->apic_state
));
3818 cpu
->apic_state
= NULL
;
3821 xcc
->parent_unrealize(dev
, &local_err
);
3822 if (local_err
!= NULL
) {
3823 error_propagate(errp
, local_err
);
3828 typedef struct BitProperty
{
3833 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
3834 void *opaque
, Error
**errp
)
3836 X86CPU
*cpu
= X86_CPU(obj
);
3837 BitProperty
*fp
= opaque
;
3838 uint32_t f
= cpu
->env
.features
[fp
->w
];
3839 bool value
= (f
& fp
->mask
) == fp
->mask
;
3840 visit_type_bool(v
, name
, &value
, errp
);
3843 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
3844 void *opaque
, Error
**errp
)
3846 DeviceState
*dev
= DEVICE(obj
);
3847 X86CPU
*cpu
= X86_CPU(obj
);
3848 BitProperty
*fp
= opaque
;
3849 Error
*local_err
= NULL
;
3852 if (dev
->realized
) {
3853 qdev_prop_set_after_realize(dev
, name
, errp
);
3857 visit_type_bool(v
, name
, &value
, &local_err
);
3859 error_propagate(errp
, local_err
);
3864 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
3866 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
3868 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
3871 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
3874 BitProperty
*prop
= opaque
;
3878 /* Register a boolean property to get/set a single bit in a uint32_t field.
3880 * The same property name can be registered multiple times to make it affect
3881 * multiple bits in the same FeatureWord. In that case, the getter will return
3882 * true only if all bits are set.
3884 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
3885 const char *prop_name
,
3891 uint32_t mask
= (1UL << bitnr
);
3893 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
3899 fp
= g_new0(BitProperty
, 1);
3902 object_property_add(OBJECT(cpu
), prop_name
, "bool",
3903 x86_cpu_get_bit_prop
,
3904 x86_cpu_set_bit_prop
,
3905 x86_cpu_release_bit_prop
, fp
, &error_abort
);
3909 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
3913 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3914 const char *name
= fi
->feat_names
[bitnr
];
3920 /* Property names should use "-" instead of "_".
3921 * Old names containing underscores are registered as aliases
3922 * using object_property_add_alias()
3924 assert(!strchr(name
, '_'));
3925 /* aliases don't use "|" delimiters anymore, they are registered
3926 * manually using object_property_add_alias() */
3927 assert(!strchr(name
, '|'));
3928 x86_cpu_register_bit_prop(cpu
, name
, w
, bitnr
);
3931 static GuestPanicInformation
*x86_cpu_get_crash_info(CPUState
*cs
)
3933 X86CPU
*cpu
= X86_CPU(cs
);
3934 CPUX86State
*env
= &cpu
->env
;
3935 GuestPanicInformation
*panic_info
= NULL
;
3937 if (env
->features
[FEAT_HYPERV_EDX
] & HV_X64_GUEST_CRASH_MSR_AVAILABLE
) {
3938 panic_info
= g_malloc0(sizeof(GuestPanicInformation
));
3940 panic_info
->type
= GUEST_PANIC_INFORMATION_TYPE_HYPER_V
;
3942 assert(HV_X64_MSR_CRASH_PARAMS
>= 5);
3943 panic_info
->u
.hyper_v
.arg1
= env
->msr_hv_crash_params
[0];
3944 panic_info
->u
.hyper_v
.arg2
= env
->msr_hv_crash_params
[1];
3945 panic_info
->u
.hyper_v
.arg3
= env
->msr_hv_crash_params
[2];
3946 panic_info
->u
.hyper_v
.arg4
= env
->msr_hv_crash_params
[3];
3947 panic_info
->u
.hyper_v
.arg5
= env
->msr_hv_crash_params
[4];
3952 static void x86_cpu_get_crash_info_qom(Object
*obj
, Visitor
*v
,
3953 const char *name
, void *opaque
,
3956 CPUState
*cs
= CPU(obj
);
3957 GuestPanicInformation
*panic_info
;
3959 if (!cs
->crash_occurred
) {
3960 error_setg(errp
, "No crash occured");
3964 panic_info
= x86_cpu_get_crash_info(cs
);
3965 if (panic_info
== NULL
) {
3966 error_setg(errp
, "No crash information");
3970 visit_type_GuestPanicInformation(v
, "crash-information", &panic_info
,
3972 qapi_free_GuestPanicInformation(panic_info
);
3975 static void x86_cpu_initfn(Object
*obj
)
3977 CPUState
*cs
= CPU(obj
);
3978 X86CPU
*cpu
= X86_CPU(obj
);
3979 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
3980 CPUX86State
*env
= &cpu
->env
;
3985 object_property_add(obj
, "family", "int",
3986 x86_cpuid_version_get_family
,
3987 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
3988 object_property_add(obj
, "model", "int",
3989 x86_cpuid_version_get_model
,
3990 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
3991 object_property_add(obj
, "stepping", "int",
3992 x86_cpuid_version_get_stepping
,
3993 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
3994 object_property_add_str(obj
, "vendor",
3995 x86_cpuid_get_vendor
,
3996 x86_cpuid_set_vendor
, NULL
);
3997 object_property_add_str(obj
, "model-id",
3998 x86_cpuid_get_model_id
,
3999 x86_cpuid_set_model_id
, NULL
);
4000 object_property_add(obj
, "tsc-frequency", "int",
4001 x86_cpuid_get_tsc_freq
,
4002 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
4003 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
4004 x86_cpu_get_feature_words
,
4005 NULL
, NULL
, (void *)env
->features
, NULL
);
4006 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
4007 x86_cpu_get_feature_words
,
4008 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
4010 object_property_add(obj
, "crash-information", "GuestPanicInformation",
4011 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
, NULL
);
4013 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
4015 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4018 for (bitnr
= 0; bitnr
< 32; bitnr
++) {
4019 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
4023 object_property_add_alias(obj
, "sse3", obj
, "pni", &error_abort
);
4024 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq", &error_abort
);
4025 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1", &error_abort
);
4026 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2", &error_abort
);
4027 object_property_add_alias(obj
, "xd", obj
, "nx", &error_abort
);
4028 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt", &error_abort
);
4029 object_property_add_alias(obj
, "i64", obj
, "lm", &error_abort
);
4031 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl", &error_abort
);
4032 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust", &error_abort
);
4033 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt", &error_abort
);
4034 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm", &error_abort
);
4035 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy", &error_abort
);
4036 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr", &error_abort
);
4037 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core", &error_abort
);
4038 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb", &error_abort
);
4039 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay", &error_abort
);
4040 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu", &error_abort
);
4041 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf", &error_abort
);
4042 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time", &error_abort
);
4043 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi", &error_abort
);
4044 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt", &error_abort
);
4045 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock", &error_abort
);
4046 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save", &error_abort
);
4047 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale", &error_abort
);
4048 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean", &error_abort
);
4049 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter", &error_abort
);
4050 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1", &error_abort
);
4051 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2", &error_abort
);
4054 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
4058 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
4060 X86CPU
*cpu
= X86_CPU(cs
);
4062 return cpu
->apic_id
;
4065 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
4067 X86CPU
*cpu
= X86_CPU(cs
);
4069 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
4072 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
4074 X86CPU
*cpu
= X86_CPU(cs
);
4076 cpu
->env
.eip
= value
;
4079 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
4081 X86CPU
*cpu
= X86_CPU(cs
);
4083 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
4086 static bool x86_cpu_has_work(CPUState
*cs
)
4088 X86CPU
*cpu
= X86_CPU(cs
);
4089 CPUX86State
*env
= &cpu
->env
;
4091 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
4092 CPU_INTERRUPT_POLL
)) &&
4093 (env
->eflags
& IF_MASK
)) ||
4094 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
4095 CPU_INTERRUPT_INIT
|
4096 CPU_INTERRUPT_SIPI
|
4097 CPU_INTERRUPT_MCE
)) ||
4098 ((cs
->interrupt_request
& CPU_INTERRUPT_SMI
) &&
4099 !(env
->hflags
& HF_SMM_MASK
));
4102 static Property x86_cpu_properties
[] = {
4103 #ifdef CONFIG_USER_ONLY
4104 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4105 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
4106 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
4107 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
4108 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
4110 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
4111 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
4112 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
4113 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
4115 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
4116 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
4117 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
4118 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
4119 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
4120 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
4121 DEFINE_PROP_BOOL("hv-crash", X86CPU
, hyperv_crash
, false),
4122 DEFINE_PROP_BOOL("hv-reset", X86CPU
, hyperv_reset
, false),
4123 DEFINE_PROP_BOOL("hv-vpindex", X86CPU
, hyperv_vpindex
, false),
4124 DEFINE_PROP_BOOL("hv-runtime", X86CPU
, hyperv_runtime
, false),
4125 DEFINE_PROP_BOOL("hv-synic", X86CPU
, hyperv_synic
, false),
4126 DEFINE_PROP_BOOL("hv-stimer", X86CPU
, hyperv_stimer
, false),
4127 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
4128 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
4129 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
4130 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
4131 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
4132 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
4133 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
4134 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
4135 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
4136 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
4137 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
4138 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
4139 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
4140 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
4141 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
4142 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
4143 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
4144 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
4146 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
4147 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
4150 * From "Requirements for Implementing the Microsoft
4151 * Hypervisor Interface":
4152 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
4154 * "Starting with Windows Server 2012 and Windows 8, if
4155 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
4156 * the hypervisor imposes no specific limit to the number of VPs.
4157 * In this case, Windows Server 2012 guest VMs may use more than
4158 * 64 VPs, up to the maximum supported number of processors applicable
4159 * to the specific Windows version being used."
4161 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
4162 DEFINE_PROP_END_OF_LIST()
4165 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
4167 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4168 CPUClass
*cc
= CPU_CLASS(oc
);
4169 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4171 xcc
->parent_realize
= dc
->realize
;
4172 xcc
->parent_unrealize
= dc
->unrealize
;
4173 dc
->realize
= x86_cpu_realizefn
;
4174 dc
->unrealize
= x86_cpu_unrealizefn
;
4175 dc
->props
= x86_cpu_properties
;
4177 xcc
->parent_reset
= cc
->reset
;
4178 cc
->reset
= x86_cpu_reset
;
4179 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
4181 cc
->class_by_name
= x86_cpu_class_by_name
;
4182 cc
->parse_features
= x86_cpu_parse_featurestr
;
4183 cc
->has_work
= x86_cpu_has_work
;
4185 cc
->do_interrupt
= x86_cpu_do_interrupt
;
4186 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
4188 cc
->dump_state
= x86_cpu_dump_state
;
4189 cc
->get_crash_info
= x86_cpu_get_crash_info
;
4190 cc
->set_pc
= x86_cpu_set_pc
;
4191 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
4192 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
4193 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
4194 cc
->get_arch_id
= x86_cpu_get_arch_id
;
4195 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
4196 #ifdef CONFIG_USER_ONLY
4197 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
4199 cc
->asidx_from_attrs
= x86_asidx_from_attrs
;
4200 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
4201 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
4202 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
4203 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
4204 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
4205 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
4206 cc
->vmsd
= &vmstate_x86_cpu
;
4208 cc
->gdb_arch_name
= x86_gdb_arch_name
;
4209 #ifdef TARGET_X86_64
4210 cc
->gdb_core_xml_file
= "i386-64bit.xml";
4211 cc
->gdb_num_core_regs
= 57;
4213 cc
->gdb_core_xml_file
= "i386-32bit.xml";
4214 cc
->gdb_num_core_regs
= 41;
4216 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
4217 cc
->debug_excp_handler
= breakpoint_handler
;
4219 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
4220 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
4222 dc
->user_creatable
= true;
4225 static const TypeInfo x86_cpu_type_info
= {
4226 .name
= TYPE_X86_CPU
,
4228 .instance_size
= sizeof(X86CPU
),
4229 .instance_init
= x86_cpu_initfn
,
4231 .class_size
= sizeof(X86CPUClass
),
4232 .class_init
= x86_cpu_common_class_init
,
4236 /* "base" CPU model, used by query-cpu-model-expansion */
4237 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
4239 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4241 xcc
->static_model
= true;
4242 xcc
->migration_safe
= true;
4243 xcc
->model_description
= "base CPU model type with no features enabled";
4247 static const TypeInfo x86_base_cpu_type_info
= {
4248 .name
= X86_CPU_TYPE_NAME("base"),
4249 .parent
= TYPE_X86_CPU
,
4250 .class_init
= x86_cpu_base_class_init
,
4253 static void x86_cpu_register_types(void)
4257 type_register_static(&x86_cpu_type_info
);
4258 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
4259 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
4261 type_register_static(&max_x86_cpu_type_info
);
4262 type_register_static(&x86_base_cpu_type_info
);
4264 type_register_static(&host_x86_cpu_type_info
);
4268 type_init(x86_cpu_register_types
)