2 * i386 CPUID, CPU class, definitions, models
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/qemu-print.h"
24 #include "qemu/hw-version.h"
26 #include "tcg/helper-tcg.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/hvf.h"
29 #include "kvm/kvm_i386.h"
31 #include "qapi/error.h"
32 #include "qemu/error-report.h"
33 #include "qapi/qapi-visit-machine.h"
34 #include "qapi/qmp/qerror.h"
35 #include "standard-headers/asm-x86/kvm_para.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/i386/topology.h"
38 #ifndef CONFIG_USER_ONLY
39 #include "qapi/qapi-commands-machine-target.h"
40 #include "exec/address-spaces.h"
41 #include "hw/boards.h"
42 #include "hw/i386/sgx-epc.h"
45 #include "disas/capstone.h"
46 #include "cpu-internal.h"
48 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
);
50 /* Helpers for building CPUID[2] descriptors: */
52 struct CPUID2CacheDescriptorInfo
{
61 * Known CPUID 2 cache descriptors.
62 * From Intel SDM Volume 2A, CPUID instruction
64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors
[] = {
65 [0x06] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 8 * KiB
,
66 .associativity
= 4, .line_size
= 32, },
67 [0x08] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 16 * KiB
,
68 .associativity
= 4, .line_size
= 32, },
69 [0x09] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
70 .associativity
= 4, .line_size
= 64, },
71 [0x0A] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
72 .associativity
= 2, .line_size
= 32, },
73 [0x0C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
74 .associativity
= 4, .line_size
= 32, },
75 [0x0D] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
76 .associativity
= 4, .line_size
= 64, },
77 [0x0E] = { .level
= 1, .type
= DATA_CACHE
, .size
= 24 * KiB
,
78 .associativity
= 6, .line_size
= 64, },
79 [0x1D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
80 .associativity
= 2, .line_size
= 64, },
81 [0x21] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
82 .associativity
= 8, .line_size
= 64, },
83 /* lines per sector is not supported cpuid2_cache_descriptor(),
84 * so descriptors 0x22, 0x23 are not included
86 [0x24] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
87 .associativity
= 16, .line_size
= 64, },
88 /* lines per sector is not supported cpuid2_cache_descriptor(),
89 * so descriptors 0x25, 0x20 are not included
91 [0x2C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
92 .associativity
= 8, .line_size
= 64, },
93 [0x30] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
94 .associativity
= 8, .line_size
= 64, },
95 [0x41] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
96 .associativity
= 4, .line_size
= 32, },
97 [0x42] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
98 .associativity
= 4, .line_size
= 32, },
99 [0x43] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
100 .associativity
= 4, .line_size
= 32, },
101 [0x44] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
102 .associativity
= 4, .line_size
= 32, },
103 [0x45] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
104 .associativity
= 4, .line_size
= 32, },
105 [0x46] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
106 .associativity
= 4, .line_size
= 64, },
107 [0x47] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
108 .associativity
= 8, .line_size
= 64, },
109 [0x48] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
110 .associativity
= 12, .line_size
= 64, },
111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
112 [0x4A] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
113 .associativity
= 12, .line_size
= 64, },
114 [0x4B] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
115 .associativity
= 16, .line_size
= 64, },
116 [0x4C] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
117 .associativity
= 12, .line_size
= 64, },
118 [0x4D] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 16 * MiB
,
119 .associativity
= 16, .line_size
= 64, },
120 [0x4E] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
121 .associativity
= 24, .line_size
= 64, },
122 [0x60] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
123 .associativity
= 8, .line_size
= 64, },
124 [0x66] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
125 .associativity
= 4, .line_size
= 64, },
126 [0x67] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
127 .associativity
= 4, .line_size
= 64, },
128 [0x68] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
129 .associativity
= 4, .line_size
= 64, },
130 [0x78] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
131 .associativity
= 4, .line_size
= 64, },
132 /* lines per sector is not supported cpuid2_cache_descriptor(),
133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
135 [0x7D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
136 .associativity
= 8, .line_size
= 64, },
137 [0x7F] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
138 .associativity
= 2, .line_size
= 64, },
139 [0x80] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
140 .associativity
= 8, .line_size
= 64, },
141 [0x82] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
142 .associativity
= 8, .line_size
= 32, },
143 [0x83] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
144 .associativity
= 8, .line_size
= 32, },
145 [0x84] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
146 .associativity
= 8, .line_size
= 32, },
147 [0x85] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
148 .associativity
= 8, .line_size
= 32, },
149 [0x86] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
150 .associativity
= 4, .line_size
= 64, },
151 [0x87] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
152 .associativity
= 8, .line_size
= 64, },
153 [0xD0] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
154 .associativity
= 4, .line_size
= 64, },
155 [0xD1] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
156 .associativity
= 4, .line_size
= 64, },
157 [0xD2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
158 .associativity
= 4, .line_size
= 64, },
159 [0xD6] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
160 .associativity
= 8, .line_size
= 64, },
161 [0xD7] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
162 .associativity
= 8, .line_size
= 64, },
163 [0xD8] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
164 .associativity
= 8, .line_size
= 64, },
165 [0xDC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1.5 * MiB
,
166 .associativity
= 12, .line_size
= 64, },
167 [0xDD] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
168 .associativity
= 12, .line_size
= 64, },
169 [0xDE] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
170 .associativity
= 12, .line_size
= 64, },
171 [0xE2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
172 .associativity
= 16, .line_size
= 64, },
173 [0xE3] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
174 .associativity
= 16, .line_size
= 64, },
175 [0xE4] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
176 .associativity
= 16, .line_size
= 64, },
177 [0xEA] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
178 .associativity
= 24, .line_size
= 64, },
179 [0xEB] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 18 * MiB
,
180 .associativity
= 24, .line_size
= 64, },
181 [0xEC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 24 * MiB
,
182 .associativity
= 24, .line_size
= 64, },
186 * "CPUID leaf 2 does not report cache descriptor information,
187 * use CPUID leaf 4 to query cache parameters"
189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
192 * Return a CPUID 2 cache descriptor for a given cache.
193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo
*cache
)
199 assert(cache
->size
> 0);
200 assert(cache
->level
> 0);
201 assert(cache
->line_size
> 0);
202 assert(cache
->associativity
> 0);
203 for (i
= 0; i
< ARRAY_SIZE(cpuid2_cache_descriptors
); i
++) {
204 struct CPUID2CacheDescriptorInfo
*d
= &cpuid2_cache_descriptors
[i
];
205 if (d
->level
== cache
->level
&& d
->type
== cache
->type
&&
206 d
->size
== cache
->size
&& d
->line_size
== cache
->line_size
&&
207 d
->associativity
== cache
->associativity
) {
212 return CACHE_DESCRIPTOR_UNAVAILABLE
;
215 /* CPUID Leaf 4 constants: */
218 #define CACHE_TYPE_D 1
219 #define CACHE_TYPE_I 2
220 #define CACHE_TYPE_UNIFIED 3
222 #define CACHE_LEVEL(l) (l << 5)
224 #define CACHE_SELF_INIT_LEVEL (1 << 8)
227 #define CACHE_NO_INVD_SHARING (1 << 0)
228 #define CACHE_INCLUSIVE (1 << 1)
229 #define CACHE_COMPLEX_IDX (1 << 2)
231 /* Encode CacheType for CPUID[4].EAX */
232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
235 0 /* Invalid value */)
238 /* Encode cache info for CPUID[4] */
239 static void encode_cache_cpuid4(CPUCacheInfo
*cache
,
240 int num_apic_ids
, int num_cores
,
241 uint32_t *eax
, uint32_t *ebx
,
242 uint32_t *ecx
, uint32_t *edx
)
244 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
245 cache
->partitions
* cache
->sets
);
247 assert(num_apic_ids
> 0);
248 *eax
= CACHE_TYPE(cache
->type
) |
249 CACHE_LEVEL(cache
->level
) |
250 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0) |
251 ((num_cores
- 1) << 26) |
252 ((num_apic_ids
- 1) << 14);
254 assert(cache
->line_size
> 0);
255 assert(cache
->partitions
> 0);
256 assert(cache
->associativity
> 0);
257 /* We don't implement fully-associative caches */
258 assert(cache
->associativity
< cache
->sets
);
259 *ebx
= (cache
->line_size
- 1) |
260 ((cache
->partitions
- 1) << 12) |
261 ((cache
->associativity
- 1) << 22);
263 assert(cache
->sets
> 0);
264 *ecx
= cache
->sets
- 1;
266 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
267 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
268 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
271 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
272 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo
*cache
)
274 assert(cache
->size
% 1024 == 0);
275 assert(cache
->lines_per_tag
> 0);
276 assert(cache
->associativity
> 0);
277 assert(cache
->line_size
> 0);
278 return ((cache
->size
/ 1024) << 24) | (cache
->associativity
<< 16) |
279 (cache
->lines_per_tag
<< 8) | (cache
->line_size
);
282 #define ASSOC_FULL 0xFF
284 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
285 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
295 a == ASSOC_FULL ? 0xF : \
296 0 /* invalid value */)
299 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
302 static void encode_cache_cpuid80000006(CPUCacheInfo
*l2
,
304 uint32_t *ecx
, uint32_t *edx
)
306 assert(l2
->size
% 1024 == 0);
307 assert(l2
->associativity
> 0);
308 assert(l2
->lines_per_tag
> 0);
309 assert(l2
->line_size
> 0);
310 *ecx
= ((l2
->size
/ 1024) << 16) |
311 (AMD_ENC_ASSOC(l2
->associativity
) << 12) |
312 (l2
->lines_per_tag
<< 8) | (l2
->line_size
);
315 assert(l3
->size
% (512 * 1024) == 0);
316 assert(l3
->associativity
> 0);
317 assert(l3
->lines_per_tag
> 0);
318 assert(l3
->line_size
> 0);
319 *edx
= ((l3
->size
/ (512 * 1024)) << 18) |
320 (AMD_ENC_ASSOC(l3
->associativity
) << 12) |
321 (l3
->lines_per_tag
<< 8) | (l3
->line_size
);
327 /* Encode cache info for CPUID[8000001D] */
328 static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache
,
329 X86CPUTopoInfo
*topo_info
,
330 uint32_t *eax
, uint32_t *ebx
,
331 uint32_t *ecx
, uint32_t *edx
)
334 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
335 cache
->partitions
* cache
->sets
);
337 *eax
= CACHE_TYPE(cache
->type
) | CACHE_LEVEL(cache
->level
) |
338 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0);
340 /* L3 is shared among multiple cores */
341 if (cache
->level
== 3) {
342 l3_threads
= topo_info
->cores_per_die
* topo_info
->threads_per_core
;
343 *eax
|= (l3_threads
- 1) << 14;
345 *eax
|= ((topo_info
->threads_per_core
- 1) << 14);
348 assert(cache
->line_size
> 0);
349 assert(cache
->partitions
> 0);
350 assert(cache
->associativity
> 0);
351 /* We don't implement fully-associative caches */
352 assert(cache
->associativity
< cache
->sets
);
353 *ebx
= (cache
->line_size
- 1) |
354 ((cache
->partitions
- 1) << 12) |
355 ((cache
->associativity
- 1) << 22);
357 assert(cache
->sets
> 0);
358 *ecx
= cache
->sets
- 1;
360 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
361 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
362 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
365 /* Encode cache info for CPUID[8000001E] */
366 static void encode_topo_cpuid8000001e(X86CPU
*cpu
, X86CPUTopoInfo
*topo_info
,
367 uint32_t *eax
, uint32_t *ebx
,
368 uint32_t *ecx
, uint32_t *edx
)
370 X86CPUTopoIDs topo_ids
;
372 x86_topo_ids_from_apicid(cpu
->apic_id
, topo_info
, &topo_ids
);
377 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
378 * Read-only. Reset: 0000_XXXXh.
379 * See Core::X86::Cpuid::ExtApicId.
380 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
383 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
384 * The number of threads per core is ThreadsPerCore+1.
385 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
387 * NOTE: CoreId is already part of apic_id. Just use it. We can
388 * use all the 8 bits to represent the core_id here.
390 *ebx
= ((topo_info
->threads_per_core
- 1) << 8) | (topo_ids
.core_id
& 0xFF);
393 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
394 * Read-only. Reset: 0000_0XXXh.
395 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
398 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
401 * 000b 1 node per processor.
402 * 001b 2 nodes per processor.
404 * 011b 4 nodes per processor.
405 * 111b-100b Reserved.
406 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
408 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
409 * But users can create more nodes than the actual hardware can
410 * support. To genaralize we can use all the upper 8 bits for nodes.
411 * NodeId is combination of node and socket_id which is already decoded
412 * in apic_id. Just use it by shifting.
414 *ecx
= ((topo_info
->dies_per_pkg
- 1) << 8) |
415 ((cpu
->apic_id
>> apicid_die_offset(topo_info
)) & 0xFF);
421 * Definitions of the hardcoded cache entries we expose:
422 * These are legacy cache values. If there is a need to change any
423 * of these values please use builtin_x86_defs
427 static CPUCacheInfo legacy_l1d_cache
= {
436 .no_invd_sharing
= true,
439 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
440 static CPUCacheInfo legacy_l1d_cache_amd
= {
450 .no_invd_sharing
= true,
453 /* L1 instruction cache: */
454 static CPUCacheInfo legacy_l1i_cache
= {
455 .type
= INSTRUCTION_CACHE
,
463 .no_invd_sharing
= true,
466 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
467 static CPUCacheInfo legacy_l1i_cache_amd
= {
468 .type
= INSTRUCTION_CACHE
,
477 .no_invd_sharing
= true,
480 /* Level 2 unified cache: */
481 static CPUCacheInfo legacy_l2_cache
= {
482 .type
= UNIFIED_CACHE
,
490 .no_invd_sharing
= true,
493 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
494 static CPUCacheInfo legacy_l2_cache_cpuid2
= {
495 .type
= UNIFIED_CACHE
,
503 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
504 static CPUCacheInfo legacy_l2_cache_amd
= {
505 .type
= UNIFIED_CACHE
,
515 /* Level 3 unified cache: */
516 static CPUCacheInfo legacy_l3_cache
= {
517 .type
= UNIFIED_CACHE
,
527 .complex_indexing
= true,
530 /* TLB definitions: */
532 #define L1_DTLB_2M_ASSOC 1
533 #define L1_DTLB_2M_ENTRIES 255
534 #define L1_DTLB_4K_ASSOC 1
535 #define L1_DTLB_4K_ENTRIES 255
537 #define L1_ITLB_2M_ASSOC 1
538 #define L1_ITLB_2M_ENTRIES 255
539 #define L1_ITLB_4K_ASSOC 1
540 #define L1_ITLB_4K_ENTRIES 255
542 #define L2_DTLB_2M_ASSOC 0 /* disabled */
543 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
544 #define L2_DTLB_4K_ASSOC 4
545 #define L2_DTLB_4K_ENTRIES 512
547 #define L2_ITLB_2M_ASSOC 0 /* disabled */
548 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
549 #define L2_ITLB_4K_ASSOC 4
550 #define L2_ITLB_4K_ENTRIES 512
552 /* CPUID Leaf 0x14 constants: */
553 #define INTEL_PT_MAX_SUBLEAF 0x1
555 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
556 * MSR can be accessed;
557 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
558 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
559 * of Intel PT MSRs across warm reset;
560 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
562 #define INTEL_PT_MINIMAL_EBX 0xf
564 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
565 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
567 * bit[01]: ToPA tables can hold any number of output entries, up to the
568 * maximum allowed by the MaskOrTableOffset field of
569 * IA32_RTIT_OUTPUT_MASK_PTRS;
570 * bit[02]: Support Single-Range Output scheme;
572 #define INTEL_PT_MINIMAL_ECX 0x7
573 /* generated packets which contain IP payloads have LIP values */
574 #define INTEL_PT_IP_LIP (1 << 31)
575 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
576 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
577 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
578 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
579 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
581 /* CPUID Leaf 0x1D constants: */
582 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
583 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
584 #define INTEL_AMX_BYTES_PER_TILE 0x400
585 #define INTEL_AMX_BYTES_PER_ROW 0x40
586 #define INTEL_AMX_TILE_MAX_NAMES 0x8
587 #define INTEL_AMX_TILE_MAX_ROWS 0x10
589 /* CPUID Leaf 0x1E constants: */
590 #define INTEL_AMX_TMUL_MAX_K 0x10
591 #define INTEL_AMX_TMUL_MAX_N 0x40
593 void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
594 uint32_t vendor2
, uint32_t vendor3
)
597 for (i
= 0; i
< 4; i
++) {
598 dst
[i
] = vendor1
>> (8 * i
);
599 dst
[i
+ 4] = vendor2
>> (8 * i
);
600 dst
[i
+ 8] = vendor3
>> (8 * i
);
602 dst
[CPUID_VENDOR_SZ
] = '\0';
605 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
606 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
607 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
608 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
609 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
610 CPUID_PSE36 | CPUID_FXSR)
611 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
612 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
613 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
614 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
615 CPUID_PAE | CPUID_SEP | CPUID_APIC)
617 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
618 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
619 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
620 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
621 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
622 /* partly implemented:
623 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
625 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
626 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
627 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
628 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
629 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
630 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
631 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
634 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
635 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
636 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
637 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
640 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
642 #define TCG_EXT2_X86_64_FEATURES 0
645 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
646 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
647 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
648 TCG_EXT2_X86_64_FEATURES)
649 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
650 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A | \
651 CPUID_EXT3_3DNOWPREFETCH)
652 #define TCG_EXT4_FEATURES 0
653 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
654 CPUID_SVM_SVME_ADDR_CHK)
655 #define TCG_KVM_FEATURES 0
656 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
657 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
658 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
659 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
660 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED)
663 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
665 #if defined CONFIG_SOFTMMU || defined CONFIG_LINUX
666 #define TCG_7_0_ECX_RDPID CPUID_7_0_ECX_RDPID
668 #define TCG_7_0_ECX_RDPID 0
670 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
671 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
672 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES | \
675 #define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
676 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
678 #define TCG_7_1_EDX_FEATURES 0
679 #define TCG_APM_FEATURES 0
680 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
681 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
683 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
684 #define TCG_14_0_ECX_FEATURES 0
685 #define TCG_SGX_12_0_EAX_FEATURES 0
686 #define TCG_SGX_12_0_EBX_FEATURES 0
687 #define TCG_SGX_12_1_EAX_FEATURES 0
689 #define TCG_8000_0008_EBX (CPUID_8000_0008_EBX_XSAVEERPTR | \
690 CPUID_8000_0008_EBX_WBNOINVD)
692 FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
694 .type
= CPUID_FEATURE_WORD
,
696 "fpu", "vme", "de", "pse",
697 "tsc", "msr", "pae", "mce",
698 "cx8", "apic", NULL
, "sep",
699 "mtrr", "pge", "mca", "cmov",
700 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
701 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
702 "fxsr", "sse", "sse2", "ss",
703 "ht" /* Intel htt */, "tm", "ia64", "pbe",
705 .cpuid
= {.eax
= 1, .reg
= R_EDX
, },
706 .tcg_features
= TCG_FEATURES
,
709 .type
= CPUID_FEATURE_WORD
,
711 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
712 "ds-cpl", "vmx", "smx", "est",
713 "tm2", "ssse3", "cid", NULL
,
714 "fma", "cx16", "xtpr", "pdcm",
715 NULL
, "pcid", "dca", "sse4.1",
716 "sse4.2", "x2apic", "movbe", "popcnt",
717 "tsc-deadline", "aes", "xsave", NULL
/* osxsave */,
718 "avx", "f16c", "rdrand", "hypervisor",
720 .cpuid
= { .eax
= 1, .reg
= R_ECX
, },
721 .tcg_features
= TCG_EXT_FEATURES
,
723 /* Feature names that are already defined on feature_name[] but
724 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
725 * names on feat_names below. They are copied automatically
726 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
728 [FEAT_8000_0001_EDX
] = {
729 .type
= CPUID_FEATURE_WORD
,
731 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
732 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
733 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
734 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
735 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
736 "nx", NULL
, "mmxext", NULL
/* mmx */,
737 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
738 NULL
, "lm", "3dnowext", "3dnow",
740 .cpuid
= { .eax
= 0x80000001, .reg
= R_EDX
, },
741 .tcg_features
= TCG_EXT2_FEATURES
,
743 [FEAT_8000_0001_ECX
] = {
744 .type
= CPUID_FEATURE_WORD
,
746 "lahf-lm", "cmp-legacy", "svm", "extapic",
747 "cr8legacy", "abm", "sse4a", "misalignsse",
748 "3dnowprefetch", "osvw", "ibs", "xop",
749 "skinit", "wdt", NULL
, "lwp",
750 "fma4", "tce", NULL
, "nodeid-msr",
751 NULL
, "tbm", "topoext", "perfctr-core",
752 "perfctr-nb", NULL
, NULL
, NULL
,
753 NULL
, NULL
, NULL
, NULL
,
755 .cpuid
= { .eax
= 0x80000001, .reg
= R_ECX
, },
756 .tcg_features
= TCG_EXT3_FEATURES
,
758 * TOPOEXT is always allowed but can't be enabled blindly by
759 * "-cpu host", as it requires consistent cache topology info
760 * to be provided so it doesn't confuse guests.
762 .no_autoenable_flags
= CPUID_EXT3_TOPOEXT
,
764 [FEAT_C000_0001_EDX
] = {
765 .type
= CPUID_FEATURE_WORD
,
767 NULL
, NULL
, "xstore", "xstore-en",
768 NULL
, NULL
, "xcrypt", "xcrypt-en",
769 "ace2", "ace2-en", "phe", "phe-en",
770 "pmm", "pmm-en", NULL
, NULL
,
771 NULL
, NULL
, NULL
, NULL
,
772 NULL
, NULL
, NULL
, NULL
,
773 NULL
, NULL
, NULL
, NULL
,
774 NULL
, NULL
, NULL
, NULL
,
776 .cpuid
= { .eax
= 0xC0000001, .reg
= R_EDX
, },
777 .tcg_features
= TCG_EXT4_FEATURES
,
780 .type
= CPUID_FEATURE_WORD
,
782 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
783 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
784 NULL
, "kvm-pv-tlb-flush", NULL
, "kvm-pv-ipi",
785 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
786 NULL
, NULL
, NULL
, NULL
,
787 NULL
, NULL
, NULL
, NULL
,
788 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
789 NULL
, NULL
, NULL
, NULL
,
791 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EAX
, },
792 .tcg_features
= TCG_KVM_FEATURES
,
795 .type
= CPUID_FEATURE_WORD
,
797 "kvm-hint-dedicated", NULL
, NULL
, NULL
,
798 NULL
, NULL
, NULL
, NULL
,
799 NULL
, NULL
, NULL
, NULL
,
800 NULL
, NULL
, NULL
, NULL
,
801 NULL
, NULL
, NULL
, NULL
,
802 NULL
, NULL
, NULL
, NULL
,
803 NULL
, NULL
, NULL
, NULL
,
804 NULL
, NULL
, NULL
, NULL
,
806 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EDX
, },
807 .tcg_features
= TCG_KVM_FEATURES
,
809 * KVM hints aren't auto-enabled by -cpu host, they need to be
810 * explicitly enabled in the command-line.
812 .no_autoenable_flags
= ~0U,
815 .type
= CPUID_FEATURE_WORD
,
817 "npt", "lbrv", "svm-lock", "nrip-save",
818 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
819 NULL
, NULL
, "pause-filter", NULL
,
820 "pfthreshold", "avic", NULL
, "v-vmsave-vmload",
821 "vgif", NULL
, NULL
, NULL
,
822 NULL
, NULL
, NULL
, NULL
,
823 NULL
, "vnmi", NULL
, NULL
,
824 "svme-addr-chk", NULL
, NULL
, NULL
,
826 .cpuid
= { .eax
= 0x8000000A, .reg
= R_EDX
, },
827 .tcg_features
= TCG_SVM_FEATURES
,
830 .type
= CPUID_FEATURE_WORD
,
832 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
833 "hle", "avx2", NULL
, "smep",
834 "bmi2", "erms", "invpcid", "rtm",
835 NULL
, NULL
, "mpx", NULL
,
836 "avx512f", "avx512dq", "rdseed", "adx",
837 "smap", "avx512ifma", "pcommit", "clflushopt",
838 "clwb", "intel-pt", "avx512pf", "avx512er",
839 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
843 .needs_ecx
= true, .ecx
= 0,
846 .tcg_features
= TCG_7_0_EBX_FEATURES
,
849 .type
= CPUID_FEATURE_WORD
,
851 NULL
, "avx512vbmi", "umip", "pku",
852 NULL
/* ospke */, "waitpkg", "avx512vbmi2", NULL
,
853 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
854 "avx512bitalg", NULL
, "avx512-vpopcntdq", NULL
,
855 "la57", NULL
, NULL
, NULL
,
856 NULL
, NULL
, "rdpid", NULL
,
857 "bus-lock-detect", "cldemote", NULL
, "movdiri",
858 "movdir64b", NULL
, "sgxlc", "pks",
862 .needs_ecx
= true, .ecx
= 0,
865 .tcg_features
= TCG_7_0_ECX_FEATURES
,
868 .type
= CPUID_FEATURE_WORD
,
870 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
871 "fsrm", NULL
, NULL
, NULL
,
872 "avx512-vp2intersect", NULL
, "md-clear", NULL
,
873 NULL
, NULL
, "serialize", NULL
,
874 "tsx-ldtrk", NULL
, NULL
/* pconfig */, "arch-lbr",
875 NULL
, NULL
, "amx-bf16", "avx512-fp16",
876 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
877 "flush-l1d", "arch-capabilities", "core-capability", "ssbd",
881 .needs_ecx
= true, .ecx
= 0,
884 .tcg_features
= TCG_7_0_EDX_FEATURES
,
887 .type
= CPUID_FEATURE_WORD
,
889 NULL
, NULL
, NULL
, NULL
,
890 "avx-vnni", "avx512-bf16", NULL
, "cmpccxadd",
891 NULL
, NULL
, "fzrm", "fsrs",
892 "fsrc", NULL
, NULL
, NULL
,
893 NULL
, NULL
, NULL
, NULL
,
894 NULL
, "amx-fp16", NULL
, "avx-ifma",
895 NULL
, NULL
, NULL
, NULL
,
896 NULL
, NULL
, NULL
, NULL
,
900 .needs_ecx
= true, .ecx
= 1,
903 .tcg_features
= TCG_7_1_EAX_FEATURES
,
906 .type
= CPUID_FEATURE_WORD
,
908 NULL
, NULL
, NULL
, NULL
,
909 "avx-vnni-int8", "avx-ne-convert", NULL
, NULL
,
910 NULL
, NULL
, NULL
, NULL
,
911 NULL
, NULL
, "prefetchiti", NULL
,
912 NULL
, NULL
, NULL
, NULL
,
913 NULL
, NULL
, NULL
, NULL
,
914 NULL
, NULL
, NULL
, NULL
,
915 NULL
, NULL
, NULL
, NULL
,
919 .needs_ecx
= true, .ecx
= 1,
922 .tcg_features
= TCG_7_1_EDX_FEATURES
,
924 [FEAT_8000_0007_EDX
] = {
925 .type
= CPUID_FEATURE_WORD
,
927 NULL
, NULL
, NULL
, NULL
,
928 NULL
, NULL
, NULL
, NULL
,
929 "invtsc", NULL
, NULL
, NULL
,
930 NULL
, NULL
, NULL
, NULL
,
931 NULL
, NULL
, NULL
, NULL
,
932 NULL
, NULL
, NULL
, NULL
,
933 NULL
, NULL
, NULL
, NULL
,
934 NULL
, NULL
, NULL
, NULL
,
936 .cpuid
= { .eax
= 0x80000007, .reg
= R_EDX
, },
937 .tcg_features
= TCG_APM_FEATURES
,
938 .unmigratable_flags
= CPUID_APM_INVTSC
,
940 [FEAT_8000_0008_EBX
] = {
941 .type
= CPUID_FEATURE_WORD
,
943 "clzero", NULL
, "xsaveerptr", NULL
,
944 NULL
, NULL
, NULL
, NULL
,
945 NULL
, "wbnoinvd", NULL
, NULL
,
946 "ibpb", NULL
, "ibrs", "amd-stibp",
947 NULL
, "stibp-always-on", NULL
, NULL
,
948 NULL
, NULL
, NULL
, NULL
,
949 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL
,
950 "amd-psfd", NULL
, NULL
, NULL
,
952 .cpuid
= { .eax
= 0x80000008, .reg
= R_EBX
, },
953 .tcg_features
= TCG_8000_0008_EBX
,
954 .unmigratable_flags
= 0,
956 [FEAT_8000_0021_EAX
] = {
957 .type
= CPUID_FEATURE_WORD
,
959 "no-nested-data-bp", NULL
, "lfence-always-serializing", NULL
,
960 NULL
, NULL
, "null-sel-clr-base", NULL
,
961 "auto-ibrs", NULL
, NULL
, NULL
,
962 NULL
, NULL
, NULL
, NULL
,
963 NULL
, NULL
, NULL
, NULL
,
964 NULL
, NULL
, NULL
, NULL
,
965 NULL
, NULL
, NULL
, NULL
,
966 NULL
, NULL
, NULL
, NULL
,
968 .cpuid
= { .eax
= 0x80000021, .reg
= R_EAX
, },
970 .unmigratable_flags
= 0,
973 .type
= CPUID_FEATURE_WORD
,
975 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
976 "xfd", NULL
, NULL
, NULL
,
977 NULL
, NULL
, NULL
, NULL
,
978 NULL
, NULL
, NULL
, NULL
,
979 NULL
, NULL
, NULL
, NULL
,
980 NULL
, NULL
, NULL
, NULL
,
981 NULL
, NULL
, NULL
, NULL
,
982 NULL
, NULL
, NULL
, NULL
,
986 .needs_ecx
= true, .ecx
= 1,
989 .tcg_features
= TCG_XSAVE_FEATURES
,
991 [FEAT_XSAVE_XSS_LO
] = {
992 .type
= CPUID_FEATURE_WORD
,
994 NULL
, NULL
, NULL
, NULL
,
995 NULL
, NULL
, NULL
, NULL
,
996 NULL
, NULL
, NULL
, NULL
,
997 NULL
, NULL
, NULL
, NULL
,
998 NULL
, NULL
, NULL
, NULL
,
999 NULL
, NULL
, NULL
, NULL
,
1000 NULL
, NULL
, NULL
, NULL
,
1001 NULL
, NULL
, NULL
, NULL
,
1010 [FEAT_XSAVE_XSS_HI
] = {
1011 .type
= CPUID_FEATURE_WORD
,
1020 .type
= CPUID_FEATURE_WORD
,
1022 NULL
, NULL
, "arat", NULL
,
1023 NULL
, NULL
, NULL
, NULL
,
1024 NULL
, NULL
, NULL
, NULL
,
1025 NULL
, NULL
, NULL
, NULL
,
1026 NULL
, NULL
, NULL
, NULL
,
1027 NULL
, NULL
, NULL
, NULL
,
1028 NULL
, NULL
, NULL
, NULL
,
1029 NULL
, NULL
, NULL
, NULL
,
1031 .cpuid
= { .eax
= 6, .reg
= R_EAX
, },
1032 .tcg_features
= TCG_6_EAX_FEATURES
,
1034 [FEAT_XSAVE_XCR0_LO
] = {
1035 .type
= CPUID_FEATURE_WORD
,
1038 .needs_ecx
= true, .ecx
= 0,
1041 .tcg_features
= ~0U,
1042 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
1043 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
1044 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
1047 [FEAT_XSAVE_XCR0_HI
] = {
1048 .type
= CPUID_FEATURE_WORD
,
1051 .needs_ecx
= true, .ecx
= 0,
1054 .tcg_features
= ~0U,
1056 /*Below are MSR exposed features*/
1057 [FEAT_ARCH_CAPABILITIES
] = {
1058 .type
= MSR_FEATURE_WORD
,
1060 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1061 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1062 "taa-no", NULL
, NULL
, NULL
,
1063 NULL
, NULL
, NULL
, NULL
,
1064 NULL
, "fb-clear", NULL
, NULL
,
1065 NULL
, NULL
, NULL
, NULL
,
1066 NULL
, NULL
, NULL
, NULL
,
1067 NULL
, NULL
, NULL
, NULL
,
1070 .index
= MSR_IA32_ARCH_CAPABILITIES
,
1073 [FEAT_CORE_CAPABILITY
] = {
1074 .type
= MSR_FEATURE_WORD
,
1076 NULL
, NULL
, NULL
, NULL
,
1077 NULL
, "split-lock-detect", NULL
, NULL
,
1078 NULL
, NULL
, NULL
, NULL
,
1079 NULL
, NULL
, NULL
, NULL
,
1080 NULL
, NULL
, NULL
, NULL
,
1081 NULL
, NULL
, NULL
, NULL
,
1082 NULL
, NULL
, NULL
, NULL
,
1083 NULL
, NULL
, NULL
, NULL
,
1086 .index
= MSR_IA32_CORE_CAPABILITY
,
1089 [FEAT_PERF_CAPABILITIES
] = {
1090 .type
= MSR_FEATURE_WORD
,
1092 NULL
, NULL
, NULL
, NULL
,
1093 NULL
, NULL
, NULL
, NULL
,
1094 NULL
, NULL
, NULL
, NULL
,
1095 NULL
, "full-width-write", NULL
, NULL
,
1096 NULL
, NULL
, NULL
, NULL
,
1097 NULL
, NULL
, NULL
, NULL
,
1098 NULL
, NULL
, NULL
, NULL
,
1099 NULL
, NULL
, NULL
, NULL
,
1102 .index
= MSR_IA32_PERF_CAPABILITIES
,
1106 [FEAT_VMX_PROCBASED_CTLS
] = {
1107 .type
= MSR_FEATURE_WORD
,
1109 NULL
, NULL
, "vmx-vintr-pending", "vmx-tsc-offset",
1110 NULL
, NULL
, NULL
, "vmx-hlt-exit",
1111 NULL
, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1112 "vmx-rdtsc-exit", NULL
, NULL
, "vmx-cr3-load-noexit",
1113 "vmx-cr3-store-noexit", NULL
, NULL
, "vmx-cr8-load-exit",
1114 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1115 "vmx-io-exit", "vmx-io-bitmap", NULL
, "vmx-mtf",
1116 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1119 .index
= MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
1123 [FEAT_VMX_SECONDARY_CTLS
] = {
1124 .type
= MSR_FEATURE_WORD
,
1126 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1127 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1128 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1129 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1130 "vmx-rdseed-exit", "vmx-pml", NULL
, NULL
,
1131 "vmx-xsaves", NULL
, NULL
, NULL
,
1132 NULL
, "vmx-tsc-scaling", NULL
, NULL
,
1133 NULL
, NULL
, NULL
, NULL
,
1136 .index
= MSR_IA32_VMX_PROCBASED_CTLS2
,
1140 [FEAT_VMX_PINBASED_CTLS
] = {
1141 .type
= MSR_FEATURE_WORD
,
1143 "vmx-intr-exit", NULL
, NULL
, "vmx-nmi-exit",
1144 NULL
, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1145 NULL
, NULL
, NULL
, NULL
,
1146 NULL
, NULL
, NULL
, NULL
,
1147 NULL
, NULL
, NULL
, NULL
,
1148 NULL
, NULL
, NULL
, NULL
,
1149 NULL
, NULL
, NULL
, NULL
,
1150 NULL
, NULL
, NULL
, NULL
,
1153 .index
= MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
1157 [FEAT_VMX_EXIT_CTLS
] = {
1158 .type
= MSR_FEATURE_WORD
,
1160 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1164 NULL
, NULL
, "vmx-exit-nosave-debugctl", NULL
,
1165 NULL
, NULL
, NULL
, NULL
,
1166 NULL
, NULL
/* vmx-exit-host-addr-space-size */, NULL
, NULL
,
1167 "vmx-exit-load-perf-global-ctrl", NULL
, NULL
, "vmx-exit-ack-intr",
1168 NULL
, NULL
, "vmx-exit-save-pat", "vmx-exit-load-pat",
1169 "vmx-exit-save-efer", "vmx-exit-load-efer",
1170 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1171 NULL
, "vmx-exit-clear-rtit-ctl", NULL
, NULL
,
1172 NULL
, "vmx-exit-load-pkrs", NULL
, NULL
,
1175 .index
= MSR_IA32_VMX_TRUE_EXIT_CTLS
,
1179 [FEAT_VMX_ENTRY_CTLS
] = {
1180 .type
= MSR_FEATURE_WORD
,
1182 NULL
, NULL
, "vmx-entry-noload-debugctl", NULL
,
1183 NULL
, NULL
, NULL
, NULL
,
1184 NULL
, "vmx-entry-ia32e-mode", NULL
, NULL
,
1185 NULL
, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1186 "vmx-entry-load-bndcfgs", NULL
, "vmx-entry-load-rtit-ctl", NULL
,
1187 NULL
, NULL
, "vmx-entry-load-pkrs", NULL
,
1188 NULL
, NULL
, NULL
, NULL
,
1189 NULL
, NULL
, NULL
, NULL
,
1192 .index
= MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
1197 .type
= MSR_FEATURE_WORD
,
1199 NULL
, NULL
, NULL
, NULL
,
1200 NULL
, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1201 "vmx-activity-wait-sipi", NULL
, NULL
, NULL
,
1202 NULL
, NULL
, NULL
, NULL
,
1203 NULL
, NULL
, NULL
, NULL
,
1204 NULL
, NULL
, NULL
, NULL
,
1205 NULL
, NULL
, NULL
, NULL
,
1206 NULL
, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL
,
1209 .index
= MSR_IA32_VMX_MISC
,
1213 [FEAT_VMX_EPT_VPID_CAPS
] = {
1214 .type
= MSR_FEATURE_WORD
,
1216 "vmx-ept-execonly", NULL
, NULL
, NULL
,
1217 NULL
, NULL
, "vmx-page-walk-4", "vmx-page-walk-5",
1218 NULL
, NULL
, NULL
, NULL
,
1219 NULL
, NULL
, NULL
, NULL
,
1220 "vmx-ept-2mb", "vmx-ept-1gb", NULL
, NULL
,
1221 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL
,
1222 NULL
, "vmx-invept-single-context", "vmx-invept-all-context", NULL
,
1223 NULL
, NULL
, NULL
, NULL
,
1224 "vmx-invvpid", NULL
, NULL
, NULL
,
1225 NULL
, NULL
, NULL
, NULL
,
1226 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1227 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1228 NULL
, NULL
, NULL
, NULL
,
1229 NULL
, NULL
, NULL
, NULL
,
1230 NULL
, NULL
, NULL
, NULL
,
1231 NULL
, NULL
, NULL
, NULL
,
1232 NULL
, NULL
, NULL
, NULL
,
1235 .index
= MSR_IA32_VMX_EPT_VPID_CAP
,
1239 [FEAT_VMX_BASIC
] = {
1240 .type
= MSR_FEATURE_WORD
,
1242 [54] = "vmx-ins-outs",
1243 [55] = "vmx-true-ctls",
1246 .index
= MSR_IA32_VMX_BASIC
,
1248 /* Just to be safe - we don't support setting the MSEG version field. */
1249 .no_autoenable_flags
= MSR_VMX_BASIC_DUAL_MONITOR
,
1252 [FEAT_VMX_VMFUNC
] = {
1253 .type
= MSR_FEATURE_WORD
,
1255 [0] = "vmx-eptp-switching",
1258 .index
= MSR_IA32_VMX_VMFUNC
,
1263 .type
= CPUID_FEATURE_WORD
,
1265 NULL
, NULL
, NULL
, NULL
,
1266 NULL
, NULL
, NULL
, NULL
,
1267 NULL
, NULL
, NULL
, NULL
,
1268 NULL
, NULL
, NULL
, NULL
,
1269 NULL
, NULL
, NULL
, NULL
,
1270 NULL
, NULL
, NULL
, NULL
,
1271 NULL
, NULL
, NULL
, NULL
,
1272 NULL
, NULL
, NULL
, "intel-pt-lip",
1276 .needs_ecx
= true, .ecx
= 0,
1279 .tcg_features
= TCG_14_0_ECX_FEATURES
,
1282 [FEAT_SGX_12_0_EAX
] = {
1283 .type
= CPUID_FEATURE_WORD
,
1285 "sgx1", "sgx2", NULL
, NULL
,
1286 NULL
, NULL
, NULL
, NULL
,
1287 NULL
, NULL
, NULL
, "sgx-edeccssa",
1288 NULL
, NULL
, NULL
, NULL
,
1289 NULL
, NULL
, NULL
, NULL
,
1290 NULL
, NULL
, NULL
, NULL
,
1291 NULL
, NULL
, NULL
, NULL
,
1292 NULL
, NULL
, NULL
, NULL
,
1296 .needs_ecx
= true, .ecx
= 0,
1299 .tcg_features
= TCG_SGX_12_0_EAX_FEATURES
,
1302 [FEAT_SGX_12_0_EBX
] = {
1303 .type
= CPUID_FEATURE_WORD
,
1305 "sgx-exinfo" , NULL
, NULL
, NULL
,
1306 NULL
, NULL
, NULL
, NULL
,
1307 NULL
, NULL
, NULL
, NULL
,
1308 NULL
, NULL
, NULL
, NULL
,
1309 NULL
, NULL
, NULL
, NULL
,
1310 NULL
, NULL
, NULL
, NULL
,
1311 NULL
, NULL
, NULL
, NULL
,
1312 NULL
, NULL
, NULL
, NULL
,
1316 .needs_ecx
= true, .ecx
= 0,
1319 .tcg_features
= TCG_SGX_12_0_EBX_FEATURES
,
1322 [FEAT_SGX_12_1_EAX
] = {
1323 .type
= CPUID_FEATURE_WORD
,
1325 NULL
, "sgx-debug", "sgx-mode64", NULL
,
1326 "sgx-provisionkey", "sgx-tokenkey", NULL
, "sgx-kss",
1327 NULL
, NULL
, "sgx-aex-notify", NULL
,
1328 NULL
, NULL
, NULL
, NULL
,
1329 NULL
, NULL
, NULL
, NULL
,
1330 NULL
, NULL
, NULL
, NULL
,
1331 NULL
, NULL
, NULL
, NULL
,
1332 NULL
, NULL
, NULL
, NULL
,
1336 .needs_ecx
= true, .ecx
= 1,
1339 .tcg_features
= TCG_SGX_12_1_EAX_FEATURES
,
1343 typedef struct FeatureMask
{
1348 typedef struct FeatureDep
{
1349 FeatureMask from
, to
;
1352 static FeatureDep feature_dependencies
[] = {
1354 .from
= { FEAT_7_0_EDX
, CPUID_7_0_EDX_ARCH_CAPABILITIES
},
1355 .to
= { FEAT_ARCH_CAPABILITIES
, ~0ull },
1358 .from
= { FEAT_7_0_EDX
, CPUID_7_0_EDX_CORE_CAPABILITY
},
1359 .to
= { FEAT_CORE_CAPABILITY
, ~0ull },
1362 .from
= { FEAT_1_ECX
, CPUID_EXT_PDCM
},
1363 .to
= { FEAT_PERF_CAPABILITIES
, ~0ull },
1366 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1367 .to
= { FEAT_VMX_PROCBASED_CTLS
, ~0ull },
1370 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1371 .to
= { FEAT_VMX_PINBASED_CTLS
, ~0ull },
1374 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1375 .to
= { FEAT_VMX_EXIT_CTLS
, ~0ull },
1378 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1379 .to
= { FEAT_VMX_ENTRY_CTLS
, ~0ull },
1382 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1383 .to
= { FEAT_VMX_MISC
, ~0ull },
1386 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1387 .to
= { FEAT_VMX_BASIC
, ~0ull },
1390 .from
= { FEAT_8000_0001_EDX
, CPUID_EXT2_LM
},
1391 .to
= { FEAT_VMX_ENTRY_CTLS
, VMX_VM_ENTRY_IA32E_MODE
},
1394 .from
= { FEAT_VMX_PROCBASED_CTLS
, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
},
1395 .to
= { FEAT_VMX_SECONDARY_CTLS
, ~0ull },
1398 .from
= { FEAT_XSAVE
, CPUID_XSAVE_XSAVES
},
1399 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_XSAVES
},
1402 .from
= { FEAT_1_ECX
, CPUID_EXT_RDRAND
},
1403 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDRAND_EXITING
},
1406 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_INVPCID
},
1407 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_INVPCID
},
1410 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_MPX
},
1411 .to
= { FEAT_VMX_EXIT_CTLS
, VMX_VM_EXIT_CLEAR_BNDCFGS
},
1414 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_MPX
},
1415 .to
= { FEAT_VMX_ENTRY_CTLS
, VMX_VM_ENTRY_LOAD_BNDCFGS
},
1418 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_RDSEED
},
1419 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDSEED_EXITING
},
1422 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_INTEL_PT
},
1423 .to
= { FEAT_14_0_ECX
, ~0ull },
1426 .from
= { FEAT_8000_0001_EDX
, CPUID_EXT2_RDTSCP
},
1427 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDTSCP
},
1430 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_EPT
},
1431 .to
= { FEAT_VMX_EPT_VPID_CAPS
, 0xffffffffull
},
1434 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_EPT
},
1435 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
},
1438 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_VPID
},
1439 .to
= { FEAT_VMX_EPT_VPID_CAPS
, 0xffffffffull
<< 32 },
1442 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_VMFUNC
},
1443 .to
= { FEAT_VMX_VMFUNC
, ~0ull },
1446 .from
= { FEAT_8000_0001_ECX
, CPUID_EXT3_SVM
},
1447 .to
= { FEAT_SVM
, ~0ull },
1451 typedef struct X86RegisterInfo32
{
1452 /* Name of register */
1454 /* QAPI enum value register */
1455 X86CPURegister32 qapi_enum
;
1456 } X86RegisterInfo32
;
1458 #define REGISTER(reg) \
1459 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1460 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
1472 /* CPUID feature bits available in XSS */
1473 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
1475 ExtSaveArea x86_ext_save_areas
[XSAVE_STATE_AREA_COUNT
] = {
1477 /* x87 FP state component is always enabled if XSAVE is supported */
1478 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1479 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1481 [XSTATE_SSE_BIT
] = {
1482 /* SSE state component is always enabled if XSAVE is supported */
1483 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1484 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1487 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
1488 .size
= sizeof(XSaveAVX
) },
1489 [XSTATE_BNDREGS_BIT
] =
1490 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1491 .size
= sizeof(XSaveBNDREG
) },
1492 [XSTATE_BNDCSR_BIT
] =
1493 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1494 .size
= sizeof(XSaveBNDCSR
) },
1495 [XSTATE_OPMASK_BIT
] =
1496 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1497 .size
= sizeof(XSaveOpmask
) },
1498 [XSTATE_ZMM_Hi256_BIT
] =
1499 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1500 .size
= sizeof(XSaveZMM_Hi256
) },
1501 [XSTATE_Hi16_ZMM_BIT
] =
1502 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1503 .size
= sizeof(XSaveHi16_ZMM
) },
1505 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
1506 .size
= sizeof(XSavePKRU
) },
1507 [XSTATE_ARCH_LBR_BIT
] = {
1508 .feature
= FEAT_7_0_EDX
, .bits
= CPUID_7_0_EDX_ARCH_LBR
,
1509 .offset
= 0 /*supervisor mode component, offset = 0 */,
1510 .size
= sizeof(XSavesArchLBR
) },
1511 [XSTATE_XTILE_CFG_BIT
] = {
1512 .feature
= FEAT_7_0_EDX
, .bits
= CPUID_7_0_EDX_AMX_TILE
,
1513 .size
= sizeof(XSaveXTILECFG
),
1515 [XSTATE_XTILE_DATA_BIT
] = {
1516 .feature
= FEAT_7_0_EDX
, .bits
= CPUID_7_0_EDX_AMX_TILE
,
1517 .size
= sizeof(XSaveXTILEDATA
)
1521 uint32_t xsave_area_size(uint64_t mask
, bool compacted
)
1523 uint64_t ret
= x86_ext_save_areas
[0].size
;
1524 const ExtSaveArea
*esa
;
1525 uint32_t offset
= 0;
1528 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
1529 esa
= &x86_ext_save_areas
[i
];
1530 if ((mask
>> i
) & 1) {
1531 offset
= compacted
? ret
: esa
->offset
;
1532 ret
= MAX(ret
, offset
+ esa
->size
);
1538 static inline bool accel_uses_host_cpuid(void)
1540 return kvm_enabled() || hvf_enabled();
1543 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU
*cpu
)
1545 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_XCR0_HI
]) << 32 |
1546 cpu
->env
.features
[FEAT_XSAVE_XCR0_LO
];
1549 /* Return name of 32-bit register, from a R_* constant */
1550 static const char *get_register_name_32(unsigned int reg
)
1552 if (reg
>= CPU_NB_REGS32
) {
1555 return x86_reg_info_32
[reg
].name
;
1558 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU
*cpu
)
1560 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_XSS_HI
]) << 32 |
1561 cpu
->env
.features
[FEAT_XSAVE_XSS_LO
];
1565 * Returns the set of feature flags that are supported and migratable by
1566 * QEMU, for a given FeatureWord.
1568 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w
)
1570 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1574 for (i
= 0; i
< 64; i
++) {
1575 uint64_t f
= 1ULL << i
;
1577 /* If the feature name is known, it is implicitly considered migratable,
1578 * unless it is explicitly set in unmigratable_flags */
1579 if ((wi
->migratable_flags
& f
) ||
1580 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
1587 void host_cpuid(uint32_t function
, uint32_t count
,
1588 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
1593 asm volatile("cpuid"
1594 : "=a"(vec
[0]), "=b"(vec
[1]),
1595 "=c"(vec
[2]), "=d"(vec
[3])
1596 : "0"(function
), "c"(count
) : "cc");
1597 #elif defined(__i386__)
1598 asm volatile("pusha \n\t"
1600 "mov %%eax, 0(%2) \n\t"
1601 "mov %%ebx, 4(%2) \n\t"
1602 "mov %%ecx, 8(%2) \n\t"
1603 "mov %%edx, 12(%2) \n\t"
1605 : : "a"(function
), "c"(count
), "S"(vec
)
1621 /* CPU class name definitions: */
1623 /* Return type name for a given CPU model name
1624 * Caller is responsible for freeing the returned string.
1626 static char *x86_cpu_type_name(const char *model_name
)
1628 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
1631 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
1633 g_autofree
char *typename
= x86_cpu_type_name(cpu_model
);
1634 return object_class_by_name(typename
);
1637 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
1639 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
1640 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
1641 return g_strndup(class_name
,
1642 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
1645 typedef struct X86CPUVersionDefinition
{
1646 X86CPUVersion version
;
1650 const CPUCaches
*const cache_info
;
1651 } X86CPUVersionDefinition
;
1653 /* Base definition for a CPU model */
1654 typedef struct X86CPUDefinition
{
1658 /* vendor is zero-terminated, 12 character ASCII string */
1659 char vendor
[CPUID_VENDOR_SZ
+ 1];
1663 FeatureWordArray features
;
1664 const char *model_id
;
1665 const CPUCaches
*const cache_info
;
1667 * Definitions for alternative versions of CPU model.
1668 * List is terminated by item with version == 0.
1669 * If NULL, version 1 will be registered automatically.
1671 const X86CPUVersionDefinition
*versions
;
1672 const char *deprecation_note
;
1675 /* Reference to a specific CPU model version */
1676 struct X86CPUModel
{
1677 /* Base CPU definition */
1678 const X86CPUDefinition
*cpudef
;
1679 /* CPU model version */
1680 X86CPUVersion version
;
1683 * If true, this is an alias CPU model.
1684 * This matters only for "-cpu help" and query-cpu-definitions
1689 /* Get full model name for CPU version */
1690 static char *x86_cpu_versioned_model_name(const X86CPUDefinition
*cpudef
,
1691 X86CPUVersion version
)
1693 assert(version
> 0);
1694 return g_strdup_printf("%s-v%d", cpudef
->name
, (int)version
);
1697 static const X86CPUVersionDefinition
*
1698 x86_cpu_def_get_versions(const X86CPUDefinition
*def
)
1700 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1701 static const X86CPUVersionDefinition default_version_list
[] = {
1703 { /* end of list */ }
1706 return def
->versions
?: default_version_list
;
1709 static const CPUCaches epyc_cache_info
= {
1710 .l1d_cache
= &(CPUCacheInfo
) {
1720 .no_invd_sharing
= true,
1722 .l1i_cache
= &(CPUCacheInfo
) {
1723 .type
= INSTRUCTION_CACHE
,
1732 .no_invd_sharing
= true,
1734 .l2_cache
= &(CPUCacheInfo
) {
1735 .type
= UNIFIED_CACHE
,
1744 .l3_cache
= &(CPUCacheInfo
) {
1745 .type
= UNIFIED_CACHE
,
1749 .associativity
= 16,
1755 .complex_indexing
= true,
1759 static CPUCaches epyc_v4_cache_info
= {
1760 .l1d_cache
= &(CPUCacheInfo
) {
1770 .no_invd_sharing
= true,
1772 .l1i_cache
= &(CPUCacheInfo
) {
1773 .type
= INSTRUCTION_CACHE
,
1782 .no_invd_sharing
= true,
1784 .l2_cache
= &(CPUCacheInfo
) {
1785 .type
= UNIFIED_CACHE
,
1794 .l3_cache
= &(CPUCacheInfo
) {
1795 .type
= UNIFIED_CACHE
,
1799 .associativity
= 16,
1805 .complex_indexing
= false,
1809 static const CPUCaches epyc_rome_cache_info
= {
1810 .l1d_cache
= &(CPUCacheInfo
) {
1820 .no_invd_sharing
= true,
1822 .l1i_cache
= &(CPUCacheInfo
) {
1823 .type
= INSTRUCTION_CACHE
,
1832 .no_invd_sharing
= true,
1834 .l2_cache
= &(CPUCacheInfo
) {
1835 .type
= UNIFIED_CACHE
,
1844 .l3_cache
= &(CPUCacheInfo
) {
1845 .type
= UNIFIED_CACHE
,
1849 .associativity
= 16,
1855 .complex_indexing
= true,
1859 static const CPUCaches epyc_rome_v3_cache_info
= {
1860 .l1d_cache
= &(CPUCacheInfo
) {
1870 .no_invd_sharing
= true,
1872 .l1i_cache
= &(CPUCacheInfo
) {
1873 .type
= INSTRUCTION_CACHE
,
1882 .no_invd_sharing
= true,
1884 .l2_cache
= &(CPUCacheInfo
) {
1885 .type
= UNIFIED_CACHE
,
1894 .l3_cache
= &(CPUCacheInfo
) {
1895 .type
= UNIFIED_CACHE
,
1899 .associativity
= 16,
1905 .complex_indexing
= false,
1909 static const CPUCaches epyc_milan_cache_info
= {
1910 .l1d_cache
= &(CPUCacheInfo
) {
1920 .no_invd_sharing
= true,
1922 .l1i_cache
= &(CPUCacheInfo
) {
1923 .type
= INSTRUCTION_CACHE
,
1932 .no_invd_sharing
= true,
1934 .l2_cache
= &(CPUCacheInfo
) {
1935 .type
= UNIFIED_CACHE
,
1944 .l3_cache
= &(CPUCacheInfo
) {
1945 .type
= UNIFIED_CACHE
,
1949 .associativity
= 16,
1955 .complex_indexing
= true,
1959 static const CPUCaches epyc_milan_v2_cache_info
= {
1960 .l1d_cache
= &(CPUCacheInfo
) {
1970 .no_invd_sharing
= true,
1972 .l1i_cache
= &(CPUCacheInfo
) {
1973 .type
= INSTRUCTION_CACHE
,
1982 .no_invd_sharing
= true,
1984 .l2_cache
= &(CPUCacheInfo
) {
1985 .type
= UNIFIED_CACHE
,
1994 .l3_cache
= &(CPUCacheInfo
) {
1995 .type
= UNIFIED_CACHE
,
1999 .associativity
= 16,
2005 .complex_indexing
= false,
2009 static const CPUCaches epyc_genoa_cache_info
= {
2010 .l1d_cache
= &(CPUCacheInfo
) {
2020 .no_invd_sharing
= true,
2022 .l1i_cache
= &(CPUCacheInfo
) {
2023 .type
= INSTRUCTION_CACHE
,
2032 .no_invd_sharing
= true,
2034 .l2_cache
= &(CPUCacheInfo
) {
2035 .type
= UNIFIED_CACHE
,
2044 .l3_cache
= &(CPUCacheInfo
) {
2045 .type
= UNIFIED_CACHE
,
2049 .associativity
= 16,
2055 .complex_indexing
= false,
2059 /* The following VMX features are not supported by KVM and are left out in the
2062 * Dual-monitor support (all processors)
2064 * Deactivate dual-monitor treatment
2065 * Number of CR3-target values
2066 * Shutdown activity state
2067 * Wait-for-SIPI activity state
2068 * PAUSE-loop exiting (Westmere and newer)
2069 * EPT-violation #VE (Broadwell and newer)
2070 * Inject event with insn length=0 (Skylake and newer)
2071 * Conceal non-root operation from PT
2072 * Conceal VM exits from PT
2073 * Conceal VM entries from PT
2074 * Enable ENCLS exiting
2075 * Mode-based execute control (XS/XU)
2076 s TSC scaling (Skylake Server and newer)
2077 * GPA translation for PT (IceLake and newer)
2078 * User wait and pause
2080 * Load IA32_RTIT_CTL
2081 * Clear IA32_RTIT_CTL
2082 * Advanced VM-exit information for EPT violations
2083 * Sub-page write permissions
2084 * PT in VMX operation
2087 static const X86CPUDefinition builtin_x86_defs
[] = {
2091 .vendor
= CPUID_VENDOR_AMD
,
2095 .features
[FEAT_1_EDX
] =
2097 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2099 .features
[FEAT_1_ECX
] =
2100 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
2101 .features
[FEAT_8000_0001_EDX
] =
2102 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2103 .features
[FEAT_8000_0001_ECX
] =
2104 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
2105 .xlevel
= 0x8000000A,
2106 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2111 .vendor
= CPUID_VENDOR_AMD
,
2115 /* Missing: CPUID_HT */
2116 .features
[FEAT_1_EDX
] =
2118 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2119 CPUID_PSE36
| CPUID_VME
,
2120 .features
[FEAT_1_ECX
] =
2121 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
2123 .features
[FEAT_8000_0001_EDX
] =
2124 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
2125 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
2126 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
2127 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2129 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2130 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
2131 .features
[FEAT_8000_0001_ECX
] =
2132 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
2133 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
2134 /* Missing: CPUID_SVM_LBRV */
2135 .features
[FEAT_SVM
] =
2137 .xlevel
= 0x8000001A,
2138 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
2143 .vendor
= CPUID_VENDOR_INTEL
,
2147 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2148 .features
[FEAT_1_EDX
] =
2150 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2151 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
2152 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
2153 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
2154 .features
[FEAT_1_ECX
] =
2155 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
2157 .features
[FEAT_8000_0001_EDX
] =
2158 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2159 .features
[FEAT_8000_0001_ECX
] =
2161 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2162 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2163 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2164 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2165 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2166 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2167 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2168 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2169 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2170 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2171 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2172 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2173 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2174 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2175 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2176 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2177 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2178 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
,
2179 .xlevel
= 0x80000008,
2180 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
2185 .vendor
= CPUID_VENDOR_INTEL
,
2189 /* Missing: CPUID_HT */
2190 .features
[FEAT_1_EDX
] =
2191 PPRO_FEATURES
| CPUID_VME
|
2192 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2194 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
2195 .features
[FEAT_1_ECX
] =
2196 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
2197 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
2198 .features
[FEAT_8000_0001_EDX
] =
2199 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2200 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2201 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
2202 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2203 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
2204 .features
[FEAT_8000_0001_ECX
] =
2206 /* VMX features from Cedar Mill/Prescott */
2207 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2208 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2209 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2210 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2211 VMX_PIN_BASED_NMI_EXITING
,
2212 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2213 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2214 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2215 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2216 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2217 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2218 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2219 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
,
2220 .xlevel
= 0x80000008,
2221 .model_id
= "Common KVM processor"
2226 .vendor
= CPUID_VENDOR_INTEL
,
2230 .features
[FEAT_1_EDX
] =
2232 .features
[FEAT_1_ECX
] =
2234 .xlevel
= 0x80000004,
2235 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2240 .vendor
= CPUID_VENDOR_INTEL
,
2244 .features
[FEAT_1_EDX
] =
2245 PPRO_FEATURES
| CPUID_VME
|
2246 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
2247 .features
[FEAT_1_ECX
] =
2249 .features
[FEAT_8000_0001_ECX
] =
2251 /* VMX features from Yonah */
2252 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2253 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2254 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2255 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2256 VMX_PIN_BASED_NMI_EXITING
,
2257 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2258 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2259 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2260 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2261 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
2262 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
2263 VMX_CPU_BASED_PAUSE_EXITING
| VMX_CPU_BASED_USE_MSR_BITMAPS
,
2264 .xlevel
= 0x80000008,
2265 .model_id
= "Common 32-bit KVM processor"
2270 .vendor
= CPUID_VENDOR_INTEL
,
2274 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2275 .features
[FEAT_1_EDX
] =
2276 PPRO_FEATURES
| CPUID_VME
|
2277 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
2279 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2280 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2281 .features
[FEAT_1_ECX
] =
2282 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
2283 .features
[FEAT_8000_0001_EDX
] =
2285 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2286 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2287 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2288 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2289 VMX_PIN_BASED_NMI_EXITING
,
2290 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2291 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2292 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2293 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2294 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
2295 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
2296 VMX_CPU_BASED_PAUSE_EXITING
| VMX_CPU_BASED_USE_MSR_BITMAPS
,
2297 .xlevel
= 0x80000008,
2298 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2303 .vendor
= CPUID_VENDOR_INTEL
,
2307 .features
[FEAT_1_EDX
] =
2315 .vendor
= CPUID_VENDOR_INTEL
,
2319 .features
[FEAT_1_EDX
] =
2327 .vendor
= CPUID_VENDOR_INTEL
,
2331 .features
[FEAT_1_EDX
] =
2339 .vendor
= CPUID_VENDOR_INTEL
,
2343 .features
[FEAT_1_EDX
] =
2351 .vendor
= CPUID_VENDOR_AMD
,
2355 .features
[FEAT_1_EDX
] =
2356 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
2358 .features
[FEAT_8000_0001_EDX
] =
2359 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
2360 .xlevel
= 0x80000008,
2361 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2366 .vendor
= CPUID_VENDOR_INTEL
,
2370 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2371 .features
[FEAT_1_EDX
] =
2373 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
2374 CPUID_ACPI
| CPUID_SS
,
2375 /* Some CPUs got no CPUID_SEP */
2376 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2378 .features
[FEAT_1_ECX
] =
2379 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
2381 .features
[FEAT_8000_0001_EDX
] =
2383 .features
[FEAT_8000_0001_ECX
] =
2385 .xlevel
= 0x80000008,
2386 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2391 .vendor
= CPUID_VENDOR_INTEL
,
2395 .features
[FEAT_1_EDX
] =
2396 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2397 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2398 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2399 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2400 CPUID_DE
| CPUID_FP87
,
2401 .features
[FEAT_1_ECX
] =
2402 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
2403 .features
[FEAT_8000_0001_EDX
] =
2404 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2405 .features
[FEAT_8000_0001_ECX
] =
2407 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2408 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2409 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2410 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2411 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2412 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2413 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2414 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2415 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2416 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2417 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2418 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2419 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2420 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2421 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2422 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2423 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2424 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
,
2425 .xlevel
= 0x80000008,
2426 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2431 .vendor
= CPUID_VENDOR_INTEL
,
2435 .features
[FEAT_1_EDX
] =
2436 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2437 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2438 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2439 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2440 CPUID_DE
| CPUID_FP87
,
2441 .features
[FEAT_1_ECX
] =
2442 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2444 .features
[FEAT_8000_0001_EDX
] =
2445 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2446 .features
[FEAT_8000_0001_ECX
] =
2448 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2449 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2450 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2451 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
|
2452 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
2453 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2454 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2455 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2456 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2457 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2458 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2459 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2460 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2461 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2462 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2463 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2464 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2465 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2466 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2467 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2468 VMX_SECONDARY_EXEC_WBINVD_EXITING
,
2469 .xlevel
= 0x80000008,
2470 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2475 .vendor
= CPUID_VENDOR_INTEL
,
2479 .features
[FEAT_1_EDX
] =
2480 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2481 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2482 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2483 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2484 CPUID_DE
| CPUID_FP87
,
2485 .features
[FEAT_1_ECX
] =
2486 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2487 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
2488 .features
[FEAT_8000_0001_EDX
] =
2489 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2490 .features
[FEAT_8000_0001_ECX
] =
2492 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2493 MSR_VMX_BASIC_TRUE_CTLS
,
2494 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2495 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2496 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2497 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2498 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2499 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2500 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2501 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2502 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2504 .features
[FEAT_VMX_EXIT_CTLS
] =
2505 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2506 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2507 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2508 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2509 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2510 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2511 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2512 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2513 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2514 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2515 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2516 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2517 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2518 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2519 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2520 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2521 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2522 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2523 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2524 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2525 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2526 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2527 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2528 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2529 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2530 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2531 VMX_SECONDARY_EXEC_ENABLE_VPID
,
2532 .xlevel
= 0x80000008,
2533 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
2534 .versions
= (X86CPUVersionDefinition
[]) {
2538 .alias
= "Nehalem-IBRS",
2539 .props
= (PropValue
[]) {
2540 { "spec-ctrl", "on" },
2542 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2543 { /* end of list */ }
2546 { /* end of list */ }
2552 .vendor
= CPUID_VENDOR_INTEL
,
2556 .features
[FEAT_1_EDX
] =
2557 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2558 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2559 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2560 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2561 CPUID_DE
| CPUID_FP87
,
2562 .features
[FEAT_1_ECX
] =
2563 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
2564 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2565 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2566 .features
[FEAT_8000_0001_EDX
] =
2567 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2568 .features
[FEAT_8000_0001_ECX
] =
2570 .features
[FEAT_6_EAX
] =
2572 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2573 MSR_VMX_BASIC_TRUE_CTLS
,
2574 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2575 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2576 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2577 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2578 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2579 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2580 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2581 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2582 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2583 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2584 .features
[FEAT_VMX_EXIT_CTLS
] =
2585 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2586 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2587 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2588 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2589 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2590 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2591 MSR_VMX_MISC_STORE_LMA
,
2592 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2593 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2594 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2595 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2596 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2597 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2598 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2599 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2600 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2601 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2602 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2603 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2604 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2605 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2606 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2607 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2608 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2609 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2610 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2611 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2612 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
,
2613 .xlevel
= 0x80000008,
2614 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2615 .versions
= (X86CPUVersionDefinition
[]) {
2619 .alias
= "Westmere-IBRS",
2620 .props
= (PropValue
[]) {
2621 { "spec-ctrl", "on" },
2623 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2624 { /* end of list */ }
2627 { /* end of list */ }
2631 .name
= "SandyBridge",
2633 .vendor
= CPUID_VENDOR_INTEL
,
2637 .features
[FEAT_1_EDX
] =
2638 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2639 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2640 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2641 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2642 CPUID_DE
| CPUID_FP87
,
2643 .features
[FEAT_1_ECX
] =
2644 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2645 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
2646 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2647 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2649 .features
[FEAT_8000_0001_EDX
] =
2650 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2652 .features
[FEAT_8000_0001_ECX
] =
2654 .features
[FEAT_XSAVE
] =
2655 CPUID_XSAVE_XSAVEOPT
,
2656 .features
[FEAT_6_EAX
] =
2658 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2659 MSR_VMX_BASIC_TRUE_CTLS
,
2660 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2661 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2662 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2663 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2664 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2665 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2666 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2667 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2668 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2669 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2670 .features
[FEAT_VMX_EXIT_CTLS
] =
2671 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2672 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2673 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2674 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2675 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2676 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2677 MSR_VMX_MISC_STORE_LMA
,
2678 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2679 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2680 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2681 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2682 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2683 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2684 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2685 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2686 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2687 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2688 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2689 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2690 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2691 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2692 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2693 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2694 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2695 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2696 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2697 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2698 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
,
2699 .xlevel
= 0x80000008,
2700 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
2701 .versions
= (X86CPUVersionDefinition
[]) {
2705 .alias
= "SandyBridge-IBRS",
2706 .props
= (PropValue
[]) {
2707 { "spec-ctrl", "on" },
2709 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2710 { /* end of list */ }
2713 { /* end of list */ }
2717 .name
= "IvyBridge",
2719 .vendor
= CPUID_VENDOR_INTEL
,
2723 .features
[FEAT_1_EDX
] =
2724 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2725 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2726 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2727 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2728 CPUID_DE
| CPUID_FP87
,
2729 .features
[FEAT_1_ECX
] =
2730 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2731 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
2732 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2733 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2734 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2735 .features
[FEAT_7_0_EBX
] =
2736 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
2738 .features
[FEAT_8000_0001_EDX
] =
2739 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2741 .features
[FEAT_8000_0001_ECX
] =
2743 .features
[FEAT_XSAVE
] =
2744 CPUID_XSAVE_XSAVEOPT
,
2745 .features
[FEAT_6_EAX
] =
2747 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2748 MSR_VMX_BASIC_TRUE_CTLS
,
2749 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2750 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2751 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2752 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2753 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2754 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2755 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2756 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2757 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2758 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2759 .features
[FEAT_VMX_EXIT_CTLS
] =
2760 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2761 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2762 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2763 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2764 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2765 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2766 MSR_VMX_MISC_STORE_LMA
,
2767 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2768 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2769 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2770 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2771 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2772 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2773 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2774 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2775 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2776 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2777 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2778 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2779 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2780 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2781 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2782 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2783 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2784 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2785 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2786 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2787 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2788 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2789 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2790 VMX_SECONDARY_EXEC_RDRAND_EXITING
,
2791 .xlevel
= 0x80000008,
2792 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2793 .versions
= (X86CPUVersionDefinition
[]) {
2797 .alias
= "IvyBridge-IBRS",
2798 .props
= (PropValue
[]) {
2799 { "spec-ctrl", "on" },
2801 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2802 { /* end of list */ }
2805 { /* end of list */ }
2811 .vendor
= CPUID_VENDOR_INTEL
,
2815 .features
[FEAT_1_EDX
] =
2816 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2817 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2818 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2819 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2820 CPUID_DE
| CPUID_FP87
,
2821 .features
[FEAT_1_ECX
] =
2822 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2823 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2824 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2825 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2826 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2827 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2828 .features
[FEAT_8000_0001_EDX
] =
2829 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2831 .features
[FEAT_8000_0001_ECX
] =
2832 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2833 .features
[FEAT_7_0_EBX
] =
2834 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2835 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2836 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2838 .features
[FEAT_XSAVE
] =
2839 CPUID_XSAVE_XSAVEOPT
,
2840 .features
[FEAT_6_EAX
] =
2842 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2843 MSR_VMX_BASIC_TRUE_CTLS
,
2844 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2845 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2846 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2847 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2848 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2849 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2850 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2851 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2852 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2853 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
2854 .features
[FEAT_VMX_EXIT_CTLS
] =
2855 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2856 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2857 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2858 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2859 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2860 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2861 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
2862 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2863 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2864 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2865 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2866 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2867 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2868 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2869 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2870 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2871 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2872 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2873 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2874 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2875 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2876 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2877 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2878 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2879 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2880 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2881 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2882 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2883 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2884 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2885 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
2886 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
,
2887 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
2888 .xlevel
= 0x80000008,
2889 .model_id
= "Intel Core Processor (Haswell)",
2890 .versions
= (X86CPUVersionDefinition
[]) {
2894 .alias
= "Haswell-noTSX",
2895 .props
= (PropValue
[]) {
2898 { "stepping", "1" },
2899 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2900 { /* end of list */ }
2905 .alias
= "Haswell-IBRS",
2906 .props
= (PropValue
[]) {
2907 /* Restore TSX features removed by -v2 above */
2911 * Haswell and Haswell-IBRS had stepping=4 in
2912 * QEMU 4.0 and older
2914 { "stepping", "4" },
2915 { "spec-ctrl", "on" },
2917 "Intel Core Processor (Haswell, IBRS)" },
2918 { /* end of list */ }
2923 .alias
= "Haswell-noTSX-IBRS",
2924 .props
= (PropValue
[]) {
2927 /* spec-ctrl was already enabled by -v3 above */
2928 { "stepping", "1" },
2930 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2931 { /* end of list */ }
2934 { /* end of list */ }
2938 .name
= "Broadwell",
2940 .vendor
= CPUID_VENDOR_INTEL
,
2944 .features
[FEAT_1_EDX
] =
2945 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2946 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2947 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2948 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2949 CPUID_DE
| CPUID_FP87
,
2950 .features
[FEAT_1_ECX
] =
2951 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2952 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2953 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2954 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2955 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2956 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2957 .features
[FEAT_8000_0001_EDX
] =
2958 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2960 .features
[FEAT_8000_0001_ECX
] =
2961 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2962 .features
[FEAT_7_0_EBX
] =
2963 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2964 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2965 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2966 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2968 .features
[FEAT_XSAVE
] =
2969 CPUID_XSAVE_XSAVEOPT
,
2970 .features
[FEAT_6_EAX
] =
2972 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2973 MSR_VMX_BASIC_TRUE_CTLS
,
2974 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2975 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2976 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2977 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2978 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2979 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2980 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2981 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2982 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2983 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
2984 .features
[FEAT_VMX_EXIT_CTLS
] =
2985 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2986 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2987 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2988 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2989 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2990 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2991 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
2992 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2993 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2994 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2995 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2996 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2997 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2998 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2999 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3000 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3001 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3002 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3003 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3004 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3005 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3006 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3007 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3008 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3009 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3010 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3011 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3012 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3013 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3014 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3015 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3016 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3017 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3018 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3019 .xlevel
= 0x80000008,
3020 .model_id
= "Intel Core Processor (Broadwell)",
3021 .versions
= (X86CPUVersionDefinition
[]) {
3025 .alias
= "Broadwell-noTSX",
3026 .props
= (PropValue
[]) {
3029 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
3030 { /* end of list */ }
3035 .alias
= "Broadwell-IBRS",
3036 .props
= (PropValue
[]) {
3037 /* Restore TSX features removed by -v2 above */
3040 { "spec-ctrl", "on" },
3042 "Intel Core Processor (Broadwell, IBRS)" },
3043 { /* end of list */ }
3048 .alias
= "Broadwell-noTSX-IBRS",
3049 .props
= (PropValue
[]) {
3052 /* spec-ctrl was already enabled by -v3 above */
3054 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
3055 { /* end of list */ }
3058 { /* end of list */ }
3062 .name
= "Skylake-Client",
3064 .vendor
= CPUID_VENDOR_INTEL
,
3068 .features
[FEAT_1_EDX
] =
3069 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3070 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3071 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3072 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3073 CPUID_DE
| CPUID_FP87
,
3074 .features
[FEAT_1_ECX
] =
3075 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3076 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3077 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3078 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3079 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3080 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3081 .features
[FEAT_8000_0001_EDX
] =
3082 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
3084 .features
[FEAT_8000_0001_ECX
] =
3085 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3086 .features
[FEAT_7_0_EBX
] =
3087 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3088 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3089 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3090 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3092 /* XSAVES is added in version 4 */
3093 .features
[FEAT_XSAVE
] =
3094 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3095 CPUID_XSAVE_XGETBV1
,
3096 .features
[FEAT_6_EAX
] =
3098 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3099 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3100 MSR_VMX_BASIC_TRUE_CTLS
,
3101 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3102 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3103 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3104 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3105 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3106 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3107 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3108 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3109 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3110 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3111 .features
[FEAT_VMX_EXIT_CTLS
] =
3112 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3113 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3114 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3115 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3116 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3117 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3118 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3119 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3120 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3121 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
3122 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3123 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3124 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3125 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3126 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3127 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3128 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3129 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3130 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3131 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3132 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3133 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3134 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3135 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3136 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3137 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3138 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3139 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3140 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3141 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3142 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3143 .xlevel
= 0x80000008,
3144 .model_id
= "Intel Core Processor (Skylake)",
3145 .versions
= (X86CPUVersionDefinition
[]) {
3149 .alias
= "Skylake-Client-IBRS",
3150 .props
= (PropValue
[]) {
3151 { "spec-ctrl", "on" },
3153 "Intel Core Processor (Skylake, IBRS)" },
3154 { /* end of list */ }
3159 .alias
= "Skylake-Client-noTSX-IBRS",
3160 .props
= (PropValue
[]) {
3164 "Intel Core Processor (Skylake, IBRS, no TSX)" },
3165 { /* end of list */ }
3170 .note
= "IBRS, XSAVES, no TSX",
3171 .props
= (PropValue
[]) {
3173 { "vmx-xsaves", "on" },
3174 { /* end of list */ }
3177 { /* end of list */ }
3181 .name
= "Skylake-Server",
3183 .vendor
= CPUID_VENDOR_INTEL
,
3187 .features
[FEAT_1_EDX
] =
3188 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3189 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3190 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3191 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3192 CPUID_DE
| CPUID_FP87
,
3193 .features
[FEAT_1_ECX
] =
3194 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3195 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3196 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3197 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3198 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3199 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3200 .features
[FEAT_8000_0001_EDX
] =
3201 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3202 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3203 .features
[FEAT_8000_0001_ECX
] =
3204 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3205 .features
[FEAT_7_0_EBX
] =
3206 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3207 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3208 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3209 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3210 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3211 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3212 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3213 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3214 .features
[FEAT_7_0_ECX
] =
3216 /* XSAVES is added in version 5 */
3217 .features
[FEAT_XSAVE
] =
3218 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3219 CPUID_XSAVE_XGETBV1
,
3220 .features
[FEAT_6_EAX
] =
3222 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3223 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3224 MSR_VMX_BASIC_TRUE_CTLS
,
3225 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3226 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3227 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3228 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3229 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3230 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3231 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3232 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3233 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3234 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3235 .features
[FEAT_VMX_EXIT_CTLS
] =
3236 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3237 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3238 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3239 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3240 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3241 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3242 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3243 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3244 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3245 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3246 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3247 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3248 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3249 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3250 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3251 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3252 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3253 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3254 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3255 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3256 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3257 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3258 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3259 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3260 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3261 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3262 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3263 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3264 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3265 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3266 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3267 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3268 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3269 .xlevel
= 0x80000008,
3270 .model_id
= "Intel Xeon Processor (Skylake)",
3271 .versions
= (X86CPUVersionDefinition
[]) {
3275 .alias
= "Skylake-Server-IBRS",
3276 .props
= (PropValue
[]) {
3277 /* clflushopt was not added to Skylake-Server-IBRS */
3278 /* TODO: add -v3 including clflushopt */
3279 { "clflushopt", "off" },
3280 { "spec-ctrl", "on" },
3282 "Intel Xeon Processor (Skylake, IBRS)" },
3283 { /* end of list */ }
3288 .alias
= "Skylake-Server-noTSX-IBRS",
3289 .props
= (PropValue
[]) {
3293 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3294 { /* end of list */ }
3299 .props
= (PropValue
[]) {
3300 { "vmx-eptp-switching", "on" },
3301 { /* end of list */ }
3306 .note
= "IBRS, XSAVES, EPT switching, no TSX",
3307 .props
= (PropValue
[]) {
3309 { "vmx-xsaves", "on" },
3310 { /* end of list */ }
3313 { /* end of list */ }
3317 .name
= "Cascadelake-Server",
3319 .vendor
= CPUID_VENDOR_INTEL
,
3323 .features
[FEAT_1_EDX
] =
3324 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3325 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3326 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3327 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3328 CPUID_DE
| CPUID_FP87
,
3329 .features
[FEAT_1_ECX
] =
3330 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3331 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3332 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3333 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3334 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3335 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3336 .features
[FEAT_8000_0001_EDX
] =
3337 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3338 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3339 .features
[FEAT_8000_0001_ECX
] =
3340 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3341 .features
[FEAT_7_0_EBX
] =
3342 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3343 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3344 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3345 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3346 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3347 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3348 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3349 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3350 .features
[FEAT_7_0_ECX
] =
3352 CPUID_7_0_ECX_AVX512VNNI
,
3353 .features
[FEAT_7_0_EDX
] =
3354 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3355 /* XSAVES is added in version 5 */
3356 .features
[FEAT_XSAVE
] =
3357 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3358 CPUID_XSAVE_XGETBV1
,
3359 .features
[FEAT_6_EAX
] =
3361 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3362 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3363 MSR_VMX_BASIC_TRUE_CTLS
,
3364 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3365 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3366 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3367 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3368 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3369 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3370 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3371 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3372 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3373 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3374 .features
[FEAT_VMX_EXIT_CTLS
] =
3375 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3376 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3377 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3378 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3379 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3380 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3381 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3382 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3383 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3384 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3385 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3386 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3387 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3388 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3389 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3390 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3391 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3392 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3393 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3394 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3395 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3396 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3397 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3398 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3399 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3400 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3401 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3402 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3403 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3404 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3405 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3406 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3407 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3408 .xlevel
= 0x80000008,
3409 .model_id
= "Intel Xeon Processor (Cascadelake)",
3410 .versions
= (X86CPUVersionDefinition
[]) {
3413 .note
= "ARCH_CAPABILITIES",
3414 .props
= (PropValue
[]) {
3415 { "arch-capabilities", "on" },
3416 { "rdctl-no", "on" },
3417 { "ibrs-all", "on" },
3418 { "skip-l1dfl-vmentry", "on" },
3420 { /* end of list */ }
3424 .alias
= "Cascadelake-Server-noTSX",
3425 .note
= "ARCH_CAPABILITIES, no TSX",
3426 .props
= (PropValue
[]) {
3429 { /* end of list */ }
3433 .note
= "ARCH_CAPABILITIES, no TSX",
3434 .props
= (PropValue
[]) {
3435 { "vmx-eptp-switching", "on" },
3436 { /* end of list */ }
3440 .note
= "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3441 .props
= (PropValue
[]) {
3443 { "vmx-xsaves", "on" },
3444 { /* end of list */ }
3447 { /* end of list */ }
3451 .name
= "Cooperlake",
3453 .vendor
= CPUID_VENDOR_INTEL
,
3457 .features
[FEAT_1_EDX
] =
3458 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3459 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3460 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3461 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3462 CPUID_DE
| CPUID_FP87
,
3463 .features
[FEAT_1_ECX
] =
3464 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3465 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3466 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3467 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3468 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3469 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3470 .features
[FEAT_8000_0001_EDX
] =
3471 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3472 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3473 .features
[FEAT_8000_0001_ECX
] =
3474 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3475 .features
[FEAT_7_0_EBX
] =
3476 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3477 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3478 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3479 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3480 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3481 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3482 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3483 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3484 .features
[FEAT_7_0_ECX
] =
3486 CPUID_7_0_ECX_AVX512VNNI
,
3487 .features
[FEAT_7_0_EDX
] =
3488 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_STIBP
|
3489 CPUID_7_0_EDX_SPEC_CTRL_SSBD
| CPUID_7_0_EDX_ARCH_CAPABILITIES
,
3490 .features
[FEAT_ARCH_CAPABILITIES
] =
3491 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_IBRS_ALL
|
3492 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
| MSR_ARCH_CAP_MDS_NO
|
3493 MSR_ARCH_CAP_PSCHANGE_MC_NO
| MSR_ARCH_CAP_TAA_NO
,
3494 .features
[FEAT_7_1_EAX
] =
3495 CPUID_7_1_EAX_AVX512_BF16
,
3496 /* XSAVES is added in version 2 */
3497 .features
[FEAT_XSAVE
] =
3498 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3499 CPUID_XSAVE_XGETBV1
,
3500 .features
[FEAT_6_EAX
] =
3502 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3503 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3504 MSR_VMX_BASIC_TRUE_CTLS
,
3505 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3506 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3507 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3508 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3509 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3510 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3511 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3512 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3513 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3514 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3515 .features
[FEAT_VMX_EXIT_CTLS
] =
3516 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3517 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3518 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3519 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3520 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3521 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3522 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3523 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3524 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3525 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3526 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3527 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3528 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3529 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3530 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3531 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3532 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3533 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3534 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3535 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3536 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3537 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3538 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3539 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3540 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3541 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3542 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3543 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3544 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3545 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3546 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3547 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3548 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3549 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3550 .xlevel
= 0x80000008,
3551 .model_id
= "Intel Xeon Processor (Cooperlake)",
3552 .versions
= (X86CPUVersionDefinition
[]) {
3556 .props
= (PropValue
[]) {
3558 { "vmx-xsaves", "on" },
3559 { /* end of list */ }
3562 { /* end of list */ }
3566 .name
= "Icelake-Server",
3568 .vendor
= CPUID_VENDOR_INTEL
,
3572 .features
[FEAT_1_EDX
] =
3573 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3574 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3575 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3576 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3577 CPUID_DE
| CPUID_FP87
,
3578 .features
[FEAT_1_ECX
] =
3579 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3580 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3581 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3582 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3583 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3584 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3585 .features
[FEAT_8000_0001_EDX
] =
3586 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3587 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3588 .features
[FEAT_8000_0001_ECX
] =
3589 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3590 .features
[FEAT_8000_0008_EBX
] =
3591 CPUID_8000_0008_EBX_WBNOINVD
,
3592 .features
[FEAT_7_0_EBX
] =
3593 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3594 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3595 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3596 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3597 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3598 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3599 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3600 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3601 .features
[FEAT_7_0_ECX
] =
3602 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
3603 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
3604 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
3605 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
3606 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
,
3607 .features
[FEAT_7_0_EDX
] =
3608 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3609 /* XSAVES is added in version 5 */
3610 .features
[FEAT_XSAVE
] =
3611 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3612 CPUID_XSAVE_XGETBV1
,
3613 .features
[FEAT_6_EAX
] =
3615 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3616 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3617 MSR_VMX_BASIC_TRUE_CTLS
,
3618 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3619 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3620 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3621 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3622 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3623 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3624 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3625 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3626 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3627 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3628 .features
[FEAT_VMX_EXIT_CTLS
] =
3629 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3630 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3631 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3632 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3633 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3634 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3635 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3636 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3637 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3638 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3639 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3640 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3641 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3642 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3643 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3644 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3645 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3646 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3647 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3648 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3649 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3650 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3651 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3652 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3653 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3654 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3655 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3656 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3657 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3658 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3659 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3660 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
,
3661 .xlevel
= 0x80000008,
3662 .model_id
= "Intel Xeon Processor (Icelake)",
3663 .versions
= (X86CPUVersionDefinition
[]) {
3668 .alias
= "Icelake-Server-noTSX",
3669 .props
= (PropValue
[]) {
3672 { /* end of list */ }
3677 .props
= (PropValue
[]) {
3678 { "arch-capabilities", "on" },
3679 { "rdctl-no", "on" },
3680 { "ibrs-all", "on" },
3681 { "skip-l1dfl-vmentry", "on" },
3683 { "pschange-mc-no", "on" },
3685 { /* end of list */ }
3690 .props
= (PropValue
[]) {
3692 { "avx512ifma", "on" },
3695 { "vmx-rdseed-exit", "on" },
3696 { "vmx-pml", "on" },
3697 { "vmx-eptp-switching", "on" },
3699 { /* end of list */ }
3705 .props
= (PropValue
[]) {
3707 { "vmx-xsaves", "on" },
3708 { /* end of list */ }
3713 .note
= "5-level EPT",
3714 .props
= (PropValue
[]) {
3715 { "vmx-page-walk-5", "on" },
3716 { /* end of list */ }
3719 { /* end of list */ }
3723 .name
= "SapphireRapids",
3725 .vendor
= CPUID_VENDOR_INTEL
,
3730 * please keep the ascending order so that we can have a clear view of
3731 * bit position of each feature.
3733 .features
[FEAT_1_EDX
] =
3734 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
| CPUID_TSC
|
3735 CPUID_MSR
| CPUID_PAE
| CPUID_MCE
| CPUID_CX8
| CPUID_APIC
|
3736 CPUID_SEP
| CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3737 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
| CPUID_MMX
| CPUID_FXSR
|
3738 CPUID_SSE
| CPUID_SSE2
,
3739 .features
[FEAT_1_ECX
] =
3740 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSSE3
|
3741 CPUID_EXT_FMA
| CPUID_EXT_CX16
| CPUID_EXT_PCID
| CPUID_EXT_SSE41
|
3742 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3743 CPUID_EXT_POPCNT
| CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_AES
|
3744 CPUID_EXT_XSAVE
| CPUID_EXT_AVX
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3745 .features
[FEAT_8000_0001_EDX
] =
3746 CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
| CPUID_EXT2_PDPE1GB
|
3747 CPUID_EXT2_RDTSCP
| CPUID_EXT2_LM
,
3748 .features
[FEAT_8000_0001_ECX
] =
3749 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_ABM
| CPUID_EXT3_3DNOWPREFETCH
,
3750 .features
[FEAT_8000_0008_EBX
] =
3751 CPUID_8000_0008_EBX_WBNOINVD
,
3752 .features
[FEAT_7_0_EBX
] =
3753 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_HLE
|
3754 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
|
3755 CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
| CPUID_7_0_EBX_RTM
|
3756 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3757 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
|
3758 CPUID_7_0_EBX_AVX512IFMA
| CPUID_7_0_EBX_CLFLUSHOPT
|
3759 CPUID_7_0_EBX_CLWB
| CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_SHA_NI
|
3760 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512VL
,
3761 .features
[FEAT_7_0_ECX
] =
3762 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
3763 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
3764 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
3765 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
3766 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
|
3767 CPUID_7_0_ECX_RDPID
| CPUID_7_0_ECX_BUS_LOCK_DETECT
,
3768 .features
[FEAT_7_0_EDX
] =
3769 CPUID_7_0_EDX_FSRM
| CPUID_7_0_EDX_SERIALIZE
|
3770 CPUID_7_0_EDX_TSX_LDTRK
| CPUID_7_0_EDX_AMX_BF16
|
3771 CPUID_7_0_EDX_AVX512_FP16
| CPUID_7_0_EDX_AMX_TILE
|
3772 CPUID_7_0_EDX_AMX_INT8
| CPUID_7_0_EDX_SPEC_CTRL
|
3773 CPUID_7_0_EDX_ARCH_CAPABILITIES
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3774 .features
[FEAT_ARCH_CAPABILITIES
] =
3775 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_IBRS_ALL
|
3776 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
| MSR_ARCH_CAP_MDS_NO
|
3777 MSR_ARCH_CAP_PSCHANGE_MC_NO
| MSR_ARCH_CAP_TAA_NO
,
3778 .features
[FEAT_XSAVE
] =
3779 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3780 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
| CPUID_D_1_EAX_XFD
,
3781 .features
[FEAT_6_EAX
] =
3783 .features
[FEAT_7_1_EAX
] =
3784 CPUID_7_1_EAX_AVX_VNNI
| CPUID_7_1_EAX_AVX512_BF16
|
3785 CPUID_7_1_EAX_FZRM
| CPUID_7_1_EAX_FSRS
| CPUID_7_1_EAX_FSRC
,
3786 .features
[FEAT_VMX_BASIC
] =
3787 MSR_VMX_BASIC_INS_OUTS
| MSR_VMX_BASIC_TRUE_CTLS
,
3788 .features
[FEAT_VMX_ENTRY_CTLS
] =
3789 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_IA32E_MODE
|
3790 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
|
3791 VMX_VM_ENTRY_LOAD_IA32_PAT
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3792 .features
[FEAT_VMX_EPT_VPID_CAPS
] =
3793 MSR_VMX_EPT_EXECONLY
|
3794 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_PAGE_WALK_LENGTH_5
|
3795 MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
| MSR_VMX_EPT_1GB
|
3796 MSR_VMX_EPT_INVEPT
| MSR_VMX_EPT_AD_BITS
|
3797 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3798 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3799 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
|
3800 MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3801 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
3802 .features
[FEAT_VMX_EXIT_CTLS
] =
3803 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3804 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3805 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_IA32_PAT
|
3806 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3807 VMX_VM_EXIT_LOAD_IA32_EFER
| VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3808 .features
[FEAT_VMX_MISC
] =
3809 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_ACTIVITY_HLT
|
3810 MSR_VMX_MISC_VMWRITE_VMEXIT
,
3811 .features
[FEAT_VMX_PINBASED_CTLS
] =
3812 VMX_PIN_BASED_EXT_INTR_MASK
| VMX_PIN_BASED_NMI_EXITING
|
3813 VMX_PIN_BASED_VIRTUAL_NMIS
| VMX_PIN_BASED_VMX_PREEMPTION_TIMER
|
3814 VMX_PIN_BASED_POSTED_INTR
,
3815 .features
[FEAT_VMX_PROCBASED_CTLS
] =
3816 VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3817 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3818 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3819 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3820 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3821 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3822 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_VIRTUAL_NMI_PENDING
|
3823 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
3824 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3825 VMX_CPU_BASED_USE_MSR_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
3826 VMX_CPU_BASED_PAUSE_EXITING
|
3827 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3828 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3829 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3830 VMX_SECONDARY_EXEC_ENABLE_EPT
| VMX_SECONDARY_EXEC_DESC
|
3831 VMX_SECONDARY_EXEC_RDTSCP
|
3832 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3833 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_WBINVD_EXITING
|
3834 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3835 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3836 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3837 VMX_SECONDARY_EXEC_RDRAND_EXITING
|
3838 VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3839 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3840 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
|
3841 VMX_SECONDARY_EXEC_XSAVES
,
3842 .features
[FEAT_VMX_VMFUNC
] =
3843 MSR_VMX_VMFUNC_EPT_SWITCHING
,
3844 .xlevel
= 0x80000008,
3845 .model_id
= "Intel Xeon Processor (SapphireRapids)",
3846 .versions
= (X86CPUVersionDefinition
[]) {
3848 { /* end of list */ },
3852 .name
= "Denverton",
3854 .vendor
= CPUID_VENDOR_INTEL
,
3858 .features
[FEAT_1_EDX
] =
3859 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
| CPUID_TSC
|
3860 CPUID_MSR
| CPUID_PAE
| CPUID_MCE
| CPUID_CX8
| CPUID_APIC
|
3861 CPUID_SEP
| CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3862 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
| CPUID_MMX
| CPUID_FXSR
|
3863 CPUID_SSE
| CPUID_SSE2
,
3864 .features
[FEAT_1_ECX
] =
3865 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_MONITOR
|
3866 CPUID_EXT_SSSE3
| CPUID_EXT_CX16
| CPUID_EXT_SSE41
|
3867 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3868 CPUID_EXT_POPCNT
| CPUID_EXT_TSC_DEADLINE_TIMER
|
3869 CPUID_EXT_AES
| CPUID_EXT_XSAVE
| CPUID_EXT_RDRAND
,
3870 .features
[FEAT_8000_0001_EDX
] =
3871 CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
| CPUID_EXT2_PDPE1GB
|
3872 CPUID_EXT2_RDTSCP
| CPUID_EXT2_LM
,
3873 .features
[FEAT_8000_0001_ECX
] =
3874 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3875 .features
[FEAT_7_0_EBX
] =
3876 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_ERMS
|
3877 CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_SMAP
|
3878 CPUID_7_0_EBX_CLFLUSHOPT
| CPUID_7_0_EBX_SHA_NI
,
3879 .features
[FEAT_7_0_EDX
] =
3880 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_ARCH_CAPABILITIES
|
3881 CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3882 /* XSAVES is added in version 3 */
3883 .features
[FEAT_XSAVE
] =
3884 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
| CPUID_XSAVE_XGETBV1
,
3885 .features
[FEAT_6_EAX
] =
3887 .features
[FEAT_ARCH_CAPABILITIES
] =
3888 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
,
3889 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3890 MSR_VMX_BASIC_TRUE_CTLS
,
3891 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3892 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3893 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3894 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3895 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3896 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3897 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3898 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3899 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3900 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3901 .features
[FEAT_VMX_EXIT_CTLS
] =
3902 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3903 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3904 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3905 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3906 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3907 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3908 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3909 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3910 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3911 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3912 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3913 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3914 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3915 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3916 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3917 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3918 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3919 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3920 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3921 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3922 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3923 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3924 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3925 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3926 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3927 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3928 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3929 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3930 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3931 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3932 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3933 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3934 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3935 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3936 .xlevel
= 0x80000008,
3937 .model_id
= "Intel Atom Processor (Denverton)",
3938 .versions
= (X86CPUVersionDefinition
[]) {
3942 .note
= "no MPX, no MONITOR",
3943 .props
= (PropValue
[]) {
3944 { "monitor", "off" },
3946 { /* end of list */ },
3951 .note
= "XSAVES, no MPX, no MONITOR",
3952 .props
= (PropValue
[]) {
3954 { "vmx-xsaves", "on" },
3955 { /* end of list */ },
3958 { /* end of list */ },
3962 .name
= "Snowridge",
3964 .vendor
= CPUID_VENDOR_INTEL
,
3968 .features
[FEAT_1_EDX
] =
3969 /* missing: CPUID_PN CPUID_IA64 */
3970 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3971 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
|
3972 CPUID_TSC
| CPUID_MSR
| CPUID_PAE
| CPUID_MCE
|
3973 CPUID_CX8
| CPUID_APIC
| CPUID_SEP
|
3974 CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3975 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
|
3977 CPUID_FXSR
| CPUID_SSE
| CPUID_SSE2
,
3978 .features
[FEAT_1_ECX
] =
3979 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_MONITOR
|
3983 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3985 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_AES
| CPUID_EXT_XSAVE
|
3987 .features
[FEAT_8000_0001_EDX
] =
3988 CPUID_EXT2_SYSCALL
|
3990 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3992 .features
[FEAT_8000_0001_ECX
] =
3993 CPUID_EXT3_LAHF_LM
|
3994 CPUID_EXT3_3DNOWPREFETCH
,
3995 .features
[FEAT_7_0_EBX
] =
3996 CPUID_7_0_EBX_FSGSBASE
|
3997 CPUID_7_0_EBX_SMEP
|
3998 CPUID_7_0_EBX_ERMS
|
3999 CPUID_7_0_EBX_MPX
| /* missing bits 13, 15 */
4000 CPUID_7_0_EBX_RDSEED
|
4001 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4002 CPUID_7_0_EBX_CLWB
|
4003 CPUID_7_0_EBX_SHA_NI
,
4004 .features
[FEAT_7_0_ECX
] =
4005 CPUID_7_0_ECX_UMIP
|
4007 CPUID_7_0_ECX_GFNI
|
4008 CPUID_7_0_ECX_MOVDIRI
| CPUID_7_0_ECX_CLDEMOTE
|
4009 CPUID_7_0_ECX_MOVDIR64B
,
4010 .features
[FEAT_7_0_EDX
] =
4011 CPUID_7_0_EDX_SPEC_CTRL
|
4012 CPUID_7_0_EDX_ARCH_CAPABILITIES
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
|
4013 CPUID_7_0_EDX_CORE_CAPABILITY
,
4014 .features
[FEAT_CORE_CAPABILITY
] =
4015 MSR_CORE_CAP_SPLIT_LOCK_DETECT
,
4016 /* XSAVES is added in version 3 */
4017 .features
[FEAT_XSAVE
] =
4018 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4019 CPUID_XSAVE_XGETBV1
,
4020 .features
[FEAT_6_EAX
] =
4022 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
4023 MSR_VMX_BASIC_TRUE_CTLS
,
4024 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
4025 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
4026 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
4027 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
4028 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
4029 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
4030 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
4031 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
4032 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
4033 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
4034 .features
[FEAT_VMX_EXIT_CTLS
] =
4035 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
4036 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
4037 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
4038 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
4039 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
4040 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
4041 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
4042 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
4043 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
4044 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
4045 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
4046 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
4047 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
4048 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
4049 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
4050 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
4051 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
4052 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
4053 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
4054 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
4055 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
4056 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
4057 .features
[FEAT_VMX_SECONDARY_CTLS
] =
4058 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
4059 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
4060 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
4061 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
4062 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
4063 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4064 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
4065 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
4066 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
4067 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
4068 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
4069 .xlevel
= 0x80000008,
4070 .model_id
= "Intel Atom Processor (SnowRidge)",
4071 .versions
= (X86CPUVersionDefinition
[]) {
4075 .props
= (PropValue
[]) {
4077 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
4078 { /* end of list */ },
4083 .note
= "XSAVES, no MPX",
4084 .props
= (PropValue
[]) {
4086 { "vmx-xsaves", "on" },
4087 { /* end of list */ },
4092 .note
= "no split lock detect, no core-capability",
4093 .props
= (PropValue
[]) {
4094 { "split-lock-detect", "off" },
4095 { "core-capability", "off" },
4096 { /* end of list */ },
4099 { /* end of list */ },
4103 .name
= "KnightsMill",
4105 .vendor
= CPUID_VENDOR_INTEL
,
4109 .features
[FEAT_1_EDX
] =
4110 CPUID_VME
| CPUID_SS
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
|
4111 CPUID_MMX
| CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
|
4112 CPUID_MCA
| CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
|
4113 CPUID_CX8
| CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
|
4114 CPUID_PSE
| CPUID_DE
| CPUID_FP87
,
4115 .features
[FEAT_1_ECX
] =
4116 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
4117 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
4118 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
4119 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
4120 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
4121 CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
4122 .features
[FEAT_8000_0001_EDX
] =
4123 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
4124 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
4125 .features
[FEAT_8000_0001_ECX
] =
4126 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
4127 .features
[FEAT_7_0_EBX
] =
4128 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4129 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
|
4130 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_AVX512F
|
4131 CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_AVX512PF
|
4132 CPUID_7_0_EBX_AVX512ER
,
4133 .features
[FEAT_7_0_ECX
] =
4134 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
4135 .features
[FEAT_7_0_EDX
] =
4136 CPUID_7_0_EDX_AVX512_4VNNIW
| CPUID_7_0_EDX_AVX512_4FMAPS
,
4137 .features
[FEAT_XSAVE
] =
4138 CPUID_XSAVE_XSAVEOPT
,
4139 .features
[FEAT_6_EAX
] =
4141 .xlevel
= 0x80000008,
4142 .model_id
= "Intel Xeon Phi Processor (Knights Mill)",
4145 .name
= "Opteron_G1",
4147 .vendor
= CPUID_VENDOR_AMD
,
4151 .features
[FEAT_1_EDX
] =
4152 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4153 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4154 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4155 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4156 CPUID_DE
| CPUID_FP87
,
4157 .features
[FEAT_1_ECX
] =
4159 .features
[FEAT_8000_0001_EDX
] =
4160 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
4161 .xlevel
= 0x80000008,
4162 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
4165 .name
= "Opteron_G2",
4167 .vendor
= CPUID_VENDOR_AMD
,
4171 .features
[FEAT_1_EDX
] =
4172 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4173 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4174 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4175 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4176 CPUID_DE
| CPUID_FP87
,
4177 .features
[FEAT_1_ECX
] =
4178 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
4179 .features
[FEAT_8000_0001_EDX
] =
4180 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
4181 .features
[FEAT_8000_0001_ECX
] =
4182 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
4183 .xlevel
= 0x80000008,
4184 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
4187 .name
= "Opteron_G3",
4189 .vendor
= CPUID_VENDOR_AMD
,
4193 .features
[FEAT_1_EDX
] =
4194 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4195 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4196 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4197 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4198 CPUID_DE
| CPUID_FP87
,
4199 .features
[FEAT_1_ECX
] =
4200 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
4202 .features
[FEAT_8000_0001_EDX
] =
4203 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
|
4205 .features
[FEAT_8000_0001_ECX
] =
4206 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
4207 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
4208 .xlevel
= 0x80000008,
4209 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
4212 .name
= "Opteron_G4",
4214 .vendor
= CPUID_VENDOR_AMD
,
4218 .features
[FEAT_1_EDX
] =
4219 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4220 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4221 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4222 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4223 CPUID_DE
| CPUID_FP87
,
4224 .features
[FEAT_1_ECX
] =
4225 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
4226 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4227 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
4229 .features
[FEAT_8000_0001_EDX
] =
4230 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
4231 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
4232 .features
[FEAT_8000_0001_ECX
] =
4233 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
4234 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
4235 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
4237 .features
[FEAT_SVM
] =
4238 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4240 .xlevel
= 0x8000001A,
4241 .model_id
= "AMD Opteron 62xx class CPU",
4244 .name
= "Opteron_G5",
4246 .vendor
= CPUID_VENDOR_AMD
,
4250 .features
[FEAT_1_EDX
] =
4251 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4252 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4253 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4254 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4255 CPUID_DE
| CPUID_FP87
,
4256 .features
[FEAT_1_ECX
] =
4257 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
4258 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
4259 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
4260 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
4261 .features
[FEAT_8000_0001_EDX
] =
4262 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
4263 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
4264 .features
[FEAT_8000_0001_ECX
] =
4265 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
4266 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
4267 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
4269 .features
[FEAT_SVM
] =
4270 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4272 .xlevel
= 0x8000001A,
4273 .model_id
= "AMD Opteron 63xx class CPU",
4278 .vendor
= CPUID_VENDOR_AMD
,
4282 .features
[FEAT_1_EDX
] =
4283 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4284 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4285 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4286 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4287 CPUID_VME
| CPUID_FP87
,
4288 .features
[FEAT_1_ECX
] =
4289 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4290 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4291 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4292 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4293 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
4294 .features
[FEAT_8000_0001_EDX
] =
4295 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4296 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4298 .features
[FEAT_8000_0001_ECX
] =
4299 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4300 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4301 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4303 .features
[FEAT_7_0_EBX
] =
4304 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4305 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4306 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4307 CPUID_7_0_EBX_SHA_NI
,
4308 .features
[FEAT_XSAVE
] =
4309 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4310 CPUID_XSAVE_XGETBV1
,
4311 .features
[FEAT_6_EAX
] =
4313 .features
[FEAT_SVM
] =
4314 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4315 .xlevel
= 0x8000001E,
4316 .model_id
= "AMD EPYC Processor",
4317 .cache_info
= &epyc_cache_info
,
4318 .versions
= (X86CPUVersionDefinition
[]) {
4322 .alias
= "EPYC-IBPB",
4323 .props
= (PropValue
[]) {
4326 "AMD EPYC Processor (with IBPB)" },
4327 { /* end of list */ }
4332 .props
= (PropValue
[]) {
4334 { "perfctr-core", "on" },
4336 { "xsaveerptr", "on" },
4339 "AMD EPYC Processor" },
4340 { /* end of list */ }
4345 .props
= (PropValue
[]) {
4347 "AMD EPYC-v4 Processor" },
4348 { /* end of list */ }
4350 .cache_info
= &epyc_v4_cache_info
4352 { /* end of list */ }
4358 .vendor
= CPUID_VENDOR_HYGON
,
4362 .features
[FEAT_1_EDX
] =
4363 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4364 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4365 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4366 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4367 CPUID_VME
| CPUID_FP87
,
4368 .features
[FEAT_1_ECX
] =
4369 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4370 CPUID_EXT_XSAVE
| CPUID_EXT_POPCNT
|
4371 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4372 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4373 CPUID_EXT_MONITOR
| CPUID_EXT_SSE3
,
4374 .features
[FEAT_8000_0001_EDX
] =
4375 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4376 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4378 .features
[FEAT_8000_0001_ECX
] =
4379 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4380 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4381 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4383 .features
[FEAT_8000_0008_EBX
] =
4384 CPUID_8000_0008_EBX_IBPB
,
4385 .features
[FEAT_7_0_EBX
] =
4386 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4387 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4388 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
,
4389 /* XSAVES is added in version 2 */
4390 .features
[FEAT_XSAVE
] =
4391 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4392 CPUID_XSAVE_XGETBV1
,
4393 .features
[FEAT_6_EAX
] =
4395 .features
[FEAT_SVM
] =
4396 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4397 .xlevel
= 0x8000001E,
4398 .model_id
= "Hygon Dhyana Processor",
4399 .cache_info
= &epyc_cache_info
,
4400 .versions
= (X86CPUVersionDefinition
[]) {
4404 .props
= (PropValue
[]) {
4406 { /* end of list */ }
4409 { /* end of list */ }
4413 .name
= "EPYC-Rome",
4415 .vendor
= CPUID_VENDOR_AMD
,
4419 .features
[FEAT_1_EDX
] =
4420 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4421 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4422 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4423 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4424 CPUID_VME
| CPUID_FP87
,
4425 .features
[FEAT_1_ECX
] =
4426 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4427 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4428 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4429 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4430 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
4431 .features
[FEAT_8000_0001_EDX
] =
4432 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4433 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4435 .features
[FEAT_8000_0001_ECX
] =
4436 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4437 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4438 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4439 CPUID_EXT3_TOPOEXT
| CPUID_EXT3_PERFCORE
,
4440 .features
[FEAT_8000_0008_EBX
] =
4441 CPUID_8000_0008_EBX_CLZERO
| CPUID_8000_0008_EBX_XSAVEERPTR
|
4442 CPUID_8000_0008_EBX_WBNOINVD
| CPUID_8000_0008_EBX_IBPB
|
4443 CPUID_8000_0008_EBX_STIBP
,
4444 .features
[FEAT_7_0_EBX
] =
4445 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4446 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4447 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4448 CPUID_7_0_EBX_SHA_NI
| CPUID_7_0_EBX_CLWB
,
4449 .features
[FEAT_7_0_ECX
] =
4450 CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_RDPID
,
4451 .features
[FEAT_XSAVE
] =
4452 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4453 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
,
4454 .features
[FEAT_6_EAX
] =
4456 .features
[FEAT_SVM
] =
4457 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4458 .xlevel
= 0x8000001E,
4459 .model_id
= "AMD EPYC-Rome Processor",
4460 .cache_info
= &epyc_rome_cache_info
,
4461 .versions
= (X86CPUVersionDefinition
[]) {
4465 .props
= (PropValue
[]) {
4467 { "amd-ssbd", "on" },
4468 { /* end of list */ }
4473 .props
= (PropValue
[]) {
4475 "AMD EPYC-Rome-v3 Processor" },
4476 { /* end of list */ }
4478 .cache_info
= &epyc_rome_v3_cache_info
4482 .props
= (PropValue
[]) {
4485 "AMD EPYC-Rome-v4 Processor (no XSAVES)" },
4486 { "xsaves", "off" },
4487 { /* end of list */ }
4490 { /* end of list */ }
4494 .name
= "EPYC-Milan",
4496 .vendor
= CPUID_VENDOR_AMD
,
4500 .features
[FEAT_1_EDX
] =
4501 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4502 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4503 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4504 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4505 CPUID_VME
| CPUID_FP87
,
4506 .features
[FEAT_1_ECX
] =
4507 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4508 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4509 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4510 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4511 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
4513 .features
[FEAT_8000_0001_EDX
] =
4514 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4515 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4517 .features
[FEAT_8000_0001_ECX
] =
4518 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4519 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4520 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4521 CPUID_EXT3_TOPOEXT
| CPUID_EXT3_PERFCORE
,
4522 .features
[FEAT_8000_0008_EBX
] =
4523 CPUID_8000_0008_EBX_CLZERO
| CPUID_8000_0008_EBX_XSAVEERPTR
|
4524 CPUID_8000_0008_EBX_WBNOINVD
| CPUID_8000_0008_EBX_IBPB
|
4525 CPUID_8000_0008_EBX_IBRS
| CPUID_8000_0008_EBX_STIBP
|
4526 CPUID_8000_0008_EBX_AMD_SSBD
,
4527 .features
[FEAT_7_0_EBX
] =
4528 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4529 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4530 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4531 CPUID_7_0_EBX_SHA_NI
| CPUID_7_0_EBX_CLWB
| CPUID_7_0_EBX_ERMS
|
4532 CPUID_7_0_EBX_INVPCID
,
4533 .features
[FEAT_7_0_ECX
] =
4534 CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_RDPID
| CPUID_7_0_ECX_PKU
,
4535 .features
[FEAT_7_0_EDX
] =
4537 .features
[FEAT_XSAVE
] =
4538 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4539 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
,
4540 .features
[FEAT_6_EAX
] =
4542 .features
[FEAT_SVM
] =
4543 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
| CPUID_SVM_SVME_ADDR_CHK
,
4544 .xlevel
= 0x8000001E,
4545 .model_id
= "AMD EPYC-Milan Processor",
4546 .cache_info
= &epyc_milan_cache_info
,
4547 .versions
= (X86CPUVersionDefinition
[]) {
4551 .props
= (PropValue
[]) {
4553 "AMD EPYC-Milan-v2 Processor" },
4555 { "vpclmulqdq", "on" },
4556 { "stibp-always-on", "on" },
4557 { "amd-psfd", "on" },
4558 { "no-nested-data-bp", "on" },
4559 { "lfence-always-serializing", "on" },
4560 { "null-sel-clr-base", "on" },
4561 { /* end of list */ }
4563 .cache_info
= &epyc_milan_v2_cache_info
4565 { /* end of list */ }
4569 .name
= "EPYC-Genoa",
4571 .vendor
= CPUID_VENDOR_AMD
,
4575 .features
[FEAT_1_EDX
] =
4576 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4577 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4578 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4579 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4580 CPUID_VME
| CPUID_FP87
,
4581 .features
[FEAT_1_ECX
] =
4582 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4583 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4584 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4585 CPUID_EXT_PCID
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
4586 CPUID_EXT_SSSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
|
4588 .features
[FEAT_8000_0001_EDX
] =
4589 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4590 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4592 .features
[FEAT_8000_0001_ECX
] =
4593 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4594 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4595 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4596 CPUID_EXT3_TOPOEXT
| CPUID_EXT3_PERFCORE
,
4597 .features
[FEAT_8000_0008_EBX
] =
4598 CPUID_8000_0008_EBX_CLZERO
| CPUID_8000_0008_EBX_XSAVEERPTR
|
4599 CPUID_8000_0008_EBX_WBNOINVD
| CPUID_8000_0008_EBX_IBPB
|
4600 CPUID_8000_0008_EBX_IBRS
| CPUID_8000_0008_EBX_STIBP
|
4601 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON
|
4602 CPUID_8000_0008_EBX_AMD_SSBD
| CPUID_8000_0008_EBX_AMD_PSFD
,
4603 .features
[FEAT_8000_0021_EAX
] =
4604 CPUID_8000_0021_EAX_No_NESTED_DATA_BP
|
4605 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING
|
4606 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE
|
4607 CPUID_8000_0021_EAX_AUTO_IBRS
,
4608 .features
[FEAT_7_0_EBX
] =
4609 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4610 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
|
4611 CPUID_7_0_EBX_INVPCID
| CPUID_7_0_EBX_AVX512F
|
4612 CPUID_7_0_EBX_AVX512DQ
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
4613 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_AVX512IFMA
|
4614 CPUID_7_0_EBX_CLFLUSHOPT
| CPUID_7_0_EBX_CLWB
|
4615 CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_SHA_NI
|
4616 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512VL
,
4617 .features
[FEAT_7_0_ECX
] =
4618 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
4619 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
4620 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
4621 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
4622 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
|
4623 CPUID_7_0_ECX_RDPID
,
4624 .features
[FEAT_7_0_EDX
] =
4626 .features
[FEAT_7_1_EAX
] =
4627 CPUID_7_1_EAX_AVX512_BF16
,
4628 .features
[FEAT_XSAVE
] =
4629 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4630 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
,
4631 .features
[FEAT_6_EAX
] =
4633 .features
[FEAT_SVM
] =
4634 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
| CPUID_SVM_VNMI
|
4635 CPUID_SVM_SVME_ADDR_CHK
,
4636 .xlevel
= 0x80000022,
4637 .model_id
= "AMD EPYC-Genoa Processor",
4638 .cache_info
= &epyc_genoa_cache_info
,
4643 * We resolve CPU model aliases using -v1 when using "-machine
4644 * none", but this is just for compatibility while libvirt isn't
4645 * adapted to resolve CPU model versions before creating VMs.
4646 * See "Runnability guarantee of CPU models" at
4647 * docs/about/deprecated.rst.
4649 X86CPUVersion default_cpu_version
= 1;
4651 void x86_cpu_set_default_version(X86CPUVersion version
)
4653 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4654 assert(version
!= CPU_VERSION_AUTO
);
4655 default_cpu_version
= version
;
4658 static X86CPUVersion
x86_cpu_model_last_version(const X86CPUModel
*model
)
4661 const X86CPUVersionDefinition
*vdef
=
4662 x86_cpu_def_get_versions(model
->cpudef
);
4663 while (vdef
->version
) {
4670 /* Return the actual version being used for a specific CPU model */
4671 static X86CPUVersion
x86_cpu_model_resolve_version(const X86CPUModel
*model
)
4673 X86CPUVersion v
= model
->version
;
4674 if (v
== CPU_VERSION_AUTO
) {
4675 v
= default_cpu_version
;
4677 if (v
== CPU_VERSION_LATEST
) {
4678 return x86_cpu_model_last_version(model
);
4683 static Property max_x86_cpu_properties
[] = {
4684 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
4685 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
4686 DEFINE_PROP_END_OF_LIST()
4689 static void max_x86_cpu_realize(DeviceState
*dev
, Error
**errp
)
4691 Object
*obj
= OBJECT(dev
);
4693 if (!object_property_get_int(obj
, "family", &error_abort
)) {
4694 if (X86_CPU(obj
)->env
.features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
4695 object_property_set_int(obj
, "family", 15, &error_abort
);
4696 object_property_set_int(obj
, "model", 107, &error_abort
);
4697 object_property_set_int(obj
, "stepping", 1, &error_abort
);
4699 object_property_set_int(obj
, "family", 6, &error_abort
);
4700 object_property_set_int(obj
, "model", 6, &error_abort
);
4701 object_property_set_int(obj
, "stepping", 3, &error_abort
);
4705 x86_cpu_realizefn(dev
, errp
);
4708 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
4710 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4711 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4715 xcc
->model_description
=
4716 "Enables all features supported by the accelerator in the current host";
4718 device_class_set_props(dc
, max_x86_cpu_properties
);
4719 dc
->realize
= max_x86_cpu_realize
;
4722 static void max_x86_cpu_initfn(Object
*obj
)
4724 X86CPU
*cpu
= X86_CPU(obj
);
4726 /* We can't fill the features array here because we don't know yet if
4727 * "migratable" is true or false.
4729 cpu
->max_features
= true;
4730 object_property_set_bool(OBJECT(cpu
), "pmu", true, &error_abort
);
4733 * these defaults are used for TCG and all other accelerators
4734 * besides KVM and HVF, which overwrite these values
4736 object_property_set_str(OBJECT(cpu
), "vendor", CPUID_VENDOR_AMD
,
4738 object_property_set_str(OBJECT(cpu
), "model-id",
4739 "QEMU TCG CPU version " QEMU_HW_VERSION
,
4743 static const TypeInfo max_x86_cpu_type_info
= {
4744 .name
= X86_CPU_TYPE_NAME("max"),
4745 .parent
= TYPE_X86_CPU
,
4746 .instance_init
= max_x86_cpu_initfn
,
4747 .class_init
= max_x86_cpu_class_init
,
4750 static char *feature_word_description(FeatureWordInfo
*f
, uint32_t bit
)
4752 assert(f
->type
== CPUID_FEATURE_WORD
|| f
->type
== MSR_FEATURE_WORD
);
4755 case CPUID_FEATURE_WORD
:
4757 const char *reg
= get_register_name_32(f
->cpuid
.reg
);
4759 return g_strdup_printf("CPUID.%02XH:%s",
4762 case MSR_FEATURE_WORD
:
4763 return g_strdup_printf("MSR(%02XH)",
4770 static bool x86_cpu_have_filtered_features(X86CPU
*cpu
)
4774 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4775 if (cpu
->filtered_features
[w
]) {
4783 static void mark_unavailable_features(X86CPU
*cpu
, FeatureWord w
, uint64_t mask
,
4784 const char *verbose_prefix
)
4786 CPUX86State
*env
= &cpu
->env
;
4787 FeatureWordInfo
*f
= &feature_word_info
[w
];
4790 if (!cpu
->force_features
) {
4791 env
->features
[w
] &= ~mask
;
4793 cpu
->filtered_features
[w
] |= mask
;
4795 if (!verbose_prefix
) {
4799 for (i
= 0; i
< 64; ++i
) {
4800 if ((1ULL << i
) & mask
) {
4801 g_autofree
char *feat_word_str
= feature_word_description(f
, i
);
4802 warn_report("%s: %s%s%s [bit %d]",
4805 f
->feat_names
[i
] ? "." : "",
4806 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
4811 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
4812 const char *name
, void *opaque
,
4815 X86CPU
*cpu
= X86_CPU(obj
);
4816 CPUX86State
*env
= &cpu
->env
;
4819 value
= (env
->cpuid_version
>> 8) & 0xf;
4821 value
+= (env
->cpuid_version
>> 20) & 0xff;
4823 visit_type_int(v
, name
, &value
, errp
);
4826 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
4827 const char *name
, void *opaque
,
4830 X86CPU
*cpu
= X86_CPU(obj
);
4831 CPUX86State
*env
= &cpu
->env
;
4832 const int64_t min
= 0;
4833 const int64_t max
= 0xff + 0xf;
4836 if (!visit_type_int(v
, name
, &value
, errp
)) {
4839 if (value
< min
|| value
> max
) {
4840 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4841 name
? name
: "null", value
, min
, max
);
4845 env
->cpuid_version
&= ~0xff00f00;
4847 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
4849 env
->cpuid_version
|= value
<< 8;
4853 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
4854 const char *name
, void *opaque
,
4857 X86CPU
*cpu
= X86_CPU(obj
);
4858 CPUX86State
*env
= &cpu
->env
;
4861 value
= (env
->cpuid_version
>> 4) & 0xf;
4862 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
4863 visit_type_int(v
, name
, &value
, errp
);
4866 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
4867 const char *name
, void *opaque
,
4870 X86CPU
*cpu
= X86_CPU(obj
);
4871 CPUX86State
*env
= &cpu
->env
;
4872 const int64_t min
= 0;
4873 const int64_t max
= 0xff;
4876 if (!visit_type_int(v
, name
, &value
, errp
)) {
4879 if (value
< min
|| value
> max
) {
4880 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4881 name
? name
: "null", value
, min
, max
);
4885 env
->cpuid_version
&= ~0xf00f0;
4886 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
4889 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
4890 const char *name
, void *opaque
,
4893 X86CPU
*cpu
= X86_CPU(obj
);
4894 CPUX86State
*env
= &cpu
->env
;
4897 value
= env
->cpuid_version
& 0xf;
4898 visit_type_int(v
, name
, &value
, errp
);
4901 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
4902 const char *name
, void *opaque
,
4905 X86CPU
*cpu
= X86_CPU(obj
);
4906 CPUX86State
*env
= &cpu
->env
;
4907 const int64_t min
= 0;
4908 const int64_t max
= 0xf;
4911 if (!visit_type_int(v
, name
, &value
, errp
)) {
4914 if (value
< min
|| value
> max
) {
4915 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4916 name
? name
: "null", value
, min
, max
);
4920 env
->cpuid_version
&= ~0xf;
4921 env
->cpuid_version
|= value
& 0xf;
4924 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
4926 X86CPU
*cpu
= X86_CPU(obj
);
4927 CPUX86State
*env
= &cpu
->env
;
4930 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
4931 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
4932 env
->cpuid_vendor3
);
4936 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
4939 X86CPU
*cpu
= X86_CPU(obj
);
4940 CPUX86State
*env
= &cpu
->env
;
4943 if (strlen(value
) != CPUID_VENDOR_SZ
) {
4944 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
4948 env
->cpuid_vendor1
= 0;
4949 env
->cpuid_vendor2
= 0;
4950 env
->cpuid_vendor3
= 0;
4951 for (i
= 0; i
< 4; i
++) {
4952 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
4953 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
4954 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
4958 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
4960 X86CPU
*cpu
= X86_CPU(obj
);
4961 CPUX86State
*env
= &cpu
->env
;
4965 value
= g_malloc(48 + 1);
4966 for (i
= 0; i
< 48; i
++) {
4967 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
4973 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
4976 X86CPU
*cpu
= X86_CPU(obj
);
4977 CPUX86State
*env
= &cpu
->env
;
4980 if (model_id
== NULL
) {
4983 len
= strlen(model_id
);
4984 memset(env
->cpuid_model
, 0, 48);
4985 for (i
= 0; i
< 48; i
++) {
4989 c
= (uint8_t)model_id
[i
];
4991 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
4995 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
4996 void *opaque
, Error
**errp
)
4998 X86CPU
*cpu
= X86_CPU(obj
);
5001 value
= cpu
->env
.tsc_khz
* 1000;
5002 visit_type_int(v
, name
, &value
, errp
);
5005 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
5006 void *opaque
, Error
**errp
)
5008 X86CPU
*cpu
= X86_CPU(obj
);
5009 const int64_t min
= 0;
5010 const int64_t max
= INT64_MAX
;
5013 if (!visit_type_int(v
, name
, &value
, errp
)) {
5016 if (value
< min
|| value
> max
) {
5017 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
5018 name
? name
: "null", value
, min
, max
);
5022 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
5025 /* Generic getter for "feature-words" and "filtered-features" properties */
5026 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
5027 const char *name
, void *opaque
,
5030 uint64_t *array
= (uint64_t *)opaque
;
5032 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
5033 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
5034 X86CPUFeatureWordInfoList
*list
= NULL
;
5036 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5037 FeatureWordInfo
*wi
= &feature_word_info
[w
];
5039 * We didn't have MSR features when "feature-words" was
5040 * introduced. Therefore skipped other type entries.
5042 if (wi
->type
!= CPUID_FEATURE_WORD
) {
5045 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
5046 qwi
->cpuid_input_eax
= wi
->cpuid
.eax
;
5047 qwi
->has_cpuid_input_ecx
= wi
->cpuid
.needs_ecx
;
5048 qwi
->cpuid_input_ecx
= wi
->cpuid
.ecx
;
5049 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid
.reg
].qapi_enum
;
5050 qwi
->features
= array
[w
];
5052 /* List will be in reverse order, but order shouldn't matter */
5053 list_entries
[w
].next
= list
;
5054 list_entries
[w
].value
= &word_infos
[w
];
5055 list
= &list_entries
[w
];
5058 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
5061 /* Convert all '_' in a feature string option name to '-', to make feature
5062 * name conform to QOM property naming rule, which uses '-' instead of '_'.
5064 static inline void feat2prop(char *s
)
5066 while ((s
= strchr(s
, '_'))) {
5071 /* Return the feature property name for a feature flag bit */
5072 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
5075 /* XSAVE components are automatically enabled by other features,
5076 * so return the original feature name instead
5078 if (w
== FEAT_XSAVE_XCR0_LO
|| w
== FEAT_XSAVE_XCR0_HI
) {
5079 int comp
= (w
== FEAT_XSAVE_XCR0_HI
) ? bitnr
+ 32 : bitnr
;
5081 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
5082 x86_ext_save_areas
[comp
].bits
) {
5083 w
= x86_ext_save_areas
[comp
].feature
;
5084 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
5089 assert(w
< FEATURE_WORDS
);
5090 name
= feature_word_info
[w
].feat_names
[bitnr
];
5091 assert(bitnr
< 32 || !(name
&& feature_word_info
[w
].type
== CPUID_FEATURE_WORD
));
5095 /* Compatibily hack to maintain legacy +-feat semantic,
5096 * where +-feat overwrites any feature set by
5097 * feat=on|feat even if the later is parsed after +-feat
5098 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
5100 static GList
*plus_features
, *minus_features
;
5102 static gint
compare_string(gconstpointer a
, gconstpointer b
)
5104 return g_strcmp0(a
, b
);
5107 /* Parse "+feature,-feature,feature=foo" CPU feature string
5109 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
5112 char *featurestr
; /* Single 'key=value" string being parsed */
5113 static bool cpu_globals_initialized
;
5114 bool ambiguous
= false;
5116 if (cpu_globals_initialized
) {
5119 cpu_globals_initialized
= true;
5125 for (featurestr
= strtok(features
, ",");
5127 featurestr
= strtok(NULL
, ",")) {
5129 const char *val
= NULL
;
5132 GlobalProperty
*prop
;
5134 /* Compatibility syntax: */
5135 if (featurestr
[0] == '+') {
5136 plus_features
= g_list_append(plus_features
,
5137 g_strdup(featurestr
+ 1));
5139 } else if (featurestr
[0] == '-') {
5140 minus_features
= g_list_append(minus_features
,
5141 g_strdup(featurestr
+ 1));
5145 eq
= strchr(featurestr
, '=');
5153 feat2prop(featurestr
);
5156 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
5157 warn_report("Ambiguous CPU model string. "
5158 "Don't mix both \"+%s\" and \"%s=%s\"",
5162 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
5163 warn_report("Ambiguous CPU model string. "
5164 "Don't mix both \"-%s\" and \"%s=%s\"",
5170 if (!strcmp(name
, "tsc-freq")) {
5174 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
5175 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
5176 error_setg(errp
, "bad numerical value %s", val
);
5179 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
5181 name
= "tsc-frequency";
5184 prop
= g_new0(typeof(*prop
), 1);
5185 prop
->driver
= typename
;
5186 prop
->property
= g_strdup(name
);
5187 prop
->value
= g_strdup(val
);
5188 qdev_prop_register_global(prop
);
5192 warn_report("Compatibility of ambiguous CPU model "
5193 "strings won't be kept on future QEMU versions");
5197 static void x86_cpu_filter_features(X86CPU
*cpu
, bool verbose
);
5199 /* Build a list with the name of all features on a feature word array */
5200 static void x86_cpu_list_feature_names(FeatureWordArray features
,
5203 strList
**tail
= list
;
5206 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5207 uint64_t filtered
= features
[w
];
5209 for (i
= 0; i
< 64; i
++) {
5210 if (filtered
& (1ULL << i
)) {
5211 QAPI_LIST_APPEND(tail
, g_strdup(x86_cpu_feature_name(w
, i
)));
5217 static void x86_cpu_get_unavailable_features(Object
*obj
, Visitor
*v
,
5218 const char *name
, void *opaque
,
5221 X86CPU
*xc
= X86_CPU(obj
);
5222 strList
*result
= NULL
;
5224 x86_cpu_list_feature_names(xc
->filtered_features
, &result
);
5225 visit_type_strList(v
, "unavailable-features", &result
, errp
);
5228 /* Print all cpuid feature names in featureset
5230 static void listflags(GList
*features
)
5235 for (tmp
= features
; tmp
; tmp
= tmp
->next
) {
5236 const char *name
= tmp
->data
;
5237 if ((len
+ strlen(name
) + 1) >= 75) {
5241 qemu_printf("%s%s", len
== 0 ? " " : " ", name
);
5242 len
+= strlen(name
) + 1;
5247 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
5248 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5250 ObjectClass
*class_a
= (ObjectClass
*)a
;
5251 ObjectClass
*class_b
= (ObjectClass
*)b
;
5252 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
5253 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
5256 if (cc_a
->ordering
!= cc_b
->ordering
) {
5257 ret
= cc_a
->ordering
- cc_b
->ordering
;
5259 g_autofree
char *name_a
= x86_cpu_class_get_model_name(cc_a
);
5260 g_autofree
char *name_b
= x86_cpu_class_get_model_name(cc_b
);
5261 ret
= strcmp(name_a
, name_b
);
5266 static GSList
*get_sorted_cpu_model_list(void)
5268 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
5269 list
= g_slist_sort(list
, x86_cpu_list_compare
);
5273 static char *x86_cpu_class_get_model_id(X86CPUClass
*xc
)
5275 Object
*obj
= object_new_with_class(OBJECT_CLASS(xc
));
5276 char *r
= object_property_get_str(obj
, "model-id", &error_abort
);
5281 static char *x86_cpu_class_get_alias_of(X86CPUClass
*cc
)
5283 X86CPUVersion version
;
5285 if (!cc
->model
|| !cc
->model
->is_alias
) {
5288 version
= x86_cpu_model_resolve_version(cc
->model
);
5292 return x86_cpu_versioned_model_name(cc
->model
->cpudef
, version
);
5295 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
5297 ObjectClass
*oc
= data
;
5298 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
5299 g_autofree
char *name
= x86_cpu_class_get_model_name(cc
);
5300 g_autofree
char *desc
= g_strdup(cc
->model_description
);
5301 g_autofree
char *alias_of
= x86_cpu_class_get_alias_of(cc
);
5302 g_autofree
char *model_id
= x86_cpu_class_get_model_id(cc
);
5304 if (!desc
&& alias_of
) {
5305 if (cc
->model
&& cc
->model
->version
== CPU_VERSION_AUTO
) {
5306 desc
= g_strdup("(alias configured by machine type)");
5308 desc
= g_strdup_printf("(alias of %s)", alias_of
);
5311 if (!desc
&& cc
->model
&& cc
->model
->note
) {
5312 desc
= g_strdup_printf("%s [%s]", model_id
, cc
->model
->note
);
5315 desc
= g_strdup_printf("%s", model_id
);
5318 if (cc
->model
&& cc
->model
->cpudef
->deprecation_note
) {
5319 g_autofree
char *olddesc
= desc
;
5320 desc
= g_strdup_printf("%s (deprecated)", olddesc
);
5323 qemu_printf("x86 %-20s %s\n", name
, desc
);
5326 /* list available CPU models and flags */
5327 void x86_cpu_list(void)
5331 GList
*names
= NULL
;
5333 qemu_printf("Available CPUs:\n");
5334 list
= get_sorted_cpu_model_list();
5335 g_slist_foreach(list
, x86_cpu_list_entry
, NULL
);
5339 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
5340 FeatureWordInfo
*fw
= &feature_word_info
[i
];
5341 for (j
= 0; j
< 64; j
++) {
5342 if (fw
->feat_names
[j
]) {
5343 names
= g_list_append(names
, (gpointer
)fw
->feat_names
[j
]);
5348 names
= g_list_sort(names
, (GCompareFunc
)strcmp
);
5350 qemu_printf("\nRecognized CPUID flags:\n");
5356 #ifndef CONFIG_USER_ONLY
5358 /* Check for missing features that may prevent the CPU class from
5359 * running using the current machine and accelerator.
5361 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
5364 strList
**tail
= list
;
5368 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
5369 QAPI_LIST_APPEND(tail
, g_strdup("kvm"));
5373 xc
= X86_CPU(object_new_with_class(OBJECT_CLASS(xcc
)));
5375 x86_cpu_expand_features(xc
, &err
);
5377 /* Errors at x86_cpu_expand_features should never happen,
5378 * but in case it does, just report the model as not
5379 * runnable at all using the "type" property.
5381 QAPI_LIST_APPEND(tail
, g_strdup("type"));
5385 x86_cpu_filter_features(xc
, false);
5387 x86_cpu_list_feature_names(xc
->filtered_features
, tail
);
5389 object_unref(OBJECT(xc
));
5392 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
5394 ObjectClass
*oc
= data
;
5395 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
5396 CpuDefinitionInfoList
**cpu_list
= user_data
;
5397 CpuDefinitionInfo
*info
;
5399 info
= g_malloc0(sizeof(*info
));
5400 info
->name
= x86_cpu_class_get_model_name(cc
);
5401 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
5402 info
->has_unavailable_features
= true;
5403 info
->q_typename
= g_strdup(object_class_get_name(oc
));
5404 info
->migration_safe
= cc
->migration_safe
;
5405 info
->has_migration_safe
= true;
5406 info
->q_static
= cc
->static_model
;
5407 if (cc
->model
&& cc
->model
->cpudef
->deprecation_note
) {
5408 info
->deprecated
= true;
5410 info
->deprecated
= false;
5413 * Old machine types won't report aliases, so that alias translation
5414 * doesn't break compatibility with previous QEMU versions.
5416 if (default_cpu_version
!= CPU_VERSION_LEGACY
) {
5417 info
->alias_of
= x86_cpu_class_get_alias_of(cc
);
5420 QAPI_LIST_PREPEND(*cpu_list
, info
);
5423 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
5425 CpuDefinitionInfoList
*cpu_list
= NULL
;
5426 GSList
*list
= get_sorted_cpu_model_list();
5427 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
5432 #endif /* !CONFIG_USER_ONLY */
5434 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w
,
5435 bool migratable_only
)
5437 FeatureWordInfo
*wi
= &feature_word_info
[w
];
5440 if (kvm_enabled()) {
5442 case CPUID_FEATURE_WORD
:
5443 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid
.eax
,
5447 case MSR_FEATURE_WORD
:
5448 r
= kvm_arch_get_supported_msr_feature(kvm_state
,
5452 } else if (hvf_enabled()) {
5453 if (wi
->type
!= CPUID_FEATURE_WORD
) {
5456 r
= hvf_get_supported_cpuid(wi
->cpuid
.eax
,
5459 } else if (tcg_enabled()) {
5460 r
= wi
->tcg_features
;
5464 #ifndef TARGET_X86_64
5465 if (w
== FEAT_8000_0001_EDX
) {
5466 r
&= ~CPUID_EXT2_LM
;
5469 if (migratable_only
) {
5470 r
&= x86_cpu_get_migratable_flags(w
);
5475 static void x86_cpu_get_supported_cpuid(uint32_t func
, uint32_t index
,
5476 uint32_t *eax
, uint32_t *ebx
,
5477 uint32_t *ecx
, uint32_t *edx
)
5479 if (kvm_enabled()) {
5480 *eax
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_EAX
);
5481 *ebx
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_EBX
);
5482 *ecx
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_ECX
);
5483 *edx
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_EDX
);
5484 } else if (hvf_enabled()) {
5485 *eax
= hvf_get_supported_cpuid(func
, index
, R_EAX
);
5486 *ebx
= hvf_get_supported_cpuid(func
, index
, R_EBX
);
5487 *ecx
= hvf_get_supported_cpuid(func
, index
, R_ECX
);
5488 *edx
= hvf_get_supported_cpuid(func
, index
, R_EDX
);
5497 static void x86_cpu_get_cache_cpuid(uint32_t func
, uint32_t index
,
5498 uint32_t *eax
, uint32_t *ebx
,
5499 uint32_t *ecx
, uint32_t *edx
)
5501 uint32_t level
, unused
;
5503 /* Only return valid host leaves. */
5507 host_cpuid(0, 0, &level
, &unused
, &unused
, &unused
);
5512 host_cpuid(0x80000000, 0, &level
, &unused
, &unused
, &unused
);
5524 host_cpuid(func
, index
, eax
, ebx
, ecx
, edx
);
5529 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5531 void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
5534 for (pv
= props
; pv
->prop
; pv
++) {
5538 object_property_parse(OBJECT(cpu
), pv
->prop
, pv
->value
,
5544 * Apply properties for the CPU model version specified in model.
5545 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5548 static void x86_cpu_apply_version_props(X86CPU
*cpu
, X86CPUModel
*model
)
5550 const X86CPUVersionDefinition
*vdef
;
5551 X86CPUVersion version
= x86_cpu_model_resolve_version(model
);
5553 if (version
== CPU_VERSION_LEGACY
) {
5557 for (vdef
= x86_cpu_def_get_versions(model
->cpudef
); vdef
->version
; vdef
++) {
5560 for (p
= vdef
->props
; p
&& p
->prop
; p
++) {
5561 object_property_parse(OBJECT(cpu
), p
->prop
, p
->value
,
5565 if (vdef
->version
== version
) {
5571 * If we reached the end of the list, version number was invalid
5573 assert(vdef
->version
== version
);
5576 static const CPUCaches
*x86_cpu_get_versioned_cache_info(X86CPU
*cpu
,
5579 const X86CPUVersionDefinition
*vdef
;
5580 X86CPUVersion version
= x86_cpu_model_resolve_version(model
);
5581 const CPUCaches
*cache_info
= model
->cpudef
->cache_info
;
5583 if (version
== CPU_VERSION_LEGACY
) {
5587 for (vdef
= x86_cpu_def_get_versions(model
->cpudef
); vdef
->version
; vdef
++) {
5588 if (vdef
->cache_info
) {
5589 cache_info
= vdef
->cache_info
;
5592 if (vdef
->version
== version
) {
5597 assert(vdef
->version
== version
);
5602 * Load data from X86CPUDefinition into a X86CPU object.
5603 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5605 static void x86_cpu_load_model(X86CPU
*cpu
, X86CPUModel
*model
)
5607 const X86CPUDefinition
*def
= model
->cpudef
;
5608 CPUX86State
*env
= &cpu
->env
;
5611 /*NOTE: any property set by this function should be returned by
5612 * x86_cpu_static_props(), so static expansion of
5613 * query-cpu-model-expansion is always complete.
5616 /* CPU models only set _minimum_ values for level/xlevel: */
5617 object_property_set_uint(OBJECT(cpu
), "min-level", def
->level
,
5619 object_property_set_uint(OBJECT(cpu
), "min-xlevel", def
->xlevel
,
5622 object_property_set_int(OBJECT(cpu
), "family", def
->family
, &error_abort
);
5623 object_property_set_int(OBJECT(cpu
), "model", def
->model
, &error_abort
);
5624 object_property_set_int(OBJECT(cpu
), "stepping", def
->stepping
,
5626 object_property_set_str(OBJECT(cpu
), "model-id", def
->model_id
,
5628 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5629 env
->features
[w
] = def
->features
[w
];
5632 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5633 cpu
->legacy_cache
= !x86_cpu_get_versioned_cache_info(cpu
, model
);
5635 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
5637 /* sysenter isn't supported in compatibility mode on AMD,
5638 * syscall isn't supported in compatibility mode on Intel.
5639 * Normally we advertise the actual CPU vendor, but you can
5640 * override this using the 'vendor' property if you want to use
5641 * KVM's sysenter/syscall emulation in compatibility mode and
5642 * when doing cross vendor migration
5646 * vendor property is set here but then overloaded with the
5647 * host cpu vendor for KVM and HVF.
5649 object_property_set_str(OBJECT(cpu
), "vendor", def
->vendor
, &error_abort
);
5651 x86_cpu_apply_version_props(cpu
, model
);
5654 * Properties in versioned CPU model are not user specified features.
5655 * We can simply clear env->user_features here since it will be filled later
5656 * in x86_cpu_expand_features() based on plus_features and minus_features.
5658 memset(&env
->user_features
, 0, sizeof(env
->user_features
));
5661 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
5663 #ifdef TARGET_X86_64
5664 return g_strdup("i386:x86-64");
5666 return g_strdup("i386");
5670 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
5672 X86CPUModel
*model
= data
;
5673 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
5674 CPUClass
*cc
= CPU_CLASS(oc
);
5677 xcc
->migration_safe
= true;
5678 cc
->deprecation_note
= model
->cpudef
->deprecation_note
;
5681 static void x86_register_cpu_model_type(const char *name
, X86CPUModel
*model
)
5683 g_autofree
char *typename
= x86_cpu_type_name(name
);
5686 .parent
= TYPE_X86_CPU
,
5687 .class_init
= x86_cpu_cpudef_class_init
,
5688 .class_data
= model
,
5696 * register builtin_x86_defs;
5697 * "max", "base" and subclasses ("host") are not registered here.
5698 * See x86_cpu_register_types for all model registrations.
5700 static void x86_register_cpudef_types(const X86CPUDefinition
*def
)
5703 const X86CPUVersionDefinition
*vdef
;
5705 /* AMD aliases are handled at runtime based on CPUID vendor, so
5706 * they shouldn't be set on the CPU model table.
5708 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
5709 /* catch mistakes instead of silently truncating model_id when too long */
5710 assert(def
->model_id
&& strlen(def
->model_id
) <= 48);
5712 /* Unversioned model: */
5713 m
= g_new0(X86CPUModel
, 1);
5715 m
->version
= CPU_VERSION_AUTO
;
5717 x86_register_cpu_model_type(def
->name
, m
);
5719 /* Versioned models: */
5721 for (vdef
= x86_cpu_def_get_versions(def
); vdef
->version
; vdef
++) {
5722 X86CPUModel
*m
= g_new0(X86CPUModel
, 1);
5723 g_autofree
char *name
=
5724 x86_cpu_versioned_model_name(def
, vdef
->version
);
5726 m
->version
= vdef
->version
;
5727 m
->note
= vdef
->note
;
5728 x86_register_cpu_model_type(name
, m
);
5731 X86CPUModel
*am
= g_new0(X86CPUModel
, 1);
5733 am
->version
= vdef
->version
;
5734 am
->is_alias
= true;
5735 x86_register_cpu_model_type(vdef
->alias
, am
);
5741 uint32_t cpu_x86_virtual_addr_width(CPUX86State
*env
)
5743 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
5744 return 57; /* 57 bits virtual */
5746 return 48; /* 48 bits virtual */
5750 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
5751 uint32_t *eax
, uint32_t *ebx
,
5752 uint32_t *ecx
, uint32_t *edx
)
5754 X86CPU
*cpu
= env_archcpu(env
);
5755 CPUState
*cs
= env_cpu(env
);
5756 uint32_t die_offset
;
5758 uint32_t signature
[3];
5759 X86CPUTopoInfo topo_info
;
5761 topo_info
.dies_per_pkg
= env
->nr_dies
;
5762 topo_info
.cores_per_die
= cs
->nr_cores
;
5763 topo_info
.threads_per_core
= cs
->nr_threads
;
5765 /* Calculate & apply limits for different index ranges */
5766 if (index
>= 0xC0000000) {
5767 limit
= env
->cpuid_xlevel2
;
5768 } else if (index
>= 0x80000000) {
5769 limit
= env
->cpuid_xlevel
;
5770 } else if (index
>= 0x40000000) {
5773 limit
= env
->cpuid_level
;
5776 if (index
> limit
) {
5777 /* Intel documentation states that invalid EAX input will
5778 * return the same information as EAX=cpuid_level
5779 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5781 index
= env
->cpuid_level
;
5786 *eax
= env
->cpuid_level
;
5787 *ebx
= env
->cpuid_vendor1
;
5788 *edx
= env
->cpuid_vendor2
;
5789 *ecx
= env
->cpuid_vendor3
;
5792 *eax
= env
->cpuid_version
;
5793 *ebx
= (cpu
->apic_id
<< 24) |
5794 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5795 *ecx
= env
->features
[FEAT_1_ECX
];
5796 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
5797 *ecx
|= CPUID_EXT_OSXSAVE
;
5799 *edx
= env
->features
[FEAT_1_EDX
];
5800 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
5801 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
5804 if (!cpu
->enable_pmu
) {
5805 *ecx
&= ~CPUID_EXT_PDCM
;
5809 /* cache info: needed for Pentium Pro compatibility */
5810 if (cpu
->cache_info_passthrough
) {
5811 x86_cpu_get_cache_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
5813 } else if (cpu
->vendor_cpuid_only
&& IS_AMD_CPU(env
)) {
5814 *eax
= *ebx
= *ecx
= *edx
= 0;
5817 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
5819 if (!cpu
->enable_l3_cache
) {
5822 *ecx
= cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l3_cache
);
5824 *edx
= (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1d_cache
) << 16) |
5825 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1i_cache
) << 8) |
5826 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l2_cache
));
5829 /* cache info: needed for Core compatibility */
5830 if (cpu
->cache_info_passthrough
) {
5831 x86_cpu_get_cache_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
5833 * QEMU has its own number of cores/logical cpus,
5834 * set 24..14, 31..26 bit to configured values
5837 int host_vcpus_per_cache
= 1 + ((*eax
& 0x3FFC000) >> 14);
5838 int vcpus_per_socket
= env
->nr_dies
* cs
->nr_cores
*
5840 if (cs
->nr_cores
> 1) {
5841 *eax
&= ~0xFC000000;
5842 *eax
|= (pow2ceil(cs
->nr_cores
) - 1) << 26;
5844 if (host_vcpus_per_cache
> vcpus_per_socket
) {
5846 *eax
|= (pow2ceil(vcpus_per_socket
) - 1) << 14;
5849 } else if (cpu
->vendor_cpuid_only
&& IS_AMD_CPU(env
)) {
5850 *eax
= *ebx
= *ecx
= *edx
= 0;
5854 case 0: /* L1 dcache info */
5855 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1d_cache
,
5857 eax
, ebx
, ecx
, edx
);
5859 case 1: /* L1 icache info */
5860 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1i_cache
,
5862 eax
, ebx
, ecx
, edx
);
5864 case 2: /* L2 cache info */
5865 encode_cache_cpuid4(env
->cache_info_cpuid4
.l2_cache
,
5866 cs
->nr_threads
, cs
->nr_cores
,
5867 eax
, ebx
, ecx
, edx
);
5869 case 3: /* L3 cache info */
5870 die_offset
= apicid_die_offset(&topo_info
);
5871 if (cpu
->enable_l3_cache
) {
5872 encode_cache_cpuid4(env
->cache_info_cpuid4
.l3_cache
,
5873 (1 << die_offset
), cs
->nr_cores
,
5874 eax
, ebx
, ecx
, edx
);
5878 default: /* end of info */
5879 *eax
= *ebx
= *ecx
= *edx
= 0;
5885 /* MONITOR/MWAIT Leaf */
5886 *eax
= cpu
->mwait
.eax
; /* Smallest monitor-line size in bytes */
5887 *ebx
= cpu
->mwait
.ebx
; /* Largest monitor-line size in bytes */
5888 *ecx
= cpu
->mwait
.ecx
; /* flags */
5889 *edx
= cpu
->mwait
.edx
; /* mwait substates */
5892 /* Thermal and Power Leaf */
5893 *eax
= env
->features
[FEAT_6_EAX
];
5899 /* Structured Extended Feature Flags Enumeration Leaf */
5901 /* Maximum ECX value for sub-leaves */
5902 *eax
= env
->cpuid_level_func7
;
5903 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
5904 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
5905 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
5906 *ecx
|= CPUID_7_0_ECX_OSPKE
;
5908 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
5911 * SGX cannot be emulated in software. If hardware does not
5912 * support enabling SGX and/or SGX flexible launch control,
5913 * then we need to update the VM's CPUID values accordingly.
5915 if ((*ebx
& CPUID_7_0_EBX_SGX
) &&
5917 !(kvm_arch_get_supported_cpuid(cs
->kvm_state
, 0x7, 0, R_EBX
) &
5918 CPUID_7_0_EBX_SGX
))) {
5919 *ebx
&= ~CPUID_7_0_EBX_SGX
;
5922 if ((*ecx
& CPUID_7_0_ECX_SGX_LC
) &&
5923 (!(*ebx
& CPUID_7_0_EBX_SGX
) || !kvm_enabled() ||
5924 !(kvm_arch_get_supported_cpuid(cs
->kvm_state
, 0x7, 0, R_ECX
) &
5925 CPUID_7_0_ECX_SGX_LC
))) {
5926 *ecx
&= ~CPUID_7_0_ECX_SGX_LC
;
5928 } else if (count
== 1) {
5929 *eax
= env
->features
[FEAT_7_1_EAX
];
5930 *edx
= env
->features
[FEAT_7_1_EDX
];
5941 /* Direct Cache Access Information Leaf */
5942 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
5948 /* Architectural Performance Monitoring Leaf */
5949 if (accel_uses_host_cpuid() && cpu
->enable_pmu
) {
5950 x86_cpu_get_supported_cpuid(0xA, count
, eax
, ebx
, ecx
, edx
);
5959 /* Extended Topology Enumeration Leaf */
5960 if (!cpu
->enable_cpuid_0xb
) {
5961 *eax
= *ebx
= *ecx
= *edx
= 0;
5965 *ecx
= count
& 0xff;
5966 *edx
= cpu
->apic_id
;
5970 *eax
= apicid_core_offset(&topo_info
);
5971 *ebx
= cs
->nr_threads
;
5972 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
5975 *eax
= apicid_pkg_offset(&topo_info
);
5976 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
5977 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
5982 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
5985 assert(!(*eax
& ~0x1f));
5986 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
5989 if (accel_uses_host_cpuid() && cpu
->enable_pmu
&&
5990 (env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_ARCH_LBR
)) {
5991 x86_cpu_get_supported_cpuid(0x1C, 0, eax
, ebx
, ecx
, edx
);
5996 /* V2 Extended Topology Enumeration Leaf */
5997 if (env
->nr_dies
< 2) {
5998 *eax
= *ebx
= *ecx
= *edx
= 0;
6002 *ecx
= count
& 0xff;
6003 *edx
= cpu
->apic_id
;
6006 *eax
= apicid_core_offset(&topo_info
);
6007 *ebx
= cs
->nr_threads
;
6008 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
6011 *eax
= apicid_die_offset(&topo_info
);
6012 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
6013 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
6016 *eax
= apicid_pkg_offset(&topo_info
);
6017 *ebx
= env
->nr_dies
* cs
->nr_cores
* cs
->nr_threads
;
6018 *ecx
|= CPUID_TOPOLOGY_LEVEL_DIE
;
6023 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
6025 assert(!(*eax
& ~0x1f));
6026 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
6029 /* Processor Extended State */
6034 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
6039 *ecx
= xsave_area_size(x86_cpu_xsave_xcr0_components(cpu
), false);
6040 *eax
= env
->features
[FEAT_XSAVE_XCR0_LO
];
6041 *edx
= env
->features
[FEAT_XSAVE_XCR0_HI
];
6043 * The initial value of xcr0 and ebx == 0, On host without kvm
6044 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
6045 * even through guest update xcr0, this will crash some legacy guest
6046 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
6048 *ebx
= kvm_enabled() ? *ecx
: xsave_area_size(env
->xcr0
, false);
6049 } else if (count
== 1) {
6050 uint64_t xstate
= x86_cpu_xsave_xcr0_components(cpu
) |
6051 x86_cpu_xsave_xss_components(cpu
);
6053 *eax
= env
->features
[FEAT_XSAVE
];
6054 *ebx
= xsave_area_size(xstate
, true);
6055 *ecx
= env
->features
[FEAT_XSAVE_XSS_LO
];
6056 *edx
= env
->features
[FEAT_XSAVE_XSS_HI
];
6057 if (kvm_enabled() && cpu
->enable_pmu
&&
6058 (env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_ARCH_LBR
) &&
6059 (*eax
& CPUID_XSAVE_XSAVES
)) {
6060 *ecx
|= XSTATE_ARCH_LBR_MASK
;
6062 *ecx
&= ~XSTATE_ARCH_LBR_MASK
;
6064 } else if (count
== 0xf &&
6065 accel_uses_host_cpuid() && cpu
->enable_pmu
&&
6066 (env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_ARCH_LBR
)) {
6067 x86_cpu_get_supported_cpuid(0xD, count
, eax
, ebx
, ecx
, edx
);
6068 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
6069 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
6071 if (x86_cpu_xsave_xcr0_components(cpu
) & (1ULL << count
)) {
6075 (ESA_FEATURE_ALIGN64_MASK
| ESA_FEATURE_XFD_MASK
);
6076 } else if (x86_cpu_xsave_xss_components(cpu
) & (1ULL << count
)) {
6085 #ifndef CONFIG_USER_ONLY
6086 if (!kvm_enabled() ||
6087 !(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SGX
)) {
6088 *eax
= *ebx
= *ecx
= *edx
= 0;
6093 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
6094 * the EPC properties, e.g. confidentiality and integrity, from the
6095 * host's first EPC section, i.e. assume there is one EPC section or
6096 * that all EPC sections have the same security properties.
6099 uint64_t epc_addr
, epc_size
;
6101 if (sgx_epc_get_section(count
- 2, &epc_addr
, &epc_size
)) {
6102 *eax
= *ebx
= *ecx
= *edx
= 0;
6105 host_cpuid(index
, 2, eax
, ebx
, ecx
, edx
);
6106 *eax
= (uint32_t)(epc_addr
& 0xfffff000) | 0x1;
6107 *ebx
= (uint32_t)(epc_addr
>> 32);
6108 *ecx
= (uint32_t)(epc_size
& 0xfffff000) | (*ecx
& 0xf);
6109 *edx
= (uint32_t)(epc_size
>> 32);
6114 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
6115 * and KVM, i.e. QEMU cannot emulate features to override what KVM
6116 * supports. Features can be further restricted by userspace, but not
6117 * made more permissive.
6119 x86_cpu_get_supported_cpuid(0x12, count
, eax
, ebx
, ecx
, edx
);
6122 *eax
&= env
->features
[FEAT_SGX_12_0_EAX
];
6123 *ebx
&= env
->features
[FEAT_SGX_12_0_EBX
];
6125 *eax
&= env
->features
[FEAT_SGX_12_1_EAX
];
6126 *ebx
&= 0; /* ebx reserve */
6127 *ecx
&= env
->features
[FEAT_XSAVE_XCR0_LO
];
6128 *edx
&= env
->features
[FEAT_XSAVE_XCR0_HI
];
6130 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
6131 *ecx
|= XSTATE_FP_MASK
| XSTATE_SSE_MASK
;
6133 /* Access to PROVISIONKEY requires additional credentials. */
6134 if ((*eax
& (1U << 4)) &&
6135 !kvm_enable_sgx_provisioning(cs
->kvm_state
)) {
6142 /* Intel Processor Trace Enumeration */
6147 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) ||
6153 *eax
= INTEL_PT_MAX_SUBLEAF
;
6154 *ebx
= INTEL_PT_MINIMAL_EBX
;
6155 *ecx
= INTEL_PT_MINIMAL_ECX
;
6156 if (env
->features
[FEAT_14_0_ECX
] & CPUID_14_0_ECX_LIP
) {
6157 *ecx
|= CPUID_14_0_ECX_LIP
;
6159 } else if (count
== 1) {
6160 *eax
= INTEL_PT_MTC_BITMAP
| INTEL_PT_ADDR_RANGES_NUM
;
6161 *ebx
= INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
;
6166 /* AMX TILE, for now hardcoded for Sapphire Rapids*/
6171 if (!(env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_AMX_TILE
)) {
6176 /* Highest numbered palette subleaf */
6177 *eax
= INTEL_AMX_TILE_MAX_SUBLEAF
;
6178 } else if (count
== 1) {
6179 *eax
= INTEL_AMX_TOTAL_TILE_BYTES
|
6180 (INTEL_AMX_BYTES_PER_TILE
<< 16);
6181 *ebx
= INTEL_AMX_BYTES_PER_ROW
| (INTEL_AMX_TILE_MAX_NAMES
<< 16);
6182 *ecx
= INTEL_AMX_TILE_MAX_ROWS
;
6187 /* AMX TMUL, for now hardcoded for Sapphire Rapids */
6192 if (!(env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_AMX_TILE
)) {
6197 /* Highest numbered palette subleaf */
6198 *ebx
= INTEL_AMX_TMUL_MAX_K
| (INTEL_AMX_TMUL_MAX_N
<< 8);
6204 * CPUID code in kvm_arch_init_vcpu() ignores stuff
6205 * set here, but we restrict to TCG none the less.
6207 if (tcg_enabled() && cpu
->expose_tcg
) {
6208 memcpy(signature
, "TCGTCGTCGTCG", 12);
6210 *ebx
= signature
[0];
6211 *ecx
= signature
[1];
6212 *edx
= signature
[2];
6227 *eax
= env
->cpuid_xlevel
;
6228 *ebx
= env
->cpuid_vendor1
;
6229 *edx
= env
->cpuid_vendor2
;
6230 *ecx
= env
->cpuid_vendor3
;
6233 *eax
= env
->cpuid_version
;
6235 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
6236 *edx
= env
->features
[FEAT_8000_0001_EDX
];
6238 /* The Linux kernel checks for the CMPLegacy bit and
6239 * discards multiple thread information if it is set.
6240 * So don't set it here for Intel to make Linux guests happy.
6242 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
6243 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
6244 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
6245 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
6246 *ecx
|= 1 << 1; /* CmpLegacy bit */
6249 if (tcg_enabled() && env
->cpuid_vendor1
== CPUID_VENDOR_INTEL_1
&&
6250 !(env
->hflags
& HF_LMA_MASK
)) {
6251 *edx
&= ~CPUID_EXT2_SYSCALL
;
6257 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
6258 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
6259 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
6260 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
6263 /* cache info (L1 cache) */
6264 if (cpu
->cache_info_passthrough
) {
6265 x86_cpu_get_cache_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
6268 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) |
6269 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
6270 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) |
6271 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
6272 *ecx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1d_cache
);
6273 *edx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1i_cache
);
6276 /* cache info (L2 cache) */
6277 if (cpu
->cache_info_passthrough
) {
6278 x86_cpu_get_cache_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
6281 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) |
6282 (L2_DTLB_2M_ENTRIES
<< 16) |
6283 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) |
6284 (L2_ITLB_2M_ENTRIES
);
6285 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) |
6286 (L2_DTLB_4K_ENTRIES
<< 16) |
6287 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) |
6288 (L2_ITLB_4K_ENTRIES
);
6289 encode_cache_cpuid80000006(env
->cache_info_amd
.l2_cache
,
6290 cpu
->enable_l3_cache
?
6291 env
->cache_info_amd
.l3_cache
: NULL
,
6298 *edx
= env
->features
[FEAT_8000_0007_EDX
];
6301 /* virtual & phys address size in low 2 bytes. */
6302 *eax
= cpu
->phys_bits
;
6303 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
6304 /* 64 bit processor */
6305 *eax
|= (cpu_x86_virtual_addr_width(env
) << 8);
6307 *ebx
= env
->features
[FEAT_8000_0008_EBX
];
6308 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
6310 * Bits 15:12 is "The number of bits in the initial
6311 * Core::X86::Apic::ApicId[ApicId] value that indicate
6312 * thread ID within a package".
6313 * Bits 7:0 is "The number of threads in the package is NC+1"
6315 *ecx
= (apicid_pkg_offset(&topo_info
) << 12) |
6316 ((cs
->nr_cores
* cs
->nr_threads
) - 1);
6323 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
6324 *eax
= 0x00000001; /* SVM Revision */
6325 *ebx
= 0x00000010; /* nr of ASIDs */
6327 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
6337 if (cpu
->cache_info_passthrough
) {
6338 x86_cpu_get_cache_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
6342 case 0: /* L1 dcache info */
6343 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1d_cache
,
6344 &topo_info
, eax
, ebx
, ecx
, edx
);
6346 case 1: /* L1 icache info */
6347 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1i_cache
,
6348 &topo_info
, eax
, ebx
, ecx
, edx
);
6350 case 2: /* L2 cache info */
6351 encode_cache_cpuid8000001d(env
->cache_info_amd
.l2_cache
,
6352 &topo_info
, eax
, ebx
, ecx
, edx
);
6354 case 3: /* L3 cache info */
6355 encode_cache_cpuid8000001d(env
->cache_info_amd
.l3_cache
,
6356 &topo_info
, eax
, ebx
, ecx
, edx
);
6358 default: /* end of info */
6359 *eax
= *ebx
= *ecx
= *edx
= 0;
6364 if (cpu
->core_id
<= 255) {
6365 encode_topo_cpuid8000001e(cpu
, &topo_info
, eax
, ebx
, ecx
, edx
);
6374 *eax
= env
->cpuid_xlevel2
;
6380 /* Support for VIA CPU's CPUID instruction */
6381 *eax
= env
->cpuid_version
;
6384 *edx
= env
->features
[FEAT_C000_0001_EDX
];
6389 /* Reserved for the future, and now filled with zero */
6396 *eax
= *ebx
= *ecx
= *edx
= 0;
6397 if (sev_enabled()) {
6399 *eax
|= sev_es_enabled() ? 0x8 : 0;
6400 *ebx
= sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
6401 *ebx
|= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
6405 *eax
= env
->features
[FEAT_8000_0021_EAX
];
6406 *ebx
= *ecx
= *edx
= 0;
6409 /* reserved values: zero */
6418 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State
*env
)
6420 #ifndef CONFIG_USER_ONLY
6421 /* Those default values are defined in Skylake HW */
6422 env
->msr_ia32_sgxlepubkeyhash
[0] = 0xa6053e051270b7acULL
;
6423 env
->msr_ia32_sgxlepubkeyhash
[1] = 0x6cfbe8ba8b3b413dULL
;
6424 env
->msr_ia32_sgxlepubkeyhash
[2] = 0xc4916d99f2b3735dULL
;
6425 env
->msr_ia32_sgxlepubkeyhash
[3] = 0xd4f8c05909f9bb3bULL
;
6429 static void x86_cpu_reset_hold(Object
*obj
)
6431 CPUState
*s
= CPU(obj
);
6432 X86CPU
*cpu
= X86_CPU(s
);
6433 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
6434 CPUX86State
*env
= &cpu
->env
;
6439 if (xcc
->parent_phases
.hold
) {
6440 xcc
->parent_phases
.hold(obj
);
6443 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
6445 env
->old_exception
= -1;
6447 /* init to reset state */
6449 env
->hflags2
|= HF2_GIF_MASK
;
6450 env
->hflags2
|= HF2_VGIF_MASK
;
6451 env
->hflags
&= ~HF_GUEST_MASK
;
6453 cpu_x86_update_cr0(env
, 0x60000010);
6454 env
->a20_mask
= ~0x0;
6455 env
->smbase
= 0x30000;
6456 env
->msr_smi_count
= 0;
6458 env
->idt
.limit
= 0xffff;
6459 env
->gdt
.limit
= 0xffff;
6460 env
->ldt
.limit
= 0xffff;
6461 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
6462 env
->tr
.limit
= 0xffff;
6463 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
6465 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
6466 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
6467 DESC_R_MASK
| DESC_A_MASK
);
6468 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
6469 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6471 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
6472 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6474 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
6475 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6477 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
6478 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6480 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
6481 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6485 env
->regs
[R_EDX
] = env
->cpuid_version
;
6490 for (i
= 0; i
< 8; i
++) {
6493 cpu_set_fpuc(env
, 0x37f);
6495 env
->mxcsr
= 0x1f80;
6496 /* All units are in INIT state. */
6499 env
->pat
= 0x0007040600070406ULL
;
6501 if (kvm_enabled()) {
6503 * KVM handles TSC = 0 specially and thinks we are hot-plugging
6504 * a new CPU, use 1 instead to force a reset.
6506 if (env
->tsc
!= 0) {
6513 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
6514 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_MONITOR
) {
6515 env
->msr_ia32_misc_enable
|= MSR_IA32_MISC_ENABLE_MWAIT
;
6518 memset(env
->dr
, 0, sizeof(env
->dr
));
6519 env
->dr
[6] = DR6_FIXED_1
;
6520 env
->dr
[7] = DR7_FIXED_1
;
6521 cpu_breakpoint_remove_all(s
, BP_CPU
);
6522 cpu_watchpoint_remove_all(s
, BP_CPU
);
6525 xcr0
= XSTATE_FP_MASK
;
6527 #ifdef CONFIG_USER_ONLY
6528 /* Enable all the features for user-mode. */
6529 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
6530 xcr0
|= XSTATE_SSE_MASK
;
6532 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
6533 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
6534 if (!((1 << i
) & CPUID_XSTATE_XCR0_MASK
)) {
6537 if (env
->features
[esa
->feature
] & esa
->bits
) {
6542 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
6543 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
6545 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
6546 cr4
|= CR4_FSGSBASE_MASK
;
6551 cpu_x86_update_cr4(env
, cr4
);
6554 * SDM 11.11.5 requires:
6555 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6556 * - IA32_MTRR_PHYSMASKn.V = 0
6557 * All other bits are undefined. For simplification, zero it all.
6559 env
->mtrr_deftype
= 0;
6560 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
6561 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
6563 env
->interrupt_injected
= -1;
6564 env
->exception_nr
= -1;
6565 env
->exception_pending
= 0;
6566 env
->exception_injected
= 0;
6567 env
->exception_has_payload
= false;
6568 env
->exception_payload
= 0;
6569 env
->nmi_injected
= false;
6570 env
->triple_fault_pending
= false;
6571 #if !defined(CONFIG_USER_ONLY)
6572 /* We hard-wire the BSP to the first CPU. */
6573 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
6575 s
->halted
= !cpu_is_bsp(cpu
);
6577 if (kvm_enabled()) {
6578 kvm_arch_reset_vcpu(cpu
);
6581 x86_cpu_set_sgxlepubkeyhash(env
);
6583 env
->amd_tsc_scale_msr
= MSR_AMD64_TSC_RATIO_DEFAULT
;
6588 void x86_cpu_after_reset(X86CPU
*cpu
)
6590 #ifndef CONFIG_USER_ONLY
6591 if (kvm_enabled()) {
6592 kvm_arch_after_reset_vcpu(cpu
);
6595 if (cpu
->apic_state
) {
6596 device_cold_reset(cpu
->apic_state
);
6601 static void mce_init(X86CPU
*cpu
)
6603 CPUX86State
*cenv
= &cpu
->env
;
6606 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
6607 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
6608 (CPUID_MCE
| CPUID_MCA
)) {
6609 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
6610 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
6611 cenv
->mcg_ctl
= ~(uint64_t)0;
6612 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
6613 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
6618 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
6625 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6626 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
6628 CPUX86State
*env
= &cpu
->env
;
6629 FeatureWordInfo
*fi
= &feature_word_info
[w
];
6630 uint32_t eax
= fi
->cpuid
.eax
;
6631 uint32_t region
= eax
& 0xF0000000;
6633 assert(feature_word_info
[w
].type
== CPUID_FEATURE_WORD
);
6634 if (!env
->features
[w
]) {
6640 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
6643 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
6646 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
6651 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level_func7
,
6656 /* Calculate XSAVE components based on the configured CPU feature flags */
6657 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
6659 CPUX86State
*env
= &cpu
->env
;
6662 static bool request_perm
;
6664 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
6665 env
->features
[FEAT_XSAVE_XCR0_LO
] = 0;
6666 env
->features
[FEAT_XSAVE_XCR0_HI
] = 0;
6671 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
6672 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
6673 if (env
->features
[esa
->feature
] & esa
->bits
) {
6674 mask
|= (1ULL << i
);
6678 /* Only request permission for first vcpu */
6679 if (kvm_enabled() && !request_perm
) {
6680 kvm_request_xsave_components(cpu
, mask
);
6681 request_perm
= true;
6684 env
->features
[FEAT_XSAVE_XCR0_LO
] = mask
& CPUID_XSTATE_XCR0_MASK
;
6685 env
->features
[FEAT_XSAVE_XCR0_HI
] = mask
>> 32;
6686 env
->features
[FEAT_XSAVE_XSS_LO
] = mask
& CPUID_XSTATE_XSS_MASK
;
6687 env
->features
[FEAT_XSAVE_XSS_HI
] = mask
>> 32;
6690 /***** Steps involved on loading and filtering CPUID data
6692 * When initializing and realizing a CPU object, the steps
6693 * involved in setting up CPUID data are:
6695 * 1) Loading CPU model definition (X86CPUDefinition). This is
6696 * implemented by x86_cpu_load_model() and should be completely
6697 * transparent, as it is done automatically by instance_init.
6698 * No code should need to look at X86CPUDefinition structs
6699 * outside instance_init.
6701 * 2) CPU expansion. This is done by realize before CPUID
6702 * filtering, and will make sure host/accelerator data is
6703 * loaded for CPU models that depend on host capabilities
6704 * (e.g. "host"). Done by x86_cpu_expand_features().
6706 * 3) CPUID filtering. This initializes extra data related to
6707 * CPUID, and checks if the host supports all capabilities
6708 * required by the CPU. Runnability of a CPU model is
6709 * determined at this step. Done by x86_cpu_filter_features().
6711 * Some operations don't require all steps to be performed.
6714 * - CPU instance creation (instance_init) will run only CPU
6715 * model loading. CPU expansion can't run at instance_init-time
6716 * because host/accelerator data may be not available yet.
6717 * - CPU realization will perform both CPU model expansion and CPUID
6718 * filtering, and return an error in case one of them fails.
6719 * - query-cpu-definitions needs to run all 3 steps. It needs
6720 * to run CPUID filtering, as the 'unavailable-features'
6721 * field is set based on the filtering results.
6722 * - The query-cpu-model-expansion QMP command only needs to run
6723 * CPU model loading and CPU expansion. It should not filter
6724 * any CPUID data based on host capabilities.
6727 /* Expand CPU configuration data, based on configured features
6728 * and host/accelerator capabilities when appropriate.
6730 void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
6732 CPUX86State
*env
= &cpu
->env
;
6737 for (l
= plus_features
; l
; l
= l
->next
) {
6738 const char *prop
= l
->data
;
6739 if (!object_property_set_bool(OBJECT(cpu
), prop
, true, errp
)) {
6744 for (l
= minus_features
; l
; l
= l
->next
) {
6745 const char *prop
= l
->data
;
6746 if (!object_property_set_bool(OBJECT(cpu
), prop
, false, errp
)) {
6751 /*TODO: Now cpu->max_features doesn't overwrite features
6752 * set using QOM properties, and we can convert
6753 * plus_features & minus_features to global properties
6754 * inside x86_cpu_parse_featurestr() too.
6756 if (cpu
->max_features
) {
6757 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
6758 /* Override only features that weren't set explicitly
6762 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
6763 ~env
->user_features
[w
] &
6764 ~feature_word_info
[w
].no_autoenable_flags
;
6768 for (i
= 0; i
< ARRAY_SIZE(feature_dependencies
); i
++) {
6769 FeatureDep
*d
= &feature_dependencies
[i
];
6770 if (!(env
->features
[d
->from
.index
] & d
->from
.mask
)) {
6771 uint64_t unavailable_features
= env
->features
[d
->to
.index
] & d
->to
.mask
;
6773 /* Not an error unless the dependent feature was added explicitly. */
6774 mark_unavailable_features(cpu
, d
->to
.index
,
6775 unavailable_features
& env
->user_features
[d
->to
.index
],
6776 "This feature depends on other features that were not requested");
6778 env
->features
[d
->to
.index
] &= ~unavailable_features
;
6782 if (!kvm_enabled() || !cpu
->expose_kvm
) {
6783 env
->features
[FEAT_KVM
] = 0;
6786 x86_cpu_enable_xsave_components(cpu
);
6788 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6789 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
6790 if (cpu
->full_cpuid_auto_level
) {
6791 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
6792 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
6793 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
6794 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
6795 x86_cpu_adjust_feat_level(cpu
, FEAT_7_1_EAX
);
6796 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
6797 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
6798 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
6799 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0008_EBX
);
6800 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
6801 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
6802 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
6804 /* Intel Processor Trace requires CPUID[0x14] */
6805 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
)) {
6806 if (cpu
->intel_pt_auto_level
) {
6807 x86_cpu_adjust_level(cpu
, &cpu
->env
.cpuid_min_level
, 0x14);
6808 } else if (cpu
->env
.cpuid_min_level
< 0x14) {
6809 mark_unavailable_features(cpu
, FEAT_7_0_EBX
,
6810 CPUID_7_0_EBX_INTEL_PT
,
6811 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
6816 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
6817 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
6818 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
6819 * cpu->vendor_cpuid_only has been unset for compatibility with older
6822 if ((env
->nr_dies
> 1) &&
6823 (IS_INTEL_CPU(env
) || !cpu
->vendor_cpuid_only
)) {
6824 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, 0x1F);
6827 /* SVM requires CPUID[0x8000000A] */
6828 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
6829 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
6832 /* SEV requires CPUID[0x8000001F] */
6833 if (sev_enabled()) {
6834 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000001F);
6837 if (env
->features
[FEAT_8000_0021_EAX
]) {
6838 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x80000021);
6841 /* SGX requires CPUID[0x12] for EPC enumeration */
6842 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SGX
) {
6843 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, 0x12);
6847 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6848 if (env
->cpuid_level_func7
== UINT32_MAX
) {
6849 env
->cpuid_level_func7
= env
->cpuid_min_level_func7
;
6851 if (env
->cpuid_level
== UINT32_MAX
) {
6852 env
->cpuid_level
= env
->cpuid_min_level
;
6854 if (env
->cpuid_xlevel
== UINT32_MAX
) {
6855 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
6857 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
6858 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
6861 if (kvm_enabled()) {
6862 kvm_hyperv_expand_features(cpu
, errp
);
6867 * Finishes initialization of CPUID data, filters CPU feature
6868 * words based on host availability of each feature.
6870 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6872 static void x86_cpu_filter_features(X86CPU
*cpu
, bool verbose
)
6874 CPUX86State
*env
= &cpu
->env
;
6876 const char *prefix
= NULL
;
6879 prefix
= accel_uses_host_cpuid()
6880 ? "host doesn't support requested feature"
6881 : "TCG doesn't support requested feature";
6884 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
6885 uint64_t host_feat
=
6886 x86_cpu_get_supported_feature_word(w
, false);
6887 uint64_t requested_features
= env
->features
[w
];
6888 uint64_t unavailable_features
= requested_features
& ~host_feat
;
6889 mark_unavailable_features(cpu
, w
, unavailable_features
, prefix
);
6892 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) &&
6894 KVMState
*s
= CPU(cpu
)->kvm_state
;
6895 uint32_t eax_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EAX
);
6896 uint32_t ebx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EBX
);
6897 uint32_t ecx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_ECX
);
6898 uint32_t eax_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EAX
);
6899 uint32_t ebx_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EBX
);
6902 ((ebx_0
& INTEL_PT_MINIMAL_EBX
) != INTEL_PT_MINIMAL_EBX
) ||
6903 ((ecx_0
& INTEL_PT_MINIMAL_ECX
) != INTEL_PT_MINIMAL_ECX
) ||
6904 ((eax_1
& INTEL_PT_MTC_BITMAP
) != INTEL_PT_MTC_BITMAP
) ||
6905 ((eax_1
& INTEL_PT_ADDR_RANGES_NUM_MASK
) <
6906 INTEL_PT_ADDR_RANGES_NUM
) ||
6907 ((ebx_1
& (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) !=
6908 (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) ||
6909 ((ecx_0
& CPUID_14_0_ECX_LIP
) !=
6910 (env
->features
[FEAT_14_0_ECX
] & CPUID_14_0_ECX_LIP
))) {
6912 * Processor Trace capabilities aren't configurable, so if the
6913 * host can't emulate the capabilities we report on
6914 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6916 mark_unavailable_features(cpu
, FEAT_7_0_EBX
, CPUID_7_0_EBX_INTEL_PT
, prefix
);
6921 static void x86_cpu_hyperv_realize(X86CPU
*cpu
)
6925 /* Hyper-V vendor id */
6926 if (!cpu
->hyperv_vendor
) {
6927 object_property_set_str(OBJECT(cpu
), "hv-vendor-id", "Microsoft Hv",
6930 len
= strlen(cpu
->hyperv_vendor
);
6932 warn_report("hv-vendor-id truncated to 12 characters");
6935 memset(cpu
->hyperv_vendor_id
, 0, 12);
6936 memcpy(cpu
->hyperv_vendor_id
, cpu
->hyperv_vendor
, len
);
6938 /* 'Hv#1' interface identification*/
6939 cpu
->hyperv_interface_id
[0] = 0x31237648;
6940 cpu
->hyperv_interface_id
[1] = 0;
6941 cpu
->hyperv_interface_id
[2] = 0;
6942 cpu
->hyperv_interface_id
[3] = 0;
6944 /* Hypervisor implementation limits */
6945 cpu
->hyperv_limits
[0] = 64;
6946 cpu
->hyperv_limits
[1] = 0;
6947 cpu
->hyperv_limits
[2] = 0;
6950 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
6952 CPUState
*cs
= CPU(dev
);
6953 X86CPU
*cpu
= X86_CPU(dev
);
6954 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
6955 CPUX86State
*env
= &cpu
->env
;
6956 Error
*local_err
= NULL
;
6957 static bool ht_warned
;
6958 unsigned requested_lbr_fmt
;
6960 /* Use pc-relative instructions in system-mode */
6961 #ifndef CONFIG_USER_ONLY
6962 cs
->tcg_cflags
|= CF_PCREL
;
6965 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
6966 error_setg(errp
, "apic-id property was not initialized properly");
6971 * Process Hyper-V enlightenments.
6972 * Note: this currently has to happen before the expansion of CPU features.
6974 x86_cpu_hyperv_realize(cpu
);
6976 x86_cpu_expand_features(cpu
, &local_err
);
6982 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT
6983 * with user-provided setting.
6985 if (cpu
->lbr_fmt
!= ~PERF_CAP_LBR_FMT
) {
6986 if ((cpu
->lbr_fmt
& PERF_CAP_LBR_FMT
) != cpu
->lbr_fmt
) {
6987 error_setg(errp
, "invalid lbr-fmt");
6990 env
->features
[FEAT_PERF_CAPABILITIES
] &= ~PERF_CAP_LBR_FMT
;
6991 env
->features
[FEAT_PERF_CAPABILITIES
] |= cpu
->lbr_fmt
;
6995 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and
6996 * 3)vPMU LBR format matches that of host setting.
6999 env
->features
[FEAT_PERF_CAPABILITIES
] & PERF_CAP_LBR_FMT
;
7000 if (requested_lbr_fmt
&& kvm_enabled()) {
7001 uint64_t host_perf_cap
=
7002 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES
, false);
7003 unsigned host_lbr_fmt
= host_perf_cap
& PERF_CAP_LBR_FMT
;
7005 if (!cpu
->enable_pmu
) {
7006 error_setg(errp
, "vPMU: LBR is unsupported without pmu=on");
7009 if (requested_lbr_fmt
!= host_lbr_fmt
) {
7010 error_setg(errp
, "vPMU: the lbr-fmt value (0x%x) does not match "
7011 "the host value (0x%x).",
7012 requested_lbr_fmt
, host_lbr_fmt
);
7017 x86_cpu_filter_features(cpu
, cpu
->check_cpuid
|| cpu
->enforce_cpuid
);
7019 if (cpu
->enforce_cpuid
&& x86_cpu_have_filtered_features(cpu
)) {
7020 error_setg(&local_err
,
7021 accel_uses_host_cpuid() ?
7022 "Host doesn't support requested features" :
7023 "TCG doesn't support requested features");
7027 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
7030 if (IS_AMD_CPU(env
)) {
7031 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
7032 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
7033 & CPUID_EXT2_AMD_ALIASES
);
7036 x86_cpu_set_sgxlepubkeyhash(env
);
7039 * note: the call to the framework needs to happen after feature expansion,
7040 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
7041 * These may be set by the accel-specific code,
7042 * and the results are subsequently checked / assumed in this function.
7044 cpu_exec_realizefn(cs
, &local_err
);
7045 if (local_err
!= NULL
) {
7046 error_propagate(errp
, local_err
);
7050 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
7051 g_autofree
char *name
= x86_cpu_class_get_model_name(xcc
);
7052 error_setg(&local_err
, "CPU model '%s' requires KVM or HVF", name
);
7056 if (cpu
->ucode_rev
== 0) {
7058 * The default is the same as KVM's. Note that this check
7059 * needs to happen after the evenual setting of ucode_rev in
7060 * accel-specific code in cpu_exec_realizefn.
7062 if (IS_AMD_CPU(env
)) {
7063 cpu
->ucode_rev
= 0x01000065;
7065 cpu
->ucode_rev
= 0x100000000ULL
;
7070 * mwait extended info: needed for Core compatibility
7071 * We always wake on interrupt even if host does not have the capability.
7073 * requires the accel-specific code in cpu_exec_realizefn to
7074 * have already acquired the CPUID data into cpu->mwait.
7076 cpu
->mwait
.ecx
|= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
7078 /* For 64bit systems think about the number of physical bits to present.
7079 * ideally this should be the same as the host; anything other than matching
7080 * the host can cause incorrect guest behaviour.
7081 * QEMU used to pick the magic value of 40 bits that corresponds to
7082 * consumer AMD devices but nothing else.
7084 * Note that this code assumes features expansion has already been done
7085 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
7086 * phys_bits adjustments to match the host have been already done in
7087 * accel-specific code in cpu_exec_realizefn.
7089 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
7090 if (cpu
->phys_bits
&&
7091 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
7092 cpu
->phys_bits
< 32)) {
7093 error_setg(errp
, "phys-bits should be between 32 and %u "
7095 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
7099 * 0 means it was not explicitly set by the user (or by machine
7100 * compat_props or by the host code in host-cpu.c).
7101 * In this case, the default is the value used by TCG (40).
7103 if (cpu
->phys_bits
== 0) {
7104 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
7107 /* For 32 bit systems don't use the user set value, but keep
7108 * phys_bits consistent with what we tell the guest.
7110 if (cpu
->phys_bits
!= 0) {
7111 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
7115 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
7116 cpu
->phys_bits
= 36;
7118 cpu
->phys_bits
= 32;
7122 /* Cache information initialization */
7123 if (!cpu
->legacy_cache
) {
7124 const CPUCaches
*cache_info
=
7125 x86_cpu_get_versioned_cache_info(cpu
, xcc
->model
);
7127 if (!xcc
->model
|| !cache_info
) {
7128 g_autofree
char *name
= x86_cpu_class_get_model_name(xcc
);
7130 "CPU model '%s' doesn't support legacy-cache=off", name
);
7133 env
->cache_info_cpuid2
= env
->cache_info_cpuid4
= env
->cache_info_amd
=
7136 /* Build legacy cache information */
7137 env
->cache_info_cpuid2
.l1d_cache
= &legacy_l1d_cache
;
7138 env
->cache_info_cpuid2
.l1i_cache
= &legacy_l1i_cache
;
7139 env
->cache_info_cpuid2
.l2_cache
= &legacy_l2_cache_cpuid2
;
7140 env
->cache_info_cpuid2
.l3_cache
= &legacy_l3_cache
;
7142 env
->cache_info_cpuid4
.l1d_cache
= &legacy_l1d_cache
;
7143 env
->cache_info_cpuid4
.l1i_cache
= &legacy_l1i_cache
;
7144 env
->cache_info_cpuid4
.l2_cache
= &legacy_l2_cache
;
7145 env
->cache_info_cpuid4
.l3_cache
= &legacy_l3_cache
;
7147 env
->cache_info_amd
.l1d_cache
= &legacy_l1d_cache_amd
;
7148 env
->cache_info_amd
.l1i_cache
= &legacy_l1i_cache_amd
;
7149 env
->cache_info_amd
.l2_cache
= &legacy_l2_cache_amd
;
7150 env
->cache_info_amd
.l3_cache
= &legacy_l3_cache
;
7153 #ifndef CONFIG_USER_ONLY
7154 MachineState
*ms
= MACHINE(qdev_get_machine());
7155 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
7157 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| ms
->smp
.cpus
> 1) {
7158 x86_cpu_apic_create(cpu
, &local_err
);
7159 if (local_err
!= NULL
) {
7170 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
7171 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
7172 * based on inputs (sockets,cores,threads), it is still better to give
7175 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
7176 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
7178 if (IS_AMD_CPU(env
) &&
7179 !(env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_TOPOEXT
) &&
7180 cs
->nr_threads
> 1 && !ht_warned
) {
7181 warn_report("This family of AMD CPU doesn't support "
7182 "hyperthreading(%d)",
7184 error_printf("Please configure -smp options properly"
7185 " or try enabling topoext feature.\n");
7189 #ifndef CONFIG_USER_ONLY
7190 x86_cpu_apic_realize(cpu
, &local_err
);
7191 if (local_err
!= NULL
) {
7194 #endif /* !CONFIG_USER_ONLY */
7197 xcc
->parent_realize(dev
, &local_err
);
7200 if (local_err
!= NULL
) {
7201 error_propagate(errp
, local_err
);
7206 static void x86_cpu_unrealizefn(DeviceState
*dev
)
7208 X86CPU
*cpu
= X86_CPU(dev
);
7209 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
7211 #ifndef CONFIG_USER_ONLY
7212 cpu_remove_sync(CPU(dev
));
7213 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
7216 if (cpu
->apic_state
) {
7217 object_unparent(OBJECT(cpu
->apic_state
));
7218 cpu
->apic_state
= NULL
;
7221 xcc
->parent_unrealize(dev
);
7224 typedef struct BitProperty
{
7229 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
7230 void *opaque
, Error
**errp
)
7232 X86CPU
*cpu
= X86_CPU(obj
);
7233 BitProperty
*fp
= opaque
;
7234 uint64_t f
= cpu
->env
.features
[fp
->w
];
7235 bool value
= (f
& fp
->mask
) == fp
->mask
;
7236 visit_type_bool(v
, name
, &value
, errp
);
7239 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
7240 void *opaque
, Error
**errp
)
7242 DeviceState
*dev
= DEVICE(obj
);
7243 X86CPU
*cpu
= X86_CPU(obj
);
7244 BitProperty
*fp
= opaque
;
7247 if (dev
->realized
) {
7248 qdev_prop_set_after_realize(dev
, name
, errp
);
7252 if (!visit_type_bool(v
, name
, &value
, errp
)) {
7257 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
7259 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
7261 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
7264 /* Register a boolean property to get/set a single bit in a uint32_t field.
7266 * The same property name can be registered multiple times to make it affect
7267 * multiple bits in the same FeatureWord. In that case, the getter will return
7268 * true only if all bits are set.
7270 static void x86_cpu_register_bit_prop(X86CPUClass
*xcc
,
7271 const char *prop_name
,
7275 ObjectClass
*oc
= OBJECT_CLASS(xcc
);
7278 uint64_t mask
= (1ULL << bitnr
);
7280 op
= object_class_property_find(oc
, prop_name
);
7286 fp
= g_new0(BitProperty
, 1);
7289 object_class_property_add(oc
, prop_name
, "bool",
7290 x86_cpu_get_bit_prop
,
7291 x86_cpu_set_bit_prop
,
7296 static void x86_cpu_register_feature_bit_props(X86CPUClass
*xcc
,
7300 FeatureWordInfo
*fi
= &feature_word_info
[w
];
7301 const char *name
= fi
->feat_names
[bitnr
];
7307 /* Property names should use "-" instead of "_".
7308 * Old names containing underscores are registered as aliases
7309 * using object_property_add_alias()
7311 assert(!strchr(name
, '_'));
7312 /* aliases don't use "|" delimiters anymore, they are registered
7313 * manually using object_property_add_alias() */
7314 assert(!strchr(name
, '|'));
7315 x86_cpu_register_bit_prop(xcc
, name
, w
, bitnr
);
7318 static void x86_cpu_post_initfn(Object
*obj
)
7320 accel_cpu_instance_init(CPU(obj
));
7323 static void x86_cpu_initfn(Object
*obj
)
7325 X86CPU
*cpu
= X86_CPU(obj
);
7326 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
7327 CPUX86State
*env
= &cpu
->env
;
7330 cpu_set_cpustate_pointers(cpu
);
7332 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
7333 x86_cpu_get_feature_words
,
7334 NULL
, NULL
, (void *)env
->features
);
7335 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
7336 x86_cpu_get_feature_words
,
7337 NULL
, NULL
, (void *)cpu
->filtered_features
);
7339 object_property_add_alias(obj
, "sse3", obj
, "pni");
7340 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq");
7341 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1");
7342 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2");
7343 object_property_add_alias(obj
, "xd", obj
, "nx");
7344 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt");
7345 object_property_add_alias(obj
, "i64", obj
, "lm");
7347 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl");
7348 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust");
7349 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt");
7350 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm");
7351 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy");
7352 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr");
7353 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core");
7354 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb");
7355 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay");
7356 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu");
7357 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf");
7358 object_property_add_alias(obj
, "kvm_asyncpf_int", obj
, "kvm-asyncpf-int");
7359 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time");
7360 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi");
7361 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt");
7362 object_property_add_alias(obj
, "kvm_poll_control", obj
, "kvm-poll-control");
7363 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock");
7364 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save");
7365 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale");
7366 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean");
7367 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter");
7368 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1");
7369 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2");
7371 object_property_add_alias(obj
, "hv-apicv", obj
, "hv-avic");
7372 cpu
->lbr_fmt
= ~PERF_CAP_LBR_FMT
;
7373 object_property_add_alias(obj
, "lbr_fmt", obj
, "lbr-fmt");
7376 x86_cpu_load_model(cpu
, xcc
->model
);
7380 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
7382 X86CPU
*cpu
= X86_CPU(cs
);
7384 return cpu
->apic_id
;
7387 #if !defined(CONFIG_USER_ONLY)
7388 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
7390 X86CPU
*cpu
= X86_CPU(cs
);
7392 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
7394 #endif /* !CONFIG_USER_ONLY */
7396 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
7398 X86CPU
*cpu
= X86_CPU(cs
);
7400 cpu
->env
.eip
= value
;
7403 static vaddr
x86_cpu_get_pc(CPUState
*cs
)
7405 X86CPU
*cpu
= X86_CPU(cs
);
7407 /* Match cpu_get_tb_cpu_state. */
7408 return cpu
->env
.eip
+ cpu
->env
.segs
[R_CS
].base
;
7411 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
)
7413 X86CPU
*cpu
= X86_CPU(cs
);
7414 CPUX86State
*env
= &cpu
->env
;
7416 #if !defined(CONFIG_USER_ONLY)
7417 if (interrupt_request
& CPU_INTERRUPT_POLL
) {
7418 return CPU_INTERRUPT_POLL
;
7421 if (interrupt_request
& CPU_INTERRUPT_SIPI
) {
7422 return CPU_INTERRUPT_SIPI
;
7425 if (env
->hflags2
& HF2_GIF_MASK
) {
7426 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
7427 !(env
->hflags
& HF_SMM_MASK
)) {
7428 return CPU_INTERRUPT_SMI
;
7429 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
7430 !(env
->hflags2
& HF2_NMI_MASK
)) {
7431 return CPU_INTERRUPT_NMI
;
7432 } else if (interrupt_request
& CPU_INTERRUPT_MCE
) {
7433 return CPU_INTERRUPT_MCE
;
7434 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
7435 (((env
->hflags2
& HF2_VINTR_MASK
) &&
7436 (env
->hflags2
& HF2_HIF_MASK
)) ||
7437 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
7438 (env
->eflags
& IF_MASK
&&
7439 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
7440 return CPU_INTERRUPT_HARD
;
7441 #if !defined(CONFIG_USER_ONLY)
7442 } else if (env
->hflags2
& HF2_VGIF_MASK
) {
7443 if((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
7444 (env
->eflags
& IF_MASK
) &&
7445 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
7446 return CPU_INTERRUPT_VIRQ
;
7455 static bool x86_cpu_has_work(CPUState
*cs
)
7457 return x86_cpu_pending_interrupt(cs
, cs
->interrupt_request
) != 0;
7460 static void x86_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
7462 X86CPU
*cpu
= X86_CPU(cs
);
7463 CPUX86State
*env
= &cpu
->env
;
7465 info
->mach
= (env
->hflags
& HF_CS64_MASK
? bfd_mach_x86_64
7466 : env
->hflags
& HF_CS32_MASK
? bfd_mach_i386_i386
7467 : bfd_mach_i386_i8086
);
7469 info
->cap_arch
= CS_ARCH_X86
;
7470 info
->cap_mode
= (env
->hflags
& HF_CS64_MASK
? CS_MODE_64
7471 : env
->hflags
& HF_CS32_MASK
? CS_MODE_32
7473 info
->cap_insn_unit
= 1;
7474 info
->cap_insn_split
= 8;
7477 void x86_update_hflags(CPUX86State
*env
)
7480 #define HFLAG_COPY_MASK \
7481 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7482 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7483 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7484 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7486 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
7487 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
7488 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
7489 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
7490 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
7491 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
7493 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
7494 hflags
|= HF_OSFXSR_MASK
;
7497 if (env
->efer
& MSR_EFER_LMA
) {
7498 hflags
|= HF_LMA_MASK
;
7501 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
7502 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
7504 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
7505 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
7506 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
7507 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
7508 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
7509 !(hflags
& HF_CS32_MASK
)) {
7510 hflags
|= HF_ADDSEG_MASK
;
7512 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
7513 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
7516 env
->hflags
= hflags
;
7519 static Property x86_cpu_properties
[] = {
7520 #ifdef CONFIG_USER_ONLY
7521 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7522 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
7523 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
7524 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
7525 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, 0),
7526 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
7528 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
7529 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
7530 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
7531 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, -1),
7532 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
7534 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
7535 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
7536 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU
, lbr_fmt
, PERF_CAP_LBR_FMT
),
7538 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU
, hyperv_spinlock_attempts
,
7539 HYPERV_SPINLOCK_NEVER_NOTIFY
),
7540 DEFINE_PROP_BIT64("hv-relaxed", X86CPU
, hyperv_features
,
7541 HYPERV_FEAT_RELAXED
, 0),
7542 DEFINE_PROP_BIT64("hv-vapic", X86CPU
, hyperv_features
,
7543 HYPERV_FEAT_VAPIC
, 0),
7544 DEFINE_PROP_BIT64("hv-time", X86CPU
, hyperv_features
,
7545 HYPERV_FEAT_TIME
, 0),
7546 DEFINE_PROP_BIT64("hv-crash", X86CPU
, hyperv_features
,
7547 HYPERV_FEAT_CRASH
, 0),
7548 DEFINE_PROP_BIT64("hv-reset", X86CPU
, hyperv_features
,
7549 HYPERV_FEAT_RESET
, 0),
7550 DEFINE_PROP_BIT64("hv-vpindex", X86CPU
, hyperv_features
,
7551 HYPERV_FEAT_VPINDEX
, 0),
7552 DEFINE_PROP_BIT64("hv-runtime", X86CPU
, hyperv_features
,
7553 HYPERV_FEAT_RUNTIME
, 0),
7554 DEFINE_PROP_BIT64("hv-synic", X86CPU
, hyperv_features
,
7555 HYPERV_FEAT_SYNIC
, 0),
7556 DEFINE_PROP_BIT64("hv-stimer", X86CPU
, hyperv_features
,
7557 HYPERV_FEAT_STIMER
, 0),
7558 DEFINE_PROP_BIT64("hv-frequencies", X86CPU
, hyperv_features
,
7559 HYPERV_FEAT_FREQUENCIES
, 0),
7560 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU
, hyperv_features
,
7561 HYPERV_FEAT_REENLIGHTENMENT
, 0),
7562 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU
, hyperv_features
,
7563 HYPERV_FEAT_TLBFLUSH
, 0),
7564 DEFINE_PROP_BIT64("hv-evmcs", X86CPU
, hyperv_features
,
7565 HYPERV_FEAT_EVMCS
, 0),
7566 DEFINE_PROP_BIT64("hv-ipi", X86CPU
, hyperv_features
,
7567 HYPERV_FEAT_IPI
, 0),
7568 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU
, hyperv_features
,
7569 HYPERV_FEAT_STIMER_DIRECT
, 0),
7570 DEFINE_PROP_BIT64("hv-avic", X86CPU
, hyperv_features
,
7571 HYPERV_FEAT_AVIC
, 0),
7572 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU
, hyperv_features
,
7573 HYPERV_FEAT_MSR_BITMAP
, 0),
7574 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU
, hyperv_features
,
7575 HYPERV_FEAT_XMM_INPUT
, 0),
7576 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU
, hyperv_features
,
7577 HYPERV_FEAT_TLBFLUSH_EXT
, 0),
7578 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU
, hyperv_features
,
7579 HYPERV_FEAT_TLBFLUSH_DIRECT
, 0),
7580 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU
,
7581 hyperv_no_nonarch_cs
, ON_OFF_AUTO_OFF
),
7582 DEFINE_PROP_BIT64("hv-syndbg", X86CPU
, hyperv_features
,
7583 HYPERV_FEAT_SYNDBG
, 0),
7584 DEFINE_PROP_BOOL("hv-passthrough", X86CPU
, hyperv_passthrough
, false),
7585 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU
, hyperv_enforce_cpuid
, false),
7587 /* WS2008R2 identify by default */
7588 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU
, hyperv_ver_id_build
,
7590 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU
, hyperv_ver_id_major
,
7592 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU
, hyperv_ver_id_minor
,
7594 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU
, hyperv_ver_id_sp
, 0),
7595 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU
, hyperv_ver_id_sb
, 0),
7596 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU
, hyperv_ver_id_sn
, 0),
7598 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
7599 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
7600 DEFINE_PROP_BOOL("x-force-features", X86CPU
, force_features
, false),
7601 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
7602 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
7603 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
7604 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU
, host_phys_bits_limit
, 0),
7605 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
7606 DEFINE_PROP_UINT32("level-func7", X86CPU
, env
.cpuid_level_func7
,
7608 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
7609 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
7610 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
7611 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
7612 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
7613 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
7614 DEFINE_PROP_UINT64("ucode-rev", X86CPU
, ucode_rev
, 0),
7615 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
7616 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor
),
7617 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
7618 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU
, vendor_cpuid_only
, true),
7619 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
7620 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
7621 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
7623 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU
, kvm_pv_enforce_cpuid
,
7625 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
7626 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
7627 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU
, migrate_smi_count
,
7630 * lecacy_cache defaults to true unless the CPU model provides its
7631 * own cache information (see x86_cpu_load_def()).
7633 DEFINE_PROP_BOOL("legacy-cache", X86CPU
, legacy_cache
, true),
7634 DEFINE_PROP_BOOL("xen-vapic", X86CPU
, xen_vapic
, false),
7637 * From "Requirements for Implementing the Microsoft
7638 * Hypervisor Interface":
7639 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7641 * "Starting with Windows Server 2012 and Windows 8, if
7642 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7643 * the hypervisor imposes no specific limit to the number of VPs.
7644 * In this case, Windows Server 2012 guest VMs may use more than
7645 * 64 VPs, up to the maximum supported number of processors applicable
7646 * to the specific Windows version being used."
7648 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
7649 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU
, hyperv_synic_kvm_only
,
7651 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU
, intel_pt_auto_level
,
7653 DEFINE_PROP_END_OF_LIST()
7656 #ifndef CONFIG_USER_ONLY
7657 #include "hw/core/sysemu-cpu-ops.h"
7659 static const struct SysemuCPUOps i386_sysemu_ops
= {
7660 .get_memory_mapping
= x86_cpu_get_memory_mapping
,
7661 .get_paging_enabled
= x86_cpu_get_paging_enabled
,
7662 .get_phys_page_attrs_debug
= x86_cpu_get_phys_page_attrs_debug
,
7663 .asidx_from_attrs
= x86_asidx_from_attrs
,
7664 .get_crash_info
= x86_cpu_get_crash_info
,
7665 .write_elf32_note
= x86_cpu_write_elf32_note
,
7666 .write_elf64_note
= x86_cpu_write_elf64_note
,
7667 .write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
,
7668 .write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
,
7669 .legacy_vmsd
= &vmstate_x86_cpu
,
7673 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
7675 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
7676 CPUClass
*cc
= CPU_CLASS(oc
);
7677 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7678 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
7681 device_class_set_parent_realize(dc
, x86_cpu_realizefn
,
7682 &xcc
->parent_realize
);
7683 device_class_set_parent_unrealize(dc
, x86_cpu_unrealizefn
,
7684 &xcc
->parent_unrealize
);
7685 device_class_set_props(dc
, x86_cpu_properties
);
7687 resettable_class_set_parent_phases(rc
, NULL
, x86_cpu_reset_hold
, NULL
,
7688 &xcc
->parent_phases
);
7689 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
7691 cc
->class_by_name
= x86_cpu_class_by_name
;
7692 cc
->parse_features
= x86_cpu_parse_featurestr
;
7693 cc
->has_work
= x86_cpu_has_work
;
7694 cc
->dump_state
= x86_cpu_dump_state
;
7695 cc
->set_pc
= x86_cpu_set_pc
;
7696 cc
->get_pc
= x86_cpu_get_pc
;
7697 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
7698 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
7699 cc
->get_arch_id
= x86_cpu_get_arch_id
;
7701 #ifndef CONFIG_USER_ONLY
7702 cc
->sysemu_ops
= &i386_sysemu_ops
;
7703 #endif /* !CONFIG_USER_ONLY */
7705 cc
->gdb_arch_name
= x86_gdb_arch_name
;
7706 #ifdef TARGET_X86_64
7707 cc
->gdb_core_xml_file
= "i386-64bit.xml";
7708 cc
->gdb_num_core_regs
= 66;
7710 cc
->gdb_core_xml_file
= "i386-32bit.xml";
7711 cc
->gdb_num_core_regs
= 50;
7713 cc
->disas_set_info
= x86_disas_set_info
;
7715 dc
->user_creatable
= true;
7717 object_class_property_add(oc
, "family", "int",
7718 x86_cpuid_version_get_family
,
7719 x86_cpuid_version_set_family
, NULL
, NULL
);
7720 object_class_property_add(oc
, "model", "int",
7721 x86_cpuid_version_get_model
,
7722 x86_cpuid_version_set_model
, NULL
, NULL
);
7723 object_class_property_add(oc
, "stepping", "int",
7724 x86_cpuid_version_get_stepping
,
7725 x86_cpuid_version_set_stepping
, NULL
, NULL
);
7726 object_class_property_add_str(oc
, "vendor",
7727 x86_cpuid_get_vendor
,
7728 x86_cpuid_set_vendor
);
7729 object_class_property_add_str(oc
, "model-id",
7730 x86_cpuid_get_model_id
,
7731 x86_cpuid_set_model_id
);
7732 object_class_property_add(oc
, "tsc-frequency", "int",
7733 x86_cpuid_get_tsc_freq
,
7734 x86_cpuid_set_tsc_freq
, NULL
, NULL
);
7736 * The "unavailable-features" property has the same semantics as
7737 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
7738 * QMP command: they list the features that would have prevented the
7739 * CPU from running if the "enforce" flag was set.
7741 object_class_property_add(oc
, "unavailable-features", "strList",
7742 x86_cpu_get_unavailable_features
,
7745 #if !defined(CONFIG_USER_ONLY)
7746 object_class_property_add(oc
, "crash-information", "GuestPanicInformation",
7747 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
);
7750 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
7752 for (bitnr
= 0; bitnr
< 64; bitnr
++) {
7753 x86_cpu_register_feature_bit_props(xcc
, w
, bitnr
);
7758 static const TypeInfo x86_cpu_type_info
= {
7759 .name
= TYPE_X86_CPU
,
7761 .instance_size
= sizeof(X86CPU
),
7762 .instance_init
= x86_cpu_initfn
,
7763 .instance_post_init
= x86_cpu_post_initfn
,
7766 .class_size
= sizeof(X86CPUClass
),
7767 .class_init
= x86_cpu_common_class_init
,
7770 /* "base" CPU model, used by query-cpu-model-expansion */
7771 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
7773 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
7775 xcc
->static_model
= true;
7776 xcc
->migration_safe
= true;
7777 xcc
->model_description
= "base CPU model type with no features enabled";
7781 static const TypeInfo x86_base_cpu_type_info
= {
7782 .name
= X86_CPU_TYPE_NAME("base"),
7783 .parent
= TYPE_X86_CPU
,
7784 .class_init
= x86_cpu_base_class_init
,
7787 static void x86_cpu_register_types(void)
7791 type_register_static(&x86_cpu_type_info
);
7792 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
7793 x86_register_cpudef_types(&builtin_x86_defs
[i
]);
7795 type_register_static(&max_x86_cpu_type_info
);
7796 type_register_static(&x86_base_cpu_type_info
);
7799 type_init(x86_cpu_register_types
)