2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/cutils.h"
24 #include "exec/exec-all.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/hvf.h"
27 #include "sysemu/cpus.h"
30 #include "qemu/error-report.h"
31 #include "qemu/option.h"
32 #include "qemu/config-file.h"
33 #include "qapi/error.h"
34 #include "qapi/qapi-visit-misc.h"
35 #include "qapi/qapi-visit-run-state.h"
36 #include "qapi/qmp/qdict.h"
37 #include "qapi/qmp/qerror.h"
38 #include "qapi/visitor.h"
39 #include "qom/qom-qobject.h"
40 #include "sysemu/arch_init.h"
42 #if defined(CONFIG_KVM)
43 #include <linux/kvm_para.h>
46 #include "sysemu/sysemu.h"
47 #include "hw/qdev-properties.h"
48 #include "hw/i386/topology.h"
49 #ifndef CONFIG_USER_ONLY
50 #include "exec/address-spaces.h"
52 #include "hw/xen/xen.h"
53 #include "hw/i386/apic_internal.h"
56 #include "disas/capstone.h"
59 /* Cache topology CPUID constants: */
61 /* CPUID Leaf 2 Descriptors */
63 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
64 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
65 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
66 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
69 /* CPUID Leaf 4 constants: */
72 #define CPUID_4_TYPE_DCACHE 1
73 #define CPUID_4_TYPE_ICACHE 2
74 #define CPUID_4_TYPE_UNIFIED 3
76 #define CPUID_4_LEVEL(l) ((l) << 5)
78 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
79 #define CPUID_4_FULLY_ASSOC (1 << 9)
82 #define CPUID_4_NO_INVD_SHARING (1 << 0)
83 #define CPUID_4_INCLUSIVE (1 << 1)
84 #define CPUID_4_COMPLEX_IDX (1 << 2)
86 #define ASSOC_FULL 0xFF
88 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
89 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
99 a == ASSOC_FULL ? 0xF : \
100 0 /* invalid value */)
103 /* Definitions of the hardcoded cache entries we expose: */
106 #define L1D_LINE_SIZE 64
107 #define L1D_ASSOCIATIVITY 8
109 #define L1D_PARTITIONS 1
110 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
111 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
112 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
113 #define L1D_LINES_PER_TAG 1
114 #define L1D_SIZE_KB_AMD 64
115 #define L1D_ASSOCIATIVITY_AMD 2
117 /* L1 instruction cache: */
118 #define L1I_LINE_SIZE 64
119 #define L1I_ASSOCIATIVITY 8
121 #define L1I_PARTITIONS 1
122 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
123 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
124 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
125 #define L1I_LINES_PER_TAG 1
126 #define L1I_SIZE_KB_AMD 64
127 #define L1I_ASSOCIATIVITY_AMD 2
129 /* Level 2 unified cache: */
130 #define L2_LINE_SIZE 64
131 #define L2_ASSOCIATIVITY 16
133 #define L2_PARTITIONS 1
134 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
135 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
136 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
137 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
138 #define L2_LINES_PER_TAG 1
139 #define L2_SIZE_KB_AMD 512
141 /* Level 3 unified cache: */
142 #define L3_SIZE_KB 0 /* disabled */
143 #define L3_ASSOCIATIVITY 0 /* disabled */
144 #define L3_LINES_PER_TAG 0 /* disabled */
145 #define L3_LINE_SIZE 0 /* disabled */
146 #define L3_N_LINE_SIZE 64
147 #define L3_N_ASSOCIATIVITY 16
148 #define L3_N_SETS 16384
149 #define L3_N_PARTITIONS 1
150 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
151 #define L3_N_LINES_PER_TAG 1
152 #define L3_N_SIZE_KB_AMD 16384
154 /* TLB definitions: */
156 #define L1_DTLB_2M_ASSOC 1
157 #define L1_DTLB_2M_ENTRIES 255
158 #define L1_DTLB_4K_ASSOC 1
159 #define L1_DTLB_4K_ENTRIES 255
161 #define L1_ITLB_2M_ASSOC 1
162 #define L1_ITLB_2M_ENTRIES 255
163 #define L1_ITLB_4K_ASSOC 1
164 #define L1_ITLB_4K_ENTRIES 255
166 #define L2_DTLB_2M_ASSOC 0 /* disabled */
167 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
168 #define L2_DTLB_4K_ASSOC 4
169 #define L2_DTLB_4K_ENTRIES 512
171 #define L2_ITLB_2M_ASSOC 0 /* disabled */
172 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
173 #define L2_ITLB_4K_ASSOC 4
174 #define L2_ITLB_4K_ENTRIES 512
178 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
179 uint32_t vendor2
, uint32_t vendor3
)
182 for (i
= 0; i
< 4; i
++) {
183 dst
[i
] = vendor1
>> (8 * i
);
184 dst
[i
+ 4] = vendor2
>> (8 * i
);
185 dst
[i
+ 8] = vendor3
>> (8 * i
);
187 dst
[CPUID_VENDOR_SZ
] = '\0';
190 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
191 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
193 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
194 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
195 CPUID_PSE36 | CPUID_FXSR)
196 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
197 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
198 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
199 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
200 CPUID_PAE | CPUID_SEP | CPUID_APIC)
202 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
203 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
204 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
205 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
206 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
207 /* partly implemented:
208 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
210 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
211 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
212 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
213 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
214 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
215 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
217 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
218 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
219 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
220 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
221 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
224 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
226 #define TCG_EXT2_X86_64_FEATURES 0
229 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
230 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
231 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
232 TCG_EXT2_X86_64_FEATURES)
233 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
234 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
235 #define TCG_EXT4_FEATURES 0
236 #define TCG_SVM_FEATURES 0
237 #define TCG_KVM_FEATURES 0
238 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
239 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
240 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
241 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
244 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
245 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
246 CPUID_7_0_EBX_RDSEED */
247 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
249 #define TCG_7_0_EDX_FEATURES 0
250 #define TCG_APM_FEATURES 0
251 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
252 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
254 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
256 typedef struct FeatureWordInfo
{
257 /* feature flags names are taken from "Intel Processor Identification and
258 * the CPUID Instruction" and AMD's "CPUID Specification".
259 * In cases of disagreement between feature naming conventions,
260 * aliases may be added.
262 const char *feat_names
[32];
263 uint32_t cpuid_eax
; /* Input EAX for CPUID */
264 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
265 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
266 int cpuid_reg
; /* output register (R_* constant) */
267 uint32_t tcg_features
; /* Feature flags supported by TCG */
268 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
269 uint32_t migratable_flags
; /* Feature flags known to be migratable */
272 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
275 "fpu", "vme", "de", "pse",
276 "tsc", "msr", "pae", "mce",
277 "cx8", "apic", NULL
, "sep",
278 "mtrr", "pge", "mca", "cmov",
279 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
280 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
281 "fxsr", "sse", "sse2", "ss",
282 "ht" /* Intel htt */, "tm", "ia64", "pbe",
284 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
285 .tcg_features
= TCG_FEATURES
,
289 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
290 "ds-cpl", "vmx", "smx", "est",
291 "tm2", "ssse3", "cid", NULL
,
292 "fma", "cx16", "xtpr", "pdcm",
293 NULL
, "pcid", "dca", "sse4.1",
294 "sse4.2", "x2apic", "movbe", "popcnt",
295 "tsc-deadline", "aes", "xsave", "osxsave",
296 "avx", "f16c", "rdrand", "hypervisor",
298 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
299 .tcg_features
= TCG_EXT_FEATURES
,
301 /* Feature names that are already defined on feature_name[] but
302 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
303 * names on feat_names below. They are copied automatically
304 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
306 [FEAT_8000_0001_EDX
] = {
308 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
309 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
310 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
311 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
312 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
313 "nx", NULL
, "mmxext", NULL
/* mmx */,
314 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
315 NULL
, "lm", "3dnowext", "3dnow",
317 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
318 .tcg_features
= TCG_EXT2_FEATURES
,
320 [FEAT_8000_0001_ECX
] = {
322 "lahf-lm", "cmp-legacy", "svm", "extapic",
323 "cr8legacy", "abm", "sse4a", "misalignsse",
324 "3dnowprefetch", "osvw", "ibs", "xop",
325 "skinit", "wdt", NULL
, "lwp",
326 "fma4", "tce", NULL
, "nodeid-msr",
327 NULL
, "tbm", "topoext", "perfctr-core",
328 "perfctr-nb", NULL
, NULL
, NULL
,
329 NULL
, NULL
, NULL
, NULL
,
331 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
332 .tcg_features
= TCG_EXT3_FEATURES
,
334 [FEAT_C000_0001_EDX
] = {
336 NULL
, NULL
, "xstore", "xstore-en",
337 NULL
, NULL
, "xcrypt", "xcrypt-en",
338 "ace2", "ace2-en", "phe", "phe-en",
339 "pmm", "pmm-en", NULL
, NULL
,
340 NULL
, NULL
, NULL
, NULL
,
341 NULL
, NULL
, NULL
, NULL
,
342 NULL
, NULL
, NULL
, NULL
,
343 NULL
, NULL
, NULL
, NULL
,
345 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
346 .tcg_features
= TCG_EXT4_FEATURES
,
350 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
351 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
352 NULL
, "kvm-pv-tlb-flush", NULL
, NULL
,
353 NULL
, NULL
, NULL
, NULL
,
354 NULL
, NULL
, NULL
, NULL
,
355 NULL
, NULL
, NULL
, NULL
,
356 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
357 NULL
, NULL
, NULL
, NULL
,
359 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
360 .tcg_features
= TCG_KVM_FEATURES
,
362 [FEAT_HYPERV_EAX
] = {
364 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
365 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
366 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
367 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
368 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
369 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
370 NULL
, NULL
, NULL
, NULL
,
371 NULL
, NULL
, NULL
, NULL
,
372 NULL
, NULL
, NULL
, NULL
,
373 NULL
, NULL
, NULL
, NULL
,
374 NULL
, NULL
, NULL
, NULL
,
376 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EAX
,
378 [FEAT_HYPERV_EBX
] = {
380 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
381 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
382 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
383 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
384 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
385 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
387 NULL
, NULL
, NULL
, NULL
,
388 NULL
, NULL
, NULL
, NULL
,
389 NULL
, NULL
, NULL
, NULL
,
390 NULL
, NULL
, NULL
, NULL
,
392 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EBX
,
394 [FEAT_HYPERV_EDX
] = {
396 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
397 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
398 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
400 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
401 NULL
, NULL
, NULL
, NULL
,
402 NULL
, NULL
, NULL
, NULL
,
403 NULL
, NULL
, NULL
, NULL
,
404 NULL
, NULL
, NULL
, NULL
,
405 NULL
, NULL
, NULL
, NULL
,
407 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EDX
,
411 "npt", "lbrv", "svm-lock", "nrip-save",
412 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
413 NULL
, NULL
, "pause-filter", NULL
,
414 "pfthreshold", NULL
, NULL
, NULL
,
415 NULL
, NULL
, NULL
, NULL
,
416 NULL
, NULL
, NULL
, NULL
,
417 NULL
, NULL
, NULL
, NULL
,
418 NULL
, NULL
, NULL
, NULL
,
420 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
421 .tcg_features
= TCG_SVM_FEATURES
,
425 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
426 "hle", "avx2", NULL
, "smep",
427 "bmi2", "erms", "invpcid", "rtm",
428 NULL
, NULL
, "mpx", NULL
,
429 "avx512f", "avx512dq", "rdseed", "adx",
430 "smap", "avx512ifma", "pcommit", "clflushopt",
431 "clwb", NULL
, "avx512pf", "avx512er",
432 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
435 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
437 .tcg_features
= TCG_7_0_EBX_FEATURES
,
441 NULL
, "avx512vbmi", "umip", "pku",
442 "ospke", NULL
, "avx512vbmi2", NULL
,
443 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
444 "avx512bitalg", NULL
, "avx512-vpopcntdq", NULL
,
445 "la57", NULL
, NULL
, NULL
,
446 NULL
, NULL
, "rdpid", NULL
,
447 NULL
, NULL
, NULL
, NULL
,
448 NULL
, NULL
, NULL
, NULL
,
451 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
453 .tcg_features
= TCG_7_0_ECX_FEATURES
,
457 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
458 NULL
, NULL
, NULL
, NULL
,
459 NULL
, NULL
, NULL
, NULL
,
460 NULL
, NULL
, NULL
, NULL
,
461 NULL
, NULL
, NULL
, NULL
,
462 NULL
, NULL
, NULL
, NULL
,
463 NULL
, NULL
, "spec-ctrl", NULL
,
464 NULL
, NULL
, NULL
, NULL
,
467 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
469 .tcg_features
= TCG_7_0_EDX_FEATURES
,
471 [FEAT_8000_0007_EDX
] = {
473 NULL
, NULL
, NULL
, NULL
,
474 NULL
, NULL
, NULL
, NULL
,
475 "invtsc", NULL
, NULL
, NULL
,
476 NULL
, NULL
, NULL
, NULL
,
477 NULL
, NULL
, NULL
, NULL
,
478 NULL
, NULL
, NULL
, NULL
,
479 NULL
, NULL
, NULL
, NULL
,
480 NULL
, NULL
, NULL
, NULL
,
482 .cpuid_eax
= 0x80000007,
484 .tcg_features
= TCG_APM_FEATURES
,
485 .unmigratable_flags
= CPUID_APM_INVTSC
,
487 [FEAT_8000_0008_EBX
] = {
489 NULL
, NULL
, NULL
, NULL
,
490 NULL
, NULL
, NULL
, NULL
,
491 NULL
, NULL
, NULL
, NULL
,
492 "ibpb", NULL
, NULL
, NULL
,
493 NULL
, NULL
, NULL
, NULL
,
494 NULL
, NULL
, NULL
, NULL
,
495 NULL
, NULL
, NULL
, NULL
,
496 NULL
, NULL
, NULL
, NULL
,
498 .cpuid_eax
= 0x80000008,
501 .unmigratable_flags
= 0,
505 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
506 NULL
, NULL
, NULL
, NULL
,
507 NULL
, NULL
, NULL
, NULL
,
508 NULL
, NULL
, NULL
, NULL
,
509 NULL
, NULL
, NULL
, NULL
,
510 NULL
, NULL
, NULL
, NULL
,
511 NULL
, NULL
, NULL
, NULL
,
512 NULL
, NULL
, NULL
, NULL
,
515 .cpuid_needs_ecx
= true, .cpuid_ecx
= 1,
517 .tcg_features
= TCG_XSAVE_FEATURES
,
521 NULL
, NULL
, "arat", NULL
,
522 NULL
, NULL
, NULL
, NULL
,
523 NULL
, NULL
, NULL
, NULL
,
524 NULL
, NULL
, NULL
, NULL
,
525 NULL
, NULL
, NULL
, NULL
,
526 NULL
, NULL
, NULL
, NULL
,
527 NULL
, NULL
, NULL
, NULL
,
528 NULL
, NULL
, NULL
, NULL
,
530 .cpuid_eax
= 6, .cpuid_reg
= R_EAX
,
531 .tcg_features
= TCG_6_EAX_FEATURES
,
533 [FEAT_XSAVE_COMP_LO
] = {
535 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
538 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
539 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
540 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
543 [FEAT_XSAVE_COMP_HI
] = {
545 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
551 typedef struct X86RegisterInfo32
{
552 /* Name of register */
554 /* QAPI enum value register */
555 X86CPURegister32 qapi_enum
;
558 #define REGISTER(reg) \
559 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
560 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
572 typedef struct ExtSaveArea
{
573 uint32_t feature
, bits
;
574 uint32_t offset
, size
;
577 static const ExtSaveArea x86_ext_save_areas
[] = {
579 /* x87 FP state component is always enabled if XSAVE is supported */
580 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
581 /* x87 state is in the legacy region of the XSAVE area */
583 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
586 /* SSE state component is always enabled if XSAVE is supported */
587 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
588 /* SSE state is in the legacy region of the XSAVE area */
590 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
593 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
594 .offset
= offsetof(X86XSaveArea
, avx_state
),
595 .size
= sizeof(XSaveAVX
) },
596 [XSTATE_BNDREGS_BIT
] =
597 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
598 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
599 .size
= sizeof(XSaveBNDREG
) },
600 [XSTATE_BNDCSR_BIT
] =
601 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
602 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
603 .size
= sizeof(XSaveBNDCSR
) },
604 [XSTATE_OPMASK_BIT
] =
605 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
606 .offset
= offsetof(X86XSaveArea
, opmask_state
),
607 .size
= sizeof(XSaveOpmask
) },
608 [XSTATE_ZMM_Hi256_BIT
] =
609 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
610 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
611 .size
= sizeof(XSaveZMM_Hi256
) },
612 [XSTATE_Hi16_ZMM_BIT
] =
613 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
614 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
615 .size
= sizeof(XSaveHi16_ZMM
) },
617 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
618 .offset
= offsetof(X86XSaveArea
, pkru_state
),
619 .size
= sizeof(XSavePKRU
) },
622 static uint32_t xsave_area_size(uint64_t mask
)
627 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
628 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
629 if ((mask
>> i
) & 1) {
630 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
636 static inline bool accel_uses_host_cpuid(void)
638 return kvm_enabled() || hvf_enabled();
641 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
643 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
644 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
647 const char *get_register_name_32(unsigned int reg
)
649 if (reg
>= CPU_NB_REGS32
) {
652 return x86_reg_info_32
[reg
].name
;
656 * Returns the set of feature flags that are supported and migratable by
657 * QEMU, for a given FeatureWord.
659 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
661 FeatureWordInfo
*wi
= &feature_word_info
[w
];
665 for (i
= 0; i
< 32; i
++) {
666 uint32_t f
= 1U << i
;
668 /* If the feature name is known, it is implicitly considered migratable,
669 * unless it is explicitly set in unmigratable_flags */
670 if ((wi
->migratable_flags
& f
) ||
671 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
678 void host_cpuid(uint32_t function
, uint32_t count
,
679 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
685 : "=a"(vec
[0]), "=b"(vec
[1]),
686 "=c"(vec
[2]), "=d"(vec
[3])
687 : "0"(function
), "c"(count
) : "cc");
688 #elif defined(__i386__)
689 asm volatile("pusha \n\t"
691 "mov %%eax, 0(%2) \n\t"
692 "mov %%ebx, 4(%2) \n\t"
693 "mov %%ecx, 8(%2) \n\t"
694 "mov %%edx, 12(%2) \n\t"
696 : : "a"(function
), "c"(count
), "S"(vec
)
712 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
)
714 uint32_t eax
, ebx
, ecx
, edx
;
716 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
717 x86_cpu_vendor_words2str(vendor
, ebx
, edx
, ecx
);
719 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
721 *family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
724 *model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
727 *stepping
= eax
& 0x0F;
731 /* CPU class name definitions: */
733 /* Return type name for a given CPU model name
734 * Caller is responsible for freeing the returned string.
736 static char *x86_cpu_type_name(const char *model_name
)
738 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
741 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
746 if (cpu_model
== NULL
) {
750 typename
= x86_cpu_type_name(cpu_model
);
751 oc
= object_class_by_name(typename
);
756 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
758 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
759 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
760 return g_strndup(class_name
,
761 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
764 struct X86CPUDefinition
{
768 /* vendor is zero-terminated, 12 character ASCII string */
769 char vendor
[CPUID_VENDOR_SZ
+ 1];
773 FeatureWordArray features
;
774 const char *model_id
;
777 static X86CPUDefinition builtin_x86_defs
[] = {
781 .vendor
= CPUID_VENDOR_AMD
,
785 .features
[FEAT_1_EDX
] =
787 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
789 .features
[FEAT_1_ECX
] =
790 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
791 .features
[FEAT_8000_0001_EDX
] =
792 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
793 .features
[FEAT_8000_0001_ECX
] =
794 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
795 .xlevel
= 0x8000000A,
796 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
801 .vendor
= CPUID_VENDOR_AMD
,
805 /* Missing: CPUID_HT */
806 .features
[FEAT_1_EDX
] =
808 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
809 CPUID_PSE36
| CPUID_VME
,
810 .features
[FEAT_1_ECX
] =
811 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
813 .features
[FEAT_8000_0001_EDX
] =
814 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
815 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
816 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
817 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
819 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
820 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
821 .features
[FEAT_8000_0001_ECX
] =
822 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
823 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
824 /* Missing: CPUID_SVM_LBRV */
825 .features
[FEAT_SVM
] =
827 .xlevel
= 0x8000001A,
828 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
833 .vendor
= CPUID_VENDOR_INTEL
,
837 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
838 .features
[FEAT_1_EDX
] =
840 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
841 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
842 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
843 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
844 .features
[FEAT_1_ECX
] =
845 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
847 .features
[FEAT_8000_0001_EDX
] =
848 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
849 .features
[FEAT_8000_0001_ECX
] =
851 .xlevel
= 0x80000008,
852 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
857 .vendor
= CPUID_VENDOR_INTEL
,
861 /* Missing: CPUID_HT */
862 .features
[FEAT_1_EDX
] =
863 PPRO_FEATURES
| CPUID_VME
|
864 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
866 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
867 .features
[FEAT_1_ECX
] =
868 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
869 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
870 .features
[FEAT_8000_0001_EDX
] =
871 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
872 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
873 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
874 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
875 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
876 .features
[FEAT_8000_0001_ECX
] =
878 .xlevel
= 0x80000008,
879 .model_id
= "Common KVM processor"
884 .vendor
= CPUID_VENDOR_INTEL
,
888 .features
[FEAT_1_EDX
] =
890 .features
[FEAT_1_ECX
] =
892 .xlevel
= 0x80000004,
893 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
898 .vendor
= CPUID_VENDOR_INTEL
,
902 .features
[FEAT_1_EDX
] =
903 PPRO_FEATURES
| CPUID_VME
|
904 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
905 .features
[FEAT_1_ECX
] =
907 .features
[FEAT_8000_0001_ECX
] =
909 .xlevel
= 0x80000008,
910 .model_id
= "Common 32-bit KVM processor"
915 .vendor
= CPUID_VENDOR_INTEL
,
919 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
920 .features
[FEAT_1_EDX
] =
921 PPRO_FEATURES
| CPUID_VME
|
922 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
924 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
925 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
926 .features
[FEAT_1_ECX
] =
927 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
928 .features
[FEAT_8000_0001_EDX
] =
930 .xlevel
= 0x80000008,
931 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
936 .vendor
= CPUID_VENDOR_INTEL
,
940 .features
[FEAT_1_EDX
] =
948 .vendor
= CPUID_VENDOR_INTEL
,
952 .features
[FEAT_1_EDX
] =
960 .vendor
= CPUID_VENDOR_INTEL
,
964 .features
[FEAT_1_EDX
] =
972 .vendor
= CPUID_VENDOR_INTEL
,
976 .features
[FEAT_1_EDX
] =
984 .vendor
= CPUID_VENDOR_AMD
,
988 .features
[FEAT_1_EDX
] =
989 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
991 .features
[FEAT_8000_0001_EDX
] =
992 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
993 .xlevel
= 0x80000008,
994 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
999 .vendor
= CPUID_VENDOR_INTEL
,
1003 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1004 .features
[FEAT_1_EDX
] =
1006 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
1007 CPUID_ACPI
| CPUID_SS
,
1008 /* Some CPUs got no CPUID_SEP */
1009 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1011 .features
[FEAT_1_ECX
] =
1012 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
1014 .features
[FEAT_8000_0001_EDX
] =
1016 .features
[FEAT_8000_0001_ECX
] =
1018 .xlevel
= 0x80000008,
1019 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1024 .vendor
= CPUID_VENDOR_INTEL
,
1028 .features
[FEAT_1_EDX
] =
1029 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1030 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1031 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1032 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1033 CPUID_DE
| CPUID_FP87
,
1034 .features
[FEAT_1_ECX
] =
1035 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1036 .features
[FEAT_8000_0001_EDX
] =
1037 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1038 .features
[FEAT_8000_0001_ECX
] =
1040 .xlevel
= 0x80000008,
1041 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1046 .vendor
= CPUID_VENDOR_INTEL
,
1050 .features
[FEAT_1_EDX
] =
1051 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1052 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1053 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1054 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1055 CPUID_DE
| CPUID_FP87
,
1056 .features
[FEAT_1_ECX
] =
1057 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1059 .features
[FEAT_8000_0001_EDX
] =
1060 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1061 .features
[FEAT_8000_0001_ECX
] =
1063 .xlevel
= 0x80000008,
1064 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1069 .vendor
= CPUID_VENDOR_INTEL
,
1073 .features
[FEAT_1_EDX
] =
1074 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1075 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1076 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1077 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1078 CPUID_DE
| CPUID_FP87
,
1079 .features
[FEAT_1_ECX
] =
1080 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1081 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1082 .features
[FEAT_8000_0001_EDX
] =
1083 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1084 .features
[FEAT_8000_0001_ECX
] =
1086 .xlevel
= 0x80000008,
1087 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
1090 .name
= "Nehalem-IBRS",
1092 .vendor
= CPUID_VENDOR_INTEL
,
1096 .features
[FEAT_1_EDX
] =
1097 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1098 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1099 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1100 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1101 CPUID_DE
| CPUID_FP87
,
1102 .features
[FEAT_1_ECX
] =
1103 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1104 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1105 .features
[FEAT_7_0_EDX
] =
1106 CPUID_7_0_EDX_SPEC_CTRL
,
1107 .features
[FEAT_8000_0001_EDX
] =
1108 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1109 .features
[FEAT_8000_0001_ECX
] =
1111 .xlevel
= 0x80000008,
1112 .model_id
= "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1117 .vendor
= CPUID_VENDOR_INTEL
,
1121 .features
[FEAT_1_EDX
] =
1122 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1123 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1124 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1125 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1126 CPUID_DE
| CPUID_FP87
,
1127 .features
[FEAT_1_ECX
] =
1128 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1129 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1130 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1131 .features
[FEAT_8000_0001_EDX
] =
1132 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1133 .features
[FEAT_8000_0001_ECX
] =
1135 .features
[FEAT_6_EAX
] =
1137 .xlevel
= 0x80000008,
1138 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1141 .name
= "Westmere-IBRS",
1143 .vendor
= CPUID_VENDOR_INTEL
,
1147 .features
[FEAT_1_EDX
] =
1148 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1149 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1150 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1151 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1152 CPUID_DE
| CPUID_FP87
,
1153 .features
[FEAT_1_ECX
] =
1154 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1155 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1156 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1157 .features
[FEAT_8000_0001_EDX
] =
1158 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1159 .features
[FEAT_8000_0001_ECX
] =
1161 .features
[FEAT_7_0_EDX
] =
1162 CPUID_7_0_EDX_SPEC_CTRL
,
1163 .features
[FEAT_6_EAX
] =
1165 .xlevel
= 0x80000008,
1166 .model_id
= "Westmere E56xx/L56xx/X56xx (IBRS update)",
1169 .name
= "SandyBridge",
1171 .vendor
= CPUID_VENDOR_INTEL
,
1175 .features
[FEAT_1_EDX
] =
1176 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1177 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1178 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1179 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1180 CPUID_DE
| CPUID_FP87
,
1181 .features
[FEAT_1_ECX
] =
1182 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1183 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1184 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1185 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1187 .features
[FEAT_8000_0001_EDX
] =
1188 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1190 .features
[FEAT_8000_0001_ECX
] =
1192 .features
[FEAT_XSAVE
] =
1193 CPUID_XSAVE_XSAVEOPT
,
1194 .features
[FEAT_6_EAX
] =
1196 .xlevel
= 0x80000008,
1197 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1200 .name
= "SandyBridge-IBRS",
1202 .vendor
= CPUID_VENDOR_INTEL
,
1206 .features
[FEAT_1_EDX
] =
1207 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1208 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1209 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1210 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1211 CPUID_DE
| CPUID_FP87
,
1212 .features
[FEAT_1_ECX
] =
1213 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1214 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1215 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1216 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1218 .features
[FEAT_8000_0001_EDX
] =
1219 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1221 .features
[FEAT_8000_0001_ECX
] =
1223 .features
[FEAT_7_0_EDX
] =
1224 CPUID_7_0_EDX_SPEC_CTRL
,
1225 .features
[FEAT_XSAVE
] =
1226 CPUID_XSAVE_XSAVEOPT
,
1227 .features
[FEAT_6_EAX
] =
1229 .xlevel
= 0x80000008,
1230 .model_id
= "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1233 .name
= "IvyBridge",
1235 .vendor
= CPUID_VENDOR_INTEL
,
1239 .features
[FEAT_1_EDX
] =
1240 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1241 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1242 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1243 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1244 CPUID_DE
| CPUID_FP87
,
1245 .features
[FEAT_1_ECX
] =
1246 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1247 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1248 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1249 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1250 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1251 .features
[FEAT_7_0_EBX
] =
1252 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1254 .features
[FEAT_8000_0001_EDX
] =
1255 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1257 .features
[FEAT_8000_0001_ECX
] =
1259 .features
[FEAT_XSAVE
] =
1260 CPUID_XSAVE_XSAVEOPT
,
1261 .features
[FEAT_6_EAX
] =
1263 .xlevel
= 0x80000008,
1264 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1267 .name
= "IvyBridge-IBRS",
1269 .vendor
= CPUID_VENDOR_INTEL
,
1273 .features
[FEAT_1_EDX
] =
1274 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1275 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1276 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1277 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1278 CPUID_DE
| CPUID_FP87
,
1279 .features
[FEAT_1_ECX
] =
1280 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1281 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1282 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1283 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1284 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1285 .features
[FEAT_7_0_EBX
] =
1286 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1288 .features
[FEAT_8000_0001_EDX
] =
1289 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1291 .features
[FEAT_8000_0001_ECX
] =
1293 .features
[FEAT_7_0_EDX
] =
1294 CPUID_7_0_EDX_SPEC_CTRL
,
1295 .features
[FEAT_XSAVE
] =
1296 CPUID_XSAVE_XSAVEOPT
,
1297 .features
[FEAT_6_EAX
] =
1299 .xlevel
= 0x80000008,
1300 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
1303 .name
= "Haswell-noTSX",
1305 .vendor
= CPUID_VENDOR_INTEL
,
1309 .features
[FEAT_1_EDX
] =
1310 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1311 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1312 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1313 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1314 CPUID_DE
| CPUID_FP87
,
1315 .features
[FEAT_1_ECX
] =
1316 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1317 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1318 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1319 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1320 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1321 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1322 .features
[FEAT_8000_0001_EDX
] =
1323 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1325 .features
[FEAT_8000_0001_ECX
] =
1326 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1327 .features
[FEAT_7_0_EBX
] =
1328 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1329 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1330 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1331 .features
[FEAT_XSAVE
] =
1332 CPUID_XSAVE_XSAVEOPT
,
1333 .features
[FEAT_6_EAX
] =
1335 .xlevel
= 0x80000008,
1336 .model_id
= "Intel Core Processor (Haswell, no TSX)",
1339 .name
= "Haswell-noTSX-IBRS",
1341 .vendor
= CPUID_VENDOR_INTEL
,
1345 .features
[FEAT_1_EDX
] =
1346 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1347 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1348 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1349 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1350 CPUID_DE
| CPUID_FP87
,
1351 .features
[FEAT_1_ECX
] =
1352 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1353 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1354 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1355 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1356 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1357 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1358 .features
[FEAT_8000_0001_EDX
] =
1359 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1361 .features
[FEAT_8000_0001_ECX
] =
1362 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1363 .features
[FEAT_7_0_EDX
] =
1364 CPUID_7_0_EDX_SPEC_CTRL
,
1365 .features
[FEAT_7_0_EBX
] =
1366 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1367 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1368 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1369 .features
[FEAT_XSAVE
] =
1370 CPUID_XSAVE_XSAVEOPT
,
1371 .features
[FEAT_6_EAX
] =
1373 .xlevel
= 0x80000008,
1374 .model_id
= "Intel Core Processor (Haswell, no TSX, IBRS)",
1379 .vendor
= CPUID_VENDOR_INTEL
,
1383 .features
[FEAT_1_EDX
] =
1384 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1385 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1386 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1387 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1388 CPUID_DE
| CPUID_FP87
,
1389 .features
[FEAT_1_ECX
] =
1390 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1391 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1392 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1393 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1394 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1395 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1396 .features
[FEAT_8000_0001_EDX
] =
1397 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1399 .features
[FEAT_8000_0001_ECX
] =
1400 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1401 .features
[FEAT_7_0_EBX
] =
1402 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1403 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1404 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1406 .features
[FEAT_XSAVE
] =
1407 CPUID_XSAVE_XSAVEOPT
,
1408 .features
[FEAT_6_EAX
] =
1410 .xlevel
= 0x80000008,
1411 .model_id
= "Intel Core Processor (Haswell)",
1414 .name
= "Haswell-IBRS",
1416 .vendor
= CPUID_VENDOR_INTEL
,
1420 .features
[FEAT_1_EDX
] =
1421 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1422 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1423 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1424 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1425 CPUID_DE
| CPUID_FP87
,
1426 .features
[FEAT_1_ECX
] =
1427 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1428 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1429 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1430 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1431 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1432 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1433 .features
[FEAT_8000_0001_EDX
] =
1434 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1436 .features
[FEAT_8000_0001_ECX
] =
1437 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1438 .features
[FEAT_7_0_EDX
] =
1439 CPUID_7_0_EDX_SPEC_CTRL
,
1440 .features
[FEAT_7_0_EBX
] =
1441 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1442 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1443 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1445 .features
[FEAT_XSAVE
] =
1446 CPUID_XSAVE_XSAVEOPT
,
1447 .features
[FEAT_6_EAX
] =
1449 .xlevel
= 0x80000008,
1450 .model_id
= "Intel Core Processor (Haswell, IBRS)",
1453 .name
= "Broadwell-noTSX",
1455 .vendor
= CPUID_VENDOR_INTEL
,
1459 .features
[FEAT_1_EDX
] =
1460 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1461 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1462 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1463 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1464 CPUID_DE
| CPUID_FP87
,
1465 .features
[FEAT_1_ECX
] =
1466 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1467 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1468 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1469 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1470 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1471 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1472 .features
[FEAT_8000_0001_EDX
] =
1473 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1475 .features
[FEAT_8000_0001_ECX
] =
1476 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1477 .features
[FEAT_7_0_EBX
] =
1478 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1479 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1480 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1481 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1483 .features
[FEAT_XSAVE
] =
1484 CPUID_XSAVE_XSAVEOPT
,
1485 .features
[FEAT_6_EAX
] =
1487 .xlevel
= 0x80000008,
1488 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
1491 .name
= "Broadwell-noTSX-IBRS",
1493 .vendor
= CPUID_VENDOR_INTEL
,
1497 .features
[FEAT_1_EDX
] =
1498 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1499 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1500 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1501 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1502 CPUID_DE
| CPUID_FP87
,
1503 .features
[FEAT_1_ECX
] =
1504 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1505 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1506 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1507 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1508 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1509 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1510 .features
[FEAT_8000_0001_EDX
] =
1511 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1513 .features
[FEAT_8000_0001_ECX
] =
1514 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1515 .features
[FEAT_7_0_EDX
] =
1516 CPUID_7_0_EDX_SPEC_CTRL
,
1517 .features
[FEAT_7_0_EBX
] =
1518 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1519 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1520 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1521 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1523 .features
[FEAT_XSAVE
] =
1524 CPUID_XSAVE_XSAVEOPT
,
1525 .features
[FEAT_6_EAX
] =
1527 .xlevel
= 0x80000008,
1528 .model_id
= "Intel Core Processor (Broadwell, no TSX, IBRS)",
1531 .name
= "Broadwell",
1533 .vendor
= CPUID_VENDOR_INTEL
,
1537 .features
[FEAT_1_EDX
] =
1538 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1539 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1540 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1541 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1542 CPUID_DE
| CPUID_FP87
,
1543 .features
[FEAT_1_ECX
] =
1544 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1545 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1546 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1547 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1548 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1549 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1550 .features
[FEAT_8000_0001_EDX
] =
1551 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1553 .features
[FEAT_8000_0001_ECX
] =
1554 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1555 .features
[FEAT_7_0_EBX
] =
1556 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1557 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1558 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1559 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1561 .features
[FEAT_XSAVE
] =
1562 CPUID_XSAVE_XSAVEOPT
,
1563 .features
[FEAT_6_EAX
] =
1565 .xlevel
= 0x80000008,
1566 .model_id
= "Intel Core Processor (Broadwell)",
1569 .name
= "Broadwell-IBRS",
1571 .vendor
= CPUID_VENDOR_INTEL
,
1575 .features
[FEAT_1_EDX
] =
1576 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1577 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1578 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1579 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1580 CPUID_DE
| CPUID_FP87
,
1581 .features
[FEAT_1_ECX
] =
1582 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1583 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1584 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1585 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1586 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1587 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1588 .features
[FEAT_8000_0001_EDX
] =
1589 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1591 .features
[FEAT_8000_0001_ECX
] =
1592 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1593 .features
[FEAT_7_0_EDX
] =
1594 CPUID_7_0_EDX_SPEC_CTRL
,
1595 .features
[FEAT_7_0_EBX
] =
1596 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1597 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1598 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1599 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1601 .features
[FEAT_XSAVE
] =
1602 CPUID_XSAVE_XSAVEOPT
,
1603 .features
[FEAT_6_EAX
] =
1605 .xlevel
= 0x80000008,
1606 .model_id
= "Intel Core Processor (Broadwell, IBRS)",
1609 .name
= "Skylake-Client",
1611 .vendor
= CPUID_VENDOR_INTEL
,
1615 .features
[FEAT_1_EDX
] =
1616 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1617 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1618 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1619 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1620 CPUID_DE
| CPUID_FP87
,
1621 .features
[FEAT_1_ECX
] =
1622 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1623 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1624 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1625 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1626 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1627 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1628 .features
[FEAT_8000_0001_EDX
] =
1629 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1631 .features
[FEAT_8000_0001_ECX
] =
1632 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1633 .features
[FEAT_7_0_EBX
] =
1634 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1635 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1636 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1637 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1638 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
,
1639 /* Missing: XSAVES (not supported by some Linux versions,
1640 * including v4.1 to v4.12).
1641 * KVM doesn't yet expose any XSAVES state save component,
1642 * and the only one defined in Skylake (processor tracing)
1643 * probably will block migration anyway.
1645 .features
[FEAT_XSAVE
] =
1646 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1647 CPUID_XSAVE_XGETBV1
,
1648 .features
[FEAT_6_EAX
] =
1650 .xlevel
= 0x80000008,
1651 .model_id
= "Intel Core Processor (Skylake)",
1654 .name
= "Skylake-Client-IBRS",
1656 .vendor
= CPUID_VENDOR_INTEL
,
1660 .features
[FEAT_1_EDX
] =
1661 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1662 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1663 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1664 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1665 CPUID_DE
| CPUID_FP87
,
1666 .features
[FEAT_1_ECX
] =
1667 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1668 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1669 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1670 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1671 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1672 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1673 .features
[FEAT_8000_0001_EDX
] =
1674 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1676 .features
[FEAT_8000_0001_ECX
] =
1677 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1678 .features
[FEAT_7_0_EDX
] =
1679 CPUID_7_0_EDX_SPEC_CTRL
,
1680 .features
[FEAT_7_0_EBX
] =
1681 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1682 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1683 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1684 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1685 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
,
1686 /* Missing: XSAVES (not supported by some Linux versions,
1687 * including v4.1 to v4.12).
1688 * KVM doesn't yet expose any XSAVES state save component,
1689 * and the only one defined in Skylake (processor tracing)
1690 * probably will block migration anyway.
1692 .features
[FEAT_XSAVE
] =
1693 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1694 CPUID_XSAVE_XGETBV1
,
1695 .features
[FEAT_6_EAX
] =
1697 .xlevel
= 0x80000008,
1698 .model_id
= "Intel Core Processor (Skylake, IBRS)",
1701 .name
= "Skylake-Server",
1703 .vendor
= CPUID_VENDOR_INTEL
,
1707 .features
[FEAT_1_EDX
] =
1708 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1709 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1710 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1711 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1712 CPUID_DE
| CPUID_FP87
,
1713 .features
[FEAT_1_ECX
] =
1714 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1715 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1716 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1717 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1718 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1719 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1720 .features
[FEAT_8000_0001_EDX
] =
1721 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
1722 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1723 .features
[FEAT_8000_0001_ECX
] =
1724 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1725 .features
[FEAT_7_0_EBX
] =
1726 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1727 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1728 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1729 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1730 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_CLWB
|
1731 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
1732 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
1733 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
1734 /* Missing: XSAVES (not supported by some Linux versions,
1735 * including v4.1 to v4.12).
1736 * KVM doesn't yet expose any XSAVES state save component,
1737 * and the only one defined in Skylake (processor tracing)
1738 * probably will block migration anyway.
1740 .features
[FEAT_XSAVE
] =
1741 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1742 CPUID_XSAVE_XGETBV1
,
1743 .features
[FEAT_6_EAX
] =
1745 .xlevel
= 0x80000008,
1746 .model_id
= "Intel Xeon Processor (Skylake)",
1749 .name
= "Skylake-Server-IBRS",
1751 .vendor
= CPUID_VENDOR_INTEL
,
1755 .features
[FEAT_1_EDX
] =
1756 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1757 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1758 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1759 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1760 CPUID_DE
| CPUID_FP87
,
1761 .features
[FEAT_1_ECX
] =
1762 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1763 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1764 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1765 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1766 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1767 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1768 .features
[FEAT_8000_0001_EDX
] =
1769 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
1770 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1771 .features
[FEAT_8000_0001_ECX
] =
1772 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1773 .features
[FEAT_7_0_EDX
] =
1774 CPUID_7_0_EDX_SPEC_CTRL
,
1775 .features
[FEAT_7_0_EBX
] =
1776 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1777 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1778 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1779 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1780 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_CLWB
|
1781 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
1782 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
1783 CPUID_7_0_EBX_AVX512VL
,
1784 /* Missing: XSAVES (not supported by some Linux versions,
1785 * including v4.1 to v4.12).
1786 * KVM doesn't yet expose any XSAVES state save component,
1787 * and the only one defined in Skylake (processor tracing)
1788 * probably will block migration anyway.
1790 .features
[FEAT_XSAVE
] =
1791 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1792 CPUID_XSAVE_XGETBV1
,
1793 .features
[FEAT_6_EAX
] =
1795 .xlevel
= 0x80000008,
1796 .model_id
= "Intel Xeon Processor (Skylake, IBRS)",
1799 .name
= "Opteron_G1",
1801 .vendor
= CPUID_VENDOR_AMD
,
1805 .features
[FEAT_1_EDX
] =
1806 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1807 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1808 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1809 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1810 CPUID_DE
| CPUID_FP87
,
1811 .features
[FEAT_1_ECX
] =
1813 .features
[FEAT_8000_0001_EDX
] =
1814 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1815 .xlevel
= 0x80000008,
1816 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1819 .name
= "Opteron_G2",
1821 .vendor
= CPUID_VENDOR_AMD
,
1825 .features
[FEAT_1_EDX
] =
1826 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1827 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1828 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1829 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1830 CPUID_DE
| CPUID_FP87
,
1831 .features
[FEAT_1_ECX
] =
1832 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1833 /* Missing: CPUID_EXT2_RDTSCP */
1834 .features
[FEAT_8000_0001_EDX
] =
1835 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1836 .features
[FEAT_8000_0001_ECX
] =
1837 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1838 .xlevel
= 0x80000008,
1839 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1842 .name
= "Opteron_G3",
1844 .vendor
= CPUID_VENDOR_AMD
,
1848 .features
[FEAT_1_EDX
] =
1849 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1850 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1851 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1852 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1853 CPUID_DE
| CPUID_FP87
,
1854 .features
[FEAT_1_ECX
] =
1855 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1857 /* Missing: CPUID_EXT2_RDTSCP */
1858 .features
[FEAT_8000_0001_EDX
] =
1859 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1860 .features
[FEAT_8000_0001_ECX
] =
1861 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1862 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1863 .xlevel
= 0x80000008,
1864 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1867 .name
= "Opteron_G4",
1869 .vendor
= CPUID_VENDOR_AMD
,
1873 .features
[FEAT_1_EDX
] =
1874 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1875 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1876 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1877 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1878 CPUID_DE
| CPUID_FP87
,
1879 .features
[FEAT_1_ECX
] =
1880 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1881 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1882 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1884 /* Missing: CPUID_EXT2_RDTSCP */
1885 .features
[FEAT_8000_0001_EDX
] =
1886 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1888 .features
[FEAT_8000_0001_ECX
] =
1889 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1890 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1891 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1894 .xlevel
= 0x8000001A,
1895 .model_id
= "AMD Opteron 62xx class CPU",
1898 .name
= "Opteron_G5",
1900 .vendor
= CPUID_VENDOR_AMD
,
1904 .features
[FEAT_1_EDX
] =
1905 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1906 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1907 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1908 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1909 CPUID_DE
| CPUID_FP87
,
1910 .features
[FEAT_1_ECX
] =
1911 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1912 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1913 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1914 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1915 /* Missing: CPUID_EXT2_RDTSCP */
1916 .features
[FEAT_8000_0001_EDX
] =
1917 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1919 .features
[FEAT_8000_0001_ECX
] =
1920 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1921 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1922 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1925 .xlevel
= 0x8000001A,
1926 .model_id
= "AMD Opteron 63xx class CPU",
1931 .vendor
= CPUID_VENDOR_AMD
,
1935 .features
[FEAT_1_EDX
] =
1936 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
1937 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
1938 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
1939 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
1940 CPUID_VME
| CPUID_FP87
,
1941 .features
[FEAT_1_ECX
] =
1942 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
1943 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
1944 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1945 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
1946 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1947 .features
[FEAT_8000_0001_EDX
] =
1948 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
1949 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
1951 .features
[FEAT_8000_0001_ECX
] =
1952 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
1953 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
1954 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1955 .features
[FEAT_7_0_EBX
] =
1956 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
1957 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
1958 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
1959 CPUID_7_0_EBX_SHA_NI
,
1960 /* Missing: XSAVES (not supported by some Linux versions,
1961 * including v4.1 to v4.12).
1962 * KVM doesn't yet expose any XSAVES state save component.
1964 .features
[FEAT_XSAVE
] =
1965 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1966 CPUID_XSAVE_XGETBV1
,
1967 .features
[FEAT_6_EAX
] =
1969 .xlevel
= 0x8000000A,
1970 .model_id
= "AMD EPYC Processor",
1973 .name
= "EPYC-IBPB",
1975 .vendor
= CPUID_VENDOR_AMD
,
1979 .features
[FEAT_1_EDX
] =
1980 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
1981 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
1982 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
1983 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
1984 CPUID_VME
| CPUID_FP87
,
1985 .features
[FEAT_1_ECX
] =
1986 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
1987 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
1988 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1989 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
1990 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1991 .features
[FEAT_8000_0001_EDX
] =
1992 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
1993 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
1995 .features
[FEAT_8000_0001_ECX
] =
1996 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
1997 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
1998 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1999 .features
[FEAT_8000_0008_EBX
] =
2000 CPUID_8000_0008_EBX_IBPB
,
2001 .features
[FEAT_7_0_EBX
] =
2002 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
2003 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
2004 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
2005 CPUID_7_0_EBX_SHA_NI
,
2006 /* Missing: XSAVES (not supported by some Linux versions,
2007 * including v4.1 to v4.12).
2008 * KVM doesn't yet expose any XSAVES state save component.
2010 .features
[FEAT_XSAVE
] =
2011 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
2012 CPUID_XSAVE_XGETBV1
,
2013 .features
[FEAT_6_EAX
] =
2015 .xlevel
= 0x8000000A,
2016 .model_id
= "AMD EPYC Processor (with IBPB)",
2020 typedef struct PropValue
{
2021 const char *prop
, *value
;
2024 /* KVM-specific features that are automatically added/removed
2025 * from all CPU models when KVM is enabled.
2027 static PropValue kvm_default_props
[] = {
2028 { "kvmclock", "on" },
2029 { "kvm-nopiodelay", "on" },
2030 { "kvm-asyncpf", "on" },
2031 { "kvm-steal-time", "on" },
2032 { "kvm-pv-eoi", "on" },
2033 { "kvmclock-stable-bit", "on" },
2036 { "monitor", "off" },
2041 /* TCG-specific defaults that override all CPU models when using TCG
2043 static PropValue tcg_default_props
[] = {
2049 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
2052 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
2053 if (!strcmp(pv
->prop
, prop
)) {
2059 /* It is valid to call this function only for properties that
2060 * are already present in the kvm_default_props table.
2065 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2066 bool migratable_only
);
2068 static bool lmce_supported(void)
2070 uint64_t mce_cap
= 0;
2073 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
2078 return !!(mce_cap
& MCG_LMCE_P
);
2081 #define CPUID_MODEL_ID_SZ 48
2084 * cpu_x86_fill_model_id:
2085 * Get CPUID model ID string from host CPU.
2087 * @str should have at least CPUID_MODEL_ID_SZ bytes
2089 * The function does NOT add a null terminator to the string
2092 static int cpu_x86_fill_model_id(char *str
)
2094 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
2097 for (i
= 0; i
< 3; i
++) {
2098 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
2099 memcpy(str
+ i
* 16 + 0, &eax
, 4);
2100 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
2101 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
2102 memcpy(str
+ i
* 16 + 12, &edx
, 4);
2107 static Property max_x86_cpu_properties
[] = {
2108 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
2109 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
2110 DEFINE_PROP_END_OF_LIST()
2113 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
2115 DeviceClass
*dc
= DEVICE_CLASS(oc
);
2116 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2120 xcc
->model_description
=
2121 "Enables all features supported by the accelerator in the current host";
2123 dc
->props
= max_x86_cpu_properties
;
2126 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
);
2128 static void max_x86_cpu_initfn(Object
*obj
)
2130 X86CPU
*cpu
= X86_CPU(obj
);
2131 CPUX86State
*env
= &cpu
->env
;
2132 KVMState
*s
= kvm_state
;
2134 /* We can't fill the features array here because we don't know yet if
2135 * "migratable" is true or false.
2137 cpu
->max_features
= true;
2139 if (accel_uses_host_cpuid()) {
2140 char vendor
[CPUID_VENDOR_SZ
+ 1] = { 0 };
2141 char model_id
[CPUID_MODEL_ID_SZ
+ 1] = { 0 };
2142 int family
, model
, stepping
;
2143 X86CPUDefinition host_cpudef
= { };
2144 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
2146 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
2147 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
2149 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
2151 cpu_x86_fill_model_id(model_id
);
2153 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", &error_abort
);
2154 object_property_set_int(OBJECT(cpu
), family
, "family", &error_abort
);
2155 object_property_set_int(OBJECT(cpu
), model
, "model", &error_abort
);
2156 object_property_set_int(OBJECT(cpu
), stepping
, "stepping",
2158 object_property_set_str(OBJECT(cpu
), model_id
, "model-id",
2161 if (kvm_enabled()) {
2162 env
->cpuid_min_level
=
2163 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
2164 env
->cpuid_min_xlevel
=
2165 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
2166 env
->cpuid_min_xlevel2
=
2167 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
2169 env
->cpuid_min_level
=
2170 hvf_get_supported_cpuid(0x0, 0, R_EAX
);
2171 env
->cpuid_min_xlevel
=
2172 hvf_get_supported_cpuid(0x80000000, 0, R_EAX
);
2173 env
->cpuid_min_xlevel2
=
2174 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX
);
2177 if (lmce_supported()) {
2178 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
2181 object_property_set_str(OBJECT(cpu
), CPUID_VENDOR_AMD
,
2182 "vendor", &error_abort
);
2183 object_property_set_int(OBJECT(cpu
), 6, "family", &error_abort
);
2184 object_property_set_int(OBJECT(cpu
), 6, "model", &error_abort
);
2185 object_property_set_int(OBJECT(cpu
), 3, "stepping", &error_abort
);
2186 object_property_set_str(OBJECT(cpu
),
2187 "QEMU TCG CPU version " QEMU_HW_VERSION
,
2188 "model-id", &error_abort
);
2191 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
2194 static const TypeInfo max_x86_cpu_type_info
= {
2195 .name
= X86_CPU_TYPE_NAME("max"),
2196 .parent
= TYPE_X86_CPU
,
2197 .instance_init
= max_x86_cpu_initfn
,
2198 .class_init
= max_x86_cpu_class_init
,
2201 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
2202 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
2204 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2206 xcc
->host_cpuid_required
= true;
2209 if (kvm_enabled()) {
2210 xcc
->model_description
=
2211 "KVM processor with all supported host features ";
2212 } else if (hvf_enabled()) {
2213 xcc
->model_description
=
2214 "HVF processor with all supported host features ";
2218 static const TypeInfo host_x86_cpu_type_info
= {
2219 .name
= X86_CPU_TYPE_NAME("host"),
2220 .parent
= X86_CPU_TYPE_NAME("max"),
2221 .class_init
= host_x86_cpu_class_init
,
2226 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
2228 FeatureWordInfo
*f
= &feature_word_info
[w
];
2231 for (i
= 0; i
< 32; ++i
) {
2232 if ((1UL << i
) & mask
) {
2233 const char *reg
= get_register_name_32(f
->cpuid_reg
);
2235 warn_report("%s doesn't support requested feature: "
2236 "CPUID.%02XH:%s%s%s [bit %d]",
2237 accel_uses_host_cpuid() ? "host" : "TCG",
2239 f
->feat_names
[i
] ? "." : "",
2240 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
2245 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
2246 const char *name
, void *opaque
,
2249 X86CPU
*cpu
= X86_CPU(obj
);
2250 CPUX86State
*env
= &cpu
->env
;
2253 value
= (env
->cpuid_version
>> 8) & 0xf;
2255 value
+= (env
->cpuid_version
>> 20) & 0xff;
2257 visit_type_int(v
, name
, &value
, errp
);
2260 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
2261 const char *name
, void *opaque
,
2264 X86CPU
*cpu
= X86_CPU(obj
);
2265 CPUX86State
*env
= &cpu
->env
;
2266 const int64_t min
= 0;
2267 const int64_t max
= 0xff + 0xf;
2268 Error
*local_err
= NULL
;
2271 visit_type_int(v
, name
, &value
, &local_err
);
2273 error_propagate(errp
, local_err
);
2276 if (value
< min
|| value
> max
) {
2277 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2278 name
? name
: "null", value
, min
, max
);
2282 env
->cpuid_version
&= ~0xff00f00;
2284 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
2286 env
->cpuid_version
|= value
<< 8;
2290 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
2291 const char *name
, void *opaque
,
2294 X86CPU
*cpu
= X86_CPU(obj
);
2295 CPUX86State
*env
= &cpu
->env
;
2298 value
= (env
->cpuid_version
>> 4) & 0xf;
2299 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
2300 visit_type_int(v
, name
, &value
, errp
);
2303 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
2304 const char *name
, void *opaque
,
2307 X86CPU
*cpu
= X86_CPU(obj
);
2308 CPUX86State
*env
= &cpu
->env
;
2309 const int64_t min
= 0;
2310 const int64_t max
= 0xff;
2311 Error
*local_err
= NULL
;
2314 visit_type_int(v
, name
, &value
, &local_err
);
2316 error_propagate(errp
, local_err
);
2319 if (value
< min
|| value
> max
) {
2320 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2321 name
? name
: "null", value
, min
, max
);
2325 env
->cpuid_version
&= ~0xf00f0;
2326 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
2329 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
2330 const char *name
, void *opaque
,
2333 X86CPU
*cpu
= X86_CPU(obj
);
2334 CPUX86State
*env
= &cpu
->env
;
2337 value
= env
->cpuid_version
& 0xf;
2338 visit_type_int(v
, name
, &value
, errp
);
2341 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
2342 const char *name
, void *opaque
,
2345 X86CPU
*cpu
= X86_CPU(obj
);
2346 CPUX86State
*env
= &cpu
->env
;
2347 const int64_t min
= 0;
2348 const int64_t max
= 0xf;
2349 Error
*local_err
= NULL
;
2352 visit_type_int(v
, name
, &value
, &local_err
);
2354 error_propagate(errp
, local_err
);
2357 if (value
< min
|| value
> max
) {
2358 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2359 name
? name
: "null", value
, min
, max
);
2363 env
->cpuid_version
&= ~0xf;
2364 env
->cpuid_version
|= value
& 0xf;
2367 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
2369 X86CPU
*cpu
= X86_CPU(obj
);
2370 CPUX86State
*env
= &cpu
->env
;
2373 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
2374 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
2375 env
->cpuid_vendor3
);
2379 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
2382 X86CPU
*cpu
= X86_CPU(obj
);
2383 CPUX86State
*env
= &cpu
->env
;
2386 if (strlen(value
) != CPUID_VENDOR_SZ
) {
2387 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
2391 env
->cpuid_vendor1
= 0;
2392 env
->cpuid_vendor2
= 0;
2393 env
->cpuid_vendor3
= 0;
2394 for (i
= 0; i
< 4; i
++) {
2395 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
2396 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
2397 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
2401 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
2403 X86CPU
*cpu
= X86_CPU(obj
);
2404 CPUX86State
*env
= &cpu
->env
;
2408 value
= g_malloc(48 + 1);
2409 for (i
= 0; i
< 48; i
++) {
2410 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
2416 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
2419 X86CPU
*cpu
= X86_CPU(obj
);
2420 CPUX86State
*env
= &cpu
->env
;
2423 if (model_id
== NULL
) {
2426 len
= strlen(model_id
);
2427 memset(env
->cpuid_model
, 0, 48);
2428 for (i
= 0; i
< 48; i
++) {
2432 c
= (uint8_t)model_id
[i
];
2434 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
2438 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
2439 void *opaque
, Error
**errp
)
2441 X86CPU
*cpu
= X86_CPU(obj
);
2444 value
= cpu
->env
.tsc_khz
* 1000;
2445 visit_type_int(v
, name
, &value
, errp
);
2448 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
2449 void *opaque
, Error
**errp
)
2451 X86CPU
*cpu
= X86_CPU(obj
);
2452 const int64_t min
= 0;
2453 const int64_t max
= INT64_MAX
;
2454 Error
*local_err
= NULL
;
2457 visit_type_int(v
, name
, &value
, &local_err
);
2459 error_propagate(errp
, local_err
);
2462 if (value
< min
|| value
> max
) {
2463 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2464 name
? name
: "null", value
, min
, max
);
2468 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
2471 /* Generic getter for "feature-words" and "filtered-features" properties */
2472 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
2473 const char *name
, void *opaque
,
2476 uint32_t *array
= (uint32_t *)opaque
;
2478 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
2479 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
2480 X86CPUFeatureWordInfoList
*list
= NULL
;
2482 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2483 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2484 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
2485 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
2486 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
2487 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
2488 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
2489 qwi
->features
= array
[w
];
2491 /* List will be in reverse order, but order shouldn't matter */
2492 list_entries
[w
].next
= list
;
2493 list_entries
[w
].value
= &word_infos
[w
];
2494 list
= &list_entries
[w
];
2497 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
2500 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2501 void *opaque
, Error
**errp
)
2503 X86CPU
*cpu
= X86_CPU(obj
);
2504 int64_t value
= cpu
->hyperv_spinlock_attempts
;
2506 visit_type_int(v
, name
, &value
, errp
);
2509 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2510 void *opaque
, Error
**errp
)
2512 const int64_t min
= 0xFFF;
2513 const int64_t max
= UINT_MAX
;
2514 X86CPU
*cpu
= X86_CPU(obj
);
2518 visit_type_int(v
, name
, &value
, &err
);
2520 error_propagate(errp
, err
);
2524 if (value
< min
|| value
> max
) {
2525 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
2526 " (minimum: %" PRId64
", maximum: %" PRId64
")",
2527 object_get_typename(obj
), name
? name
: "null",
2531 cpu
->hyperv_spinlock_attempts
= value
;
2534 static const PropertyInfo qdev_prop_spinlocks
= {
2536 .get
= x86_get_hv_spinlocks
,
2537 .set
= x86_set_hv_spinlocks
,
2540 /* Convert all '_' in a feature string option name to '-', to make feature
2541 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2543 static inline void feat2prop(char *s
)
2545 while ((s
= strchr(s
, '_'))) {
2550 /* Return the feature property name for a feature flag bit */
2551 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
2553 /* XSAVE components are automatically enabled by other features,
2554 * so return the original feature name instead
2556 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
2557 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
2559 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
2560 x86_ext_save_areas
[comp
].bits
) {
2561 w
= x86_ext_save_areas
[comp
].feature
;
2562 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
2567 assert(w
< FEATURE_WORDS
);
2568 return feature_word_info
[w
].feat_names
[bitnr
];
2571 /* Compatibily hack to maintain legacy +-feat semantic,
2572 * where +-feat overwrites any feature set by
2573 * feat=on|feat even if the later is parsed after +-feat
2574 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2576 static GList
*plus_features
, *minus_features
;
2578 static gint
compare_string(gconstpointer a
, gconstpointer b
)
2580 return g_strcmp0(a
, b
);
2583 /* Parse "+feature,-feature,feature=foo" CPU feature string
2585 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
2588 char *featurestr
; /* Single 'key=value" string being parsed */
2589 static bool cpu_globals_initialized
;
2590 bool ambiguous
= false;
2592 if (cpu_globals_initialized
) {
2595 cpu_globals_initialized
= true;
2601 for (featurestr
= strtok(features
, ",");
2603 featurestr
= strtok(NULL
, ",")) {
2605 const char *val
= NULL
;
2608 GlobalProperty
*prop
;
2610 /* Compatibility syntax: */
2611 if (featurestr
[0] == '+') {
2612 plus_features
= g_list_append(plus_features
,
2613 g_strdup(featurestr
+ 1));
2615 } else if (featurestr
[0] == '-') {
2616 minus_features
= g_list_append(minus_features
,
2617 g_strdup(featurestr
+ 1));
2621 eq
= strchr(featurestr
, '=');
2629 feat2prop(featurestr
);
2632 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
2633 warn_report("Ambiguous CPU model string. "
2634 "Don't mix both \"+%s\" and \"%s=%s\"",
2638 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
2639 warn_report("Ambiguous CPU model string. "
2640 "Don't mix both \"-%s\" and \"%s=%s\"",
2646 if (!strcmp(name
, "tsc-freq")) {
2650 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
2651 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
2652 error_setg(errp
, "bad numerical value %s", val
);
2655 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
2657 name
= "tsc-frequency";
2660 prop
= g_new0(typeof(*prop
), 1);
2661 prop
->driver
= typename
;
2662 prop
->property
= g_strdup(name
);
2663 prop
->value
= g_strdup(val
);
2664 prop
->errp
= &error_fatal
;
2665 qdev_prop_register_global(prop
);
2669 warn_report("Compatibility of ambiguous CPU model "
2670 "strings won't be kept on future QEMU versions");
2674 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
);
2675 static int x86_cpu_filter_features(X86CPU
*cpu
);
2677 /* Check for missing features that may prevent the CPU class from
2678 * running using the current machine and accelerator.
2680 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
2681 strList
**missing_feats
)
2686 strList
**next
= missing_feats
;
2688 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
2689 strList
*new = g_new0(strList
, 1);
2690 new->value
= g_strdup("kvm");
2691 *missing_feats
= new;
2695 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
2697 x86_cpu_expand_features(xc
, &err
);
2699 /* Errors at x86_cpu_expand_features should never happen,
2700 * but in case it does, just report the model as not
2701 * runnable at all using the "type" property.
2703 strList
*new = g_new0(strList
, 1);
2704 new->value
= g_strdup("type");
2709 x86_cpu_filter_features(xc
);
2711 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2712 uint32_t filtered
= xc
->filtered_features
[w
];
2714 for (i
= 0; i
< 32; i
++) {
2715 if (filtered
& (1UL << i
)) {
2716 strList
*new = g_new0(strList
, 1);
2717 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
2724 object_unref(OBJECT(xc
));
2727 /* Print all cpuid feature names in featureset
2729 static void listflags(FILE *f
, fprintf_function print
, const char **featureset
)
2734 for (bit
= 0; bit
< 32; bit
++) {
2735 if (featureset
[bit
]) {
2736 print(f
, "%s%s", first
? "" : " ", featureset
[bit
]);
2742 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
2743 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2745 ObjectClass
*class_a
= (ObjectClass
*)a
;
2746 ObjectClass
*class_b
= (ObjectClass
*)b
;
2747 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
2748 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
2749 const char *name_a
, *name_b
;
2751 if (cc_a
->ordering
!= cc_b
->ordering
) {
2752 return cc_a
->ordering
- cc_b
->ordering
;
2754 name_a
= object_class_get_name(class_a
);
2755 name_b
= object_class_get_name(class_b
);
2756 return strcmp(name_a
, name_b
);
2760 static GSList
*get_sorted_cpu_model_list(void)
2762 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
2763 list
= g_slist_sort(list
, x86_cpu_list_compare
);
2767 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
2769 ObjectClass
*oc
= data
;
2770 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2771 CPUListState
*s
= user_data
;
2772 char *name
= x86_cpu_class_get_model_name(cc
);
2773 const char *desc
= cc
->model_description
;
2774 if (!desc
&& cc
->cpu_def
) {
2775 desc
= cc
->cpu_def
->model_id
;
2778 (*s
->cpu_fprintf
)(s
->file
, "x86 %16s %-48s\n",
2783 /* list available CPU models and flags */
2784 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2789 .cpu_fprintf
= cpu_fprintf
,
2793 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2794 list
= get_sorted_cpu_model_list();
2795 g_slist_foreach(list
, x86_cpu_list_entry
, &s
);
2798 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
2799 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
2800 FeatureWordInfo
*fw
= &feature_word_info
[i
];
2802 (*cpu_fprintf
)(f
, " ");
2803 listflags(f
, cpu_fprintf
, fw
->feat_names
);
2804 (*cpu_fprintf
)(f
, "\n");
2808 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
2810 ObjectClass
*oc
= data
;
2811 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2812 CpuDefinitionInfoList
**cpu_list
= user_data
;
2813 CpuDefinitionInfoList
*entry
;
2814 CpuDefinitionInfo
*info
;
2816 info
= g_malloc0(sizeof(*info
));
2817 info
->name
= x86_cpu_class_get_model_name(cc
);
2818 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
2819 info
->has_unavailable_features
= true;
2820 info
->q_typename
= g_strdup(object_class_get_name(oc
));
2821 info
->migration_safe
= cc
->migration_safe
;
2822 info
->has_migration_safe
= true;
2823 info
->q_static
= cc
->static_model
;
2825 entry
= g_malloc0(sizeof(*entry
));
2826 entry
->value
= info
;
2827 entry
->next
= *cpu_list
;
2831 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2833 CpuDefinitionInfoList
*cpu_list
= NULL
;
2834 GSList
*list
= get_sorted_cpu_model_list();
2835 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
2840 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2841 bool migratable_only
)
2843 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2846 if (kvm_enabled()) {
2847 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
2850 } else if (hvf_enabled()) {
2851 r
= hvf_get_supported_cpuid(wi
->cpuid_eax
,
2854 } else if (tcg_enabled()) {
2855 r
= wi
->tcg_features
;
2859 if (migratable_only
) {
2860 r
&= x86_cpu_get_migratable_flags(w
);
2865 static void x86_cpu_report_filtered_features(X86CPU
*cpu
)
2869 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2870 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
2874 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
2877 for (pv
= props
; pv
->prop
; pv
++) {
2881 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
2886 /* Load data from X86CPUDefinition into a X86CPU object
2888 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
2890 CPUX86State
*env
= &cpu
->env
;
2892 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
2895 /*NOTE: any property set by this function should be returned by
2896 * x86_cpu_static_props(), so static expansion of
2897 * query-cpu-model-expansion is always complete.
2900 /* CPU models only set _minimum_ values for level/xlevel: */
2901 object_property_set_uint(OBJECT(cpu
), def
->level
, "min-level", errp
);
2902 object_property_set_uint(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
2904 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
2905 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
2906 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
2907 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
2908 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2909 env
->features
[w
] = def
->features
[w
];
2912 /* Special cases not set in the X86CPUDefinition structs: */
2913 /* TODO: in-kernel irqchip for hvf */
2914 if (kvm_enabled()) {
2915 if (!kvm_irqchip_in_kernel()) {
2916 x86_cpu_change_kvm_default("x2apic", "off");
2919 x86_cpu_apply_props(cpu
, kvm_default_props
);
2920 } else if (tcg_enabled()) {
2921 x86_cpu_apply_props(cpu
, tcg_default_props
);
2924 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2926 /* sysenter isn't supported in compatibility mode on AMD,
2927 * syscall isn't supported in compatibility mode on Intel.
2928 * Normally we advertise the actual CPU vendor, but you can
2929 * override this using the 'vendor' property if you want to use
2930 * KVM's sysenter/syscall emulation in compatibility mode and
2931 * when doing cross vendor migration
2933 vendor
= def
->vendor
;
2934 if (accel_uses_host_cpuid()) {
2935 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2936 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2937 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2938 vendor
= host_vendor
;
2941 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2945 /* Return a QDict containing keys for all properties that can be included
2946 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2947 * must be included in the dictionary.
2949 static QDict
*x86_cpu_static_props(void)
2953 static const char *props
[] = {
2971 for (i
= 0; props
[i
]; i
++) {
2972 qdict_put_null(d
, props
[i
]);
2975 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2976 FeatureWordInfo
*fi
= &feature_word_info
[w
];
2978 for (bit
= 0; bit
< 32; bit
++) {
2979 if (!fi
->feat_names
[bit
]) {
2982 qdict_put_null(d
, fi
->feat_names
[bit
]);
2989 /* Add an entry to @props dict, with the value for property. */
2990 static void x86_cpu_expand_prop(X86CPU
*cpu
, QDict
*props
, const char *prop
)
2992 QObject
*value
= object_property_get_qobject(OBJECT(cpu
), prop
,
2995 qdict_put_obj(props
, prop
, value
);
2998 /* Convert CPU model data from X86CPU object to a property dictionary
2999 * that can recreate exactly the same CPU model.
3001 static void x86_cpu_to_dict(X86CPU
*cpu
, QDict
*props
)
3003 QDict
*sprops
= x86_cpu_static_props();
3004 const QDictEntry
*e
;
3006 for (e
= qdict_first(sprops
); e
; e
= qdict_next(sprops
, e
)) {
3007 const char *prop
= qdict_entry_key(e
);
3008 x86_cpu_expand_prop(cpu
, props
, prop
);
3012 /* Convert CPU model data from X86CPU object to a property dictionary
3013 * that can recreate exactly the same CPU model, including every
3014 * writeable QOM property.
3016 static void x86_cpu_to_dict_full(X86CPU
*cpu
, QDict
*props
)
3018 ObjectPropertyIterator iter
;
3019 ObjectProperty
*prop
;
3021 object_property_iter_init(&iter
, OBJECT(cpu
));
3022 while ((prop
= object_property_iter_next(&iter
))) {
3023 /* skip read-only or write-only properties */
3024 if (!prop
->get
|| !prop
->set
) {
3028 /* "hotplugged" is the only property that is configurable
3029 * on the command-line but will be set differently on CPUs
3030 * created using "-cpu ... -smp ..." and by CPUs created
3031 * on the fly by x86_cpu_from_model() for querying. Skip it.
3033 if (!strcmp(prop
->name
, "hotplugged")) {
3036 x86_cpu_expand_prop(cpu
, props
, prop
->name
);
3040 static void object_apply_props(Object
*obj
, QDict
*props
, Error
**errp
)
3042 const QDictEntry
*prop
;
3045 for (prop
= qdict_first(props
); prop
; prop
= qdict_next(props
, prop
)) {
3046 object_property_set_qobject(obj
, qdict_entry_value(prop
),
3047 qdict_entry_key(prop
), &err
);
3053 error_propagate(errp
, err
);
3056 /* Create X86CPU object according to model+props specification */
3057 static X86CPU
*x86_cpu_from_model(const char *model
, QDict
*props
, Error
**errp
)
3063 xcc
= X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU
, model
));
3065 error_setg(&err
, "CPU model '%s' not found", model
);
3069 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
3071 object_apply_props(OBJECT(xc
), props
, &err
);
3077 x86_cpu_expand_features(xc
, &err
);
3084 error_propagate(errp
, err
);
3085 object_unref(OBJECT(xc
));
3091 CpuModelExpansionInfo
*
3092 arch_query_cpu_model_expansion(CpuModelExpansionType type
,
3093 CpuModelInfo
*model
,
3098 CpuModelExpansionInfo
*ret
= g_new0(CpuModelExpansionInfo
, 1);
3099 QDict
*props
= NULL
;
3100 const char *base_name
;
3102 xc
= x86_cpu_from_model(model
->name
,
3104 qobject_to_qdict(model
->props
) :
3110 props
= qdict_new();
3113 case CPU_MODEL_EXPANSION_TYPE_STATIC
:
3114 /* Static expansion will be based on "base" only */
3116 x86_cpu_to_dict(xc
, props
);
3118 case CPU_MODEL_EXPANSION_TYPE_FULL
:
3119 /* As we don't return every single property, full expansion needs
3120 * to keep the original model name+props, and add extra
3121 * properties on top of that.
3123 base_name
= model
->name
;
3124 x86_cpu_to_dict_full(xc
, props
);
3127 error_setg(&err
, "Unsupportted expansion type");
3132 props
= qdict_new();
3134 x86_cpu_to_dict(xc
, props
);
3136 ret
->model
= g_new0(CpuModelInfo
, 1);
3137 ret
->model
->name
= g_strdup(base_name
);
3138 ret
->model
->props
= QOBJECT(props
);
3139 ret
->model
->has_props
= true;
3142 object_unref(OBJECT(xc
));
3144 error_propagate(errp
, err
);
3145 qapi_free_CpuModelExpansionInfo(ret
);
3151 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
3153 #ifdef TARGET_X86_64
3154 return g_strdup("i386:x86-64");
3156 return g_strdup("i386");
3160 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
3162 X86CPUDefinition
*cpudef
= data
;
3163 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
3165 xcc
->cpu_def
= cpudef
;
3166 xcc
->migration_safe
= true;
3169 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
3171 char *typename
= x86_cpu_type_name(def
->name
);
3174 .parent
= TYPE_X86_CPU
,
3175 .class_init
= x86_cpu_cpudef_class_init
,
3179 /* AMD aliases are handled at runtime based on CPUID vendor, so
3180 * they shouldn't be set on the CPU model table.
3182 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
3183 /* catch mistakes instead of silently truncating model_id when too long */
3184 assert(def
->model_id
&& strlen(def
->model_id
) <= 48);
3191 #if !defined(CONFIG_USER_ONLY)
3193 void cpu_clear_apic_feature(CPUX86State
*env
)
3195 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
3198 #endif /* !CONFIG_USER_ONLY */
3200 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
3201 uint32_t *eax
, uint32_t *ebx
,
3202 uint32_t *ecx
, uint32_t *edx
)
3204 X86CPU
*cpu
= x86_env_get_cpu(env
);
3205 CPUState
*cs
= CPU(cpu
);
3206 uint32_t pkg_offset
;
3208 uint32_t signature
[3];
3210 /* Calculate & apply limits for different index ranges */
3211 if (index
>= 0xC0000000) {
3212 limit
= env
->cpuid_xlevel2
;
3213 } else if (index
>= 0x80000000) {
3214 limit
= env
->cpuid_xlevel
;
3215 } else if (index
>= 0x40000000) {
3218 limit
= env
->cpuid_level
;
3221 if (index
> limit
) {
3222 /* Intel documentation states that invalid EAX input will
3223 * return the same information as EAX=cpuid_level
3224 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
3226 index
= env
->cpuid_level
;
3231 *eax
= env
->cpuid_level
;
3232 *ebx
= env
->cpuid_vendor1
;
3233 *edx
= env
->cpuid_vendor2
;
3234 *ecx
= env
->cpuid_vendor3
;
3237 *eax
= env
->cpuid_version
;
3238 *ebx
= (cpu
->apic_id
<< 24) |
3239 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
3240 *ecx
= env
->features
[FEAT_1_ECX
];
3241 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
3242 *ecx
|= CPUID_EXT_OSXSAVE
;
3244 *edx
= env
->features
[FEAT_1_EDX
];
3245 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3246 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
3251 /* cache info: needed for Pentium Pro compatibility */
3252 if (cpu
->cache_info_passthrough
) {
3253 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3256 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
3258 if (!cpu
->enable_l3_cache
) {
3261 *ecx
= L3_N_DESCRIPTOR
;
3263 *edx
= (L1D_DESCRIPTOR
<< 16) | \
3264 (L1I_DESCRIPTOR
<< 8) | \
3268 /* cache info: needed for Core compatibility */
3269 if (cpu
->cache_info_passthrough
) {
3270 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
3271 *eax
&= ~0xFC000000;
3275 case 0: /* L1 dcache info */
3276 *eax
|= CPUID_4_TYPE_DCACHE
| \
3277 CPUID_4_LEVEL(1) | \
3278 CPUID_4_SELF_INIT_LEVEL
;
3279 *ebx
= (L1D_LINE_SIZE
- 1) | \
3280 ((L1D_PARTITIONS
- 1) << 12) | \
3281 ((L1D_ASSOCIATIVITY
- 1) << 22);
3282 *ecx
= L1D_SETS
- 1;
3283 *edx
= CPUID_4_NO_INVD_SHARING
;
3285 case 1: /* L1 icache info */
3286 *eax
|= CPUID_4_TYPE_ICACHE
| \
3287 CPUID_4_LEVEL(1) | \
3288 CPUID_4_SELF_INIT_LEVEL
;
3289 *ebx
= (L1I_LINE_SIZE
- 1) | \
3290 ((L1I_PARTITIONS
- 1) << 12) | \
3291 ((L1I_ASSOCIATIVITY
- 1) << 22);
3292 *ecx
= L1I_SETS
- 1;
3293 *edx
= CPUID_4_NO_INVD_SHARING
;
3295 case 2: /* L2 cache info */
3296 *eax
|= CPUID_4_TYPE_UNIFIED
| \
3297 CPUID_4_LEVEL(2) | \
3298 CPUID_4_SELF_INIT_LEVEL
;
3299 if (cs
->nr_threads
> 1) {
3300 *eax
|= (cs
->nr_threads
- 1) << 14;
3302 *ebx
= (L2_LINE_SIZE
- 1) | \
3303 ((L2_PARTITIONS
- 1) << 12) | \
3304 ((L2_ASSOCIATIVITY
- 1) << 22);
3306 *edx
= CPUID_4_NO_INVD_SHARING
;
3308 case 3: /* L3 cache info */
3309 if (!cpu
->enable_l3_cache
) {
3316 *eax
|= CPUID_4_TYPE_UNIFIED
| \
3317 CPUID_4_LEVEL(3) | \
3318 CPUID_4_SELF_INIT_LEVEL
;
3319 pkg_offset
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
3320 *eax
|= ((1 << pkg_offset
) - 1) << 14;
3321 *ebx
= (L3_N_LINE_SIZE
- 1) | \
3322 ((L3_N_PARTITIONS
- 1) << 12) | \
3323 ((L3_N_ASSOCIATIVITY
- 1) << 22);
3324 *ecx
= L3_N_SETS
- 1;
3325 *edx
= CPUID_4_INCLUSIVE
| CPUID_4_COMPLEX_IDX
;
3327 default: /* end of info */
3336 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
3337 if ((*eax
& 31) && cs
->nr_cores
> 1) {
3338 *eax
|= (cs
->nr_cores
- 1) << 26;
3342 /* mwait info: needed for Core compatibility */
3343 *eax
= 0; /* Smallest monitor-line size in bytes */
3344 *ebx
= 0; /* Largest monitor-line size in bytes */
3345 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
3349 /* Thermal and Power Leaf */
3350 *eax
= env
->features
[FEAT_6_EAX
];
3356 /* Structured Extended Feature Flags Enumeration Leaf */
3358 *eax
= 0; /* Maximum ECX value for sub-leaves */
3359 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
3360 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
3361 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
3362 *ecx
|= CPUID_7_0_ECX_OSPKE
;
3364 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
3373 /* Direct Cache Access Information Leaf */
3374 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
3380 /* Architectural Performance Monitoring Leaf */
3381 if (kvm_enabled() && cpu
->enable_pmu
) {
3382 KVMState
*s
= cs
->kvm_state
;
3384 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
3385 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
3386 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
3387 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
3388 } else if (hvf_enabled() && cpu
->enable_pmu
) {
3389 *eax
= hvf_get_supported_cpuid(0xA, count
, R_EAX
);
3390 *ebx
= hvf_get_supported_cpuid(0xA, count
, R_EBX
);
3391 *ecx
= hvf_get_supported_cpuid(0xA, count
, R_ECX
);
3392 *edx
= hvf_get_supported_cpuid(0xA, count
, R_EDX
);
3401 /* Extended Topology Enumeration Leaf */
3402 if (!cpu
->enable_cpuid_0xb
) {
3403 *eax
= *ebx
= *ecx
= *edx
= 0;
3407 *ecx
= count
& 0xff;
3408 *edx
= cpu
->apic_id
;
3412 *eax
= apicid_core_offset(cs
->nr_cores
, cs
->nr_threads
);
3413 *ebx
= cs
->nr_threads
;
3414 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
3417 *eax
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
3418 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
3419 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
3424 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
3427 assert(!(*eax
& ~0x1f));
3428 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
3431 /* Processor Extended State */
3436 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
3441 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
3442 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
3443 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
3445 } else if (count
== 1) {
3446 *eax
= env
->features
[FEAT_XSAVE
];
3447 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
3448 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
3449 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
3458 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3459 * set here, but we restrict to TCG none the less.
3461 if (tcg_enabled() && cpu
->expose_tcg
) {
3462 memcpy(signature
, "TCGTCGTCGTCG", 12);
3464 *ebx
= signature
[0];
3465 *ecx
= signature
[1];
3466 *edx
= signature
[2];
3481 *eax
= env
->cpuid_xlevel
;
3482 *ebx
= env
->cpuid_vendor1
;
3483 *edx
= env
->cpuid_vendor2
;
3484 *ecx
= env
->cpuid_vendor3
;
3487 *eax
= env
->cpuid_version
;
3489 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
3490 *edx
= env
->features
[FEAT_8000_0001_EDX
];
3492 /* The Linux kernel checks for the CMPLegacy bit and
3493 * discards multiple thread information if it is set.
3494 * So don't set it here for Intel to make Linux guests happy.
3496 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3497 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
3498 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
3499 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
3500 *ecx
|= 1 << 1; /* CmpLegacy bit */
3507 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
3508 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
3509 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
3510 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
3513 /* cache info (L1 cache) */
3514 if (cpu
->cache_info_passthrough
) {
3515 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3518 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
3519 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
3520 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
3521 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
3522 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
3523 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
3524 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
3525 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
3528 /* cache info (L2 cache) */
3529 if (cpu
->cache_info_passthrough
) {
3530 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3533 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
3534 (L2_DTLB_2M_ENTRIES
<< 16) | \
3535 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
3536 (L2_ITLB_2M_ENTRIES
);
3537 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
3538 (L2_DTLB_4K_ENTRIES
<< 16) | \
3539 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
3540 (L2_ITLB_4K_ENTRIES
);
3541 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
3542 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
3543 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
3544 if (!cpu
->enable_l3_cache
) {
3545 *edx
= ((L3_SIZE_KB
/ 512) << 18) | \
3546 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
3547 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
3549 *edx
= ((L3_N_SIZE_KB_AMD
/ 512) << 18) | \
3550 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY
) << 12) | \
3551 (L3_N_LINES_PER_TAG
<< 8) | (L3_N_LINE_SIZE
);
3558 *edx
= env
->features
[FEAT_8000_0007_EDX
];
3561 /* virtual & phys address size in low 2 bytes. */
3562 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
3563 /* 64 bit processor */
3564 *eax
= cpu
->phys_bits
; /* configurable physical bits */
3565 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
3566 *eax
|= 0x00003900; /* 57 bits virtual */
3568 *eax
|= 0x00003000; /* 48 bits virtual */
3571 *eax
= cpu
->phys_bits
;
3573 *ebx
= env
->features
[FEAT_8000_0008_EBX
];
3576 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3577 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
3581 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
3582 *eax
= 0x00000001; /* SVM Revision */
3583 *ebx
= 0x00000010; /* nr of ASIDs */
3585 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
3594 *eax
= env
->cpuid_xlevel2
;
3600 /* Support for VIA CPU's CPUID instruction */
3601 *eax
= env
->cpuid_version
;
3604 *edx
= env
->features
[FEAT_C000_0001_EDX
];
3609 /* Reserved for the future, and now filled with zero */
3616 /* reserved values: zero */
3625 /* CPUClass::reset() */
3626 static void x86_cpu_reset(CPUState
*s
)
3628 X86CPU
*cpu
= X86_CPU(s
);
3629 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
3630 CPUX86State
*env
= &cpu
->env
;
3635 xcc
->parent_reset(s
);
3637 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
3639 env
->old_exception
= -1;
3641 /* init to reset state */
3643 env
->hflags2
|= HF2_GIF_MASK
;
3645 cpu_x86_update_cr0(env
, 0x60000010);
3646 env
->a20_mask
= ~0x0;
3647 env
->smbase
= 0x30000;
3648 env
->msr_smi_count
= 0;
3650 env
->idt
.limit
= 0xffff;
3651 env
->gdt
.limit
= 0xffff;
3652 env
->ldt
.limit
= 0xffff;
3653 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
3654 env
->tr
.limit
= 0xffff;
3655 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
3657 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
3658 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
3659 DESC_R_MASK
| DESC_A_MASK
);
3660 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
3661 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3663 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
3664 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3666 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
3667 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3669 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
3670 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3672 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
3673 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3677 env
->regs
[R_EDX
] = env
->cpuid_version
;
3682 for (i
= 0; i
< 8; i
++) {
3685 cpu_set_fpuc(env
, 0x37f);
3687 env
->mxcsr
= 0x1f80;
3688 /* All units are in INIT state. */
3691 env
->pat
= 0x0007040600070406ULL
;
3692 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
3694 memset(env
->dr
, 0, sizeof(env
->dr
));
3695 env
->dr
[6] = DR6_FIXED_1
;
3696 env
->dr
[7] = DR7_FIXED_1
;
3697 cpu_breakpoint_remove_all(s
, BP_CPU
);
3698 cpu_watchpoint_remove_all(s
, BP_CPU
);
3701 xcr0
= XSTATE_FP_MASK
;
3703 #ifdef CONFIG_USER_ONLY
3704 /* Enable all the features for user-mode. */
3705 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
3706 xcr0
|= XSTATE_SSE_MASK
;
3708 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3709 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3710 if (env
->features
[esa
->feature
] & esa
->bits
) {
3715 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
3716 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
3718 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
3719 cr4
|= CR4_FSGSBASE_MASK
;
3724 cpu_x86_update_cr4(env
, cr4
);
3727 * SDM 11.11.5 requires:
3728 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3729 * - IA32_MTRR_PHYSMASKn.V = 0
3730 * All other bits are undefined. For simplification, zero it all.
3732 env
->mtrr_deftype
= 0;
3733 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
3734 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
3736 env
->interrupt_injected
= -1;
3737 env
->exception_injected
= -1;
3738 env
->nmi_injected
= false;
3739 #if !defined(CONFIG_USER_ONLY)
3740 /* We hard-wire the BSP to the first CPU. */
3741 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
3743 s
->halted
= !cpu_is_bsp(cpu
);
3745 if (kvm_enabled()) {
3746 kvm_arch_reset_vcpu(cpu
);
3748 else if (hvf_enabled()) {
3754 #ifndef CONFIG_USER_ONLY
3755 bool cpu_is_bsp(X86CPU
*cpu
)
3757 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
3760 /* TODO: remove me, when reset over QOM tree is implemented */
3761 static void x86_cpu_machine_reset_cb(void *opaque
)
3763 X86CPU
*cpu
= opaque
;
3764 cpu_reset(CPU(cpu
));
3768 static void mce_init(X86CPU
*cpu
)
3770 CPUX86State
*cenv
= &cpu
->env
;
3773 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
3774 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
3775 (CPUID_MCE
| CPUID_MCA
)) {
3776 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
3777 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
3778 cenv
->mcg_ctl
= ~(uint64_t)0;
3779 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
3780 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
3785 #ifndef CONFIG_USER_ONLY
3786 APICCommonClass
*apic_get_class(void)
3788 const char *apic_type
= "apic";
3790 /* TODO: in-kernel irqchip for hvf */
3791 if (kvm_apic_in_kernel()) {
3792 apic_type
= "kvm-apic";
3793 } else if (xen_enabled()) {
3794 apic_type
= "xen-apic";
3797 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
3800 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
3802 APICCommonState
*apic
;
3803 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
3805 cpu
->apic_state
= DEVICE(object_new(object_class_get_name(apic_class
)));
3807 object_property_add_child(OBJECT(cpu
), "lapic",
3808 OBJECT(cpu
->apic_state
), &error_abort
);
3809 object_unref(OBJECT(cpu
->apic_state
));
3811 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
3812 /* TODO: convert to link<> */
3813 apic
= APIC_COMMON(cpu
->apic_state
);
3815 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
3818 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3820 APICCommonState
*apic
;
3821 static bool apic_mmio_map_once
;
3823 if (cpu
->apic_state
== NULL
) {
3826 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
3829 /* Map APIC MMIO area */
3830 apic
= APIC_COMMON(cpu
->apic_state
);
3831 if (!apic_mmio_map_once
) {
3832 memory_region_add_subregion_overlap(get_system_memory(),
3834 MSR_IA32_APICBASE_BASE
,
3837 apic_mmio_map_once
= true;
3841 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
3843 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
3844 MemoryRegion
*smram
=
3845 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
3848 cpu
->smram
= g_new(MemoryRegion
, 1);
3849 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
3850 smram
, 0, 1ull << 32);
3851 memory_region_set_enabled(cpu
->smram
, true);
3852 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
3856 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3861 /* Note: Only safe for use on x86(-64) hosts */
3862 static uint32_t x86_host_phys_bits(void)
3865 uint32_t host_phys_bits
;
3867 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
3868 if (eax
>= 0x80000008) {
3869 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
3870 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3871 * at 23:16 that can specify a maximum physical address bits for
3872 * the guest that can override this value; but I've not seen
3873 * anything with that set.
3875 host_phys_bits
= eax
& 0xff;
3877 /* It's an odd 64 bit machine that doesn't have the leaf for
3878 * physical address bits; fall back to 36 that's most older
3881 host_phys_bits
= 36;
3884 return host_phys_bits
;
3887 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
3894 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3895 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
3897 CPUX86State
*env
= &cpu
->env
;
3898 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3899 uint32_t eax
= fi
->cpuid_eax
;
3900 uint32_t region
= eax
& 0xF0000000;
3902 if (!env
->features
[w
]) {
3908 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
3911 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
3914 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
3919 /* Calculate XSAVE components based on the configured CPU feature flags */
3920 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
3922 CPUX86State
*env
= &cpu
->env
;
3926 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
3931 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3932 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3933 if (env
->features
[esa
->feature
] & esa
->bits
) {
3934 mask
|= (1ULL << i
);
3938 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
3939 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
3942 /***** Steps involved on loading and filtering CPUID data
3944 * When initializing and realizing a CPU object, the steps
3945 * involved in setting up CPUID data are:
3947 * 1) Loading CPU model definition (X86CPUDefinition). This is
3948 * implemented by x86_cpu_load_def() and should be completely
3949 * transparent, as it is done automatically by instance_init.
3950 * No code should need to look at X86CPUDefinition structs
3951 * outside instance_init.
3953 * 2) CPU expansion. This is done by realize before CPUID
3954 * filtering, and will make sure host/accelerator data is
3955 * loaded for CPU models that depend on host capabilities
3956 * (e.g. "host"). Done by x86_cpu_expand_features().
3958 * 3) CPUID filtering. This initializes extra data related to
3959 * CPUID, and checks if the host supports all capabilities
3960 * required by the CPU. Runnability of a CPU model is
3961 * determined at this step. Done by x86_cpu_filter_features().
3963 * Some operations don't require all steps to be performed.
3966 * - CPU instance creation (instance_init) will run only CPU
3967 * model loading. CPU expansion can't run at instance_init-time
3968 * because host/accelerator data may be not available yet.
3969 * - CPU realization will perform both CPU model expansion and CPUID
3970 * filtering, and return an error in case one of them fails.
3971 * - query-cpu-definitions needs to run all 3 steps. It needs
3972 * to run CPUID filtering, as the 'unavailable-features'
3973 * field is set based on the filtering results.
3974 * - The query-cpu-model-expansion QMP command only needs to run
3975 * CPU model loading and CPU expansion. It should not filter
3976 * any CPUID data based on host capabilities.
3979 /* Expand CPU configuration data, based on configured features
3980 * and host/accelerator capabilities when appropriate.
3982 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
3984 CPUX86State
*env
= &cpu
->env
;
3987 Error
*local_err
= NULL
;
3989 /*TODO: Now cpu->max_features doesn't overwrite features
3990 * set using QOM properties, and we can convert
3991 * plus_features & minus_features to global properties
3992 * inside x86_cpu_parse_featurestr() too.
3994 if (cpu
->max_features
) {
3995 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3996 /* Override only features that weren't set explicitly
4000 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
4001 ~env
->user_features
[w
];
4005 for (l
= plus_features
; l
; l
= l
->next
) {
4006 const char *prop
= l
->data
;
4007 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
4013 for (l
= minus_features
; l
; l
= l
->next
) {
4014 const char *prop
= l
->data
;
4015 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
4021 if (!kvm_enabled() || !cpu
->expose_kvm
) {
4022 env
->features
[FEAT_KVM
] = 0;
4025 x86_cpu_enable_xsave_components(cpu
);
4027 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
4028 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
4029 if (cpu
->full_cpuid_auto_level
) {
4030 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
4031 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
4032 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
4033 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
4034 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
4035 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
4036 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
4037 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0008_EBX
);
4038 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
4039 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
4040 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
4041 /* SVM requires CPUID[0x8000000A] */
4042 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
4043 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
4047 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
4048 if (env
->cpuid_level
== UINT32_MAX
) {
4049 env
->cpuid_level
= env
->cpuid_min_level
;
4051 if (env
->cpuid_xlevel
== UINT32_MAX
) {
4052 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
4054 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
4055 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
4059 if (local_err
!= NULL
) {
4060 error_propagate(errp
, local_err
);
4065 * Finishes initialization of CPUID data, filters CPU feature
4066 * words based on host availability of each feature.
4068 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
4070 static int x86_cpu_filter_features(X86CPU
*cpu
)
4072 CPUX86State
*env
= &cpu
->env
;
4076 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4077 uint32_t host_feat
=
4078 x86_cpu_get_supported_feature_word(w
, false);
4079 uint32_t requested_features
= env
->features
[w
];
4080 env
->features
[w
] &= host_feat
;
4081 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
4082 if (cpu
->filtered_features
[w
]) {
4090 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
4091 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
4092 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
4093 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
4094 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
4095 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
4096 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
4098 CPUState
*cs
= CPU(dev
);
4099 X86CPU
*cpu
= X86_CPU(dev
);
4100 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
4101 CPUX86State
*env
= &cpu
->env
;
4102 Error
*local_err
= NULL
;
4103 static bool ht_warned
;
4105 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
4106 char *name
= x86_cpu_class_get_model_name(xcc
);
4107 error_setg(&local_err
, "CPU model '%s' requires KVM", name
);
4112 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
4113 error_setg(errp
, "apic-id property was not initialized properly");
4117 x86_cpu_expand_features(cpu
, &local_err
);
4122 if (x86_cpu_filter_features(cpu
) &&
4123 (cpu
->check_cpuid
|| cpu
->enforce_cpuid
)) {
4124 x86_cpu_report_filtered_features(cpu
);
4125 if (cpu
->enforce_cpuid
) {
4126 error_setg(&local_err
,
4127 accel_uses_host_cpuid() ?
4128 "Host doesn't support requested features" :
4129 "TCG doesn't support requested features");
4134 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
4137 if (IS_AMD_CPU(env
)) {
4138 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
4139 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
4140 & CPUID_EXT2_AMD_ALIASES
);
4143 /* For 64bit systems think about the number of physical bits to present.
4144 * ideally this should be the same as the host; anything other than matching
4145 * the host can cause incorrect guest behaviour.
4146 * QEMU used to pick the magic value of 40 bits that corresponds to
4147 * consumer AMD devices but nothing else.
4149 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
4150 if (accel_uses_host_cpuid()) {
4151 uint32_t host_phys_bits
= x86_host_phys_bits();
4154 if (cpu
->host_phys_bits
) {
4155 /* The user asked for us to use the host physical bits */
4156 cpu
->phys_bits
= host_phys_bits
;
4159 /* Print a warning if the user set it to a value that's not the
4162 if (cpu
->phys_bits
!= host_phys_bits
&& cpu
->phys_bits
!= 0 &&
4164 warn_report("Host physical bits (%u)"
4165 " does not match phys-bits property (%u)",
4166 host_phys_bits
, cpu
->phys_bits
);
4170 if (cpu
->phys_bits
&&
4171 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
4172 cpu
->phys_bits
< 32)) {
4173 error_setg(errp
, "phys-bits should be between 32 and %u "
4175 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
4179 if (cpu
->phys_bits
&& cpu
->phys_bits
!= TCG_PHYS_ADDR_BITS
) {
4180 error_setg(errp
, "TCG only supports phys-bits=%u",
4181 TCG_PHYS_ADDR_BITS
);
4185 /* 0 means it was not explicitly set by the user (or by machine
4186 * compat_props or by the host code above). In this case, the default
4187 * is the value used by TCG (40).
4189 if (cpu
->phys_bits
== 0) {
4190 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
4193 /* For 32 bit systems don't use the user set value, but keep
4194 * phys_bits consistent with what we tell the guest.
4196 if (cpu
->phys_bits
!= 0) {
4197 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
4201 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
4202 cpu
->phys_bits
= 36;
4204 cpu
->phys_bits
= 32;
4207 cpu_exec_realizefn(cs
, &local_err
);
4208 if (local_err
!= NULL
) {
4209 error_propagate(errp
, local_err
);
4213 #ifndef CONFIG_USER_ONLY
4214 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
4216 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
4217 x86_cpu_apic_create(cpu
, &local_err
);
4218 if (local_err
!= NULL
) {
4226 #ifndef CONFIG_USER_ONLY
4227 if (tcg_enabled()) {
4228 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
4229 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
4231 /* Outer container... */
4232 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
4233 memory_region_set_enabled(cpu
->cpu_as_root
, true);
4235 /* ... with two regions inside: normal system memory with low
4238 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
4239 get_system_memory(), 0, ~0ull);
4240 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
4241 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
4244 cpu_address_space_init(cs
, 0, "cpu-memory", cs
->memory
);
4245 cpu_address_space_init(cs
, 1, "cpu-smm", cpu
->cpu_as_root
);
4247 /* ... SMRAM with higher priority, linked from /machine/smram. */
4248 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
4249 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
4255 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
4256 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
4257 * based on inputs (sockets,cores,threads), it is still better to gives
4260 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
4261 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
4263 if (!IS_INTEL_CPU(env
) && cs
->nr_threads
> 1 && !ht_warned
) {
4264 error_report("AMD CPU doesn't support hyperthreading. Please configure"
4265 " -smp options properly.");
4269 x86_cpu_apic_realize(cpu
, &local_err
);
4270 if (local_err
!= NULL
) {
4275 xcc
->parent_realize(dev
, &local_err
);
4278 if (local_err
!= NULL
) {
4279 error_propagate(errp
, local_err
);
4284 static void x86_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
4286 X86CPU
*cpu
= X86_CPU(dev
);
4287 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
4288 Error
*local_err
= NULL
;
4290 #ifndef CONFIG_USER_ONLY
4291 cpu_remove_sync(CPU(dev
));
4292 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
4295 if (cpu
->apic_state
) {
4296 object_unparent(OBJECT(cpu
->apic_state
));
4297 cpu
->apic_state
= NULL
;
4300 xcc
->parent_unrealize(dev
, &local_err
);
4301 if (local_err
!= NULL
) {
4302 error_propagate(errp
, local_err
);
4307 typedef struct BitProperty
{
4312 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
4313 void *opaque
, Error
**errp
)
4315 X86CPU
*cpu
= X86_CPU(obj
);
4316 BitProperty
*fp
= opaque
;
4317 uint32_t f
= cpu
->env
.features
[fp
->w
];
4318 bool value
= (f
& fp
->mask
) == fp
->mask
;
4319 visit_type_bool(v
, name
, &value
, errp
);
4322 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
4323 void *opaque
, Error
**errp
)
4325 DeviceState
*dev
= DEVICE(obj
);
4326 X86CPU
*cpu
= X86_CPU(obj
);
4327 BitProperty
*fp
= opaque
;
4328 Error
*local_err
= NULL
;
4331 if (dev
->realized
) {
4332 qdev_prop_set_after_realize(dev
, name
, errp
);
4336 visit_type_bool(v
, name
, &value
, &local_err
);
4338 error_propagate(errp
, local_err
);
4343 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
4345 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
4347 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
4350 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
4353 BitProperty
*prop
= opaque
;
4357 /* Register a boolean property to get/set a single bit in a uint32_t field.
4359 * The same property name can be registered multiple times to make it affect
4360 * multiple bits in the same FeatureWord. In that case, the getter will return
4361 * true only if all bits are set.
4363 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
4364 const char *prop_name
,
4370 uint32_t mask
= (1UL << bitnr
);
4372 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
4378 fp
= g_new0(BitProperty
, 1);
4381 object_property_add(OBJECT(cpu
), prop_name
, "bool",
4382 x86_cpu_get_bit_prop
,
4383 x86_cpu_set_bit_prop
,
4384 x86_cpu_release_bit_prop
, fp
, &error_abort
);
4388 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
4392 FeatureWordInfo
*fi
= &feature_word_info
[w
];
4393 const char *name
= fi
->feat_names
[bitnr
];
4399 /* Property names should use "-" instead of "_".
4400 * Old names containing underscores are registered as aliases
4401 * using object_property_add_alias()
4403 assert(!strchr(name
, '_'));
4404 /* aliases don't use "|" delimiters anymore, they are registered
4405 * manually using object_property_add_alias() */
4406 assert(!strchr(name
, '|'));
4407 x86_cpu_register_bit_prop(cpu
, name
, w
, bitnr
);
4410 static GuestPanicInformation
*x86_cpu_get_crash_info(CPUState
*cs
)
4412 X86CPU
*cpu
= X86_CPU(cs
);
4413 CPUX86State
*env
= &cpu
->env
;
4414 GuestPanicInformation
*panic_info
= NULL
;
4416 if (env
->features
[FEAT_HYPERV_EDX
] & HV_GUEST_CRASH_MSR_AVAILABLE
) {
4417 panic_info
= g_malloc0(sizeof(GuestPanicInformation
));
4419 panic_info
->type
= GUEST_PANIC_INFORMATION_TYPE_HYPER_V
;
4421 assert(HV_CRASH_PARAMS
>= 5);
4422 panic_info
->u
.hyper_v
.arg1
= env
->msr_hv_crash_params
[0];
4423 panic_info
->u
.hyper_v
.arg2
= env
->msr_hv_crash_params
[1];
4424 panic_info
->u
.hyper_v
.arg3
= env
->msr_hv_crash_params
[2];
4425 panic_info
->u
.hyper_v
.arg4
= env
->msr_hv_crash_params
[3];
4426 panic_info
->u
.hyper_v
.arg5
= env
->msr_hv_crash_params
[4];
4431 static void x86_cpu_get_crash_info_qom(Object
*obj
, Visitor
*v
,
4432 const char *name
, void *opaque
,
4435 CPUState
*cs
= CPU(obj
);
4436 GuestPanicInformation
*panic_info
;
4438 if (!cs
->crash_occurred
) {
4439 error_setg(errp
, "No crash occured");
4443 panic_info
= x86_cpu_get_crash_info(cs
);
4444 if (panic_info
== NULL
) {
4445 error_setg(errp
, "No crash information");
4449 visit_type_GuestPanicInformation(v
, "crash-information", &panic_info
,
4451 qapi_free_GuestPanicInformation(panic_info
);
4454 static void x86_cpu_initfn(Object
*obj
)
4456 CPUState
*cs
= CPU(obj
);
4457 X86CPU
*cpu
= X86_CPU(obj
);
4458 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
4459 CPUX86State
*env
= &cpu
->env
;
4464 object_property_add(obj
, "family", "int",
4465 x86_cpuid_version_get_family
,
4466 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
4467 object_property_add(obj
, "model", "int",
4468 x86_cpuid_version_get_model
,
4469 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
4470 object_property_add(obj
, "stepping", "int",
4471 x86_cpuid_version_get_stepping
,
4472 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
4473 object_property_add_str(obj
, "vendor",
4474 x86_cpuid_get_vendor
,
4475 x86_cpuid_set_vendor
, NULL
);
4476 object_property_add_str(obj
, "model-id",
4477 x86_cpuid_get_model_id
,
4478 x86_cpuid_set_model_id
, NULL
);
4479 object_property_add(obj
, "tsc-frequency", "int",
4480 x86_cpuid_get_tsc_freq
,
4481 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
4482 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
4483 x86_cpu_get_feature_words
,
4484 NULL
, NULL
, (void *)env
->features
, NULL
);
4485 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
4486 x86_cpu_get_feature_words
,
4487 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
4489 object_property_add(obj
, "crash-information", "GuestPanicInformation",
4490 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
, NULL
);
4492 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
4494 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4497 for (bitnr
= 0; bitnr
< 32; bitnr
++) {
4498 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
4502 object_property_add_alias(obj
, "sse3", obj
, "pni", &error_abort
);
4503 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq", &error_abort
);
4504 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1", &error_abort
);
4505 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2", &error_abort
);
4506 object_property_add_alias(obj
, "xd", obj
, "nx", &error_abort
);
4507 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt", &error_abort
);
4508 object_property_add_alias(obj
, "i64", obj
, "lm", &error_abort
);
4510 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl", &error_abort
);
4511 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust", &error_abort
);
4512 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt", &error_abort
);
4513 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm", &error_abort
);
4514 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy", &error_abort
);
4515 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr", &error_abort
);
4516 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core", &error_abort
);
4517 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb", &error_abort
);
4518 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay", &error_abort
);
4519 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu", &error_abort
);
4520 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf", &error_abort
);
4521 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time", &error_abort
);
4522 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi", &error_abort
);
4523 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt", &error_abort
);
4524 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock", &error_abort
);
4525 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save", &error_abort
);
4526 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale", &error_abort
);
4527 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean", &error_abort
);
4528 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter", &error_abort
);
4529 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1", &error_abort
);
4530 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2", &error_abort
);
4533 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
4537 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
4539 X86CPU
*cpu
= X86_CPU(cs
);
4541 return cpu
->apic_id
;
4544 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
4546 X86CPU
*cpu
= X86_CPU(cs
);
4548 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
4551 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
4553 X86CPU
*cpu
= X86_CPU(cs
);
4555 cpu
->env
.eip
= value
;
4558 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
4560 X86CPU
*cpu
= X86_CPU(cs
);
4562 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
4565 static bool x86_cpu_has_work(CPUState
*cs
)
4567 X86CPU
*cpu
= X86_CPU(cs
);
4568 CPUX86State
*env
= &cpu
->env
;
4570 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
4571 CPU_INTERRUPT_POLL
)) &&
4572 (env
->eflags
& IF_MASK
)) ||
4573 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
4574 CPU_INTERRUPT_INIT
|
4575 CPU_INTERRUPT_SIPI
|
4576 CPU_INTERRUPT_MCE
)) ||
4577 ((cs
->interrupt_request
& CPU_INTERRUPT_SMI
) &&
4578 !(env
->hflags
& HF_SMM_MASK
));
4581 static void x86_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
4583 X86CPU
*cpu
= X86_CPU(cs
);
4584 CPUX86State
*env
= &cpu
->env
;
4586 info
->mach
= (env
->hflags
& HF_CS64_MASK
? bfd_mach_x86_64
4587 : env
->hflags
& HF_CS32_MASK
? bfd_mach_i386_i386
4588 : bfd_mach_i386_i8086
);
4589 info
->print_insn
= print_insn_i386
;
4591 info
->cap_arch
= CS_ARCH_X86
;
4592 info
->cap_mode
= (env
->hflags
& HF_CS64_MASK
? CS_MODE_64
4593 : env
->hflags
& HF_CS32_MASK
? CS_MODE_32
4595 info
->cap_insn_unit
= 1;
4596 info
->cap_insn_split
= 8;
4599 void x86_update_hflags(CPUX86State
*env
)
4602 #define HFLAG_COPY_MASK \
4603 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
4604 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
4605 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
4606 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
4608 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
4609 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
4610 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
4611 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
4612 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
4613 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
4615 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
4616 hflags
|= HF_OSFXSR_MASK
;
4619 if (env
->efer
& MSR_EFER_LMA
) {
4620 hflags
|= HF_LMA_MASK
;
4623 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
4624 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
4626 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
4627 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
4628 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
4629 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
4630 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
4631 !(hflags
& HF_CS32_MASK
)) {
4632 hflags
|= HF_ADDSEG_MASK
;
4634 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
4635 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
4638 env
->hflags
= hflags
;
4641 static Property x86_cpu_properties
[] = {
4642 #ifdef CONFIG_USER_ONLY
4643 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4644 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
4645 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
4646 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
4647 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
4649 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
4650 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
4651 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
4652 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
4654 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
4655 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
4656 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
4657 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
4658 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
4659 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
4660 DEFINE_PROP_BOOL("hv-crash", X86CPU
, hyperv_crash
, false),
4661 DEFINE_PROP_BOOL("hv-reset", X86CPU
, hyperv_reset
, false),
4662 DEFINE_PROP_BOOL("hv-vpindex", X86CPU
, hyperv_vpindex
, false),
4663 DEFINE_PROP_BOOL("hv-runtime", X86CPU
, hyperv_runtime
, false),
4664 DEFINE_PROP_BOOL("hv-synic", X86CPU
, hyperv_synic
, false),
4665 DEFINE_PROP_BOOL("hv-stimer", X86CPU
, hyperv_stimer
, false),
4666 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
4667 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
4668 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
4669 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
4670 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
4671 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
4672 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
4673 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
4674 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
4675 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
4676 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
4677 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
4678 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
4679 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
4680 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
4681 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
4682 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
4683 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
4685 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
4686 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
4689 * From "Requirements for Implementing the Microsoft
4690 * Hypervisor Interface":
4691 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
4693 * "Starting with Windows Server 2012 and Windows 8, if
4694 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
4695 * the hypervisor imposes no specific limit to the number of VPs.
4696 * In this case, Windows Server 2012 guest VMs may use more than
4697 * 64 VPs, up to the maximum supported number of processors applicable
4698 * to the specific Windows version being used."
4700 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
4701 DEFINE_PROP_END_OF_LIST()
4704 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
4706 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4707 CPUClass
*cc
= CPU_CLASS(oc
);
4708 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4710 device_class_set_parent_realize(dc
, x86_cpu_realizefn
,
4711 &xcc
->parent_realize
);
4712 device_class_set_parent_unrealize(dc
, x86_cpu_unrealizefn
,
4713 &xcc
->parent_unrealize
);
4714 dc
->props
= x86_cpu_properties
;
4716 xcc
->parent_reset
= cc
->reset
;
4717 cc
->reset
= x86_cpu_reset
;
4718 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
4720 cc
->class_by_name
= x86_cpu_class_by_name
;
4721 cc
->parse_features
= x86_cpu_parse_featurestr
;
4722 cc
->has_work
= x86_cpu_has_work
;
4724 cc
->do_interrupt
= x86_cpu_do_interrupt
;
4725 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
4727 cc
->dump_state
= x86_cpu_dump_state
;
4728 cc
->get_crash_info
= x86_cpu_get_crash_info
;
4729 cc
->set_pc
= x86_cpu_set_pc
;
4730 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
4731 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
4732 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
4733 cc
->get_arch_id
= x86_cpu_get_arch_id
;
4734 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
4735 #ifdef CONFIG_USER_ONLY
4736 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
4738 cc
->asidx_from_attrs
= x86_asidx_from_attrs
;
4739 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
4740 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
4741 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
4742 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
4743 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
4744 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
4745 cc
->vmsd
= &vmstate_x86_cpu
;
4747 cc
->gdb_arch_name
= x86_gdb_arch_name
;
4748 #ifdef TARGET_X86_64
4749 cc
->gdb_core_xml_file
= "i386-64bit.xml";
4750 cc
->gdb_num_core_regs
= 57;
4752 cc
->gdb_core_xml_file
= "i386-32bit.xml";
4753 cc
->gdb_num_core_regs
= 41;
4755 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
4756 cc
->debug_excp_handler
= breakpoint_handler
;
4758 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
4759 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
4761 cc
->tcg_initialize
= tcg_x86_init
;
4763 cc
->disas_set_info
= x86_disas_set_info
;
4765 dc
->user_creatable
= true;
4768 static const TypeInfo x86_cpu_type_info
= {
4769 .name
= TYPE_X86_CPU
,
4771 .instance_size
= sizeof(X86CPU
),
4772 .instance_init
= x86_cpu_initfn
,
4774 .class_size
= sizeof(X86CPUClass
),
4775 .class_init
= x86_cpu_common_class_init
,
4779 /* "base" CPU model, used by query-cpu-model-expansion */
4780 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
4782 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4784 xcc
->static_model
= true;
4785 xcc
->migration_safe
= true;
4786 xcc
->model_description
= "base CPU model type with no features enabled";
4790 static const TypeInfo x86_base_cpu_type_info
= {
4791 .name
= X86_CPU_TYPE_NAME("base"),
4792 .parent
= TYPE_X86_CPU
,
4793 .class_init
= x86_cpu_base_class_init
,
4796 static void x86_cpu_register_types(void)
4800 type_register_static(&x86_cpu_type_info
);
4801 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
4802 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
4804 type_register_static(&max_x86_cpu_type_info
);
4805 type_register_static(&x86_base_cpu_type_info
);
4806 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4807 type_register_static(&host_x86_cpu_type_info
);
4811 type_init(x86_cpu_register_types
)