]> git.proxmox.com Git - mirror_qemu.git/blob - target/i386/cpu.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
util/cutils: Change qemu_strtosz*() from int64_t to uint64_t
[mirror_qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
21
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/cpus.h"
26 #include "kvm_i386.h"
27
28 #include "qemu/error-report.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #if defined(CONFIG_KVM)
39 #include <linux/kvm_para.h>
40 #endif
41
42 #include "sysemu/sysemu.h"
43 #include "hw/qdev-properties.h"
44 #include "hw/i386/topology.h"
45 #ifndef CONFIG_USER_ONLY
46 #include "exec/address-spaces.h"
47 #include "hw/hw.h"
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
50 #endif
51
52
53 /* Cache topology CPUID constants: */
54
55 /* CPUID Leaf 2 Descriptors */
56
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
60 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
61
62
63 /* CPUID Leaf 4 constants: */
64
65 /* EAX: */
66 #define CPUID_4_TYPE_DCACHE 1
67 #define CPUID_4_TYPE_ICACHE 2
68 #define CPUID_4_TYPE_UNIFIED 3
69
70 #define CPUID_4_LEVEL(l) ((l) << 5)
71
72 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73 #define CPUID_4_FULLY_ASSOC (1 << 9)
74
75 /* EDX: */
76 #define CPUID_4_NO_INVD_SHARING (1 << 0)
77 #define CPUID_4_INCLUSIVE (1 << 1)
78 #define CPUID_4_COMPLEX_IDX (1 << 2)
79
80 #define ASSOC_FULL 0xFF
81
82 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97 /* Definitions of the hardcoded cache entries we expose: */
98
99 /* L1 data cache: */
100 #define L1D_LINE_SIZE 64
101 #define L1D_ASSOCIATIVITY 8
102 #define L1D_SETS 64
103 #define L1D_PARTITIONS 1
104 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107 #define L1D_LINES_PER_TAG 1
108 #define L1D_SIZE_KB_AMD 64
109 #define L1D_ASSOCIATIVITY_AMD 2
110
111 /* L1 instruction cache: */
112 #define L1I_LINE_SIZE 64
113 #define L1I_ASSOCIATIVITY 8
114 #define L1I_SETS 64
115 #define L1I_PARTITIONS 1
116 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119 #define L1I_LINES_PER_TAG 1
120 #define L1I_SIZE_KB_AMD 64
121 #define L1I_ASSOCIATIVITY_AMD 2
122
123 /* Level 2 unified cache: */
124 #define L2_LINE_SIZE 64
125 #define L2_ASSOCIATIVITY 16
126 #define L2_SETS 4096
127 #define L2_PARTITIONS 1
128 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132 #define L2_LINES_PER_TAG 1
133 #define L2_SIZE_KB_AMD 512
134
135 /* Level 3 unified cache: */
136 #define L3_SIZE_KB 0 /* disabled */
137 #define L3_ASSOCIATIVITY 0 /* disabled */
138 #define L3_LINES_PER_TAG 0 /* disabled */
139 #define L3_LINE_SIZE 0 /* disabled */
140 #define L3_N_LINE_SIZE 64
141 #define L3_N_ASSOCIATIVITY 16
142 #define L3_N_SETS 16384
143 #define L3_N_PARTITIONS 1
144 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145 #define L3_N_LINES_PER_TAG 1
146 #define L3_N_SIZE_KB_AMD 16384
147
148 /* TLB definitions: */
149
150 #define L1_DTLB_2M_ASSOC 1
151 #define L1_DTLB_2M_ENTRIES 255
152 #define L1_DTLB_4K_ASSOC 1
153 #define L1_DTLB_4K_ENTRIES 255
154
155 #define L1_ITLB_2M_ASSOC 1
156 #define L1_ITLB_2M_ENTRIES 255
157 #define L1_ITLB_4K_ASSOC 1
158 #define L1_ITLB_4K_ENTRIES 255
159
160 #define L2_DTLB_2M_ASSOC 0 /* disabled */
161 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
162 #define L2_DTLB_4K_ASSOC 4
163 #define L2_DTLB_4K_ENTRIES 512
164
165 #define L2_ITLB_2M_ASSOC 0 /* disabled */
166 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
167 #define L2_ITLB_4K_ASSOC 4
168 #define L2_ITLB_4K_ENTRIES 512
169
170
171
172 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174 {
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182 }
183
184 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
185 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
186 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
187 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
188 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
189 CPUID_PSE36 | CPUID_FXSR)
190 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
191 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
192 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
193 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
194 CPUID_PAE | CPUID_SEP | CPUID_APIC)
195
196 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
197 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
198 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
199 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
200 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
201 /* partly implemented:
202 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
203 /* missing:
204 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
205 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
206 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
207 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
208 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
209 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
210 /* missing:
211 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
212 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
213 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
214 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
215 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
216
217 #ifdef TARGET_X86_64
218 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
219 #else
220 #define TCG_EXT2_X86_64_FEATURES 0
221 #endif
222
223 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
224 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
225 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
226 TCG_EXT2_X86_64_FEATURES)
227 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
228 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
229 #define TCG_EXT4_FEATURES 0
230 #define TCG_SVM_FEATURES 0
231 #define TCG_KVM_FEATURES 0
232 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
233 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
234 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
235 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
236 CPUID_7_0_EBX_ERMS)
237 /* missing:
238 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
239 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
240 CPUID_7_0_EBX_RDSEED */
241 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
242 CPUID_7_0_ECX_LA57)
243 #define TCG_7_0_EDX_FEATURES 0
244 #define TCG_APM_FEATURES 0
245 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
246 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
247 /* missing:
248 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
249
250 typedef struct FeatureWordInfo {
251 /* feature flags names are taken from "Intel Processor Identification and
252 * the CPUID Instruction" and AMD's "CPUID Specification".
253 * In cases of disagreement between feature naming conventions,
254 * aliases may be added.
255 */
256 const char *feat_names[32];
257 uint32_t cpuid_eax; /* Input EAX for CPUID */
258 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
259 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
260 int cpuid_reg; /* output register (R_* constant) */
261 uint32_t tcg_features; /* Feature flags supported by TCG */
262 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
263 uint32_t migratable_flags; /* Feature flags known to be migratable */
264 } FeatureWordInfo;
265
266 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
267 [FEAT_1_EDX] = {
268 .feat_names = {
269 "fpu", "vme", "de", "pse",
270 "tsc", "msr", "pae", "mce",
271 "cx8", "apic", NULL, "sep",
272 "mtrr", "pge", "mca", "cmov",
273 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
274 NULL, "ds" /* Intel dts */, "acpi", "mmx",
275 "fxsr", "sse", "sse2", "ss",
276 "ht" /* Intel htt */, "tm", "ia64", "pbe",
277 },
278 .cpuid_eax = 1, .cpuid_reg = R_EDX,
279 .tcg_features = TCG_FEATURES,
280 },
281 [FEAT_1_ECX] = {
282 .feat_names = {
283 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
284 "ds-cpl", "vmx", "smx", "est",
285 "tm2", "ssse3", "cid", NULL,
286 "fma", "cx16", "xtpr", "pdcm",
287 NULL, "pcid", "dca", "sse4.1",
288 "sse4.2", "x2apic", "movbe", "popcnt",
289 "tsc-deadline", "aes", "xsave", "osxsave",
290 "avx", "f16c", "rdrand", "hypervisor",
291 },
292 .cpuid_eax = 1, .cpuid_reg = R_ECX,
293 .tcg_features = TCG_EXT_FEATURES,
294 },
295 /* Feature names that are already defined on feature_name[] but
296 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
297 * names on feat_names below. They are copied automatically
298 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
299 */
300 [FEAT_8000_0001_EDX] = {
301 .feat_names = {
302 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
303 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
304 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
305 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
306 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
307 "nx", NULL, "mmxext", NULL /* mmx */,
308 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
309 NULL, "lm", "3dnowext", "3dnow",
310 },
311 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
312 .tcg_features = TCG_EXT2_FEATURES,
313 },
314 [FEAT_8000_0001_ECX] = {
315 .feat_names = {
316 "lahf-lm", "cmp-legacy", "svm", "extapic",
317 "cr8legacy", "abm", "sse4a", "misalignsse",
318 "3dnowprefetch", "osvw", "ibs", "xop",
319 "skinit", "wdt", NULL, "lwp",
320 "fma4", "tce", NULL, "nodeid-msr",
321 NULL, "tbm", "topoext", "perfctr-core",
322 "perfctr-nb", NULL, NULL, NULL,
323 NULL, NULL, NULL, NULL,
324 },
325 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
326 .tcg_features = TCG_EXT3_FEATURES,
327 },
328 [FEAT_C000_0001_EDX] = {
329 .feat_names = {
330 NULL, NULL, "xstore", "xstore-en",
331 NULL, NULL, "xcrypt", "xcrypt-en",
332 "ace2", "ace2-en", "phe", "phe-en",
333 "pmm", "pmm-en", NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 },
339 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
340 .tcg_features = TCG_EXT4_FEATURES,
341 },
342 [FEAT_KVM] = {
343 .feat_names = {
344 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
345 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 "kvmclock-stable-bit", NULL, NULL, NULL,
351 NULL, NULL, NULL, NULL,
352 },
353 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
354 .tcg_features = TCG_KVM_FEATURES,
355 },
356 [FEAT_HYPERV_EAX] = {
357 .feat_names = {
358 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
359 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
360 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
361 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
362 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
363 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
364 NULL, NULL, NULL, NULL,
365 NULL, NULL, NULL, NULL,
366 NULL, NULL, NULL, NULL,
367 NULL, NULL, NULL, NULL,
368 NULL, NULL, NULL, NULL,
369 },
370 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
371 },
372 [FEAT_HYPERV_EBX] = {
373 .feat_names = {
374 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
375 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
376 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
377 NULL /* hv_create_port */, NULL /* hv_connect_port */,
378 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
379 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
380 NULL, NULL,
381 NULL, NULL, NULL, NULL,
382 NULL, NULL, NULL, NULL,
383 NULL, NULL, NULL, NULL,
384 NULL, NULL, NULL, NULL,
385 },
386 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
387 },
388 [FEAT_HYPERV_EDX] = {
389 .feat_names = {
390 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
391 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
392 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
393 NULL, NULL,
394 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
395 NULL, NULL, NULL, NULL,
396 NULL, NULL, NULL, NULL,
397 NULL, NULL, NULL, NULL,
398 NULL, NULL, NULL, NULL,
399 NULL, NULL, NULL, NULL,
400 },
401 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
402 },
403 [FEAT_SVM] = {
404 .feat_names = {
405 "npt", "lbrv", "svm-lock", "nrip-save",
406 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
407 NULL, NULL, "pause-filter", NULL,
408 "pfthreshold", NULL, NULL, NULL,
409 NULL, NULL, NULL, NULL,
410 NULL, NULL, NULL, NULL,
411 NULL, NULL, NULL, NULL,
412 NULL, NULL, NULL, NULL,
413 },
414 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
415 .tcg_features = TCG_SVM_FEATURES,
416 },
417 [FEAT_7_0_EBX] = {
418 .feat_names = {
419 "fsgsbase", "tsc-adjust", NULL, "bmi1",
420 "hle", "avx2", NULL, "smep",
421 "bmi2", "erms", "invpcid", "rtm",
422 NULL, NULL, "mpx", NULL,
423 "avx512f", "avx512dq", "rdseed", "adx",
424 "smap", "avx512ifma", "pcommit", "clflushopt",
425 "clwb", NULL, "avx512pf", "avx512er",
426 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
427 },
428 .cpuid_eax = 7,
429 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
430 .cpuid_reg = R_EBX,
431 .tcg_features = TCG_7_0_EBX_FEATURES,
432 },
433 [FEAT_7_0_ECX] = {
434 .feat_names = {
435 NULL, "avx512vbmi", "umip", "pku",
436 "ospke", NULL, NULL, NULL,
437 NULL, NULL, NULL, NULL,
438 NULL, NULL, "avx512-vpopcntdq", NULL,
439 "la57", NULL, NULL, NULL,
440 NULL, NULL, "rdpid", NULL,
441 NULL, NULL, NULL, NULL,
442 NULL, NULL, NULL, NULL,
443 },
444 .cpuid_eax = 7,
445 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
446 .cpuid_reg = R_ECX,
447 .tcg_features = TCG_7_0_ECX_FEATURES,
448 },
449 [FEAT_7_0_EDX] = {
450 .feat_names = {
451 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
452 NULL, NULL, NULL, NULL,
453 NULL, NULL, NULL, NULL,
454 NULL, NULL, NULL, NULL,
455 NULL, NULL, NULL, NULL,
456 NULL, NULL, NULL, NULL,
457 NULL, NULL, NULL, NULL,
458 NULL, NULL, NULL, NULL,
459 },
460 .cpuid_eax = 7,
461 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
462 .cpuid_reg = R_EDX,
463 .tcg_features = TCG_7_0_EDX_FEATURES,
464 },
465 [FEAT_8000_0007_EDX] = {
466 .feat_names = {
467 NULL, NULL, NULL, NULL,
468 NULL, NULL, NULL, NULL,
469 "invtsc", NULL, NULL, NULL,
470 NULL, NULL, NULL, NULL,
471 NULL, NULL, NULL, NULL,
472 NULL, NULL, NULL, NULL,
473 NULL, NULL, NULL, NULL,
474 NULL, NULL, NULL, NULL,
475 },
476 .cpuid_eax = 0x80000007,
477 .cpuid_reg = R_EDX,
478 .tcg_features = TCG_APM_FEATURES,
479 .unmigratable_flags = CPUID_APM_INVTSC,
480 },
481 [FEAT_XSAVE] = {
482 .feat_names = {
483 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
484 NULL, NULL, NULL, NULL,
485 NULL, NULL, NULL, NULL,
486 NULL, NULL, NULL, NULL,
487 NULL, NULL, NULL, NULL,
488 NULL, NULL, NULL, NULL,
489 NULL, NULL, NULL, NULL,
490 NULL, NULL, NULL, NULL,
491 },
492 .cpuid_eax = 0xd,
493 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
494 .cpuid_reg = R_EAX,
495 .tcg_features = TCG_XSAVE_FEATURES,
496 },
497 [FEAT_6_EAX] = {
498 .feat_names = {
499 NULL, NULL, "arat", NULL,
500 NULL, NULL, NULL, NULL,
501 NULL, NULL, NULL, NULL,
502 NULL, NULL, NULL, NULL,
503 NULL, NULL, NULL, NULL,
504 NULL, NULL, NULL, NULL,
505 NULL, NULL, NULL, NULL,
506 NULL, NULL, NULL, NULL,
507 },
508 .cpuid_eax = 6, .cpuid_reg = R_EAX,
509 .tcg_features = TCG_6_EAX_FEATURES,
510 },
511 [FEAT_XSAVE_COMP_LO] = {
512 .cpuid_eax = 0xD,
513 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
514 .cpuid_reg = R_EAX,
515 .tcg_features = ~0U,
516 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
517 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
518 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
519 XSTATE_PKRU_MASK,
520 },
521 [FEAT_XSAVE_COMP_HI] = {
522 .cpuid_eax = 0xD,
523 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
524 .cpuid_reg = R_EDX,
525 .tcg_features = ~0U,
526 },
527 };
528
529 typedef struct X86RegisterInfo32 {
530 /* Name of register */
531 const char *name;
532 /* QAPI enum value register */
533 X86CPURegister32 qapi_enum;
534 } X86RegisterInfo32;
535
536 #define REGISTER(reg) \
537 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
538 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
539 REGISTER(EAX),
540 REGISTER(ECX),
541 REGISTER(EDX),
542 REGISTER(EBX),
543 REGISTER(ESP),
544 REGISTER(EBP),
545 REGISTER(ESI),
546 REGISTER(EDI),
547 };
548 #undef REGISTER
549
550 typedef struct ExtSaveArea {
551 uint32_t feature, bits;
552 uint32_t offset, size;
553 } ExtSaveArea;
554
555 static const ExtSaveArea x86_ext_save_areas[] = {
556 [XSTATE_FP_BIT] = {
557 /* x87 FP state component is always enabled if XSAVE is supported */
558 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
559 /* x87 state is in the legacy region of the XSAVE area */
560 .offset = 0,
561 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
562 },
563 [XSTATE_SSE_BIT] = {
564 /* SSE state component is always enabled if XSAVE is supported */
565 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
566 /* SSE state is in the legacy region of the XSAVE area */
567 .offset = 0,
568 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
569 },
570 [XSTATE_YMM_BIT] =
571 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
572 .offset = offsetof(X86XSaveArea, avx_state),
573 .size = sizeof(XSaveAVX) },
574 [XSTATE_BNDREGS_BIT] =
575 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
576 .offset = offsetof(X86XSaveArea, bndreg_state),
577 .size = sizeof(XSaveBNDREG) },
578 [XSTATE_BNDCSR_BIT] =
579 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
580 .offset = offsetof(X86XSaveArea, bndcsr_state),
581 .size = sizeof(XSaveBNDCSR) },
582 [XSTATE_OPMASK_BIT] =
583 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
584 .offset = offsetof(X86XSaveArea, opmask_state),
585 .size = sizeof(XSaveOpmask) },
586 [XSTATE_ZMM_Hi256_BIT] =
587 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
588 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
589 .size = sizeof(XSaveZMM_Hi256) },
590 [XSTATE_Hi16_ZMM_BIT] =
591 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
592 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
593 .size = sizeof(XSaveHi16_ZMM) },
594 [XSTATE_PKRU_BIT] =
595 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
596 .offset = offsetof(X86XSaveArea, pkru_state),
597 .size = sizeof(XSavePKRU) },
598 };
599
600 static uint32_t xsave_area_size(uint64_t mask)
601 {
602 int i;
603 uint64_t ret = 0;
604
605 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
606 const ExtSaveArea *esa = &x86_ext_save_areas[i];
607 if ((mask >> i) & 1) {
608 ret = MAX(ret, esa->offset + esa->size);
609 }
610 }
611 return ret;
612 }
613
614 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
615 {
616 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
617 cpu->env.features[FEAT_XSAVE_COMP_LO];
618 }
619
620 const char *get_register_name_32(unsigned int reg)
621 {
622 if (reg >= CPU_NB_REGS32) {
623 return NULL;
624 }
625 return x86_reg_info_32[reg].name;
626 }
627
628 /*
629 * Returns the set of feature flags that are supported and migratable by
630 * QEMU, for a given FeatureWord.
631 */
632 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
633 {
634 FeatureWordInfo *wi = &feature_word_info[w];
635 uint32_t r = 0;
636 int i;
637
638 for (i = 0; i < 32; i++) {
639 uint32_t f = 1U << i;
640
641 /* If the feature name is known, it is implicitly considered migratable,
642 * unless it is explicitly set in unmigratable_flags */
643 if ((wi->migratable_flags & f) ||
644 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
645 r |= f;
646 }
647 }
648 return r;
649 }
650
651 void host_cpuid(uint32_t function, uint32_t count,
652 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
653 {
654 uint32_t vec[4];
655
656 #ifdef __x86_64__
657 asm volatile("cpuid"
658 : "=a"(vec[0]), "=b"(vec[1]),
659 "=c"(vec[2]), "=d"(vec[3])
660 : "0"(function), "c"(count) : "cc");
661 #elif defined(__i386__)
662 asm volatile("pusha \n\t"
663 "cpuid \n\t"
664 "mov %%eax, 0(%2) \n\t"
665 "mov %%ebx, 4(%2) \n\t"
666 "mov %%ecx, 8(%2) \n\t"
667 "mov %%edx, 12(%2) \n\t"
668 "popa"
669 : : "a"(function), "c"(count), "S"(vec)
670 : "memory", "cc");
671 #else
672 abort();
673 #endif
674
675 if (eax)
676 *eax = vec[0];
677 if (ebx)
678 *ebx = vec[1];
679 if (ecx)
680 *ecx = vec[2];
681 if (edx)
682 *edx = vec[3];
683 }
684
685 /* CPU class name definitions: */
686
687 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
688 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
689
690 /* Return type name for a given CPU model name
691 * Caller is responsible for freeing the returned string.
692 */
693 static char *x86_cpu_type_name(const char *model_name)
694 {
695 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
696 }
697
698 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
699 {
700 ObjectClass *oc;
701 char *typename;
702
703 if (cpu_model == NULL) {
704 return NULL;
705 }
706
707 typename = x86_cpu_type_name(cpu_model);
708 oc = object_class_by_name(typename);
709 g_free(typename);
710 return oc;
711 }
712
713 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
714 {
715 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
716 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
717 return g_strndup(class_name,
718 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
719 }
720
721 struct X86CPUDefinition {
722 const char *name;
723 uint32_t level;
724 uint32_t xlevel;
725 /* vendor is zero-terminated, 12 character ASCII string */
726 char vendor[CPUID_VENDOR_SZ + 1];
727 int family;
728 int model;
729 int stepping;
730 FeatureWordArray features;
731 char model_id[48];
732 };
733
734 static X86CPUDefinition builtin_x86_defs[] = {
735 {
736 .name = "qemu64",
737 .level = 0xd,
738 .vendor = CPUID_VENDOR_AMD,
739 .family = 6,
740 .model = 6,
741 .stepping = 3,
742 .features[FEAT_1_EDX] =
743 PPRO_FEATURES |
744 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
745 CPUID_PSE36,
746 .features[FEAT_1_ECX] =
747 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
748 .features[FEAT_8000_0001_EDX] =
749 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
750 .features[FEAT_8000_0001_ECX] =
751 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
752 .xlevel = 0x8000000A,
753 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
754 },
755 {
756 .name = "phenom",
757 .level = 5,
758 .vendor = CPUID_VENDOR_AMD,
759 .family = 16,
760 .model = 2,
761 .stepping = 3,
762 /* Missing: CPUID_HT */
763 .features[FEAT_1_EDX] =
764 PPRO_FEATURES |
765 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
766 CPUID_PSE36 | CPUID_VME,
767 .features[FEAT_1_ECX] =
768 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
769 CPUID_EXT_POPCNT,
770 .features[FEAT_8000_0001_EDX] =
771 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
772 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
773 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
774 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
775 CPUID_EXT3_CR8LEG,
776 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
777 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
778 .features[FEAT_8000_0001_ECX] =
779 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
780 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
781 /* Missing: CPUID_SVM_LBRV */
782 .features[FEAT_SVM] =
783 CPUID_SVM_NPT,
784 .xlevel = 0x8000001A,
785 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
786 },
787 {
788 .name = "core2duo",
789 .level = 10,
790 .vendor = CPUID_VENDOR_INTEL,
791 .family = 6,
792 .model = 15,
793 .stepping = 11,
794 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
795 .features[FEAT_1_EDX] =
796 PPRO_FEATURES |
797 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
798 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
799 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
800 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
801 .features[FEAT_1_ECX] =
802 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
803 CPUID_EXT_CX16,
804 .features[FEAT_8000_0001_EDX] =
805 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
806 .features[FEAT_8000_0001_ECX] =
807 CPUID_EXT3_LAHF_LM,
808 .xlevel = 0x80000008,
809 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
810 },
811 {
812 .name = "kvm64",
813 .level = 0xd,
814 .vendor = CPUID_VENDOR_INTEL,
815 .family = 15,
816 .model = 6,
817 .stepping = 1,
818 /* Missing: CPUID_HT */
819 .features[FEAT_1_EDX] =
820 PPRO_FEATURES | CPUID_VME |
821 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
822 CPUID_PSE36,
823 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
824 .features[FEAT_1_ECX] =
825 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
826 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
827 .features[FEAT_8000_0001_EDX] =
828 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
829 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
830 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
831 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
832 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
833 .features[FEAT_8000_0001_ECX] =
834 0,
835 .xlevel = 0x80000008,
836 .model_id = "Common KVM processor"
837 },
838 {
839 .name = "qemu32",
840 .level = 4,
841 .vendor = CPUID_VENDOR_INTEL,
842 .family = 6,
843 .model = 6,
844 .stepping = 3,
845 .features[FEAT_1_EDX] =
846 PPRO_FEATURES,
847 .features[FEAT_1_ECX] =
848 CPUID_EXT_SSE3,
849 .xlevel = 0x80000004,
850 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
851 },
852 {
853 .name = "kvm32",
854 .level = 5,
855 .vendor = CPUID_VENDOR_INTEL,
856 .family = 15,
857 .model = 6,
858 .stepping = 1,
859 .features[FEAT_1_EDX] =
860 PPRO_FEATURES | CPUID_VME |
861 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
862 .features[FEAT_1_ECX] =
863 CPUID_EXT_SSE3,
864 .features[FEAT_8000_0001_ECX] =
865 0,
866 .xlevel = 0x80000008,
867 .model_id = "Common 32-bit KVM processor"
868 },
869 {
870 .name = "coreduo",
871 .level = 10,
872 .vendor = CPUID_VENDOR_INTEL,
873 .family = 6,
874 .model = 14,
875 .stepping = 8,
876 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
877 .features[FEAT_1_EDX] =
878 PPRO_FEATURES | CPUID_VME |
879 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
880 CPUID_SS,
881 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
882 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
883 .features[FEAT_1_ECX] =
884 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
885 .features[FEAT_8000_0001_EDX] =
886 CPUID_EXT2_NX,
887 .xlevel = 0x80000008,
888 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
889 },
890 {
891 .name = "486",
892 .level = 1,
893 .vendor = CPUID_VENDOR_INTEL,
894 .family = 4,
895 .model = 8,
896 .stepping = 0,
897 .features[FEAT_1_EDX] =
898 I486_FEATURES,
899 .xlevel = 0,
900 },
901 {
902 .name = "pentium",
903 .level = 1,
904 .vendor = CPUID_VENDOR_INTEL,
905 .family = 5,
906 .model = 4,
907 .stepping = 3,
908 .features[FEAT_1_EDX] =
909 PENTIUM_FEATURES,
910 .xlevel = 0,
911 },
912 {
913 .name = "pentium2",
914 .level = 2,
915 .vendor = CPUID_VENDOR_INTEL,
916 .family = 6,
917 .model = 5,
918 .stepping = 2,
919 .features[FEAT_1_EDX] =
920 PENTIUM2_FEATURES,
921 .xlevel = 0,
922 },
923 {
924 .name = "pentium3",
925 .level = 3,
926 .vendor = CPUID_VENDOR_INTEL,
927 .family = 6,
928 .model = 7,
929 .stepping = 3,
930 .features[FEAT_1_EDX] =
931 PENTIUM3_FEATURES,
932 .xlevel = 0,
933 },
934 {
935 .name = "athlon",
936 .level = 2,
937 .vendor = CPUID_VENDOR_AMD,
938 .family = 6,
939 .model = 2,
940 .stepping = 3,
941 .features[FEAT_1_EDX] =
942 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
943 CPUID_MCA,
944 .features[FEAT_8000_0001_EDX] =
945 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
946 .xlevel = 0x80000008,
947 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
948 },
949 {
950 .name = "n270",
951 .level = 10,
952 .vendor = CPUID_VENDOR_INTEL,
953 .family = 6,
954 .model = 28,
955 .stepping = 2,
956 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
957 .features[FEAT_1_EDX] =
958 PPRO_FEATURES |
959 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
960 CPUID_ACPI | CPUID_SS,
961 /* Some CPUs got no CPUID_SEP */
962 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
963 * CPUID_EXT_XTPR */
964 .features[FEAT_1_ECX] =
965 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
966 CPUID_EXT_MOVBE,
967 .features[FEAT_8000_0001_EDX] =
968 CPUID_EXT2_NX,
969 .features[FEAT_8000_0001_ECX] =
970 CPUID_EXT3_LAHF_LM,
971 .xlevel = 0x80000008,
972 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
973 },
974 {
975 .name = "Conroe",
976 .level = 10,
977 .vendor = CPUID_VENDOR_INTEL,
978 .family = 6,
979 .model = 15,
980 .stepping = 3,
981 .features[FEAT_1_EDX] =
982 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
983 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
984 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
985 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
986 CPUID_DE | CPUID_FP87,
987 .features[FEAT_1_ECX] =
988 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
989 .features[FEAT_8000_0001_EDX] =
990 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
991 .features[FEAT_8000_0001_ECX] =
992 CPUID_EXT3_LAHF_LM,
993 .xlevel = 0x80000008,
994 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
995 },
996 {
997 .name = "Penryn",
998 .level = 10,
999 .vendor = CPUID_VENDOR_INTEL,
1000 .family = 6,
1001 .model = 23,
1002 .stepping = 3,
1003 .features[FEAT_1_EDX] =
1004 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1005 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1006 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1007 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1008 CPUID_DE | CPUID_FP87,
1009 .features[FEAT_1_ECX] =
1010 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1011 CPUID_EXT_SSE3,
1012 .features[FEAT_8000_0001_EDX] =
1013 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1014 .features[FEAT_8000_0001_ECX] =
1015 CPUID_EXT3_LAHF_LM,
1016 .xlevel = 0x80000008,
1017 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1018 },
1019 {
1020 .name = "Nehalem",
1021 .level = 11,
1022 .vendor = CPUID_VENDOR_INTEL,
1023 .family = 6,
1024 .model = 26,
1025 .stepping = 3,
1026 .features[FEAT_1_EDX] =
1027 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1028 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1029 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1030 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1031 CPUID_DE | CPUID_FP87,
1032 .features[FEAT_1_ECX] =
1033 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1034 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1035 .features[FEAT_8000_0001_EDX] =
1036 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1037 .features[FEAT_8000_0001_ECX] =
1038 CPUID_EXT3_LAHF_LM,
1039 .xlevel = 0x80000008,
1040 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1041 },
1042 {
1043 .name = "Westmere",
1044 .level = 11,
1045 .vendor = CPUID_VENDOR_INTEL,
1046 .family = 6,
1047 .model = 44,
1048 .stepping = 1,
1049 .features[FEAT_1_EDX] =
1050 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1051 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054 CPUID_DE | CPUID_FP87,
1055 .features[FEAT_1_ECX] =
1056 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1057 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1058 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1059 .features[FEAT_8000_0001_EDX] =
1060 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1061 .features[FEAT_8000_0001_ECX] =
1062 CPUID_EXT3_LAHF_LM,
1063 .features[FEAT_6_EAX] =
1064 CPUID_6_EAX_ARAT,
1065 .xlevel = 0x80000008,
1066 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1067 },
1068 {
1069 .name = "SandyBridge",
1070 .level = 0xd,
1071 .vendor = CPUID_VENDOR_INTEL,
1072 .family = 6,
1073 .model = 42,
1074 .stepping = 1,
1075 .features[FEAT_1_EDX] =
1076 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1077 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1078 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1079 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1080 CPUID_DE | CPUID_FP87,
1081 .features[FEAT_1_ECX] =
1082 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1083 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1084 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1085 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1086 CPUID_EXT_SSE3,
1087 .features[FEAT_8000_0001_EDX] =
1088 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1089 CPUID_EXT2_SYSCALL,
1090 .features[FEAT_8000_0001_ECX] =
1091 CPUID_EXT3_LAHF_LM,
1092 .features[FEAT_XSAVE] =
1093 CPUID_XSAVE_XSAVEOPT,
1094 .features[FEAT_6_EAX] =
1095 CPUID_6_EAX_ARAT,
1096 .xlevel = 0x80000008,
1097 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1098 },
1099 {
1100 .name = "IvyBridge",
1101 .level = 0xd,
1102 .vendor = CPUID_VENDOR_INTEL,
1103 .family = 6,
1104 .model = 58,
1105 .stepping = 9,
1106 .features[FEAT_1_EDX] =
1107 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1108 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1109 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1110 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1111 CPUID_DE | CPUID_FP87,
1112 .features[FEAT_1_ECX] =
1113 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1114 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1115 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1116 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1117 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1118 .features[FEAT_7_0_EBX] =
1119 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1120 CPUID_7_0_EBX_ERMS,
1121 .features[FEAT_8000_0001_EDX] =
1122 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1123 CPUID_EXT2_SYSCALL,
1124 .features[FEAT_8000_0001_ECX] =
1125 CPUID_EXT3_LAHF_LM,
1126 .features[FEAT_XSAVE] =
1127 CPUID_XSAVE_XSAVEOPT,
1128 .features[FEAT_6_EAX] =
1129 CPUID_6_EAX_ARAT,
1130 .xlevel = 0x80000008,
1131 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1132 },
1133 {
1134 .name = "Haswell-noTSX",
1135 .level = 0xd,
1136 .vendor = CPUID_VENDOR_INTEL,
1137 .family = 6,
1138 .model = 60,
1139 .stepping = 1,
1140 .features[FEAT_1_EDX] =
1141 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1142 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1143 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1144 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1145 CPUID_DE | CPUID_FP87,
1146 .features[FEAT_1_ECX] =
1147 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1148 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1149 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1150 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1151 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1152 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1153 .features[FEAT_8000_0001_EDX] =
1154 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1155 CPUID_EXT2_SYSCALL,
1156 .features[FEAT_8000_0001_ECX] =
1157 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1158 .features[FEAT_7_0_EBX] =
1159 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1160 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1161 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1162 .features[FEAT_XSAVE] =
1163 CPUID_XSAVE_XSAVEOPT,
1164 .features[FEAT_6_EAX] =
1165 CPUID_6_EAX_ARAT,
1166 .xlevel = 0x80000008,
1167 .model_id = "Intel Core Processor (Haswell, no TSX)",
1168 }, {
1169 .name = "Haswell",
1170 .level = 0xd,
1171 .vendor = CPUID_VENDOR_INTEL,
1172 .family = 6,
1173 .model = 60,
1174 .stepping = 1,
1175 .features[FEAT_1_EDX] =
1176 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1177 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1178 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1179 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1180 CPUID_DE | CPUID_FP87,
1181 .features[FEAT_1_ECX] =
1182 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1183 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1184 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1185 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1186 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1187 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1188 .features[FEAT_8000_0001_EDX] =
1189 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1190 CPUID_EXT2_SYSCALL,
1191 .features[FEAT_8000_0001_ECX] =
1192 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1193 .features[FEAT_7_0_EBX] =
1194 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1195 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1196 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1197 CPUID_7_0_EBX_RTM,
1198 .features[FEAT_XSAVE] =
1199 CPUID_XSAVE_XSAVEOPT,
1200 .features[FEAT_6_EAX] =
1201 CPUID_6_EAX_ARAT,
1202 .xlevel = 0x80000008,
1203 .model_id = "Intel Core Processor (Haswell)",
1204 },
1205 {
1206 .name = "Broadwell-noTSX",
1207 .level = 0xd,
1208 .vendor = CPUID_VENDOR_INTEL,
1209 .family = 6,
1210 .model = 61,
1211 .stepping = 2,
1212 .features[FEAT_1_EDX] =
1213 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1214 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1215 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1216 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1217 CPUID_DE | CPUID_FP87,
1218 .features[FEAT_1_ECX] =
1219 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1220 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1221 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1222 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1223 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1224 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1225 .features[FEAT_8000_0001_EDX] =
1226 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1227 CPUID_EXT2_SYSCALL,
1228 .features[FEAT_8000_0001_ECX] =
1229 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1230 .features[FEAT_7_0_EBX] =
1231 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1232 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1233 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1234 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1235 CPUID_7_0_EBX_SMAP,
1236 .features[FEAT_XSAVE] =
1237 CPUID_XSAVE_XSAVEOPT,
1238 .features[FEAT_6_EAX] =
1239 CPUID_6_EAX_ARAT,
1240 .xlevel = 0x80000008,
1241 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1242 },
1243 {
1244 .name = "Broadwell",
1245 .level = 0xd,
1246 .vendor = CPUID_VENDOR_INTEL,
1247 .family = 6,
1248 .model = 61,
1249 .stepping = 2,
1250 .features[FEAT_1_EDX] =
1251 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1252 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1253 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1254 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1255 CPUID_DE | CPUID_FP87,
1256 .features[FEAT_1_ECX] =
1257 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1258 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1259 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1260 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1261 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1262 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1263 .features[FEAT_8000_0001_EDX] =
1264 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1265 CPUID_EXT2_SYSCALL,
1266 .features[FEAT_8000_0001_ECX] =
1267 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1268 .features[FEAT_7_0_EBX] =
1269 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1270 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1271 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1272 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1273 CPUID_7_0_EBX_SMAP,
1274 .features[FEAT_XSAVE] =
1275 CPUID_XSAVE_XSAVEOPT,
1276 .features[FEAT_6_EAX] =
1277 CPUID_6_EAX_ARAT,
1278 .xlevel = 0x80000008,
1279 .model_id = "Intel Core Processor (Broadwell)",
1280 },
1281 {
1282 .name = "Skylake-Client",
1283 .level = 0xd,
1284 .vendor = CPUID_VENDOR_INTEL,
1285 .family = 6,
1286 .model = 94,
1287 .stepping = 3,
1288 .features[FEAT_1_EDX] =
1289 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1290 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1291 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1292 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1293 CPUID_DE | CPUID_FP87,
1294 .features[FEAT_1_ECX] =
1295 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1296 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1297 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1298 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1299 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1300 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1301 .features[FEAT_8000_0001_EDX] =
1302 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1303 CPUID_EXT2_SYSCALL,
1304 .features[FEAT_8000_0001_ECX] =
1305 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1306 .features[FEAT_7_0_EBX] =
1307 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1308 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1309 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1310 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1311 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1312 /* Missing: XSAVES (not supported by some Linux versions,
1313 * including v4.1 to v4.6).
1314 * KVM doesn't yet expose any XSAVES state save component,
1315 * and the only one defined in Skylake (processor tracing)
1316 * probably will block migration anyway.
1317 */
1318 .features[FEAT_XSAVE] =
1319 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1320 CPUID_XSAVE_XGETBV1,
1321 .features[FEAT_6_EAX] =
1322 CPUID_6_EAX_ARAT,
1323 .xlevel = 0x80000008,
1324 .model_id = "Intel Core Processor (Skylake)",
1325 },
1326 {
1327 .name = "Opteron_G1",
1328 .level = 5,
1329 .vendor = CPUID_VENDOR_AMD,
1330 .family = 15,
1331 .model = 6,
1332 .stepping = 1,
1333 .features[FEAT_1_EDX] =
1334 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1335 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1336 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1337 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1338 CPUID_DE | CPUID_FP87,
1339 .features[FEAT_1_ECX] =
1340 CPUID_EXT_SSE3,
1341 .features[FEAT_8000_0001_EDX] =
1342 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1343 .xlevel = 0x80000008,
1344 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1345 },
1346 {
1347 .name = "Opteron_G2",
1348 .level = 5,
1349 .vendor = CPUID_VENDOR_AMD,
1350 .family = 15,
1351 .model = 6,
1352 .stepping = 1,
1353 .features[FEAT_1_EDX] =
1354 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1355 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1356 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1357 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1358 CPUID_DE | CPUID_FP87,
1359 .features[FEAT_1_ECX] =
1360 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1361 /* Missing: CPUID_EXT2_RDTSCP */
1362 .features[FEAT_8000_0001_EDX] =
1363 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1364 .features[FEAT_8000_0001_ECX] =
1365 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1366 .xlevel = 0x80000008,
1367 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1368 },
1369 {
1370 .name = "Opteron_G3",
1371 .level = 5,
1372 .vendor = CPUID_VENDOR_AMD,
1373 .family = 16,
1374 .model = 2,
1375 .stepping = 3,
1376 .features[FEAT_1_EDX] =
1377 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1378 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1379 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1380 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1381 CPUID_DE | CPUID_FP87,
1382 .features[FEAT_1_ECX] =
1383 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1384 CPUID_EXT_SSE3,
1385 /* Missing: CPUID_EXT2_RDTSCP */
1386 .features[FEAT_8000_0001_EDX] =
1387 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1388 .features[FEAT_8000_0001_ECX] =
1389 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1390 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1391 .xlevel = 0x80000008,
1392 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1393 },
1394 {
1395 .name = "Opteron_G4",
1396 .level = 0xd,
1397 .vendor = CPUID_VENDOR_AMD,
1398 .family = 21,
1399 .model = 1,
1400 .stepping = 2,
1401 .features[FEAT_1_EDX] =
1402 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1403 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1404 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1405 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1406 CPUID_DE | CPUID_FP87,
1407 .features[FEAT_1_ECX] =
1408 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1409 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1410 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1411 CPUID_EXT_SSE3,
1412 /* Missing: CPUID_EXT2_RDTSCP */
1413 .features[FEAT_8000_0001_EDX] =
1414 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1415 CPUID_EXT2_SYSCALL,
1416 .features[FEAT_8000_0001_ECX] =
1417 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1418 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1419 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1420 CPUID_EXT3_LAHF_LM,
1421 /* no xsaveopt! */
1422 .xlevel = 0x8000001A,
1423 .model_id = "AMD Opteron 62xx class CPU",
1424 },
1425 {
1426 .name = "Opteron_G5",
1427 .level = 0xd,
1428 .vendor = CPUID_VENDOR_AMD,
1429 .family = 21,
1430 .model = 2,
1431 .stepping = 0,
1432 .features[FEAT_1_EDX] =
1433 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1434 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1435 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1436 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1437 CPUID_DE | CPUID_FP87,
1438 .features[FEAT_1_ECX] =
1439 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1440 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1441 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1442 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1443 /* Missing: CPUID_EXT2_RDTSCP */
1444 .features[FEAT_8000_0001_EDX] =
1445 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
1446 CPUID_EXT2_SYSCALL,
1447 .features[FEAT_8000_0001_ECX] =
1448 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1449 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1450 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1451 CPUID_EXT3_LAHF_LM,
1452 /* no xsaveopt! */
1453 .xlevel = 0x8000001A,
1454 .model_id = "AMD Opteron 63xx class CPU",
1455 },
1456 };
1457
1458 typedef struct PropValue {
1459 const char *prop, *value;
1460 } PropValue;
1461
1462 /* KVM-specific features that are automatically added/removed
1463 * from all CPU models when KVM is enabled.
1464 */
1465 static PropValue kvm_default_props[] = {
1466 { "kvmclock", "on" },
1467 { "kvm-nopiodelay", "on" },
1468 { "kvm-asyncpf", "on" },
1469 { "kvm-steal-time", "on" },
1470 { "kvm-pv-eoi", "on" },
1471 { "kvmclock-stable-bit", "on" },
1472 { "x2apic", "on" },
1473 { "acpi", "off" },
1474 { "monitor", "off" },
1475 { "svm", "off" },
1476 { NULL, NULL },
1477 };
1478
1479 /* TCG-specific defaults that override all CPU models when using TCG
1480 */
1481 static PropValue tcg_default_props[] = {
1482 { "vme", "off" },
1483 { NULL, NULL },
1484 };
1485
1486
1487 void x86_cpu_change_kvm_default(const char *prop, const char *value)
1488 {
1489 PropValue *pv;
1490 for (pv = kvm_default_props; pv->prop; pv++) {
1491 if (!strcmp(pv->prop, prop)) {
1492 pv->value = value;
1493 break;
1494 }
1495 }
1496
1497 /* It is valid to call this function only for properties that
1498 * are already present in the kvm_default_props table.
1499 */
1500 assert(pv->prop);
1501 }
1502
1503 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1504 bool migratable_only);
1505
1506 #ifdef CONFIG_KVM
1507
1508 static bool lmce_supported(void)
1509 {
1510 uint64_t mce_cap;
1511
1512 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1513 return false;
1514 }
1515
1516 return !!(mce_cap & MCG_LMCE_P);
1517 }
1518
1519 static int cpu_x86_fill_model_id(char *str)
1520 {
1521 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1522 int i;
1523
1524 for (i = 0; i < 3; i++) {
1525 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1526 memcpy(str + i * 16 + 0, &eax, 4);
1527 memcpy(str + i * 16 + 4, &ebx, 4);
1528 memcpy(str + i * 16 + 8, &ecx, 4);
1529 memcpy(str + i * 16 + 12, &edx, 4);
1530 }
1531 return 0;
1532 }
1533
1534 static X86CPUDefinition host_cpudef;
1535
1536 static Property host_x86_cpu_properties[] = {
1537 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1538 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
1539 DEFINE_PROP_END_OF_LIST()
1540 };
1541
1542 /* class_init for the "host" CPU model
1543 *
1544 * This function may be called before KVM is initialized.
1545 */
1546 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1547 {
1548 DeviceClass *dc = DEVICE_CLASS(oc);
1549 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1550 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1551
1552 xcc->kvm_required = true;
1553
1554 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1555 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1556
1557 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1558 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1559 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1560 host_cpudef.stepping = eax & 0x0F;
1561
1562 cpu_x86_fill_model_id(host_cpudef.model_id);
1563
1564 xcc->cpu_def = &host_cpudef;
1565 xcc->model_description =
1566 "KVM processor with all supported host features "
1567 "(only available in KVM mode)";
1568
1569 /* level, xlevel, xlevel2, and the feature words are initialized on
1570 * instance_init, because they require KVM to be initialized.
1571 */
1572
1573 dc->props = host_x86_cpu_properties;
1574 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1575 dc->cannot_destroy_with_object_finalize_yet = true;
1576 }
1577
1578 static void host_x86_cpu_initfn(Object *obj)
1579 {
1580 X86CPU *cpu = X86_CPU(obj);
1581 CPUX86State *env = &cpu->env;
1582 KVMState *s = kvm_state;
1583
1584 /* We can't fill the features array here because we don't know yet if
1585 * "migratable" is true or false.
1586 */
1587 cpu->host_features = true;
1588
1589 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
1590 if (kvm_enabled()) {
1591 env->cpuid_min_level =
1592 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1593 env->cpuid_min_xlevel =
1594 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1595 env->cpuid_min_xlevel2 =
1596 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1597
1598 if (lmce_supported()) {
1599 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1600 }
1601 }
1602
1603 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1604 }
1605
1606 static const TypeInfo host_x86_cpu_type_info = {
1607 .name = X86_CPU_TYPE_NAME("host"),
1608 .parent = TYPE_X86_CPU,
1609 .instance_init = host_x86_cpu_initfn,
1610 .class_init = host_x86_cpu_class_init,
1611 };
1612
1613 #endif
1614
1615 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1616 {
1617 FeatureWordInfo *f = &feature_word_info[w];
1618 int i;
1619
1620 for (i = 0; i < 32; ++i) {
1621 if ((1UL << i) & mask) {
1622 const char *reg = get_register_name_32(f->cpuid_reg);
1623 assert(reg);
1624 fprintf(stderr, "warning: %s doesn't support requested feature: "
1625 "CPUID.%02XH:%s%s%s [bit %d]\n",
1626 kvm_enabled() ? "host" : "TCG",
1627 f->cpuid_eax, reg,
1628 f->feat_names[i] ? "." : "",
1629 f->feat_names[i] ? f->feat_names[i] : "", i);
1630 }
1631 }
1632 }
1633
1634 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1635 const char *name, void *opaque,
1636 Error **errp)
1637 {
1638 X86CPU *cpu = X86_CPU(obj);
1639 CPUX86State *env = &cpu->env;
1640 int64_t value;
1641
1642 value = (env->cpuid_version >> 8) & 0xf;
1643 if (value == 0xf) {
1644 value += (env->cpuid_version >> 20) & 0xff;
1645 }
1646 visit_type_int(v, name, &value, errp);
1647 }
1648
1649 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1650 const char *name, void *opaque,
1651 Error **errp)
1652 {
1653 X86CPU *cpu = X86_CPU(obj);
1654 CPUX86State *env = &cpu->env;
1655 const int64_t min = 0;
1656 const int64_t max = 0xff + 0xf;
1657 Error *local_err = NULL;
1658 int64_t value;
1659
1660 visit_type_int(v, name, &value, &local_err);
1661 if (local_err) {
1662 error_propagate(errp, local_err);
1663 return;
1664 }
1665 if (value < min || value > max) {
1666 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1667 name ? name : "null", value, min, max);
1668 return;
1669 }
1670
1671 env->cpuid_version &= ~0xff00f00;
1672 if (value > 0x0f) {
1673 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1674 } else {
1675 env->cpuid_version |= value << 8;
1676 }
1677 }
1678
1679 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1680 const char *name, void *opaque,
1681 Error **errp)
1682 {
1683 X86CPU *cpu = X86_CPU(obj);
1684 CPUX86State *env = &cpu->env;
1685 int64_t value;
1686
1687 value = (env->cpuid_version >> 4) & 0xf;
1688 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1689 visit_type_int(v, name, &value, errp);
1690 }
1691
1692 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1693 const char *name, void *opaque,
1694 Error **errp)
1695 {
1696 X86CPU *cpu = X86_CPU(obj);
1697 CPUX86State *env = &cpu->env;
1698 const int64_t min = 0;
1699 const int64_t max = 0xff;
1700 Error *local_err = NULL;
1701 int64_t value;
1702
1703 visit_type_int(v, name, &value, &local_err);
1704 if (local_err) {
1705 error_propagate(errp, local_err);
1706 return;
1707 }
1708 if (value < min || value > max) {
1709 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1710 name ? name : "null", value, min, max);
1711 return;
1712 }
1713
1714 env->cpuid_version &= ~0xf00f0;
1715 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1716 }
1717
1718 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1719 const char *name, void *opaque,
1720 Error **errp)
1721 {
1722 X86CPU *cpu = X86_CPU(obj);
1723 CPUX86State *env = &cpu->env;
1724 int64_t value;
1725
1726 value = env->cpuid_version & 0xf;
1727 visit_type_int(v, name, &value, errp);
1728 }
1729
1730 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1731 const char *name, void *opaque,
1732 Error **errp)
1733 {
1734 X86CPU *cpu = X86_CPU(obj);
1735 CPUX86State *env = &cpu->env;
1736 const int64_t min = 0;
1737 const int64_t max = 0xf;
1738 Error *local_err = NULL;
1739 int64_t value;
1740
1741 visit_type_int(v, name, &value, &local_err);
1742 if (local_err) {
1743 error_propagate(errp, local_err);
1744 return;
1745 }
1746 if (value < min || value > max) {
1747 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1748 name ? name : "null", value, min, max);
1749 return;
1750 }
1751
1752 env->cpuid_version &= ~0xf;
1753 env->cpuid_version |= value & 0xf;
1754 }
1755
1756 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1757 {
1758 X86CPU *cpu = X86_CPU(obj);
1759 CPUX86State *env = &cpu->env;
1760 char *value;
1761
1762 value = g_malloc(CPUID_VENDOR_SZ + 1);
1763 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1764 env->cpuid_vendor3);
1765 return value;
1766 }
1767
1768 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1769 Error **errp)
1770 {
1771 X86CPU *cpu = X86_CPU(obj);
1772 CPUX86State *env = &cpu->env;
1773 int i;
1774
1775 if (strlen(value) != CPUID_VENDOR_SZ) {
1776 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
1777 return;
1778 }
1779
1780 env->cpuid_vendor1 = 0;
1781 env->cpuid_vendor2 = 0;
1782 env->cpuid_vendor3 = 0;
1783 for (i = 0; i < 4; i++) {
1784 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1785 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1786 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1787 }
1788 }
1789
1790 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1791 {
1792 X86CPU *cpu = X86_CPU(obj);
1793 CPUX86State *env = &cpu->env;
1794 char *value;
1795 int i;
1796
1797 value = g_malloc(48 + 1);
1798 for (i = 0; i < 48; i++) {
1799 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1800 }
1801 value[48] = '\0';
1802 return value;
1803 }
1804
1805 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1806 Error **errp)
1807 {
1808 X86CPU *cpu = X86_CPU(obj);
1809 CPUX86State *env = &cpu->env;
1810 int c, len, i;
1811
1812 if (model_id == NULL) {
1813 model_id = "";
1814 }
1815 len = strlen(model_id);
1816 memset(env->cpuid_model, 0, 48);
1817 for (i = 0; i < 48; i++) {
1818 if (i >= len) {
1819 c = '\0';
1820 } else {
1821 c = (uint8_t)model_id[i];
1822 }
1823 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1824 }
1825 }
1826
1827 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1828 void *opaque, Error **errp)
1829 {
1830 X86CPU *cpu = X86_CPU(obj);
1831 int64_t value;
1832
1833 value = cpu->env.tsc_khz * 1000;
1834 visit_type_int(v, name, &value, errp);
1835 }
1836
1837 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1838 void *opaque, Error **errp)
1839 {
1840 X86CPU *cpu = X86_CPU(obj);
1841 const int64_t min = 0;
1842 const int64_t max = INT64_MAX;
1843 Error *local_err = NULL;
1844 int64_t value;
1845
1846 visit_type_int(v, name, &value, &local_err);
1847 if (local_err) {
1848 error_propagate(errp, local_err);
1849 return;
1850 }
1851 if (value < min || value > max) {
1852 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1853 name ? name : "null", value, min, max);
1854 return;
1855 }
1856
1857 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
1858 }
1859
1860 /* Generic getter for "feature-words" and "filtered-features" properties */
1861 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1862 const char *name, void *opaque,
1863 Error **errp)
1864 {
1865 uint32_t *array = (uint32_t *)opaque;
1866 FeatureWord w;
1867 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1868 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1869 X86CPUFeatureWordInfoList *list = NULL;
1870
1871 for (w = 0; w < FEATURE_WORDS; w++) {
1872 FeatureWordInfo *wi = &feature_word_info[w];
1873 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1874 qwi->cpuid_input_eax = wi->cpuid_eax;
1875 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1876 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1877 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1878 qwi->features = array[w];
1879
1880 /* List will be in reverse order, but order shouldn't matter */
1881 list_entries[w].next = list;
1882 list_entries[w].value = &word_infos[w];
1883 list = &list_entries[w];
1884 }
1885
1886 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
1887 }
1888
1889 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1890 void *opaque, Error **errp)
1891 {
1892 X86CPU *cpu = X86_CPU(obj);
1893 int64_t value = cpu->hyperv_spinlock_attempts;
1894
1895 visit_type_int(v, name, &value, errp);
1896 }
1897
1898 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1899 void *opaque, Error **errp)
1900 {
1901 const int64_t min = 0xFFF;
1902 const int64_t max = UINT_MAX;
1903 X86CPU *cpu = X86_CPU(obj);
1904 Error *err = NULL;
1905 int64_t value;
1906
1907 visit_type_int(v, name, &value, &err);
1908 if (err) {
1909 error_propagate(errp, err);
1910 return;
1911 }
1912
1913 if (value < min || value > max) {
1914 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1915 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1916 object_get_typename(obj), name ? name : "null",
1917 value, min, max);
1918 return;
1919 }
1920 cpu->hyperv_spinlock_attempts = value;
1921 }
1922
1923 static PropertyInfo qdev_prop_spinlocks = {
1924 .name = "int",
1925 .get = x86_get_hv_spinlocks,
1926 .set = x86_set_hv_spinlocks,
1927 };
1928
1929 /* Convert all '_' in a feature string option name to '-', to make feature
1930 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1931 */
1932 static inline void feat2prop(char *s)
1933 {
1934 while ((s = strchr(s, '_'))) {
1935 *s = '-';
1936 }
1937 }
1938
1939 /* Return the feature property name for a feature flag bit */
1940 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
1941 {
1942 /* XSAVE components are automatically enabled by other features,
1943 * so return the original feature name instead
1944 */
1945 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
1946 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
1947
1948 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
1949 x86_ext_save_areas[comp].bits) {
1950 w = x86_ext_save_areas[comp].feature;
1951 bitnr = ctz32(x86_ext_save_areas[comp].bits);
1952 }
1953 }
1954
1955 assert(bitnr < 32);
1956 assert(w < FEATURE_WORDS);
1957 return feature_word_info[w].feat_names[bitnr];
1958 }
1959
1960 /* Compatibily hack to maintain legacy +-feat semantic,
1961 * where +-feat overwrites any feature set by
1962 * feat=on|feat even if the later is parsed after +-feat
1963 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1964 */
1965 static GList *plus_features, *minus_features;
1966
1967 static gint compare_string(gconstpointer a, gconstpointer b)
1968 {
1969 return g_strcmp0(a, b);
1970 }
1971
1972 /* Parse "+feature,-feature,feature=foo" CPU feature string
1973 */
1974 static void x86_cpu_parse_featurestr(const char *typename, char *features,
1975 Error **errp)
1976 {
1977 char *featurestr; /* Single 'key=value" string being parsed */
1978 static bool cpu_globals_initialized;
1979 bool ambiguous = false;
1980
1981 if (cpu_globals_initialized) {
1982 return;
1983 }
1984 cpu_globals_initialized = true;
1985
1986 if (!features) {
1987 return;
1988 }
1989
1990 for (featurestr = strtok(features, ",");
1991 featurestr;
1992 featurestr = strtok(NULL, ",")) {
1993 const char *name;
1994 const char *val = NULL;
1995 char *eq = NULL;
1996 char num[32];
1997 GlobalProperty *prop;
1998
1999 /* Compatibility syntax: */
2000 if (featurestr[0] == '+') {
2001 plus_features = g_list_append(plus_features,
2002 g_strdup(featurestr + 1));
2003 continue;
2004 } else if (featurestr[0] == '-') {
2005 minus_features = g_list_append(minus_features,
2006 g_strdup(featurestr + 1));
2007 continue;
2008 }
2009
2010 eq = strchr(featurestr, '=');
2011 if (eq) {
2012 *eq++ = 0;
2013 val = eq;
2014 } else {
2015 val = "on";
2016 }
2017
2018 feat2prop(featurestr);
2019 name = featurestr;
2020
2021 if (g_list_find_custom(plus_features, name, compare_string)) {
2022 error_report("warning: Ambiguous CPU model string. "
2023 "Don't mix both \"+%s\" and \"%s=%s\"",
2024 name, name, val);
2025 ambiguous = true;
2026 }
2027 if (g_list_find_custom(minus_features, name, compare_string)) {
2028 error_report("warning: Ambiguous CPU model string. "
2029 "Don't mix both \"-%s\" and \"%s=%s\"",
2030 name, name, val);
2031 ambiguous = true;
2032 }
2033
2034 /* Special case: */
2035 if (!strcmp(name, "tsc-freq")) {
2036 int ret;
2037 uint64_t tsc_freq;
2038
2039 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
2040 if (ret < 0 || tsc_freq > INT64_MAX) {
2041 error_setg(errp, "bad numerical value %s", val);
2042 return;
2043 }
2044 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2045 val = num;
2046 name = "tsc-frequency";
2047 }
2048
2049 prop = g_new0(typeof(*prop), 1);
2050 prop->driver = typename;
2051 prop->property = g_strdup(name);
2052 prop->value = g_strdup(val);
2053 prop->errp = &error_fatal;
2054 qdev_prop_register_global(prop);
2055 }
2056
2057 if (ambiguous) {
2058 error_report("warning: Compatibility of ambiguous CPU model "
2059 "strings won't be kept on future QEMU versions");
2060 }
2061 }
2062
2063 static void x86_cpu_load_features(X86CPU *cpu, Error **errp);
2064 static int x86_cpu_filter_features(X86CPU *cpu);
2065
2066 /* Check for missing features that may prevent the CPU class from
2067 * running using the current machine and accelerator.
2068 */
2069 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
2070 strList **missing_feats)
2071 {
2072 X86CPU *xc;
2073 FeatureWord w;
2074 Error *err = NULL;
2075 strList **next = missing_feats;
2076
2077 if (xcc->kvm_required && !kvm_enabled()) {
2078 strList *new = g_new0(strList, 1);
2079 new->value = g_strdup("kvm");;
2080 *missing_feats = new;
2081 return;
2082 }
2083
2084 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
2085
2086 x86_cpu_load_features(xc, &err);
2087 if (err) {
2088 /* Errors at x86_cpu_load_features should never happen,
2089 * but in case it does, just report the model as not
2090 * runnable at all using the "type" property.
2091 */
2092 strList *new = g_new0(strList, 1);
2093 new->value = g_strdup("type");
2094 *next = new;
2095 next = &new->next;
2096 }
2097
2098 x86_cpu_filter_features(xc);
2099
2100 for (w = 0; w < FEATURE_WORDS; w++) {
2101 uint32_t filtered = xc->filtered_features[w];
2102 int i;
2103 for (i = 0; i < 32; i++) {
2104 if (filtered & (1UL << i)) {
2105 strList *new = g_new0(strList, 1);
2106 new->value = g_strdup(x86_cpu_feature_name(w, i));
2107 *next = new;
2108 next = &new->next;
2109 }
2110 }
2111 }
2112
2113 object_unref(OBJECT(xc));
2114 }
2115
2116 /* Print all cpuid feature names in featureset
2117 */
2118 static void listflags(FILE *f, fprintf_function print, const char **featureset)
2119 {
2120 int bit;
2121 bool first = true;
2122
2123 for (bit = 0; bit < 32; bit++) {
2124 if (featureset[bit]) {
2125 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2126 first = false;
2127 }
2128 }
2129 }
2130
2131 /* Sort alphabetically by type name, listing kvm_required models last. */
2132 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
2133 {
2134 ObjectClass *class_a = (ObjectClass *)a;
2135 ObjectClass *class_b = (ObjectClass *)b;
2136 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
2137 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
2138 const char *name_a, *name_b;
2139
2140 if (cc_a->kvm_required != cc_b->kvm_required) {
2141 /* kvm_required items go last */
2142 return cc_a->kvm_required ? 1 : -1;
2143 } else {
2144 name_a = object_class_get_name(class_a);
2145 name_b = object_class_get_name(class_b);
2146 return strcmp(name_a, name_b);
2147 }
2148 }
2149
2150 static GSList *get_sorted_cpu_model_list(void)
2151 {
2152 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
2153 list = g_slist_sort(list, x86_cpu_list_compare);
2154 return list;
2155 }
2156
2157 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
2158 {
2159 ObjectClass *oc = data;
2160 X86CPUClass *cc = X86_CPU_CLASS(oc);
2161 CPUListState *s = user_data;
2162 char *name = x86_cpu_class_get_model_name(cc);
2163 const char *desc = cc->model_description;
2164 if (!desc) {
2165 desc = cc->cpu_def->model_id;
2166 }
2167
2168 (*s->cpu_fprintf)(s->file, "x86 %16s %-48s\n",
2169 name, desc);
2170 g_free(name);
2171 }
2172
2173 /* list available CPU models and flags */
2174 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2175 {
2176 int i;
2177 CPUListState s = {
2178 .file = f,
2179 .cpu_fprintf = cpu_fprintf,
2180 };
2181 GSList *list;
2182
2183 (*cpu_fprintf)(f, "Available CPUs:\n");
2184 list = get_sorted_cpu_model_list();
2185 g_slist_foreach(list, x86_cpu_list_entry, &s);
2186 g_slist_free(list);
2187
2188 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
2189 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2190 FeatureWordInfo *fw = &feature_word_info[i];
2191
2192 (*cpu_fprintf)(f, " ");
2193 listflags(f, cpu_fprintf, fw->feat_names);
2194 (*cpu_fprintf)(f, "\n");
2195 }
2196 }
2197
2198 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
2199 {
2200 ObjectClass *oc = data;
2201 X86CPUClass *cc = X86_CPU_CLASS(oc);
2202 CpuDefinitionInfoList **cpu_list = user_data;
2203 CpuDefinitionInfoList *entry;
2204 CpuDefinitionInfo *info;
2205
2206 info = g_malloc0(sizeof(*info));
2207 info->name = x86_cpu_class_get_model_name(cc);
2208 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
2209 info->has_unavailable_features = true;
2210 info->q_typename = g_strdup(object_class_get_name(oc));
2211 info->migration_safe = cc->migration_safe;
2212 info->has_migration_safe = true;
2213
2214 entry = g_malloc0(sizeof(*entry));
2215 entry->value = info;
2216 entry->next = *cpu_list;
2217 *cpu_list = entry;
2218 }
2219
2220 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2221 {
2222 CpuDefinitionInfoList *cpu_list = NULL;
2223 GSList *list = get_sorted_cpu_model_list();
2224 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
2225 g_slist_free(list);
2226 return cpu_list;
2227 }
2228
2229 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2230 bool migratable_only)
2231 {
2232 FeatureWordInfo *wi = &feature_word_info[w];
2233 uint32_t r;
2234
2235 if (kvm_enabled()) {
2236 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2237 wi->cpuid_ecx,
2238 wi->cpuid_reg);
2239 } else if (tcg_enabled()) {
2240 r = wi->tcg_features;
2241 } else {
2242 return ~0;
2243 }
2244 if (migratable_only) {
2245 r &= x86_cpu_get_migratable_flags(w);
2246 }
2247 return r;
2248 }
2249
2250 /*
2251 * Filters CPU feature words based on host availability of each feature.
2252 *
2253 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2254 */
2255 static int x86_cpu_filter_features(X86CPU *cpu)
2256 {
2257 CPUX86State *env = &cpu->env;
2258 FeatureWord w;
2259 int rv = 0;
2260
2261 for (w = 0; w < FEATURE_WORDS; w++) {
2262 uint32_t host_feat =
2263 x86_cpu_get_supported_feature_word(w, false);
2264 uint32_t requested_features = env->features[w];
2265 env->features[w] &= host_feat;
2266 cpu->filtered_features[w] = requested_features & ~env->features[w];
2267 if (cpu->filtered_features[w]) {
2268 rv = 1;
2269 }
2270 }
2271
2272 return rv;
2273 }
2274
2275 static void x86_cpu_report_filtered_features(X86CPU *cpu)
2276 {
2277 FeatureWord w;
2278
2279 for (w = 0; w < FEATURE_WORDS; w++) {
2280 report_unavailable_features(w, cpu->filtered_features[w]);
2281 }
2282 }
2283
2284 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2285 {
2286 PropValue *pv;
2287 for (pv = props; pv->prop; pv++) {
2288 if (!pv->value) {
2289 continue;
2290 }
2291 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2292 &error_abort);
2293 }
2294 }
2295
2296 /* Load data from X86CPUDefinition
2297 */
2298 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
2299 {
2300 CPUX86State *env = &cpu->env;
2301 const char *vendor;
2302 char host_vendor[CPUID_VENDOR_SZ + 1];
2303 FeatureWord w;
2304
2305 /* CPU models only set _minimum_ values for level/xlevel: */
2306 object_property_set_int(OBJECT(cpu), def->level, "min-level", errp);
2307 object_property_set_int(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
2308
2309 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2310 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2311 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2312 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
2313 for (w = 0; w < FEATURE_WORDS; w++) {
2314 env->features[w] = def->features[w];
2315 }
2316
2317 /* Special cases not set in the X86CPUDefinition structs: */
2318 if (kvm_enabled()) {
2319 if (!kvm_irqchip_in_kernel()) {
2320 x86_cpu_change_kvm_default("x2apic", "off");
2321 }
2322
2323 x86_cpu_apply_props(cpu, kvm_default_props);
2324 } else if (tcg_enabled()) {
2325 x86_cpu_apply_props(cpu, tcg_default_props);
2326 }
2327
2328 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
2329
2330 /* sysenter isn't supported in compatibility mode on AMD,
2331 * syscall isn't supported in compatibility mode on Intel.
2332 * Normally we advertise the actual CPU vendor, but you can
2333 * override this using the 'vendor' property if you want to use
2334 * KVM's sysenter/syscall emulation in compatibility mode and
2335 * when doing cross vendor migration
2336 */
2337 vendor = def->vendor;
2338 if (kvm_enabled()) {
2339 uint32_t ebx = 0, ecx = 0, edx = 0;
2340 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2341 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2342 vendor = host_vendor;
2343 }
2344
2345 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2346
2347 }
2348
2349 X86CPU *cpu_x86_init(const char *cpu_model)
2350 {
2351 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
2352 }
2353
2354 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2355 {
2356 X86CPUDefinition *cpudef = data;
2357 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2358
2359 xcc->cpu_def = cpudef;
2360 xcc->migration_safe = true;
2361 }
2362
2363 static void x86_register_cpudef_type(X86CPUDefinition *def)
2364 {
2365 char *typename = x86_cpu_type_name(def->name);
2366 TypeInfo ti = {
2367 .name = typename,
2368 .parent = TYPE_X86_CPU,
2369 .class_init = x86_cpu_cpudef_class_init,
2370 .class_data = def,
2371 };
2372
2373 /* AMD aliases are handled at runtime based on CPUID vendor, so
2374 * they shouldn't be set on the CPU model table.
2375 */
2376 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
2377
2378 type_register(&ti);
2379 g_free(typename);
2380 }
2381
2382 #if !defined(CONFIG_USER_ONLY)
2383
2384 void cpu_clear_apic_feature(CPUX86State *env)
2385 {
2386 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2387 }
2388
2389 #endif /* !CONFIG_USER_ONLY */
2390
2391 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2392 uint32_t *eax, uint32_t *ebx,
2393 uint32_t *ecx, uint32_t *edx)
2394 {
2395 X86CPU *cpu = x86_env_get_cpu(env);
2396 CPUState *cs = CPU(cpu);
2397 uint32_t pkg_offset;
2398
2399 /* test if maximum index reached */
2400 if (index & 0x80000000) {
2401 if (index > env->cpuid_xlevel) {
2402 if (env->cpuid_xlevel2 > 0) {
2403 /* Handle the Centaur's CPUID instruction. */
2404 if (index > env->cpuid_xlevel2) {
2405 index = env->cpuid_xlevel2;
2406 } else if (index < 0xC0000000) {
2407 index = env->cpuid_xlevel;
2408 }
2409 } else {
2410 /* Intel documentation states that invalid EAX input will
2411 * return the same information as EAX=cpuid_level
2412 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2413 */
2414 index = env->cpuid_level;
2415 }
2416 }
2417 } else {
2418 if (index > env->cpuid_level)
2419 index = env->cpuid_level;
2420 }
2421
2422 switch(index) {
2423 case 0:
2424 *eax = env->cpuid_level;
2425 *ebx = env->cpuid_vendor1;
2426 *edx = env->cpuid_vendor2;
2427 *ecx = env->cpuid_vendor3;
2428 break;
2429 case 1:
2430 *eax = env->cpuid_version;
2431 *ebx = (cpu->apic_id << 24) |
2432 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2433 *ecx = env->features[FEAT_1_ECX];
2434 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2435 *ecx |= CPUID_EXT_OSXSAVE;
2436 }
2437 *edx = env->features[FEAT_1_EDX];
2438 if (cs->nr_cores * cs->nr_threads > 1) {
2439 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2440 *edx |= CPUID_HT;
2441 }
2442 break;
2443 case 2:
2444 /* cache info: needed for Pentium Pro compatibility */
2445 if (cpu->cache_info_passthrough) {
2446 host_cpuid(index, 0, eax, ebx, ecx, edx);
2447 break;
2448 }
2449 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2450 *ebx = 0;
2451 if (!cpu->enable_l3_cache) {
2452 *ecx = 0;
2453 } else {
2454 *ecx = L3_N_DESCRIPTOR;
2455 }
2456 *edx = (L1D_DESCRIPTOR << 16) | \
2457 (L1I_DESCRIPTOR << 8) | \
2458 (L2_DESCRIPTOR);
2459 break;
2460 case 4:
2461 /* cache info: needed for Core compatibility */
2462 if (cpu->cache_info_passthrough) {
2463 host_cpuid(index, count, eax, ebx, ecx, edx);
2464 *eax &= ~0xFC000000;
2465 } else {
2466 *eax = 0;
2467 switch (count) {
2468 case 0: /* L1 dcache info */
2469 *eax |= CPUID_4_TYPE_DCACHE | \
2470 CPUID_4_LEVEL(1) | \
2471 CPUID_4_SELF_INIT_LEVEL;
2472 *ebx = (L1D_LINE_SIZE - 1) | \
2473 ((L1D_PARTITIONS - 1) << 12) | \
2474 ((L1D_ASSOCIATIVITY - 1) << 22);
2475 *ecx = L1D_SETS - 1;
2476 *edx = CPUID_4_NO_INVD_SHARING;
2477 break;
2478 case 1: /* L1 icache info */
2479 *eax |= CPUID_4_TYPE_ICACHE | \
2480 CPUID_4_LEVEL(1) | \
2481 CPUID_4_SELF_INIT_LEVEL;
2482 *ebx = (L1I_LINE_SIZE - 1) | \
2483 ((L1I_PARTITIONS - 1) << 12) | \
2484 ((L1I_ASSOCIATIVITY - 1) << 22);
2485 *ecx = L1I_SETS - 1;
2486 *edx = CPUID_4_NO_INVD_SHARING;
2487 break;
2488 case 2: /* L2 cache info */
2489 *eax |= CPUID_4_TYPE_UNIFIED | \
2490 CPUID_4_LEVEL(2) | \
2491 CPUID_4_SELF_INIT_LEVEL;
2492 if (cs->nr_threads > 1) {
2493 *eax |= (cs->nr_threads - 1) << 14;
2494 }
2495 *ebx = (L2_LINE_SIZE - 1) | \
2496 ((L2_PARTITIONS - 1) << 12) | \
2497 ((L2_ASSOCIATIVITY - 1) << 22);
2498 *ecx = L2_SETS - 1;
2499 *edx = CPUID_4_NO_INVD_SHARING;
2500 break;
2501 case 3: /* L3 cache info */
2502 if (!cpu->enable_l3_cache) {
2503 *eax = 0;
2504 *ebx = 0;
2505 *ecx = 0;
2506 *edx = 0;
2507 break;
2508 }
2509 *eax |= CPUID_4_TYPE_UNIFIED | \
2510 CPUID_4_LEVEL(3) | \
2511 CPUID_4_SELF_INIT_LEVEL;
2512 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2513 *eax |= ((1 << pkg_offset) - 1) << 14;
2514 *ebx = (L3_N_LINE_SIZE - 1) | \
2515 ((L3_N_PARTITIONS - 1) << 12) | \
2516 ((L3_N_ASSOCIATIVITY - 1) << 22);
2517 *ecx = L3_N_SETS - 1;
2518 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2519 break;
2520 default: /* end of info */
2521 *eax = 0;
2522 *ebx = 0;
2523 *ecx = 0;
2524 *edx = 0;
2525 break;
2526 }
2527 }
2528
2529 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2530 if ((*eax & 31) && cs->nr_cores > 1) {
2531 *eax |= (cs->nr_cores - 1) << 26;
2532 }
2533 break;
2534 case 5:
2535 /* mwait info: needed for Core compatibility */
2536 *eax = 0; /* Smallest monitor-line size in bytes */
2537 *ebx = 0; /* Largest monitor-line size in bytes */
2538 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2539 *edx = 0;
2540 break;
2541 case 6:
2542 /* Thermal and Power Leaf */
2543 *eax = env->features[FEAT_6_EAX];
2544 *ebx = 0;
2545 *ecx = 0;
2546 *edx = 0;
2547 break;
2548 case 7:
2549 /* Structured Extended Feature Flags Enumeration Leaf */
2550 if (count == 0) {
2551 *eax = 0; /* Maximum ECX value for sub-leaves */
2552 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2553 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
2554 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2555 *ecx |= CPUID_7_0_ECX_OSPKE;
2556 }
2557 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
2558 } else {
2559 *eax = 0;
2560 *ebx = 0;
2561 *ecx = 0;
2562 *edx = 0;
2563 }
2564 break;
2565 case 9:
2566 /* Direct Cache Access Information Leaf */
2567 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2568 *ebx = 0;
2569 *ecx = 0;
2570 *edx = 0;
2571 break;
2572 case 0xA:
2573 /* Architectural Performance Monitoring Leaf */
2574 if (kvm_enabled() && cpu->enable_pmu) {
2575 KVMState *s = cs->kvm_state;
2576
2577 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2578 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2579 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2580 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2581 } else {
2582 *eax = 0;
2583 *ebx = 0;
2584 *ecx = 0;
2585 *edx = 0;
2586 }
2587 break;
2588 case 0xB:
2589 /* Extended Topology Enumeration Leaf */
2590 if (!cpu->enable_cpuid_0xb) {
2591 *eax = *ebx = *ecx = *edx = 0;
2592 break;
2593 }
2594
2595 *ecx = count & 0xff;
2596 *edx = cpu->apic_id;
2597
2598 switch (count) {
2599 case 0:
2600 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
2601 *ebx = cs->nr_threads;
2602 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2603 break;
2604 case 1:
2605 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2606 *ebx = cs->nr_cores * cs->nr_threads;
2607 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2608 break;
2609 default:
2610 *eax = 0;
2611 *ebx = 0;
2612 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2613 }
2614
2615 assert(!(*eax & ~0x1f));
2616 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2617 break;
2618 case 0xD: {
2619 /* Processor Extended State */
2620 *eax = 0;
2621 *ebx = 0;
2622 *ecx = 0;
2623 *edx = 0;
2624 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
2625 break;
2626 }
2627
2628 if (count == 0) {
2629 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
2630 *eax = env->features[FEAT_XSAVE_COMP_LO];
2631 *edx = env->features[FEAT_XSAVE_COMP_HI];
2632 *ebx = *ecx;
2633 } else if (count == 1) {
2634 *eax = env->features[FEAT_XSAVE];
2635 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2636 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
2637 const ExtSaveArea *esa = &x86_ext_save_areas[count];
2638 *eax = esa->size;
2639 *ebx = esa->offset;
2640 }
2641 }
2642 break;
2643 }
2644 case 0x80000000:
2645 *eax = env->cpuid_xlevel;
2646 *ebx = env->cpuid_vendor1;
2647 *edx = env->cpuid_vendor2;
2648 *ecx = env->cpuid_vendor3;
2649 break;
2650 case 0x80000001:
2651 *eax = env->cpuid_version;
2652 *ebx = 0;
2653 *ecx = env->features[FEAT_8000_0001_ECX];
2654 *edx = env->features[FEAT_8000_0001_EDX];
2655
2656 /* The Linux kernel checks for the CMPLegacy bit and
2657 * discards multiple thread information if it is set.
2658 * So don't set it here for Intel to make Linux guests happy.
2659 */
2660 if (cs->nr_cores * cs->nr_threads > 1) {
2661 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2662 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2663 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
2664 *ecx |= 1 << 1; /* CmpLegacy bit */
2665 }
2666 }
2667 break;
2668 case 0x80000002:
2669 case 0x80000003:
2670 case 0x80000004:
2671 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2672 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2673 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2674 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2675 break;
2676 case 0x80000005:
2677 /* cache info (L1 cache) */
2678 if (cpu->cache_info_passthrough) {
2679 host_cpuid(index, 0, eax, ebx, ecx, edx);
2680 break;
2681 }
2682 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2683 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2684 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2685 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2686 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2687 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2688 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2689 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2690 break;
2691 case 0x80000006:
2692 /* cache info (L2 cache) */
2693 if (cpu->cache_info_passthrough) {
2694 host_cpuid(index, 0, eax, ebx, ecx, edx);
2695 break;
2696 }
2697 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2698 (L2_DTLB_2M_ENTRIES << 16) | \
2699 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2700 (L2_ITLB_2M_ENTRIES);
2701 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2702 (L2_DTLB_4K_ENTRIES << 16) | \
2703 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2704 (L2_ITLB_4K_ENTRIES);
2705 *ecx = (L2_SIZE_KB_AMD << 16) | \
2706 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2707 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2708 if (!cpu->enable_l3_cache) {
2709 *edx = ((L3_SIZE_KB / 512) << 18) | \
2710 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2711 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2712 } else {
2713 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2714 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2715 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2716 }
2717 break;
2718 case 0x80000007:
2719 *eax = 0;
2720 *ebx = 0;
2721 *ecx = 0;
2722 *edx = env->features[FEAT_8000_0007_EDX];
2723 break;
2724 case 0x80000008:
2725 /* virtual & phys address size in low 2 bytes. */
2726 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2727 /* 64 bit processor */
2728 *eax = cpu->phys_bits; /* configurable physical bits */
2729 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
2730 *eax |= 0x00003900; /* 57 bits virtual */
2731 } else {
2732 *eax |= 0x00003000; /* 48 bits virtual */
2733 }
2734 } else {
2735 *eax = cpu->phys_bits;
2736 }
2737 *ebx = 0;
2738 *ecx = 0;
2739 *edx = 0;
2740 if (cs->nr_cores * cs->nr_threads > 1) {
2741 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2742 }
2743 break;
2744 case 0x8000000A:
2745 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2746 *eax = 0x00000001; /* SVM Revision */
2747 *ebx = 0x00000010; /* nr of ASIDs */
2748 *ecx = 0;
2749 *edx = env->features[FEAT_SVM]; /* optional features */
2750 } else {
2751 *eax = 0;
2752 *ebx = 0;
2753 *ecx = 0;
2754 *edx = 0;
2755 }
2756 break;
2757 case 0xC0000000:
2758 *eax = env->cpuid_xlevel2;
2759 *ebx = 0;
2760 *ecx = 0;
2761 *edx = 0;
2762 break;
2763 case 0xC0000001:
2764 /* Support for VIA CPU's CPUID instruction */
2765 *eax = env->cpuid_version;
2766 *ebx = 0;
2767 *ecx = 0;
2768 *edx = env->features[FEAT_C000_0001_EDX];
2769 break;
2770 case 0xC0000002:
2771 case 0xC0000003:
2772 case 0xC0000004:
2773 /* Reserved for the future, and now filled with zero */
2774 *eax = 0;
2775 *ebx = 0;
2776 *ecx = 0;
2777 *edx = 0;
2778 break;
2779 default:
2780 /* reserved values: zero */
2781 *eax = 0;
2782 *ebx = 0;
2783 *ecx = 0;
2784 *edx = 0;
2785 break;
2786 }
2787 }
2788
2789 /* CPUClass::reset() */
2790 static void x86_cpu_reset(CPUState *s)
2791 {
2792 X86CPU *cpu = X86_CPU(s);
2793 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2794 CPUX86State *env = &cpu->env;
2795 target_ulong cr4;
2796 uint64_t xcr0;
2797 int i;
2798
2799 xcc->parent_reset(s);
2800
2801 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
2802
2803 env->old_exception = -1;
2804
2805 /* init to reset state */
2806
2807 env->hflags2 |= HF2_GIF_MASK;
2808
2809 cpu_x86_update_cr0(env, 0x60000010);
2810 env->a20_mask = ~0x0;
2811 env->smbase = 0x30000;
2812
2813 env->idt.limit = 0xffff;
2814 env->gdt.limit = 0xffff;
2815 env->ldt.limit = 0xffff;
2816 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2817 env->tr.limit = 0xffff;
2818 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2819
2820 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2821 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2822 DESC_R_MASK | DESC_A_MASK);
2823 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2824 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2825 DESC_A_MASK);
2826 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2827 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2828 DESC_A_MASK);
2829 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2830 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2831 DESC_A_MASK);
2832 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2833 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2834 DESC_A_MASK);
2835 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2836 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2837 DESC_A_MASK);
2838
2839 env->eip = 0xfff0;
2840 env->regs[R_EDX] = env->cpuid_version;
2841
2842 env->eflags = 0x2;
2843
2844 /* FPU init */
2845 for (i = 0; i < 8; i++) {
2846 env->fptags[i] = 1;
2847 }
2848 cpu_set_fpuc(env, 0x37f);
2849
2850 env->mxcsr = 0x1f80;
2851 /* All units are in INIT state. */
2852 env->xstate_bv = 0;
2853
2854 env->pat = 0x0007040600070406ULL;
2855 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2856
2857 memset(env->dr, 0, sizeof(env->dr));
2858 env->dr[6] = DR6_FIXED_1;
2859 env->dr[7] = DR7_FIXED_1;
2860 cpu_breakpoint_remove_all(s, BP_CPU);
2861 cpu_watchpoint_remove_all(s, BP_CPU);
2862
2863 cr4 = 0;
2864 xcr0 = XSTATE_FP_MASK;
2865
2866 #ifdef CONFIG_USER_ONLY
2867 /* Enable all the features for user-mode. */
2868 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
2869 xcr0 |= XSTATE_SSE_MASK;
2870 }
2871 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2872 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2873 if (env->features[esa->feature] & esa->bits) {
2874 xcr0 |= 1ull << i;
2875 }
2876 }
2877
2878 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2879 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2880 }
2881 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2882 cr4 |= CR4_FSGSBASE_MASK;
2883 }
2884 #endif
2885
2886 env->xcr0 = xcr0;
2887 cpu_x86_update_cr4(env, cr4);
2888
2889 /*
2890 * SDM 11.11.5 requires:
2891 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2892 * - IA32_MTRR_PHYSMASKn.V = 0
2893 * All other bits are undefined. For simplification, zero it all.
2894 */
2895 env->mtrr_deftype = 0;
2896 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2897 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2898
2899 #if !defined(CONFIG_USER_ONLY)
2900 /* We hard-wire the BSP to the first CPU. */
2901 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
2902
2903 s->halted = !cpu_is_bsp(cpu);
2904
2905 if (kvm_enabled()) {
2906 kvm_arch_reset_vcpu(cpu);
2907 }
2908 #endif
2909 }
2910
2911 #ifndef CONFIG_USER_ONLY
2912 bool cpu_is_bsp(X86CPU *cpu)
2913 {
2914 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2915 }
2916
2917 /* TODO: remove me, when reset over QOM tree is implemented */
2918 static void x86_cpu_machine_reset_cb(void *opaque)
2919 {
2920 X86CPU *cpu = opaque;
2921 cpu_reset(CPU(cpu));
2922 }
2923 #endif
2924
2925 static void mce_init(X86CPU *cpu)
2926 {
2927 CPUX86State *cenv = &cpu->env;
2928 unsigned int bank;
2929
2930 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2931 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2932 (CPUID_MCE | CPUID_MCA)) {
2933 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2934 (cpu->enable_lmce ? MCG_LMCE_P : 0);
2935 cenv->mcg_ctl = ~(uint64_t)0;
2936 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2937 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2938 }
2939 }
2940 }
2941
2942 #ifndef CONFIG_USER_ONLY
2943 APICCommonClass *apic_get_class(void)
2944 {
2945 const char *apic_type = "apic";
2946
2947 if (kvm_apic_in_kernel()) {
2948 apic_type = "kvm-apic";
2949 } else if (xen_enabled()) {
2950 apic_type = "xen-apic";
2951 }
2952
2953 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
2954 }
2955
2956 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2957 {
2958 APICCommonState *apic;
2959 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
2960
2961 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
2962
2963 object_property_add_child(OBJECT(cpu), "lapic",
2964 OBJECT(cpu->apic_state), &error_abort);
2965 object_unref(OBJECT(cpu->apic_state));
2966
2967 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
2968 /* TODO: convert to link<> */
2969 apic = APIC_COMMON(cpu->apic_state);
2970 apic->cpu = cpu;
2971 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
2972 }
2973
2974 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2975 {
2976 APICCommonState *apic;
2977 static bool apic_mmio_map_once;
2978
2979 if (cpu->apic_state == NULL) {
2980 return;
2981 }
2982 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2983 errp);
2984
2985 /* Map APIC MMIO area */
2986 apic = APIC_COMMON(cpu->apic_state);
2987 if (!apic_mmio_map_once) {
2988 memory_region_add_subregion_overlap(get_system_memory(),
2989 apic->apicbase &
2990 MSR_IA32_APICBASE_BASE,
2991 &apic->io_memory,
2992 0x1000);
2993 apic_mmio_map_once = true;
2994 }
2995 }
2996
2997 static void x86_cpu_machine_done(Notifier *n, void *unused)
2998 {
2999 X86CPU *cpu = container_of(n, X86CPU, machine_done);
3000 MemoryRegion *smram =
3001 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
3002
3003 if (smram) {
3004 cpu->smram = g_new(MemoryRegion, 1);
3005 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
3006 smram, 0, 1ull << 32);
3007 memory_region_set_enabled(cpu->smram, false);
3008 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
3009 }
3010 }
3011 #else
3012 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
3013 {
3014 }
3015 #endif
3016
3017 /* Note: Only safe for use on x86(-64) hosts */
3018 static uint32_t x86_host_phys_bits(void)
3019 {
3020 uint32_t eax;
3021 uint32_t host_phys_bits;
3022
3023 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
3024 if (eax >= 0x80000008) {
3025 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
3026 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3027 * at 23:16 that can specify a maximum physical address bits for
3028 * the guest that can override this value; but I've not seen
3029 * anything with that set.
3030 */
3031 host_phys_bits = eax & 0xff;
3032 } else {
3033 /* It's an odd 64 bit machine that doesn't have the leaf for
3034 * physical address bits; fall back to 36 that's most older
3035 * Intel.
3036 */
3037 host_phys_bits = 36;
3038 }
3039
3040 return host_phys_bits;
3041 }
3042
3043 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
3044 {
3045 if (*min < value) {
3046 *min = value;
3047 }
3048 }
3049
3050 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3051 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
3052 {
3053 CPUX86State *env = &cpu->env;
3054 FeatureWordInfo *fi = &feature_word_info[w];
3055 uint32_t eax = fi->cpuid_eax;
3056 uint32_t region = eax & 0xF0000000;
3057
3058 if (!env->features[w]) {
3059 return;
3060 }
3061
3062 switch (region) {
3063 case 0x00000000:
3064 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
3065 break;
3066 case 0x80000000:
3067 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
3068 break;
3069 case 0xC0000000:
3070 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
3071 break;
3072 }
3073 }
3074
3075 /* Calculate XSAVE components based on the configured CPU feature flags */
3076 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
3077 {
3078 CPUX86State *env = &cpu->env;
3079 int i;
3080 uint64_t mask;
3081
3082 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
3083 return;
3084 }
3085
3086 mask = 0;
3087 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
3088 const ExtSaveArea *esa = &x86_ext_save_areas[i];
3089 if (env->features[esa->feature] & esa->bits) {
3090 mask |= (1ULL << i);
3091 }
3092 }
3093
3094 env->features[FEAT_XSAVE_COMP_LO] = mask;
3095 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
3096 }
3097
3098 /* Load CPUID data based on configured features */
3099 static void x86_cpu_load_features(X86CPU *cpu, Error **errp)
3100 {
3101 CPUX86State *env = &cpu->env;
3102 FeatureWord w;
3103 GList *l;
3104 Error *local_err = NULL;
3105
3106 /*TODO: cpu->host_features incorrectly overwrites features
3107 * set using "feat=on|off". Once we fix this, we can convert
3108 * plus_features & minus_features to global properties
3109 * inside x86_cpu_parse_featurestr() too.
3110 */
3111 if (cpu->host_features) {
3112 for (w = 0; w < FEATURE_WORDS; w++) {
3113 env->features[w] =
3114 x86_cpu_get_supported_feature_word(w, cpu->migratable);
3115 }
3116 }
3117
3118 for (l = plus_features; l; l = l->next) {
3119 const char *prop = l->data;
3120 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
3121 if (local_err) {
3122 goto out;
3123 }
3124 }
3125
3126 for (l = minus_features; l; l = l->next) {
3127 const char *prop = l->data;
3128 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
3129 if (local_err) {
3130 goto out;
3131 }
3132 }
3133
3134 if (!kvm_enabled() || !cpu->expose_kvm) {
3135 env->features[FEAT_KVM] = 0;
3136 }
3137
3138 x86_cpu_enable_xsave_components(cpu);
3139
3140 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3141 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
3142 if (cpu->full_cpuid_auto_level) {
3143 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
3144 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
3145 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
3146 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
3147 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
3148 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
3149 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
3150 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
3151 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
3152 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
3153 /* SVM requires CPUID[0x8000000A] */
3154 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
3155 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
3156 }
3157 }
3158
3159 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3160 if (env->cpuid_level == UINT32_MAX) {
3161 env->cpuid_level = env->cpuid_min_level;
3162 }
3163 if (env->cpuid_xlevel == UINT32_MAX) {
3164 env->cpuid_xlevel = env->cpuid_min_xlevel;
3165 }
3166 if (env->cpuid_xlevel2 == UINT32_MAX) {
3167 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
3168 }
3169
3170 out:
3171 if (local_err != NULL) {
3172 error_propagate(errp, local_err);
3173 }
3174 }
3175
3176 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3177 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3178 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3179 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3180 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3181 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3182 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
3183 {
3184 CPUState *cs = CPU(dev);
3185 X86CPU *cpu = X86_CPU(dev);
3186 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3187 CPUX86State *env = &cpu->env;
3188 Error *local_err = NULL;
3189 static bool ht_warned;
3190
3191 if (xcc->kvm_required && !kvm_enabled()) {
3192 char *name = x86_cpu_class_get_model_name(xcc);
3193 error_setg(&local_err, "CPU model '%s' requires KVM", name);
3194 g_free(name);
3195 goto out;
3196 }
3197
3198 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
3199 error_setg(errp, "apic-id property was not initialized properly");
3200 return;
3201 }
3202
3203 x86_cpu_load_features(cpu, &local_err);
3204 if (local_err) {
3205 goto out;
3206 }
3207
3208 if (x86_cpu_filter_features(cpu) &&
3209 (cpu->check_cpuid || cpu->enforce_cpuid)) {
3210 x86_cpu_report_filtered_features(cpu);
3211 if (cpu->enforce_cpuid) {
3212 error_setg(&local_err,
3213 kvm_enabled() ?
3214 "Host doesn't support requested features" :
3215 "TCG doesn't support requested features");
3216 goto out;
3217 }
3218 }
3219
3220 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3221 * CPUID[1].EDX.
3222 */
3223 if (IS_AMD_CPU(env)) {
3224 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3225 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
3226 & CPUID_EXT2_AMD_ALIASES);
3227 }
3228
3229 /* For 64bit systems think about the number of physical bits to present.
3230 * ideally this should be the same as the host; anything other than matching
3231 * the host can cause incorrect guest behaviour.
3232 * QEMU used to pick the magic value of 40 bits that corresponds to
3233 * consumer AMD devices but nothing else.
3234 */
3235 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
3236 if (kvm_enabled()) {
3237 uint32_t host_phys_bits = x86_host_phys_bits();
3238 static bool warned;
3239
3240 if (cpu->host_phys_bits) {
3241 /* The user asked for us to use the host physical bits */
3242 cpu->phys_bits = host_phys_bits;
3243 }
3244
3245 /* Print a warning if the user set it to a value that's not the
3246 * host value.
3247 */
3248 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3249 !warned) {
3250 error_report("Warning: Host physical bits (%u)"
3251 " does not match phys-bits property (%u)",
3252 host_phys_bits, cpu->phys_bits);
3253 warned = true;
3254 }
3255
3256 if (cpu->phys_bits &&
3257 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3258 cpu->phys_bits < 32)) {
3259 error_setg(errp, "phys-bits should be between 32 and %u "
3260 " (but is %u)",
3261 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3262 return;
3263 }
3264 } else {
3265 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
3266 error_setg(errp, "TCG only supports phys-bits=%u",
3267 TCG_PHYS_ADDR_BITS);
3268 return;
3269 }
3270 }
3271 /* 0 means it was not explicitly set by the user (or by machine
3272 * compat_props or by the host code above). In this case, the default
3273 * is the value used by TCG (40).
3274 */
3275 if (cpu->phys_bits == 0) {
3276 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3277 }
3278 } else {
3279 /* For 32 bit systems don't use the user set value, but keep
3280 * phys_bits consistent with what we tell the guest.
3281 */
3282 if (cpu->phys_bits != 0) {
3283 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3284 return;
3285 }
3286
3287 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3288 cpu->phys_bits = 36;
3289 } else {
3290 cpu->phys_bits = 32;
3291 }
3292 }
3293 cpu_exec_realizefn(cs, &local_err);
3294 if (local_err != NULL) {
3295 error_propagate(errp, local_err);
3296 return;
3297 }
3298
3299 if (tcg_enabled()) {
3300 tcg_x86_init();
3301 }
3302
3303 #ifndef CONFIG_USER_ONLY
3304 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
3305
3306 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
3307 x86_cpu_apic_create(cpu, &local_err);
3308 if (local_err != NULL) {
3309 goto out;
3310 }
3311 }
3312 #endif
3313
3314 mce_init(cpu);
3315
3316 #ifndef CONFIG_USER_ONLY
3317 if (tcg_enabled()) {
3318 AddressSpace *newas = g_new(AddressSpace, 1);
3319
3320 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
3321 cpu->cpu_as_root = g_new(MemoryRegion, 1);
3322
3323 /* Outer container... */
3324 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
3325 memory_region_set_enabled(cpu->cpu_as_root, true);
3326
3327 /* ... with two regions inside: normal system memory with low
3328 * priority, and...
3329 */
3330 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3331 get_system_memory(), 0, ~0ull);
3332 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3333 memory_region_set_enabled(cpu->cpu_as_mem, true);
3334 address_space_init(newas, cpu->cpu_as_root, "CPU");
3335 cs->num_ases = 1;
3336 cpu_address_space_init(cs, newas, 0);
3337
3338 /* ... SMRAM with higher priority, linked from /machine/smram. */
3339 cpu->machine_done.notify = x86_cpu_machine_done;
3340 qemu_add_machine_init_done_notifier(&cpu->machine_done);
3341 }
3342 #endif
3343
3344 qemu_init_vcpu(cs);
3345
3346 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3347 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3348 * based on inputs (sockets,cores,threads), it is still better to gives
3349 * users a warning.
3350 *
3351 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3352 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3353 */
3354 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3355 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3356 " -smp options properly.");
3357 ht_warned = true;
3358 }
3359
3360 x86_cpu_apic_realize(cpu, &local_err);
3361 if (local_err != NULL) {
3362 goto out;
3363 }
3364 cpu_reset(cs);
3365
3366 xcc->parent_realize(dev, &local_err);
3367
3368 out:
3369 if (local_err != NULL) {
3370 error_propagate(errp, local_err);
3371 return;
3372 }
3373 }
3374
3375 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3376 {
3377 X86CPU *cpu = X86_CPU(dev);
3378 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
3379 Error *local_err = NULL;
3380
3381 #ifndef CONFIG_USER_ONLY
3382 cpu_remove_sync(CPU(dev));
3383 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3384 #endif
3385
3386 if (cpu->apic_state) {
3387 object_unparent(OBJECT(cpu->apic_state));
3388 cpu->apic_state = NULL;
3389 }
3390
3391 xcc->parent_unrealize(dev, &local_err);
3392 if (local_err != NULL) {
3393 error_propagate(errp, local_err);
3394 return;
3395 }
3396 }
3397
3398 typedef struct BitProperty {
3399 uint32_t *ptr;
3400 uint32_t mask;
3401 } BitProperty;
3402
3403 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3404 void *opaque, Error **errp)
3405 {
3406 BitProperty *fp = opaque;
3407 bool value = (*fp->ptr & fp->mask) == fp->mask;
3408 visit_type_bool(v, name, &value, errp);
3409 }
3410
3411 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3412 void *opaque, Error **errp)
3413 {
3414 DeviceState *dev = DEVICE(obj);
3415 BitProperty *fp = opaque;
3416 Error *local_err = NULL;
3417 bool value;
3418
3419 if (dev->realized) {
3420 qdev_prop_set_after_realize(dev, name, errp);
3421 return;
3422 }
3423
3424 visit_type_bool(v, name, &value, &local_err);
3425 if (local_err) {
3426 error_propagate(errp, local_err);
3427 return;
3428 }
3429
3430 if (value) {
3431 *fp->ptr |= fp->mask;
3432 } else {
3433 *fp->ptr &= ~fp->mask;
3434 }
3435 }
3436
3437 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3438 void *opaque)
3439 {
3440 BitProperty *prop = opaque;
3441 g_free(prop);
3442 }
3443
3444 /* Register a boolean property to get/set a single bit in a uint32_t field.
3445 *
3446 * The same property name can be registered multiple times to make it affect
3447 * multiple bits in the same FeatureWord. In that case, the getter will return
3448 * true only if all bits are set.
3449 */
3450 static void x86_cpu_register_bit_prop(X86CPU *cpu,
3451 const char *prop_name,
3452 uint32_t *field,
3453 int bitnr)
3454 {
3455 BitProperty *fp;
3456 ObjectProperty *op;
3457 uint32_t mask = (1UL << bitnr);
3458
3459 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3460 if (op) {
3461 fp = op->opaque;
3462 assert(fp->ptr == field);
3463 fp->mask |= mask;
3464 } else {
3465 fp = g_new0(BitProperty, 1);
3466 fp->ptr = field;
3467 fp->mask = mask;
3468 object_property_add(OBJECT(cpu), prop_name, "bool",
3469 x86_cpu_get_bit_prop,
3470 x86_cpu_set_bit_prop,
3471 x86_cpu_release_bit_prop, fp, &error_abort);
3472 }
3473 }
3474
3475 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3476 FeatureWord w,
3477 int bitnr)
3478 {
3479 FeatureWordInfo *fi = &feature_word_info[w];
3480 const char *name = fi->feat_names[bitnr];
3481
3482 if (!name) {
3483 return;
3484 }
3485
3486 /* Property names should use "-" instead of "_".
3487 * Old names containing underscores are registered as aliases
3488 * using object_property_add_alias()
3489 */
3490 assert(!strchr(name, '_'));
3491 /* aliases don't use "|" delimiters anymore, they are registered
3492 * manually using object_property_add_alias() */
3493 assert(!strchr(name, '|'));
3494 x86_cpu_register_bit_prop(cpu, name, &cpu->env.features[w], bitnr);
3495 }
3496
3497 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
3498 {
3499 X86CPU *cpu = X86_CPU(cs);
3500 CPUX86State *env = &cpu->env;
3501 GuestPanicInformation *panic_info = NULL;
3502
3503 if (env->features[FEAT_HYPERV_EDX] & HV_X64_GUEST_CRASH_MSR_AVAILABLE) {
3504 GuestPanicInformationHyperV *panic_info_hv =
3505 g_malloc0(sizeof(GuestPanicInformationHyperV));
3506 panic_info = g_malloc0(sizeof(GuestPanicInformation));
3507
3508 panic_info->type = GUEST_PANIC_INFORMATION_KIND_HYPER_V;
3509 panic_info->u.hyper_v.data = panic_info_hv;
3510
3511 assert(HV_X64_MSR_CRASH_PARAMS >= 5);
3512 panic_info_hv->arg1 = env->msr_hv_crash_params[0];
3513 panic_info_hv->arg2 = env->msr_hv_crash_params[1];
3514 panic_info_hv->arg3 = env->msr_hv_crash_params[2];
3515 panic_info_hv->arg4 = env->msr_hv_crash_params[3];
3516 panic_info_hv->arg5 = env->msr_hv_crash_params[4];
3517 }
3518
3519 return panic_info;
3520 }
3521 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
3522 const char *name, void *opaque,
3523 Error **errp)
3524 {
3525 CPUState *cs = CPU(obj);
3526 GuestPanicInformation *panic_info;
3527
3528 if (!cs->crash_occurred) {
3529 error_setg(errp, "No crash occured");
3530 return;
3531 }
3532
3533 panic_info = x86_cpu_get_crash_info(cs);
3534 if (panic_info == NULL) {
3535 error_setg(errp, "No crash information");
3536 return;
3537 }
3538
3539 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
3540 errp);
3541 qapi_free_GuestPanicInformation(panic_info);
3542 }
3543
3544 static void x86_cpu_initfn(Object *obj)
3545 {
3546 CPUState *cs = CPU(obj);
3547 X86CPU *cpu = X86_CPU(obj);
3548 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
3549 CPUX86State *env = &cpu->env;
3550 FeatureWord w;
3551
3552 cs->env_ptr = env;
3553
3554 object_property_add(obj, "family", "int",
3555 x86_cpuid_version_get_family,
3556 x86_cpuid_version_set_family, NULL, NULL, NULL);
3557 object_property_add(obj, "model", "int",
3558 x86_cpuid_version_get_model,
3559 x86_cpuid_version_set_model, NULL, NULL, NULL);
3560 object_property_add(obj, "stepping", "int",
3561 x86_cpuid_version_get_stepping,
3562 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
3563 object_property_add_str(obj, "vendor",
3564 x86_cpuid_get_vendor,
3565 x86_cpuid_set_vendor, NULL);
3566 object_property_add_str(obj, "model-id",
3567 x86_cpuid_get_model_id,
3568 x86_cpuid_set_model_id, NULL);
3569 object_property_add(obj, "tsc-frequency", "int",
3570 x86_cpuid_get_tsc_freq,
3571 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
3572 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3573 x86_cpu_get_feature_words,
3574 NULL, NULL, (void *)env->features, NULL);
3575 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3576 x86_cpu_get_feature_words,
3577 NULL, NULL, (void *)cpu->filtered_features, NULL);
3578
3579 object_property_add(obj, "crash-information", "GuestPanicInformation",
3580 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
3581
3582 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
3583
3584 for (w = 0; w < FEATURE_WORDS; w++) {
3585 int bitnr;
3586
3587 for (bitnr = 0; bitnr < 32; bitnr++) {
3588 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3589 }
3590 }
3591
3592 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
3593 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
3594 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
3595 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
3596 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
3597 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
3598 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
3599
3600 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
3601 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
3602 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
3603 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
3604 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
3605 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
3606 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
3607 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
3608 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
3609 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
3610 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
3611 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
3612 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
3613 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
3614 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
3615 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
3616 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
3617 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
3618 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
3619 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
3620 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
3621
3622 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3623 }
3624
3625 static int64_t x86_cpu_get_arch_id(CPUState *cs)
3626 {
3627 X86CPU *cpu = X86_CPU(cs);
3628
3629 return cpu->apic_id;
3630 }
3631
3632 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3633 {
3634 X86CPU *cpu = X86_CPU(cs);
3635
3636 return cpu->env.cr[0] & CR0_PG_MASK;
3637 }
3638
3639 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3640 {
3641 X86CPU *cpu = X86_CPU(cs);
3642
3643 cpu->env.eip = value;
3644 }
3645
3646 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3647 {
3648 X86CPU *cpu = X86_CPU(cs);
3649
3650 cpu->env.eip = tb->pc - tb->cs_base;
3651 }
3652
3653 static bool x86_cpu_has_work(CPUState *cs)
3654 {
3655 X86CPU *cpu = X86_CPU(cs);
3656 CPUX86State *env = &cpu->env;
3657
3658 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3659 CPU_INTERRUPT_POLL)) &&
3660 (env->eflags & IF_MASK)) ||
3661 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3662 CPU_INTERRUPT_INIT |
3663 CPU_INTERRUPT_SIPI |
3664 CPU_INTERRUPT_MCE)) ||
3665 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3666 !(env->hflags & HF_SMM_MASK));
3667 }
3668
3669 static Property x86_cpu_properties[] = {
3670 #ifdef CONFIG_USER_ONLY
3671 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3672 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
3673 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3674 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3675 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
3676 #else
3677 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
3678 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3679 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3680 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
3681 #endif
3682 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
3683 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
3684 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
3685 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
3686 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
3687 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
3688 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
3689 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
3690 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
3691 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
3692 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
3693 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
3694 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
3695 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
3696 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
3697 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
3698 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
3699 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
3700 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
3701 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
3702 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
3703 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
3704 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
3705 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
3706 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
3707 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
3708 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
3709 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
3710 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
3711 DEFINE_PROP_END_OF_LIST()
3712 };
3713
3714 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3715 {
3716 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3717 CPUClass *cc = CPU_CLASS(oc);
3718 DeviceClass *dc = DEVICE_CLASS(oc);
3719
3720 xcc->parent_realize = dc->realize;
3721 xcc->parent_unrealize = dc->unrealize;
3722 dc->realize = x86_cpu_realizefn;
3723 dc->unrealize = x86_cpu_unrealizefn;
3724 dc->props = x86_cpu_properties;
3725
3726 xcc->parent_reset = cc->reset;
3727 cc->reset = x86_cpu_reset;
3728 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
3729
3730 cc->class_by_name = x86_cpu_class_by_name;
3731 cc->parse_features = x86_cpu_parse_featurestr;
3732 cc->has_work = x86_cpu_has_work;
3733 cc->do_interrupt = x86_cpu_do_interrupt;
3734 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
3735 cc->dump_state = x86_cpu_dump_state;
3736 cc->get_crash_info = x86_cpu_get_crash_info;
3737 cc->set_pc = x86_cpu_set_pc;
3738 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
3739 cc->gdb_read_register = x86_cpu_gdb_read_register;
3740 cc->gdb_write_register = x86_cpu_gdb_write_register;
3741 cc->get_arch_id = x86_cpu_get_arch_id;
3742 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
3743 #ifdef CONFIG_USER_ONLY
3744 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3745 #else
3746 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
3747 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
3748 cc->write_elf64_note = x86_cpu_write_elf64_note;
3749 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3750 cc->write_elf32_note = x86_cpu_write_elf32_note;
3751 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
3752 cc->vmsd = &vmstate_x86_cpu;
3753 #endif
3754 /* CPU_NB_REGS * 2 = general regs + xmm regs
3755 * 25 = eip, eflags, 6 seg regs, st[0-7], fctrl,...,fop, mxcsr.
3756 */
3757 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
3758 #ifndef CONFIG_USER_ONLY
3759 cc->debug_excp_handler = breakpoint_handler;
3760 #endif
3761 cc->cpu_exec_enter = x86_cpu_exec_enter;
3762 cc->cpu_exec_exit = x86_cpu_exec_exit;
3763
3764 dc->cannot_instantiate_with_device_add_yet = false;
3765 }
3766
3767 static const TypeInfo x86_cpu_type_info = {
3768 .name = TYPE_X86_CPU,
3769 .parent = TYPE_CPU,
3770 .instance_size = sizeof(X86CPU),
3771 .instance_init = x86_cpu_initfn,
3772 .abstract = true,
3773 .class_size = sizeof(X86CPUClass),
3774 .class_init = x86_cpu_common_class_init,
3775 };
3776
3777 static void x86_cpu_register_types(void)
3778 {
3779 int i;
3780
3781 type_register_static(&x86_cpu_type_info);
3782 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3783 x86_register_cpudef_type(&builtin_x86_defs[i]);
3784 }
3785 #ifdef CONFIG_KVM
3786 type_register_static(&host_x86_cpu_type_info);
3787 #endif
3788 }
3789
3790 type_init(x86_cpu_register_types)
QEMU mirror