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target/i386: Support up to 32768 CPUs without IRQ remapping
[mirror_qemu.git] / target / i386 / cpu.c
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
25
26 #include "cpu.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/hvf.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/xen.h"
33 #include "kvm_i386.h"
34 #include "sev_i386.h"
35
36 #include "qemu/error-report.h"
37 #include "qemu/module.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qapi/error.h"
41 #include "qapi/qapi-visit-machine.h"
42 #include "qapi/qapi-visit-run-state.h"
43 #include "qapi/qmp/qdict.h"
44 #include "qapi/qmp/qerror.h"
45 #include "qapi/visitor.h"
46 #include "qom/qom-qobject.h"
47 #include "sysemu/arch_init.h"
48 #include "qapi/qapi-commands-machine-target.h"
49
50 #include "standard-headers/asm-x86/kvm_para.h"
51
52 #include "sysemu/sysemu.h"
53 #include "sysemu/tcg.h"
54 #include "hw/qdev-properties.h"
55 #include "hw/i386/topology.h"
56 #ifndef CONFIG_USER_ONLY
57 #include "exec/address-spaces.h"
58 #include "hw/i386/apic_internal.h"
59 #include "hw/boards.h"
60 #endif
61
62 #include "disas/capstone.h"
63
64 /* Helpers for building CPUID[2] descriptors: */
65
66 struct CPUID2CacheDescriptorInfo {
67 enum CacheType type;
68 int level;
69 int size;
70 int line_size;
71 int associativity;
72 };
73
74 /*
75 * Known CPUID 2 cache descriptors.
76 * From Intel SDM Volume 2A, CPUID instruction
77 */
78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
79 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
80 .associativity = 4, .line_size = 32, },
81 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
82 .associativity = 4, .line_size = 32, },
83 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
84 .associativity = 4, .line_size = 64, },
85 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
86 .associativity = 2, .line_size = 32, },
87 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
88 .associativity = 4, .line_size = 32, },
89 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
90 .associativity = 4, .line_size = 64, },
91 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
92 .associativity = 6, .line_size = 64, },
93 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
94 .associativity = 2, .line_size = 64, },
95 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
96 .associativity = 8, .line_size = 64, },
97 /* lines per sector is not supported cpuid2_cache_descriptor(),
98 * so descriptors 0x22, 0x23 are not included
99 */
100 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
101 .associativity = 16, .line_size = 64, },
102 /* lines per sector is not supported cpuid2_cache_descriptor(),
103 * so descriptors 0x25, 0x20 are not included
104 */
105 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
106 .associativity = 8, .line_size = 64, },
107 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
108 .associativity = 8, .line_size = 64, },
109 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
110 .associativity = 4, .line_size = 32, },
111 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
112 .associativity = 4, .line_size = 32, },
113 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
114 .associativity = 4, .line_size = 32, },
115 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
116 .associativity = 4, .line_size = 32, },
117 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
118 .associativity = 4, .line_size = 32, },
119 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
120 .associativity = 4, .line_size = 64, },
121 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
122 .associativity = 8, .line_size = 64, },
123 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
124 .associativity = 12, .line_size = 64, },
125 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
126 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
127 .associativity = 12, .line_size = 64, },
128 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
129 .associativity = 16, .line_size = 64, },
130 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
131 .associativity = 12, .line_size = 64, },
132 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
133 .associativity = 16, .line_size = 64, },
134 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
135 .associativity = 24, .line_size = 64, },
136 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
137 .associativity = 8, .line_size = 64, },
138 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
139 .associativity = 4, .line_size = 64, },
140 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
141 .associativity = 4, .line_size = 64, },
142 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
143 .associativity = 4, .line_size = 64, },
144 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
145 .associativity = 4, .line_size = 64, },
146 /* lines per sector is not supported cpuid2_cache_descriptor(),
147 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
148 */
149 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
150 .associativity = 8, .line_size = 64, },
151 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
152 .associativity = 2, .line_size = 64, },
153 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
154 .associativity = 8, .line_size = 64, },
155 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
156 .associativity = 8, .line_size = 32, },
157 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
158 .associativity = 8, .line_size = 32, },
159 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
160 .associativity = 8, .line_size = 32, },
161 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
162 .associativity = 8, .line_size = 32, },
163 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
164 .associativity = 4, .line_size = 64, },
165 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
166 .associativity = 8, .line_size = 64, },
167 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
168 .associativity = 4, .line_size = 64, },
169 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
170 .associativity = 4, .line_size = 64, },
171 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
172 .associativity = 4, .line_size = 64, },
173 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
174 .associativity = 8, .line_size = 64, },
175 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
176 .associativity = 8, .line_size = 64, },
177 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
178 .associativity = 8, .line_size = 64, },
179 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
180 .associativity = 12, .line_size = 64, },
181 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
182 .associativity = 12, .line_size = 64, },
183 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
184 .associativity = 12, .line_size = 64, },
185 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
186 .associativity = 16, .line_size = 64, },
187 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
188 .associativity = 16, .line_size = 64, },
189 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
190 .associativity = 16, .line_size = 64, },
191 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
192 .associativity = 24, .line_size = 64, },
193 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
194 .associativity = 24, .line_size = 64, },
195 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
196 .associativity = 24, .line_size = 64, },
197 };
198
199 /*
200 * "CPUID leaf 2 does not report cache descriptor information,
201 * use CPUID leaf 4 to query cache parameters"
202 */
203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
204
205 /*
206 * Return a CPUID 2 cache descriptor for a given cache.
207 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
208 */
209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 {
211 int i;
212
213 assert(cache->size > 0);
214 assert(cache->level > 0);
215 assert(cache->line_size > 0);
216 assert(cache->associativity > 0);
217 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
218 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
219 if (d->level == cache->level && d->type == cache->type &&
220 d->size == cache->size && d->line_size == cache->line_size &&
221 d->associativity == cache->associativity) {
222 return i;
223 }
224 }
225
226 return CACHE_DESCRIPTOR_UNAVAILABLE;
227 }
228
229 /* CPUID Leaf 4 constants: */
230
231 /* EAX: */
232 #define CACHE_TYPE_D 1
233 #define CACHE_TYPE_I 2
234 #define CACHE_TYPE_UNIFIED 3
235
236 #define CACHE_LEVEL(l) (l << 5)
237
238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
239
240 /* EDX: */
241 #define CACHE_NO_INVD_SHARING (1 << 0)
242 #define CACHE_INCLUSIVE (1 << 1)
243 #define CACHE_COMPLEX_IDX (1 << 2)
244
245 /* Encode CacheType for CPUID[4].EAX */
246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
247 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
248 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
249 0 /* Invalid value */)
250
251
252 /* Encode cache info for CPUID[4] */
253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
254 int num_apic_ids, int num_cores,
255 uint32_t *eax, uint32_t *ebx,
256 uint32_t *ecx, uint32_t *edx)
257 {
258 assert(cache->size == cache->line_size * cache->associativity *
259 cache->partitions * cache->sets);
260
261 assert(num_apic_ids > 0);
262 *eax = CACHE_TYPE(cache->type) |
263 CACHE_LEVEL(cache->level) |
264 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
265 ((num_cores - 1) << 26) |
266 ((num_apic_ids - 1) << 14);
267
268 assert(cache->line_size > 0);
269 assert(cache->partitions > 0);
270 assert(cache->associativity > 0);
271 /* We don't implement fully-associative caches */
272 assert(cache->associativity < cache->sets);
273 *ebx = (cache->line_size - 1) |
274 ((cache->partitions - 1) << 12) |
275 ((cache->associativity - 1) << 22);
276
277 assert(cache->sets > 0);
278 *ecx = cache->sets - 1;
279
280 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
281 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
282 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
283 }
284
285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
287 {
288 assert(cache->size % 1024 == 0);
289 assert(cache->lines_per_tag > 0);
290 assert(cache->associativity > 0);
291 assert(cache->line_size > 0);
292 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
293 (cache->lines_per_tag << 8) | (cache->line_size);
294 }
295
296 #define ASSOC_FULL 0xFF
297
298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
299 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
300 a == 2 ? 0x2 : \
301 a == 4 ? 0x4 : \
302 a == 8 ? 0x6 : \
303 a == 16 ? 0x8 : \
304 a == 32 ? 0xA : \
305 a == 48 ? 0xB : \
306 a == 64 ? 0xC : \
307 a == 96 ? 0xD : \
308 a == 128 ? 0xE : \
309 a == ASSOC_FULL ? 0xF : \
310 0 /* invalid value */)
311
312 /*
313 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
314 * @l3 can be NULL.
315 */
316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
317 CPUCacheInfo *l3,
318 uint32_t *ecx, uint32_t *edx)
319 {
320 assert(l2->size % 1024 == 0);
321 assert(l2->associativity > 0);
322 assert(l2->lines_per_tag > 0);
323 assert(l2->line_size > 0);
324 *ecx = ((l2->size / 1024) << 16) |
325 (AMD_ENC_ASSOC(l2->associativity) << 12) |
326 (l2->lines_per_tag << 8) | (l2->line_size);
327
328 if (l3) {
329 assert(l3->size % (512 * 1024) == 0);
330 assert(l3->associativity > 0);
331 assert(l3->lines_per_tag > 0);
332 assert(l3->line_size > 0);
333 *edx = ((l3->size / (512 * 1024)) << 18) |
334 (AMD_ENC_ASSOC(l3->associativity) << 12) |
335 (l3->lines_per_tag << 8) | (l3->line_size);
336 } else {
337 *edx = 0;
338 }
339 }
340
341 /* Encode cache info for CPUID[8000001D] */
342 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
343 X86CPUTopoInfo *topo_info,
344 uint32_t *eax, uint32_t *ebx,
345 uint32_t *ecx, uint32_t *edx)
346 {
347 uint32_t l3_threads;
348 assert(cache->size == cache->line_size * cache->associativity *
349 cache->partitions * cache->sets);
350
351 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
352 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
353
354 /* L3 is shared among multiple cores */
355 if (cache->level == 3) {
356 l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
357 *eax |= (l3_threads - 1) << 14;
358 } else {
359 *eax |= ((topo_info->threads_per_core - 1) << 14);
360 }
361
362 assert(cache->line_size > 0);
363 assert(cache->partitions > 0);
364 assert(cache->associativity > 0);
365 /* We don't implement fully-associative caches */
366 assert(cache->associativity < cache->sets);
367 *ebx = (cache->line_size - 1) |
368 ((cache->partitions - 1) << 12) |
369 ((cache->associativity - 1) << 22);
370
371 assert(cache->sets > 0);
372 *ecx = cache->sets - 1;
373
374 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
375 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
376 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
377 }
378
379 /* Encode cache info for CPUID[8000001E] */
380 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
381 uint32_t *eax, uint32_t *ebx,
382 uint32_t *ecx, uint32_t *edx)
383 {
384 X86CPUTopoIDs topo_ids;
385
386 x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
387
388 *eax = cpu->apic_id;
389
390 /*
391 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
392 * Read-only. Reset: 0000_XXXXh.
393 * See Core::X86::Cpuid::ExtApicId.
394 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
395 * Bits Description
396 * 31:16 Reserved.
397 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
398 * The number of threads per core is ThreadsPerCore+1.
399 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
400 *
401 * NOTE: CoreId is already part of apic_id. Just use it. We can
402 * use all the 8 bits to represent the core_id here.
403 */
404 *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
405
406 /*
407 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
408 * Read-only. Reset: 0000_0XXXh.
409 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
410 * Bits Description
411 * 31:11 Reserved.
412 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
413 * ValidValues:
414 * Value Description
415 * 000b 1 node per processor.
416 * 001b 2 nodes per processor.
417 * 010b Reserved.
418 * 011b 4 nodes per processor.
419 * 111b-100b Reserved.
420 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
421 *
422 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
423 * But users can create more nodes than the actual hardware can
424 * support. To genaralize we can use all the upper 8 bits for nodes.
425 * NodeId is combination of node and socket_id which is already decoded
426 * in apic_id. Just use it by shifting.
427 */
428 *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
429 ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
430
431 *edx = 0;
432 }
433
434 /*
435 * Definitions of the hardcoded cache entries we expose:
436 * These are legacy cache values. If there is a need to change any
437 * of these values please use builtin_x86_defs
438 */
439
440 /* L1 data cache: */
441 static CPUCacheInfo legacy_l1d_cache = {
442 .type = DATA_CACHE,
443 .level = 1,
444 .size = 32 * KiB,
445 .self_init = 1,
446 .line_size = 64,
447 .associativity = 8,
448 .sets = 64,
449 .partitions = 1,
450 .no_invd_sharing = true,
451 };
452
453 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
454 static CPUCacheInfo legacy_l1d_cache_amd = {
455 .type = DATA_CACHE,
456 .level = 1,
457 .size = 64 * KiB,
458 .self_init = 1,
459 .line_size = 64,
460 .associativity = 2,
461 .sets = 512,
462 .partitions = 1,
463 .lines_per_tag = 1,
464 .no_invd_sharing = true,
465 };
466
467 /* L1 instruction cache: */
468 static CPUCacheInfo legacy_l1i_cache = {
469 .type = INSTRUCTION_CACHE,
470 .level = 1,
471 .size = 32 * KiB,
472 .self_init = 1,
473 .line_size = 64,
474 .associativity = 8,
475 .sets = 64,
476 .partitions = 1,
477 .no_invd_sharing = true,
478 };
479
480 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
481 static CPUCacheInfo legacy_l1i_cache_amd = {
482 .type = INSTRUCTION_CACHE,
483 .level = 1,
484 .size = 64 * KiB,
485 .self_init = 1,
486 .line_size = 64,
487 .associativity = 2,
488 .sets = 512,
489 .partitions = 1,
490 .lines_per_tag = 1,
491 .no_invd_sharing = true,
492 };
493
494 /* Level 2 unified cache: */
495 static CPUCacheInfo legacy_l2_cache = {
496 .type = UNIFIED_CACHE,
497 .level = 2,
498 .size = 4 * MiB,
499 .self_init = 1,
500 .line_size = 64,
501 .associativity = 16,
502 .sets = 4096,
503 .partitions = 1,
504 .no_invd_sharing = true,
505 };
506
507 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
508 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
509 .type = UNIFIED_CACHE,
510 .level = 2,
511 .size = 2 * MiB,
512 .line_size = 64,
513 .associativity = 8,
514 };
515
516
517 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
518 static CPUCacheInfo legacy_l2_cache_amd = {
519 .type = UNIFIED_CACHE,
520 .level = 2,
521 .size = 512 * KiB,
522 .line_size = 64,
523 .lines_per_tag = 1,
524 .associativity = 16,
525 .sets = 512,
526 .partitions = 1,
527 };
528
529 /* Level 3 unified cache: */
530 static CPUCacheInfo legacy_l3_cache = {
531 .type = UNIFIED_CACHE,
532 .level = 3,
533 .size = 16 * MiB,
534 .line_size = 64,
535 .associativity = 16,
536 .sets = 16384,
537 .partitions = 1,
538 .lines_per_tag = 1,
539 .self_init = true,
540 .inclusive = true,
541 .complex_indexing = true,
542 };
543
544 /* TLB definitions: */
545
546 #define L1_DTLB_2M_ASSOC 1
547 #define L1_DTLB_2M_ENTRIES 255
548 #define L1_DTLB_4K_ASSOC 1
549 #define L1_DTLB_4K_ENTRIES 255
550
551 #define L1_ITLB_2M_ASSOC 1
552 #define L1_ITLB_2M_ENTRIES 255
553 #define L1_ITLB_4K_ASSOC 1
554 #define L1_ITLB_4K_ENTRIES 255
555
556 #define L2_DTLB_2M_ASSOC 0 /* disabled */
557 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
558 #define L2_DTLB_4K_ASSOC 4
559 #define L2_DTLB_4K_ENTRIES 512
560
561 #define L2_ITLB_2M_ASSOC 0 /* disabled */
562 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
563 #define L2_ITLB_4K_ASSOC 4
564 #define L2_ITLB_4K_ENTRIES 512
565
566 /* CPUID Leaf 0x14 constants: */
567 #define INTEL_PT_MAX_SUBLEAF 0x1
568 /*
569 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
570 * MSR can be accessed;
571 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
572 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
573 * of Intel PT MSRs across warm reset;
574 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
575 */
576 #define INTEL_PT_MINIMAL_EBX 0xf
577 /*
578 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
579 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
580 * accessed;
581 * bit[01]: ToPA tables can hold any number of output entries, up to the
582 * maximum allowed by the MaskOrTableOffset field of
583 * IA32_RTIT_OUTPUT_MASK_PTRS;
584 * bit[02]: Support Single-Range Output scheme;
585 */
586 #define INTEL_PT_MINIMAL_ECX 0x7
587 /* generated packets which contain IP payloads have LIP values */
588 #define INTEL_PT_IP_LIP (1 << 31)
589 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
590 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
591 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
592 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
593 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
594
595 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
596 uint32_t vendor2, uint32_t vendor3)
597 {
598 int i;
599 for (i = 0; i < 4; i++) {
600 dst[i] = vendor1 >> (8 * i);
601 dst[i + 4] = vendor2 >> (8 * i);
602 dst[i + 8] = vendor3 >> (8 * i);
603 }
604 dst[CPUID_VENDOR_SZ] = '\0';
605 }
606
607 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
608 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
609 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
610 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
611 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
612 CPUID_PSE36 | CPUID_FXSR)
613 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
614 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
615 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
616 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
617 CPUID_PAE | CPUID_SEP | CPUID_APIC)
618
619 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
620 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
621 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
622 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
623 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
624 /* partly implemented:
625 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
626 /* missing:
627 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
628 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
629 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
630 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
631 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
632 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
633 CPUID_EXT_RDRAND)
634 /* missing:
635 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
636 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
637 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
638 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
639 CPUID_EXT_F16C */
640
641 #ifdef TARGET_X86_64
642 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
643 #else
644 #define TCG_EXT2_X86_64_FEATURES 0
645 #endif
646
647 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
648 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
649 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
650 TCG_EXT2_X86_64_FEATURES)
651 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
652 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
653 #define TCG_EXT4_FEATURES 0
654 #define TCG_SVM_FEATURES CPUID_SVM_NPT
655 #define TCG_KVM_FEATURES 0
656 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
657 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
658 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
659 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
660 CPUID_7_0_EBX_ERMS)
661 /* missing:
662 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
663 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
664 CPUID_7_0_EBX_RDSEED */
665 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
666 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
667 CPUID_7_0_ECX_LA57)
668 #define TCG_7_0_EDX_FEATURES 0
669 #define TCG_7_1_EAX_FEATURES 0
670 #define TCG_APM_FEATURES 0
671 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
672 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
673 /* missing:
674 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
675
676 typedef enum FeatureWordType {
677 CPUID_FEATURE_WORD,
678 MSR_FEATURE_WORD,
679 } FeatureWordType;
680
681 typedef struct FeatureWordInfo {
682 FeatureWordType type;
683 /* feature flags names are taken from "Intel Processor Identification and
684 * the CPUID Instruction" and AMD's "CPUID Specification".
685 * In cases of disagreement between feature naming conventions,
686 * aliases may be added.
687 */
688 const char *feat_names[64];
689 union {
690 /* If type==CPUID_FEATURE_WORD */
691 struct {
692 uint32_t eax; /* Input EAX for CPUID */
693 bool needs_ecx; /* CPUID instruction uses ECX as input */
694 uint32_t ecx; /* Input ECX value for CPUID */
695 int reg; /* output register (R_* constant) */
696 } cpuid;
697 /* If type==MSR_FEATURE_WORD */
698 struct {
699 uint32_t index;
700 } msr;
701 };
702 uint64_t tcg_features; /* Feature flags supported by TCG */
703 uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
704 uint64_t migratable_flags; /* Feature flags known to be migratable */
705 /* Features that shouldn't be auto-enabled by "-cpu host" */
706 uint64_t no_autoenable_flags;
707 } FeatureWordInfo;
708
709 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
710 [FEAT_1_EDX] = {
711 .type = CPUID_FEATURE_WORD,
712 .feat_names = {
713 "fpu", "vme", "de", "pse",
714 "tsc", "msr", "pae", "mce",
715 "cx8", "apic", NULL, "sep",
716 "mtrr", "pge", "mca", "cmov",
717 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
718 NULL, "ds" /* Intel dts */, "acpi", "mmx",
719 "fxsr", "sse", "sse2", "ss",
720 "ht" /* Intel htt */, "tm", "ia64", "pbe",
721 },
722 .cpuid = {.eax = 1, .reg = R_EDX, },
723 .tcg_features = TCG_FEATURES,
724 },
725 [FEAT_1_ECX] = {
726 .type = CPUID_FEATURE_WORD,
727 .feat_names = {
728 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
729 "ds-cpl", "vmx", "smx", "est",
730 "tm2", "ssse3", "cid", NULL,
731 "fma", "cx16", "xtpr", "pdcm",
732 NULL, "pcid", "dca", "sse4.1",
733 "sse4.2", "x2apic", "movbe", "popcnt",
734 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
735 "avx", "f16c", "rdrand", "hypervisor",
736 },
737 .cpuid = { .eax = 1, .reg = R_ECX, },
738 .tcg_features = TCG_EXT_FEATURES,
739 },
740 /* Feature names that are already defined on feature_name[] but
741 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
742 * names on feat_names below. They are copied automatically
743 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
744 */
745 [FEAT_8000_0001_EDX] = {
746 .type = CPUID_FEATURE_WORD,
747 .feat_names = {
748 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
749 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
750 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
751 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
752 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
753 "nx", NULL, "mmxext", NULL /* mmx */,
754 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
755 NULL, "lm", "3dnowext", "3dnow",
756 },
757 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
758 .tcg_features = TCG_EXT2_FEATURES,
759 },
760 [FEAT_8000_0001_ECX] = {
761 .type = CPUID_FEATURE_WORD,
762 .feat_names = {
763 "lahf-lm", "cmp-legacy", "svm", "extapic",
764 "cr8legacy", "abm", "sse4a", "misalignsse",
765 "3dnowprefetch", "osvw", "ibs", "xop",
766 "skinit", "wdt", NULL, "lwp",
767 "fma4", "tce", NULL, "nodeid-msr",
768 NULL, "tbm", "topoext", "perfctr-core",
769 "perfctr-nb", NULL, NULL, NULL,
770 NULL, NULL, NULL, NULL,
771 },
772 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
773 .tcg_features = TCG_EXT3_FEATURES,
774 /*
775 * TOPOEXT is always allowed but can't be enabled blindly by
776 * "-cpu host", as it requires consistent cache topology info
777 * to be provided so it doesn't confuse guests.
778 */
779 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
780 },
781 [FEAT_C000_0001_EDX] = {
782 .type = CPUID_FEATURE_WORD,
783 .feat_names = {
784 NULL, NULL, "xstore", "xstore-en",
785 NULL, NULL, "xcrypt", "xcrypt-en",
786 "ace2", "ace2-en", "phe", "phe-en",
787 "pmm", "pmm-en", NULL, NULL,
788 NULL, NULL, NULL, NULL,
789 NULL, NULL, NULL, NULL,
790 NULL, NULL, NULL, NULL,
791 NULL, NULL, NULL, NULL,
792 },
793 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
794 .tcg_features = TCG_EXT4_FEATURES,
795 },
796 [FEAT_KVM] = {
797 .type = CPUID_FEATURE_WORD,
798 .feat_names = {
799 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
800 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
801 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
802 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
803 NULL, NULL, NULL, NULL,
804 NULL, NULL, NULL, NULL,
805 "kvmclock-stable-bit", NULL, NULL, NULL,
806 NULL, NULL, NULL, NULL,
807 },
808 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
809 .tcg_features = TCG_KVM_FEATURES,
810 },
811 [FEAT_KVM_HINTS] = {
812 .type = CPUID_FEATURE_WORD,
813 .feat_names = {
814 "kvm-hint-dedicated", NULL, NULL, NULL,
815 NULL, NULL, NULL, NULL,
816 NULL, NULL, NULL, NULL,
817 NULL, NULL, NULL, NULL,
818 NULL, NULL, NULL, NULL,
819 NULL, NULL, NULL, NULL,
820 NULL, NULL, NULL, NULL,
821 NULL, NULL, NULL, NULL,
822 },
823 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
824 .tcg_features = TCG_KVM_FEATURES,
825 /*
826 * KVM hints aren't auto-enabled by -cpu host, they need to be
827 * explicitly enabled in the command-line.
828 */
829 .no_autoenable_flags = ~0U,
830 },
831 /*
832 * .feat_names are commented out for Hyper-V enlightenments because we
833 * don't want to have two different ways for enabling them on QEMU command
834 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
835 * enabling several feature bits simultaneously, exposing these bits
836 * individually may just confuse guests.
837 */
838 [FEAT_HYPERV_EAX] = {
839 .type = CPUID_FEATURE_WORD,
840 .feat_names = {
841 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
842 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
843 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
844 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
845 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
846 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
847 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
848 NULL, NULL,
849 NULL, NULL, NULL, NULL,
850 NULL, NULL, NULL, NULL,
851 NULL, NULL, NULL, NULL,
852 NULL, NULL, NULL, NULL,
853 },
854 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
855 },
856 [FEAT_HYPERV_EBX] = {
857 .type = CPUID_FEATURE_WORD,
858 .feat_names = {
859 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
860 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
861 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
862 NULL /* hv_create_port */, NULL /* hv_connect_port */,
863 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
864 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
865 NULL, NULL,
866 NULL, NULL, NULL, NULL,
867 NULL, NULL, NULL, NULL,
868 NULL, NULL, NULL, NULL,
869 NULL, NULL, NULL, NULL,
870 },
871 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
872 },
873 [FEAT_HYPERV_EDX] = {
874 .type = CPUID_FEATURE_WORD,
875 .feat_names = {
876 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
877 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
878 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
879 NULL, NULL,
880 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
881 NULL, NULL, NULL, NULL,
882 NULL, NULL, NULL, NULL,
883 NULL, NULL, NULL, NULL,
884 NULL, NULL, NULL, NULL,
885 NULL, NULL, NULL, NULL,
886 },
887 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
888 },
889 [FEAT_HV_RECOMM_EAX] = {
890 .type = CPUID_FEATURE_WORD,
891 .feat_names = {
892 NULL /* hv_recommend_pv_as_switch */,
893 NULL /* hv_recommend_pv_tlbflush_local */,
894 NULL /* hv_recommend_pv_tlbflush_remote */,
895 NULL /* hv_recommend_msr_apic_access */,
896 NULL /* hv_recommend_msr_reset */,
897 NULL /* hv_recommend_relaxed_timing */,
898 NULL /* hv_recommend_dma_remapping */,
899 NULL /* hv_recommend_int_remapping */,
900 NULL /* hv_recommend_x2apic_msrs */,
901 NULL /* hv_recommend_autoeoi_deprecation */,
902 NULL /* hv_recommend_pv_ipi */,
903 NULL /* hv_recommend_ex_hypercalls */,
904 NULL /* hv_hypervisor_is_nested */,
905 NULL /* hv_recommend_int_mbec */,
906 NULL /* hv_recommend_evmcs */,
907 NULL,
908 NULL, NULL, NULL, NULL,
909 NULL, NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
911 NULL, NULL, NULL, NULL,
912 },
913 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
914 },
915 [FEAT_HV_NESTED_EAX] = {
916 .type = CPUID_FEATURE_WORD,
917 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
918 },
919 [FEAT_SVM] = {
920 .type = CPUID_FEATURE_WORD,
921 .feat_names = {
922 "npt", "lbrv", "svm-lock", "nrip-save",
923 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
924 NULL, NULL, "pause-filter", NULL,
925 "pfthreshold", NULL, NULL, NULL,
926 NULL, NULL, NULL, NULL,
927 NULL, NULL, NULL, NULL,
928 NULL, NULL, NULL, NULL,
929 NULL, NULL, NULL, NULL,
930 },
931 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
932 .tcg_features = TCG_SVM_FEATURES,
933 },
934 [FEAT_7_0_EBX] = {
935 .type = CPUID_FEATURE_WORD,
936 .feat_names = {
937 "fsgsbase", "tsc-adjust", NULL, "bmi1",
938 "hle", "avx2", NULL, "smep",
939 "bmi2", "erms", "invpcid", "rtm",
940 NULL, NULL, "mpx", NULL,
941 "avx512f", "avx512dq", "rdseed", "adx",
942 "smap", "avx512ifma", "pcommit", "clflushopt",
943 "clwb", "intel-pt", "avx512pf", "avx512er",
944 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
945 },
946 .cpuid = {
947 .eax = 7,
948 .needs_ecx = true, .ecx = 0,
949 .reg = R_EBX,
950 },
951 .tcg_features = TCG_7_0_EBX_FEATURES,
952 },
953 [FEAT_7_0_ECX] = {
954 .type = CPUID_FEATURE_WORD,
955 .feat_names = {
956 NULL, "avx512vbmi", "umip", "pku",
957 NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
958 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
959 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
960 "la57", NULL, NULL, NULL,
961 NULL, NULL, "rdpid", NULL,
962 NULL, "cldemote", NULL, "movdiri",
963 "movdir64b", NULL, NULL, NULL,
964 },
965 .cpuid = {
966 .eax = 7,
967 .needs_ecx = true, .ecx = 0,
968 .reg = R_ECX,
969 },
970 .tcg_features = TCG_7_0_ECX_FEATURES,
971 },
972 [FEAT_7_0_EDX] = {
973 .type = CPUID_FEATURE_WORD,
974 .feat_names = {
975 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
976 "fsrm", NULL, NULL, NULL,
977 "avx512-vp2intersect", NULL, "md-clear", NULL,
978 NULL, NULL, "serialize", NULL,
979 "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
980 NULL, NULL, NULL, NULL,
981 NULL, NULL, "spec-ctrl", "stibp",
982 NULL, "arch-capabilities", "core-capability", "ssbd",
983 },
984 .cpuid = {
985 .eax = 7,
986 .needs_ecx = true, .ecx = 0,
987 .reg = R_EDX,
988 },
989 .tcg_features = TCG_7_0_EDX_FEATURES,
990 },
991 [FEAT_7_1_EAX] = {
992 .type = CPUID_FEATURE_WORD,
993 .feat_names = {
994 NULL, NULL, NULL, NULL,
995 NULL, "avx512-bf16", NULL, NULL,
996 NULL, NULL, NULL, NULL,
997 NULL, NULL, NULL, NULL,
998 NULL, NULL, NULL, NULL,
999 NULL, NULL, NULL, NULL,
1000 NULL, NULL, NULL, NULL,
1001 NULL, NULL, NULL, NULL,
1002 },
1003 .cpuid = {
1004 .eax = 7,
1005 .needs_ecx = true, .ecx = 1,
1006 .reg = R_EAX,
1007 },
1008 .tcg_features = TCG_7_1_EAX_FEATURES,
1009 },
1010 [FEAT_8000_0007_EDX] = {
1011 .type = CPUID_FEATURE_WORD,
1012 .feat_names = {
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 "invtsc", NULL, NULL, NULL,
1016 NULL, NULL, NULL, NULL,
1017 NULL, NULL, NULL, NULL,
1018 NULL, NULL, NULL, NULL,
1019 NULL, NULL, NULL, NULL,
1020 NULL, NULL, NULL, NULL,
1021 },
1022 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1023 .tcg_features = TCG_APM_FEATURES,
1024 .unmigratable_flags = CPUID_APM_INVTSC,
1025 },
1026 [FEAT_8000_0008_EBX] = {
1027 .type = CPUID_FEATURE_WORD,
1028 .feat_names = {
1029 "clzero", NULL, "xsaveerptr", NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, "wbnoinvd", NULL, NULL,
1032 "ibpb", NULL, NULL, "amd-stibp",
1033 NULL, NULL, NULL, NULL,
1034 NULL, NULL, NULL, NULL,
1035 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1036 NULL, NULL, NULL, NULL,
1037 },
1038 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1039 .tcg_features = 0,
1040 .unmigratable_flags = 0,
1041 },
1042 [FEAT_XSAVE] = {
1043 .type = CPUID_FEATURE_WORD,
1044 .feat_names = {
1045 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1046 NULL, NULL, NULL, NULL,
1047 NULL, NULL, NULL, NULL,
1048 NULL, NULL, NULL, NULL,
1049 NULL, NULL, NULL, NULL,
1050 NULL, NULL, NULL, NULL,
1051 NULL, NULL, NULL, NULL,
1052 NULL, NULL, NULL, NULL,
1053 },
1054 .cpuid = {
1055 .eax = 0xd,
1056 .needs_ecx = true, .ecx = 1,
1057 .reg = R_EAX,
1058 },
1059 .tcg_features = TCG_XSAVE_FEATURES,
1060 },
1061 [FEAT_6_EAX] = {
1062 .type = CPUID_FEATURE_WORD,
1063 .feat_names = {
1064 NULL, NULL, "arat", NULL,
1065 NULL, NULL, NULL, NULL,
1066 NULL, NULL, NULL, NULL,
1067 NULL, NULL, NULL, NULL,
1068 NULL, NULL, NULL, NULL,
1069 NULL, NULL, NULL, NULL,
1070 NULL, NULL, NULL, NULL,
1071 NULL, NULL, NULL, NULL,
1072 },
1073 .cpuid = { .eax = 6, .reg = R_EAX, },
1074 .tcg_features = TCG_6_EAX_FEATURES,
1075 },
1076 [FEAT_XSAVE_COMP_LO] = {
1077 .type = CPUID_FEATURE_WORD,
1078 .cpuid = {
1079 .eax = 0xD,
1080 .needs_ecx = true, .ecx = 0,
1081 .reg = R_EAX,
1082 },
1083 .tcg_features = ~0U,
1084 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1085 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1086 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1087 XSTATE_PKRU_MASK,
1088 },
1089 [FEAT_XSAVE_COMP_HI] = {
1090 .type = CPUID_FEATURE_WORD,
1091 .cpuid = {
1092 .eax = 0xD,
1093 .needs_ecx = true, .ecx = 0,
1094 .reg = R_EDX,
1095 },
1096 .tcg_features = ~0U,
1097 },
1098 /*Below are MSR exposed features*/
1099 [FEAT_ARCH_CAPABILITIES] = {
1100 .type = MSR_FEATURE_WORD,
1101 .feat_names = {
1102 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1103 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1104 "taa-no", NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1106 NULL, NULL, NULL, NULL,
1107 NULL, NULL, NULL, NULL,
1108 NULL, NULL, NULL, NULL,
1109 NULL, NULL, NULL, NULL,
1110 },
1111 .msr = {
1112 .index = MSR_IA32_ARCH_CAPABILITIES,
1113 },
1114 },
1115 [FEAT_CORE_CAPABILITY] = {
1116 .type = MSR_FEATURE_WORD,
1117 .feat_names = {
1118 NULL, NULL, NULL, NULL,
1119 NULL, "split-lock-detect", NULL, NULL,
1120 NULL, NULL, NULL, NULL,
1121 NULL, NULL, NULL, NULL,
1122 NULL, NULL, NULL, NULL,
1123 NULL, NULL, NULL, NULL,
1124 NULL, NULL, NULL, NULL,
1125 NULL, NULL, NULL, NULL,
1126 },
1127 .msr = {
1128 .index = MSR_IA32_CORE_CAPABILITY,
1129 },
1130 },
1131 [FEAT_PERF_CAPABILITIES] = {
1132 .type = MSR_FEATURE_WORD,
1133 .feat_names = {
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, "full-width-write", NULL, NULL,
1138 NULL, NULL, NULL, NULL,
1139 NULL, NULL, NULL, NULL,
1140 NULL, NULL, NULL, NULL,
1141 NULL, NULL, NULL, NULL,
1142 },
1143 .msr = {
1144 .index = MSR_IA32_PERF_CAPABILITIES,
1145 },
1146 },
1147
1148 [FEAT_VMX_PROCBASED_CTLS] = {
1149 .type = MSR_FEATURE_WORD,
1150 .feat_names = {
1151 NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1152 NULL, NULL, NULL, "vmx-hlt-exit",
1153 NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1154 "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1155 "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1156 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1157 "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1158 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1159 },
1160 .msr = {
1161 .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1162 }
1163 },
1164
1165 [FEAT_VMX_SECONDARY_CTLS] = {
1166 .type = MSR_FEATURE_WORD,
1167 .feat_names = {
1168 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1169 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1170 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1171 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1172 "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1173 "vmx-xsaves", NULL, NULL, NULL,
1174 NULL, NULL, NULL, NULL,
1175 NULL, NULL, NULL, NULL,
1176 },
1177 .msr = {
1178 .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1179 }
1180 },
1181
1182 [FEAT_VMX_PINBASED_CTLS] = {
1183 .type = MSR_FEATURE_WORD,
1184 .feat_names = {
1185 "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1186 NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1187 NULL, NULL, NULL, NULL,
1188 NULL, NULL, NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 },
1194 .msr = {
1195 .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1196 }
1197 },
1198
1199 [FEAT_VMX_EXIT_CTLS] = {
1200 .type = MSR_FEATURE_WORD,
1201 /*
1202 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1203 * the LM CPUID bit.
1204 */
1205 .feat_names = {
1206 NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1207 NULL, NULL, NULL, NULL,
1208 NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1209 "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1210 NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1211 "vmx-exit-save-efer", "vmx-exit-load-efer",
1212 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1213 NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1214 NULL, NULL, NULL, NULL,
1215 },
1216 .msr = {
1217 .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1218 }
1219 },
1220
1221 [FEAT_VMX_ENTRY_CTLS] = {
1222 .type = MSR_FEATURE_WORD,
1223 .feat_names = {
1224 NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1225 NULL, NULL, NULL, NULL,
1226 NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1227 NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1228 "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1229 NULL, NULL, NULL, NULL,
1230 NULL, NULL, NULL, NULL,
1231 NULL, NULL, NULL, NULL,
1232 },
1233 .msr = {
1234 .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1235 }
1236 },
1237
1238 [FEAT_VMX_MISC] = {
1239 .type = MSR_FEATURE_WORD,
1240 .feat_names = {
1241 NULL, NULL, NULL, NULL,
1242 NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1243 "vmx-activity-wait-sipi", NULL, NULL, NULL,
1244 NULL, NULL, NULL, NULL,
1245 NULL, NULL, NULL, NULL,
1246 NULL, NULL, NULL, NULL,
1247 NULL, NULL, NULL, NULL,
1248 NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1249 },
1250 .msr = {
1251 .index = MSR_IA32_VMX_MISC,
1252 }
1253 },
1254
1255 [FEAT_VMX_EPT_VPID_CAPS] = {
1256 .type = MSR_FEATURE_WORD,
1257 .feat_names = {
1258 "vmx-ept-execonly", NULL, NULL, NULL,
1259 NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1260 NULL, NULL, NULL, NULL,
1261 NULL, NULL, NULL, NULL,
1262 "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1263 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1264 NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1265 NULL, NULL, NULL, NULL,
1266 "vmx-invvpid", NULL, NULL, NULL,
1267 NULL, NULL, NULL, NULL,
1268 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1269 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1270 NULL, NULL, NULL, NULL,
1271 NULL, NULL, NULL, NULL,
1272 NULL, NULL, NULL, NULL,
1273 NULL, NULL, NULL, NULL,
1274 NULL, NULL, NULL, NULL,
1275 },
1276 .msr = {
1277 .index = MSR_IA32_VMX_EPT_VPID_CAP,
1278 }
1279 },
1280
1281 [FEAT_VMX_BASIC] = {
1282 .type = MSR_FEATURE_WORD,
1283 .feat_names = {
1284 [54] = "vmx-ins-outs",
1285 [55] = "vmx-true-ctls",
1286 },
1287 .msr = {
1288 .index = MSR_IA32_VMX_BASIC,
1289 },
1290 /* Just to be safe - we don't support setting the MSEG version field. */
1291 .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1292 },
1293
1294 [FEAT_VMX_VMFUNC] = {
1295 .type = MSR_FEATURE_WORD,
1296 .feat_names = {
1297 [0] = "vmx-eptp-switching",
1298 },
1299 .msr = {
1300 .index = MSR_IA32_VMX_VMFUNC,
1301 }
1302 },
1303
1304 };
1305
1306 typedef struct FeatureMask {
1307 FeatureWord index;
1308 uint64_t mask;
1309 } FeatureMask;
1310
1311 typedef struct FeatureDep {
1312 FeatureMask from, to;
1313 } FeatureDep;
1314
1315 static FeatureDep feature_dependencies[] = {
1316 {
1317 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_ARCH_CAPABILITIES },
1318 .to = { FEAT_ARCH_CAPABILITIES, ~0ull },
1319 },
1320 {
1321 .from = { FEAT_7_0_EDX, CPUID_7_0_EDX_CORE_CAPABILITY },
1322 .to = { FEAT_CORE_CAPABILITY, ~0ull },
1323 },
1324 {
1325 .from = { FEAT_1_ECX, CPUID_EXT_PDCM },
1326 .to = { FEAT_PERF_CAPABILITIES, ~0ull },
1327 },
1328 {
1329 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1330 .to = { FEAT_VMX_PROCBASED_CTLS, ~0ull },
1331 },
1332 {
1333 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1334 .to = { FEAT_VMX_PINBASED_CTLS, ~0ull },
1335 },
1336 {
1337 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1338 .to = { FEAT_VMX_EXIT_CTLS, ~0ull },
1339 },
1340 {
1341 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1342 .to = { FEAT_VMX_ENTRY_CTLS, ~0ull },
1343 },
1344 {
1345 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1346 .to = { FEAT_VMX_MISC, ~0ull },
1347 },
1348 {
1349 .from = { FEAT_1_ECX, CPUID_EXT_VMX },
1350 .to = { FEAT_VMX_BASIC, ~0ull },
1351 },
1352 {
1353 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_LM },
1354 .to = { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_IA32E_MODE },
1355 },
1356 {
1357 .from = { FEAT_VMX_PROCBASED_CTLS, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1358 .to = { FEAT_VMX_SECONDARY_CTLS, ~0ull },
1359 },
1360 {
1361 .from = { FEAT_XSAVE, CPUID_XSAVE_XSAVES },
1362 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_XSAVES },
1363 },
1364 {
1365 .from = { FEAT_1_ECX, CPUID_EXT_RDRAND },
1366 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDRAND_EXITING },
1367 },
1368 {
1369 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_INVPCID },
1370 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1371 },
1372 {
1373 .from = { FEAT_7_0_EBX, CPUID_7_0_EBX_RDSEED },
1374 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDSEED_EXITING },
1375 },
1376 {
1377 .from = { FEAT_8000_0001_EDX, CPUID_EXT2_RDTSCP },
1378 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_RDTSCP },
1379 },
1380 {
1381 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1382 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull },
1383 },
1384 {
1385 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_EPT },
1386 .to = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1387 },
1388 {
1389 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VPID },
1390 .to = { FEAT_VMX_EPT_VPID_CAPS, 0xffffffffull << 32 },
1391 },
1392 {
1393 .from = { FEAT_VMX_SECONDARY_CTLS, VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1394 .to = { FEAT_VMX_VMFUNC, ~0ull },
1395 },
1396 {
1397 .from = { FEAT_8000_0001_ECX, CPUID_EXT3_SVM },
1398 .to = { FEAT_SVM, ~0ull },
1399 },
1400 };
1401
1402 typedef struct X86RegisterInfo32 {
1403 /* Name of register */
1404 const char *name;
1405 /* QAPI enum value register */
1406 X86CPURegister32 qapi_enum;
1407 } X86RegisterInfo32;
1408
1409 #define REGISTER(reg) \
1410 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1411 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1412 REGISTER(EAX),
1413 REGISTER(ECX),
1414 REGISTER(EDX),
1415 REGISTER(EBX),
1416 REGISTER(ESP),
1417 REGISTER(EBP),
1418 REGISTER(ESI),
1419 REGISTER(EDI),
1420 };
1421 #undef REGISTER
1422
1423 typedef struct ExtSaveArea {
1424 uint32_t feature, bits;
1425 uint32_t offset, size;
1426 } ExtSaveArea;
1427
1428 static const ExtSaveArea x86_ext_save_areas[] = {
1429 [XSTATE_FP_BIT] = {
1430 /* x87 FP state component is always enabled if XSAVE is supported */
1431 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1432 /* x87 state is in the legacy region of the XSAVE area */
1433 .offset = 0,
1434 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1435 },
1436 [XSTATE_SSE_BIT] = {
1437 /* SSE state component is always enabled if XSAVE is supported */
1438 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1439 /* SSE state is in the legacy region of the XSAVE area */
1440 .offset = 0,
1441 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1442 },
1443 [XSTATE_YMM_BIT] =
1444 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1445 .offset = offsetof(X86XSaveArea, avx_state),
1446 .size = sizeof(XSaveAVX) },
1447 [XSTATE_BNDREGS_BIT] =
1448 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1449 .offset = offsetof(X86XSaveArea, bndreg_state),
1450 .size = sizeof(XSaveBNDREG) },
1451 [XSTATE_BNDCSR_BIT] =
1452 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1453 .offset = offsetof(X86XSaveArea, bndcsr_state),
1454 .size = sizeof(XSaveBNDCSR) },
1455 [XSTATE_OPMASK_BIT] =
1456 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1457 .offset = offsetof(X86XSaveArea, opmask_state),
1458 .size = sizeof(XSaveOpmask) },
1459 [XSTATE_ZMM_Hi256_BIT] =
1460 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1461 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1462 .size = sizeof(XSaveZMM_Hi256) },
1463 [XSTATE_Hi16_ZMM_BIT] =
1464 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1465 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1466 .size = sizeof(XSaveHi16_ZMM) },
1467 [XSTATE_PKRU_BIT] =
1468 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1469 .offset = offsetof(X86XSaveArea, pkru_state),
1470 .size = sizeof(XSavePKRU) },
1471 };
1472
1473 static uint32_t xsave_area_size(uint64_t mask)
1474 {
1475 int i;
1476 uint64_t ret = 0;
1477
1478 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1479 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1480 if ((mask >> i) & 1) {
1481 ret = MAX(ret, esa->offset + esa->size);
1482 }
1483 }
1484 return ret;
1485 }
1486
1487 static inline bool accel_uses_host_cpuid(void)
1488 {
1489 return kvm_enabled() || hvf_enabled();
1490 }
1491
1492 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1493 {
1494 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1495 cpu->env.features[FEAT_XSAVE_COMP_LO];
1496 }
1497
1498 const char *get_register_name_32(unsigned int reg)
1499 {
1500 if (reg >= CPU_NB_REGS32) {
1501 return NULL;
1502 }
1503 return x86_reg_info_32[reg].name;
1504 }
1505
1506 /*
1507 * Returns the set of feature flags that are supported and migratable by
1508 * QEMU, for a given FeatureWord.
1509 */
1510 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1511 {
1512 FeatureWordInfo *wi = &feature_word_info[w];
1513 uint64_t r = 0;
1514 int i;
1515
1516 for (i = 0; i < 64; i++) {
1517 uint64_t f = 1ULL << i;
1518
1519 /* If the feature name is known, it is implicitly considered migratable,
1520 * unless it is explicitly set in unmigratable_flags */
1521 if ((wi->migratable_flags & f) ||
1522 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1523 r |= f;
1524 }
1525 }
1526 return r;
1527 }
1528
1529 void host_cpuid(uint32_t function, uint32_t count,
1530 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1531 {
1532 uint32_t vec[4];
1533
1534 #ifdef __x86_64__
1535 asm volatile("cpuid"
1536 : "=a"(vec[0]), "=b"(vec[1]),
1537 "=c"(vec[2]), "=d"(vec[3])
1538 : "0"(function), "c"(count) : "cc");
1539 #elif defined(__i386__)
1540 asm volatile("pusha \n\t"
1541 "cpuid \n\t"
1542 "mov %%eax, 0(%2) \n\t"
1543 "mov %%ebx, 4(%2) \n\t"
1544 "mov %%ecx, 8(%2) \n\t"
1545 "mov %%edx, 12(%2) \n\t"
1546 "popa"
1547 : : "a"(function), "c"(count), "S"(vec)
1548 : "memory", "cc");
1549 #else
1550 abort();
1551 #endif
1552
1553 if (eax)
1554 *eax = vec[0];
1555 if (ebx)
1556 *ebx = vec[1];
1557 if (ecx)
1558 *ecx = vec[2];
1559 if (edx)
1560 *edx = vec[3];
1561 }
1562
1563 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1564 {
1565 uint32_t eax, ebx, ecx, edx;
1566
1567 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1568 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1569
1570 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1571 if (family) {
1572 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1573 }
1574 if (model) {
1575 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1576 }
1577 if (stepping) {
1578 *stepping = eax & 0x0F;
1579 }
1580 }
1581
1582 /* CPU class name definitions: */
1583
1584 /* Return type name for a given CPU model name
1585 * Caller is responsible for freeing the returned string.
1586 */
1587 static char *x86_cpu_type_name(const char *model_name)
1588 {
1589 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1590 }
1591
1592 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1593 {
1594 g_autofree char *typename = x86_cpu_type_name(cpu_model);
1595 return object_class_by_name(typename);
1596 }
1597
1598 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1599 {
1600 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1601 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1602 return g_strndup(class_name,
1603 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1604 }
1605
1606 typedef struct PropValue {
1607 const char *prop, *value;
1608 } PropValue;
1609
1610 typedef struct X86CPUVersionDefinition {
1611 X86CPUVersion version;
1612 const char *alias;
1613 const char *note;
1614 PropValue *props;
1615 } X86CPUVersionDefinition;
1616
1617 /* Base definition for a CPU model */
1618 typedef struct X86CPUDefinition {
1619 const char *name;
1620 uint32_t level;
1621 uint32_t xlevel;
1622 /* vendor is zero-terminated, 12 character ASCII string */
1623 char vendor[CPUID_VENDOR_SZ + 1];
1624 int family;
1625 int model;
1626 int stepping;
1627 FeatureWordArray features;
1628 const char *model_id;
1629 CPUCaches *cache_info;
1630 /*
1631 * Definitions for alternative versions of CPU model.
1632 * List is terminated by item with version == 0.
1633 * If NULL, version 1 will be registered automatically.
1634 */
1635 const X86CPUVersionDefinition *versions;
1636 const char *deprecation_note;
1637 } X86CPUDefinition;
1638
1639 /* Reference to a specific CPU model version */
1640 struct X86CPUModel {
1641 /* Base CPU definition */
1642 X86CPUDefinition *cpudef;
1643 /* CPU model version */
1644 X86CPUVersion version;
1645 const char *note;
1646 /*
1647 * If true, this is an alias CPU model.
1648 * This matters only for "-cpu help" and query-cpu-definitions
1649 */
1650 bool is_alias;
1651 };
1652
1653 /* Get full model name for CPU version */
1654 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1655 X86CPUVersion version)
1656 {
1657 assert(version > 0);
1658 return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1659 }
1660
1661 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1662 {
1663 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1664 static const X86CPUVersionDefinition default_version_list[] = {
1665 { 1 },
1666 { /* end of list */ }
1667 };
1668
1669 return def->versions ?: default_version_list;
1670 }
1671
1672 static CPUCaches epyc_cache_info = {
1673 .l1d_cache = &(CPUCacheInfo) {
1674 .type = DATA_CACHE,
1675 .level = 1,
1676 .size = 32 * KiB,
1677 .line_size = 64,
1678 .associativity = 8,
1679 .partitions = 1,
1680 .sets = 64,
1681 .lines_per_tag = 1,
1682 .self_init = 1,
1683 .no_invd_sharing = true,
1684 },
1685 .l1i_cache = &(CPUCacheInfo) {
1686 .type = INSTRUCTION_CACHE,
1687 .level = 1,
1688 .size = 64 * KiB,
1689 .line_size = 64,
1690 .associativity = 4,
1691 .partitions = 1,
1692 .sets = 256,
1693 .lines_per_tag = 1,
1694 .self_init = 1,
1695 .no_invd_sharing = true,
1696 },
1697 .l2_cache = &(CPUCacheInfo) {
1698 .type = UNIFIED_CACHE,
1699 .level = 2,
1700 .size = 512 * KiB,
1701 .line_size = 64,
1702 .associativity = 8,
1703 .partitions = 1,
1704 .sets = 1024,
1705 .lines_per_tag = 1,
1706 },
1707 .l3_cache = &(CPUCacheInfo) {
1708 .type = UNIFIED_CACHE,
1709 .level = 3,
1710 .size = 8 * MiB,
1711 .line_size = 64,
1712 .associativity = 16,
1713 .partitions = 1,
1714 .sets = 8192,
1715 .lines_per_tag = 1,
1716 .self_init = true,
1717 .inclusive = true,
1718 .complex_indexing = true,
1719 },
1720 };
1721
1722 static CPUCaches epyc_rome_cache_info = {
1723 .l1d_cache = &(CPUCacheInfo) {
1724 .type = DATA_CACHE,
1725 .level = 1,
1726 .size = 32 * KiB,
1727 .line_size = 64,
1728 .associativity = 8,
1729 .partitions = 1,
1730 .sets = 64,
1731 .lines_per_tag = 1,
1732 .self_init = 1,
1733 .no_invd_sharing = true,
1734 },
1735 .l1i_cache = &(CPUCacheInfo) {
1736 .type = INSTRUCTION_CACHE,
1737 .level = 1,
1738 .size = 32 * KiB,
1739 .line_size = 64,
1740 .associativity = 8,
1741 .partitions = 1,
1742 .sets = 64,
1743 .lines_per_tag = 1,
1744 .self_init = 1,
1745 .no_invd_sharing = true,
1746 },
1747 .l2_cache = &(CPUCacheInfo) {
1748 .type = UNIFIED_CACHE,
1749 .level = 2,
1750 .size = 512 * KiB,
1751 .line_size = 64,
1752 .associativity = 8,
1753 .partitions = 1,
1754 .sets = 1024,
1755 .lines_per_tag = 1,
1756 },
1757 .l3_cache = &(CPUCacheInfo) {
1758 .type = UNIFIED_CACHE,
1759 .level = 3,
1760 .size = 16 * MiB,
1761 .line_size = 64,
1762 .associativity = 16,
1763 .partitions = 1,
1764 .sets = 16384,
1765 .lines_per_tag = 1,
1766 .self_init = true,
1767 .inclusive = true,
1768 .complex_indexing = true,
1769 },
1770 };
1771
1772 /* The following VMX features are not supported by KVM and are left out in the
1773 * CPU definitions:
1774 *
1775 * Dual-monitor support (all processors)
1776 * Entry to SMM
1777 * Deactivate dual-monitor treatment
1778 * Number of CR3-target values
1779 * Shutdown activity state
1780 * Wait-for-SIPI activity state
1781 * PAUSE-loop exiting (Westmere and newer)
1782 * EPT-violation #VE (Broadwell and newer)
1783 * Inject event with insn length=0 (Skylake and newer)
1784 * Conceal non-root operation from PT
1785 * Conceal VM exits from PT
1786 * Conceal VM entries from PT
1787 * Enable ENCLS exiting
1788 * Mode-based execute control (XS/XU)
1789 s TSC scaling (Skylake Server and newer)
1790 * GPA translation for PT (IceLake and newer)
1791 * User wait and pause
1792 * ENCLV exiting
1793 * Load IA32_RTIT_CTL
1794 * Clear IA32_RTIT_CTL
1795 * Advanced VM-exit information for EPT violations
1796 * Sub-page write permissions
1797 * PT in VMX operation
1798 */
1799
1800 static X86CPUDefinition builtin_x86_defs[] = {
1801 {
1802 .name = "qemu64",
1803 .level = 0xd,
1804 .vendor = CPUID_VENDOR_AMD,
1805 .family = 6,
1806 .model = 6,
1807 .stepping = 3,
1808 .features[FEAT_1_EDX] =
1809 PPRO_FEATURES |
1810 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1811 CPUID_PSE36,
1812 .features[FEAT_1_ECX] =
1813 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1814 .features[FEAT_8000_0001_EDX] =
1815 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1816 .features[FEAT_8000_0001_ECX] =
1817 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1818 .xlevel = 0x8000000A,
1819 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1820 },
1821 {
1822 .name = "phenom",
1823 .level = 5,
1824 .vendor = CPUID_VENDOR_AMD,
1825 .family = 16,
1826 .model = 2,
1827 .stepping = 3,
1828 /* Missing: CPUID_HT */
1829 .features[FEAT_1_EDX] =
1830 PPRO_FEATURES |
1831 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1832 CPUID_PSE36 | CPUID_VME,
1833 .features[FEAT_1_ECX] =
1834 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1835 CPUID_EXT_POPCNT,
1836 .features[FEAT_8000_0001_EDX] =
1837 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1838 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1839 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1840 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1841 CPUID_EXT3_CR8LEG,
1842 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1843 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1844 .features[FEAT_8000_0001_ECX] =
1845 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1846 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1847 /* Missing: CPUID_SVM_LBRV */
1848 .features[FEAT_SVM] =
1849 CPUID_SVM_NPT,
1850 .xlevel = 0x8000001A,
1851 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1852 },
1853 {
1854 .name = "core2duo",
1855 .level = 10,
1856 .vendor = CPUID_VENDOR_INTEL,
1857 .family = 6,
1858 .model = 15,
1859 .stepping = 11,
1860 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1861 .features[FEAT_1_EDX] =
1862 PPRO_FEATURES |
1863 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1864 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1865 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1866 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1867 .features[FEAT_1_ECX] =
1868 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1869 CPUID_EXT_CX16,
1870 .features[FEAT_8000_0001_EDX] =
1871 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1872 .features[FEAT_8000_0001_ECX] =
1873 CPUID_EXT3_LAHF_LM,
1874 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1875 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1876 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1877 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1878 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1879 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1880 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1881 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1882 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1883 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1884 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1885 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1886 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1887 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1888 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1889 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1890 .features[FEAT_VMX_SECONDARY_CTLS] =
1891 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1892 .xlevel = 0x80000008,
1893 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1894 },
1895 {
1896 .name = "kvm64",
1897 .level = 0xd,
1898 .vendor = CPUID_VENDOR_INTEL,
1899 .family = 15,
1900 .model = 6,
1901 .stepping = 1,
1902 /* Missing: CPUID_HT */
1903 .features[FEAT_1_EDX] =
1904 PPRO_FEATURES | CPUID_VME |
1905 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1906 CPUID_PSE36,
1907 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1908 .features[FEAT_1_ECX] =
1909 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1910 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1911 .features[FEAT_8000_0001_EDX] =
1912 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1913 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1914 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1915 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1916 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1917 .features[FEAT_8000_0001_ECX] =
1918 0,
1919 /* VMX features from Cedar Mill/Prescott */
1920 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1921 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1922 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1923 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1924 VMX_PIN_BASED_NMI_EXITING,
1925 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1926 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1927 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1928 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1929 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1930 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1931 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1932 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1933 .xlevel = 0x80000008,
1934 .model_id = "Common KVM processor"
1935 },
1936 {
1937 .name = "qemu32",
1938 .level = 4,
1939 .vendor = CPUID_VENDOR_INTEL,
1940 .family = 6,
1941 .model = 6,
1942 .stepping = 3,
1943 .features[FEAT_1_EDX] =
1944 PPRO_FEATURES,
1945 .features[FEAT_1_ECX] =
1946 CPUID_EXT_SSE3,
1947 .xlevel = 0x80000004,
1948 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1949 },
1950 {
1951 .name = "kvm32",
1952 .level = 5,
1953 .vendor = CPUID_VENDOR_INTEL,
1954 .family = 15,
1955 .model = 6,
1956 .stepping = 1,
1957 .features[FEAT_1_EDX] =
1958 PPRO_FEATURES | CPUID_VME |
1959 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1960 .features[FEAT_1_ECX] =
1961 CPUID_EXT_SSE3,
1962 .features[FEAT_8000_0001_ECX] =
1963 0,
1964 /* VMX features from Yonah */
1965 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1966 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1967 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1968 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1969 VMX_PIN_BASED_NMI_EXITING,
1970 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1971 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1972 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1973 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1974 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
1975 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
1976 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
1977 .xlevel = 0x80000008,
1978 .model_id = "Common 32-bit KVM processor"
1979 },
1980 {
1981 .name = "coreduo",
1982 .level = 10,
1983 .vendor = CPUID_VENDOR_INTEL,
1984 .family = 6,
1985 .model = 14,
1986 .stepping = 8,
1987 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1988 .features[FEAT_1_EDX] =
1989 PPRO_FEATURES | CPUID_VME |
1990 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1991 CPUID_SS,
1992 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1993 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1994 .features[FEAT_1_ECX] =
1995 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1996 .features[FEAT_8000_0001_EDX] =
1997 CPUID_EXT2_NX,
1998 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1999 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2000 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2001 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2002 VMX_PIN_BASED_NMI_EXITING,
2003 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2004 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2005 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2006 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2007 VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2008 VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2009 VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2010 .xlevel = 0x80000008,
2011 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2012 },
2013 {
2014 .name = "486",
2015 .level = 1,
2016 .vendor = CPUID_VENDOR_INTEL,
2017 .family = 4,
2018 .model = 8,
2019 .stepping = 0,
2020 .features[FEAT_1_EDX] =
2021 I486_FEATURES,
2022 .xlevel = 0,
2023 .model_id = "",
2024 },
2025 {
2026 .name = "pentium",
2027 .level = 1,
2028 .vendor = CPUID_VENDOR_INTEL,
2029 .family = 5,
2030 .model = 4,
2031 .stepping = 3,
2032 .features[FEAT_1_EDX] =
2033 PENTIUM_FEATURES,
2034 .xlevel = 0,
2035 .model_id = "",
2036 },
2037 {
2038 .name = "pentium2",
2039 .level = 2,
2040 .vendor = CPUID_VENDOR_INTEL,
2041 .family = 6,
2042 .model = 5,
2043 .stepping = 2,
2044 .features[FEAT_1_EDX] =
2045 PENTIUM2_FEATURES,
2046 .xlevel = 0,
2047 .model_id = "",
2048 },
2049 {
2050 .name = "pentium3",
2051 .level = 3,
2052 .vendor = CPUID_VENDOR_INTEL,
2053 .family = 6,
2054 .model = 7,
2055 .stepping = 3,
2056 .features[FEAT_1_EDX] =
2057 PENTIUM3_FEATURES,
2058 .xlevel = 0,
2059 .model_id = "",
2060 },
2061 {
2062 .name = "athlon",
2063 .level = 2,
2064 .vendor = CPUID_VENDOR_AMD,
2065 .family = 6,
2066 .model = 2,
2067 .stepping = 3,
2068 .features[FEAT_1_EDX] =
2069 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2070 CPUID_MCA,
2071 .features[FEAT_8000_0001_EDX] =
2072 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2073 .xlevel = 0x80000008,
2074 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2075 },
2076 {
2077 .name = "n270",
2078 .level = 10,
2079 .vendor = CPUID_VENDOR_INTEL,
2080 .family = 6,
2081 .model = 28,
2082 .stepping = 2,
2083 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2084 .features[FEAT_1_EDX] =
2085 PPRO_FEATURES |
2086 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2087 CPUID_ACPI | CPUID_SS,
2088 /* Some CPUs got no CPUID_SEP */
2089 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2090 * CPUID_EXT_XTPR */
2091 .features[FEAT_1_ECX] =
2092 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2093 CPUID_EXT_MOVBE,
2094 .features[FEAT_8000_0001_EDX] =
2095 CPUID_EXT2_NX,
2096 .features[FEAT_8000_0001_ECX] =
2097 CPUID_EXT3_LAHF_LM,
2098 .xlevel = 0x80000008,
2099 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2100 },
2101 {
2102 .name = "Conroe",
2103 .level = 10,
2104 .vendor = CPUID_VENDOR_INTEL,
2105 .family = 6,
2106 .model = 15,
2107 .stepping = 3,
2108 .features[FEAT_1_EDX] =
2109 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2110 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2111 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2112 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2113 CPUID_DE | CPUID_FP87,
2114 .features[FEAT_1_ECX] =
2115 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2116 .features[FEAT_8000_0001_EDX] =
2117 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2118 .features[FEAT_8000_0001_ECX] =
2119 CPUID_EXT3_LAHF_LM,
2120 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2121 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2122 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2123 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2124 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2125 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2126 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2127 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2128 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2129 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2130 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2131 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2132 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2133 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2134 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2135 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2136 .features[FEAT_VMX_SECONDARY_CTLS] =
2137 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2138 .xlevel = 0x80000008,
2139 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2140 },
2141 {
2142 .name = "Penryn",
2143 .level = 10,
2144 .vendor = CPUID_VENDOR_INTEL,
2145 .family = 6,
2146 .model = 23,
2147 .stepping = 3,
2148 .features[FEAT_1_EDX] =
2149 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2150 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2151 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2152 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2153 CPUID_DE | CPUID_FP87,
2154 .features[FEAT_1_ECX] =
2155 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2156 CPUID_EXT_SSE3,
2157 .features[FEAT_8000_0001_EDX] =
2158 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2159 .features[FEAT_8000_0001_ECX] =
2160 CPUID_EXT3_LAHF_LM,
2161 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2162 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2163 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2164 .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2165 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2166 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2167 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2168 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2169 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2170 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2171 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2172 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2173 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2174 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2175 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2176 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2177 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2178 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2179 .features[FEAT_VMX_SECONDARY_CTLS] =
2180 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2181 VMX_SECONDARY_EXEC_WBINVD_EXITING,
2182 .xlevel = 0x80000008,
2183 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2184 },
2185 {
2186 .name = "Nehalem",
2187 .level = 11,
2188 .vendor = CPUID_VENDOR_INTEL,
2189 .family = 6,
2190 .model = 26,
2191 .stepping = 3,
2192 .features[FEAT_1_EDX] =
2193 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2194 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2195 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2196 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2197 CPUID_DE | CPUID_FP87,
2198 .features[FEAT_1_ECX] =
2199 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2200 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2201 .features[FEAT_8000_0001_EDX] =
2202 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2203 .features[FEAT_8000_0001_ECX] =
2204 CPUID_EXT3_LAHF_LM,
2205 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2206 MSR_VMX_BASIC_TRUE_CTLS,
2207 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2208 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2209 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2210 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2211 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2212 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2213 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2214 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2215 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2216 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2217 .features[FEAT_VMX_EXIT_CTLS] =
2218 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2219 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2220 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2221 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2222 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2223 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2224 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2225 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2226 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2227 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2228 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2229 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2230 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2231 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2232 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2233 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2234 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2235 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2236 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2237 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2238 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2239 .features[FEAT_VMX_SECONDARY_CTLS] =
2240 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2241 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2242 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2243 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2244 VMX_SECONDARY_EXEC_ENABLE_VPID,
2245 .xlevel = 0x80000008,
2246 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2247 .versions = (X86CPUVersionDefinition[]) {
2248 { .version = 1 },
2249 {
2250 .version = 2,
2251 .alias = "Nehalem-IBRS",
2252 .props = (PropValue[]) {
2253 { "spec-ctrl", "on" },
2254 { "model-id",
2255 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2256 { /* end of list */ }
2257 }
2258 },
2259 { /* end of list */ }
2260 }
2261 },
2262 {
2263 .name = "Westmere",
2264 .level = 11,
2265 .vendor = CPUID_VENDOR_INTEL,
2266 .family = 6,
2267 .model = 44,
2268 .stepping = 1,
2269 .features[FEAT_1_EDX] =
2270 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2271 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2272 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2273 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2274 CPUID_DE | CPUID_FP87,
2275 .features[FEAT_1_ECX] =
2276 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2279 .features[FEAT_8000_0001_EDX] =
2280 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2281 .features[FEAT_8000_0001_ECX] =
2282 CPUID_EXT3_LAHF_LM,
2283 .features[FEAT_6_EAX] =
2284 CPUID_6_EAX_ARAT,
2285 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2286 MSR_VMX_BASIC_TRUE_CTLS,
2287 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2288 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2289 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2290 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2291 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2292 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2293 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2294 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2295 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2296 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2297 .features[FEAT_VMX_EXIT_CTLS] =
2298 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2299 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2300 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2301 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2302 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2303 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2304 MSR_VMX_MISC_STORE_LMA,
2305 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2306 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2307 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2308 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2309 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2310 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2311 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2312 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2313 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2314 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2315 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2316 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2317 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2318 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2319 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2320 .features[FEAT_VMX_SECONDARY_CTLS] =
2321 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2322 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2323 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2324 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2325 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2326 .xlevel = 0x80000008,
2327 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2328 .versions = (X86CPUVersionDefinition[]) {
2329 { .version = 1 },
2330 {
2331 .version = 2,
2332 .alias = "Westmere-IBRS",
2333 .props = (PropValue[]) {
2334 { "spec-ctrl", "on" },
2335 { "model-id",
2336 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2337 { /* end of list */ }
2338 }
2339 },
2340 { /* end of list */ }
2341 }
2342 },
2343 {
2344 .name = "SandyBridge",
2345 .level = 0xd,
2346 .vendor = CPUID_VENDOR_INTEL,
2347 .family = 6,
2348 .model = 42,
2349 .stepping = 1,
2350 .features[FEAT_1_EDX] =
2351 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2352 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2353 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2354 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2355 CPUID_DE | CPUID_FP87,
2356 .features[FEAT_1_ECX] =
2357 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2358 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2359 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2360 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2361 CPUID_EXT_SSE3,
2362 .features[FEAT_8000_0001_EDX] =
2363 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2364 CPUID_EXT2_SYSCALL,
2365 .features[FEAT_8000_0001_ECX] =
2366 CPUID_EXT3_LAHF_LM,
2367 .features[FEAT_XSAVE] =
2368 CPUID_XSAVE_XSAVEOPT,
2369 .features[FEAT_6_EAX] =
2370 CPUID_6_EAX_ARAT,
2371 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2372 MSR_VMX_BASIC_TRUE_CTLS,
2373 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2374 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2375 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2376 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2377 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2378 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2379 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2380 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2381 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2382 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2383 .features[FEAT_VMX_EXIT_CTLS] =
2384 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2385 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2386 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2387 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2388 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2389 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2390 MSR_VMX_MISC_STORE_LMA,
2391 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2392 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2393 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2394 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2395 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2396 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2397 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2398 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2399 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2400 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2401 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2402 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2403 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2404 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2405 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2406 .features[FEAT_VMX_SECONDARY_CTLS] =
2407 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2408 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2409 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2410 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2411 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2412 .xlevel = 0x80000008,
2413 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2414 .versions = (X86CPUVersionDefinition[]) {
2415 { .version = 1 },
2416 {
2417 .version = 2,
2418 .alias = "SandyBridge-IBRS",
2419 .props = (PropValue[]) {
2420 { "spec-ctrl", "on" },
2421 { "model-id",
2422 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2423 { /* end of list */ }
2424 }
2425 },
2426 { /* end of list */ }
2427 }
2428 },
2429 {
2430 .name = "IvyBridge",
2431 .level = 0xd,
2432 .vendor = CPUID_VENDOR_INTEL,
2433 .family = 6,
2434 .model = 58,
2435 .stepping = 9,
2436 .features[FEAT_1_EDX] =
2437 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2438 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2439 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2440 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2441 CPUID_DE | CPUID_FP87,
2442 .features[FEAT_1_ECX] =
2443 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2444 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2445 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2446 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2447 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2448 .features[FEAT_7_0_EBX] =
2449 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2450 CPUID_7_0_EBX_ERMS,
2451 .features[FEAT_8000_0001_EDX] =
2452 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2453 CPUID_EXT2_SYSCALL,
2454 .features[FEAT_8000_0001_ECX] =
2455 CPUID_EXT3_LAHF_LM,
2456 .features[FEAT_XSAVE] =
2457 CPUID_XSAVE_XSAVEOPT,
2458 .features[FEAT_6_EAX] =
2459 CPUID_6_EAX_ARAT,
2460 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2461 MSR_VMX_BASIC_TRUE_CTLS,
2462 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2463 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2464 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2465 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2466 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2467 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2468 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2469 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2470 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2471 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2472 .features[FEAT_VMX_EXIT_CTLS] =
2473 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2474 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2475 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2476 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2477 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2478 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2479 MSR_VMX_MISC_STORE_LMA,
2480 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2481 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2482 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2483 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2484 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2485 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2486 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2487 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2488 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2489 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2490 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2491 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2492 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2493 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2494 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2495 .features[FEAT_VMX_SECONDARY_CTLS] =
2496 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2497 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2498 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2499 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2500 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2501 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2502 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2503 VMX_SECONDARY_EXEC_RDRAND_EXITING,
2504 .xlevel = 0x80000008,
2505 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2506 .versions = (X86CPUVersionDefinition[]) {
2507 { .version = 1 },
2508 {
2509 .version = 2,
2510 .alias = "IvyBridge-IBRS",
2511 .props = (PropValue[]) {
2512 { "spec-ctrl", "on" },
2513 { "model-id",
2514 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2515 { /* end of list */ }
2516 }
2517 },
2518 { /* end of list */ }
2519 }
2520 },
2521 {
2522 .name = "Haswell",
2523 .level = 0xd,
2524 .vendor = CPUID_VENDOR_INTEL,
2525 .family = 6,
2526 .model = 60,
2527 .stepping = 4,
2528 .features[FEAT_1_EDX] =
2529 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2530 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2531 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2532 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2533 CPUID_DE | CPUID_FP87,
2534 .features[FEAT_1_ECX] =
2535 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2536 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2537 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2538 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2539 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2540 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2541 .features[FEAT_8000_0001_EDX] =
2542 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2543 CPUID_EXT2_SYSCALL,
2544 .features[FEAT_8000_0001_ECX] =
2545 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2546 .features[FEAT_7_0_EBX] =
2547 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2548 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2549 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2550 CPUID_7_0_EBX_RTM,
2551 .features[FEAT_XSAVE] =
2552 CPUID_XSAVE_XSAVEOPT,
2553 .features[FEAT_6_EAX] =
2554 CPUID_6_EAX_ARAT,
2555 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2556 MSR_VMX_BASIC_TRUE_CTLS,
2557 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2558 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2559 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2560 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2561 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2562 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2563 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2564 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2565 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2566 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2567 .features[FEAT_VMX_EXIT_CTLS] =
2568 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2569 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2570 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2571 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2572 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2573 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2574 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2575 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2576 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2577 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2578 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2579 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2580 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2581 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2582 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2583 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2584 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2585 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2586 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2587 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2588 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2589 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2590 .features[FEAT_VMX_SECONDARY_CTLS] =
2591 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2592 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2593 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2594 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2595 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2596 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2597 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2598 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2599 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2600 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2601 .xlevel = 0x80000008,
2602 .model_id = "Intel Core Processor (Haswell)",
2603 .versions = (X86CPUVersionDefinition[]) {
2604 { .version = 1 },
2605 {
2606 .version = 2,
2607 .alias = "Haswell-noTSX",
2608 .props = (PropValue[]) {
2609 { "hle", "off" },
2610 { "rtm", "off" },
2611 { "stepping", "1" },
2612 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2613 { /* end of list */ }
2614 },
2615 },
2616 {
2617 .version = 3,
2618 .alias = "Haswell-IBRS",
2619 .props = (PropValue[]) {
2620 /* Restore TSX features removed by -v2 above */
2621 { "hle", "on" },
2622 { "rtm", "on" },
2623 /*
2624 * Haswell and Haswell-IBRS had stepping=4 in
2625 * QEMU 4.0 and older
2626 */
2627 { "stepping", "4" },
2628 { "spec-ctrl", "on" },
2629 { "model-id",
2630 "Intel Core Processor (Haswell, IBRS)" },
2631 { /* end of list */ }
2632 }
2633 },
2634 {
2635 .version = 4,
2636 .alias = "Haswell-noTSX-IBRS",
2637 .props = (PropValue[]) {
2638 { "hle", "off" },
2639 { "rtm", "off" },
2640 /* spec-ctrl was already enabled by -v3 above */
2641 { "stepping", "1" },
2642 { "model-id",
2643 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2644 { /* end of list */ }
2645 }
2646 },
2647 { /* end of list */ }
2648 }
2649 },
2650 {
2651 .name = "Broadwell",
2652 .level = 0xd,
2653 .vendor = CPUID_VENDOR_INTEL,
2654 .family = 6,
2655 .model = 61,
2656 .stepping = 2,
2657 .features[FEAT_1_EDX] =
2658 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2659 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2660 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2661 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2662 CPUID_DE | CPUID_FP87,
2663 .features[FEAT_1_ECX] =
2664 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2665 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2666 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2667 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2668 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2669 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2670 .features[FEAT_8000_0001_EDX] =
2671 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2672 CPUID_EXT2_SYSCALL,
2673 .features[FEAT_8000_0001_ECX] =
2674 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2675 .features[FEAT_7_0_EBX] =
2676 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2677 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2678 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2679 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2680 CPUID_7_0_EBX_SMAP,
2681 .features[FEAT_XSAVE] =
2682 CPUID_XSAVE_XSAVEOPT,
2683 .features[FEAT_6_EAX] =
2684 CPUID_6_EAX_ARAT,
2685 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2686 MSR_VMX_BASIC_TRUE_CTLS,
2687 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2688 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2689 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2690 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2691 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2692 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2693 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2694 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2695 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2696 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2697 .features[FEAT_VMX_EXIT_CTLS] =
2698 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2699 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2700 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2701 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2702 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2703 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2704 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2705 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2706 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2707 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2708 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2709 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2710 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2711 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2712 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2713 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2714 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2715 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2716 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2717 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2718 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2719 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2720 .features[FEAT_VMX_SECONDARY_CTLS] =
2721 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2722 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2723 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2724 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2725 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2726 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2727 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2728 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2729 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2730 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2731 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2732 .xlevel = 0x80000008,
2733 .model_id = "Intel Core Processor (Broadwell)",
2734 .versions = (X86CPUVersionDefinition[]) {
2735 { .version = 1 },
2736 {
2737 .version = 2,
2738 .alias = "Broadwell-noTSX",
2739 .props = (PropValue[]) {
2740 { "hle", "off" },
2741 { "rtm", "off" },
2742 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2743 { /* end of list */ }
2744 },
2745 },
2746 {
2747 .version = 3,
2748 .alias = "Broadwell-IBRS",
2749 .props = (PropValue[]) {
2750 /* Restore TSX features removed by -v2 above */
2751 { "hle", "on" },
2752 { "rtm", "on" },
2753 { "spec-ctrl", "on" },
2754 { "model-id",
2755 "Intel Core Processor (Broadwell, IBRS)" },
2756 { /* end of list */ }
2757 }
2758 },
2759 {
2760 .version = 4,
2761 .alias = "Broadwell-noTSX-IBRS",
2762 .props = (PropValue[]) {
2763 { "hle", "off" },
2764 { "rtm", "off" },
2765 /* spec-ctrl was already enabled by -v3 above */
2766 { "model-id",
2767 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2768 { /* end of list */ }
2769 }
2770 },
2771 { /* end of list */ }
2772 }
2773 },
2774 {
2775 .name = "Skylake-Client",
2776 .level = 0xd,
2777 .vendor = CPUID_VENDOR_INTEL,
2778 .family = 6,
2779 .model = 94,
2780 .stepping = 3,
2781 .features[FEAT_1_EDX] =
2782 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2783 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2784 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2785 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2786 CPUID_DE | CPUID_FP87,
2787 .features[FEAT_1_ECX] =
2788 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2789 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2790 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2791 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2792 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2793 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2794 .features[FEAT_8000_0001_EDX] =
2795 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2796 CPUID_EXT2_SYSCALL,
2797 .features[FEAT_8000_0001_ECX] =
2798 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2799 .features[FEAT_7_0_EBX] =
2800 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2801 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2802 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2803 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2804 CPUID_7_0_EBX_SMAP,
2805 /* Missing: XSAVES (not supported by some Linux versions,
2806 * including v4.1 to v4.12).
2807 * KVM doesn't yet expose any XSAVES state save component,
2808 * and the only one defined in Skylake (processor tracing)
2809 * probably will block migration anyway.
2810 */
2811 .features[FEAT_XSAVE] =
2812 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2813 CPUID_XSAVE_XGETBV1,
2814 .features[FEAT_6_EAX] =
2815 CPUID_6_EAX_ARAT,
2816 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2817 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2818 MSR_VMX_BASIC_TRUE_CTLS,
2819 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2820 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2821 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2822 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2823 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2824 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2825 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2826 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2827 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2828 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2829 .features[FEAT_VMX_EXIT_CTLS] =
2830 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2831 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2832 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2833 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2834 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2835 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2836 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2837 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2838 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2839 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2840 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2841 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2842 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2843 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2844 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2845 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2846 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2847 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2848 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2849 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2850 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2851 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2852 .features[FEAT_VMX_SECONDARY_CTLS] =
2853 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2854 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2855 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2856 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2857 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2858 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2859 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2860 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2861 .xlevel = 0x80000008,
2862 .model_id = "Intel Core Processor (Skylake)",
2863 .versions = (X86CPUVersionDefinition[]) {
2864 { .version = 1 },
2865 {
2866 .version = 2,
2867 .alias = "Skylake-Client-IBRS",
2868 .props = (PropValue[]) {
2869 { "spec-ctrl", "on" },
2870 { "model-id",
2871 "Intel Core Processor (Skylake, IBRS)" },
2872 { /* end of list */ }
2873 }
2874 },
2875 {
2876 .version = 3,
2877 .alias = "Skylake-Client-noTSX-IBRS",
2878 .props = (PropValue[]) {
2879 { "hle", "off" },
2880 { "rtm", "off" },
2881 { "model-id",
2882 "Intel Core Processor (Skylake, IBRS, no TSX)" },
2883 { /* end of list */ }
2884 }
2885 },
2886 { /* end of list */ }
2887 }
2888 },
2889 {
2890 .name = "Skylake-Server",
2891 .level = 0xd,
2892 .vendor = CPUID_VENDOR_INTEL,
2893 .family = 6,
2894 .model = 85,
2895 .stepping = 4,
2896 .features[FEAT_1_EDX] =
2897 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2898 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2899 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2900 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2901 CPUID_DE | CPUID_FP87,
2902 .features[FEAT_1_ECX] =
2903 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2904 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2905 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2906 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2907 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2908 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2909 .features[FEAT_8000_0001_EDX] =
2910 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2911 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2912 .features[FEAT_8000_0001_ECX] =
2913 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2914 .features[FEAT_7_0_EBX] =
2915 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2916 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2917 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2918 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2919 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2920 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2921 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2922 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2923 .features[FEAT_7_0_ECX] =
2924 CPUID_7_0_ECX_PKU,
2925 /* Missing: XSAVES (not supported by some Linux versions,
2926 * including v4.1 to v4.12).
2927 * KVM doesn't yet expose any XSAVES state save component,
2928 * and the only one defined in Skylake (processor tracing)
2929 * probably will block migration anyway.
2930 */
2931 .features[FEAT_XSAVE] =
2932 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2933 CPUID_XSAVE_XGETBV1,
2934 .features[FEAT_6_EAX] =
2935 CPUID_6_EAX_ARAT,
2936 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2937 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2938 MSR_VMX_BASIC_TRUE_CTLS,
2939 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2940 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2941 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2942 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2943 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2944 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2945 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2946 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2947 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2948 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2949 .features[FEAT_VMX_EXIT_CTLS] =
2950 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2951 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2952 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2953 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2954 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2955 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2956 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2957 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2958 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2959 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2960 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2961 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2962 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2963 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2964 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2965 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2966 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2967 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2968 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2969 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2970 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2971 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2972 .features[FEAT_VMX_SECONDARY_CTLS] =
2973 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2974 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2975 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2976 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2977 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2978 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2979 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2980 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2981 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2982 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2983 .xlevel = 0x80000008,
2984 .model_id = "Intel Xeon Processor (Skylake)",
2985 .versions = (X86CPUVersionDefinition[]) {
2986 { .version = 1 },
2987 {
2988 .version = 2,
2989 .alias = "Skylake-Server-IBRS",
2990 .props = (PropValue[]) {
2991 /* clflushopt was not added to Skylake-Server-IBRS */
2992 /* TODO: add -v3 including clflushopt */
2993 { "clflushopt", "off" },
2994 { "spec-ctrl", "on" },
2995 { "model-id",
2996 "Intel Xeon Processor (Skylake, IBRS)" },
2997 { /* end of list */ }
2998 }
2999 },
3000 {
3001 .version = 3,
3002 .alias = "Skylake-Server-noTSX-IBRS",
3003 .props = (PropValue[]) {
3004 { "hle", "off" },
3005 { "rtm", "off" },
3006 { "model-id",
3007 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3008 { /* end of list */ }
3009 }
3010 },
3011 {
3012 .version = 4,
3013 .props = (PropValue[]) {
3014 { "vmx-eptp-switching", "on" },
3015 { /* end of list */ }
3016 }
3017 },
3018 { /* end of list */ }
3019 }
3020 },
3021 {
3022 .name = "Cascadelake-Server",
3023 .level = 0xd,
3024 .vendor = CPUID_VENDOR_INTEL,
3025 .family = 6,
3026 .model = 85,
3027 .stepping = 6,
3028 .features[FEAT_1_EDX] =
3029 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3030 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3031 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3032 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3033 CPUID_DE | CPUID_FP87,
3034 .features[FEAT_1_ECX] =
3035 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3036 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3037 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3038 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3039 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3040 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3041 .features[FEAT_8000_0001_EDX] =
3042 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3043 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3044 .features[FEAT_8000_0001_ECX] =
3045 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3046 .features[FEAT_7_0_EBX] =
3047 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3048 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3049 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3050 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3051 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3052 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3053 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3054 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3055 .features[FEAT_7_0_ECX] =
3056 CPUID_7_0_ECX_PKU |
3057 CPUID_7_0_ECX_AVX512VNNI,
3058 .features[FEAT_7_0_EDX] =
3059 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3060 /* Missing: XSAVES (not supported by some Linux versions,
3061 * including v4.1 to v4.12).
3062 * KVM doesn't yet expose any XSAVES state save component,
3063 * and the only one defined in Skylake (processor tracing)
3064 * probably will block migration anyway.
3065 */
3066 .features[FEAT_XSAVE] =
3067 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3068 CPUID_XSAVE_XGETBV1,
3069 .features[FEAT_6_EAX] =
3070 CPUID_6_EAX_ARAT,
3071 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3072 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3073 MSR_VMX_BASIC_TRUE_CTLS,
3074 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3075 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3076 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3077 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3078 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3079 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3080 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3081 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3082 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3083 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3084 .features[FEAT_VMX_EXIT_CTLS] =
3085 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3086 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3087 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3088 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3089 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3090 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3091 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3092 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3093 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3094 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3095 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3096 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3097 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3098 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3099 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3100 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3101 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3102 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3103 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3104 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3105 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3106 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3107 .features[FEAT_VMX_SECONDARY_CTLS] =
3108 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3109 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3110 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3111 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3112 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3113 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3114 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3115 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3116 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3117 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3118 .xlevel = 0x80000008,
3119 .model_id = "Intel Xeon Processor (Cascadelake)",
3120 .versions = (X86CPUVersionDefinition[]) {
3121 { .version = 1 },
3122 { .version = 2,
3123 .note = "ARCH_CAPABILITIES",
3124 .props = (PropValue[]) {
3125 { "arch-capabilities", "on" },
3126 { "rdctl-no", "on" },
3127 { "ibrs-all", "on" },
3128 { "skip-l1dfl-vmentry", "on" },
3129 { "mds-no", "on" },
3130 { /* end of list */ }
3131 },
3132 },
3133 { .version = 3,
3134 .alias = "Cascadelake-Server-noTSX",
3135 .note = "ARCH_CAPABILITIES, no TSX",
3136 .props = (PropValue[]) {
3137 { "hle", "off" },
3138 { "rtm", "off" },
3139 { /* end of list */ }
3140 },
3141 },
3142 { .version = 4,
3143 .note = "ARCH_CAPABILITIES, no TSX",
3144 .props = (PropValue[]) {
3145 { "vmx-eptp-switching", "on" },
3146 { /* end of list */ }
3147 },
3148 },
3149 { /* end of list */ }
3150 }
3151 },
3152 {
3153 .name = "Cooperlake",
3154 .level = 0xd,
3155 .vendor = CPUID_VENDOR_INTEL,
3156 .family = 6,
3157 .model = 85,
3158 .stepping = 10,
3159 .features[FEAT_1_EDX] =
3160 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3161 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3162 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3163 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3164 CPUID_DE | CPUID_FP87,
3165 .features[FEAT_1_ECX] =
3166 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3167 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3168 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3169 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3170 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3171 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3172 .features[FEAT_8000_0001_EDX] =
3173 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3174 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3175 .features[FEAT_8000_0001_ECX] =
3176 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3177 .features[FEAT_7_0_EBX] =
3178 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3179 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3180 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3181 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3182 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3183 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3184 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3185 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3186 .features[FEAT_7_0_ECX] =
3187 CPUID_7_0_ECX_PKU |
3188 CPUID_7_0_ECX_AVX512VNNI,
3189 .features[FEAT_7_0_EDX] =
3190 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3191 CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3192 .features[FEAT_ARCH_CAPABILITIES] =
3193 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3194 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3195 MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3196 .features[FEAT_7_1_EAX] =
3197 CPUID_7_1_EAX_AVX512_BF16,
3198 /*
3199 * Missing: XSAVES (not supported by some Linux versions,
3200 * including v4.1 to v4.12).
3201 * KVM doesn't yet expose any XSAVES state save component,
3202 * and the only one defined in Skylake (processor tracing)
3203 * probably will block migration anyway.
3204 */
3205 .features[FEAT_XSAVE] =
3206 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3207 CPUID_XSAVE_XGETBV1,
3208 .features[FEAT_6_EAX] =
3209 CPUID_6_EAX_ARAT,
3210 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3211 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3212 MSR_VMX_BASIC_TRUE_CTLS,
3213 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3214 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3215 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3216 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3217 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3218 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3219 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3220 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3221 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3222 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3223 .features[FEAT_VMX_EXIT_CTLS] =
3224 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3225 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3226 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3227 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3228 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3229 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3230 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3231 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3232 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3233 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3234 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3235 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3236 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3237 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3238 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3239 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3240 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3241 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3242 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3243 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3244 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3245 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3246 .features[FEAT_VMX_SECONDARY_CTLS] =
3247 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3248 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3249 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3250 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3251 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3252 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3253 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3254 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3255 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3256 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3257 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3258 .xlevel = 0x80000008,
3259 .model_id = "Intel Xeon Processor (Cooperlake)",
3260 },
3261 {
3262 .name = "Icelake-Client",
3263 .level = 0xd,
3264 .vendor = CPUID_VENDOR_INTEL,
3265 .family = 6,
3266 .model = 126,
3267 .stepping = 0,
3268 .features[FEAT_1_EDX] =
3269 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3270 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3271 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3272 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3273 CPUID_DE | CPUID_FP87,
3274 .features[FEAT_1_ECX] =
3275 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3276 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3277 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3278 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3279 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3280 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3281 .features[FEAT_8000_0001_EDX] =
3282 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3283 CPUID_EXT2_SYSCALL,
3284 .features[FEAT_8000_0001_ECX] =
3285 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3286 .features[FEAT_8000_0008_EBX] =
3287 CPUID_8000_0008_EBX_WBNOINVD,
3288 .features[FEAT_7_0_EBX] =
3289 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3290 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3291 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3292 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3293 CPUID_7_0_EBX_SMAP,
3294 .features[FEAT_7_0_ECX] =
3295 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3296 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3297 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3298 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3299 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3300 .features[FEAT_7_0_EDX] =
3301 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3302 /* Missing: XSAVES (not supported by some Linux versions,
3303 * including v4.1 to v4.12).
3304 * KVM doesn't yet expose any XSAVES state save component,
3305 * and the only one defined in Skylake (processor tracing)
3306 * probably will block migration anyway.
3307 */
3308 .features[FEAT_XSAVE] =
3309 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3310 CPUID_XSAVE_XGETBV1,
3311 .features[FEAT_6_EAX] =
3312 CPUID_6_EAX_ARAT,
3313 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3314 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3315 MSR_VMX_BASIC_TRUE_CTLS,
3316 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3317 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3318 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3319 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3320 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3321 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3322 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3323 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3324 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3325 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3326 .features[FEAT_VMX_EXIT_CTLS] =
3327 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3328 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3329 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3330 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3331 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3332 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3333 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3334 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3335 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3336 VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3337 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3338 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3339 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3340 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3341 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3342 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3343 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3344 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3345 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3346 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3347 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3348 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3349 .features[FEAT_VMX_SECONDARY_CTLS] =
3350 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3351 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3352 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3353 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3354 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3355 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3356 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3357 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3358 .xlevel = 0x80000008,
3359 .model_id = "Intel Core Processor (Icelake)",
3360 .versions = (X86CPUVersionDefinition[]) {
3361 {
3362 .version = 1,
3363 .note = "deprecated"
3364 },
3365 {
3366 .version = 2,
3367 .note = "no TSX, deprecated",
3368 .alias = "Icelake-Client-noTSX",
3369 .props = (PropValue[]) {
3370 { "hle", "off" },
3371 { "rtm", "off" },
3372 { /* end of list */ }
3373 },
3374 },
3375 { /* end of list */ }
3376 },
3377 .deprecation_note = "use Icelake-Server instead"
3378 },
3379 {
3380 .name = "Icelake-Server",
3381 .level = 0xd,
3382 .vendor = CPUID_VENDOR_INTEL,
3383 .family = 6,
3384 .model = 134,
3385 .stepping = 0,
3386 .features[FEAT_1_EDX] =
3387 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3388 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3389 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3390 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3391 CPUID_DE | CPUID_FP87,
3392 .features[FEAT_1_ECX] =
3393 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3394 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3395 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3396 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3397 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3398 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3399 .features[FEAT_8000_0001_EDX] =
3400 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3401 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3402 .features[FEAT_8000_0001_ECX] =
3403 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3404 .features[FEAT_8000_0008_EBX] =
3405 CPUID_8000_0008_EBX_WBNOINVD,
3406 .features[FEAT_7_0_EBX] =
3407 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3408 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3409 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3410 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3411 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3412 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3413 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3414 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3415 .features[FEAT_7_0_ECX] =
3416 CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3417 CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3418 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3419 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3420 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3421 .features[FEAT_7_0_EDX] =
3422 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3423 /* Missing: XSAVES (not supported by some Linux versions,
3424 * including v4.1 to v4.12).
3425 * KVM doesn't yet expose any XSAVES state save component,
3426 * and the only one defined in Skylake (processor tracing)
3427 * probably will block migration anyway.
3428 */
3429 .features[FEAT_XSAVE] =
3430 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3431 CPUID_XSAVE_XGETBV1,
3432 .features[FEAT_6_EAX] =
3433 CPUID_6_EAX_ARAT,
3434 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3435 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3436 MSR_VMX_BASIC_TRUE_CTLS,
3437 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3438 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3439 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3440 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3441 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3442 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3443 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3444 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3445 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3446 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3447 .features[FEAT_VMX_EXIT_CTLS] =
3448 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3449 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3450 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3451 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3452 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3453 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3454 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3455 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3456 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3457 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3458 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3459 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3460 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3461 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3462 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3463 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3464 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3465 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3466 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3467 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3468 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3469 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3470 .features[FEAT_VMX_SECONDARY_CTLS] =
3471 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3472 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3473 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3474 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3475 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3476 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3477 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3478 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3479 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3480 .xlevel = 0x80000008,
3481 .model_id = "Intel Xeon Processor (Icelake)",
3482 .versions = (X86CPUVersionDefinition[]) {
3483 { .version = 1 },
3484 {
3485 .version = 2,
3486 .note = "no TSX",
3487 .alias = "Icelake-Server-noTSX",
3488 .props = (PropValue[]) {
3489 { "hle", "off" },
3490 { "rtm", "off" },
3491 { /* end of list */ }
3492 },
3493 },
3494 {
3495 .version = 3,
3496 .props = (PropValue[]) {
3497 { "arch-capabilities", "on" },
3498 { "rdctl-no", "on" },
3499 { "ibrs-all", "on" },
3500 { "skip-l1dfl-vmentry", "on" },
3501 { "mds-no", "on" },
3502 { "pschange-mc-no", "on" },
3503 { "taa-no", "on" },
3504 { /* end of list */ }
3505 },
3506 },
3507 {
3508 .version = 4,
3509 .props = (PropValue[]) {
3510 { "sha-ni", "on" },
3511 { "avx512ifma", "on" },
3512 { "rdpid", "on" },
3513 { "fsrm", "on" },
3514 { "vmx-rdseed-exit", "on" },
3515 { "vmx-pml", "on" },
3516 { "vmx-eptp-switching", "on" },
3517 { "model", "106" },
3518 { /* end of list */ }
3519 },
3520 },
3521 { /* end of list */ }
3522 }
3523 },
3524 {
3525 .name = "Denverton",
3526 .level = 21,
3527 .vendor = CPUID_VENDOR_INTEL,
3528 .family = 6,
3529 .model = 95,
3530 .stepping = 1,
3531 .features[FEAT_1_EDX] =
3532 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3533 CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3534 CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3535 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3536 CPUID_SSE | CPUID_SSE2,
3537 .features[FEAT_1_ECX] =
3538 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3539 CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3540 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3541 CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3542 CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3543 .features[FEAT_8000_0001_EDX] =
3544 CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3545 CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3546 .features[FEAT_8000_0001_ECX] =
3547 CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3548 .features[FEAT_7_0_EBX] =
3549 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3550 CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3551 CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3552 .features[FEAT_7_0_EDX] =
3553 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3554 CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3555 /*
3556 * Missing: XSAVES (not supported by some Linux versions,
3557 * including v4.1 to v4.12).
3558 * KVM doesn't yet expose any XSAVES state save component,
3559 * and the only one defined in Skylake (processor tracing)
3560 * probably will block migration anyway.
3561 */
3562 .features[FEAT_XSAVE] =
3563 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3564 .features[FEAT_6_EAX] =
3565 CPUID_6_EAX_ARAT,
3566 .features[FEAT_ARCH_CAPABILITIES] =
3567 MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3568 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3569 MSR_VMX_BASIC_TRUE_CTLS,
3570 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3571 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3572 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3573 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3574 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3575 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3576 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3577 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3578 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3579 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3580 .features[FEAT_VMX_EXIT_CTLS] =
3581 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3582 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3583 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3584 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3585 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3586 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3587 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3588 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3589 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3590 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3591 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3592 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3593 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3594 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3595 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3596 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3597 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3598 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3599 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3600 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3601 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3602 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3603 .features[FEAT_VMX_SECONDARY_CTLS] =
3604 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3605 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3606 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3607 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3608 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3609 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3610 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3611 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3612 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3613 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3614 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3615 .xlevel = 0x80000008,
3616 .model_id = "Intel Atom Processor (Denverton)",
3617 .versions = (X86CPUVersionDefinition[]) {
3618 { .version = 1 },
3619 {
3620 .version = 2,
3621 .note = "no MPX, no MONITOR",
3622 .props = (PropValue[]) {
3623 { "monitor", "off" },
3624 { "mpx", "off" },
3625 { /* end of list */ },
3626 },
3627 },
3628 { /* end of list */ },
3629 },
3630 },
3631 {
3632 .name = "Snowridge",
3633 .level = 27,
3634 .vendor = CPUID_VENDOR_INTEL,
3635 .family = 6,
3636 .model = 134,
3637 .stepping = 1,
3638 .features[FEAT_1_EDX] =
3639 /* missing: CPUID_PN CPUID_IA64 */
3640 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3641 CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3642 CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3643 CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3644 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3645 CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3646 CPUID_MMX |
3647 CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3648 .features[FEAT_1_ECX] =
3649 CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3650 CPUID_EXT_SSSE3 |
3651 CPUID_EXT_CX16 |
3652 CPUID_EXT_SSE41 |
3653 CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3654 CPUID_EXT_POPCNT |
3655 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3656 CPUID_EXT_RDRAND,
3657 .features[FEAT_8000_0001_EDX] =
3658 CPUID_EXT2_SYSCALL |
3659 CPUID_EXT2_NX |
3660 CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3661 CPUID_EXT2_LM,
3662 .features[FEAT_8000_0001_ECX] =
3663 CPUID_EXT3_LAHF_LM |
3664 CPUID_EXT3_3DNOWPREFETCH,
3665 .features[FEAT_7_0_EBX] =
3666 CPUID_7_0_EBX_FSGSBASE |
3667 CPUID_7_0_EBX_SMEP |
3668 CPUID_7_0_EBX_ERMS |
3669 CPUID_7_0_EBX_MPX | /* missing bits 13, 15 */
3670 CPUID_7_0_EBX_RDSEED |
3671 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3672 CPUID_7_0_EBX_CLWB |
3673 CPUID_7_0_EBX_SHA_NI,
3674 .features[FEAT_7_0_ECX] =
3675 CPUID_7_0_ECX_UMIP |
3676 /* missing bit 5 */
3677 CPUID_7_0_ECX_GFNI |
3678 CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3679 CPUID_7_0_ECX_MOVDIR64B,
3680 .features[FEAT_7_0_EDX] =
3681 CPUID_7_0_EDX_SPEC_CTRL |
3682 CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3683 CPUID_7_0_EDX_CORE_CAPABILITY,
3684 .features[FEAT_CORE_CAPABILITY] =
3685 MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3686 /*
3687 * Missing: XSAVES (not supported by some Linux versions,
3688 * including v4.1 to v4.12).
3689 * KVM doesn't yet expose any XSAVES state save component,
3690 * and the only one defined in Skylake (processor tracing)
3691 * probably will block migration anyway.
3692 */
3693 .features[FEAT_XSAVE] =
3694 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3695 CPUID_XSAVE_XGETBV1,
3696 .features[FEAT_6_EAX] =
3697 CPUID_6_EAX_ARAT,
3698 .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3699 MSR_VMX_BASIC_TRUE_CTLS,
3700 .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3701 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3702 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3703 .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3704 MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3705 MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3706 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3707 MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3708 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3709 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3710 .features[FEAT_VMX_EXIT_CTLS] =
3711 VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3712 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3713 VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3714 VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3715 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3716 .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3717 MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3718 .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3719 VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3720 VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3721 .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3722 VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3723 VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3724 VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3725 VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3726 VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3727 VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3728 VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3729 VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3730 VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3731 VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3732 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3733 .features[FEAT_VMX_SECONDARY_CTLS] =
3734 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3735 VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3736 VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3737 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3738 VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3739 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3740 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3741 VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3742 VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3743 VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3744 .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3745 .xlevel = 0x80000008,
3746 .model_id = "Intel Atom Processor (SnowRidge)",
3747 .versions = (X86CPUVersionDefinition[]) {
3748 { .version = 1 },
3749 {
3750 .version = 2,
3751 .props = (PropValue[]) {
3752 { "mpx", "off" },
3753 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3754 { /* end of list */ },
3755 },
3756 },
3757 { /* end of list */ },
3758 },
3759 },
3760 {
3761 .name = "KnightsMill",
3762 .level = 0xd,
3763 .vendor = CPUID_VENDOR_INTEL,
3764 .family = 6,
3765 .model = 133,
3766 .stepping = 0,
3767 .features[FEAT_1_EDX] =
3768 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3769 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3770 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3771 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3772 CPUID_PSE | CPUID_DE | CPUID_FP87,
3773 .features[FEAT_1_ECX] =
3774 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3775 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3776 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3777 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3778 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3779 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3780 .features[FEAT_8000_0001_EDX] =
3781 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3782 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3783 .features[FEAT_8000_0001_ECX] =
3784 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3785 .features[FEAT_7_0_EBX] =
3786 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3787 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3788 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3789 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3790 CPUID_7_0_EBX_AVX512ER,
3791 .features[FEAT_7_0_ECX] =
3792 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3793 .features[FEAT_7_0_EDX] =
3794 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3795 .features[FEAT_XSAVE] =
3796 CPUID_XSAVE_XSAVEOPT,
3797 .features[FEAT_6_EAX] =
3798 CPUID_6_EAX_ARAT,
3799 .xlevel = 0x80000008,
3800 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3801 },
3802 {
3803 .name = "Opteron_G1",
3804 .level = 5,
3805 .vendor = CPUID_VENDOR_AMD,
3806 .family = 15,
3807 .model = 6,
3808 .stepping = 1,
3809 .features[FEAT_1_EDX] =
3810 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3811 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3812 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3813 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3814 CPUID_DE | CPUID_FP87,
3815 .features[FEAT_1_ECX] =
3816 CPUID_EXT_SSE3,
3817 .features[FEAT_8000_0001_EDX] =
3818 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3819 .xlevel = 0x80000008,
3820 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3821 },
3822 {
3823 .name = "Opteron_G2",
3824 .level = 5,
3825 .vendor = CPUID_VENDOR_AMD,
3826 .family = 15,
3827 .model = 6,
3828 .stepping = 1,
3829 .features[FEAT_1_EDX] =
3830 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3831 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3832 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3833 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3834 CPUID_DE | CPUID_FP87,
3835 .features[FEAT_1_ECX] =
3836 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
3837 .features[FEAT_8000_0001_EDX] =
3838 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3839 .features[FEAT_8000_0001_ECX] =
3840 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3841 .xlevel = 0x80000008,
3842 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3843 },
3844 {
3845 .name = "Opteron_G3",
3846 .level = 5,
3847 .vendor = CPUID_VENDOR_AMD,
3848 .family = 16,
3849 .model = 2,
3850 .stepping = 3,
3851 .features[FEAT_1_EDX] =
3852 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3853 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3854 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3855 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3856 CPUID_DE | CPUID_FP87,
3857 .features[FEAT_1_ECX] =
3858 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3859 CPUID_EXT_SSE3,
3860 .features[FEAT_8000_0001_EDX] =
3861 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3862 CPUID_EXT2_RDTSCP,
3863 .features[FEAT_8000_0001_ECX] =
3864 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3865 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3866 .xlevel = 0x80000008,
3867 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3868 },
3869 {
3870 .name = "Opteron_G4",
3871 .level = 0xd,
3872 .vendor = CPUID_VENDOR_AMD,
3873 .family = 21,
3874 .model = 1,
3875 .stepping = 2,
3876 .features[FEAT_1_EDX] =
3877 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3878 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3879 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3880 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3881 CPUID_DE | CPUID_FP87,
3882 .features[FEAT_1_ECX] =
3883 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3884 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3885 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3886 CPUID_EXT_SSE3,
3887 .features[FEAT_8000_0001_EDX] =
3888 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3889 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3890 .features[FEAT_8000_0001_ECX] =
3891 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3892 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3893 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3894 CPUID_EXT3_LAHF_LM,
3895 .features[FEAT_SVM] =
3896 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3897 /* no xsaveopt! */
3898 .xlevel = 0x8000001A,
3899 .model_id = "AMD Opteron 62xx class CPU",
3900 },
3901 {
3902 .name = "Opteron_G5",
3903 .level = 0xd,
3904 .vendor = CPUID_VENDOR_AMD,
3905 .family = 21,
3906 .model = 2,
3907 .stepping = 0,
3908 .features[FEAT_1_EDX] =
3909 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3910 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3911 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3912 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3913 CPUID_DE | CPUID_FP87,
3914 .features[FEAT_1_ECX] =
3915 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
3916 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3917 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3918 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3919 .features[FEAT_8000_0001_EDX] =
3920 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3921 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3922 .features[FEAT_8000_0001_ECX] =
3923 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3924 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3925 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3926 CPUID_EXT3_LAHF_LM,
3927 .features[FEAT_SVM] =
3928 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3929 /* no xsaveopt! */
3930 .xlevel = 0x8000001A,
3931 .model_id = "AMD Opteron 63xx class CPU",
3932 },
3933 {
3934 .name = "EPYC",
3935 .level = 0xd,
3936 .vendor = CPUID_VENDOR_AMD,
3937 .family = 23,
3938 .model = 1,
3939 .stepping = 2,
3940 .features[FEAT_1_EDX] =
3941 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3942 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3943 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3944 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3945 CPUID_VME | CPUID_FP87,
3946 .features[FEAT_1_ECX] =
3947 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3948 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
3949 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3950 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3951 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3952 .features[FEAT_8000_0001_EDX] =
3953 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3954 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3955 CPUID_EXT2_SYSCALL,
3956 .features[FEAT_8000_0001_ECX] =
3957 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3958 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3959 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3960 CPUID_EXT3_TOPOEXT,
3961 .features[FEAT_7_0_EBX] =
3962 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3963 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3964 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3965 CPUID_7_0_EBX_SHA_NI,
3966 .features[FEAT_XSAVE] =
3967 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3968 CPUID_XSAVE_XGETBV1,
3969 .features[FEAT_6_EAX] =
3970 CPUID_6_EAX_ARAT,
3971 .features[FEAT_SVM] =
3972 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3973 .xlevel = 0x8000001E,
3974 .model_id = "AMD EPYC Processor",
3975 .cache_info = &epyc_cache_info,
3976 .versions = (X86CPUVersionDefinition[]) {
3977 { .version = 1 },
3978 {
3979 .version = 2,
3980 .alias = "EPYC-IBPB",
3981 .props = (PropValue[]) {
3982 { "ibpb", "on" },
3983 { "model-id",
3984 "AMD EPYC Processor (with IBPB)" },
3985 { /* end of list */ }
3986 }
3987 },
3988 {
3989 .version = 3,
3990 .props = (PropValue[]) {
3991 { "ibpb", "on" },
3992 { "perfctr-core", "on" },
3993 { "clzero", "on" },
3994 { "xsaveerptr", "on" },
3995 { "xsaves", "on" },
3996 { "model-id",
3997 "AMD EPYC Processor" },
3998 { /* end of list */ }
3999 }
4000 },
4001 { /* end of list */ }
4002 }
4003 },
4004 {
4005 .name = "Dhyana",
4006 .level = 0xd,
4007 .vendor = CPUID_VENDOR_HYGON,
4008 .family = 24,
4009 .model = 0,
4010 .stepping = 1,
4011 .features[FEAT_1_EDX] =
4012 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4013 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4014 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4015 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4016 CPUID_VME | CPUID_FP87,
4017 .features[FEAT_1_ECX] =
4018 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4019 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4020 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4021 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4022 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4023 .features[FEAT_8000_0001_EDX] =
4024 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4025 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4026 CPUID_EXT2_SYSCALL,
4027 .features[FEAT_8000_0001_ECX] =
4028 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4029 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4030 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4031 CPUID_EXT3_TOPOEXT,
4032 .features[FEAT_8000_0008_EBX] =
4033 CPUID_8000_0008_EBX_IBPB,
4034 .features[FEAT_7_0_EBX] =
4035 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4036 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4037 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4038 /*
4039 * Missing: XSAVES (not supported by some Linux versions,
4040 * including v4.1 to v4.12).
4041 * KVM doesn't yet expose any XSAVES state save component.
4042 */
4043 .features[FEAT_XSAVE] =
4044 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4045 CPUID_XSAVE_XGETBV1,
4046 .features[FEAT_6_EAX] =
4047 CPUID_6_EAX_ARAT,
4048 .features[FEAT_SVM] =
4049 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4050 .xlevel = 0x8000001E,
4051 .model_id = "Hygon Dhyana Processor",
4052 .cache_info = &epyc_cache_info,
4053 },
4054 {
4055 .name = "EPYC-Rome",
4056 .level = 0xd,
4057 .vendor = CPUID_VENDOR_AMD,
4058 .family = 23,
4059 .model = 49,
4060 .stepping = 0,
4061 .features[FEAT_1_EDX] =
4062 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4063 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4064 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4065 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4066 CPUID_VME | CPUID_FP87,
4067 .features[FEAT_1_ECX] =
4068 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4069 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
4070 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4071 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4072 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4073 .features[FEAT_8000_0001_EDX] =
4074 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4075 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4076 CPUID_EXT2_SYSCALL,
4077 .features[FEAT_8000_0001_ECX] =
4078 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4079 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4080 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4081 CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4082 .features[FEAT_8000_0008_EBX] =
4083 CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4084 CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4085 CPUID_8000_0008_EBX_STIBP,
4086 .features[FEAT_7_0_EBX] =
4087 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4088 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4089 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4090 CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4091 .features[FEAT_7_0_ECX] =
4092 CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4093 .features[FEAT_XSAVE] =
4094 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4095 CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4096 .features[FEAT_6_EAX] =
4097 CPUID_6_EAX_ARAT,
4098 .features[FEAT_SVM] =
4099 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4100 .xlevel = 0x8000001E,
4101 .model_id = "AMD EPYC-Rome Processor",
4102 .cache_info = &epyc_rome_cache_info,
4103 },
4104 };
4105
4106 /* KVM-specific features that are automatically added/removed
4107 * from all CPU models when KVM is enabled.
4108 */
4109 static PropValue kvm_default_props[] = {
4110 { "kvmclock", "on" },
4111 { "kvm-nopiodelay", "on" },
4112 { "kvm-asyncpf", "on" },
4113 { "kvm-steal-time", "on" },
4114 { "kvm-pv-eoi", "on" },
4115 { "kvmclock-stable-bit", "on" },
4116 { "x2apic", "on" },
4117 { "kvm-msi-ext-dest-id", "off" },
4118 { "acpi", "off" },
4119 { "monitor", "off" },
4120 { "svm", "off" },
4121 { NULL, NULL },
4122 };
4123
4124 /* TCG-specific defaults that override all CPU models when using TCG
4125 */
4126 static PropValue tcg_default_props[] = {
4127 { "vme", "off" },
4128 { NULL, NULL },
4129 };
4130
4131
4132 /*
4133 * We resolve CPU model aliases using -v1 when using "-machine
4134 * none", but this is just for compatibility while libvirt isn't
4135 * adapted to resolve CPU model versions before creating VMs.
4136 * See "Runnability guarantee of CPU models" at
4137 * docs/system/deprecated.rst.
4138 */
4139 X86CPUVersion default_cpu_version = 1;
4140
4141 void x86_cpu_set_default_version(X86CPUVersion version)
4142 {
4143 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4144 assert(version != CPU_VERSION_AUTO);
4145 default_cpu_version = version;
4146 }
4147
4148 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4149 {
4150 int v = 0;
4151 const X86CPUVersionDefinition *vdef =
4152 x86_cpu_def_get_versions(model->cpudef);
4153 while (vdef->version) {
4154 v = vdef->version;
4155 vdef++;
4156 }
4157 return v;
4158 }
4159
4160 /* Return the actual version being used for a specific CPU model */
4161 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4162 {
4163 X86CPUVersion v = model->version;
4164 if (v == CPU_VERSION_AUTO) {
4165 v = default_cpu_version;
4166 }
4167 if (v == CPU_VERSION_LATEST) {
4168 return x86_cpu_model_last_version(model);
4169 }
4170 return v;
4171 }
4172
4173 void x86_cpu_change_kvm_default(const char *prop, const char *value)
4174 {
4175 PropValue *pv;
4176 for (pv = kvm_default_props; pv->prop; pv++) {
4177 if (!strcmp(pv->prop, prop)) {
4178 pv->value = value;
4179 break;
4180 }
4181 }
4182
4183 /* It is valid to call this function only for properties that
4184 * are already present in the kvm_default_props table.
4185 */
4186 assert(pv->prop);
4187 }
4188
4189 static bool lmce_supported(void)
4190 {
4191 uint64_t mce_cap = 0;
4192
4193 #ifdef CONFIG_KVM
4194 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4195 return false;
4196 }
4197 #endif
4198
4199 return !!(mce_cap & MCG_LMCE_P);
4200 }
4201
4202 #define CPUID_MODEL_ID_SZ 48
4203
4204 /**
4205 * cpu_x86_fill_model_id:
4206 * Get CPUID model ID string from host CPU.
4207 *
4208 * @str should have at least CPUID_MODEL_ID_SZ bytes
4209 *
4210 * The function does NOT add a null terminator to the string
4211 * automatically.
4212 */
4213 static int cpu_x86_fill_model_id(char *str)
4214 {
4215 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4216 int i;
4217
4218 for (i = 0; i < 3; i++) {
4219 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4220 memcpy(str + i * 16 + 0, &eax, 4);
4221 memcpy(str + i * 16 + 4, &ebx, 4);
4222 memcpy(str + i * 16 + 8, &ecx, 4);
4223 memcpy(str + i * 16 + 12, &edx, 4);
4224 }
4225 return 0;
4226 }
4227
4228 static Property max_x86_cpu_properties[] = {
4229 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
4230 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
4231 DEFINE_PROP_END_OF_LIST()
4232 };
4233
4234 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
4235 {
4236 DeviceClass *dc = DEVICE_CLASS(oc);
4237 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4238
4239 xcc->ordering = 9;
4240
4241 xcc->model_description =
4242 "Enables all features supported by the accelerator in the current host";
4243
4244 device_class_set_props(dc, max_x86_cpu_properties);
4245 }
4246
4247 static void max_x86_cpu_initfn(Object *obj)
4248 {
4249 X86CPU *cpu = X86_CPU(obj);
4250 CPUX86State *env = &cpu->env;
4251 KVMState *s = kvm_state;
4252
4253 /* We can't fill the features array here because we don't know yet if
4254 * "migratable" is true or false.
4255 */
4256 cpu->max_features = true;
4257
4258 if (accel_uses_host_cpuid()) {
4259 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4260 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4261 int family, model, stepping;
4262
4263 host_vendor_fms(vendor, &family, &model, &stepping);
4264 cpu_x86_fill_model_id(model_id);
4265
4266 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
4267 object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
4268 object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
4269 object_property_set_int(OBJECT(cpu), "stepping", stepping,
4270 &error_abort);
4271 object_property_set_str(OBJECT(cpu), "model-id", model_id,
4272 &error_abort);
4273
4274 if (kvm_enabled()) {
4275 env->cpuid_min_level =
4276 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4277 env->cpuid_min_xlevel =
4278 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4279 env->cpuid_min_xlevel2 =
4280 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4281 } else {
4282 env->cpuid_min_level =
4283 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4284 env->cpuid_min_xlevel =
4285 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4286 env->cpuid_min_xlevel2 =
4287 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4288 }
4289
4290 if (lmce_supported()) {
4291 object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
4292 }
4293 } else {
4294 object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4295 &error_abort);
4296 object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4297 object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4298 object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
4299 object_property_set_str(OBJECT(cpu), "model-id",
4300 "QEMU TCG CPU version " QEMU_HW_VERSION,
4301 &error_abort);
4302 }
4303
4304 object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
4305 }
4306
4307 static const TypeInfo max_x86_cpu_type_info = {
4308 .name = X86_CPU_TYPE_NAME("max"),
4309 .parent = TYPE_X86_CPU,
4310 .instance_init = max_x86_cpu_initfn,
4311 .class_init = max_x86_cpu_class_init,
4312 };
4313
4314 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4315 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4316 {
4317 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4318
4319 xcc->host_cpuid_required = true;
4320 xcc->ordering = 8;
4321
4322 #if defined(CONFIG_KVM)
4323 xcc->model_description =
4324 "KVM processor with all supported host features ";
4325 #elif defined(CONFIG_HVF)
4326 xcc->model_description =
4327 "HVF processor with all supported host features ";
4328 #endif
4329 }
4330
4331 static const TypeInfo host_x86_cpu_type_info = {
4332 .name = X86_CPU_TYPE_NAME("host"),
4333 .parent = X86_CPU_TYPE_NAME("max"),
4334 .class_init = host_x86_cpu_class_init,
4335 };
4336
4337 #endif
4338
4339 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4340 {
4341 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4342
4343 switch (f->type) {
4344 case CPUID_FEATURE_WORD:
4345 {
4346 const char *reg = get_register_name_32(f->cpuid.reg);
4347 assert(reg);
4348 return g_strdup_printf("CPUID.%02XH:%s",
4349 f->cpuid.eax, reg);
4350 }
4351 case MSR_FEATURE_WORD:
4352 return g_strdup_printf("MSR(%02XH)",
4353 f->msr.index);
4354 }
4355
4356 return NULL;
4357 }
4358
4359 static bool x86_cpu_have_filtered_features(X86CPU *cpu)
4360 {
4361 FeatureWord w;
4362
4363 for (w = 0; w < FEATURE_WORDS; w++) {
4364 if (cpu->filtered_features[w]) {
4365 return true;
4366 }
4367 }
4368
4369 return false;
4370 }
4371
4372 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
4373 const char *verbose_prefix)
4374 {
4375 CPUX86State *env = &cpu->env;
4376 FeatureWordInfo *f = &feature_word_info[w];
4377 int i;
4378
4379 if (!cpu->force_features) {
4380 env->features[w] &= ~mask;
4381 }
4382 cpu->filtered_features[w] |= mask;
4383
4384 if (!verbose_prefix) {
4385 return;
4386 }
4387
4388 for (i = 0; i < 64; ++i) {
4389 if ((1ULL << i) & mask) {
4390 g_autofree char *feat_word_str = feature_word_description(f, i);
4391 warn_report("%s: %s%s%s [bit %d]",
4392 verbose_prefix,
4393 feat_word_str,
4394 f->feat_names[i] ? "." : "",
4395 f->feat_names[i] ? f->feat_names[i] : "", i);
4396 }
4397 }
4398 }
4399
4400 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4401 const char *name, void *opaque,
4402 Error **errp)
4403 {
4404 X86CPU *cpu = X86_CPU(obj);
4405 CPUX86State *env = &cpu->env;
4406 int64_t value;
4407
4408 value = (env->cpuid_version >> 8) & 0xf;
4409 if (value == 0xf) {
4410 value += (env->cpuid_version >> 20) & 0xff;
4411 }
4412 visit_type_int(v, name, &value, errp);
4413 }
4414
4415 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4416 const char *name, void *opaque,
4417 Error **errp)
4418 {
4419 X86CPU *cpu = X86_CPU(obj);
4420 CPUX86State *env = &cpu->env;
4421 const int64_t min = 0;
4422 const int64_t max = 0xff + 0xf;
4423 int64_t value;
4424
4425 if (!visit_type_int(v, name, &value, errp)) {
4426 return;
4427 }
4428 if (value < min || value > max) {
4429 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4430 name ? name : "null", value, min, max);
4431 return;
4432 }
4433
4434 env->cpuid_version &= ~0xff00f00;
4435 if (value > 0x0f) {
4436 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
4437 } else {
4438 env->cpuid_version |= value << 8;
4439 }
4440 }
4441
4442 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4443 const char *name, void *opaque,
4444 Error **errp)
4445 {
4446 X86CPU *cpu = X86_CPU(obj);
4447 CPUX86State *env = &cpu->env;
4448 int64_t value;
4449
4450 value = (env->cpuid_version >> 4) & 0xf;
4451 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
4452 visit_type_int(v, name, &value, errp);
4453 }
4454
4455 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4456 const char *name, void *opaque,
4457 Error **errp)
4458 {
4459 X86CPU *cpu = X86_CPU(obj);
4460 CPUX86State *env = &cpu->env;
4461 const int64_t min = 0;
4462 const int64_t max = 0xff;
4463 int64_t value;
4464
4465 if (!visit_type_int(v, name, &value, errp)) {
4466 return;
4467 }
4468 if (value < min || value > max) {
4469 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4470 name ? name : "null", value, min, max);
4471 return;
4472 }
4473
4474 env->cpuid_version &= ~0xf00f0;
4475 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
4476 }
4477
4478 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
4479 const char *name, void *opaque,
4480 Error **errp)
4481 {
4482 X86CPU *cpu = X86_CPU(obj);
4483 CPUX86State *env = &cpu->env;
4484 int64_t value;
4485
4486 value = env->cpuid_version & 0xf;
4487 visit_type_int(v, name, &value, errp);
4488 }
4489
4490 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
4491 const char *name, void *opaque,
4492 Error **errp)
4493 {
4494 X86CPU *cpu = X86_CPU(obj);
4495 CPUX86State *env = &cpu->env;
4496 const int64_t min = 0;
4497 const int64_t max = 0xf;
4498 int64_t value;
4499
4500 if (!visit_type_int(v, name, &value, errp)) {
4501 return;
4502 }
4503 if (value < min || value > max) {
4504 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4505 name ? name : "null", value, min, max);
4506 return;
4507 }
4508
4509 env->cpuid_version &= ~0xf;
4510 env->cpuid_version |= value & 0xf;
4511 }
4512
4513 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4514 {
4515 X86CPU *cpu = X86_CPU(obj);
4516 CPUX86State *env = &cpu->env;
4517 char *value;
4518
4519 value = g_malloc(CPUID_VENDOR_SZ + 1);
4520 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4521 env->cpuid_vendor3);
4522 return value;
4523 }
4524
4525 static void x86_cpuid_set_vendor(Object *obj, const char *value,
4526 Error **errp)
4527 {
4528 X86CPU *cpu = X86_CPU(obj);
4529 CPUX86State *env = &cpu->env;
4530 int i;
4531
4532 if (strlen(value) != CPUID_VENDOR_SZ) {
4533 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
4534 return;
4535 }
4536
4537 env->cpuid_vendor1 = 0;
4538 env->cpuid_vendor2 = 0;
4539 env->cpuid_vendor3 = 0;
4540 for (i = 0; i < 4; i++) {
4541 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
4542 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4543 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4544 }
4545 }
4546
4547 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4548 {
4549 X86CPU *cpu = X86_CPU(obj);
4550 CPUX86State *env = &cpu->env;
4551 char *value;
4552 int i;
4553
4554 value = g_malloc(48 + 1);
4555 for (i = 0; i < 48; i++) {
4556 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4557 }
4558 value[48] = '\0';
4559 return value;
4560 }
4561
4562 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4563 Error **errp)
4564 {
4565 X86CPU *cpu = X86_CPU(obj);
4566 CPUX86State *env = &cpu->env;
4567 int c, len, i;
4568
4569 if (model_id == NULL) {
4570 model_id = "";
4571 }
4572 len = strlen(model_id);
4573 memset(env->cpuid_model, 0, 48);
4574 for (i = 0; i < 48; i++) {
4575 if (i >= len) {
4576 c = '\0';
4577 } else {
4578 c = (uint8_t)model_id[i];
4579 }
4580 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4581 }
4582 }
4583
4584 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4585 void *opaque, Error **errp)
4586 {
4587 X86CPU *cpu = X86_CPU(obj);
4588 int64_t value;
4589
4590 value = cpu->env.tsc_khz * 1000;
4591 visit_type_int(v, name, &value, errp);
4592 }
4593
4594 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4595 void *opaque, Error **errp)
4596 {
4597 X86CPU *cpu = X86_CPU(obj);
4598 const int64_t min = 0;
4599 const int64_t max = INT64_MAX;
4600 int64_t value;
4601
4602 if (!visit_type_int(v, name, &value, errp)) {
4603 return;
4604 }
4605 if (value < min || value > max) {
4606 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4607 name ? name : "null", value, min, max);
4608 return;
4609 }
4610
4611 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
4612 }
4613
4614 /* Generic getter for "feature-words" and "filtered-features" properties */
4615 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4616 const char *name, void *opaque,
4617 Error **errp)
4618 {
4619 uint64_t *array = (uint64_t *)opaque;
4620 FeatureWord w;
4621 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4622 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4623 X86CPUFeatureWordInfoList *list = NULL;
4624
4625 for (w = 0; w < FEATURE_WORDS; w++) {
4626 FeatureWordInfo *wi = &feature_word_info[w];
4627 /*
4628 * We didn't have MSR features when "feature-words" was
4629 * introduced. Therefore skipped other type entries.
4630 */
4631 if (wi->type != CPUID_FEATURE_WORD) {
4632 continue;
4633 }
4634 X86CPUFeatureWordInfo *qwi = &word_infos[w];
4635 qwi->cpuid_input_eax = wi->cpuid.eax;
4636 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4637 qwi->cpuid_input_ecx = wi->cpuid.ecx;
4638 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
4639 qwi->features = array[w];
4640
4641 /* List will be in reverse order, but order shouldn't matter */
4642 list_entries[w].next = list;
4643 list_entries[w].value = &word_infos[w];
4644 list = &list_entries[w];
4645 }
4646
4647 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
4648 }
4649
4650 /* Convert all '_' in a feature string option name to '-', to make feature
4651 * name conform to QOM property naming rule, which uses '-' instead of '_'.
4652 */
4653 static inline void feat2prop(char *s)
4654 {
4655 while ((s = strchr(s, '_'))) {
4656 *s = '-';
4657 }
4658 }
4659
4660 /* Return the feature property name for a feature flag bit */
4661 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4662 {
4663 const char *name;
4664 /* XSAVE components are automatically enabled by other features,
4665 * so return the original feature name instead
4666 */
4667 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4668 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4669
4670 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4671 x86_ext_save_areas[comp].bits) {
4672 w = x86_ext_save_areas[comp].feature;
4673 bitnr = ctz32(x86_ext_save_areas[comp].bits);
4674 }
4675 }
4676
4677 assert(bitnr < 64);
4678 assert(w < FEATURE_WORDS);
4679 name = feature_word_info[w].feat_names[bitnr];
4680 assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4681 return name;
4682 }
4683
4684 /* Compatibily hack to maintain legacy +-feat semantic,
4685 * where +-feat overwrites any feature set by
4686 * feat=on|feat even if the later is parsed after +-feat
4687 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4688 */
4689 static GList *plus_features, *minus_features;
4690
4691 static gint compare_string(gconstpointer a, gconstpointer b)
4692 {
4693 return g_strcmp0(a, b);
4694 }
4695
4696 /* Parse "+feature,-feature,feature=foo" CPU feature string
4697 */
4698 static void x86_cpu_parse_featurestr(const char *typename, char *features,
4699 Error **errp)
4700 {
4701 char *featurestr; /* Single 'key=value" string being parsed */
4702 static bool cpu_globals_initialized;
4703 bool ambiguous = false;
4704
4705 if (cpu_globals_initialized) {
4706 return;
4707 }
4708 cpu_globals_initialized = true;
4709
4710 if (!features) {
4711 return;
4712 }
4713
4714 for (featurestr = strtok(features, ",");
4715 featurestr;
4716 featurestr = strtok(NULL, ",")) {
4717 const char *name;
4718 const char *val = NULL;
4719 char *eq = NULL;
4720 char num[32];
4721 GlobalProperty *prop;
4722
4723 /* Compatibility syntax: */
4724 if (featurestr[0] == '+') {
4725 plus_features = g_list_append(plus_features,
4726 g_strdup(featurestr + 1));
4727 continue;
4728 } else if (featurestr[0] == '-') {
4729 minus_features = g_list_append(minus_features,
4730 g_strdup(featurestr + 1));
4731 continue;
4732 }
4733
4734 eq = strchr(featurestr, '=');
4735 if (eq) {
4736 *eq++ = 0;
4737 val = eq;
4738 } else {
4739 val = "on";
4740 }
4741
4742 feat2prop(featurestr);
4743 name = featurestr;
4744
4745 if (g_list_find_custom(plus_features, name, compare_string)) {
4746 warn_report("Ambiguous CPU model string. "
4747 "Don't mix both \"+%s\" and \"%s=%s\"",
4748 name, name, val);
4749 ambiguous = true;
4750 }
4751 if (g_list_find_custom(minus_features, name, compare_string)) {
4752 warn_report("Ambiguous CPU model string. "
4753 "Don't mix both \"-%s\" and \"%s=%s\"",
4754 name, name, val);
4755 ambiguous = true;
4756 }
4757
4758 /* Special case: */
4759 if (!strcmp(name, "tsc-freq")) {
4760 int ret;
4761 uint64_t tsc_freq;
4762
4763 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
4764 if (ret < 0 || tsc_freq > INT64_MAX) {
4765 error_setg(errp, "bad numerical value %s", val);
4766 return;
4767 }
4768 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4769 val = num;
4770 name = "tsc-frequency";
4771 }
4772
4773 prop = g_new0(typeof(*prop), 1);
4774 prop->driver = typename;
4775 prop->property = g_strdup(name);
4776 prop->value = g_strdup(val);
4777 qdev_prop_register_global(prop);
4778 }
4779
4780 if (ambiguous) {
4781 warn_report("Compatibility of ambiguous CPU model "
4782 "strings won't be kept on future QEMU versions");
4783 }
4784 }
4785
4786 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
4787 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
4788
4789 /* Build a list with the name of all features on a feature word array */
4790 static void x86_cpu_list_feature_names(FeatureWordArray features,
4791 strList **feat_names)
4792 {
4793 FeatureWord w;
4794 strList **next = feat_names;
4795
4796 for (w = 0; w < FEATURE_WORDS; w++) {
4797 uint64_t filtered = features[w];
4798 int i;
4799 for (i = 0; i < 64; i++) {
4800 if (filtered & (1ULL << i)) {
4801 strList *new = g_new0(strList, 1);
4802 new->value = g_strdup(x86_cpu_feature_name(w, i));
4803 *next = new;
4804 next = &new->next;
4805 }
4806 }
4807 }
4808 }
4809
4810 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4811 const char *name, void *opaque,
4812 Error **errp)
4813 {
4814 X86CPU *xc = X86_CPU(obj);
4815 strList *result = NULL;
4816
4817 x86_cpu_list_feature_names(xc->filtered_features, &result);
4818 visit_type_strList(v, "unavailable-features", &result, errp);
4819 }
4820
4821 /* Check for missing features that may prevent the CPU class from
4822 * running using the current machine and accelerator.
4823 */
4824 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4825 strList **missing_feats)
4826 {
4827 X86CPU *xc;
4828 Error *err = NULL;
4829 strList **next = missing_feats;
4830
4831 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
4832 strList *new = g_new0(strList, 1);
4833 new->value = g_strdup("kvm");
4834 *missing_feats = new;
4835 return;
4836 }
4837
4838 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
4839
4840 x86_cpu_expand_features(xc, &err);
4841 if (err) {
4842 /* Errors at x86_cpu_expand_features should never happen,
4843 * but in case it does, just report the model as not
4844 * runnable at all using the "type" property.
4845 */
4846 strList *new = g_new0(strList, 1);
4847 new->value = g_strdup("type");
4848 *next = new;
4849 next = &new->next;
4850 error_free(err);
4851 }
4852
4853 x86_cpu_filter_features(xc, false);
4854
4855 x86_cpu_list_feature_names(xc->filtered_features, next);
4856
4857 object_unref(OBJECT(xc));
4858 }
4859
4860 /* Print all cpuid feature names in featureset
4861 */
4862 static void listflags(GList *features)
4863 {
4864 size_t len = 0;
4865 GList *tmp;
4866
4867 for (tmp = features; tmp; tmp = tmp->next) {
4868 const char *name = tmp->data;
4869 if ((len + strlen(name) + 1) >= 75) {
4870 qemu_printf("\n");
4871 len = 0;
4872 }
4873 qemu_printf("%s%s", len == 0 ? " " : " ", name);
4874 len += strlen(name) + 1;
4875 }
4876 qemu_printf("\n");
4877 }
4878
4879 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4880 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4881 {
4882 ObjectClass *class_a = (ObjectClass *)a;
4883 ObjectClass *class_b = (ObjectClass *)b;
4884 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4885 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
4886 int ret;
4887
4888 if (cc_a->ordering != cc_b->ordering) {
4889 ret = cc_a->ordering - cc_b->ordering;
4890 } else {
4891 g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4892 g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
4893 ret = strcmp(name_a, name_b);
4894 }
4895 return ret;
4896 }
4897
4898 static GSList *get_sorted_cpu_model_list(void)
4899 {
4900 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4901 list = g_slist_sort(list, x86_cpu_list_compare);
4902 return list;
4903 }
4904
4905 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4906 {
4907 Object *obj = object_new_with_class(OBJECT_CLASS(xc));
4908 char *r = object_property_get_str(obj, "model-id", &error_abort);
4909 object_unref(obj);
4910 return r;
4911 }
4912
4913 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4914 {
4915 X86CPUVersion version;
4916
4917 if (!cc->model || !cc->model->is_alias) {
4918 return NULL;
4919 }
4920 version = x86_cpu_model_resolve_version(cc->model);
4921 if (version <= 0) {
4922 return NULL;
4923 }
4924 return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4925 }
4926
4927 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4928 {
4929 ObjectClass *oc = data;
4930 X86CPUClass *cc = X86_CPU_CLASS(oc);
4931 g_autofree char *name = x86_cpu_class_get_model_name(cc);
4932 g_autofree char *desc = g_strdup(cc->model_description);
4933 g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
4934 g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
4935
4936 if (!desc && alias_of) {
4937 if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4938 desc = g_strdup("(alias configured by machine type)");
4939 } else {
4940 desc = g_strdup_printf("(alias of %s)", alias_of);
4941 }
4942 }
4943 if (!desc && cc->model && cc->model->note) {
4944 desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4945 }
4946 if (!desc) {
4947 desc = g_strdup_printf("%s", model_id);
4948 }
4949
4950 qemu_printf("x86 %-20s %-58s\n", name, desc);
4951 }
4952
4953 /* list available CPU models and flags */
4954 void x86_cpu_list(void)
4955 {
4956 int i, j;
4957 GSList *list;
4958 GList *names = NULL;
4959
4960 qemu_printf("Available CPUs:\n");
4961 list = get_sorted_cpu_model_list();
4962 g_slist_foreach(list, x86_cpu_list_entry, NULL);
4963 g_slist_free(list);
4964
4965 names = NULL;
4966 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4967 FeatureWordInfo *fw = &feature_word_info[i];
4968 for (j = 0; j < 64; j++) {
4969 if (fw->feat_names[j]) {
4970 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4971 }
4972 }
4973 }
4974
4975 names = g_list_sort(names, (GCompareFunc)strcmp);
4976
4977 qemu_printf("\nRecognized CPUID flags:\n");
4978 listflags(names);
4979 qemu_printf("\n");
4980 g_list_free(names);
4981 }
4982
4983 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4984 {
4985 ObjectClass *oc = data;
4986 X86CPUClass *cc = X86_CPU_CLASS(oc);
4987 CpuDefinitionInfoList **cpu_list = user_data;
4988 CpuDefinitionInfoList *entry;
4989 CpuDefinitionInfo *info;
4990
4991 info = g_malloc0(sizeof(*info));
4992 info->name = x86_cpu_class_get_model_name(cc);
4993 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4994 info->has_unavailable_features = true;
4995 info->q_typename = g_strdup(object_class_get_name(oc));
4996 info->migration_safe = cc->migration_safe;
4997 info->has_migration_safe = true;
4998 info->q_static = cc->static_model;
4999 if (cc->model && cc->model->cpudef->deprecation_note) {
5000 info->deprecated = true;
5001 } else {
5002 info->deprecated = false;
5003 }
5004 /*
5005 * Old machine types won't report aliases, so that alias translation
5006 * doesn't break compatibility with previous QEMU versions.
5007 */
5008 if (default_cpu_version != CPU_VERSION_LEGACY) {
5009 info->alias_of = x86_cpu_class_get_alias_of(cc);
5010 info->has_alias_of = !!info->alias_of;
5011 }
5012
5013 entry = g_malloc0(sizeof(*entry));
5014 entry->value = info;
5015 entry->next = *cpu_list;
5016 *cpu_list = entry;
5017 }
5018
5019 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
5020 {
5021 CpuDefinitionInfoList *cpu_list = NULL;
5022 GSList *list = get_sorted_cpu_model_list();
5023 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5024 g_slist_free(list);
5025 return cpu_list;
5026 }
5027
5028 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
5029 bool migratable_only)
5030 {
5031 FeatureWordInfo *wi = &feature_word_info[w];
5032 uint64_t r = 0;
5033
5034 if (kvm_enabled()) {
5035 switch (wi->type) {
5036 case CPUID_FEATURE_WORD:
5037 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5038 wi->cpuid.ecx,
5039 wi->cpuid.reg);
5040 break;
5041 case MSR_FEATURE_WORD:
5042 r = kvm_arch_get_supported_msr_feature(kvm_state,
5043 wi->msr.index);
5044 break;
5045 }
5046 } else if (hvf_enabled()) {
5047 if (wi->type != CPUID_FEATURE_WORD) {
5048 return 0;
5049 }
5050 r = hvf_get_supported_cpuid(wi->cpuid.eax,
5051 wi->cpuid.ecx,
5052 wi->cpuid.reg);
5053 } else if (tcg_enabled()) {
5054 r = wi->tcg_features;
5055 } else {
5056 return ~0;
5057 }
5058 if (migratable_only) {
5059 r &= x86_cpu_get_migratable_flags(w);
5060 }
5061 return r;
5062 }
5063
5064 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5065 {
5066 PropValue *pv;
5067 for (pv = props; pv->prop; pv++) {
5068 if (!pv->value) {
5069 continue;
5070 }
5071 object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5072 &error_abort);
5073 }
5074 }
5075
5076 /* Apply properties for the CPU model version specified in model */
5077 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5078 {
5079 const X86CPUVersionDefinition *vdef;
5080 X86CPUVersion version = x86_cpu_model_resolve_version(model);
5081
5082 if (version == CPU_VERSION_LEGACY) {
5083 return;
5084 }
5085
5086 for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5087 PropValue *p;
5088
5089 for (p = vdef->props; p && p->prop; p++) {
5090 object_property_parse(OBJECT(cpu), p->prop, p->value,
5091 &error_abort);
5092 }
5093
5094 if (vdef->version == version) {
5095 break;
5096 }
5097 }
5098
5099 /*
5100 * If we reached the end of the list, version number was invalid
5101 */
5102 assert(vdef->version == version);
5103 }
5104
5105 /* Load data from X86CPUDefinition into a X86CPU object
5106 */
5107 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
5108 {
5109 X86CPUDefinition *def = model->cpudef;
5110 CPUX86State *env = &cpu->env;
5111 const char *vendor;
5112 char host_vendor[CPUID_VENDOR_SZ + 1];
5113 FeatureWord w;
5114
5115 /*NOTE: any property set by this function should be returned by
5116 * x86_cpu_static_props(), so static expansion of
5117 * query-cpu-model-expansion is always complete.
5118 */
5119
5120 /* CPU models only set _minimum_ values for level/xlevel: */
5121 object_property_set_uint(OBJECT(cpu), "min-level", def->level,
5122 &error_abort);
5123 object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
5124 &error_abort);
5125
5126 object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5127 object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5128 object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
5129 &error_abort);
5130 object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
5131 &error_abort);
5132 for (w = 0; w < FEATURE_WORDS; w++) {
5133 env->features[w] = def->features[w];
5134 }
5135
5136 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5137 cpu->legacy_cache = !def->cache_info;
5138
5139 /* Special cases not set in the X86CPUDefinition structs: */
5140 /* TODO: in-kernel irqchip for hvf */
5141 if (kvm_enabled()) {
5142 if (!kvm_irqchip_in_kernel()) {
5143 x86_cpu_change_kvm_default("x2apic", "off");
5144 } else if (kvm_irqchip_is_split() && kvm_enable_x2apic()) {
5145 x86_cpu_change_kvm_default("kvm-msi-ext-dest-id", "on");
5146 }
5147
5148 x86_cpu_apply_props(cpu, kvm_default_props);
5149 } else if (tcg_enabled()) {
5150 x86_cpu_apply_props(cpu, tcg_default_props);
5151 }
5152
5153 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
5154
5155 /* sysenter isn't supported in compatibility mode on AMD,
5156 * syscall isn't supported in compatibility mode on Intel.
5157 * Normally we advertise the actual CPU vendor, but you can
5158 * override this using the 'vendor' property if you want to use
5159 * KVM's sysenter/syscall emulation in compatibility mode and
5160 * when doing cross vendor migration
5161 */
5162 vendor = def->vendor;
5163 if (accel_uses_host_cpuid()) {
5164 uint32_t ebx = 0, ecx = 0, edx = 0;
5165 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5166 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5167 vendor = host_vendor;
5168 }
5169
5170 object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
5171
5172 x86_cpu_apply_version_props(cpu, model);
5173
5174 /*
5175 * Properties in versioned CPU model are not user specified features.
5176 * We can simply clear env->user_features here since it will be filled later
5177 * in x86_cpu_expand_features() based on plus_features and minus_features.
5178 */
5179 memset(&env->user_features, 0, sizeof(env->user_features));
5180 }
5181
5182 #ifndef CONFIG_USER_ONLY
5183 /* Return a QDict containing keys for all properties that can be included
5184 * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5185 * must be included in the dictionary.
5186 */
5187 static QDict *x86_cpu_static_props(void)
5188 {
5189 FeatureWord w;
5190 int i;
5191 static const char *props[] = {
5192 "min-level",
5193 "min-xlevel",
5194 "family",
5195 "model",
5196 "stepping",
5197 "model-id",
5198 "vendor",
5199 "lmce",
5200 NULL,
5201 };
5202 static QDict *d;
5203
5204 if (d) {
5205 return d;
5206 }
5207
5208 d = qdict_new();
5209 for (i = 0; props[i]; i++) {
5210 qdict_put_null(d, props[i]);
5211 }
5212
5213 for (w = 0; w < FEATURE_WORDS; w++) {
5214 FeatureWordInfo *fi = &feature_word_info[w];
5215 int bit;
5216 for (bit = 0; bit < 64; bit++) {
5217 if (!fi->feat_names[bit]) {
5218 continue;
5219 }
5220 qdict_put_null(d, fi->feat_names[bit]);
5221 }
5222 }
5223
5224 return d;
5225 }
5226
5227 /* Add an entry to @props dict, with the value for property. */
5228 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5229 {
5230 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5231 &error_abort);
5232
5233 qdict_put_obj(props, prop, value);
5234 }
5235
5236 /* Convert CPU model data from X86CPU object to a property dictionary
5237 * that can recreate exactly the same CPU model.
5238 */
5239 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5240 {
5241 QDict *sprops = x86_cpu_static_props();
5242 const QDictEntry *e;
5243
5244 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5245 const char *prop = qdict_entry_key(e);
5246 x86_cpu_expand_prop(cpu, props, prop);
5247 }
5248 }
5249
5250 /* Convert CPU model data from X86CPU object to a property dictionary
5251 * that can recreate exactly the same CPU model, including every
5252 * writeable QOM property.
5253 */
5254 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5255 {
5256 ObjectPropertyIterator iter;
5257 ObjectProperty *prop;
5258
5259 object_property_iter_init(&iter, OBJECT(cpu));
5260 while ((prop = object_property_iter_next(&iter))) {
5261 /* skip read-only or write-only properties */
5262 if (!prop->get || !prop->set) {
5263 continue;
5264 }
5265
5266 /* "hotplugged" is the only property that is configurable
5267 * on the command-line but will be set differently on CPUs
5268 * created using "-cpu ... -smp ..." and by CPUs created
5269 * on the fly by x86_cpu_from_model() for querying. Skip it.
5270 */
5271 if (!strcmp(prop->name, "hotplugged")) {
5272 continue;
5273 }
5274 x86_cpu_expand_prop(cpu, props, prop->name);
5275 }
5276 }
5277
5278 static void object_apply_props(Object *obj, QDict *props, Error **errp)
5279 {
5280 const QDictEntry *prop;
5281
5282 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5283 if (!object_property_set_qobject(obj, qdict_entry_key(prop),
5284 qdict_entry_value(prop), errp)) {
5285 break;
5286 }
5287 }
5288 }
5289
5290 /* Create X86CPU object according to model+props specification */
5291 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5292 {
5293 X86CPU *xc = NULL;
5294 X86CPUClass *xcc;
5295 Error *err = NULL;
5296
5297 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5298 if (xcc == NULL) {
5299 error_setg(&err, "CPU model '%s' not found", model);
5300 goto out;
5301 }
5302
5303 xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5304 if (props) {
5305 object_apply_props(OBJECT(xc), props, &err);
5306 if (err) {
5307 goto out;
5308 }
5309 }
5310
5311 x86_cpu_expand_features(xc, &err);
5312 if (err) {
5313 goto out;
5314 }
5315
5316 out:
5317 if (err) {
5318 error_propagate(errp, err);
5319 object_unref(OBJECT(xc));
5320 xc = NULL;
5321 }
5322 return xc;
5323 }
5324
5325 CpuModelExpansionInfo *
5326 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
5327 CpuModelInfo *model,
5328 Error **errp)
5329 {
5330 X86CPU *xc = NULL;
5331 Error *err = NULL;
5332 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5333 QDict *props = NULL;
5334 const char *base_name;
5335
5336 xc = x86_cpu_from_model(model->name,
5337 model->has_props ?
5338 qobject_to(QDict, model->props) :
5339 NULL, &err);
5340 if (err) {
5341 goto out;
5342 }
5343
5344 props = qdict_new();
5345 ret->model = g_new0(CpuModelInfo, 1);
5346 ret->model->props = QOBJECT(props);
5347 ret->model->has_props = true;
5348
5349 switch (type) {
5350 case CPU_MODEL_EXPANSION_TYPE_STATIC:
5351 /* Static expansion will be based on "base" only */
5352 base_name = "base";
5353 x86_cpu_to_dict(xc, props);
5354 break;
5355 case CPU_MODEL_EXPANSION_TYPE_FULL:
5356 /* As we don't return every single property, full expansion needs
5357 * to keep the original model name+props, and add extra
5358 * properties on top of that.
5359 */
5360 base_name = model->name;
5361 x86_cpu_to_dict_full(xc, props);
5362 break;
5363 default:
5364 error_setg(&err, "Unsupported expansion type");
5365 goto out;
5366 }
5367
5368 x86_cpu_to_dict(xc, props);
5369
5370 ret->model->name = g_strdup(base_name);
5371
5372 out:
5373 object_unref(OBJECT(xc));
5374 if (err) {
5375 error_propagate(errp, err);
5376 qapi_free_CpuModelExpansionInfo(ret);
5377 ret = NULL;
5378 }
5379 return ret;
5380 }
5381 #endif /* !CONFIG_USER_ONLY */
5382
5383 static gchar *x86_gdb_arch_name(CPUState *cs)
5384 {
5385 #ifdef TARGET_X86_64
5386 return g_strdup("i386:x86-64");
5387 #else
5388 return g_strdup("i386");
5389 #endif
5390 }
5391
5392 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5393 {
5394 X86CPUModel *model = data;
5395 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5396 CPUClass *cc = CPU_CLASS(oc);
5397
5398 xcc->model = model;
5399 xcc->migration_safe = true;
5400 cc->deprecation_note = model->cpudef->deprecation_note;
5401 }
5402
5403 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
5404 {
5405 g_autofree char *typename = x86_cpu_type_name(name);
5406 TypeInfo ti = {
5407 .name = typename,
5408 .parent = TYPE_X86_CPU,
5409 .class_init = x86_cpu_cpudef_class_init,
5410 .class_data = model,
5411 };
5412
5413 type_register(&ti);
5414 }
5415
5416 static void x86_register_cpudef_types(X86CPUDefinition *def)
5417 {
5418 X86CPUModel *m;
5419 const X86CPUVersionDefinition *vdef;
5420
5421 /* AMD aliases are handled at runtime based on CPUID vendor, so
5422 * they shouldn't be set on the CPU model table.
5423 */
5424 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
5425 /* catch mistakes instead of silently truncating model_id when too long */
5426 assert(def->model_id && strlen(def->model_id) <= 48);
5427
5428 /* Unversioned model: */
5429 m = g_new0(X86CPUModel, 1);
5430 m->cpudef = def;
5431 m->version = CPU_VERSION_AUTO;
5432 m->is_alias = true;
5433 x86_register_cpu_model_type(def->name, m);
5434
5435 /* Versioned models: */
5436
5437 for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5438 X86CPUModel *m = g_new0(X86CPUModel, 1);
5439 g_autofree char *name =
5440 x86_cpu_versioned_model_name(def, vdef->version);
5441 m->cpudef = def;
5442 m->version = vdef->version;
5443 m->note = vdef->note;
5444 x86_register_cpu_model_type(name, m);
5445
5446 if (vdef->alias) {
5447 X86CPUModel *am = g_new0(X86CPUModel, 1);
5448 am->cpudef = def;
5449 am->version = vdef->version;
5450 am->is_alias = true;
5451 x86_register_cpu_model_type(vdef->alias, am);
5452 }
5453 }
5454
5455 }
5456
5457 #if !defined(CONFIG_USER_ONLY)
5458
5459 void cpu_clear_apic_feature(CPUX86State *env)
5460 {
5461 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
5462 }
5463
5464 #endif /* !CONFIG_USER_ONLY */
5465
5466 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5467 uint32_t *eax, uint32_t *ebx,
5468 uint32_t *ecx, uint32_t *edx)
5469 {
5470 X86CPU *cpu = env_archcpu(env);
5471 CPUState *cs = env_cpu(env);
5472 uint32_t die_offset;
5473 uint32_t limit;
5474 uint32_t signature[3];
5475 X86CPUTopoInfo topo_info;
5476
5477 topo_info.dies_per_pkg = env->nr_dies;
5478 topo_info.cores_per_die = cs->nr_cores;
5479 topo_info.threads_per_core = cs->nr_threads;
5480
5481 /* Calculate & apply limits for different index ranges */
5482 if (index >= 0xC0000000) {
5483 limit = env->cpuid_xlevel2;
5484 } else if (index >= 0x80000000) {
5485 limit = env->cpuid_xlevel;
5486 } else if (index >= 0x40000000) {
5487 limit = 0x40000001;
5488 } else {
5489 limit = env->cpuid_level;
5490 }
5491
5492 if (index > limit) {
5493 /* Intel documentation states that invalid EAX input will
5494 * return the same information as EAX=cpuid_level
5495 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5496 */
5497 index = env->cpuid_level;
5498 }
5499
5500 switch(index) {
5501 case 0:
5502 *eax = env->cpuid_level;
5503 *ebx = env->cpuid_vendor1;
5504 *edx = env->cpuid_vendor2;
5505 *ecx = env->cpuid_vendor3;
5506 break;
5507 case 1:
5508 *eax = env->cpuid_version;
5509 *ebx = (cpu->apic_id << 24) |
5510 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5511 *ecx = env->features[FEAT_1_ECX];
5512 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5513 *ecx |= CPUID_EXT_OSXSAVE;
5514 }
5515 *edx = env->features[FEAT_1_EDX];
5516 if (cs->nr_cores * cs->nr_threads > 1) {
5517 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
5518 *edx |= CPUID_HT;
5519 }
5520 if (!cpu->enable_pmu) {
5521 *ecx &= ~CPUID_EXT_PDCM;
5522 }
5523 break;
5524 case 2:
5525 /* cache info: needed for Pentium Pro compatibility */
5526 if (cpu->cache_info_passthrough) {
5527 host_cpuid(index, 0, eax, ebx, ecx, edx);
5528 break;
5529 }
5530 *eax = 1; /* Number of CPUID[EAX=2] calls required */
5531 *ebx = 0;
5532 if (!cpu->enable_l3_cache) {
5533 *ecx = 0;
5534 } else {
5535 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
5536 }
5537 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5538 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
5539 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
5540 break;
5541 case 4:
5542 /* cache info: needed for Core compatibility */
5543 if (cpu->cache_info_passthrough) {
5544 host_cpuid(index, count, eax, ebx, ecx, edx);
5545 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
5546 *eax &= ~0xFC000000;
5547 if ((*eax & 31) && cs->nr_cores > 1) {
5548 *eax |= (cs->nr_cores - 1) << 26;
5549 }
5550 } else {
5551 *eax = 0;
5552 switch (count) {
5553 case 0: /* L1 dcache info */
5554 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5555 1, cs->nr_cores,
5556 eax, ebx, ecx, edx);
5557 break;
5558 case 1: /* L1 icache info */
5559 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5560 1, cs->nr_cores,
5561 eax, ebx, ecx, edx);
5562 break;
5563 case 2: /* L2 cache info */
5564 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5565 cs->nr_threads, cs->nr_cores,
5566 eax, ebx, ecx, edx);
5567 break;
5568 case 3: /* L3 cache info */
5569 die_offset = apicid_die_offset(&topo_info);
5570 if (cpu->enable_l3_cache) {
5571 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
5572 (1 << die_offset), cs->nr_cores,
5573 eax, ebx, ecx, edx);
5574 break;
5575 }
5576 /* fall through */
5577 default: /* end of info */
5578 *eax = *ebx = *ecx = *edx = 0;
5579 break;
5580 }
5581 }
5582 break;
5583 case 5:
5584 /* MONITOR/MWAIT Leaf */
5585 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5586 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5587 *ecx = cpu->mwait.ecx; /* flags */
5588 *edx = cpu->mwait.edx; /* mwait substates */
5589 break;
5590 case 6:
5591 /* Thermal and Power Leaf */
5592 *eax = env->features[FEAT_6_EAX];
5593 *ebx = 0;
5594 *ecx = 0;
5595 *edx = 0;
5596 break;
5597 case 7:
5598 /* Structured Extended Feature Flags Enumeration Leaf */
5599 if (count == 0) {
5600 /* Maximum ECX value for sub-leaves */
5601 *eax = env->cpuid_level_func7;
5602 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
5603 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
5604 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5605 *ecx |= CPUID_7_0_ECX_OSPKE;
5606 }
5607 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
5608 } else if (count == 1) {
5609 *eax = env->features[FEAT_7_1_EAX];
5610 *ebx = 0;
5611 *ecx = 0;
5612 *edx = 0;
5613 } else {
5614 *eax = 0;
5615 *ebx = 0;
5616 *ecx = 0;
5617 *edx = 0;
5618 }
5619 break;
5620 case 9:
5621 /* Direct Cache Access Information Leaf */
5622 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5623 *ebx = 0;
5624 *ecx = 0;
5625 *edx = 0;
5626 break;
5627 case 0xA:
5628 /* Architectural Performance Monitoring Leaf */
5629 if (kvm_enabled() && cpu->enable_pmu) {
5630 KVMState *s = cs->kvm_state;
5631
5632 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5633 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5634 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5635 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
5636 } else if (hvf_enabled() && cpu->enable_pmu) {
5637 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5638 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5639 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5640 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
5641 } else {
5642 *eax = 0;
5643 *ebx = 0;
5644 *ecx = 0;
5645 *edx = 0;
5646 }
5647 break;
5648 case 0xB:
5649 /* Extended Topology Enumeration Leaf */
5650 if (!cpu->enable_cpuid_0xb) {
5651 *eax = *ebx = *ecx = *edx = 0;
5652 break;
5653 }
5654
5655 *ecx = count & 0xff;
5656 *edx = cpu->apic_id;
5657
5658 switch (count) {
5659 case 0:
5660 *eax = apicid_core_offset(&topo_info);
5661 *ebx = cs->nr_threads;
5662 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5663 break;
5664 case 1:
5665 *eax = apicid_pkg_offset(&topo_info);
5666 *ebx = cs->nr_cores * cs->nr_threads;
5667 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5668 break;
5669 default:
5670 *eax = 0;
5671 *ebx = 0;
5672 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5673 }
5674
5675 assert(!(*eax & ~0x1f));
5676 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5677 break;
5678 case 0x1F:
5679 /* V2 Extended Topology Enumeration Leaf */
5680 if (env->nr_dies < 2) {
5681 *eax = *ebx = *ecx = *edx = 0;
5682 break;
5683 }
5684
5685 *ecx = count & 0xff;
5686 *edx = cpu->apic_id;
5687 switch (count) {
5688 case 0:
5689 *eax = apicid_core_offset(&topo_info);
5690 *ebx = cs->nr_threads;
5691 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5692 break;
5693 case 1:
5694 *eax = apicid_die_offset(&topo_info);
5695 *ebx = cs->nr_cores * cs->nr_threads;
5696 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5697 break;
5698 case 2:
5699 *eax = apicid_pkg_offset(&topo_info);
5700 *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5701 *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5702 break;
5703 default:
5704 *eax = 0;
5705 *ebx = 0;
5706 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5707 }
5708 assert(!(*eax & ~0x1f));
5709 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5710 break;
5711 case 0xD: {
5712 /* Processor Extended State */
5713 *eax = 0;
5714 *ebx = 0;
5715 *ecx = 0;
5716 *edx = 0;
5717 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
5718 break;
5719 }
5720
5721 if (count == 0) {
5722 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5723 *eax = env->features[FEAT_XSAVE_COMP_LO];
5724 *edx = env->features[FEAT_XSAVE_COMP_HI];
5725 /*
5726 * The initial value of xcr0 and ebx == 0, On host without kvm
5727 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5728 * even through guest update xcr0, this will crash some legacy guest
5729 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5730 */
5731 *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
5732 } else if (count == 1) {
5733 *eax = env->features[FEAT_XSAVE];
5734 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
5735 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5736 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5737 *eax = esa->size;
5738 *ebx = esa->offset;
5739 }
5740 }
5741 break;
5742 }
5743 case 0x14: {
5744 /* Intel Processor Trace Enumeration */
5745 *eax = 0;
5746 *ebx = 0;
5747 *ecx = 0;
5748 *edx = 0;
5749 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5750 !kvm_enabled()) {
5751 break;
5752 }
5753
5754 if (count == 0) {
5755 *eax = INTEL_PT_MAX_SUBLEAF;
5756 *ebx = INTEL_PT_MINIMAL_EBX;
5757 *ecx = INTEL_PT_MINIMAL_ECX;
5758 } else if (count == 1) {
5759 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5760 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5761 }
5762 break;
5763 }
5764 case 0x40000000:
5765 /*
5766 * CPUID code in kvm_arch_init_vcpu() ignores stuff
5767 * set here, but we restrict to TCG none the less.
5768 */
5769 if (tcg_enabled() && cpu->expose_tcg) {
5770 memcpy(signature, "TCGTCGTCGTCG", 12);
5771 *eax = 0x40000001;
5772 *ebx = signature[0];
5773 *ecx = signature[1];
5774 *edx = signature[2];
5775 } else {
5776 *eax = 0;
5777 *ebx = 0;
5778 *ecx = 0;
5779 *edx = 0;
5780 }
5781 break;
5782 case 0x40000001:
5783 *eax = 0;
5784 *ebx = 0;
5785 *ecx = 0;
5786 *edx = 0;
5787 break;
5788 case 0x80000000:
5789 *eax = env->cpuid_xlevel;
5790 *ebx = env->cpuid_vendor1;
5791 *edx = env->cpuid_vendor2;
5792 *ecx = env->cpuid_vendor3;
5793 break;
5794 case 0x80000001:
5795 *eax = env->cpuid_version;
5796 *ebx = 0;
5797 *ecx = env->features[FEAT_8000_0001_ECX];
5798 *edx = env->features[FEAT_8000_0001_EDX];
5799
5800 /* The Linux kernel checks for the CMPLegacy bit and
5801 * discards multiple thread information if it is set.
5802 * So don't set it here for Intel to make Linux guests happy.
5803 */
5804 if (cs->nr_cores * cs->nr_threads > 1) {
5805 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5806 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5807 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
5808 *ecx |= 1 << 1; /* CmpLegacy bit */
5809 }
5810 }
5811 break;
5812 case 0x80000002:
5813 case 0x80000003:
5814 case 0x80000004:
5815 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5816 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5817 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5818 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5819 break;
5820 case 0x80000005:
5821 /* cache info (L1 cache) */
5822 if (cpu->cache_info_passthrough) {
5823 host_cpuid(index, 0, eax, ebx, ecx, edx);
5824 break;
5825 }
5826 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5827 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
5828 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5829 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
5830 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5831 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
5832 break;
5833 case 0x80000006:
5834 /* cache info (L2 cache) */
5835 if (cpu->cache_info_passthrough) {
5836 host_cpuid(index, 0, eax, ebx, ecx, edx);
5837 break;
5838 }
5839 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5840 (L2_DTLB_2M_ENTRIES << 16) |
5841 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5842 (L2_ITLB_2M_ENTRIES);
5843 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5844 (L2_DTLB_4K_ENTRIES << 16) |
5845 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5846 (L2_ITLB_4K_ENTRIES);
5847 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5848 cpu->enable_l3_cache ?
5849 env->cache_info_amd.l3_cache : NULL,
5850 ecx, edx);
5851 break;
5852 case 0x80000007:
5853 *eax = 0;
5854 *ebx = 0;
5855 *ecx = 0;
5856 *edx = env->features[FEAT_8000_0007_EDX];
5857 break;
5858 case 0x80000008:
5859 /* virtual & phys address size in low 2 bytes. */
5860 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5861 /* 64 bit processor */
5862 *eax = cpu->phys_bits; /* configurable physical bits */
5863 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5864 *eax |= 0x00003900; /* 57 bits virtual */
5865 } else {
5866 *eax |= 0x00003000; /* 48 bits virtual */
5867 }
5868 } else {
5869 *eax = cpu->phys_bits;
5870 }
5871 *ebx = env->features[FEAT_8000_0008_EBX];
5872 if (cs->nr_cores * cs->nr_threads > 1) {
5873 /*
5874 * Bits 15:12 is "The number of bits in the initial
5875 * Core::X86::Apic::ApicId[ApicId] value that indicate
5876 * thread ID within a package".
5877 * Bits 7:0 is "The number of threads in the package is NC+1"
5878 */
5879 *ecx = (apicid_pkg_offset(&topo_info) << 12) |
5880 ((cs->nr_cores * cs->nr_threads) - 1);
5881 } else {
5882 *ecx = 0;
5883 }
5884 *edx = 0;
5885 break;
5886 case 0x8000000A:
5887 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5888 *eax = 0x00000001; /* SVM Revision */
5889 *ebx = 0x00000010; /* nr of ASIDs */
5890 *ecx = 0;
5891 *edx = env->features[FEAT_SVM]; /* optional features */
5892 } else {
5893 *eax = 0;
5894 *ebx = 0;
5895 *ecx = 0;
5896 *edx = 0;
5897 }
5898 break;
5899 case 0x8000001D:
5900 *eax = 0;
5901 if (cpu->cache_info_passthrough) {
5902 host_cpuid(index, count, eax, ebx, ecx, edx);
5903 break;
5904 }
5905 switch (count) {
5906 case 0: /* L1 dcache info */
5907 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5908 &topo_info, eax, ebx, ecx, edx);
5909 break;
5910 case 1: /* L1 icache info */
5911 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5912 &topo_info, eax, ebx, ecx, edx);
5913 break;
5914 case 2: /* L2 cache info */
5915 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5916 &topo_info, eax, ebx, ecx, edx);
5917 break;
5918 case 3: /* L3 cache info */
5919 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5920 &topo_info, eax, ebx, ecx, edx);
5921 break;
5922 default: /* end of info */
5923 *eax = *ebx = *ecx = *edx = 0;
5924 break;
5925 }
5926 break;
5927 case 0x8000001E:
5928 if (cpu->core_id <= 255) {
5929 encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5930 } else {
5931 *eax = 0;
5932 *ebx = 0;
5933 *ecx = 0;
5934 *edx = 0;
5935 }
5936 break;
5937 case 0xC0000000:
5938 *eax = env->cpuid_xlevel2;
5939 *ebx = 0;
5940 *ecx = 0;
5941 *edx = 0;
5942 break;
5943 case 0xC0000001:
5944 /* Support for VIA CPU's CPUID instruction */
5945 *eax = env->cpuid_version;
5946 *ebx = 0;
5947 *ecx = 0;
5948 *edx = env->features[FEAT_C000_0001_EDX];
5949 break;
5950 case 0xC0000002:
5951 case 0xC0000003:
5952 case 0xC0000004:
5953 /* Reserved for the future, and now filled with zero */
5954 *eax = 0;
5955 *ebx = 0;
5956 *ecx = 0;
5957 *edx = 0;
5958 break;
5959 case 0x8000001F:
5960 *eax = sev_enabled() ? 0x2 : 0;
5961 *ebx = sev_get_cbit_position();
5962 *ebx |= sev_get_reduced_phys_bits() << 6;
5963 *ecx = 0;
5964 *edx = 0;
5965 break;
5966 default:
5967 /* reserved values: zero */
5968 *eax = 0;
5969 *ebx = 0;
5970 *ecx = 0;
5971 *edx = 0;
5972 break;
5973 }
5974 }
5975
5976 static void x86_cpu_reset(DeviceState *dev)
5977 {
5978 CPUState *s = CPU(dev);
5979 X86CPU *cpu = X86_CPU(s);
5980 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5981 CPUX86State *env = &cpu->env;
5982 target_ulong cr4;
5983 uint64_t xcr0;
5984 int i;
5985
5986 xcc->parent_reset(dev);
5987
5988 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
5989
5990 env->old_exception = -1;
5991
5992 /* init to reset state */
5993
5994 env->hflags2 |= HF2_GIF_MASK;
5995 env->hflags &= ~HF_GUEST_MASK;
5996
5997 cpu_x86_update_cr0(env, 0x60000010);
5998 env->a20_mask = ~0x0;
5999 env->smbase = 0x30000;
6000 env->msr_smi_count = 0;
6001
6002 env->idt.limit = 0xffff;
6003 env->gdt.limit = 0xffff;
6004 env->ldt.limit = 0xffff;
6005 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
6006 env->tr.limit = 0xffff;
6007 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
6008
6009 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
6010 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
6011 DESC_R_MASK | DESC_A_MASK);
6012 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
6013 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6014 DESC_A_MASK);
6015 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
6016 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6017 DESC_A_MASK);
6018 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
6019 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6020 DESC_A_MASK);
6021 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
6022 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6023 DESC_A_MASK);
6024 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6025 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6026 DESC_A_MASK);
6027
6028 env->eip = 0xfff0;
6029 env->regs[R_EDX] = env->cpuid_version;
6030
6031 env->eflags = 0x2;
6032
6033 /* FPU init */
6034 for (i = 0; i < 8; i++) {
6035 env->fptags[i] = 1;
6036 }
6037 cpu_set_fpuc(env, 0x37f);
6038
6039 env->mxcsr = 0x1f80;
6040 /* All units are in INIT state. */
6041 env->xstate_bv = 0;
6042
6043 env->pat = 0x0007040600070406ULL;
6044 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
6045 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6046 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6047 }
6048
6049 memset(env->dr, 0, sizeof(env->dr));
6050 env->dr[6] = DR6_FIXED_1;
6051 env->dr[7] = DR7_FIXED_1;
6052 cpu_breakpoint_remove_all(s, BP_CPU);
6053 cpu_watchpoint_remove_all(s, BP_CPU);
6054
6055 cr4 = 0;
6056 xcr0 = XSTATE_FP_MASK;
6057
6058 #ifdef CONFIG_USER_ONLY
6059 /* Enable all the features for user-mode. */
6060 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
6061 xcr0 |= XSTATE_SSE_MASK;
6062 }
6063 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6064 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6065 if (env->features[esa->feature] & esa->bits) {
6066 xcr0 |= 1ull << i;
6067 }
6068 }
6069
6070 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6071 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6072 }
6073 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6074 cr4 |= CR4_FSGSBASE_MASK;
6075 }
6076 #endif
6077
6078 env->xcr0 = xcr0;
6079 cpu_x86_update_cr4(env, cr4);
6080
6081 /*
6082 * SDM 11.11.5 requires:
6083 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6084 * - IA32_MTRR_PHYSMASKn.V = 0
6085 * All other bits are undefined. For simplification, zero it all.
6086 */
6087 env->mtrr_deftype = 0;
6088 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6089 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6090
6091 env->interrupt_injected = -1;
6092 env->exception_nr = -1;
6093 env->exception_pending = 0;
6094 env->exception_injected = 0;
6095 env->exception_has_payload = false;
6096 env->exception_payload = 0;
6097 env->nmi_injected = false;
6098 #if !defined(CONFIG_USER_ONLY)
6099 /* We hard-wire the BSP to the first CPU. */
6100 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
6101
6102 s->halted = !cpu_is_bsp(cpu);
6103
6104 if (kvm_enabled()) {
6105 kvm_arch_reset_vcpu(cpu);
6106 }
6107 #endif
6108 }
6109
6110 #ifndef CONFIG_USER_ONLY
6111 bool cpu_is_bsp(X86CPU *cpu)
6112 {
6113 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
6114 }
6115
6116 /* TODO: remove me, when reset over QOM tree is implemented */
6117 static void x86_cpu_machine_reset_cb(void *opaque)
6118 {
6119 X86CPU *cpu = opaque;
6120 cpu_reset(CPU(cpu));
6121 }
6122 #endif
6123
6124 static void mce_init(X86CPU *cpu)
6125 {
6126 CPUX86State *cenv = &cpu->env;
6127 unsigned int bank;
6128
6129 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
6130 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
6131 (CPUID_MCE | CPUID_MCA)) {
6132 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6133 (cpu->enable_lmce ? MCG_LMCE_P : 0);
6134 cenv->mcg_ctl = ~(uint64_t)0;
6135 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6136 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6137 }
6138 }
6139 }
6140
6141 #ifndef CONFIG_USER_ONLY
6142 APICCommonClass *apic_get_class(void)
6143 {
6144 const char *apic_type = "apic";
6145
6146 /* TODO: in-kernel irqchip for hvf */
6147 if (kvm_apic_in_kernel()) {
6148 apic_type = "kvm-apic";
6149 } else if (xen_enabled()) {
6150 apic_type = "xen-apic";
6151 }
6152
6153 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6154 }
6155
6156 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6157 {
6158 APICCommonState *apic;
6159 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6160
6161 cpu->apic_state = DEVICE(object_new_with_class(apic_class));
6162
6163 object_property_add_child(OBJECT(cpu), "lapic",
6164 OBJECT(cpu->apic_state));
6165 object_unref(OBJECT(cpu->apic_state));
6166
6167 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
6168 /* TODO: convert to link<> */
6169 apic = APIC_COMMON(cpu->apic_state);
6170 apic->cpu = cpu;
6171 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
6172 }
6173
6174 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6175 {
6176 APICCommonState *apic;
6177 static bool apic_mmio_map_once;
6178
6179 if (cpu->apic_state == NULL) {
6180 return;
6181 }
6182 qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
6183
6184 /* Map APIC MMIO area */
6185 apic = APIC_COMMON(cpu->apic_state);
6186 if (!apic_mmio_map_once) {
6187 memory_region_add_subregion_overlap(get_system_memory(),
6188 apic->apicbase &
6189 MSR_IA32_APICBASE_BASE,
6190 &apic->io_memory,
6191 0x1000);
6192 apic_mmio_map_once = true;
6193 }
6194 }
6195
6196 static void x86_cpu_machine_done(Notifier *n, void *unused)
6197 {
6198 X86CPU *cpu = container_of(n, X86CPU, machine_done);
6199 MemoryRegion *smram =
6200 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6201
6202 if (smram) {
6203 cpu->smram = g_new(MemoryRegion, 1);
6204 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
6205 smram, 0, 4 * GiB);
6206 memory_region_set_enabled(cpu->smram, true);
6207 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6208 }
6209 }
6210 #else
6211 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6212 {
6213 }
6214 #endif
6215
6216 /* Note: Only safe for use on x86(-64) hosts */
6217 static uint32_t x86_host_phys_bits(void)
6218 {
6219 uint32_t eax;
6220 uint32_t host_phys_bits;
6221
6222 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6223 if (eax >= 0x80000008) {
6224 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6225 /* Note: According to AMD doc 25481 rev 2.34 they have a field
6226 * at 23:16 that can specify a maximum physical address bits for
6227 * the guest that can override this value; but I've not seen
6228 * anything with that set.
6229 */
6230 host_phys_bits = eax & 0xff;
6231 } else {
6232 /* It's an odd 64 bit machine that doesn't have the leaf for
6233 * physical address bits; fall back to 36 that's most older
6234 * Intel.
6235 */
6236 host_phys_bits = 36;
6237 }
6238
6239 return host_phys_bits;
6240 }
6241
6242 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6243 {
6244 if (*min < value) {
6245 *min = value;
6246 }
6247 }
6248
6249 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6250 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6251 {
6252 CPUX86State *env = &cpu->env;
6253 FeatureWordInfo *fi = &feature_word_info[w];
6254 uint32_t eax = fi->cpuid.eax;
6255 uint32_t region = eax & 0xF0000000;
6256
6257 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
6258 if (!env->features[w]) {
6259 return;
6260 }
6261
6262 switch (region) {
6263 case 0x00000000:
6264 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6265 break;
6266 case 0x80000000:
6267 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6268 break;
6269 case 0xC0000000:
6270 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6271 break;
6272 }
6273
6274 if (eax == 7) {
6275 x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6276 fi->cpuid.ecx);
6277 }
6278 }
6279
6280 /* Calculate XSAVE components based on the configured CPU feature flags */
6281 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6282 {
6283 CPUX86State *env = &cpu->env;
6284 int i;
6285 uint64_t mask;
6286
6287 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6288 env->features[FEAT_XSAVE_COMP_LO] = 0;
6289 env->features[FEAT_XSAVE_COMP_HI] = 0;
6290 return;
6291 }
6292
6293 mask = 0;
6294 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6295 const ExtSaveArea *esa = &x86_ext_save_areas[i];
6296 if (env->features[esa->feature] & esa->bits) {
6297 mask |= (1ULL << i);
6298 }
6299 }
6300
6301 env->features[FEAT_XSAVE_COMP_LO] = mask;
6302 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
6303 }
6304
6305 /***** Steps involved on loading and filtering CPUID data
6306 *
6307 * When initializing and realizing a CPU object, the steps
6308 * involved in setting up CPUID data are:
6309 *
6310 * 1) Loading CPU model definition (X86CPUDefinition). This is
6311 * implemented by x86_cpu_load_model() and should be completely
6312 * transparent, as it is done automatically by instance_init.
6313 * No code should need to look at X86CPUDefinition structs
6314 * outside instance_init.
6315 *
6316 * 2) CPU expansion. This is done by realize before CPUID
6317 * filtering, and will make sure host/accelerator data is
6318 * loaded for CPU models that depend on host capabilities
6319 * (e.g. "host"). Done by x86_cpu_expand_features().
6320 *
6321 * 3) CPUID filtering. This initializes extra data related to
6322 * CPUID, and checks if the host supports all capabilities
6323 * required by the CPU. Runnability of a CPU model is
6324 * determined at this step. Done by x86_cpu_filter_features().
6325 *
6326 * Some operations don't require all steps to be performed.
6327 * More precisely:
6328 *
6329 * - CPU instance creation (instance_init) will run only CPU
6330 * model loading. CPU expansion can't run at instance_init-time
6331 * because host/accelerator data may be not available yet.
6332 * - CPU realization will perform both CPU model expansion and CPUID
6333 * filtering, and return an error in case one of them fails.
6334 * - query-cpu-definitions needs to run all 3 steps. It needs
6335 * to run CPUID filtering, as the 'unavailable-features'
6336 * field is set based on the filtering results.
6337 * - The query-cpu-model-expansion QMP command only needs to run
6338 * CPU model loading and CPU expansion. It should not filter
6339 * any CPUID data based on host capabilities.
6340 */
6341
6342 /* Expand CPU configuration data, based on configured features
6343 * and host/accelerator capabilities when appropriate.
6344 */
6345 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
6346 {
6347 CPUX86State *env = &cpu->env;
6348 FeatureWord w;
6349 int i;
6350 GList *l;
6351
6352 for (l = plus_features; l; l = l->next) {
6353 const char *prop = l->data;
6354 if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6355 return;
6356 }
6357 }
6358
6359 for (l = minus_features; l; l = l->next) {
6360 const char *prop = l->data;
6361 if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6362 return;
6363 }
6364 }
6365
6366 /*TODO: Now cpu->max_features doesn't overwrite features
6367 * set using QOM properties, and we can convert
6368 * plus_features & minus_features to global properties
6369 * inside x86_cpu_parse_featurestr() too.
6370 */
6371 if (cpu->max_features) {
6372 for (w = 0; w < FEATURE_WORDS; w++) {
6373 /* Override only features that weren't set explicitly
6374 * by the user.
6375 */
6376 env->features[w] |=
6377 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
6378 ~env->user_features[w] &
6379 ~feature_word_info[w].no_autoenable_flags;
6380 }
6381 }
6382
6383 for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6384 FeatureDep *d = &feature_dependencies[i];
6385 if (!(env->features[d->from.index] & d->from.mask)) {
6386 uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
6387
6388 /* Not an error unless the dependent feature was added explicitly. */
6389 mark_unavailable_features(cpu, d->to.index,
6390 unavailable_features & env->user_features[d->to.index],
6391 "This feature depends on other features that were not requested");
6392
6393 env->features[d->to.index] &= ~unavailable_features;
6394 }
6395 }
6396
6397 if (!kvm_enabled() || !cpu->expose_kvm) {
6398 env->features[FEAT_KVM] = 0;
6399 }
6400
6401 x86_cpu_enable_xsave_components(cpu);
6402
6403 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6404 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6405 if (cpu->full_cpuid_auto_level) {
6406 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6407 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6408 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6409 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
6410 x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
6411 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6412 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6413 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
6414 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
6415 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6416 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6417 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
6418
6419 /* Intel Processor Trace requires CPUID[0x14] */
6420 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6421 if (cpu->intel_pt_auto_level) {
6422 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6423 } else if (cpu->env.cpuid_min_level < 0x14) {
6424 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6425 CPUID_7_0_EBX_INTEL_PT,
6426 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,min-level=0x14\"");
6427 }
6428 }
6429
6430 /* CPU topology with multi-dies support requires CPUID[0x1F] */
6431 if (env->nr_dies > 1) {
6432 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6433 }
6434
6435 /* SVM requires CPUID[0x8000000A] */
6436 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6437 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6438 }
6439
6440 /* SEV requires CPUID[0x8000001F] */
6441 if (sev_enabled()) {
6442 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6443 }
6444 }
6445
6446 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6447 if (env->cpuid_level_func7 == UINT32_MAX) {
6448 env->cpuid_level_func7 = env->cpuid_min_level_func7;
6449 }
6450 if (env->cpuid_level == UINT32_MAX) {
6451 env->cpuid_level = env->cpuid_min_level;
6452 }
6453 if (env->cpuid_xlevel == UINT32_MAX) {
6454 env->cpuid_xlevel = env->cpuid_min_xlevel;
6455 }
6456 if (env->cpuid_xlevel2 == UINT32_MAX) {
6457 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
6458 }
6459 }
6460
6461 /*
6462 * Finishes initialization of CPUID data, filters CPU feature
6463 * words based on host availability of each feature.
6464 *
6465 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6466 */
6467 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
6468 {
6469 CPUX86State *env = &cpu->env;
6470 FeatureWord w;
6471 const char *prefix = NULL;
6472
6473 if (verbose) {
6474 prefix = accel_uses_host_cpuid()
6475 ? "host doesn't support requested feature"
6476 : "TCG doesn't support requested feature";
6477 }
6478
6479 for (w = 0; w < FEATURE_WORDS; w++) {
6480 uint64_t host_feat =
6481 x86_cpu_get_supported_feature_word(w, false);
6482 uint64_t requested_features = env->features[w];
6483 uint64_t unavailable_features = requested_features & ~host_feat;
6484 mark_unavailable_features(cpu, w, unavailable_features, prefix);
6485 }
6486
6487 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6488 kvm_enabled()) {
6489 KVMState *s = CPU(cpu)->kvm_state;
6490 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6491 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6492 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6493 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6494 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6495
6496 if (!eax_0 ||
6497 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6498 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6499 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6500 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6501 INTEL_PT_ADDR_RANGES_NUM) ||
6502 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
6503 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6504 (ecx_0 & INTEL_PT_IP_LIP)) {
6505 /*
6506 * Processor Trace capabilities aren't configurable, so if the
6507 * host can't emulate the capabilities we report on
6508 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6509 */
6510 mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
6511 }
6512 }
6513 }
6514
6515 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6516 {
6517 CPUState *cs = CPU(dev);
6518 X86CPU *cpu = X86_CPU(dev);
6519 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6520 CPUX86State *env = &cpu->env;
6521 Error *local_err = NULL;
6522 static bool ht_warned;
6523
6524 if (xcc->host_cpuid_required) {
6525 if (!accel_uses_host_cpuid()) {
6526 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6527 error_setg(&local_err, "CPU model '%s' requires KVM", name);
6528 goto out;
6529 }
6530 }
6531
6532 if (cpu->max_features && accel_uses_host_cpuid()) {
6533 if (enable_cpu_pm) {
6534 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6535 &cpu->mwait.ecx, &cpu->mwait.edx);
6536 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6537 if (kvm_enabled() && kvm_has_waitpkg()) {
6538 env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
6539 }
6540 }
6541 if (kvm_enabled() && cpu->ucode_rev == 0) {
6542 cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6543 MSR_IA32_UCODE_REV);
6544 }
6545 }
6546
6547 if (cpu->ucode_rev == 0) {
6548 /* The default is the same as KVM's. */
6549 if (IS_AMD_CPU(env)) {
6550 cpu->ucode_rev = 0x01000065;
6551 } else {
6552 cpu->ucode_rev = 0x100000000ULL;
6553 }
6554 }
6555
6556 /* mwait extended info: needed for Core compatibility */
6557 /* We always wake on interrupt even if host does not have the capability */
6558 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6559
6560 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6561 error_setg(errp, "apic-id property was not initialized properly");
6562 return;
6563 }
6564
6565 x86_cpu_expand_features(cpu, &local_err);
6566 if (local_err) {
6567 goto out;
6568 }
6569
6570 x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6571
6572 if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6573 error_setg(&local_err,
6574 accel_uses_host_cpuid() ?
6575 "Host doesn't support requested features" :
6576 "TCG doesn't support requested features");
6577 goto out;
6578 }
6579
6580 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6581 * CPUID[1].EDX.
6582 */
6583 if (IS_AMD_CPU(env)) {
6584 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6585 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
6586 & CPUID_EXT2_AMD_ALIASES);
6587 }
6588
6589 /* For 64bit systems think about the number of physical bits to present.
6590 * ideally this should be the same as the host; anything other than matching
6591 * the host can cause incorrect guest behaviour.
6592 * QEMU used to pick the magic value of 40 bits that corresponds to
6593 * consumer AMD devices but nothing else.
6594 */
6595 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6596 if (accel_uses_host_cpuid()) {
6597 uint32_t host_phys_bits = x86_host_phys_bits();
6598 static bool warned;
6599
6600 /* Print a warning if the user set it to a value that's not the
6601 * host value.
6602 */
6603 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6604 !warned) {
6605 warn_report("Host physical bits (%u)"
6606 " does not match phys-bits property (%u)",
6607 host_phys_bits, cpu->phys_bits);
6608 warned = true;
6609 }
6610
6611 if (cpu->host_phys_bits) {
6612 /* The user asked for us to use the host physical bits */
6613 cpu->phys_bits = host_phys_bits;
6614 if (cpu->host_phys_bits_limit &&
6615 cpu->phys_bits > cpu->host_phys_bits_limit) {
6616 cpu->phys_bits = cpu->host_phys_bits_limit;
6617 }
6618 }
6619
6620 if (cpu->phys_bits &&
6621 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6622 cpu->phys_bits < 32)) {
6623 error_setg(errp, "phys-bits should be between 32 and %u "
6624 " (but is %u)",
6625 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6626 return;
6627 }
6628 } else {
6629 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
6630 error_setg(errp, "TCG only supports phys-bits=%u",
6631 TCG_PHYS_ADDR_BITS);
6632 return;
6633 }
6634 }
6635 /* 0 means it was not explicitly set by the user (or by machine
6636 * compat_props or by the host code above). In this case, the default
6637 * is the value used by TCG (40).
6638 */
6639 if (cpu->phys_bits == 0) {
6640 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6641 }
6642 } else {
6643 /* For 32 bit systems don't use the user set value, but keep
6644 * phys_bits consistent with what we tell the guest.
6645 */
6646 if (cpu->phys_bits != 0) {
6647 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6648 return;
6649 }
6650
6651 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6652 cpu->phys_bits = 36;
6653 } else {
6654 cpu->phys_bits = 32;
6655 }
6656 }
6657
6658 /* Cache information initialization */
6659 if (!cpu->legacy_cache) {
6660 if (!xcc->model || !xcc->model->cpudef->cache_info) {
6661 g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6662 error_setg(errp,
6663 "CPU model '%s' doesn't support legacy-cache=off", name);
6664 return;
6665 }
6666 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
6667 *xcc->model->cpudef->cache_info;
6668 } else {
6669 /* Build legacy cache information */
6670 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6671 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6672 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6673 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6674
6675 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6676 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6677 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6678 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6679
6680 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6681 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6682 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6683 env->cache_info_amd.l3_cache = &legacy_l3_cache;
6684 }
6685
6686
6687 cpu_exec_realizefn(cs, &local_err);
6688 if (local_err != NULL) {
6689 error_propagate(errp, local_err);
6690 return;
6691 }
6692
6693 #ifndef CONFIG_USER_ONLY
6694 MachineState *ms = MACHINE(qdev_get_machine());
6695 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
6696
6697 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
6698 x86_cpu_apic_create(cpu, &local_err);
6699 if (local_err != NULL) {
6700 goto out;
6701 }
6702 }
6703 #endif
6704
6705 mce_init(cpu);
6706
6707 #ifndef CONFIG_USER_ONLY
6708 if (tcg_enabled()) {
6709 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
6710 cpu->cpu_as_root = g_new(MemoryRegion, 1);
6711
6712 /* Outer container... */
6713 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
6714 memory_region_set_enabled(cpu->cpu_as_root, true);
6715
6716 /* ... with two regions inside: normal system memory with low
6717 * priority, and...
6718 */
6719 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6720 get_system_memory(), 0, ~0ull);
6721 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6722 memory_region_set_enabled(cpu->cpu_as_mem, true);
6723
6724 cs->num_ases = 2;
6725 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6726 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
6727
6728 /* ... SMRAM with higher priority, linked from /machine/smram. */
6729 cpu->machine_done.notify = x86_cpu_machine_done;
6730 qemu_add_machine_init_done_notifier(&cpu->machine_done);
6731 }
6732 #endif
6733
6734 qemu_init_vcpu(cs);
6735
6736 /*
6737 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6738 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6739 * based on inputs (sockets,cores,threads), it is still better to give
6740 * users a warning.
6741 *
6742 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6743 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6744 */
6745 if (IS_AMD_CPU(env) &&
6746 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6747 cs->nr_threads > 1 && !ht_warned) {
6748 warn_report("This family of AMD CPU doesn't support "
6749 "hyperthreading(%d)",
6750 cs->nr_threads);
6751 error_printf("Please configure -smp options properly"
6752 " or try enabling topoext feature.\n");
6753 ht_warned = true;
6754 }
6755
6756 x86_cpu_apic_realize(cpu, &local_err);
6757 if (local_err != NULL) {
6758 goto out;
6759 }
6760 cpu_reset(cs);
6761
6762 xcc->parent_realize(dev, &local_err);
6763
6764 out:
6765 if (local_err != NULL) {
6766 error_propagate(errp, local_err);
6767 return;
6768 }
6769 }
6770
6771 static void x86_cpu_unrealizefn(DeviceState *dev)
6772 {
6773 X86CPU *cpu = X86_CPU(dev);
6774 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6775
6776 #ifndef CONFIG_USER_ONLY
6777 cpu_remove_sync(CPU(dev));
6778 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6779 #endif
6780
6781 if (cpu->apic_state) {
6782 object_unparent(OBJECT(cpu->apic_state));
6783 cpu->apic_state = NULL;
6784 }
6785
6786 xcc->parent_unrealize(dev);
6787 }
6788
6789 typedef struct BitProperty {
6790 FeatureWord w;
6791 uint64_t mask;
6792 } BitProperty;
6793
6794 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6795 void *opaque, Error **errp)
6796 {
6797 X86CPU *cpu = X86_CPU(obj);
6798 BitProperty *fp = opaque;
6799 uint64_t f = cpu->env.features[fp->w];
6800 bool value = (f & fp->mask) == fp->mask;
6801 visit_type_bool(v, name, &value, errp);
6802 }
6803
6804 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6805 void *opaque, Error **errp)
6806 {
6807 DeviceState *dev = DEVICE(obj);
6808 X86CPU *cpu = X86_CPU(obj);
6809 BitProperty *fp = opaque;
6810 bool value;
6811
6812 if (dev->realized) {
6813 qdev_prop_set_after_realize(dev, name, errp);
6814 return;
6815 }
6816
6817 if (!visit_type_bool(v, name, &value, errp)) {
6818 return;
6819 }
6820
6821 if (value) {
6822 cpu->env.features[fp->w] |= fp->mask;
6823 } else {
6824 cpu->env.features[fp->w] &= ~fp->mask;
6825 }
6826 cpu->env.user_features[fp->w] |= fp->mask;
6827 }
6828
6829 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6830 void *opaque)
6831 {
6832 BitProperty *prop = opaque;
6833 g_free(prop);
6834 }
6835
6836 /* Register a boolean property to get/set a single bit in a uint32_t field.
6837 *
6838 * The same property name can be registered multiple times to make it affect
6839 * multiple bits in the same FeatureWord. In that case, the getter will return
6840 * true only if all bits are set.
6841 */
6842 static void x86_cpu_register_bit_prop(X86CPU *cpu,
6843 const char *prop_name,
6844 FeatureWord w,
6845 int bitnr)
6846 {
6847 BitProperty *fp;
6848 ObjectProperty *op;
6849 uint64_t mask = (1ULL << bitnr);
6850
6851 op = object_property_find(OBJECT(cpu), prop_name);
6852 if (op) {
6853 fp = op->opaque;
6854 assert(fp->w == w);
6855 fp->mask |= mask;
6856 } else {
6857 fp = g_new0(BitProperty, 1);
6858 fp->w = w;
6859 fp->mask = mask;
6860 object_property_add(OBJECT(cpu), prop_name, "bool",
6861 x86_cpu_get_bit_prop,
6862 x86_cpu_set_bit_prop,
6863 x86_cpu_release_bit_prop, fp);
6864 }
6865 }
6866
6867 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6868 FeatureWord w,
6869 int bitnr)
6870 {
6871 FeatureWordInfo *fi = &feature_word_info[w];
6872 const char *name = fi->feat_names[bitnr];
6873
6874 if (!name) {
6875 return;
6876 }
6877
6878 /* Property names should use "-" instead of "_".
6879 * Old names containing underscores are registered as aliases
6880 * using object_property_add_alias()
6881 */
6882 assert(!strchr(name, '_'));
6883 /* aliases don't use "|" delimiters anymore, they are registered
6884 * manually using object_property_add_alias() */
6885 assert(!strchr(name, '|'));
6886 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
6887 }
6888
6889 #if !defined(CONFIG_USER_ONLY)
6890 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6891 {
6892 X86CPU *cpu = X86_CPU(cs);
6893 CPUX86State *env = &cpu->env;
6894 GuestPanicInformation *panic_info = NULL;
6895
6896 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
6897 panic_info = g_malloc0(sizeof(GuestPanicInformation));
6898
6899 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
6900
6901 assert(HV_CRASH_PARAMS >= 5);
6902 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6903 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6904 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6905 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6906 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
6907 }
6908
6909 return panic_info;
6910 }
6911 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6912 const char *name, void *opaque,
6913 Error **errp)
6914 {
6915 CPUState *cs = CPU(obj);
6916 GuestPanicInformation *panic_info;
6917
6918 if (!cs->crash_occurred) {
6919 error_setg(errp, "No crash occured");
6920 return;
6921 }
6922
6923 panic_info = x86_cpu_get_crash_info(cs);
6924 if (panic_info == NULL) {
6925 error_setg(errp, "No crash information");
6926 return;
6927 }
6928
6929 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6930 errp);
6931 qapi_free_GuestPanicInformation(panic_info);
6932 }
6933 #endif /* !CONFIG_USER_ONLY */
6934
6935 static void x86_cpu_initfn(Object *obj)
6936 {
6937 X86CPU *cpu = X86_CPU(obj);
6938 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
6939 CPUX86State *env = &cpu->env;
6940 FeatureWord w;
6941
6942 env->nr_dies = 1;
6943 cpu_set_cpustate_pointers(cpu);
6944
6945 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6946 x86_cpu_get_feature_words,
6947 NULL, NULL, (void *)env->features);
6948 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6949 x86_cpu_get_feature_words,
6950 NULL, NULL, (void *)cpu->filtered_features);
6951
6952 for (w = 0; w < FEATURE_WORDS; w++) {
6953 int bitnr;
6954
6955 for (bitnr = 0; bitnr < 64; bitnr++) {
6956 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6957 }
6958 }
6959
6960 object_property_add_alias(obj, "sse3", obj, "pni");
6961 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6962 object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6963 object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6964 object_property_add_alias(obj, "xd", obj, "nx");
6965 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6966 object_property_add_alias(obj, "i64", obj, "lm");
6967
6968 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6969 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6970 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6971 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6972 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6973 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6974 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6975 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6976 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6977 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6978 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
6979 object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
6980 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6981 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6982 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6983 object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6984 object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6985 object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6986 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6987 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6988 object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6989 object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6990 object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
6991
6992 if (xcc->model) {
6993 x86_cpu_load_model(cpu, xcc->model);
6994 }
6995 }
6996
6997 static int64_t x86_cpu_get_arch_id(CPUState *cs)
6998 {
6999 X86CPU *cpu = X86_CPU(cs);
7000
7001 return cpu->apic_id;
7002 }
7003
7004 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7005 {
7006 X86CPU *cpu = X86_CPU(cs);
7007
7008 return cpu->env.cr[0] & CR0_PG_MASK;
7009 }
7010
7011 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7012 {
7013 X86CPU *cpu = X86_CPU(cs);
7014
7015 cpu->env.eip = value;
7016 }
7017
7018 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
7019 {
7020 X86CPU *cpu = X86_CPU(cs);
7021
7022 cpu->env.eip = tb->pc - tb->cs_base;
7023 }
7024
7025 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
7026 {
7027 X86CPU *cpu = X86_CPU(cs);
7028 CPUX86State *env = &cpu->env;
7029
7030 #if !defined(CONFIG_USER_ONLY)
7031 if (interrupt_request & CPU_INTERRUPT_POLL) {
7032 return CPU_INTERRUPT_POLL;
7033 }
7034 #endif
7035 if (interrupt_request & CPU_INTERRUPT_SIPI) {
7036 return CPU_INTERRUPT_SIPI;
7037 }
7038
7039 if (env->hflags2 & HF2_GIF_MASK) {
7040 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7041 !(env->hflags & HF_SMM_MASK)) {
7042 return CPU_INTERRUPT_SMI;
7043 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7044 !(env->hflags2 & HF2_NMI_MASK)) {
7045 return CPU_INTERRUPT_NMI;
7046 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7047 return CPU_INTERRUPT_MCE;
7048 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7049 (((env->hflags2 & HF2_VINTR_MASK) &&
7050 (env->hflags2 & HF2_HIF_MASK)) ||
7051 (!(env->hflags2 & HF2_VINTR_MASK) &&
7052 (env->eflags & IF_MASK &&
7053 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7054 return CPU_INTERRUPT_HARD;
7055 #if !defined(CONFIG_USER_ONLY)
7056 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
7057 (env->eflags & IF_MASK) &&
7058 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
7059 return CPU_INTERRUPT_VIRQ;
7060 #endif
7061 }
7062 }
7063
7064 return 0;
7065 }
7066
7067 static bool x86_cpu_has_work(CPUState *cs)
7068 {
7069 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
7070 }
7071
7072 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7073 {
7074 X86CPU *cpu = X86_CPU(cs);
7075 CPUX86State *env = &cpu->env;
7076
7077 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7078 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7079 : bfd_mach_i386_i8086);
7080 info->print_insn = print_insn_i386;
7081
7082 info->cap_arch = CS_ARCH_X86;
7083 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7084 : env->hflags & HF_CS32_MASK ? CS_MODE_32
7085 : CS_MODE_16);
7086 info->cap_insn_unit = 1;
7087 info->cap_insn_split = 8;
7088 }
7089
7090 void x86_update_hflags(CPUX86State *env)
7091 {
7092 uint32_t hflags;
7093 #define HFLAG_COPY_MASK \
7094 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7095 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7096 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7097 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7098
7099 hflags = env->hflags & HFLAG_COPY_MASK;
7100 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7101 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7102 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7103 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7104 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7105
7106 if (env->cr[4] & CR4_OSFXSR_MASK) {
7107 hflags |= HF_OSFXSR_MASK;
7108 }
7109
7110 if (env->efer & MSR_EFER_LMA) {
7111 hflags |= HF_LMA_MASK;
7112 }
7113
7114 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7115 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7116 } else {
7117 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7118 (DESC_B_SHIFT - HF_CS32_SHIFT);
7119 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7120 (DESC_B_SHIFT - HF_SS32_SHIFT);
7121 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7122 !(hflags & HF_CS32_MASK)) {
7123 hflags |= HF_ADDSEG_MASK;
7124 } else {
7125 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7126 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7127 }
7128 }
7129 env->hflags = hflags;
7130 }
7131
7132 static Property x86_cpu_properties[] = {
7133 #ifdef CONFIG_USER_ONLY
7134 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7135 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
7136 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7137 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
7138 DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
7139 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
7140 #else
7141 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
7142 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7143 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
7144 DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
7145 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
7146 #endif
7147 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
7148 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
7149
7150 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7151 HYPERV_SPINLOCK_NEVER_NOTIFY),
7152 DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7153 HYPERV_FEAT_RELAXED, 0),
7154 DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7155 HYPERV_FEAT_VAPIC, 0),
7156 DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7157 HYPERV_FEAT_TIME, 0),
7158 DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7159 HYPERV_FEAT_CRASH, 0),
7160 DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7161 HYPERV_FEAT_RESET, 0),
7162 DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7163 HYPERV_FEAT_VPINDEX, 0),
7164 DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7165 HYPERV_FEAT_RUNTIME, 0),
7166 DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7167 HYPERV_FEAT_SYNIC, 0),
7168 DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7169 HYPERV_FEAT_STIMER, 0),
7170 DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7171 HYPERV_FEAT_FREQUENCIES, 0),
7172 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7173 HYPERV_FEAT_REENLIGHTENMENT, 0),
7174 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7175 HYPERV_FEAT_TLBFLUSH, 0),
7176 DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7177 HYPERV_FEAT_EVMCS, 0),
7178 DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7179 HYPERV_FEAT_IPI, 0),
7180 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7181 HYPERV_FEAT_STIMER_DIRECT, 0),
7182 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7183 hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
7184 DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
7185
7186 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
7187 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
7188 DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
7189 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
7190 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
7191 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
7192 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
7193 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
7194 DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7195 UINT32_MAX),
7196 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7197 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7198 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7199 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7200 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7201 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
7202 DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
7203 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
7204 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
7205 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
7206 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
7207 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
7208 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7209 false),
7210 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
7211 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
7212 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7213 true),
7214 /*
7215 * lecacy_cache defaults to true unless the CPU model provides its
7216 * own cache information (see x86_cpu_load_def()).
7217 */
7218 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
7219
7220 /*
7221 * From "Requirements for Implementing the Microsoft
7222 * Hypervisor Interface":
7223 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7224 *
7225 * "Starting with Windows Server 2012 and Windows 8, if
7226 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7227 * the hypervisor imposes no specific limit to the number of VPs.
7228 * In this case, Windows Server 2012 guest VMs may use more than
7229 * 64 VPs, up to the maximum supported number of processors applicable
7230 * to the specific Windows version being used."
7231 */
7232 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
7233 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7234 false),
7235 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7236 true),
7237 DEFINE_PROP_END_OF_LIST()
7238 };
7239
7240 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7241 {
7242 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7243 CPUClass *cc = CPU_CLASS(oc);
7244 DeviceClass *dc = DEVICE_CLASS(oc);
7245
7246 device_class_set_parent_realize(dc, x86_cpu_realizefn,
7247 &xcc->parent_realize);
7248 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7249 &xcc->parent_unrealize);
7250 device_class_set_props(dc, x86_cpu_properties);
7251
7252 device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
7253 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
7254
7255 cc->class_by_name = x86_cpu_class_by_name;
7256 cc->parse_features = x86_cpu_parse_featurestr;
7257 cc->has_work = x86_cpu_has_work;
7258 #ifdef CONFIG_TCG
7259 cc->do_interrupt = x86_cpu_do_interrupt;
7260 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
7261 #endif
7262 cc->dump_state = x86_cpu_dump_state;
7263 cc->set_pc = x86_cpu_set_pc;
7264 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
7265 cc->gdb_read_register = x86_cpu_gdb_read_register;
7266 cc->gdb_write_register = x86_cpu_gdb_write_register;
7267 cc->get_arch_id = x86_cpu_get_arch_id;
7268 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7269 #ifndef CONFIG_USER_ONLY
7270 cc->asidx_from_attrs = x86_asidx_from_attrs;
7271 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
7272 cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
7273 cc->get_crash_info = x86_cpu_get_crash_info;
7274 cc->write_elf64_note = x86_cpu_write_elf64_note;
7275 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7276 cc->write_elf32_note = x86_cpu_write_elf32_note;
7277 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
7278 cc->vmsd = &vmstate_x86_cpu;
7279 #endif
7280 cc->gdb_arch_name = x86_gdb_arch_name;
7281 #ifdef TARGET_X86_64
7282 cc->gdb_core_xml_file = "i386-64bit.xml";
7283 cc->gdb_num_core_regs = 66;
7284 #else
7285 cc->gdb_core_xml_file = "i386-32bit.xml";
7286 cc->gdb_num_core_regs = 50;
7287 #endif
7288 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
7289 cc->debug_excp_handler = breakpoint_handler;
7290 #endif
7291 cc->cpu_exec_enter = x86_cpu_exec_enter;
7292 cc->cpu_exec_exit = x86_cpu_exec_exit;
7293 #ifdef CONFIG_TCG
7294 cc->tcg_initialize = tcg_x86_init;
7295 cc->tlb_fill = x86_cpu_tlb_fill;
7296 #endif
7297 cc->disas_set_info = x86_disas_set_info;
7298
7299 dc->user_creatable = true;
7300
7301 object_class_property_add(oc, "family", "int",
7302 x86_cpuid_version_get_family,
7303 x86_cpuid_version_set_family, NULL, NULL);
7304 object_class_property_add(oc, "model", "int",
7305 x86_cpuid_version_get_model,
7306 x86_cpuid_version_set_model, NULL, NULL);
7307 object_class_property_add(oc, "stepping", "int",
7308 x86_cpuid_version_get_stepping,
7309 x86_cpuid_version_set_stepping, NULL, NULL);
7310 object_class_property_add_str(oc, "vendor",
7311 x86_cpuid_get_vendor,
7312 x86_cpuid_set_vendor);
7313 object_class_property_add_str(oc, "model-id",
7314 x86_cpuid_get_model_id,
7315 x86_cpuid_set_model_id);
7316 object_class_property_add(oc, "tsc-frequency", "int",
7317 x86_cpuid_get_tsc_freq,
7318 x86_cpuid_set_tsc_freq, NULL, NULL);
7319 /*
7320 * The "unavailable-features" property has the same semantics as
7321 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
7322 * QMP command: they list the features that would have prevented the
7323 * CPU from running if the "enforce" flag was set.
7324 */
7325 object_class_property_add(oc, "unavailable-features", "strList",
7326 x86_cpu_get_unavailable_features,
7327 NULL, NULL, NULL);
7328
7329 #if !defined(CONFIG_USER_ONLY)
7330 object_class_property_add(oc, "crash-information", "GuestPanicInformation",
7331 x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
7332 #endif
7333
7334 }
7335
7336 static const TypeInfo x86_cpu_type_info = {
7337 .name = TYPE_X86_CPU,
7338 .parent = TYPE_CPU,
7339 .instance_size = sizeof(X86CPU),
7340 .instance_init = x86_cpu_initfn,
7341 .abstract = true,
7342 .class_size = sizeof(X86CPUClass),
7343 .class_init = x86_cpu_common_class_init,
7344 };
7345
7346
7347 /* "base" CPU model, used by query-cpu-model-expansion */
7348 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7349 {
7350 X86CPUClass *xcc = X86_CPU_CLASS(oc);
7351
7352 xcc->static_model = true;
7353 xcc->migration_safe = true;
7354 xcc->model_description = "base CPU model type with no features enabled";
7355 xcc->ordering = 8;
7356 }
7357
7358 static const TypeInfo x86_base_cpu_type_info = {
7359 .name = X86_CPU_TYPE_NAME("base"),
7360 .parent = TYPE_X86_CPU,
7361 .class_init = x86_cpu_base_class_init,
7362 };
7363
7364 static void x86_cpu_register_types(void)
7365 {
7366 int i;
7367
7368 type_register_static(&x86_cpu_type_info);
7369 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
7370 x86_register_cpudef_types(&builtin_x86_defs[i]);
7371 }
7372 type_register_static(&max_x86_cpu_type_info);
7373 type_register_static(&x86_base_cpu_type_info);
7374 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
7375 type_register_static(&host_x86_cpu_type_info);
7376 #endif
7377 }
7378
7379 type_init(x86_cpu_register_types)
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