2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/hvf.h"
26 #include "sysemu/cpus.h"
29 #include "qemu/error-report.h"
30 #include "qemu/option.h"
31 #include "qemu/config-file.h"
32 #include "qapi/qmp/qerror.h"
33 #include "qapi/qmp/types.h"
35 #include "qapi-types.h"
36 #include "qapi-visit.h"
37 #include "qapi/visitor.h"
38 #include "qom/qom-qobject.h"
39 #include "sysemu/arch_init.h"
41 #if defined(CONFIG_KVM)
42 #include <linux/kvm_para.h>
45 #include "sysemu/sysemu.h"
46 #include "hw/qdev-properties.h"
47 #include "hw/i386/topology.h"
48 #ifndef CONFIG_USER_ONLY
49 #include "exec/address-spaces.h"
51 #include "hw/xen/xen.h"
52 #include "hw/i386/apic_internal.h"
55 #include "disas/capstone.h"
58 /* Cache topology CPUID constants: */
60 /* CPUID Leaf 2 Descriptors */
62 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
63 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
64 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
65 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
68 /* CPUID Leaf 4 constants: */
71 #define CPUID_4_TYPE_DCACHE 1
72 #define CPUID_4_TYPE_ICACHE 2
73 #define CPUID_4_TYPE_UNIFIED 3
75 #define CPUID_4_LEVEL(l) ((l) << 5)
77 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
78 #define CPUID_4_FULLY_ASSOC (1 << 9)
81 #define CPUID_4_NO_INVD_SHARING (1 << 0)
82 #define CPUID_4_INCLUSIVE (1 << 1)
83 #define CPUID_4_COMPLEX_IDX (1 << 2)
85 #define ASSOC_FULL 0xFF
87 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
88 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
98 a == ASSOC_FULL ? 0xF : \
99 0 /* invalid value */)
102 /* Definitions of the hardcoded cache entries we expose: */
105 #define L1D_LINE_SIZE 64
106 #define L1D_ASSOCIATIVITY 8
108 #define L1D_PARTITIONS 1
109 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
110 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
111 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
112 #define L1D_LINES_PER_TAG 1
113 #define L1D_SIZE_KB_AMD 64
114 #define L1D_ASSOCIATIVITY_AMD 2
116 /* L1 instruction cache: */
117 #define L1I_LINE_SIZE 64
118 #define L1I_ASSOCIATIVITY 8
120 #define L1I_PARTITIONS 1
121 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
122 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
123 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
124 #define L1I_LINES_PER_TAG 1
125 #define L1I_SIZE_KB_AMD 64
126 #define L1I_ASSOCIATIVITY_AMD 2
128 /* Level 2 unified cache: */
129 #define L2_LINE_SIZE 64
130 #define L2_ASSOCIATIVITY 16
132 #define L2_PARTITIONS 1
133 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
134 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
135 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
136 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
137 #define L2_LINES_PER_TAG 1
138 #define L2_SIZE_KB_AMD 512
140 /* Level 3 unified cache: */
141 #define L3_SIZE_KB 0 /* disabled */
142 #define L3_ASSOCIATIVITY 0 /* disabled */
143 #define L3_LINES_PER_TAG 0 /* disabled */
144 #define L3_LINE_SIZE 0 /* disabled */
145 #define L3_N_LINE_SIZE 64
146 #define L3_N_ASSOCIATIVITY 16
147 #define L3_N_SETS 16384
148 #define L3_N_PARTITIONS 1
149 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
150 #define L3_N_LINES_PER_TAG 1
151 #define L3_N_SIZE_KB_AMD 16384
153 /* TLB definitions: */
155 #define L1_DTLB_2M_ASSOC 1
156 #define L1_DTLB_2M_ENTRIES 255
157 #define L1_DTLB_4K_ASSOC 1
158 #define L1_DTLB_4K_ENTRIES 255
160 #define L1_ITLB_2M_ASSOC 1
161 #define L1_ITLB_2M_ENTRIES 255
162 #define L1_ITLB_4K_ASSOC 1
163 #define L1_ITLB_4K_ENTRIES 255
165 #define L2_DTLB_2M_ASSOC 0 /* disabled */
166 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
167 #define L2_DTLB_4K_ASSOC 4
168 #define L2_DTLB_4K_ENTRIES 512
170 #define L2_ITLB_2M_ASSOC 0 /* disabled */
171 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
172 #define L2_ITLB_4K_ASSOC 4
173 #define L2_ITLB_4K_ENTRIES 512
177 static void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
178 uint32_t vendor2
, uint32_t vendor3
)
181 for (i
= 0; i
< 4; i
++) {
182 dst
[i
] = vendor1
>> (8 * i
);
183 dst
[i
+ 4] = vendor2
>> (8 * i
);
184 dst
[i
+ 8] = vendor3
>> (8 * i
);
186 dst
[CPUID_VENDOR_SZ
] = '\0';
189 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
190 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
191 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
192 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
193 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
194 CPUID_PSE36 | CPUID_FXSR)
195 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
196 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
197 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
198 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
199 CPUID_PAE | CPUID_SEP | CPUID_APIC)
201 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
202 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
203 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
204 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
205 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
206 /* partly implemented:
207 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
209 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
210 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
211 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
212 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
213 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
214 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
216 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
217 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
218 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
219 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
220 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
223 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
225 #define TCG_EXT2_X86_64_FEATURES 0
228 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
229 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
230 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
231 TCG_EXT2_X86_64_FEATURES)
232 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
233 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
234 #define TCG_EXT4_FEATURES 0
235 #define TCG_SVM_FEATURES 0
236 #define TCG_KVM_FEATURES 0
237 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
238 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
239 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
240 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
243 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
244 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
245 CPUID_7_0_EBX_RDSEED */
246 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE | \
248 #define TCG_7_0_EDX_FEATURES 0
249 #define TCG_APM_FEATURES 0
250 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
251 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
253 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
255 typedef struct FeatureWordInfo
{
256 /* feature flags names are taken from "Intel Processor Identification and
257 * the CPUID Instruction" and AMD's "CPUID Specification".
258 * In cases of disagreement between feature naming conventions,
259 * aliases may be added.
261 const char *feat_names
[32];
262 uint32_t cpuid_eax
; /* Input EAX for CPUID */
263 bool cpuid_needs_ecx
; /* CPUID instruction uses ECX as input */
264 uint32_t cpuid_ecx
; /* Input ECX value for CPUID */
265 int cpuid_reg
; /* output register (R_* constant) */
266 uint32_t tcg_features
; /* Feature flags supported by TCG */
267 uint32_t unmigratable_flags
; /* Feature flags known to be unmigratable */
268 uint32_t migratable_flags
; /* Feature flags known to be migratable */
271 static FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
274 "fpu", "vme", "de", "pse",
275 "tsc", "msr", "pae", "mce",
276 "cx8", "apic", NULL
, "sep",
277 "mtrr", "pge", "mca", "cmov",
278 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
279 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
280 "fxsr", "sse", "sse2", "ss",
281 "ht" /* Intel htt */, "tm", "ia64", "pbe",
283 .cpuid_eax
= 1, .cpuid_reg
= R_EDX
,
284 .tcg_features
= TCG_FEATURES
,
288 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
289 "ds-cpl", "vmx", "smx", "est",
290 "tm2", "ssse3", "cid", NULL
,
291 "fma", "cx16", "xtpr", "pdcm",
292 NULL
, "pcid", "dca", "sse4.1",
293 "sse4.2", "x2apic", "movbe", "popcnt",
294 "tsc-deadline", "aes", "xsave", "osxsave",
295 "avx", "f16c", "rdrand", "hypervisor",
297 .cpuid_eax
= 1, .cpuid_reg
= R_ECX
,
298 .tcg_features
= TCG_EXT_FEATURES
,
300 /* Feature names that are already defined on feature_name[] but
301 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
302 * names on feat_names below. They are copied automatically
303 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
305 [FEAT_8000_0001_EDX
] = {
307 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
308 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
309 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
310 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
311 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
312 "nx", NULL
, "mmxext", NULL
/* mmx */,
313 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
314 NULL
, "lm", "3dnowext", "3dnow",
316 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_EDX
,
317 .tcg_features
= TCG_EXT2_FEATURES
,
319 [FEAT_8000_0001_ECX
] = {
321 "lahf-lm", "cmp-legacy", "svm", "extapic",
322 "cr8legacy", "abm", "sse4a", "misalignsse",
323 "3dnowprefetch", "osvw", "ibs", "xop",
324 "skinit", "wdt", NULL
, "lwp",
325 "fma4", "tce", NULL
, "nodeid-msr",
326 NULL
, "tbm", "topoext", "perfctr-core",
327 "perfctr-nb", NULL
, NULL
, NULL
,
328 NULL
, NULL
, NULL
, NULL
,
330 .cpuid_eax
= 0x80000001, .cpuid_reg
= R_ECX
,
331 .tcg_features
= TCG_EXT3_FEATURES
,
333 [FEAT_C000_0001_EDX
] = {
335 NULL
, NULL
, "xstore", "xstore-en",
336 NULL
, NULL
, "xcrypt", "xcrypt-en",
337 "ace2", "ace2-en", "phe", "phe-en",
338 "pmm", "pmm-en", NULL
, NULL
,
339 NULL
, NULL
, NULL
, NULL
,
340 NULL
, NULL
, NULL
, NULL
,
341 NULL
, NULL
, NULL
, NULL
,
342 NULL
, NULL
, NULL
, NULL
,
344 .cpuid_eax
= 0xC0000001, .cpuid_reg
= R_EDX
,
345 .tcg_features
= TCG_EXT4_FEATURES
,
349 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
350 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
351 NULL
, "kvm-pv-tlb-flush", NULL
, NULL
,
352 NULL
, NULL
, NULL
, NULL
,
353 NULL
, NULL
, NULL
, NULL
,
354 NULL
, NULL
, NULL
, NULL
,
355 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
356 NULL
, NULL
, NULL
, NULL
,
358 .cpuid_eax
= KVM_CPUID_FEATURES
, .cpuid_reg
= R_EAX
,
359 .tcg_features
= TCG_KVM_FEATURES
,
361 [FEAT_HYPERV_EAX
] = {
363 NULL
/* hv_msr_vp_runtime_access */, NULL
/* hv_msr_time_refcount_access */,
364 NULL
/* hv_msr_synic_access */, NULL
/* hv_msr_stimer_access */,
365 NULL
/* hv_msr_apic_access */, NULL
/* hv_msr_hypercall_access */,
366 NULL
/* hv_vpindex_access */, NULL
/* hv_msr_reset_access */,
367 NULL
/* hv_msr_stats_access */, NULL
/* hv_reftsc_access */,
368 NULL
/* hv_msr_idle_access */, NULL
/* hv_msr_frequency_access */,
369 NULL
, NULL
, NULL
, NULL
,
370 NULL
, NULL
, NULL
, NULL
,
371 NULL
, NULL
, NULL
, NULL
,
372 NULL
, NULL
, NULL
, NULL
,
373 NULL
, NULL
, NULL
, NULL
,
375 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EAX
,
377 [FEAT_HYPERV_EBX
] = {
379 NULL
/* hv_create_partitions */, NULL
/* hv_access_partition_id */,
380 NULL
/* hv_access_memory_pool */, NULL
/* hv_adjust_message_buffers */,
381 NULL
/* hv_post_messages */, NULL
/* hv_signal_events */,
382 NULL
/* hv_create_port */, NULL
/* hv_connect_port */,
383 NULL
/* hv_access_stats */, NULL
, NULL
, NULL
/* hv_debugging */,
384 NULL
/* hv_cpu_power_management */, NULL
/* hv_configure_profiler */,
386 NULL
, NULL
, NULL
, NULL
,
387 NULL
, NULL
, NULL
, NULL
,
388 NULL
, NULL
, NULL
, NULL
,
389 NULL
, NULL
, NULL
, NULL
,
391 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EBX
,
393 [FEAT_HYPERV_EDX
] = {
395 NULL
/* hv_mwait */, NULL
/* hv_guest_debugging */,
396 NULL
/* hv_perf_monitor */, NULL
/* hv_cpu_dynamic_part */,
397 NULL
/* hv_hypercall_params_xmm */, NULL
/* hv_guest_idle_state */,
399 NULL
, NULL
, NULL
/* hv_guest_crash_msr */, NULL
,
400 NULL
, NULL
, NULL
, NULL
,
401 NULL
, NULL
, NULL
, NULL
,
402 NULL
, NULL
, NULL
, NULL
,
403 NULL
, NULL
, NULL
, NULL
,
404 NULL
, NULL
, NULL
, NULL
,
406 .cpuid_eax
= 0x40000003, .cpuid_reg
= R_EDX
,
410 "npt", "lbrv", "svm-lock", "nrip-save",
411 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
412 NULL
, NULL
, "pause-filter", NULL
,
413 "pfthreshold", NULL
, NULL
, NULL
,
414 NULL
, NULL
, NULL
, NULL
,
415 NULL
, NULL
, NULL
, NULL
,
416 NULL
, NULL
, NULL
, NULL
,
417 NULL
, NULL
, NULL
, NULL
,
419 .cpuid_eax
= 0x8000000A, .cpuid_reg
= R_EDX
,
420 .tcg_features
= TCG_SVM_FEATURES
,
424 "fsgsbase", "tsc-adjust", NULL
, "bmi1",
425 "hle", "avx2", NULL
, "smep",
426 "bmi2", "erms", "invpcid", "rtm",
427 NULL
, NULL
, "mpx", NULL
,
428 "avx512f", "avx512dq", "rdseed", "adx",
429 "smap", "avx512ifma", "pcommit", "clflushopt",
430 "clwb", NULL
, "avx512pf", "avx512er",
431 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
434 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
436 .tcg_features
= TCG_7_0_EBX_FEATURES
,
440 NULL
, "avx512vbmi", "umip", "pku",
441 "ospke", NULL
, "avx512vbmi2", NULL
,
442 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
443 "avx512bitalg", NULL
, "avx512-vpopcntdq", NULL
,
444 "la57", NULL
, NULL
, NULL
,
445 NULL
, NULL
, "rdpid", NULL
,
446 NULL
, NULL
, NULL
, NULL
,
447 NULL
, NULL
, NULL
, NULL
,
450 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
452 .tcg_features
= TCG_7_0_ECX_FEATURES
,
456 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
457 NULL
, NULL
, NULL
, NULL
,
458 NULL
, NULL
, NULL
, NULL
,
459 NULL
, NULL
, NULL
, NULL
,
460 NULL
, NULL
, NULL
, NULL
,
461 NULL
, NULL
, NULL
, NULL
,
462 NULL
, NULL
, NULL
, NULL
,
463 NULL
, NULL
, NULL
, NULL
,
466 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
468 .tcg_features
= TCG_7_0_EDX_FEATURES
,
470 [FEAT_8000_0007_EDX
] = {
472 NULL
, NULL
, NULL
, NULL
,
473 NULL
, NULL
, NULL
, NULL
,
474 "invtsc", NULL
, NULL
, NULL
,
475 NULL
, NULL
, NULL
, NULL
,
476 NULL
, NULL
, NULL
, NULL
,
477 NULL
, NULL
, NULL
, NULL
,
478 NULL
, NULL
, NULL
, NULL
,
479 NULL
, NULL
, NULL
, NULL
,
481 .cpuid_eax
= 0x80000007,
483 .tcg_features
= TCG_APM_FEATURES
,
484 .unmigratable_flags
= CPUID_APM_INVTSC
,
488 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
489 NULL
, NULL
, NULL
, NULL
,
490 NULL
, NULL
, NULL
, NULL
,
491 NULL
, NULL
, NULL
, NULL
,
492 NULL
, NULL
, NULL
, NULL
,
493 NULL
, NULL
, NULL
, NULL
,
494 NULL
, NULL
, NULL
, NULL
,
495 NULL
, NULL
, NULL
, NULL
,
498 .cpuid_needs_ecx
= true, .cpuid_ecx
= 1,
500 .tcg_features
= TCG_XSAVE_FEATURES
,
504 NULL
, NULL
, "arat", NULL
,
505 NULL
, NULL
, NULL
, NULL
,
506 NULL
, NULL
, NULL
, NULL
,
507 NULL
, NULL
, NULL
, NULL
,
508 NULL
, NULL
, NULL
, NULL
,
509 NULL
, NULL
, NULL
, NULL
,
510 NULL
, NULL
, NULL
, NULL
,
511 NULL
, NULL
, NULL
, NULL
,
513 .cpuid_eax
= 6, .cpuid_reg
= R_EAX
,
514 .tcg_features
= TCG_6_EAX_FEATURES
,
516 [FEAT_XSAVE_COMP_LO
] = {
518 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
521 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
522 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
523 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
526 [FEAT_XSAVE_COMP_HI
] = {
528 .cpuid_needs_ecx
= true, .cpuid_ecx
= 0,
534 typedef struct X86RegisterInfo32
{
535 /* Name of register */
537 /* QAPI enum value register */
538 X86CPURegister32 qapi_enum
;
541 #define REGISTER(reg) \
542 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
543 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
555 typedef struct ExtSaveArea
{
556 uint32_t feature
, bits
;
557 uint32_t offset
, size
;
560 static const ExtSaveArea x86_ext_save_areas
[] = {
562 /* x87 FP state component is always enabled if XSAVE is supported */
563 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
564 /* x87 state is in the legacy region of the XSAVE area */
566 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
569 /* SSE state component is always enabled if XSAVE is supported */
570 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
571 /* SSE state is in the legacy region of the XSAVE area */
573 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
576 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
577 .offset
= offsetof(X86XSaveArea
, avx_state
),
578 .size
= sizeof(XSaveAVX
) },
579 [XSTATE_BNDREGS_BIT
] =
580 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
581 .offset
= offsetof(X86XSaveArea
, bndreg_state
),
582 .size
= sizeof(XSaveBNDREG
) },
583 [XSTATE_BNDCSR_BIT
] =
584 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
585 .offset
= offsetof(X86XSaveArea
, bndcsr_state
),
586 .size
= sizeof(XSaveBNDCSR
) },
587 [XSTATE_OPMASK_BIT
] =
588 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
589 .offset
= offsetof(X86XSaveArea
, opmask_state
),
590 .size
= sizeof(XSaveOpmask
) },
591 [XSTATE_ZMM_Hi256_BIT
] =
592 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
593 .offset
= offsetof(X86XSaveArea
, zmm_hi256_state
),
594 .size
= sizeof(XSaveZMM_Hi256
) },
595 [XSTATE_Hi16_ZMM_BIT
] =
596 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
597 .offset
= offsetof(X86XSaveArea
, hi16_zmm_state
),
598 .size
= sizeof(XSaveHi16_ZMM
) },
600 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
601 .offset
= offsetof(X86XSaveArea
, pkru_state
),
602 .size
= sizeof(XSavePKRU
) },
605 static uint32_t xsave_area_size(uint64_t mask
)
610 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
611 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
612 if ((mask
>> i
) & 1) {
613 ret
= MAX(ret
, esa
->offset
+ esa
->size
);
619 static inline bool accel_uses_host_cpuid(void)
621 return kvm_enabled() || hvf_enabled();
624 static inline uint64_t x86_cpu_xsave_components(X86CPU
*cpu
)
626 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_COMP_HI
]) << 32 |
627 cpu
->env
.features
[FEAT_XSAVE_COMP_LO
];
630 const char *get_register_name_32(unsigned int reg
)
632 if (reg
>= CPU_NB_REGS32
) {
635 return x86_reg_info_32
[reg
].name
;
639 * Returns the set of feature flags that are supported and migratable by
640 * QEMU, for a given FeatureWord.
642 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w
)
644 FeatureWordInfo
*wi
= &feature_word_info
[w
];
648 for (i
= 0; i
< 32; i
++) {
649 uint32_t f
= 1U << i
;
651 /* If the feature name is known, it is implicitly considered migratable,
652 * unless it is explicitly set in unmigratable_flags */
653 if ((wi
->migratable_flags
& f
) ||
654 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
661 void host_cpuid(uint32_t function
, uint32_t count
,
662 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
668 : "=a"(vec
[0]), "=b"(vec
[1]),
669 "=c"(vec
[2]), "=d"(vec
[3])
670 : "0"(function
), "c"(count
) : "cc");
671 #elif defined(__i386__)
672 asm volatile("pusha \n\t"
674 "mov %%eax, 0(%2) \n\t"
675 "mov %%ebx, 4(%2) \n\t"
676 "mov %%ecx, 8(%2) \n\t"
677 "mov %%edx, 12(%2) \n\t"
679 : : "a"(function
), "c"(count
), "S"(vec
)
695 void host_vendor_fms(char *vendor
, int *family
, int *model
, int *stepping
)
697 uint32_t eax
, ebx
, ecx
, edx
;
699 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
700 x86_cpu_vendor_words2str(vendor
, ebx
, edx
, ecx
);
702 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
704 *family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
707 *model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
710 *stepping
= eax
& 0x0F;
714 /* CPU class name definitions: */
716 /* Return type name for a given CPU model name
717 * Caller is responsible for freeing the returned string.
719 static char *x86_cpu_type_name(const char *model_name
)
721 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
724 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
729 if (cpu_model
== NULL
) {
733 typename
= x86_cpu_type_name(cpu_model
);
734 oc
= object_class_by_name(typename
);
739 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
741 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
742 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
743 return g_strndup(class_name
,
744 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
747 struct X86CPUDefinition
{
751 /* vendor is zero-terminated, 12 character ASCII string */
752 char vendor
[CPUID_VENDOR_SZ
+ 1];
756 FeatureWordArray features
;
760 static X86CPUDefinition builtin_x86_defs
[] = {
764 .vendor
= CPUID_VENDOR_AMD
,
768 .features
[FEAT_1_EDX
] =
770 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
772 .features
[FEAT_1_ECX
] =
773 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
774 .features
[FEAT_8000_0001_EDX
] =
775 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
776 .features
[FEAT_8000_0001_ECX
] =
777 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
778 .xlevel
= 0x8000000A,
779 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
784 .vendor
= CPUID_VENDOR_AMD
,
788 /* Missing: CPUID_HT */
789 .features
[FEAT_1_EDX
] =
791 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
792 CPUID_PSE36
| CPUID_VME
,
793 .features
[FEAT_1_ECX
] =
794 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
796 .features
[FEAT_8000_0001_EDX
] =
797 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
798 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
799 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
800 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
802 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
803 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
804 .features
[FEAT_8000_0001_ECX
] =
805 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
806 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
807 /* Missing: CPUID_SVM_LBRV */
808 .features
[FEAT_SVM
] =
810 .xlevel
= 0x8000001A,
811 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
816 .vendor
= CPUID_VENDOR_INTEL
,
820 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
821 .features
[FEAT_1_EDX
] =
823 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
824 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
825 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
826 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
827 .features
[FEAT_1_ECX
] =
828 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
830 .features
[FEAT_8000_0001_EDX
] =
831 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
832 .features
[FEAT_8000_0001_ECX
] =
834 .xlevel
= 0x80000008,
835 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
840 .vendor
= CPUID_VENDOR_INTEL
,
844 /* Missing: CPUID_HT */
845 .features
[FEAT_1_EDX
] =
846 PPRO_FEATURES
| CPUID_VME
|
847 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
849 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
850 .features
[FEAT_1_ECX
] =
851 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
852 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
853 .features
[FEAT_8000_0001_EDX
] =
854 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
855 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
856 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
857 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
858 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
859 .features
[FEAT_8000_0001_ECX
] =
861 .xlevel
= 0x80000008,
862 .model_id
= "Common KVM processor"
867 .vendor
= CPUID_VENDOR_INTEL
,
871 .features
[FEAT_1_EDX
] =
873 .features
[FEAT_1_ECX
] =
875 .xlevel
= 0x80000004,
876 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
881 .vendor
= CPUID_VENDOR_INTEL
,
885 .features
[FEAT_1_EDX
] =
886 PPRO_FEATURES
| CPUID_VME
|
887 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
888 .features
[FEAT_1_ECX
] =
890 .features
[FEAT_8000_0001_ECX
] =
892 .xlevel
= 0x80000008,
893 .model_id
= "Common 32-bit KVM processor"
898 .vendor
= CPUID_VENDOR_INTEL
,
902 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
903 .features
[FEAT_1_EDX
] =
904 PPRO_FEATURES
| CPUID_VME
|
905 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
907 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
908 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
909 .features
[FEAT_1_ECX
] =
910 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
911 .features
[FEAT_8000_0001_EDX
] =
913 .xlevel
= 0x80000008,
914 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
919 .vendor
= CPUID_VENDOR_INTEL
,
923 .features
[FEAT_1_EDX
] =
930 .vendor
= CPUID_VENDOR_INTEL
,
934 .features
[FEAT_1_EDX
] =
941 .vendor
= CPUID_VENDOR_INTEL
,
945 .features
[FEAT_1_EDX
] =
952 .vendor
= CPUID_VENDOR_INTEL
,
956 .features
[FEAT_1_EDX
] =
963 .vendor
= CPUID_VENDOR_AMD
,
967 .features
[FEAT_1_EDX
] =
968 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
970 .features
[FEAT_8000_0001_EDX
] =
971 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
972 .xlevel
= 0x80000008,
973 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
978 .vendor
= CPUID_VENDOR_INTEL
,
982 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
983 .features
[FEAT_1_EDX
] =
985 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
986 CPUID_ACPI
| CPUID_SS
,
987 /* Some CPUs got no CPUID_SEP */
988 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
990 .features
[FEAT_1_ECX
] =
991 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
993 .features
[FEAT_8000_0001_EDX
] =
995 .features
[FEAT_8000_0001_ECX
] =
997 .xlevel
= 0x80000008,
998 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1003 .vendor
= CPUID_VENDOR_INTEL
,
1007 .features
[FEAT_1_EDX
] =
1008 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1009 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1010 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1011 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1012 CPUID_DE
| CPUID_FP87
,
1013 .features
[FEAT_1_ECX
] =
1014 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1015 .features
[FEAT_8000_0001_EDX
] =
1016 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1017 .features
[FEAT_8000_0001_ECX
] =
1019 .xlevel
= 0x80000008,
1020 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1025 .vendor
= CPUID_VENDOR_INTEL
,
1029 .features
[FEAT_1_EDX
] =
1030 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1031 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1032 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1033 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1034 CPUID_DE
| CPUID_FP87
,
1035 .features
[FEAT_1_ECX
] =
1036 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1038 .features
[FEAT_8000_0001_EDX
] =
1039 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1040 .features
[FEAT_8000_0001_ECX
] =
1042 .xlevel
= 0x80000008,
1043 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1048 .vendor
= CPUID_VENDOR_INTEL
,
1052 .features
[FEAT_1_EDX
] =
1053 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1054 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1055 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1056 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1057 CPUID_DE
| CPUID_FP87
,
1058 .features
[FEAT_1_ECX
] =
1059 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1060 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
1061 .features
[FEAT_8000_0001_EDX
] =
1062 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1063 .features
[FEAT_8000_0001_ECX
] =
1065 .xlevel
= 0x80000008,
1066 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
1071 .vendor
= CPUID_VENDOR_INTEL
,
1075 .features
[FEAT_1_EDX
] =
1076 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1077 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1078 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1079 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1080 CPUID_DE
| CPUID_FP87
,
1081 .features
[FEAT_1_ECX
] =
1082 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1083 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1084 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1085 .features
[FEAT_8000_0001_EDX
] =
1086 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
1087 .features
[FEAT_8000_0001_ECX
] =
1089 .features
[FEAT_6_EAX
] =
1091 .xlevel
= 0x80000008,
1092 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1095 .name
= "SandyBridge",
1097 .vendor
= CPUID_VENDOR_INTEL
,
1101 .features
[FEAT_1_EDX
] =
1102 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1103 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1104 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1105 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1106 CPUID_DE
| CPUID_FP87
,
1107 .features
[FEAT_1_ECX
] =
1108 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1109 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1110 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1111 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1113 .features
[FEAT_8000_0001_EDX
] =
1114 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1116 .features
[FEAT_8000_0001_ECX
] =
1118 .features
[FEAT_XSAVE
] =
1119 CPUID_XSAVE_XSAVEOPT
,
1120 .features
[FEAT_6_EAX
] =
1122 .xlevel
= 0x80000008,
1123 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
1126 .name
= "IvyBridge",
1128 .vendor
= CPUID_VENDOR_INTEL
,
1132 .features
[FEAT_1_EDX
] =
1133 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1134 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1135 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1136 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1137 CPUID_DE
| CPUID_FP87
,
1138 .features
[FEAT_1_ECX
] =
1139 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1140 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
1141 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1142 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1143 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1144 .features
[FEAT_7_0_EBX
] =
1145 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
1147 .features
[FEAT_8000_0001_EDX
] =
1148 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1150 .features
[FEAT_8000_0001_ECX
] =
1152 .features
[FEAT_XSAVE
] =
1153 CPUID_XSAVE_XSAVEOPT
,
1154 .features
[FEAT_6_EAX
] =
1156 .xlevel
= 0x80000008,
1157 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1160 .name
= "Haswell-noTSX",
1162 .vendor
= CPUID_VENDOR_INTEL
,
1166 .features
[FEAT_1_EDX
] =
1167 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1168 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1169 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1170 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1171 CPUID_DE
| CPUID_FP87
,
1172 .features
[FEAT_1_ECX
] =
1173 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1174 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1175 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1176 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1177 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1178 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1179 .features
[FEAT_8000_0001_EDX
] =
1180 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1182 .features
[FEAT_8000_0001_ECX
] =
1183 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1184 .features
[FEAT_7_0_EBX
] =
1185 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1186 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1187 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
,
1188 .features
[FEAT_XSAVE
] =
1189 CPUID_XSAVE_XSAVEOPT
,
1190 .features
[FEAT_6_EAX
] =
1192 .xlevel
= 0x80000008,
1193 .model_id
= "Intel Core Processor (Haswell, no TSX)",
1197 .vendor
= CPUID_VENDOR_INTEL
,
1201 .features
[FEAT_1_EDX
] =
1202 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1203 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1204 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1205 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1206 CPUID_DE
| CPUID_FP87
,
1207 .features
[FEAT_1_ECX
] =
1208 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1209 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1210 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1211 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1212 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1213 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1214 .features
[FEAT_8000_0001_EDX
] =
1215 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1217 .features
[FEAT_8000_0001_ECX
] =
1218 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
1219 .features
[FEAT_7_0_EBX
] =
1220 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1221 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1222 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1224 .features
[FEAT_XSAVE
] =
1225 CPUID_XSAVE_XSAVEOPT
,
1226 .features
[FEAT_6_EAX
] =
1228 .xlevel
= 0x80000008,
1229 .model_id
= "Intel Core Processor (Haswell)",
1232 .name
= "Broadwell-noTSX",
1234 .vendor
= CPUID_VENDOR_INTEL
,
1238 .features
[FEAT_1_EDX
] =
1239 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1240 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1241 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1242 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1243 CPUID_DE
| CPUID_FP87
,
1244 .features
[FEAT_1_ECX
] =
1245 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1246 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1247 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1248 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1249 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1250 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1251 .features
[FEAT_8000_0001_EDX
] =
1252 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1254 .features
[FEAT_8000_0001_ECX
] =
1255 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1256 .features
[FEAT_7_0_EBX
] =
1257 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1258 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1259 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1260 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1262 .features
[FEAT_XSAVE
] =
1263 CPUID_XSAVE_XSAVEOPT
,
1264 .features
[FEAT_6_EAX
] =
1266 .xlevel
= 0x80000008,
1267 .model_id
= "Intel Core Processor (Broadwell, no TSX)",
1270 .name
= "Broadwell",
1272 .vendor
= CPUID_VENDOR_INTEL
,
1276 .features
[FEAT_1_EDX
] =
1277 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1278 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1279 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1280 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1281 CPUID_DE
| CPUID_FP87
,
1282 .features
[FEAT_1_ECX
] =
1283 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1284 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1285 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1286 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1287 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1288 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1289 .features
[FEAT_8000_0001_EDX
] =
1290 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1292 .features
[FEAT_8000_0001_ECX
] =
1293 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1294 .features
[FEAT_7_0_EBX
] =
1295 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1296 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1297 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1298 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1300 .features
[FEAT_XSAVE
] =
1301 CPUID_XSAVE_XSAVEOPT
,
1302 .features
[FEAT_6_EAX
] =
1304 .xlevel
= 0x80000008,
1305 .model_id
= "Intel Core Processor (Broadwell)",
1308 .name
= "Skylake-Client",
1310 .vendor
= CPUID_VENDOR_INTEL
,
1314 .features
[FEAT_1_EDX
] =
1315 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1316 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1317 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1318 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1319 CPUID_DE
| CPUID_FP87
,
1320 .features
[FEAT_1_ECX
] =
1321 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1322 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1323 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1324 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1325 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1326 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1327 .features
[FEAT_8000_0001_EDX
] =
1328 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
1330 .features
[FEAT_8000_0001_ECX
] =
1331 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1332 .features
[FEAT_7_0_EBX
] =
1333 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1334 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1335 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1336 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1337 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
,
1338 /* Missing: XSAVES (not supported by some Linux versions,
1339 * including v4.1 to v4.12).
1340 * KVM doesn't yet expose any XSAVES state save component,
1341 * and the only one defined in Skylake (processor tracing)
1342 * probably will block migration anyway.
1344 .features
[FEAT_XSAVE
] =
1345 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1346 CPUID_XSAVE_XGETBV1
,
1347 .features
[FEAT_6_EAX
] =
1349 .xlevel
= 0x80000008,
1350 .model_id
= "Intel Core Processor (Skylake)",
1353 .name
= "Skylake-Server",
1355 .vendor
= CPUID_VENDOR_INTEL
,
1359 .features
[FEAT_1_EDX
] =
1360 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1361 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1362 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1363 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1364 CPUID_DE
| CPUID_FP87
,
1365 .features
[FEAT_1_ECX
] =
1366 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1367 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
1368 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
1369 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
1370 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
1371 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
1372 .features
[FEAT_8000_0001_EDX
] =
1373 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
1374 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1375 .features
[FEAT_8000_0001_ECX
] =
1376 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
1377 .features
[FEAT_7_0_EBX
] =
1378 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
1379 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
1380 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
1381 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
1382 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_CLWB
|
1383 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
1384 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
1385 CPUID_7_0_EBX_AVX512VL
,
1386 /* Missing: XSAVES (not supported by some Linux versions,
1387 * including v4.1 to v4.12).
1388 * KVM doesn't yet expose any XSAVES state save component,
1389 * and the only one defined in Skylake (processor tracing)
1390 * probably will block migration anyway.
1392 .features
[FEAT_XSAVE
] =
1393 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1394 CPUID_XSAVE_XGETBV1
,
1395 .features
[FEAT_6_EAX
] =
1397 .xlevel
= 0x80000008,
1398 .model_id
= "Intel Xeon Processor (Skylake)",
1401 .name
= "Opteron_G1",
1403 .vendor
= CPUID_VENDOR_AMD
,
1407 .features
[FEAT_1_EDX
] =
1408 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1409 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1410 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1411 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1412 CPUID_DE
| CPUID_FP87
,
1413 .features
[FEAT_1_ECX
] =
1415 .features
[FEAT_8000_0001_EDX
] =
1416 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1417 .xlevel
= 0x80000008,
1418 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
1421 .name
= "Opteron_G2",
1423 .vendor
= CPUID_VENDOR_AMD
,
1427 .features
[FEAT_1_EDX
] =
1428 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1429 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1430 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1431 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1432 CPUID_DE
| CPUID_FP87
,
1433 .features
[FEAT_1_ECX
] =
1434 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
1435 /* Missing: CPUID_EXT2_RDTSCP */
1436 .features
[FEAT_8000_0001_EDX
] =
1437 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1438 .features
[FEAT_8000_0001_ECX
] =
1439 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1440 .xlevel
= 0x80000008,
1441 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
1444 .name
= "Opteron_G3",
1446 .vendor
= CPUID_VENDOR_AMD
,
1450 .features
[FEAT_1_EDX
] =
1451 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1452 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1453 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1454 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1455 CPUID_DE
| CPUID_FP87
,
1456 .features
[FEAT_1_ECX
] =
1457 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
1459 /* Missing: CPUID_EXT2_RDTSCP */
1460 .features
[FEAT_8000_0001_EDX
] =
1461 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
1462 .features
[FEAT_8000_0001_ECX
] =
1463 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
1464 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1465 .xlevel
= 0x80000008,
1466 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
1469 .name
= "Opteron_G4",
1471 .vendor
= CPUID_VENDOR_AMD
,
1475 .features
[FEAT_1_EDX
] =
1476 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1477 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1478 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1479 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1480 CPUID_DE
| CPUID_FP87
,
1481 .features
[FEAT_1_ECX
] =
1482 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
1483 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1484 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
1486 /* Missing: CPUID_EXT2_RDTSCP */
1487 .features
[FEAT_8000_0001_EDX
] =
1488 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1490 .features
[FEAT_8000_0001_ECX
] =
1491 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1492 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1493 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1496 .xlevel
= 0x8000001A,
1497 .model_id
= "AMD Opteron 62xx class CPU",
1500 .name
= "Opteron_G5",
1502 .vendor
= CPUID_VENDOR_AMD
,
1506 .features
[FEAT_1_EDX
] =
1507 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
1508 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
1509 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
1510 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
1511 CPUID_DE
| CPUID_FP87
,
1512 .features
[FEAT_1_ECX
] =
1513 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
1514 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
1515 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
1516 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1517 /* Missing: CPUID_EXT2_RDTSCP */
1518 .features
[FEAT_8000_0001_EDX
] =
1519 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
1521 .features
[FEAT_8000_0001_ECX
] =
1522 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
1523 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
1524 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
1527 .xlevel
= 0x8000001A,
1528 .model_id
= "AMD Opteron 63xx class CPU",
1533 .vendor
= CPUID_VENDOR_AMD
,
1537 .features
[FEAT_1_EDX
] =
1538 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
1539 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
1540 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
1541 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
1542 CPUID_VME
| CPUID_FP87
,
1543 .features
[FEAT_1_ECX
] =
1544 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
1545 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
1546 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
1547 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
1548 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
1549 .features
[FEAT_8000_0001_EDX
] =
1550 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
1551 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
1553 .features
[FEAT_8000_0001_ECX
] =
1554 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
1555 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
1556 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
1557 .features
[FEAT_7_0_EBX
] =
1558 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
1559 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
1560 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
1561 CPUID_7_0_EBX_SHA_NI
,
1562 /* Missing: XSAVES (not supported by some Linux versions,
1563 * including v4.1 to v4.12).
1564 * KVM doesn't yet expose any XSAVES state save component.
1566 .features
[FEAT_XSAVE
] =
1567 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
1568 CPUID_XSAVE_XGETBV1
,
1569 .features
[FEAT_6_EAX
] =
1571 .xlevel
= 0x8000000A,
1572 .model_id
= "AMD EPYC Processor",
1576 typedef struct PropValue
{
1577 const char *prop
, *value
;
1580 /* KVM-specific features that are automatically added/removed
1581 * from all CPU models when KVM is enabled.
1583 static PropValue kvm_default_props
[] = {
1584 { "kvmclock", "on" },
1585 { "kvm-nopiodelay", "on" },
1586 { "kvm-asyncpf", "on" },
1587 { "kvm-steal-time", "on" },
1588 { "kvm-pv-eoi", "on" },
1589 { "kvmclock-stable-bit", "on" },
1592 { "monitor", "off" },
1597 /* TCG-specific defaults that override all CPU models when using TCG
1599 static PropValue tcg_default_props
[] = {
1605 void x86_cpu_change_kvm_default(const char *prop
, const char *value
)
1608 for (pv
= kvm_default_props
; pv
->prop
; pv
++) {
1609 if (!strcmp(pv
->prop
, prop
)) {
1615 /* It is valid to call this function only for properties that
1616 * are already present in the kvm_default_props table.
1621 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
1622 bool migratable_only
);
1624 static bool lmce_supported(void)
1626 uint64_t mce_cap
= 0;
1629 if (kvm_ioctl(kvm_state
, KVM_X86_GET_MCE_CAP_SUPPORTED
, &mce_cap
) < 0) {
1634 return !!(mce_cap
& MCG_LMCE_P
);
1637 #define CPUID_MODEL_ID_SZ 48
1640 * cpu_x86_fill_model_id:
1641 * Get CPUID model ID string from host CPU.
1643 * @str should have at least CPUID_MODEL_ID_SZ bytes
1645 * The function does NOT add a null terminator to the string
1648 static int cpu_x86_fill_model_id(char *str
)
1650 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1653 for (i
= 0; i
< 3; i
++) {
1654 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
1655 memcpy(str
+ i
* 16 + 0, &eax
, 4);
1656 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
1657 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
1658 memcpy(str
+ i
* 16 + 12, &edx
, 4);
1663 static Property max_x86_cpu_properties
[] = {
1664 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
1665 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
1666 DEFINE_PROP_END_OF_LIST()
1669 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1671 DeviceClass
*dc
= DEVICE_CLASS(oc
);
1672 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1676 xcc
->model_description
=
1677 "Enables all features supported by the accelerator in the current host";
1679 dc
->props
= max_x86_cpu_properties
;
1682 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
);
1684 static void max_x86_cpu_initfn(Object
*obj
)
1686 X86CPU
*cpu
= X86_CPU(obj
);
1687 CPUX86State
*env
= &cpu
->env
;
1688 KVMState
*s
= kvm_state
;
1690 /* We can't fill the features array here because we don't know yet if
1691 * "migratable" is true or false.
1693 cpu
->max_features
= true;
1695 if (accel_uses_host_cpuid()) {
1696 char vendor
[CPUID_VENDOR_SZ
+ 1] = { 0 };
1697 char model_id
[CPUID_MODEL_ID_SZ
+ 1] = { 0 };
1698 int family
, model
, stepping
;
1699 X86CPUDefinition host_cpudef
= { };
1700 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
1702 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
1703 x86_cpu_vendor_words2str(host_cpudef
.vendor
, ebx
, edx
, ecx
);
1705 host_vendor_fms(vendor
, &family
, &model
, &stepping
);
1707 cpu_x86_fill_model_id(model_id
);
1709 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", &error_abort
);
1710 object_property_set_int(OBJECT(cpu
), family
, "family", &error_abort
);
1711 object_property_set_int(OBJECT(cpu
), model
, "model", &error_abort
);
1712 object_property_set_int(OBJECT(cpu
), stepping
, "stepping",
1714 object_property_set_str(OBJECT(cpu
), model_id
, "model-id",
1717 if (kvm_enabled()) {
1718 env
->cpuid_min_level
=
1719 kvm_arch_get_supported_cpuid(s
, 0x0, 0, R_EAX
);
1720 env
->cpuid_min_xlevel
=
1721 kvm_arch_get_supported_cpuid(s
, 0x80000000, 0, R_EAX
);
1722 env
->cpuid_min_xlevel2
=
1723 kvm_arch_get_supported_cpuid(s
, 0xC0000000, 0, R_EAX
);
1725 env
->cpuid_min_level
=
1726 hvf_get_supported_cpuid(0x0, 0, R_EAX
);
1727 env
->cpuid_min_xlevel
=
1728 hvf_get_supported_cpuid(0x80000000, 0, R_EAX
);
1729 env
->cpuid_min_xlevel2
=
1730 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX
);
1733 if (lmce_supported()) {
1734 object_property_set_bool(OBJECT(cpu
), true, "lmce", &error_abort
);
1737 object_property_set_str(OBJECT(cpu
), CPUID_VENDOR_AMD
,
1738 "vendor", &error_abort
);
1739 object_property_set_int(OBJECT(cpu
), 6, "family", &error_abort
);
1740 object_property_set_int(OBJECT(cpu
), 6, "model", &error_abort
);
1741 object_property_set_int(OBJECT(cpu
), 3, "stepping", &error_abort
);
1742 object_property_set_str(OBJECT(cpu
),
1743 "QEMU TCG CPU version " QEMU_HW_VERSION
,
1744 "model-id", &error_abort
);
1747 object_property_set_bool(OBJECT(cpu
), true, "pmu", &error_abort
);
1750 static const TypeInfo max_x86_cpu_type_info
= {
1751 .name
= X86_CPU_TYPE_NAME("max"),
1752 .parent
= TYPE_X86_CPU
,
1753 .instance_init
= max_x86_cpu_initfn
,
1754 .class_init
= max_x86_cpu_class_init
,
1757 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
1758 static void host_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
1760 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1762 xcc
->host_cpuid_required
= true;
1765 if (kvm_enabled()) {
1766 xcc
->model_description
=
1767 "KVM processor with all supported host features ";
1768 } else if (hvf_enabled()) {
1769 xcc
->model_description
=
1770 "HVF processor with all supported host features ";
1774 static const TypeInfo host_x86_cpu_type_info
= {
1775 .name
= X86_CPU_TYPE_NAME("host"),
1776 .parent
= X86_CPU_TYPE_NAME("max"),
1777 .class_init
= host_x86_cpu_class_init
,
1782 static void report_unavailable_features(FeatureWord w
, uint32_t mask
)
1784 FeatureWordInfo
*f
= &feature_word_info
[w
];
1787 for (i
= 0; i
< 32; ++i
) {
1788 if ((1UL << i
) & mask
) {
1789 const char *reg
= get_register_name_32(f
->cpuid_reg
);
1791 warn_report("%s doesn't support requested feature: "
1792 "CPUID.%02XH:%s%s%s [bit %d]",
1793 accel_uses_host_cpuid() ? "host" : "TCG",
1795 f
->feat_names
[i
] ? "." : "",
1796 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
1801 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
1802 const char *name
, void *opaque
,
1805 X86CPU
*cpu
= X86_CPU(obj
);
1806 CPUX86State
*env
= &cpu
->env
;
1809 value
= (env
->cpuid_version
>> 8) & 0xf;
1811 value
+= (env
->cpuid_version
>> 20) & 0xff;
1813 visit_type_int(v
, name
, &value
, errp
);
1816 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
1817 const char *name
, void *opaque
,
1820 X86CPU
*cpu
= X86_CPU(obj
);
1821 CPUX86State
*env
= &cpu
->env
;
1822 const int64_t min
= 0;
1823 const int64_t max
= 0xff + 0xf;
1824 Error
*local_err
= NULL
;
1827 visit_type_int(v
, name
, &value
, &local_err
);
1829 error_propagate(errp
, local_err
);
1832 if (value
< min
|| value
> max
) {
1833 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1834 name
? name
: "null", value
, min
, max
);
1838 env
->cpuid_version
&= ~0xff00f00;
1840 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
1842 env
->cpuid_version
|= value
<< 8;
1846 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
1847 const char *name
, void *opaque
,
1850 X86CPU
*cpu
= X86_CPU(obj
);
1851 CPUX86State
*env
= &cpu
->env
;
1854 value
= (env
->cpuid_version
>> 4) & 0xf;
1855 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
1856 visit_type_int(v
, name
, &value
, errp
);
1859 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
1860 const char *name
, void *opaque
,
1863 X86CPU
*cpu
= X86_CPU(obj
);
1864 CPUX86State
*env
= &cpu
->env
;
1865 const int64_t min
= 0;
1866 const int64_t max
= 0xff;
1867 Error
*local_err
= NULL
;
1870 visit_type_int(v
, name
, &value
, &local_err
);
1872 error_propagate(errp
, local_err
);
1875 if (value
< min
|| value
> max
) {
1876 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1877 name
? name
: "null", value
, min
, max
);
1881 env
->cpuid_version
&= ~0xf00f0;
1882 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
1885 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
1886 const char *name
, void *opaque
,
1889 X86CPU
*cpu
= X86_CPU(obj
);
1890 CPUX86State
*env
= &cpu
->env
;
1893 value
= env
->cpuid_version
& 0xf;
1894 visit_type_int(v
, name
, &value
, errp
);
1897 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
1898 const char *name
, void *opaque
,
1901 X86CPU
*cpu
= X86_CPU(obj
);
1902 CPUX86State
*env
= &cpu
->env
;
1903 const int64_t min
= 0;
1904 const int64_t max
= 0xf;
1905 Error
*local_err
= NULL
;
1908 visit_type_int(v
, name
, &value
, &local_err
);
1910 error_propagate(errp
, local_err
);
1913 if (value
< min
|| value
> max
) {
1914 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
1915 name
? name
: "null", value
, min
, max
);
1919 env
->cpuid_version
&= ~0xf;
1920 env
->cpuid_version
|= value
& 0xf;
1923 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
1925 X86CPU
*cpu
= X86_CPU(obj
);
1926 CPUX86State
*env
= &cpu
->env
;
1929 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
1930 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
1931 env
->cpuid_vendor3
);
1935 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
1938 X86CPU
*cpu
= X86_CPU(obj
);
1939 CPUX86State
*env
= &cpu
->env
;
1942 if (strlen(value
) != CPUID_VENDOR_SZ
) {
1943 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
1947 env
->cpuid_vendor1
= 0;
1948 env
->cpuid_vendor2
= 0;
1949 env
->cpuid_vendor3
= 0;
1950 for (i
= 0; i
< 4; i
++) {
1951 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
1952 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
1953 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
1957 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
1959 X86CPU
*cpu
= X86_CPU(obj
);
1960 CPUX86State
*env
= &cpu
->env
;
1964 value
= g_malloc(48 + 1);
1965 for (i
= 0; i
< 48; i
++) {
1966 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
1972 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
1975 X86CPU
*cpu
= X86_CPU(obj
);
1976 CPUX86State
*env
= &cpu
->env
;
1979 if (model_id
== NULL
) {
1982 len
= strlen(model_id
);
1983 memset(env
->cpuid_model
, 0, 48);
1984 for (i
= 0; i
< 48; i
++) {
1988 c
= (uint8_t)model_id
[i
];
1990 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
1994 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
1995 void *opaque
, Error
**errp
)
1997 X86CPU
*cpu
= X86_CPU(obj
);
2000 value
= cpu
->env
.tsc_khz
* 1000;
2001 visit_type_int(v
, name
, &value
, errp
);
2004 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
2005 void *opaque
, Error
**errp
)
2007 X86CPU
*cpu
= X86_CPU(obj
);
2008 const int64_t min
= 0;
2009 const int64_t max
= INT64_MAX
;
2010 Error
*local_err
= NULL
;
2013 visit_type_int(v
, name
, &value
, &local_err
);
2015 error_propagate(errp
, local_err
);
2018 if (value
< min
|| value
> max
) {
2019 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
2020 name
? name
: "null", value
, min
, max
);
2024 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
2027 /* Generic getter for "feature-words" and "filtered-features" properties */
2028 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
2029 const char *name
, void *opaque
,
2032 uint32_t *array
= (uint32_t *)opaque
;
2034 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
2035 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
2036 X86CPUFeatureWordInfoList
*list
= NULL
;
2038 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2039 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2040 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
2041 qwi
->cpuid_input_eax
= wi
->cpuid_eax
;
2042 qwi
->has_cpuid_input_ecx
= wi
->cpuid_needs_ecx
;
2043 qwi
->cpuid_input_ecx
= wi
->cpuid_ecx
;
2044 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid_reg
].qapi_enum
;
2045 qwi
->features
= array
[w
];
2047 /* List will be in reverse order, but order shouldn't matter */
2048 list_entries
[w
].next
= list
;
2049 list_entries
[w
].value
= &word_infos
[w
];
2050 list
= &list_entries
[w
];
2053 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
2056 static void x86_get_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2057 void *opaque
, Error
**errp
)
2059 X86CPU
*cpu
= X86_CPU(obj
);
2060 int64_t value
= cpu
->hyperv_spinlock_attempts
;
2062 visit_type_int(v
, name
, &value
, errp
);
2065 static void x86_set_hv_spinlocks(Object
*obj
, Visitor
*v
, const char *name
,
2066 void *opaque
, Error
**errp
)
2068 const int64_t min
= 0xFFF;
2069 const int64_t max
= UINT_MAX
;
2070 X86CPU
*cpu
= X86_CPU(obj
);
2074 visit_type_int(v
, name
, &value
, &err
);
2076 error_propagate(errp
, err
);
2080 if (value
< min
|| value
> max
) {
2081 error_setg(errp
, "Property %s.%s doesn't take value %" PRId64
2082 " (minimum: %" PRId64
", maximum: %" PRId64
")",
2083 object_get_typename(obj
), name
? name
: "null",
2087 cpu
->hyperv_spinlock_attempts
= value
;
2090 static const PropertyInfo qdev_prop_spinlocks
= {
2092 .get
= x86_get_hv_spinlocks
,
2093 .set
= x86_set_hv_spinlocks
,
2096 /* Convert all '_' in a feature string option name to '-', to make feature
2097 * name conform to QOM property naming rule, which uses '-' instead of '_'.
2099 static inline void feat2prop(char *s
)
2101 while ((s
= strchr(s
, '_'))) {
2106 /* Return the feature property name for a feature flag bit */
2107 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
2109 /* XSAVE components are automatically enabled by other features,
2110 * so return the original feature name instead
2112 if (w
== FEAT_XSAVE_COMP_LO
|| w
== FEAT_XSAVE_COMP_HI
) {
2113 int comp
= (w
== FEAT_XSAVE_COMP_HI
) ? bitnr
+ 32 : bitnr
;
2115 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
2116 x86_ext_save_areas
[comp
].bits
) {
2117 w
= x86_ext_save_areas
[comp
].feature
;
2118 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
2123 assert(w
< FEATURE_WORDS
);
2124 return feature_word_info
[w
].feat_names
[bitnr
];
2127 /* Compatibily hack to maintain legacy +-feat semantic,
2128 * where +-feat overwrites any feature set by
2129 * feat=on|feat even if the later is parsed after +-feat
2130 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
2132 static GList
*plus_features
, *minus_features
;
2134 static gint
compare_string(gconstpointer a
, gconstpointer b
)
2136 return g_strcmp0(a
, b
);
2139 /* Parse "+feature,-feature,feature=foo" CPU feature string
2141 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
2144 char *featurestr
; /* Single 'key=value" string being parsed */
2145 static bool cpu_globals_initialized
;
2146 bool ambiguous
= false;
2148 if (cpu_globals_initialized
) {
2151 cpu_globals_initialized
= true;
2157 for (featurestr
= strtok(features
, ",");
2159 featurestr
= strtok(NULL
, ",")) {
2161 const char *val
= NULL
;
2164 GlobalProperty
*prop
;
2166 /* Compatibility syntax: */
2167 if (featurestr
[0] == '+') {
2168 plus_features
= g_list_append(plus_features
,
2169 g_strdup(featurestr
+ 1));
2171 } else if (featurestr
[0] == '-') {
2172 minus_features
= g_list_append(minus_features
,
2173 g_strdup(featurestr
+ 1));
2177 eq
= strchr(featurestr
, '=');
2185 feat2prop(featurestr
);
2188 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
2189 warn_report("Ambiguous CPU model string. "
2190 "Don't mix both \"+%s\" and \"%s=%s\"",
2194 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
2195 warn_report("Ambiguous CPU model string. "
2196 "Don't mix both \"-%s\" and \"%s=%s\"",
2202 if (!strcmp(name
, "tsc-freq")) {
2206 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
2207 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
2208 error_setg(errp
, "bad numerical value %s", val
);
2211 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
2213 name
= "tsc-frequency";
2216 prop
= g_new0(typeof(*prop
), 1);
2217 prop
->driver
= typename
;
2218 prop
->property
= g_strdup(name
);
2219 prop
->value
= g_strdup(val
);
2220 prop
->errp
= &error_fatal
;
2221 qdev_prop_register_global(prop
);
2225 warn_report("Compatibility of ambiguous CPU model "
2226 "strings won't be kept on future QEMU versions");
2230 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
);
2231 static int x86_cpu_filter_features(X86CPU
*cpu
);
2233 /* Check for missing features that may prevent the CPU class from
2234 * running using the current machine and accelerator.
2236 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
2237 strList
**missing_feats
)
2242 strList
**next
= missing_feats
;
2244 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
2245 strList
*new = g_new0(strList
, 1);
2246 new->value
= g_strdup("kvm");
2247 *missing_feats
= new;
2251 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
2253 x86_cpu_expand_features(xc
, &err
);
2255 /* Errors at x86_cpu_expand_features should never happen,
2256 * but in case it does, just report the model as not
2257 * runnable at all using the "type" property.
2259 strList
*new = g_new0(strList
, 1);
2260 new->value
= g_strdup("type");
2265 x86_cpu_filter_features(xc
);
2267 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2268 uint32_t filtered
= xc
->filtered_features
[w
];
2270 for (i
= 0; i
< 32; i
++) {
2271 if (filtered
& (1UL << i
)) {
2272 strList
*new = g_new0(strList
, 1);
2273 new->value
= g_strdup(x86_cpu_feature_name(w
, i
));
2280 object_unref(OBJECT(xc
));
2283 /* Print all cpuid feature names in featureset
2285 static void listflags(FILE *f
, fprintf_function print
, const char **featureset
)
2290 for (bit
= 0; bit
< 32; bit
++) {
2291 if (featureset
[bit
]) {
2292 print(f
, "%s%s", first
? "" : " ", featureset
[bit
]);
2298 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
2299 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
2301 ObjectClass
*class_a
= (ObjectClass
*)a
;
2302 ObjectClass
*class_b
= (ObjectClass
*)b
;
2303 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
2304 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
2305 const char *name_a
, *name_b
;
2307 if (cc_a
->ordering
!= cc_b
->ordering
) {
2308 return cc_a
->ordering
- cc_b
->ordering
;
2310 name_a
= object_class_get_name(class_a
);
2311 name_b
= object_class_get_name(class_b
);
2312 return strcmp(name_a
, name_b
);
2316 static GSList
*get_sorted_cpu_model_list(void)
2318 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
2319 list
= g_slist_sort(list
, x86_cpu_list_compare
);
2323 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
2325 ObjectClass
*oc
= data
;
2326 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2327 CPUListState
*s
= user_data
;
2328 char *name
= x86_cpu_class_get_model_name(cc
);
2329 const char *desc
= cc
->model_description
;
2330 if (!desc
&& cc
->cpu_def
) {
2331 desc
= cc
->cpu_def
->model_id
;
2334 (*s
->cpu_fprintf
)(s
->file
, "x86 %16s %-48s\n",
2339 /* list available CPU models and flags */
2340 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
2345 .cpu_fprintf
= cpu_fprintf
,
2349 (*cpu_fprintf
)(f
, "Available CPUs:\n");
2350 list
= get_sorted_cpu_model_list();
2351 g_slist_foreach(list
, x86_cpu_list_entry
, &s
);
2354 (*cpu_fprintf
)(f
, "\nRecognized CPUID flags:\n");
2355 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
2356 FeatureWordInfo
*fw
= &feature_word_info
[i
];
2358 (*cpu_fprintf
)(f
, " ");
2359 listflags(f
, cpu_fprintf
, fw
->feat_names
);
2360 (*cpu_fprintf
)(f
, "\n");
2364 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
2366 ObjectClass
*oc
= data
;
2367 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
2368 CpuDefinitionInfoList
**cpu_list
= user_data
;
2369 CpuDefinitionInfoList
*entry
;
2370 CpuDefinitionInfo
*info
;
2372 info
= g_malloc0(sizeof(*info
));
2373 info
->name
= x86_cpu_class_get_model_name(cc
);
2374 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
2375 info
->has_unavailable_features
= true;
2376 info
->q_typename
= g_strdup(object_class_get_name(oc
));
2377 info
->migration_safe
= cc
->migration_safe
;
2378 info
->has_migration_safe
= true;
2379 info
->q_static
= cc
->static_model
;
2381 entry
= g_malloc0(sizeof(*entry
));
2382 entry
->value
= info
;
2383 entry
->next
= *cpu_list
;
2387 CpuDefinitionInfoList
*arch_query_cpu_definitions(Error
**errp
)
2389 CpuDefinitionInfoList
*cpu_list
= NULL
;
2390 GSList
*list
= get_sorted_cpu_model_list();
2391 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
2396 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w
,
2397 bool migratable_only
)
2399 FeatureWordInfo
*wi
= &feature_word_info
[w
];
2402 if (kvm_enabled()) {
2403 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid_eax
,
2406 } else if (hvf_enabled()) {
2407 r
= hvf_get_supported_cpuid(wi
->cpuid_eax
,
2410 } else if (tcg_enabled()) {
2411 r
= wi
->tcg_features
;
2415 if (migratable_only
) {
2416 r
&= x86_cpu_get_migratable_flags(w
);
2421 static void x86_cpu_report_filtered_features(X86CPU
*cpu
)
2425 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2426 report_unavailable_features(w
, cpu
->filtered_features
[w
]);
2430 static void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
2433 for (pv
= props
; pv
->prop
; pv
++) {
2437 object_property_parse(OBJECT(cpu
), pv
->value
, pv
->prop
,
2442 /* Load data from X86CPUDefinition into a X86CPU object
2444 static void x86_cpu_load_def(X86CPU
*cpu
, X86CPUDefinition
*def
, Error
**errp
)
2446 CPUX86State
*env
= &cpu
->env
;
2448 char host_vendor
[CPUID_VENDOR_SZ
+ 1];
2451 /*NOTE: any property set by this function should be returned by
2452 * x86_cpu_static_props(), so static expansion of
2453 * query-cpu-model-expansion is always complete.
2456 /* CPU models only set _minimum_ values for level/xlevel: */
2457 object_property_set_uint(OBJECT(cpu
), def
->level
, "min-level", errp
);
2458 object_property_set_uint(OBJECT(cpu
), def
->xlevel
, "min-xlevel", errp
);
2460 object_property_set_int(OBJECT(cpu
), def
->family
, "family", errp
);
2461 object_property_set_int(OBJECT(cpu
), def
->model
, "model", errp
);
2462 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", errp
);
2463 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", errp
);
2464 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2465 env
->features
[w
] = def
->features
[w
];
2468 /* Special cases not set in the X86CPUDefinition structs: */
2469 /* TODO: in-kernel irqchip for hvf */
2470 if (kvm_enabled()) {
2471 if (!kvm_irqchip_in_kernel()) {
2472 x86_cpu_change_kvm_default("x2apic", "off");
2475 x86_cpu_apply_props(cpu
, kvm_default_props
);
2476 } else if (tcg_enabled()) {
2477 x86_cpu_apply_props(cpu
, tcg_default_props
);
2480 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
2482 /* sysenter isn't supported in compatibility mode on AMD,
2483 * syscall isn't supported in compatibility mode on Intel.
2484 * Normally we advertise the actual CPU vendor, but you can
2485 * override this using the 'vendor' property if you want to use
2486 * KVM's sysenter/syscall emulation in compatibility mode and
2487 * when doing cross vendor migration
2489 vendor
= def
->vendor
;
2490 if (accel_uses_host_cpuid()) {
2491 uint32_t ebx
= 0, ecx
= 0, edx
= 0;
2492 host_cpuid(0, 0, NULL
, &ebx
, &ecx
, &edx
);
2493 x86_cpu_vendor_words2str(host_vendor
, ebx
, edx
, ecx
);
2494 vendor
= host_vendor
;
2497 object_property_set_str(OBJECT(cpu
), vendor
, "vendor", errp
);
2501 /* Return a QDict containing keys for all properties that can be included
2502 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
2503 * must be included in the dictionary.
2505 static QDict
*x86_cpu_static_props(void)
2509 static const char *props
[] = {
2527 for (i
= 0; props
[i
]; i
++) {
2528 qdict_put_null(d
, props
[i
]);
2531 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
2532 FeatureWordInfo
*fi
= &feature_word_info
[w
];
2534 for (bit
= 0; bit
< 32; bit
++) {
2535 if (!fi
->feat_names
[bit
]) {
2538 qdict_put_null(d
, fi
->feat_names
[bit
]);
2545 /* Add an entry to @props dict, with the value for property. */
2546 static void x86_cpu_expand_prop(X86CPU
*cpu
, QDict
*props
, const char *prop
)
2548 QObject
*value
= object_property_get_qobject(OBJECT(cpu
), prop
,
2551 qdict_put_obj(props
, prop
, value
);
2554 /* Convert CPU model data from X86CPU object to a property dictionary
2555 * that can recreate exactly the same CPU model.
2557 static void x86_cpu_to_dict(X86CPU
*cpu
, QDict
*props
)
2559 QDict
*sprops
= x86_cpu_static_props();
2560 const QDictEntry
*e
;
2562 for (e
= qdict_first(sprops
); e
; e
= qdict_next(sprops
, e
)) {
2563 const char *prop
= qdict_entry_key(e
);
2564 x86_cpu_expand_prop(cpu
, props
, prop
);
2568 /* Convert CPU model data from X86CPU object to a property dictionary
2569 * that can recreate exactly the same CPU model, including every
2570 * writeable QOM property.
2572 static void x86_cpu_to_dict_full(X86CPU
*cpu
, QDict
*props
)
2574 ObjectPropertyIterator iter
;
2575 ObjectProperty
*prop
;
2577 object_property_iter_init(&iter
, OBJECT(cpu
));
2578 while ((prop
= object_property_iter_next(&iter
))) {
2579 /* skip read-only or write-only properties */
2580 if (!prop
->get
|| !prop
->set
) {
2584 /* "hotplugged" is the only property that is configurable
2585 * on the command-line but will be set differently on CPUs
2586 * created using "-cpu ... -smp ..." and by CPUs created
2587 * on the fly by x86_cpu_from_model() for querying. Skip it.
2589 if (!strcmp(prop
->name
, "hotplugged")) {
2592 x86_cpu_expand_prop(cpu
, props
, prop
->name
);
2596 static void object_apply_props(Object
*obj
, QDict
*props
, Error
**errp
)
2598 const QDictEntry
*prop
;
2601 for (prop
= qdict_first(props
); prop
; prop
= qdict_next(props
, prop
)) {
2602 object_property_set_qobject(obj
, qdict_entry_value(prop
),
2603 qdict_entry_key(prop
), &err
);
2609 error_propagate(errp
, err
);
2612 /* Create X86CPU object according to model+props specification */
2613 static X86CPU
*x86_cpu_from_model(const char *model
, QDict
*props
, Error
**errp
)
2619 xcc
= X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU
, model
));
2621 error_setg(&err
, "CPU model '%s' not found", model
);
2625 xc
= X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc
))));
2627 object_apply_props(OBJECT(xc
), props
, &err
);
2633 x86_cpu_expand_features(xc
, &err
);
2640 error_propagate(errp
, err
);
2641 object_unref(OBJECT(xc
));
2647 CpuModelExpansionInfo
*
2648 arch_query_cpu_model_expansion(CpuModelExpansionType type
,
2649 CpuModelInfo
*model
,
2654 CpuModelExpansionInfo
*ret
= g_new0(CpuModelExpansionInfo
, 1);
2655 QDict
*props
= NULL
;
2656 const char *base_name
;
2658 xc
= x86_cpu_from_model(model
->name
,
2660 qobject_to_qdict(model
->props
) :
2666 props
= qdict_new();
2669 case CPU_MODEL_EXPANSION_TYPE_STATIC
:
2670 /* Static expansion will be based on "base" only */
2672 x86_cpu_to_dict(xc
, props
);
2674 case CPU_MODEL_EXPANSION_TYPE_FULL
:
2675 /* As we don't return every single property, full expansion needs
2676 * to keep the original model name+props, and add extra
2677 * properties on top of that.
2679 base_name
= model
->name
;
2680 x86_cpu_to_dict_full(xc
, props
);
2683 error_setg(&err
, "Unsupportted expansion type");
2688 props
= qdict_new();
2690 x86_cpu_to_dict(xc
, props
);
2692 ret
->model
= g_new0(CpuModelInfo
, 1);
2693 ret
->model
->name
= g_strdup(base_name
);
2694 ret
->model
->props
= QOBJECT(props
);
2695 ret
->model
->has_props
= true;
2698 object_unref(OBJECT(xc
));
2700 error_propagate(errp
, err
);
2701 qapi_free_CpuModelExpansionInfo(ret
);
2707 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
2709 #ifdef TARGET_X86_64
2710 return g_strdup("i386:x86-64");
2712 return g_strdup("i386");
2716 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
2718 X86CPUDefinition
*cpudef
= data
;
2719 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
2721 xcc
->cpu_def
= cpudef
;
2722 xcc
->migration_safe
= true;
2725 static void x86_register_cpudef_type(X86CPUDefinition
*def
)
2727 char *typename
= x86_cpu_type_name(def
->name
);
2730 .parent
= TYPE_X86_CPU
,
2731 .class_init
= x86_cpu_cpudef_class_init
,
2735 /* AMD aliases are handled at runtime based on CPUID vendor, so
2736 * they shouldn't be set on the CPU model table.
2738 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
2744 #if !defined(CONFIG_USER_ONLY)
2746 void cpu_clear_apic_feature(CPUX86State
*env
)
2748 env
->features
[FEAT_1_EDX
] &= ~CPUID_APIC
;
2751 #endif /* !CONFIG_USER_ONLY */
2753 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
2754 uint32_t *eax
, uint32_t *ebx
,
2755 uint32_t *ecx
, uint32_t *edx
)
2757 X86CPU
*cpu
= x86_env_get_cpu(env
);
2758 CPUState
*cs
= CPU(cpu
);
2759 uint32_t pkg_offset
;
2761 uint32_t signature
[3];
2763 /* Calculate & apply limits for different index ranges */
2764 if (index
>= 0xC0000000) {
2765 limit
= env
->cpuid_xlevel2
;
2766 } else if (index
>= 0x80000000) {
2767 limit
= env
->cpuid_xlevel
;
2768 } else if (index
>= 0x40000000) {
2771 limit
= env
->cpuid_level
;
2774 if (index
> limit
) {
2775 /* Intel documentation states that invalid EAX input will
2776 * return the same information as EAX=cpuid_level
2777 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2779 index
= env
->cpuid_level
;
2784 *eax
= env
->cpuid_level
;
2785 *ebx
= env
->cpuid_vendor1
;
2786 *edx
= env
->cpuid_vendor2
;
2787 *ecx
= env
->cpuid_vendor3
;
2790 *eax
= env
->cpuid_version
;
2791 *ebx
= (cpu
->apic_id
<< 24) |
2792 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2793 *ecx
= env
->features
[FEAT_1_ECX
];
2794 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
2795 *ecx
|= CPUID_EXT_OSXSAVE
;
2797 *edx
= env
->features
[FEAT_1_EDX
];
2798 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
2799 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
2804 /* cache info: needed for Pentium Pro compatibility */
2805 if (cpu
->cache_info_passthrough
) {
2806 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
2809 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
2811 if (!cpu
->enable_l3_cache
) {
2814 *ecx
= L3_N_DESCRIPTOR
;
2816 *edx
= (L1D_DESCRIPTOR
<< 16) | \
2817 (L1I_DESCRIPTOR
<< 8) | \
2821 /* cache info: needed for Core compatibility */
2822 if (cpu
->cache_info_passthrough
) {
2823 host_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
2824 *eax
&= ~0xFC000000;
2828 case 0: /* L1 dcache info */
2829 *eax
|= CPUID_4_TYPE_DCACHE
| \
2830 CPUID_4_LEVEL(1) | \
2831 CPUID_4_SELF_INIT_LEVEL
;
2832 *ebx
= (L1D_LINE_SIZE
- 1) | \
2833 ((L1D_PARTITIONS
- 1) << 12) | \
2834 ((L1D_ASSOCIATIVITY
- 1) << 22);
2835 *ecx
= L1D_SETS
- 1;
2836 *edx
= CPUID_4_NO_INVD_SHARING
;
2838 case 1: /* L1 icache info */
2839 *eax
|= CPUID_4_TYPE_ICACHE
| \
2840 CPUID_4_LEVEL(1) | \
2841 CPUID_4_SELF_INIT_LEVEL
;
2842 *ebx
= (L1I_LINE_SIZE
- 1) | \
2843 ((L1I_PARTITIONS
- 1) << 12) | \
2844 ((L1I_ASSOCIATIVITY
- 1) << 22);
2845 *ecx
= L1I_SETS
- 1;
2846 *edx
= CPUID_4_NO_INVD_SHARING
;
2848 case 2: /* L2 cache info */
2849 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2850 CPUID_4_LEVEL(2) | \
2851 CPUID_4_SELF_INIT_LEVEL
;
2852 if (cs
->nr_threads
> 1) {
2853 *eax
|= (cs
->nr_threads
- 1) << 14;
2855 *ebx
= (L2_LINE_SIZE
- 1) | \
2856 ((L2_PARTITIONS
- 1) << 12) | \
2857 ((L2_ASSOCIATIVITY
- 1) << 22);
2859 *edx
= CPUID_4_NO_INVD_SHARING
;
2861 case 3: /* L3 cache info */
2862 if (!cpu
->enable_l3_cache
) {
2869 *eax
|= CPUID_4_TYPE_UNIFIED
| \
2870 CPUID_4_LEVEL(3) | \
2871 CPUID_4_SELF_INIT_LEVEL
;
2872 pkg_offset
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
2873 *eax
|= ((1 << pkg_offset
) - 1) << 14;
2874 *ebx
= (L3_N_LINE_SIZE
- 1) | \
2875 ((L3_N_PARTITIONS
- 1) << 12) | \
2876 ((L3_N_ASSOCIATIVITY
- 1) << 22);
2877 *ecx
= L3_N_SETS
- 1;
2878 *edx
= CPUID_4_INCLUSIVE
| CPUID_4_COMPLEX_IDX
;
2880 default: /* end of info */
2889 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2890 if ((*eax
& 31) && cs
->nr_cores
> 1) {
2891 *eax
|= (cs
->nr_cores
- 1) << 26;
2895 /* mwait info: needed for Core compatibility */
2896 *eax
= 0; /* Smallest monitor-line size in bytes */
2897 *ebx
= 0; /* Largest monitor-line size in bytes */
2898 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
2902 /* Thermal and Power Leaf */
2903 *eax
= env
->features
[FEAT_6_EAX
];
2909 /* Structured Extended Feature Flags Enumeration Leaf */
2911 *eax
= 0; /* Maximum ECX value for sub-leaves */
2912 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
2913 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
2914 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
2915 *ecx
|= CPUID_7_0_ECX_OSPKE
;
2917 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
2926 /* Direct Cache Access Information Leaf */
2927 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
2933 /* Architectural Performance Monitoring Leaf */
2934 if (kvm_enabled() && cpu
->enable_pmu
) {
2935 KVMState
*s
= cs
->kvm_state
;
2937 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
2938 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
2939 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
2940 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
2941 } else if (hvf_enabled() && cpu
->enable_pmu
) {
2942 *eax
= hvf_get_supported_cpuid(0xA, count
, R_EAX
);
2943 *ebx
= hvf_get_supported_cpuid(0xA, count
, R_EBX
);
2944 *ecx
= hvf_get_supported_cpuid(0xA, count
, R_ECX
);
2945 *edx
= hvf_get_supported_cpuid(0xA, count
, R_EDX
);
2954 /* Extended Topology Enumeration Leaf */
2955 if (!cpu
->enable_cpuid_0xb
) {
2956 *eax
= *ebx
= *ecx
= *edx
= 0;
2960 *ecx
= count
& 0xff;
2961 *edx
= cpu
->apic_id
;
2965 *eax
= apicid_core_offset(cs
->nr_cores
, cs
->nr_threads
);
2966 *ebx
= cs
->nr_threads
;
2967 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
2970 *eax
= apicid_pkg_offset(cs
->nr_cores
, cs
->nr_threads
);
2971 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
2972 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
2977 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
2980 assert(!(*eax
& ~0x1f));
2981 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
2984 /* Processor Extended State */
2989 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
2994 *ecx
= xsave_area_size(x86_cpu_xsave_components(cpu
));
2995 *eax
= env
->features
[FEAT_XSAVE_COMP_LO
];
2996 *edx
= env
->features
[FEAT_XSAVE_COMP_HI
];
2998 } else if (count
== 1) {
2999 *eax
= env
->features
[FEAT_XSAVE
];
3000 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
3001 if ((x86_cpu_xsave_components(cpu
) >> count
) & 1) {
3002 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
3011 * CPUID code in kvm_arch_init_vcpu() ignores stuff
3012 * set here, but we restrict to TCG none the less.
3014 if (tcg_enabled() && cpu
->expose_tcg
) {
3015 memcpy(signature
, "TCGTCGTCGTCG", 12);
3017 *ebx
= signature
[0];
3018 *ecx
= signature
[1];
3019 *edx
= signature
[2];
3034 *eax
= env
->cpuid_xlevel
;
3035 *ebx
= env
->cpuid_vendor1
;
3036 *edx
= env
->cpuid_vendor2
;
3037 *ecx
= env
->cpuid_vendor3
;
3040 *eax
= env
->cpuid_version
;
3042 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
3043 *edx
= env
->features
[FEAT_8000_0001_EDX
];
3045 /* The Linux kernel checks for the CMPLegacy bit and
3046 * discards multiple thread information if it is set.
3047 * So don't set it here for Intel to make Linux guests happy.
3049 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3050 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
3051 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
3052 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
3053 *ecx
|= 1 << 1; /* CmpLegacy bit */
3060 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
3061 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
3062 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
3063 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
3066 /* cache info (L1 cache) */
3067 if (cpu
->cache_info_passthrough
) {
3068 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3071 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) | \
3072 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
3073 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) | \
3074 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
3075 *ecx
= (L1D_SIZE_KB_AMD
<< 24) | (L1D_ASSOCIATIVITY_AMD
<< 16) | \
3076 (L1D_LINES_PER_TAG
<< 8) | (L1D_LINE_SIZE
);
3077 *edx
= (L1I_SIZE_KB_AMD
<< 24) | (L1I_ASSOCIATIVITY_AMD
<< 16) | \
3078 (L1I_LINES_PER_TAG
<< 8) | (L1I_LINE_SIZE
);
3081 /* cache info (L2 cache) */
3082 if (cpu
->cache_info_passthrough
) {
3083 host_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
3086 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) | \
3087 (L2_DTLB_2M_ENTRIES
<< 16) | \
3088 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) | \
3089 (L2_ITLB_2M_ENTRIES
);
3090 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) | \
3091 (L2_DTLB_4K_ENTRIES
<< 16) | \
3092 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) | \
3093 (L2_ITLB_4K_ENTRIES
);
3094 *ecx
= (L2_SIZE_KB_AMD
<< 16) | \
3095 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY
) << 12) | \
3096 (L2_LINES_PER_TAG
<< 8) | (L2_LINE_SIZE
);
3097 if (!cpu
->enable_l3_cache
) {
3098 *edx
= ((L3_SIZE_KB
/ 512) << 18) | \
3099 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY
) << 12) | \
3100 (L3_LINES_PER_TAG
<< 8) | (L3_LINE_SIZE
);
3102 *edx
= ((L3_N_SIZE_KB_AMD
/ 512) << 18) | \
3103 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY
) << 12) | \
3104 (L3_N_LINES_PER_TAG
<< 8) | (L3_N_LINE_SIZE
);
3111 *edx
= env
->features
[FEAT_8000_0007_EDX
];
3114 /* virtual & phys address size in low 2 bytes. */
3115 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
3116 /* 64 bit processor */
3117 *eax
= cpu
->phys_bits
; /* configurable physical bits */
3118 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
3119 *eax
|= 0x00003900; /* 57 bits virtual */
3121 *eax
|= 0x00003000; /* 48 bits virtual */
3124 *eax
= cpu
->phys_bits
;
3129 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
3130 *ecx
|= (cs
->nr_cores
* cs
->nr_threads
) - 1;
3134 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
3135 *eax
= 0x00000001; /* SVM Revision */
3136 *ebx
= 0x00000010; /* nr of ASIDs */
3138 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
3147 *eax
= env
->cpuid_xlevel2
;
3153 /* Support for VIA CPU's CPUID instruction */
3154 *eax
= env
->cpuid_version
;
3157 *edx
= env
->features
[FEAT_C000_0001_EDX
];
3162 /* Reserved for the future, and now filled with zero */
3169 /* reserved values: zero */
3178 /* CPUClass::reset() */
3179 static void x86_cpu_reset(CPUState
*s
)
3181 X86CPU
*cpu
= X86_CPU(s
);
3182 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
3183 CPUX86State
*env
= &cpu
->env
;
3188 xcc
->parent_reset(s
);
3190 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
3192 env
->old_exception
= -1;
3194 /* init to reset state */
3196 env
->hflags2
|= HF2_GIF_MASK
;
3198 cpu_x86_update_cr0(env
, 0x60000010);
3199 env
->a20_mask
= ~0x0;
3200 env
->smbase
= 0x30000;
3202 env
->idt
.limit
= 0xffff;
3203 env
->gdt
.limit
= 0xffff;
3204 env
->ldt
.limit
= 0xffff;
3205 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
3206 env
->tr
.limit
= 0xffff;
3207 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
3209 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
3210 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
3211 DESC_R_MASK
| DESC_A_MASK
);
3212 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
3213 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3215 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
3216 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3218 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
3219 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3221 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
3222 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3224 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
3225 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
3229 env
->regs
[R_EDX
] = env
->cpuid_version
;
3234 for (i
= 0; i
< 8; i
++) {
3237 cpu_set_fpuc(env
, 0x37f);
3239 env
->mxcsr
= 0x1f80;
3240 /* All units are in INIT state. */
3243 env
->pat
= 0x0007040600070406ULL
;
3244 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
3246 memset(env
->dr
, 0, sizeof(env
->dr
));
3247 env
->dr
[6] = DR6_FIXED_1
;
3248 env
->dr
[7] = DR7_FIXED_1
;
3249 cpu_breakpoint_remove_all(s
, BP_CPU
);
3250 cpu_watchpoint_remove_all(s
, BP_CPU
);
3253 xcr0
= XSTATE_FP_MASK
;
3255 #ifdef CONFIG_USER_ONLY
3256 /* Enable all the features for user-mode. */
3257 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
3258 xcr0
|= XSTATE_SSE_MASK
;
3260 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3261 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3262 if (env
->features
[esa
->feature
] & esa
->bits
) {
3267 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
3268 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
3270 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
3271 cr4
|= CR4_FSGSBASE_MASK
;
3276 cpu_x86_update_cr4(env
, cr4
);
3279 * SDM 11.11.5 requires:
3280 * - IA32_MTRR_DEF_TYPE MSR.E = 0
3281 * - IA32_MTRR_PHYSMASKn.V = 0
3282 * All other bits are undefined. For simplification, zero it all.
3284 env
->mtrr_deftype
= 0;
3285 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
3286 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
3288 #if !defined(CONFIG_USER_ONLY)
3289 /* We hard-wire the BSP to the first CPU. */
3290 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
3292 s
->halted
= !cpu_is_bsp(cpu
);
3294 if (kvm_enabled()) {
3295 kvm_arch_reset_vcpu(cpu
);
3297 else if (hvf_enabled()) {
3303 #ifndef CONFIG_USER_ONLY
3304 bool cpu_is_bsp(X86CPU
*cpu
)
3306 return cpu_get_apic_base(cpu
->apic_state
) & MSR_IA32_APICBASE_BSP
;
3309 /* TODO: remove me, when reset over QOM tree is implemented */
3310 static void x86_cpu_machine_reset_cb(void *opaque
)
3312 X86CPU
*cpu
= opaque
;
3313 cpu_reset(CPU(cpu
));
3317 static void mce_init(X86CPU
*cpu
)
3319 CPUX86State
*cenv
= &cpu
->env
;
3322 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
3323 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
3324 (CPUID_MCE
| CPUID_MCA
)) {
3325 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
3326 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
3327 cenv
->mcg_ctl
= ~(uint64_t)0;
3328 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
3329 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
3334 #ifndef CONFIG_USER_ONLY
3335 APICCommonClass
*apic_get_class(void)
3337 const char *apic_type
= "apic";
3339 /* TODO: in-kernel irqchip for hvf */
3340 if (kvm_apic_in_kernel()) {
3341 apic_type
= "kvm-apic";
3342 } else if (xen_enabled()) {
3343 apic_type
= "xen-apic";
3346 return APIC_COMMON_CLASS(object_class_by_name(apic_type
));
3349 static void x86_cpu_apic_create(X86CPU
*cpu
, Error
**errp
)
3351 APICCommonState
*apic
;
3352 ObjectClass
*apic_class
= OBJECT_CLASS(apic_get_class());
3354 cpu
->apic_state
= DEVICE(object_new(object_class_get_name(apic_class
)));
3356 object_property_add_child(OBJECT(cpu
), "lapic",
3357 OBJECT(cpu
->apic_state
), &error_abort
);
3358 object_unref(OBJECT(cpu
->apic_state
));
3360 qdev_prop_set_uint32(cpu
->apic_state
, "id", cpu
->apic_id
);
3361 /* TODO: convert to link<> */
3362 apic
= APIC_COMMON(cpu
->apic_state
);
3364 apic
->apicbase
= APIC_DEFAULT_ADDRESS
| MSR_IA32_APICBASE_ENABLE
;
3367 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3369 APICCommonState
*apic
;
3370 static bool apic_mmio_map_once
;
3372 if (cpu
->apic_state
== NULL
) {
3375 object_property_set_bool(OBJECT(cpu
->apic_state
), true, "realized",
3378 /* Map APIC MMIO area */
3379 apic
= APIC_COMMON(cpu
->apic_state
);
3380 if (!apic_mmio_map_once
) {
3381 memory_region_add_subregion_overlap(get_system_memory(),
3383 MSR_IA32_APICBASE_BASE
,
3386 apic_mmio_map_once
= true;
3390 static void x86_cpu_machine_done(Notifier
*n
, void *unused
)
3392 X86CPU
*cpu
= container_of(n
, X86CPU
, machine_done
);
3393 MemoryRegion
*smram
=
3394 (MemoryRegion
*) object_resolve_path("/machine/smram", NULL
);
3397 cpu
->smram
= g_new(MemoryRegion
, 1);
3398 memory_region_init_alias(cpu
->smram
, OBJECT(cpu
), "smram",
3399 smram
, 0, 1ull << 32);
3400 memory_region_set_enabled(cpu
->smram
, true);
3401 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->smram
, 1);
3405 static void x86_cpu_apic_realize(X86CPU
*cpu
, Error
**errp
)
3410 /* Note: Only safe for use on x86(-64) hosts */
3411 static uint32_t x86_host_phys_bits(void)
3414 uint32_t host_phys_bits
;
3416 host_cpuid(0x80000000, 0, &eax
, NULL
, NULL
, NULL
);
3417 if (eax
>= 0x80000008) {
3418 host_cpuid(0x80000008, 0, &eax
, NULL
, NULL
, NULL
);
3419 /* Note: According to AMD doc 25481 rev 2.34 they have a field
3420 * at 23:16 that can specify a maximum physical address bits for
3421 * the guest that can override this value; but I've not seen
3422 * anything with that set.
3424 host_phys_bits
= eax
& 0xff;
3426 /* It's an odd 64 bit machine that doesn't have the leaf for
3427 * physical address bits; fall back to 36 that's most older
3430 host_phys_bits
= 36;
3433 return host_phys_bits
;
3436 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
3443 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
3444 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
3446 CPUX86State
*env
= &cpu
->env
;
3447 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3448 uint32_t eax
= fi
->cpuid_eax
;
3449 uint32_t region
= eax
& 0xF0000000;
3451 if (!env
->features
[w
]) {
3457 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
3460 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
3463 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
3468 /* Calculate XSAVE components based on the configured CPU feature flags */
3469 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
3471 CPUX86State
*env
= &cpu
->env
;
3475 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
3480 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
3481 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
3482 if (env
->features
[esa
->feature
] & esa
->bits
) {
3483 mask
|= (1ULL << i
);
3487 env
->features
[FEAT_XSAVE_COMP_LO
] = mask
;
3488 env
->features
[FEAT_XSAVE_COMP_HI
] = mask
>> 32;
3491 /***** Steps involved on loading and filtering CPUID data
3493 * When initializing and realizing a CPU object, the steps
3494 * involved in setting up CPUID data are:
3496 * 1) Loading CPU model definition (X86CPUDefinition). This is
3497 * implemented by x86_cpu_load_def() and should be completely
3498 * transparent, as it is done automatically by instance_init.
3499 * No code should need to look at X86CPUDefinition structs
3500 * outside instance_init.
3502 * 2) CPU expansion. This is done by realize before CPUID
3503 * filtering, and will make sure host/accelerator data is
3504 * loaded for CPU models that depend on host capabilities
3505 * (e.g. "host"). Done by x86_cpu_expand_features().
3507 * 3) CPUID filtering. This initializes extra data related to
3508 * CPUID, and checks if the host supports all capabilities
3509 * required by the CPU. Runnability of a CPU model is
3510 * determined at this step. Done by x86_cpu_filter_features().
3512 * Some operations don't require all steps to be performed.
3515 * - CPU instance creation (instance_init) will run only CPU
3516 * model loading. CPU expansion can't run at instance_init-time
3517 * because host/accelerator data may be not available yet.
3518 * - CPU realization will perform both CPU model expansion and CPUID
3519 * filtering, and return an error in case one of them fails.
3520 * - query-cpu-definitions needs to run all 3 steps. It needs
3521 * to run CPUID filtering, as the 'unavailable-features'
3522 * field is set based on the filtering results.
3523 * - The query-cpu-model-expansion QMP command only needs to run
3524 * CPU model loading and CPU expansion. It should not filter
3525 * any CPUID data based on host capabilities.
3528 /* Expand CPU configuration data, based on configured features
3529 * and host/accelerator capabilities when appropriate.
3531 static void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
3533 CPUX86State
*env
= &cpu
->env
;
3536 Error
*local_err
= NULL
;
3538 /*TODO: Now cpu->max_features doesn't overwrite features
3539 * set using QOM properties, and we can convert
3540 * plus_features & minus_features to global properties
3541 * inside x86_cpu_parse_featurestr() too.
3543 if (cpu
->max_features
) {
3544 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3545 /* Override only features that weren't set explicitly
3549 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
3550 ~env
->user_features
[w
];
3554 for (l
= plus_features
; l
; l
= l
->next
) {
3555 const char *prop
= l
->data
;
3556 object_property_set_bool(OBJECT(cpu
), true, prop
, &local_err
);
3562 for (l
= minus_features
; l
; l
= l
->next
) {
3563 const char *prop
= l
->data
;
3564 object_property_set_bool(OBJECT(cpu
), false, prop
, &local_err
);
3570 if (!kvm_enabled() || !cpu
->expose_kvm
) {
3571 env
->features
[FEAT_KVM
] = 0;
3574 x86_cpu_enable_xsave_components(cpu
);
3576 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
3577 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
3578 if (cpu
->full_cpuid_auto_level
) {
3579 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
3580 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
3581 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
3582 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
3583 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
3584 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
3585 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
3586 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
3587 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
3588 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
3589 /* SVM requires CPUID[0x8000000A] */
3590 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
3591 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
3595 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
3596 if (env
->cpuid_level
== UINT32_MAX
) {
3597 env
->cpuid_level
= env
->cpuid_min_level
;
3599 if (env
->cpuid_xlevel
== UINT32_MAX
) {
3600 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
3602 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
3603 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
3607 if (local_err
!= NULL
) {
3608 error_propagate(errp
, local_err
);
3613 * Finishes initialization of CPUID data, filters CPU feature
3614 * words based on host availability of each feature.
3616 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
3618 static int x86_cpu_filter_features(X86CPU
*cpu
)
3620 CPUX86State
*env
= &cpu
->env
;
3624 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
3625 uint32_t host_feat
=
3626 x86_cpu_get_supported_feature_word(w
, false);
3627 uint32_t requested_features
= env
->features
[w
];
3628 env
->features
[w
] &= host_feat
;
3629 cpu
->filtered_features
[w
] = requested_features
& ~env
->features
[w
];
3630 if (cpu
->filtered_features
[w
]) {
3638 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
3639 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
3640 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
3641 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
3642 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
3643 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
3644 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
3646 CPUState
*cs
= CPU(dev
);
3647 X86CPU
*cpu
= X86_CPU(dev
);
3648 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
3649 CPUX86State
*env
= &cpu
->env
;
3650 Error
*local_err
= NULL
;
3651 static bool ht_warned
;
3653 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
3654 char *name
= x86_cpu_class_get_model_name(xcc
);
3655 error_setg(&local_err
, "CPU model '%s' requires KVM", name
);
3660 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
3661 error_setg(errp
, "apic-id property was not initialized properly");
3665 x86_cpu_expand_features(cpu
, &local_err
);
3670 if (x86_cpu_filter_features(cpu
) &&
3671 (cpu
->check_cpuid
|| cpu
->enforce_cpuid
)) {
3672 x86_cpu_report_filtered_features(cpu
);
3673 if (cpu
->enforce_cpuid
) {
3674 error_setg(&local_err
,
3675 accel_uses_host_cpuid() ?
3676 "Host doesn't support requested features" :
3677 "TCG doesn't support requested features");
3682 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3685 if (IS_AMD_CPU(env
)) {
3686 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
3687 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
3688 & CPUID_EXT2_AMD_ALIASES
);
3691 /* For 64bit systems think about the number of physical bits to present.
3692 * ideally this should be the same as the host; anything other than matching
3693 * the host can cause incorrect guest behaviour.
3694 * QEMU used to pick the magic value of 40 bits that corresponds to
3695 * consumer AMD devices but nothing else.
3697 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
3698 if (accel_uses_host_cpuid()) {
3699 uint32_t host_phys_bits
= x86_host_phys_bits();
3702 if (cpu
->host_phys_bits
) {
3703 /* The user asked for us to use the host physical bits */
3704 cpu
->phys_bits
= host_phys_bits
;
3707 /* Print a warning if the user set it to a value that's not the
3710 if (cpu
->phys_bits
!= host_phys_bits
&& cpu
->phys_bits
!= 0 &&
3712 warn_report("Host physical bits (%u)"
3713 " does not match phys-bits property (%u)",
3714 host_phys_bits
, cpu
->phys_bits
);
3718 if (cpu
->phys_bits
&&
3719 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
3720 cpu
->phys_bits
< 32)) {
3721 error_setg(errp
, "phys-bits should be between 32 and %u "
3723 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
3727 if (cpu
->phys_bits
&& cpu
->phys_bits
!= TCG_PHYS_ADDR_BITS
) {
3728 error_setg(errp
, "TCG only supports phys-bits=%u",
3729 TCG_PHYS_ADDR_BITS
);
3733 /* 0 means it was not explicitly set by the user (or by machine
3734 * compat_props or by the host code above). In this case, the default
3735 * is the value used by TCG (40).
3737 if (cpu
->phys_bits
== 0) {
3738 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
3741 /* For 32 bit systems don't use the user set value, but keep
3742 * phys_bits consistent with what we tell the guest.
3744 if (cpu
->phys_bits
!= 0) {
3745 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
3749 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
3750 cpu
->phys_bits
= 36;
3752 cpu
->phys_bits
= 32;
3755 cpu_exec_realizefn(cs
, &local_err
);
3756 if (local_err
!= NULL
) {
3757 error_propagate(errp
, local_err
);
3761 #ifndef CONFIG_USER_ONLY
3762 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
3764 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| smp_cpus
> 1) {
3765 x86_cpu_apic_create(cpu
, &local_err
);
3766 if (local_err
!= NULL
) {
3774 #ifndef CONFIG_USER_ONLY
3775 if (tcg_enabled()) {
3776 cpu
->cpu_as_mem
= g_new(MemoryRegion
, 1);
3777 cpu
->cpu_as_root
= g_new(MemoryRegion
, 1);
3779 /* Outer container... */
3780 memory_region_init(cpu
->cpu_as_root
, OBJECT(cpu
), "memory", ~0ull);
3781 memory_region_set_enabled(cpu
->cpu_as_root
, true);
3783 /* ... with two regions inside: normal system memory with low
3786 memory_region_init_alias(cpu
->cpu_as_mem
, OBJECT(cpu
), "memory",
3787 get_system_memory(), 0, ~0ull);
3788 memory_region_add_subregion_overlap(cpu
->cpu_as_root
, 0, cpu
->cpu_as_mem
, 0);
3789 memory_region_set_enabled(cpu
->cpu_as_mem
, true);
3792 cpu_address_space_init(cs
, 0, "cpu-memory", cs
->memory
);
3793 cpu_address_space_init(cs
, 1, "cpu-smm", cpu
->cpu_as_root
);
3795 /* ... SMRAM with higher priority, linked from /machine/smram. */
3796 cpu
->machine_done
.notify
= x86_cpu_machine_done
;
3797 qemu_add_machine_init_done_notifier(&cpu
->machine_done
);
3803 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3804 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3805 * based on inputs (sockets,cores,threads), it is still better to gives
3808 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3809 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3811 if (!IS_INTEL_CPU(env
) && cs
->nr_threads
> 1 && !ht_warned
) {
3812 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3813 " -smp options properly.");
3817 x86_cpu_apic_realize(cpu
, &local_err
);
3818 if (local_err
!= NULL
) {
3823 xcc
->parent_realize(dev
, &local_err
);
3826 if (local_err
!= NULL
) {
3827 error_propagate(errp
, local_err
);
3832 static void x86_cpu_unrealizefn(DeviceState
*dev
, Error
**errp
)
3834 X86CPU
*cpu
= X86_CPU(dev
);
3835 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
3836 Error
*local_err
= NULL
;
3838 #ifndef CONFIG_USER_ONLY
3839 cpu_remove_sync(CPU(dev
));
3840 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
3843 if (cpu
->apic_state
) {
3844 object_unparent(OBJECT(cpu
->apic_state
));
3845 cpu
->apic_state
= NULL
;
3848 xcc
->parent_unrealize(dev
, &local_err
);
3849 if (local_err
!= NULL
) {
3850 error_propagate(errp
, local_err
);
3855 typedef struct BitProperty
{
3860 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
3861 void *opaque
, Error
**errp
)
3863 X86CPU
*cpu
= X86_CPU(obj
);
3864 BitProperty
*fp
= opaque
;
3865 uint32_t f
= cpu
->env
.features
[fp
->w
];
3866 bool value
= (f
& fp
->mask
) == fp
->mask
;
3867 visit_type_bool(v
, name
, &value
, errp
);
3870 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
3871 void *opaque
, Error
**errp
)
3873 DeviceState
*dev
= DEVICE(obj
);
3874 X86CPU
*cpu
= X86_CPU(obj
);
3875 BitProperty
*fp
= opaque
;
3876 Error
*local_err
= NULL
;
3879 if (dev
->realized
) {
3880 qdev_prop_set_after_realize(dev
, name
, errp
);
3884 visit_type_bool(v
, name
, &value
, &local_err
);
3886 error_propagate(errp
, local_err
);
3891 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
3893 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
3895 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
3898 static void x86_cpu_release_bit_prop(Object
*obj
, const char *name
,
3901 BitProperty
*prop
= opaque
;
3905 /* Register a boolean property to get/set a single bit in a uint32_t field.
3907 * The same property name can be registered multiple times to make it affect
3908 * multiple bits in the same FeatureWord. In that case, the getter will return
3909 * true only if all bits are set.
3911 static void x86_cpu_register_bit_prop(X86CPU
*cpu
,
3912 const char *prop_name
,
3918 uint32_t mask
= (1UL << bitnr
);
3920 op
= object_property_find(OBJECT(cpu
), prop_name
, NULL
);
3926 fp
= g_new0(BitProperty
, 1);
3929 object_property_add(OBJECT(cpu
), prop_name
, "bool",
3930 x86_cpu_get_bit_prop
,
3931 x86_cpu_set_bit_prop
,
3932 x86_cpu_release_bit_prop
, fp
, &error_abort
);
3936 static void x86_cpu_register_feature_bit_props(X86CPU
*cpu
,
3940 FeatureWordInfo
*fi
= &feature_word_info
[w
];
3941 const char *name
= fi
->feat_names
[bitnr
];
3947 /* Property names should use "-" instead of "_".
3948 * Old names containing underscores are registered as aliases
3949 * using object_property_add_alias()
3951 assert(!strchr(name
, '_'));
3952 /* aliases don't use "|" delimiters anymore, they are registered
3953 * manually using object_property_add_alias() */
3954 assert(!strchr(name
, '|'));
3955 x86_cpu_register_bit_prop(cpu
, name
, w
, bitnr
);
3958 static GuestPanicInformation
*x86_cpu_get_crash_info(CPUState
*cs
)
3960 X86CPU
*cpu
= X86_CPU(cs
);
3961 CPUX86State
*env
= &cpu
->env
;
3962 GuestPanicInformation
*panic_info
= NULL
;
3964 if (env
->features
[FEAT_HYPERV_EDX
] & HV_GUEST_CRASH_MSR_AVAILABLE
) {
3965 panic_info
= g_malloc0(sizeof(GuestPanicInformation
));
3967 panic_info
->type
= GUEST_PANIC_INFORMATION_TYPE_HYPER_V
;
3969 assert(HV_CRASH_PARAMS
>= 5);
3970 panic_info
->u
.hyper_v
.arg1
= env
->msr_hv_crash_params
[0];
3971 panic_info
->u
.hyper_v
.arg2
= env
->msr_hv_crash_params
[1];
3972 panic_info
->u
.hyper_v
.arg3
= env
->msr_hv_crash_params
[2];
3973 panic_info
->u
.hyper_v
.arg4
= env
->msr_hv_crash_params
[3];
3974 panic_info
->u
.hyper_v
.arg5
= env
->msr_hv_crash_params
[4];
3979 static void x86_cpu_get_crash_info_qom(Object
*obj
, Visitor
*v
,
3980 const char *name
, void *opaque
,
3983 CPUState
*cs
= CPU(obj
);
3984 GuestPanicInformation
*panic_info
;
3986 if (!cs
->crash_occurred
) {
3987 error_setg(errp
, "No crash occured");
3991 panic_info
= x86_cpu_get_crash_info(cs
);
3992 if (panic_info
== NULL
) {
3993 error_setg(errp
, "No crash information");
3997 visit_type_GuestPanicInformation(v
, "crash-information", &panic_info
,
3999 qapi_free_GuestPanicInformation(panic_info
);
4002 static void x86_cpu_initfn(Object
*obj
)
4004 CPUState
*cs
= CPU(obj
);
4005 X86CPU
*cpu
= X86_CPU(obj
);
4006 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
4007 CPUX86State
*env
= &cpu
->env
;
4012 object_property_add(obj
, "family", "int",
4013 x86_cpuid_version_get_family
,
4014 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
4015 object_property_add(obj
, "model", "int",
4016 x86_cpuid_version_get_model
,
4017 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
4018 object_property_add(obj
, "stepping", "int",
4019 x86_cpuid_version_get_stepping
,
4020 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
4021 object_property_add_str(obj
, "vendor",
4022 x86_cpuid_get_vendor
,
4023 x86_cpuid_set_vendor
, NULL
);
4024 object_property_add_str(obj
, "model-id",
4025 x86_cpuid_get_model_id
,
4026 x86_cpuid_set_model_id
, NULL
);
4027 object_property_add(obj
, "tsc-frequency", "int",
4028 x86_cpuid_get_tsc_freq
,
4029 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
4030 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
4031 x86_cpu_get_feature_words
,
4032 NULL
, NULL
, (void *)env
->features
, NULL
);
4033 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
4034 x86_cpu_get_feature_words
,
4035 NULL
, NULL
, (void *)cpu
->filtered_features
, NULL
);
4037 object_property_add(obj
, "crash-information", "GuestPanicInformation",
4038 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
, NULL
);
4040 cpu
->hyperv_spinlock_attempts
= HYPERV_SPINLOCK_NEVER_RETRY
;
4042 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4045 for (bitnr
= 0; bitnr
< 32; bitnr
++) {
4046 x86_cpu_register_feature_bit_props(cpu
, w
, bitnr
);
4050 object_property_add_alias(obj
, "sse3", obj
, "pni", &error_abort
);
4051 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq", &error_abort
);
4052 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1", &error_abort
);
4053 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2", &error_abort
);
4054 object_property_add_alias(obj
, "xd", obj
, "nx", &error_abort
);
4055 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt", &error_abort
);
4056 object_property_add_alias(obj
, "i64", obj
, "lm", &error_abort
);
4058 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl", &error_abort
);
4059 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust", &error_abort
);
4060 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt", &error_abort
);
4061 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm", &error_abort
);
4062 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy", &error_abort
);
4063 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr", &error_abort
);
4064 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core", &error_abort
);
4065 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb", &error_abort
);
4066 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay", &error_abort
);
4067 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu", &error_abort
);
4068 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf", &error_abort
);
4069 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time", &error_abort
);
4070 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi", &error_abort
);
4071 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt", &error_abort
);
4072 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock", &error_abort
);
4073 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save", &error_abort
);
4074 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale", &error_abort
);
4075 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean", &error_abort
);
4076 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter", &error_abort
);
4077 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1", &error_abort
);
4078 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2", &error_abort
);
4081 x86_cpu_load_def(cpu
, xcc
->cpu_def
, &error_abort
);
4085 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
4087 X86CPU
*cpu
= X86_CPU(cs
);
4089 return cpu
->apic_id
;
4092 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
4094 X86CPU
*cpu
= X86_CPU(cs
);
4096 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
4099 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
4101 X86CPU
*cpu
= X86_CPU(cs
);
4103 cpu
->env
.eip
= value
;
4106 static void x86_cpu_synchronize_from_tb(CPUState
*cs
, TranslationBlock
*tb
)
4108 X86CPU
*cpu
= X86_CPU(cs
);
4110 cpu
->env
.eip
= tb
->pc
- tb
->cs_base
;
4113 static bool x86_cpu_has_work(CPUState
*cs
)
4115 X86CPU
*cpu
= X86_CPU(cs
);
4116 CPUX86State
*env
= &cpu
->env
;
4118 return ((cs
->interrupt_request
& (CPU_INTERRUPT_HARD
|
4119 CPU_INTERRUPT_POLL
)) &&
4120 (env
->eflags
& IF_MASK
)) ||
4121 (cs
->interrupt_request
& (CPU_INTERRUPT_NMI
|
4122 CPU_INTERRUPT_INIT
|
4123 CPU_INTERRUPT_SIPI
|
4124 CPU_INTERRUPT_MCE
)) ||
4125 ((cs
->interrupt_request
& CPU_INTERRUPT_SMI
) &&
4126 !(env
->hflags
& HF_SMM_MASK
));
4129 static void x86_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
4131 X86CPU
*cpu
= X86_CPU(cs
);
4132 CPUX86State
*env
= &cpu
->env
;
4134 info
->mach
= (env
->hflags
& HF_CS64_MASK
? bfd_mach_x86_64
4135 : env
->hflags
& HF_CS32_MASK
? bfd_mach_i386_i386
4136 : bfd_mach_i386_i8086
);
4137 info
->print_insn
= print_insn_i386
;
4139 info
->cap_arch
= CS_ARCH_X86
;
4140 info
->cap_mode
= (env
->hflags
& HF_CS64_MASK
? CS_MODE_64
4141 : env
->hflags
& HF_CS32_MASK
? CS_MODE_32
4143 info
->cap_insn_unit
= 1;
4144 info
->cap_insn_split
= 8;
4147 static Property x86_cpu_properties
[] = {
4148 #ifdef CONFIG_USER_ONLY
4149 /* apic_id = 0 by default for *-user, see commit 9886e834 */
4150 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
4151 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
4152 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
4153 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
4155 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
4156 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
4157 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
4158 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
4160 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
4161 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
4162 { .name
= "hv-spinlocks", .info
= &qdev_prop_spinlocks
},
4163 DEFINE_PROP_BOOL("hv-relaxed", X86CPU
, hyperv_relaxed_timing
, false),
4164 DEFINE_PROP_BOOL("hv-vapic", X86CPU
, hyperv_vapic
, false),
4165 DEFINE_PROP_BOOL("hv-time", X86CPU
, hyperv_time
, false),
4166 DEFINE_PROP_BOOL("hv-crash", X86CPU
, hyperv_crash
, false),
4167 DEFINE_PROP_BOOL("hv-reset", X86CPU
, hyperv_reset
, false),
4168 DEFINE_PROP_BOOL("hv-vpindex", X86CPU
, hyperv_vpindex
, false),
4169 DEFINE_PROP_BOOL("hv-runtime", X86CPU
, hyperv_runtime
, false),
4170 DEFINE_PROP_BOOL("hv-synic", X86CPU
, hyperv_synic
, false),
4171 DEFINE_PROP_BOOL("hv-stimer", X86CPU
, hyperv_stimer
, false),
4172 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
4173 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
4174 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
4175 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
4176 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
4177 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
4178 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
4179 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
4180 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
4181 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
4182 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
4183 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
4184 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
4185 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor_id
),
4186 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
4187 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
4188 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
4189 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
4191 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
4192 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
4195 * From "Requirements for Implementing the Microsoft
4196 * Hypervisor Interface":
4197 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
4199 * "Starting with Windows Server 2012 and Windows 8, if
4200 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
4201 * the hypervisor imposes no specific limit to the number of VPs.
4202 * In this case, Windows Server 2012 guest VMs may use more than
4203 * 64 VPs, up to the maximum supported number of processors applicable
4204 * to the specific Windows version being used."
4206 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
4207 DEFINE_PROP_END_OF_LIST()
4210 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
4212 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4213 CPUClass
*cc
= CPU_CLASS(oc
);
4214 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4216 xcc
->parent_realize
= dc
->realize
;
4217 xcc
->parent_unrealize
= dc
->unrealize
;
4218 dc
->realize
= x86_cpu_realizefn
;
4219 dc
->unrealize
= x86_cpu_unrealizefn
;
4220 dc
->props
= x86_cpu_properties
;
4222 xcc
->parent_reset
= cc
->reset
;
4223 cc
->reset
= x86_cpu_reset
;
4224 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
4226 cc
->class_by_name
= x86_cpu_class_by_name
;
4227 cc
->parse_features
= x86_cpu_parse_featurestr
;
4228 cc
->has_work
= x86_cpu_has_work
;
4230 cc
->do_interrupt
= x86_cpu_do_interrupt
;
4231 cc
->cpu_exec_interrupt
= x86_cpu_exec_interrupt
;
4233 cc
->dump_state
= x86_cpu_dump_state
;
4234 cc
->get_crash_info
= x86_cpu_get_crash_info
;
4235 cc
->set_pc
= x86_cpu_set_pc
;
4236 cc
->synchronize_from_tb
= x86_cpu_synchronize_from_tb
;
4237 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
4238 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
4239 cc
->get_arch_id
= x86_cpu_get_arch_id
;
4240 cc
->get_paging_enabled
= x86_cpu_get_paging_enabled
;
4241 #ifdef CONFIG_USER_ONLY
4242 cc
->handle_mmu_fault
= x86_cpu_handle_mmu_fault
;
4244 cc
->asidx_from_attrs
= x86_asidx_from_attrs
;
4245 cc
->get_memory_mapping
= x86_cpu_get_memory_mapping
;
4246 cc
->get_phys_page_debug
= x86_cpu_get_phys_page_debug
;
4247 cc
->write_elf64_note
= x86_cpu_write_elf64_note
;
4248 cc
->write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
;
4249 cc
->write_elf32_note
= x86_cpu_write_elf32_note
;
4250 cc
->write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
;
4251 cc
->vmsd
= &vmstate_x86_cpu
;
4253 cc
->gdb_arch_name
= x86_gdb_arch_name
;
4254 #ifdef TARGET_X86_64
4255 cc
->gdb_core_xml_file
= "i386-64bit.xml";
4256 cc
->gdb_num_core_regs
= 57;
4258 cc
->gdb_core_xml_file
= "i386-32bit.xml";
4259 cc
->gdb_num_core_regs
= 41;
4261 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
4262 cc
->debug_excp_handler
= breakpoint_handler
;
4264 cc
->cpu_exec_enter
= x86_cpu_exec_enter
;
4265 cc
->cpu_exec_exit
= x86_cpu_exec_exit
;
4267 cc
->tcg_initialize
= tcg_x86_init
;
4269 cc
->disas_set_info
= x86_disas_set_info
;
4271 dc
->user_creatable
= true;
4274 static const TypeInfo x86_cpu_type_info
= {
4275 .name
= TYPE_X86_CPU
,
4277 .instance_size
= sizeof(X86CPU
),
4278 .instance_init
= x86_cpu_initfn
,
4280 .class_size
= sizeof(X86CPUClass
),
4281 .class_init
= x86_cpu_common_class_init
,
4285 /* "base" CPU model, used by query-cpu-model-expansion */
4286 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
4288 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4290 xcc
->static_model
= true;
4291 xcc
->migration_safe
= true;
4292 xcc
->model_description
= "base CPU model type with no features enabled";
4296 static const TypeInfo x86_base_cpu_type_info
= {
4297 .name
= X86_CPU_TYPE_NAME("base"),
4298 .parent
= TYPE_X86_CPU
,
4299 .class_init
= x86_cpu_base_class_init
,
4302 static void x86_cpu_register_types(void)
4306 type_register_static(&x86_cpu_type_info
);
4307 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
4308 x86_register_cpudef_type(&builtin_x86_defs
[i
]);
4310 type_register_static(&max_x86_cpu_type_info
);
4311 type_register_static(&x86_base_cpu_type_info
);
4312 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4313 type_register_static(&host_x86_cpu_type_info
);
4317 type_init(x86_cpu_register_types
)