2 * i386 CPUID, CPU class, definitions, models
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/qemu-print.h"
24 #include "qemu/hw-version.h"
26 #include "tcg/helper-tcg.h"
27 #include "sysemu/reset.h"
28 #include "sysemu/hvf.h"
29 #include "kvm/kvm_i386.h"
31 #include "qapi/error.h"
32 #include "qemu/error-report.h"
33 #include "qapi/qapi-visit-machine.h"
34 #include "qapi/qmp/qerror.h"
35 #include "standard-headers/asm-x86/kvm_para.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/i386/topology.h"
38 #ifndef CONFIG_USER_ONLY
39 #include "qapi/qapi-commands-machine-target.h"
40 #include "exec/address-spaces.h"
41 #include "hw/boards.h"
42 #include "hw/i386/sgx-epc.h"
45 #include "disas/capstone.h"
46 #include "cpu-internal.h"
48 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
);
50 /* Helpers for building CPUID[2] descriptors: */
52 struct CPUID2CacheDescriptorInfo
{
61 * Known CPUID 2 cache descriptors.
62 * From Intel SDM Volume 2A, CPUID instruction
64 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors
[] = {
65 [0x06] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 8 * KiB
,
66 .associativity
= 4, .line_size
= 32, },
67 [0x08] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 16 * KiB
,
68 .associativity
= 4, .line_size
= 32, },
69 [0x09] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
70 .associativity
= 4, .line_size
= 64, },
71 [0x0A] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
72 .associativity
= 2, .line_size
= 32, },
73 [0x0C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
74 .associativity
= 4, .line_size
= 32, },
75 [0x0D] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
76 .associativity
= 4, .line_size
= 64, },
77 [0x0E] = { .level
= 1, .type
= DATA_CACHE
, .size
= 24 * KiB
,
78 .associativity
= 6, .line_size
= 64, },
79 [0x1D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
80 .associativity
= 2, .line_size
= 64, },
81 [0x21] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
82 .associativity
= 8, .line_size
= 64, },
83 /* lines per sector is not supported cpuid2_cache_descriptor(),
84 * so descriptors 0x22, 0x23 are not included
86 [0x24] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
87 .associativity
= 16, .line_size
= 64, },
88 /* lines per sector is not supported cpuid2_cache_descriptor(),
89 * so descriptors 0x25, 0x20 are not included
91 [0x2C] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
92 .associativity
= 8, .line_size
= 64, },
93 [0x30] = { .level
= 1, .type
= INSTRUCTION_CACHE
, .size
= 32 * KiB
,
94 .associativity
= 8, .line_size
= 64, },
95 [0x41] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 128 * KiB
,
96 .associativity
= 4, .line_size
= 32, },
97 [0x42] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
98 .associativity
= 4, .line_size
= 32, },
99 [0x43] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
100 .associativity
= 4, .line_size
= 32, },
101 [0x44] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
102 .associativity
= 4, .line_size
= 32, },
103 [0x45] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
104 .associativity
= 4, .line_size
= 32, },
105 [0x46] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
106 .associativity
= 4, .line_size
= 64, },
107 [0x47] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
108 .associativity
= 8, .line_size
= 64, },
109 [0x48] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
110 .associativity
= 12, .line_size
= 64, },
111 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
112 [0x4A] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
113 .associativity
= 12, .line_size
= 64, },
114 [0x4B] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
115 .associativity
= 16, .line_size
= 64, },
116 [0x4C] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
117 .associativity
= 12, .line_size
= 64, },
118 [0x4D] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 16 * MiB
,
119 .associativity
= 16, .line_size
= 64, },
120 [0x4E] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
121 .associativity
= 24, .line_size
= 64, },
122 [0x60] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
123 .associativity
= 8, .line_size
= 64, },
124 [0x66] = { .level
= 1, .type
= DATA_CACHE
, .size
= 8 * KiB
,
125 .associativity
= 4, .line_size
= 64, },
126 [0x67] = { .level
= 1, .type
= DATA_CACHE
, .size
= 16 * KiB
,
127 .associativity
= 4, .line_size
= 64, },
128 [0x68] = { .level
= 1, .type
= DATA_CACHE
, .size
= 32 * KiB
,
129 .associativity
= 4, .line_size
= 64, },
130 [0x78] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
131 .associativity
= 4, .line_size
= 64, },
132 /* lines per sector is not supported cpuid2_cache_descriptor(),
133 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
135 [0x7D] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
136 .associativity
= 8, .line_size
= 64, },
137 [0x7F] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
138 .associativity
= 2, .line_size
= 64, },
139 [0x80] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
140 .associativity
= 8, .line_size
= 64, },
141 [0x82] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 256 * KiB
,
142 .associativity
= 8, .line_size
= 32, },
143 [0x83] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
144 .associativity
= 8, .line_size
= 32, },
145 [0x84] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
146 .associativity
= 8, .line_size
= 32, },
147 [0x85] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
148 .associativity
= 8, .line_size
= 32, },
149 [0x86] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
150 .associativity
= 4, .line_size
= 64, },
151 [0x87] = { .level
= 2, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
152 .associativity
= 8, .line_size
= 64, },
153 [0xD0] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 512 * KiB
,
154 .associativity
= 4, .line_size
= 64, },
155 [0xD1] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
156 .associativity
= 4, .line_size
= 64, },
157 [0xD2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
158 .associativity
= 4, .line_size
= 64, },
159 [0xD6] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1 * MiB
,
160 .associativity
= 8, .line_size
= 64, },
161 [0xD7] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
162 .associativity
= 8, .line_size
= 64, },
163 [0xD8] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
164 .associativity
= 8, .line_size
= 64, },
165 [0xDC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 1.5 * MiB
,
166 .associativity
= 12, .line_size
= 64, },
167 [0xDD] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 3 * MiB
,
168 .associativity
= 12, .line_size
= 64, },
169 [0xDE] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 6 * MiB
,
170 .associativity
= 12, .line_size
= 64, },
171 [0xE2] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 2 * MiB
,
172 .associativity
= 16, .line_size
= 64, },
173 [0xE3] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 4 * MiB
,
174 .associativity
= 16, .line_size
= 64, },
175 [0xE4] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 8 * MiB
,
176 .associativity
= 16, .line_size
= 64, },
177 [0xEA] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 12 * MiB
,
178 .associativity
= 24, .line_size
= 64, },
179 [0xEB] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 18 * MiB
,
180 .associativity
= 24, .line_size
= 64, },
181 [0xEC] = { .level
= 3, .type
= UNIFIED_CACHE
, .size
= 24 * MiB
,
182 .associativity
= 24, .line_size
= 64, },
186 * "CPUID leaf 2 does not report cache descriptor information,
187 * use CPUID leaf 4 to query cache parameters"
189 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
192 * Return a CPUID 2 cache descriptor for a given cache.
193 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
195 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo
*cache
)
199 assert(cache
->size
> 0);
200 assert(cache
->level
> 0);
201 assert(cache
->line_size
> 0);
202 assert(cache
->associativity
> 0);
203 for (i
= 0; i
< ARRAY_SIZE(cpuid2_cache_descriptors
); i
++) {
204 struct CPUID2CacheDescriptorInfo
*d
= &cpuid2_cache_descriptors
[i
];
205 if (d
->level
== cache
->level
&& d
->type
== cache
->type
&&
206 d
->size
== cache
->size
&& d
->line_size
== cache
->line_size
&&
207 d
->associativity
== cache
->associativity
) {
212 return CACHE_DESCRIPTOR_UNAVAILABLE
;
215 /* CPUID Leaf 4 constants: */
218 #define CACHE_TYPE_D 1
219 #define CACHE_TYPE_I 2
220 #define CACHE_TYPE_UNIFIED 3
222 #define CACHE_LEVEL(l) (l << 5)
224 #define CACHE_SELF_INIT_LEVEL (1 << 8)
227 #define CACHE_NO_INVD_SHARING (1 << 0)
228 #define CACHE_INCLUSIVE (1 << 1)
229 #define CACHE_COMPLEX_IDX (1 << 2)
231 /* Encode CacheType for CPUID[4].EAX */
232 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
233 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
234 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
235 0 /* Invalid value */)
238 /* Encode cache info for CPUID[4] */
239 static void encode_cache_cpuid4(CPUCacheInfo
*cache
,
240 int num_apic_ids
, int num_cores
,
241 uint32_t *eax
, uint32_t *ebx
,
242 uint32_t *ecx
, uint32_t *edx
)
244 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
245 cache
->partitions
* cache
->sets
);
247 assert(num_apic_ids
> 0);
248 *eax
= CACHE_TYPE(cache
->type
) |
249 CACHE_LEVEL(cache
->level
) |
250 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0) |
251 ((num_cores
- 1) << 26) |
252 ((num_apic_ids
- 1) << 14);
254 assert(cache
->line_size
> 0);
255 assert(cache
->partitions
> 0);
256 assert(cache
->associativity
> 0);
257 /* We don't implement fully-associative caches */
258 assert(cache
->associativity
< cache
->sets
);
259 *ebx
= (cache
->line_size
- 1) |
260 ((cache
->partitions
- 1) << 12) |
261 ((cache
->associativity
- 1) << 22);
263 assert(cache
->sets
> 0);
264 *ecx
= cache
->sets
- 1;
266 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
267 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
268 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
271 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
272 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo
*cache
)
274 assert(cache
->size
% 1024 == 0);
275 assert(cache
->lines_per_tag
> 0);
276 assert(cache
->associativity
> 0);
277 assert(cache
->line_size
> 0);
278 return ((cache
->size
/ 1024) << 24) | (cache
->associativity
<< 16) |
279 (cache
->lines_per_tag
<< 8) | (cache
->line_size
);
282 #define ASSOC_FULL 0xFF
284 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
285 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
295 a == ASSOC_FULL ? 0xF : \
296 0 /* invalid value */)
299 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
302 static void encode_cache_cpuid80000006(CPUCacheInfo
*l2
,
304 uint32_t *ecx
, uint32_t *edx
)
306 assert(l2
->size
% 1024 == 0);
307 assert(l2
->associativity
> 0);
308 assert(l2
->lines_per_tag
> 0);
309 assert(l2
->line_size
> 0);
310 *ecx
= ((l2
->size
/ 1024) << 16) |
311 (AMD_ENC_ASSOC(l2
->associativity
) << 12) |
312 (l2
->lines_per_tag
<< 8) | (l2
->line_size
);
315 assert(l3
->size
% (512 * 1024) == 0);
316 assert(l3
->associativity
> 0);
317 assert(l3
->lines_per_tag
> 0);
318 assert(l3
->line_size
> 0);
319 *edx
= ((l3
->size
/ (512 * 1024)) << 18) |
320 (AMD_ENC_ASSOC(l3
->associativity
) << 12) |
321 (l3
->lines_per_tag
<< 8) | (l3
->line_size
);
327 /* Encode cache info for CPUID[8000001D] */
328 static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache
,
329 X86CPUTopoInfo
*topo_info
,
330 uint32_t *eax
, uint32_t *ebx
,
331 uint32_t *ecx
, uint32_t *edx
)
334 assert(cache
->size
== cache
->line_size
* cache
->associativity
*
335 cache
->partitions
* cache
->sets
);
337 *eax
= CACHE_TYPE(cache
->type
) | CACHE_LEVEL(cache
->level
) |
338 (cache
->self_init
? CACHE_SELF_INIT_LEVEL
: 0);
340 /* L3 is shared among multiple cores */
341 if (cache
->level
== 3) {
342 l3_threads
= topo_info
->cores_per_die
* topo_info
->threads_per_core
;
343 *eax
|= (l3_threads
- 1) << 14;
345 *eax
|= ((topo_info
->threads_per_core
- 1) << 14);
348 assert(cache
->line_size
> 0);
349 assert(cache
->partitions
> 0);
350 assert(cache
->associativity
> 0);
351 /* We don't implement fully-associative caches */
352 assert(cache
->associativity
< cache
->sets
);
353 *ebx
= (cache
->line_size
- 1) |
354 ((cache
->partitions
- 1) << 12) |
355 ((cache
->associativity
- 1) << 22);
357 assert(cache
->sets
> 0);
358 *ecx
= cache
->sets
- 1;
360 *edx
= (cache
->no_invd_sharing
? CACHE_NO_INVD_SHARING
: 0) |
361 (cache
->inclusive
? CACHE_INCLUSIVE
: 0) |
362 (cache
->complex_indexing
? CACHE_COMPLEX_IDX
: 0);
365 /* Encode cache info for CPUID[8000001E] */
366 static void encode_topo_cpuid8000001e(X86CPU
*cpu
, X86CPUTopoInfo
*topo_info
,
367 uint32_t *eax
, uint32_t *ebx
,
368 uint32_t *ecx
, uint32_t *edx
)
370 X86CPUTopoIDs topo_ids
;
372 x86_topo_ids_from_apicid(cpu
->apic_id
, topo_info
, &topo_ids
);
377 * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
378 * Read-only. Reset: 0000_XXXXh.
379 * See Core::X86::Cpuid::ExtApicId.
380 * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
383 * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
384 * The number of threads per core is ThreadsPerCore+1.
385 * 7:0 CoreId: core ID. Read-only. Reset: XXh.
387 * NOTE: CoreId is already part of apic_id. Just use it. We can
388 * use all the 8 bits to represent the core_id here.
390 *ebx
= ((topo_info
->threads_per_core
- 1) << 8) | (topo_ids
.core_id
& 0xFF);
393 * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
394 * Read-only. Reset: 0000_0XXXh.
395 * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
398 * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
401 * 000b 1 node per processor.
402 * 001b 2 nodes per processor.
404 * 011b 4 nodes per processor.
405 * 111b-100b Reserved.
406 * 7:0 NodeId: Node ID. Read-only. Reset: XXh.
408 * NOTE: Hardware reserves 3 bits for number of nodes per processor.
409 * But users can create more nodes than the actual hardware can
410 * support. To genaralize we can use all the upper 8 bits for nodes.
411 * NodeId is combination of node and socket_id which is already decoded
412 * in apic_id. Just use it by shifting.
414 *ecx
= ((topo_info
->dies_per_pkg
- 1) << 8) |
415 ((cpu
->apic_id
>> apicid_die_offset(topo_info
)) & 0xFF);
421 * Definitions of the hardcoded cache entries we expose:
422 * These are legacy cache values. If there is a need to change any
423 * of these values please use builtin_x86_defs
427 static CPUCacheInfo legacy_l1d_cache
= {
436 .no_invd_sharing
= true,
439 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
440 static CPUCacheInfo legacy_l1d_cache_amd
= {
450 .no_invd_sharing
= true,
453 /* L1 instruction cache: */
454 static CPUCacheInfo legacy_l1i_cache
= {
455 .type
= INSTRUCTION_CACHE
,
463 .no_invd_sharing
= true,
466 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
467 static CPUCacheInfo legacy_l1i_cache_amd
= {
468 .type
= INSTRUCTION_CACHE
,
477 .no_invd_sharing
= true,
480 /* Level 2 unified cache: */
481 static CPUCacheInfo legacy_l2_cache
= {
482 .type
= UNIFIED_CACHE
,
490 .no_invd_sharing
= true,
493 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
494 static CPUCacheInfo legacy_l2_cache_cpuid2
= {
495 .type
= UNIFIED_CACHE
,
503 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
504 static CPUCacheInfo legacy_l2_cache_amd
= {
505 .type
= UNIFIED_CACHE
,
515 /* Level 3 unified cache: */
516 static CPUCacheInfo legacy_l3_cache
= {
517 .type
= UNIFIED_CACHE
,
527 .complex_indexing
= true,
530 /* TLB definitions: */
532 #define L1_DTLB_2M_ASSOC 1
533 #define L1_DTLB_2M_ENTRIES 255
534 #define L1_DTLB_4K_ASSOC 1
535 #define L1_DTLB_4K_ENTRIES 255
537 #define L1_ITLB_2M_ASSOC 1
538 #define L1_ITLB_2M_ENTRIES 255
539 #define L1_ITLB_4K_ASSOC 1
540 #define L1_ITLB_4K_ENTRIES 255
542 #define L2_DTLB_2M_ASSOC 0 /* disabled */
543 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
544 #define L2_DTLB_4K_ASSOC 4
545 #define L2_DTLB_4K_ENTRIES 512
547 #define L2_ITLB_2M_ASSOC 0 /* disabled */
548 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
549 #define L2_ITLB_4K_ASSOC 4
550 #define L2_ITLB_4K_ENTRIES 512
552 /* CPUID Leaf 0x14 constants: */
553 #define INTEL_PT_MAX_SUBLEAF 0x1
555 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
556 * MSR can be accessed;
557 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
558 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
559 * of Intel PT MSRs across warm reset;
560 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
562 #define INTEL_PT_MINIMAL_EBX 0xf
564 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
565 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
567 * bit[01]: ToPA tables can hold any number of output entries, up to the
568 * maximum allowed by the MaskOrTableOffset field of
569 * IA32_RTIT_OUTPUT_MASK_PTRS;
570 * bit[02]: Support Single-Range Output scheme;
572 #define INTEL_PT_MINIMAL_ECX 0x7
573 /* generated packets which contain IP payloads have LIP values */
574 #define INTEL_PT_IP_LIP (1 << 31)
575 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
576 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
577 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
578 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
579 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
581 /* CPUID Leaf 0x1D constants: */
582 #define INTEL_AMX_TILE_MAX_SUBLEAF 0x1
583 #define INTEL_AMX_TOTAL_TILE_BYTES 0x2000
584 #define INTEL_AMX_BYTES_PER_TILE 0x400
585 #define INTEL_AMX_BYTES_PER_ROW 0x40
586 #define INTEL_AMX_TILE_MAX_NAMES 0x8
587 #define INTEL_AMX_TILE_MAX_ROWS 0x10
589 /* CPUID Leaf 0x1E constants: */
590 #define INTEL_AMX_TMUL_MAX_K 0x10
591 #define INTEL_AMX_TMUL_MAX_N 0x40
593 void x86_cpu_vendor_words2str(char *dst
, uint32_t vendor1
,
594 uint32_t vendor2
, uint32_t vendor3
)
597 for (i
= 0; i
< 4; i
++) {
598 dst
[i
] = vendor1
>> (8 * i
);
599 dst
[i
+ 4] = vendor2
>> (8 * i
);
600 dst
[i
+ 8] = vendor3
>> (8 * i
);
602 dst
[CPUID_VENDOR_SZ
] = '\0';
605 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
606 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
607 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
608 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
609 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
610 CPUID_PSE36 | CPUID_FXSR)
611 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
612 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
613 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
614 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
615 CPUID_PAE | CPUID_SEP | CPUID_APIC)
617 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
618 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
619 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
620 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
621 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
622 /* partly implemented:
623 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
625 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
626 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
627 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
628 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
629 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
630 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
631 CPUID_EXT_RDRAND | CPUID_EXT_AVX | CPUID_EXT_F16C | \
634 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
635 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID,
636 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
637 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER */
640 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
642 #define TCG_EXT2_X86_64_FEATURES 0
645 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
646 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
647 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
648 TCG_EXT2_X86_64_FEATURES)
649 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
650 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
651 #define TCG_EXT4_FEATURES 0
652 #define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \
653 CPUID_SVM_SVME_ADDR_CHK)
654 #define TCG_KVM_FEATURES 0
655 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
656 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
657 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
658 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
659 CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2)
662 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
663 CPUID_7_0_EBX_RDSEED */
664 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU | \
665 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
666 CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS | CPUID_7_0_ECX_VAES)
667 #define TCG_7_0_EDX_FEATURES CPUID_7_0_EDX_FSRM
668 #define TCG_7_1_EAX_FEATURES (CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | \
670 #define TCG_7_1_EDX_FEATURES 0
671 #define TCG_APM_FEATURES 0
672 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
673 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
675 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
676 #define TCG_14_0_ECX_FEATURES 0
677 #define TCG_SGX_12_0_EAX_FEATURES 0
678 #define TCG_SGX_12_0_EBX_FEATURES 0
679 #define TCG_SGX_12_1_EAX_FEATURES 0
681 FeatureWordInfo feature_word_info
[FEATURE_WORDS
] = {
683 .type
= CPUID_FEATURE_WORD
,
685 "fpu", "vme", "de", "pse",
686 "tsc", "msr", "pae", "mce",
687 "cx8", "apic", NULL
, "sep",
688 "mtrr", "pge", "mca", "cmov",
689 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
690 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
691 "fxsr", "sse", "sse2", "ss",
692 "ht" /* Intel htt */, "tm", "ia64", "pbe",
694 .cpuid
= {.eax
= 1, .reg
= R_EDX
, },
695 .tcg_features
= TCG_FEATURES
,
698 .type
= CPUID_FEATURE_WORD
,
700 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
701 "ds-cpl", "vmx", "smx", "est",
702 "tm2", "ssse3", "cid", NULL
,
703 "fma", "cx16", "xtpr", "pdcm",
704 NULL
, "pcid", "dca", "sse4.1",
705 "sse4.2", "x2apic", "movbe", "popcnt",
706 "tsc-deadline", "aes", "xsave", NULL
/* osxsave */,
707 "avx", "f16c", "rdrand", "hypervisor",
709 .cpuid
= { .eax
= 1, .reg
= R_ECX
, },
710 .tcg_features
= TCG_EXT_FEATURES
,
712 /* Feature names that are already defined on feature_name[] but
713 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
714 * names on feat_names below. They are copied automatically
715 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
717 [FEAT_8000_0001_EDX
] = {
718 .type
= CPUID_FEATURE_WORD
,
720 NULL
/* fpu */, NULL
/* vme */, NULL
/* de */, NULL
/* pse */,
721 NULL
/* tsc */, NULL
/* msr */, NULL
/* pae */, NULL
/* mce */,
722 NULL
/* cx8 */, NULL
/* apic */, NULL
, "syscall",
723 NULL
/* mtrr */, NULL
/* pge */, NULL
/* mca */, NULL
/* cmov */,
724 NULL
/* pat */, NULL
/* pse36 */, NULL
, NULL
/* Linux mp */,
725 "nx", NULL
, "mmxext", NULL
/* mmx */,
726 NULL
/* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
727 NULL
, "lm", "3dnowext", "3dnow",
729 .cpuid
= { .eax
= 0x80000001, .reg
= R_EDX
, },
730 .tcg_features
= TCG_EXT2_FEATURES
,
732 [FEAT_8000_0001_ECX
] = {
733 .type
= CPUID_FEATURE_WORD
,
735 "lahf-lm", "cmp-legacy", "svm", "extapic",
736 "cr8legacy", "abm", "sse4a", "misalignsse",
737 "3dnowprefetch", "osvw", "ibs", "xop",
738 "skinit", "wdt", NULL
, "lwp",
739 "fma4", "tce", NULL
, "nodeid-msr",
740 NULL
, "tbm", "topoext", "perfctr-core",
741 "perfctr-nb", NULL
, NULL
, NULL
,
742 NULL
, NULL
, NULL
, NULL
,
744 .cpuid
= { .eax
= 0x80000001, .reg
= R_ECX
, },
745 .tcg_features
= TCG_EXT3_FEATURES
,
747 * TOPOEXT is always allowed but can't be enabled blindly by
748 * "-cpu host", as it requires consistent cache topology info
749 * to be provided so it doesn't confuse guests.
751 .no_autoenable_flags
= CPUID_EXT3_TOPOEXT
,
753 [FEAT_C000_0001_EDX
] = {
754 .type
= CPUID_FEATURE_WORD
,
756 NULL
, NULL
, "xstore", "xstore-en",
757 NULL
, NULL
, "xcrypt", "xcrypt-en",
758 "ace2", "ace2-en", "phe", "phe-en",
759 "pmm", "pmm-en", NULL
, NULL
,
760 NULL
, NULL
, NULL
, NULL
,
761 NULL
, NULL
, NULL
, NULL
,
762 NULL
, NULL
, NULL
, NULL
,
763 NULL
, NULL
, NULL
, NULL
,
765 .cpuid
= { .eax
= 0xC0000001, .reg
= R_EDX
, },
766 .tcg_features
= TCG_EXT4_FEATURES
,
769 .type
= CPUID_FEATURE_WORD
,
771 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
772 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
773 NULL
, "kvm-pv-tlb-flush", NULL
, "kvm-pv-ipi",
774 "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
775 NULL
, NULL
, NULL
, NULL
,
776 NULL
, NULL
, NULL
, NULL
,
777 "kvmclock-stable-bit", NULL
, NULL
, NULL
,
778 NULL
, NULL
, NULL
, NULL
,
780 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EAX
, },
781 .tcg_features
= TCG_KVM_FEATURES
,
784 .type
= CPUID_FEATURE_WORD
,
786 "kvm-hint-dedicated", NULL
, NULL
, NULL
,
787 NULL
, NULL
, NULL
, NULL
,
788 NULL
, NULL
, NULL
, NULL
,
789 NULL
, NULL
, NULL
, NULL
,
790 NULL
, NULL
, NULL
, NULL
,
791 NULL
, NULL
, NULL
, NULL
,
792 NULL
, NULL
, NULL
, NULL
,
793 NULL
, NULL
, NULL
, NULL
,
795 .cpuid
= { .eax
= KVM_CPUID_FEATURES
, .reg
= R_EDX
, },
796 .tcg_features
= TCG_KVM_FEATURES
,
798 * KVM hints aren't auto-enabled by -cpu host, they need to be
799 * explicitly enabled in the command-line.
801 .no_autoenable_flags
= ~0U,
804 .type
= CPUID_FEATURE_WORD
,
806 "npt", "lbrv", "svm-lock", "nrip-save",
807 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
808 NULL
, NULL
, "pause-filter", NULL
,
809 "pfthreshold", "avic", NULL
, "v-vmsave-vmload",
810 "vgif", NULL
, NULL
, NULL
,
811 NULL
, NULL
, NULL
, NULL
,
812 NULL
, "vnmi", NULL
, NULL
,
813 "svme-addr-chk", NULL
, NULL
, NULL
,
815 .cpuid
= { .eax
= 0x8000000A, .reg
= R_EDX
, },
816 .tcg_features
= TCG_SVM_FEATURES
,
819 .type
= CPUID_FEATURE_WORD
,
821 "fsgsbase", "tsc-adjust", "sgx", "bmi1",
822 "hle", "avx2", NULL
, "smep",
823 "bmi2", "erms", "invpcid", "rtm",
824 NULL
, NULL
, "mpx", NULL
,
825 "avx512f", "avx512dq", "rdseed", "adx",
826 "smap", "avx512ifma", "pcommit", "clflushopt",
827 "clwb", "intel-pt", "avx512pf", "avx512er",
828 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
832 .needs_ecx
= true, .ecx
= 0,
835 .tcg_features
= TCG_7_0_EBX_FEATURES
,
838 .type
= CPUID_FEATURE_WORD
,
840 NULL
, "avx512vbmi", "umip", "pku",
841 NULL
/* ospke */, "waitpkg", "avx512vbmi2", NULL
,
842 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
843 "avx512bitalg", NULL
, "avx512-vpopcntdq", NULL
,
844 "la57", NULL
, NULL
, NULL
,
845 NULL
, NULL
, "rdpid", NULL
,
846 "bus-lock-detect", "cldemote", NULL
, "movdiri",
847 "movdir64b", NULL
, "sgxlc", "pks",
851 .needs_ecx
= true, .ecx
= 0,
854 .tcg_features
= TCG_7_0_ECX_FEATURES
,
857 .type
= CPUID_FEATURE_WORD
,
859 NULL
, NULL
, "avx512-4vnniw", "avx512-4fmaps",
860 "fsrm", NULL
, NULL
, NULL
,
861 "avx512-vp2intersect", NULL
, "md-clear", NULL
,
862 NULL
, NULL
, "serialize", NULL
,
863 "tsx-ldtrk", NULL
, NULL
/* pconfig */, "arch-lbr",
864 NULL
, NULL
, "amx-bf16", "avx512-fp16",
865 "amx-tile", "amx-int8", "spec-ctrl", "stibp",
866 NULL
, "arch-capabilities", "core-capability", "ssbd",
870 .needs_ecx
= true, .ecx
= 0,
873 .tcg_features
= TCG_7_0_EDX_FEATURES
,
876 .type
= CPUID_FEATURE_WORD
,
878 NULL
, NULL
, NULL
, NULL
,
879 "avx-vnni", "avx512-bf16", NULL
, "cmpccxadd",
880 NULL
, NULL
, "fzrm", "fsrs",
881 "fsrc", NULL
, NULL
, NULL
,
882 NULL
, NULL
, NULL
, NULL
,
883 NULL
, "amx-fp16", NULL
, "avx-ifma",
884 NULL
, NULL
, NULL
, NULL
,
885 NULL
, NULL
, NULL
, NULL
,
889 .needs_ecx
= true, .ecx
= 1,
892 .tcg_features
= TCG_7_1_EAX_FEATURES
,
895 .type
= CPUID_FEATURE_WORD
,
897 NULL
, NULL
, NULL
, NULL
,
898 "avx-vnni-int8", "avx-ne-convert", NULL
, NULL
,
899 NULL
, NULL
, NULL
, NULL
,
900 NULL
, NULL
, "prefetchiti", NULL
,
901 NULL
, NULL
, NULL
, NULL
,
902 NULL
, NULL
, NULL
, NULL
,
903 NULL
, NULL
, NULL
, NULL
,
904 NULL
, NULL
, NULL
, NULL
,
908 .needs_ecx
= true, .ecx
= 1,
911 .tcg_features
= TCG_7_1_EDX_FEATURES
,
913 [FEAT_8000_0007_EDX
] = {
914 .type
= CPUID_FEATURE_WORD
,
916 NULL
, NULL
, NULL
, NULL
,
917 NULL
, NULL
, NULL
, NULL
,
918 "invtsc", NULL
, NULL
, NULL
,
919 NULL
, NULL
, NULL
, NULL
,
920 NULL
, NULL
, NULL
, NULL
,
921 NULL
, NULL
, NULL
, NULL
,
922 NULL
, NULL
, NULL
, NULL
,
923 NULL
, NULL
, NULL
, NULL
,
925 .cpuid
= { .eax
= 0x80000007, .reg
= R_EDX
, },
926 .tcg_features
= TCG_APM_FEATURES
,
927 .unmigratable_flags
= CPUID_APM_INVTSC
,
929 [FEAT_8000_0008_EBX
] = {
930 .type
= CPUID_FEATURE_WORD
,
932 "clzero", NULL
, "xsaveerptr", NULL
,
933 NULL
, NULL
, NULL
, NULL
,
934 NULL
, "wbnoinvd", NULL
, NULL
,
935 "ibpb", NULL
, "ibrs", "amd-stibp",
936 NULL
, "stibp-always-on", NULL
, NULL
,
937 NULL
, NULL
, NULL
, NULL
,
938 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL
,
939 "amd-psfd", NULL
, NULL
, NULL
,
941 .cpuid
= { .eax
= 0x80000008, .reg
= R_EBX
, },
943 .unmigratable_flags
= 0,
945 [FEAT_8000_0021_EAX
] = {
946 .type
= CPUID_FEATURE_WORD
,
948 "no-nested-data-bp", NULL
, "lfence-always-serializing", NULL
,
949 NULL
, NULL
, "null-sel-clr-base", NULL
,
950 "auto-ibrs", NULL
, NULL
, NULL
,
951 NULL
, NULL
, NULL
, NULL
,
952 NULL
, NULL
, NULL
, NULL
,
953 NULL
, NULL
, NULL
, NULL
,
954 NULL
, NULL
, NULL
, NULL
,
955 NULL
, NULL
, NULL
, NULL
,
957 .cpuid
= { .eax
= 0x80000021, .reg
= R_EAX
, },
959 .unmigratable_flags
= 0,
962 .type
= CPUID_FEATURE_WORD
,
964 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
965 "xfd", NULL
, NULL
, NULL
,
966 NULL
, NULL
, NULL
, NULL
,
967 NULL
, NULL
, NULL
, NULL
,
968 NULL
, NULL
, NULL
, NULL
,
969 NULL
, NULL
, NULL
, NULL
,
970 NULL
, NULL
, NULL
, NULL
,
971 NULL
, NULL
, NULL
, NULL
,
975 .needs_ecx
= true, .ecx
= 1,
978 .tcg_features
= TCG_XSAVE_FEATURES
,
980 [FEAT_XSAVE_XSS_LO
] = {
981 .type
= CPUID_FEATURE_WORD
,
983 NULL
, NULL
, NULL
, NULL
,
984 NULL
, NULL
, NULL
, NULL
,
985 NULL
, NULL
, NULL
, NULL
,
986 NULL
, NULL
, NULL
, NULL
,
987 NULL
, NULL
, NULL
, NULL
,
988 NULL
, NULL
, NULL
, NULL
,
989 NULL
, NULL
, NULL
, NULL
,
990 NULL
, NULL
, NULL
, NULL
,
999 [FEAT_XSAVE_XSS_HI
] = {
1000 .type
= CPUID_FEATURE_WORD
,
1009 .type
= CPUID_FEATURE_WORD
,
1011 NULL
, NULL
, "arat", NULL
,
1012 NULL
, NULL
, NULL
, NULL
,
1013 NULL
, NULL
, NULL
, NULL
,
1014 NULL
, NULL
, NULL
, NULL
,
1015 NULL
, NULL
, NULL
, NULL
,
1016 NULL
, NULL
, NULL
, NULL
,
1017 NULL
, NULL
, NULL
, NULL
,
1018 NULL
, NULL
, NULL
, NULL
,
1020 .cpuid
= { .eax
= 6, .reg
= R_EAX
, },
1021 .tcg_features
= TCG_6_EAX_FEATURES
,
1023 [FEAT_XSAVE_XCR0_LO
] = {
1024 .type
= CPUID_FEATURE_WORD
,
1027 .needs_ecx
= true, .ecx
= 0,
1030 .tcg_features
= ~0U,
1031 .migratable_flags
= XSTATE_FP_MASK
| XSTATE_SSE_MASK
|
1032 XSTATE_YMM_MASK
| XSTATE_BNDREGS_MASK
| XSTATE_BNDCSR_MASK
|
1033 XSTATE_OPMASK_MASK
| XSTATE_ZMM_Hi256_MASK
| XSTATE_Hi16_ZMM_MASK
|
1036 [FEAT_XSAVE_XCR0_HI
] = {
1037 .type
= CPUID_FEATURE_WORD
,
1040 .needs_ecx
= true, .ecx
= 0,
1043 .tcg_features
= ~0U,
1045 /*Below are MSR exposed features*/
1046 [FEAT_ARCH_CAPABILITIES
] = {
1047 .type
= MSR_FEATURE_WORD
,
1049 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1050 "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1051 "taa-no", NULL
, NULL
, NULL
,
1052 NULL
, NULL
, NULL
, NULL
,
1053 NULL
, NULL
, NULL
, NULL
,
1054 NULL
, NULL
, NULL
, NULL
,
1055 NULL
, NULL
, NULL
, NULL
,
1056 NULL
, NULL
, NULL
, NULL
,
1059 .index
= MSR_IA32_ARCH_CAPABILITIES
,
1062 [FEAT_CORE_CAPABILITY
] = {
1063 .type
= MSR_FEATURE_WORD
,
1065 NULL
, NULL
, NULL
, NULL
,
1066 NULL
, "split-lock-detect", NULL
, NULL
,
1067 NULL
, NULL
, NULL
, NULL
,
1068 NULL
, NULL
, NULL
, NULL
,
1069 NULL
, NULL
, NULL
, NULL
,
1070 NULL
, NULL
, NULL
, NULL
,
1071 NULL
, NULL
, NULL
, NULL
,
1072 NULL
, NULL
, NULL
, NULL
,
1075 .index
= MSR_IA32_CORE_CAPABILITY
,
1078 [FEAT_PERF_CAPABILITIES
] = {
1079 .type
= MSR_FEATURE_WORD
,
1081 NULL
, NULL
, NULL
, NULL
,
1082 NULL
, NULL
, NULL
, NULL
,
1083 NULL
, NULL
, NULL
, NULL
,
1084 NULL
, "full-width-write", NULL
, NULL
,
1085 NULL
, NULL
, NULL
, NULL
,
1086 NULL
, NULL
, NULL
, NULL
,
1087 NULL
, NULL
, NULL
, NULL
,
1088 NULL
, NULL
, NULL
, NULL
,
1091 .index
= MSR_IA32_PERF_CAPABILITIES
,
1095 [FEAT_VMX_PROCBASED_CTLS
] = {
1096 .type
= MSR_FEATURE_WORD
,
1098 NULL
, NULL
, "vmx-vintr-pending", "vmx-tsc-offset",
1099 NULL
, NULL
, NULL
, "vmx-hlt-exit",
1100 NULL
, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1101 "vmx-rdtsc-exit", NULL
, NULL
, "vmx-cr3-load-noexit",
1102 "vmx-cr3-store-noexit", NULL
, NULL
, "vmx-cr8-load-exit",
1103 "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1104 "vmx-io-exit", "vmx-io-bitmap", NULL
, "vmx-mtf",
1105 "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1108 .index
= MSR_IA32_VMX_TRUE_PROCBASED_CTLS
,
1112 [FEAT_VMX_SECONDARY_CTLS
] = {
1113 .type
= MSR_FEATURE_WORD
,
1115 "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1116 "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1117 "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1118 "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1119 "vmx-rdseed-exit", "vmx-pml", NULL
, NULL
,
1120 "vmx-xsaves", NULL
, NULL
, NULL
,
1121 NULL
, "vmx-tsc-scaling", NULL
, NULL
,
1122 NULL
, NULL
, NULL
, NULL
,
1125 .index
= MSR_IA32_VMX_PROCBASED_CTLS2
,
1129 [FEAT_VMX_PINBASED_CTLS
] = {
1130 .type
= MSR_FEATURE_WORD
,
1132 "vmx-intr-exit", NULL
, NULL
, "vmx-nmi-exit",
1133 NULL
, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1134 NULL
, NULL
, NULL
, NULL
,
1135 NULL
, NULL
, NULL
, NULL
,
1136 NULL
, NULL
, NULL
, NULL
,
1137 NULL
, NULL
, NULL
, NULL
,
1138 NULL
, NULL
, NULL
, NULL
,
1139 NULL
, NULL
, NULL
, NULL
,
1142 .index
= MSR_IA32_VMX_TRUE_PINBASED_CTLS
,
1146 [FEAT_VMX_EXIT_CTLS
] = {
1147 .type
= MSR_FEATURE_WORD
,
1149 * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1153 NULL
, NULL
, "vmx-exit-nosave-debugctl", NULL
,
1154 NULL
, NULL
, NULL
, NULL
,
1155 NULL
, NULL
/* vmx-exit-host-addr-space-size */, NULL
, NULL
,
1156 "vmx-exit-load-perf-global-ctrl", NULL
, NULL
, "vmx-exit-ack-intr",
1157 NULL
, NULL
, "vmx-exit-save-pat", "vmx-exit-load-pat",
1158 "vmx-exit-save-efer", "vmx-exit-load-efer",
1159 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1160 NULL
, "vmx-exit-clear-rtit-ctl", NULL
, NULL
,
1161 NULL
, "vmx-exit-load-pkrs", NULL
, NULL
,
1164 .index
= MSR_IA32_VMX_TRUE_EXIT_CTLS
,
1168 [FEAT_VMX_ENTRY_CTLS
] = {
1169 .type
= MSR_FEATURE_WORD
,
1171 NULL
, NULL
, "vmx-entry-noload-debugctl", NULL
,
1172 NULL
, NULL
, NULL
, NULL
,
1173 NULL
, "vmx-entry-ia32e-mode", NULL
, NULL
,
1174 NULL
, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1175 "vmx-entry-load-bndcfgs", NULL
, "vmx-entry-load-rtit-ctl", NULL
,
1176 NULL
, NULL
, "vmx-entry-load-pkrs", NULL
,
1177 NULL
, NULL
, NULL
, NULL
,
1178 NULL
, NULL
, NULL
, NULL
,
1181 .index
= MSR_IA32_VMX_TRUE_ENTRY_CTLS
,
1186 .type
= MSR_FEATURE_WORD
,
1188 NULL
, NULL
, NULL
, NULL
,
1189 NULL
, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1190 "vmx-activity-wait-sipi", NULL
, NULL
, NULL
,
1191 NULL
, NULL
, NULL
, NULL
,
1192 NULL
, NULL
, NULL
, NULL
,
1193 NULL
, NULL
, NULL
, NULL
,
1194 NULL
, NULL
, NULL
, NULL
,
1195 NULL
, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL
,
1198 .index
= MSR_IA32_VMX_MISC
,
1202 [FEAT_VMX_EPT_VPID_CAPS
] = {
1203 .type
= MSR_FEATURE_WORD
,
1205 "vmx-ept-execonly", NULL
, NULL
, NULL
,
1206 NULL
, NULL
, "vmx-page-walk-4", "vmx-page-walk-5",
1207 NULL
, NULL
, NULL
, NULL
,
1208 NULL
, NULL
, NULL
, NULL
,
1209 "vmx-ept-2mb", "vmx-ept-1gb", NULL
, NULL
,
1210 "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL
,
1211 NULL
, "vmx-invept-single-context", "vmx-invept-all-context", NULL
,
1212 NULL
, NULL
, NULL
, NULL
,
1213 "vmx-invvpid", NULL
, NULL
, NULL
,
1214 NULL
, NULL
, NULL
, NULL
,
1215 "vmx-invvpid-single-addr", "vmx-invept-single-context",
1216 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1217 NULL
, NULL
, NULL
, NULL
,
1218 NULL
, NULL
, NULL
, NULL
,
1219 NULL
, NULL
, NULL
, NULL
,
1220 NULL
, NULL
, NULL
, NULL
,
1221 NULL
, NULL
, NULL
, NULL
,
1224 .index
= MSR_IA32_VMX_EPT_VPID_CAP
,
1228 [FEAT_VMX_BASIC
] = {
1229 .type
= MSR_FEATURE_WORD
,
1231 [54] = "vmx-ins-outs",
1232 [55] = "vmx-true-ctls",
1235 .index
= MSR_IA32_VMX_BASIC
,
1237 /* Just to be safe - we don't support setting the MSEG version field. */
1238 .no_autoenable_flags
= MSR_VMX_BASIC_DUAL_MONITOR
,
1241 [FEAT_VMX_VMFUNC
] = {
1242 .type
= MSR_FEATURE_WORD
,
1244 [0] = "vmx-eptp-switching",
1247 .index
= MSR_IA32_VMX_VMFUNC
,
1252 .type
= CPUID_FEATURE_WORD
,
1254 NULL
, NULL
, NULL
, NULL
,
1255 NULL
, NULL
, NULL
, NULL
,
1256 NULL
, NULL
, NULL
, NULL
,
1257 NULL
, NULL
, NULL
, NULL
,
1258 NULL
, NULL
, NULL
, NULL
,
1259 NULL
, NULL
, NULL
, NULL
,
1260 NULL
, NULL
, NULL
, NULL
,
1261 NULL
, NULL
, NULL
, "intel-pt-lip",
1265 .needs_ecx
= true, .ecx
= 0,
1268 .tcg_features
= TCG_14_0_ECX_FEATURES
,
1271 [FEAT_SGX_12_0_EAX
] = {
1272 .type
= CPUID_FEATURE_WORD
,
1274 "sgx1", "sgx2", NULL
, NULL
,
1275 NULL
, NULL
, NULL
, NULL
,
1276 NULL
, NULL
, NULL
, "sgx-edeccssa",
1277 NULL
, NULL
, NULL
, NULL
,
1278 NULL
, NULL
, NULL
, NULL
,
1279 NULL
, NULL
, NULL
, NULL
,
1280 NULL
, NULL
, NULL
, NULL
,
1281 NULL
, NULL
, NULL
, NULL
,
1285 .needs_ecx
= true, .ecx
= 0,
1288 .tcg_features
= TCG_SGX_12_0_EAX_FEATURES
,
1291 [FEAT_SGX_12_0_EBX
] = {
1292 .type
= CPUID_FEATURE_WORD
,
1294 "sgx-exinfo" , NULL
, NULL
, NULL
,
1295 NULL
, NULL
, NULL
, NULL
,
1296 NULL
, NULL
, NULL
, NULL
,
1297 NULL
, NULL
, NULL
, NULL
,
1298 NULL
, NULL
, NULL
, NULL
,
1299 NULL
, NULL
, NULL
, NULL
,
1300 NULL
, NULL
, NULL
, NULL
,
1301 NULL
, NULL
, NULL
, NULL
,
1305 .needs_ecx
= true, .ecx
= 0,
1308 .tcg_features
= TCG_SGX_12_0_EBX_FEATURES
,
1311 [FEAT_SGX_12_1_EAX
] = {
1312 .type
= CPUID_FEATURE_WORD
,
1314 NULL
, "sgx-debug", "sgx-mode64", NULL
,
1315 "sgx-provisionkey", "sgx-tokenkey", NULL
, "sgx-kss",
1316 NULL
, NULL
, "sgx-aex-notify", NULL
,
1317 NULL
, NULL
, NULL
, NULL
,
1318 NULL
, NULL
, NULL
, NULL
,
1319 NULL
, NULL
, NULL
, NULL
,
1320 NULL
, NULL
, NULL
, NULL
,
1321 NULL
, NULL
, NULL
, NULL
,
1325 .needs_ecx
= true, .ecx
= 1,
1328 .tcg_features
= TCG_SGX_12_1_EAX_FEATURES
,
1332 typedef struct FeatureMask
{
1337 typedef struct FeatureDep
{
1338 FeatureMask from
, to
;
1341 static FeatureDep feature_dependencies
[] = {
1343 .from
= { FEAT_7_0_EDX
, CPUID_7_0_EDX_ARCH_CAPABILITIES
},
1344 .to
= { FEAT_ARCH_CAPABILITIES
, ~0ull },
1347 .from
= { FEAT_7_0_EDX
, CPUID_7_0_EDX_CORE_CAPABILITY
},
1348 .to
= { FEAT_CORE_CAPABILITY
, ~0ull },
1351 .from
= { FEAT_1_ECX
, CPUID_EXT_PDCM
},
1352 .to
= { FEAT_PERF_CAPABILITIES
, ~0ull },
1355 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1356 .to
= { FEAT_VMX_PROCBASED_CTLS
, ~0ull },
1359 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1360 .to
= { FEAT_VMX_PINBASED_CTLS
, ~0ull },
1363 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1364 .to
= { FEAT_VMX_EXIT_CTLS
, ~0ull },
1367 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1368 .to
= { FEAT_VMX_ENTRY_CTLS
, ~0ull },
1371 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1372 .to
= { FEAT_VMX_MISC
, ~0ull },
1375 .from
= { FEAT_1_ECX
, CPUID_EXT_VMX
},
1376 .to
= { FEAT_VMX_BASIC
, ~0ull },
1379 .from
= { FEAT_8000_0001_EDX
, CPUID_EXT2_LM
},
1380 .to
= { FEAT_VMX_ENTRY_CTLS
, VMX_VM_ENTRY_IA32E_MODE
},
1383 .from
= { FEAT_VMX_PROCBASED_CTLS
, VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
},
1384 .to
= { FEAT_VMX_SECONDARY_CTLS
, ~0ull },
1387 .from
= { FEAT_XSAVE
, CPUID_XSAVE_XSAVES
},
1388 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_XSAVES
},
1391 .from
= { FEAT_1_ECX
, CPUID_EXT_RDRAND
},
1392 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDRAND_EXITING
},
1395 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_INVPCID
},
1396 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_INVPCID
},
1399 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_MPX
},
1400 .to
= { FEAT_VMX_EXIT_CTLS
, VMX_VM_EXIT_CLEAR_BNDCFGS
},
1403 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_MPX
},
1404 .to
= { FEAT_VMX_ENTRY_CTLS
, VMX_VM_ENTRY_LOAD_BNDCFGS
},
1407 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_RDSEED
},
1408 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDSEED_EXITING
},
1411 .from
= { FEAT_7_0_EBX
, CPUID_7_0_EBX_INTEL_PT
},
1412 .to
= { FEAT_14_0_ECX
, ~0ull },
1415 .from
= { FEAT_8000_0001_EDX
, CPUID_EXT2_RDTSCP
},
1416 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_RDTSCP
},
1419 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_EPT
},
1420 .to
= { FEAT_VMX_EPT_VPID_CAPS
, 0xffffffffull
},
1423 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_EPT
},
1424 .to
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
},
1427 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_VPID
},
1428 .to
= { FEAT_VMX_EPT_VPID_CAPS
, 0xffffffffull
<< 32 },
1431 .from
= { FEAT_VMX_SECONDARY_CTLS
, VMX_SECONDARY_EXEC_ENABLE_VMFUNC
},
1432 .to
= { FEAT_VMX_VMFUNC
, ~0ull },
1435 .from
= { FEAT_8000_0001_ECX
, CPUID_EXT3_SVM
},
1436 .to
= { FEAT_SVM
, ~0ull },
1440 typedef struct X86RegisterInfo32
{
1441 /* Name of register */
1443 /* QAPI enum value register */
1444 X86CPURegister32 qapi_enum
;
1445 } X86RegisterInfo32
;
1447 #define REGISTER(reg) \
1448 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1449 static const X86RegisterInfo32 x86_reg_info_32
[CPU_NB_REGS32
] = {
1461 /* CPUID feature bits available in XSS */
1462 #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK)
1464 ExtSaveArea x86_ext_save_areas
[XSAVE_STATE_AREA_COUNT
] = {
1466 /* x87 FP state component is always enabled if XSAVE is supported */
1467 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1468 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1470 [XSTATE_SSE_BIT
] = {
1471 /* SSE state component is always enabled if XSAVE is supported */
1472 .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_XSAVE
,
1473 .size
= sizeof(X86LegacyXSaveArea
) + sizeof(X86XSaveHeader
),
1476 { .feature
= FEAT_1_ECX
, .bits
= CPUID_EXT_AVX
,
1477 .size
= sizeof(XSaveAVX
) },
1478 [XSTATE_BNDREGS_BIT
] =
1479 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1480 .size
= sizeof(XSaveBNDREG
) },
1481 [XSTATE_BNDCSR_BIT
] =
1482 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_MPX
,
1483 .size
= sizeof(XSaveBNDCSR
) },
1484 [XSTATE_OPMASK_BIT
] =
1485 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1486 .size
= sizeof(XSaveOpmask
) },
1487 [XSTATE_ZMM_Hi256_BIT
] =
1488 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1489 .size
= sizeof(XSaveZMM_Hi256
) },
1490 [XSTATE_Hi16_ZMM_BIT
] =
1491 { .feature
= FEAT_7_0_EBX
, .bits
= CPUID_7_0_EBX_AVX512F
,
1492 .size
= sizeof(XSaveHi16_ZMM
) },
1494 { .feature
= FEAT_7_0_ECX
, .bits
= CPUID_7_0_ECX_PKU
,
1495 .size
= sizeof(XSavePKRU
) },
1496 [XSTATE_ARCH_LBR_BIT
] = {
1497 .feature
= FEAT_7_0_EDX
, .bits
= CPUID_7_0_EDX_ARCH_LBR
,
1498 .offset
= 0 /*supervisor mode component, offset = 0 */,
1499 .size
= sizeof(XSavesArchLBR
) },
1500 [XSTATE_XTILE_CFG_BIT
] = {
1501 .feature
= FEAT_7_0_EDX
, .bits
= CPUID_7_0_EDX_AMX_TILE
,
1502 .size
= sizeof(XSaveXTILECFG
),
1504 [XSTATE_XTILE_DATA_BIT
] = {
1505 .feature
= FEAT_7_0_EDX
, .bits
= CPUID_7_0_EDX_AMX_TILE
,
1506 .size
= sizeof(XSaveXTILEDATA
)
1510 uint32_t xsave_area_size(uint64_t mask
, bool compacted
)
1512 uint64_t ret
= x86_ext_save_areas
[0].size
;
1513 const ExtSaveArea
*esa
;
1514 uint32_t offset
= 0;
1517 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
1518 esa
= &x86_ext_save_areas
[i
];
1519 if ((mask
>> i
) & 1) {
1520 offset
= compacted
? ret
: esa
->offset
;
1521 ret
= MAX(ret
, offset
+ esa
->size
);
1527 static inline bool accel_uses_host_cpuid(void)
1529 return kvm_enabled() || hvf_enabled();
1532 static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU
*cpu
)
1534 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_XCR0_HI
]) << 32 |
1535 cpu
->env
.features
[FEAT_XSAVE_XCR0_LO
];
1538 /* Return name of 32-bit register, from a R_* constant */
1539 static const char *get_register_name_32(unsigned int reg
)
1541 if (reg
>= CPU_NB_REGS32
) {
1544 return x86_reg_info_32
[reg
].name
;
1547 static inline uint64_t x86_cpu_xsave_xss_components(X86CPU
*cpu
)
1549 return ((uint64_t)cpu
->env
.features
[FEAT_XSAVE_XSS_HI
]) << 32 |
1550 cpu
->env
.features
[FEAT_XSAVE_XSS_LO
];
1554 * Returns the set of feature flags that are supported and migratable by
1555 * QEMU, for a given FeatureWord.
1557 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w
)
1559 FeatureWordInfo
*wi
= &feature_word_info
[w
];
1563 for (i
= 0; i
< 64; i
++) {
1564 uint64_t f
= 1ULL << i
;
1566 /* If the feature name is known, it is implicitly considered migratable,
1567 * unless it is explicitly set in unmigratable_flags */
1568 if ((wi
->migratable_flags
& f
) ||
1569 (wi
->feat_names
[i
] && !(wi
->unmigratable_flags
& f
))) {
1576 void host_cpuid(uint32_t function
, uint32_t count
,
1577 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
1582 asm volatile("cpuid"
1583 : "=a"(vec
[0]), "=b"(vec
[1]),
1584 "=c"(vec
[2]), "=d"(vec
[3])
1585 : "0"(function
), "c"(count
) : "cc");
1586 #elif defined(__i386__)
1587 asm volatile("pusha \n\t"
1589 "mov %%eax, 0(%2) \n\t"
1590 "mov %%ebx, 4(%2) \n\t"
1591 "mov %%ecx, 8(%2) \n\t"
1592 "mov %%edx, 12(%2) \n\t"
1594 : : "a"(function
), "c"(count
), "S"(vec
)
1610 /* CPU class name definitions: */
1612 /* Return type name for a given CPU model name
1613 * Caller is responsible for freeing the returned string.
1615 static char *x86_cpu_type_name(const char *model_name
)
1617 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name
);
1620 static ObjectClass
*x86_cpu_class_by_name(const char *cpu_model
)
1622 g_autofree
char *typename
= x86_cpu_type_name(cpu_model
);
1623 return object_class_by_name(typename
);
1626 static char *x86_cpu_class_get_model_name(X86CPUClass
*cc
)
1628 const char *class_name
= object_class_get_name(OBJECT_CLASS(cc
));
1629 assert(g_str_has_suffix(class_name
, X86_CPU_TYPE_SUFFIX
));
1630 return g_strndup(class_name
,
1631 strlen(class_name
) - strlen(X86_CPU_TYPE_SUFFIX
));
1634 typedef struct X86CPUVersionDefinition
{
1635 X86CPUVersion version
;
1639 const CPUCaches
*const cache_info
;
1640 } X86CPUVersionDefinition
;
1642 /* Base definition for a CPU model */
1643 typedef struct X86CPUDefinition
{
1647 /* vendor is zero-terminated, 12 character ASCII string */
1648 char vendor
[CPUID_VENDOR_SZ
+ 1];
1652 FeatureWordArray features
;
1653 const char *model_id
;
1654 const CPUCaches
*const cache_info
;
1656 * Definitions for alternative versions of CPU model.
1657 * List is terminated by item with version == 0.
1658 * If NULL, version 1 will be registered automatically.
1660 const X86CPUVersionDefinition
*versions
;
1661 const char *deprecation_note
;
1664 /* Reference to a specific CPU model version */
1665 struct X86CPUModel
{
1666 /* Base CPU definition */
1667 const X86CPUDefinition
*cpudef
;
1668 /* CPU model version */
1669 X86CPUVersion version
;
1672 * If true, this is an alias CPU model.
1673 * This matters only for "-cpu help" and query-cpu-definitions
1678 /* Get full model name for CPU version */
1679 static char *x86_cpu_versioned_model_name(const X86CPUDefinition
*cpudef
,
1680 X86CPUVersion version
)
1682 assert(version
> 0);
1683 return g_strdup_printf("%s-v%d", cpudef
->name
, (int)version
);
1686 static const X86CPUVersionDefinition
*
1687 x86_cpu_def_get_versions(const X86CPUDefinition
*def
)
1689 /* When X86CPUDefinition::versions is NULL, we register only v1 */
1690 static const X86CPUVersionDefinition default_version_list
[] = {
1692 { /* end of list */ }
1695 return def
->versions
?: default_version_list
;
1698 static const CPUCaches epyc_cache_info
= {
1699 .l1d_cache
= &(CPUCacheInfo
) {
1709 .no_invd_sharing
= true,
1711 .l1i_cache
= &(CPUCacheInfo
) {
1712 .type
= INSTRUCTION_CACHE
,
1721 .no_invd_sharing
= true,
1723 .l2_cache
= &(CPUCacheInfo
) {
1724 .type
= UNIFIED_CACHE
,
1733 .l3_cache
= &(CPUCacheInfo
) {
1734 .type
= UNIFIED_CACHE
,
1738 .associativity
= 16,
1744 .complex_indexing
= true,
1748 static CPUCaches epyc_v4_cache_info
= {
1749 .l1d_cache
= &(CPUCacheInfo
) {
1759 .no_invd_sharing
= true,
1761 .l1i_cache
= &(CPUCacheInfo
) {
1762 .type
= INSTRUCTION_CACHE
,
1771 .no_invd_sharing
= true,
1773 .l2_cache
= &(CPUCacheInfo
) {
1774 .type
= UNIFIED_CACHE
,
1783 .l3_cache
= &(CPUCacheInfo
) {
1784 .type
= UNIFIED_CACHE
,
1788 .associativity
= 16,
1794 .complex_indexing
= false,
1798 static const CPUCaches epyc_rome_cache_info
= {
1799 .l1d_cache
= &(CPUCacheInfo
) {
1809 .no_invd_sharing
= true,
1811 .l1i_cache
= &(CPUCacheInfo
) {
1812 .type
= INSTRUCTION_CACHE
,
1821 .no_invd_sharing
= true,
1823 .l2_cache
= &(CPUCacheInfo
) {
1824 .type
= UNIFIED_CACHE
,
1833 .l3_cache
= &(CPUCacheInfo
) {
1834 .type
= UNIFIED_CACHE
,
1838 .associativity
= 16,
1844 .complex_indexing
= true,
1848 static const CPUCaches epyc_rome_v3_cache_info
= {
1849 .l1d_cache
= &(CPUCacheInfo
) {
1859 .no_invd_sharing
= true,
1861 .l1i_cache
= &(CPUCacheInfo
) {
1862 .type
= INSTRUCTION_CACHE
,
1871 .no_invd_sharing
= true,
1873 .l2_cache
= &(CPUCacheInfo
) {
1874 .type
= UNIFIED_CACHE
,
1883 .l3_cache
= &(CPUCacheInfo
) {
1884 .type
= UNIFIED_CACHE
,
1888 .associativity
= 16,
1894 .complex_indexing
= false,
1898 static const CPUCaches epyc_milan_cache_info
= {
1899 .l1d_cache
= &(CPUCacheInfo
) {
1909 .no_invd_sharing
= true,
1911 .l1i_cache
= &(CPUCacheInfo
) {
1912 .type
= INSTRUCTION_CACHE
,
1921 .no_invd_sharing
= true,
1923 .l2_cache
= &(CPUCacheInfo
) {
1924 .type
= UNIFIED_CACHE
,
1933 .l3_cache
= &(CPUCacheInfo
) {
1934 .type
= UNIFIED_CACHE
,
1938 .associativity
= 16,
1944 .complex_indexing
= true,
1948 static const CPUCaches epyc_milan_v2_cache_info
= {
1949 .l1d_cache
= &(CPUCacheInfo
) {
1959 .no_invd_sharing
= true,
1961 .l1i_cache
= &(CPUCacheInfo
) {
1962 .type
= INSTRUCTION_CACHE
,
1971 .no_invd_sharing
= true,
1973 .l2_cache
= &(CPUCacheInfo
) {
1974 .type
= UNIFIED_CACHE
,
1983 .l3_cache
= &(CPUCacheInfo
) {
1984 .type
= UNIFIED_CACHE
,
1988 .associativity
= 16,
1994 .complex_indexing
= false,
1998 static const CPUCaches epyc_genoa_cache_info
= {
1999 .l1d_cache
= &(CPUCacheInfo
) {
2009 .no_invd_sharing
= true,
2011 .l1i_cache
= &(CPUCacheInfo
) {
2012 .type
= INSTRUCTION_CACHE
,
2021 .no_invd_sharing
= true,
2023 .l2_cache
= &(CPUCacheInfo
) {
2024 .type
= UNIFIED_CACHE
,
2033 .l3_cache
= &(CPUCacheInfo
) {
2034 .type
= UNIFIED_CACHE
,
2038 .associativity
= 16,
2044 .complex_indexing
= false,
2048 /* The following VMX features are not supported by KVM and are left out in the
2051 * Dual-monitor support (all processors)
2053 * Deactivate dual-monitor treatment
2054 * Number of CR3-target values
2055 * Shutdown activity state
2056 * Wait-for-SIPI activity state
2057 * PAUSE-loop exiting (Westmere and newer)
2058 * EPT-violation #VE (Broadwell and newer)
2059 * Inject event with insn length=0 (Skylake and newer)
2060 * Conceal non-root operation from PT
2061 * Conceal VM exits from PT
2062 * Conceal VM entries from PT
2063 * Enable ENCLS exiting
2064 * Mode-based execute control (XS/XU)
2065 s TSC scaling (Skylake Server and newer)
2066 * GPA translation for PT (IceLake and newer)
2067 * User wait and pause
2069 * Load IA32_RTIT_CTL
2070 * Clear IA32_RTIT_CTL
2071 * Advanced VM-exit information for EPT violations
2072 * Sub-page write permissions
2073 * PT in VMX operation
2076 static const X86CPUDefinition builtin_x86_defs
[] = {
2080 .vendor
= CPUID_VENDOR_AMD
,
2084 .features
[FEAT_1_EDX
] =
2086 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2088 .features
[FEAT_1_ECX
] =
2089 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
2090 .features
[FEAT_8000_0001_EDX
] =
2091 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2092 .features
[FEAT_8000_0001_ECX
] =
2093 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
,
2094 .xlevel
= 0x8000000A,
2095 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2100 .vendor
= CPUID_VENDOR_AMD
,
2104 /* Missing: CPUID_HT */
2105 .features
[FEAT_1_EDX
] =
2107 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2108 CPUID_PSE36
| CPUID_VME
,
2109 .features
[FEAT_1_ECX
] =
2110 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
2112 .features
[FEAT_8000_0001_EDX
] =
2113 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
2114 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
2115 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
2116 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2118 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2119 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
2120 .features
[FEAT_8000_0001_ECX
] =
2121 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
2122 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
2123 /* Missing: CPUID_SVM_LBRV */
2124 .features
[FEAT_SVM
] =
2126 .xlevel
= 0x8000001A,
2127 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
2132 .vendor
= CPUID_VENDOR_INTEL
,
2136 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2137 .features
[FEAT_1_EDX
] =
2139 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2140 CPUID_PSE36
| CPUID_VME
| CPUID_ACPI
| CPUID_SS
,
2141 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
2142 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
2143 .features
[FEAT_1_ECX
] =
2144 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
2146 .features
[FEAT_8000_0001_EDX
] =
2147 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2148 .features
[FEAT_8000_0001_ECX
] =
2150 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2151 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2152 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2153 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2154 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2155 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2156 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2157 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2158 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2159 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2160 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2161 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2162 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2163 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2164 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2165 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2166 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2167 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
,
2168 .xlevel
= 0x80000008,
2169 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
2174 .vendor
= CPUID_VENDOR_INTEL
,
2178 /* Missing: CPUID_HT */
2179 .features
[FEAT_1_EDX
] =
2180 PPRO_FEATURES
| CPUID_VME
|
2181 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
2183 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
2184 .features
[FEAT_1_ECX
] =
2185 CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
2186 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
2187 .features
[FEAT_8000_0001_EDX
] =
2188 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2189 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
2190 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
2191 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
2192 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
2193 .features
[FEAT_8000_0001_ECX
] =
2195 /* VMX features from Cedar Mill/Prescott */
2196 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2197 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2198 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2199 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2200 VMX_PIN_BASED_NMI_EXITING
,
2201 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2202 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2203 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2204 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2205 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2206 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2207 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2208 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
,
2209 .xlevel
= 0x80000008,
2210 .model_id
= "Common KVM processor"
2215 .vendor
= CPUID_VENDOR_INTEL
,
2219 .features
[FEAT_1_EDX
] =
2221 .features
[FEAT_1_ECX
] =
2223 .xlevel
= 0x80000004,
2224 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2229 .vendor
= CPUID_VENDOR_INTEL
,
2233 .features
[FEAT_1_EDX
] =
2234 PPRO_FEATURES
| CPUID_VME
|
2235 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
2236 .features
[FEAT_1_ECX
] =
2238 .features
[FEAT_8000_0001_ECX
] =
2240 /* VMX features from Yonah */
2241 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2242 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2243 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2244 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2245 VMX_PIN_BASED_NMI_EXITING
,
2246 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2247 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2248 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2249 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2250 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
2251 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
2252 VMX_CPU_BASED_PAUSE_EXITING
| VMX_CPU_BASED_USE_MSR_BITMAPS
,
2253 .xlevel
= 0x80000008,
2254 .model_id
= "Common 32-bit KVM processor"
2259 .vendor
= CPUID_VENDOR_INTEL
,
2263 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2264 .features
[FEAT_1_EDX
] =
2265 PPRO_FEATURES
| CPUID_VME
|
2266 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_ACPI
|
2268 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2269 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2270 .features
[FEAT_1_ECX
] =
2271 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
,
2272 .features
[FEAT_8000_0001_EDX
] =
2274 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2275 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2276 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2277 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2278 VMX_PIN_BASED_NMI_EXITING
,
2279 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2280 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2281 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2282 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2283 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
2284 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
2285 VMX_CPU_BASED_PAUSE_EXITING
| VMX_CPU_BASED_USE_MSR_BITMAPS
,
2286 .xlevel
= 0x80000008,
2287 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
2292 .vendor
= CPUID_VENDOR_INTEL
,
2296 .features
[FEAT_1_EDX
] =
2304 .vendor
= CPUID_VENDOR_INTEL
,
2308 .features
[FEAT_1_EDX
] =
2316 .vendor
= CPUID_VENDOR_INTEL
,
2320 .features
[FEAT_1_EDX
] =
2328 .vendor
= CPUID_VENDOR_INTEL
,
2332 .features
[FEAT_1_EDX
] =
2340 .vendor
= CPUID_VENDOR_AMD
,
2344 .features
[FEAT_1_EDX
] =
2345 PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
|
2347 .features
[FEAT_8000_0001_EDX
] =
2348 CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
2349 .xlevel
= 0x80000008,
2350 .model_id
= "QEMU Virtual CPU version " QEMU_HW_VERSION
,
2355 .vendor
= CPUID_VENDOR_INTEL
,
2359 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2360 .features
[FEAT_1_EDX
] =
2362 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
|
2363 CPUID_ACPI
| CPUID_SS
,
2364 /* Some CPUs got no CPUID_SEP */
2365 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2367 .features
[FEAT_1_ECX
] =
2368 CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
2370 .features
[FEAT_8000_0001_EDX
] =
2372 .features
[FEAT_8000_0001_ECX
] =
2374 .xlevel
= 0x80000008,
2375 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
2380 .vendor
= CPUID_VENDOR_INTEL
,
2384 .features
[FEAT_1_EDX
] =
2385 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2386 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2387 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2388 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2389 CPUID_DE
| CPUID_FP87
,
2390 .features
[FEAT_1_ECX
] =
2391 CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
2392 .features
[FEAT_8000_0001_EDX
] =
2393 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2394 .features
[FEAT_8000_0001_ECX
] =
2396 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2397 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
,
2398 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
,
2399 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2400 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2401 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2402 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2403 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2404 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2405 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2406 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2407 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2408 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2409 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2410 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2411 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2412 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2413 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
,
2414 .xlevel
= 0x80000008,
2415 .model_id
= "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2420 .vendor
= CPUID_VENDOR_INTEL
,
2424 .features
[FEAT_1_EDX
] =
2425 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2426 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2427 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2428 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2429 CPUID_DE
| CPUID_FP87
,
2430 .features
[FEAT_1_ECX
] =
2431 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2433 .features
[FEAT_8000_0001_EDX
] =
2434 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
2435 .features
[FEAT_8000_0001_ECX
] =
2437 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
,
2438 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2439 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2440 .features
[FEAT_VMX_EXIT_CTLS
] = VMX_VM_EXIT_ACK_INTR_ON_EXIT
|
2441 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
2442 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2443 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2444 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
,
2445 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2446 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2447 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2448 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2449 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2450 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2451 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2452 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2453 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2454 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2455 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2456 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2457 VMX_SECONDARY_EXEC_WBINVD_EXITING
,
2458 .xlevel
= 0x80000008,
2459 .model_id
= "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2464 .vendor
= CPUID_VENDOR_INTEL
,
2468 .features
[FEAT_1_EDX
] =
2469 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2470 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2471 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2472 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2473 CPUID_DE
| CPUID_FP87
,
2474 .features
[FEAT_1_ECX
] =
2475 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2476 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_SSE3
,
2477 .features
[FEAT_8000_0001_EDX
] =
2478 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2479 .features
[FEAT_8000_0001_ECX
] =
2481 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2482 MSR_VMX_BASIC_TRUE_CTLS
,
2483 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2484 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2485 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2486 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2487 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2488 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2489 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2490 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2491 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2492 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2493 .features
[FEAT_VMX_EXIT_CTLS
] =
2494 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2495 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2496 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2497 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2498 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2499 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
,
2500 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2501 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2502 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2503 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2504 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2505 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2506 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2507 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2508 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2509 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2510 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2511 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2512 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2513 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2514 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2515 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2516 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2517 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2518 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2519 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2520 VMX_SECONDARY_EXEC_ENABLE_VPID
,
2521 .xlevel
= 0x80000008,
2522 .model_id
= "Intel Core i7 9xx (Nehalem Class Core i7)",
2523 .versions
= (X86CPUVersionDefinition
[]) {
2527 .alias
= "Nehalem-IBRS",
2528 .props
= (PropValue
[]) {
2529 { "spec-ctrl", "on" },
2531 "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2532 { /* end of list */ }
2535 { /* end of list */ }
2541 .vendor
= CPUID_VENDOR_INTEL
,
2545 .features
[FEAT_1_EDX
] =
2546 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2547 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2548 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2549 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2550 CPUID_DE
| CPUID_FP87
,
2551 .features
[FEAT_1_ECX
] =
2552 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
2553 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2554 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
2555 .features
[FEAT_8000_0001_EDX
] =
2556 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
2557 .features
[FEAT_8000_0001_ECX
] =
2559 .features
[FEAT_6_EAX
] =
2561 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2562 MSR_VMX_BASIC_TRUE_CTLS
,
2563 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2564 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2565 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2566 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2567 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2568 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2569 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2570 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2571 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2572 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2573 .features
[FEAT_VMX_EXIT_CTLS
] =
2574 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2575 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2576 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2577 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2578 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2579 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2580 MSR_VMX_MISC_STORE_LMA
,
2581 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2582 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2583 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2584 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2585 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2586 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2587 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2588 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2589 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2590 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2591 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2592 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2593 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2594 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2595 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2596 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2597 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2598 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2599 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2600 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2601 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
,
2602 .xlevel
= 0x80000008,
2603 .model_id
= "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2604 .versions
= (X86CPUVersionDefinition
[]) {
2608 .alias
= "Westmere-IBRS",
2609 .props
= (PropValue
[]) {
2610 { "spec-ctrl", "on" },
2612 "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2613 { /* end of list */ }
2616 { /* end of list */ }
2620 .name
= "SandyBridge",
2622 .vendor
= CPUID_VENDOR_INTEL
,
2626 .features
[FEAT_1_EDX
] =
2627 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2628 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2629 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2630 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2631 CPUID_DE
| CPUID_FP87
,
2632 .features
[FEAT_1_ECX
] =
2633 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2634 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
2635 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2636 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2638 .features
[FEAT_8000_0001_EDX
] =
2639 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2641 .features
[FEAT_8000_0001_ECX
] =
2643 .features
[FEAT_XSAVE
] =
2644 CPUID_XSAVE_XSAVEOPT
,
2645 .features
[FEAT_6_EAX
] =
2647 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2648 MSR_VMX_BASIC_TRUE_CTLS
,
2649 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2650 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2651 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2652 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2653 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2654 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2655 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2656 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2657 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2658 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2659 .features
[FEAT_VMX_EXIT_CTLS
] =
2660 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2661 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2662 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2663 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2664 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2665 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2666 MSR_VMX_MISC_STORE_LMA
,
2667 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2668 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2669 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
2670 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2671 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2672 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2673 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2674 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2675 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2676 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2677 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2678 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2679 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2680 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2681 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2682 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2683 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2684 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2685 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2686 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2687 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
,
2688 .xlevel
= 0x80000008,
2689 .model_id
= "Intel Xeon E312xx (Sandy Bridge)",
2690 .versions
= (X86CPUVersionDefinition
[]) {
2694 .alias
= "SandyBridge-IBRS",
2695 .props
= (PropValue
[]) {
2696 { "spec-ctrl", "on" },
2698 "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2699 { /* end of list */ }
2702 { /* end of list */ }
2706 .name
= "IvyBridge",
2708 .vendor
= CPUID_VENDOR_INTEL
,
2712 .features
[FEAT_1_EDX
] =
2713 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2714 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2715 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2716 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2717 CPUID_DE
| CPUID_FP87
,
2718 .features
[FEAT_1_ECX
] =
2719 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2720 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_POPCNT
|
2721 CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
2722 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
2723 CPUID_EXT_SSE3
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2724 .features
[FEAT_7_0_EBX
] =
2725 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
|
2727 .features
[FEAT_8000_0001_EDX
] =
2728 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2730 .features
[FEAT_8000_0001_ECX
] =
2732 .features
[FEAT_XSAVE
] =
2733 CPUID_XSAVE_XSAVEOPT
,
2734 .features
[FEAT_6_EAX
] =
2736 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2737 MSR_VMX_BASIC_TRUE_CTLS
,
2738 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2739 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2740 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2741 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2742 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2743 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2744 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2745 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2746 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2747 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
2748 .features
[FEAT_VMX_EXIT_CTLS
] =
2749 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2750 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2751 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2752 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2753 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2754 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2755 MSR_VMX_MISC_STORE_LMA
,
2756 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2757 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2758 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2759 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2760 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2761 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2762 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2763 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2764 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2765 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2766 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2767 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2768 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2769 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2770 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2771 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2772 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2773 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2774 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2775 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2776 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2777 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2778 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2779 VMX_SECONDARY_EXEC_RDRAND_EXITING
,
2780 .xlevel
= 0x80000008,
2781 .model_id
= "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2782 .versions
= (X86CPUVersionDefinition
[]) {
2786 .alias
= "IvyBridge-IBRS",
2787 .props
= (PropValue
[]) {
2788 { "spec-ctrl", "on" },
2790 "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2791 { /* end of list */ }
2794 { /* end of list */ }
2800 .vendor
= CPUID_VENDOR_INTEL
,
2804 .features
[FEAT_1_EDX
] =
2805 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2806 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2807 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2808 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2809 CPUID_DE
| CPUID_FP87
,
2810 .features
[FEAT_1_ECX
] =
2811 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2812 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2813 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2814 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2815 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2816 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2817 .features
[FEAT_8000_0001_EDX
] =
2818 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2820 .features
[FEAT_8000_0001_ECX
] =
2821 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
,
2822 .features
[FEAT_7_0_EBX
] =
2823 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2824 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2825 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2827 .features
[FEAT_XSAVE
] =
2828 CPUID_XSAVE_XSAVEOPT
,
2829 .features
[FEAT_6_EAX
] =
2831 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2832 MSR_VMX_BASIC_TRUE_CTLS
,
2833 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2834 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2835 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2836 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2837 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2838 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2839 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2840 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2841 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2842 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
2843 .features
[FEAT_VMX_EXIT_CTLS
] =
2844 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2845 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2846 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2847 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2848 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2849 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2850 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
2851 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2852 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2853 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2854 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2855 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2856 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2857 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2858 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2859 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2860 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2861 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2862 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2863 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2864 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2865 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2866 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2867 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2868 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2869 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
2870 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2871 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2872 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2873 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2874 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
2875 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
,
2876 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
2877 .xlevel
= 0x80000008,
2878 .model_id
= "Intel Core Processor (Haswell)",
2879 .versions
= (X86CPUVersionDefinition
[]) {
2883 .alias
= "Haswell-noTSX",
2884 .props
= (PropValue
[]) {
2887 { "stepping", "1" },
2888 { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2889 { /* end of list */ }
2894 .alias
= "Haswell-IBRS",
2895 .props
= (PropValue
[]) {
2896 /* Restore TSX features removed by -v2 above */
2900 * Haswell and Haswell-IBRS had stepping=4 in
2901 * QEMU 4.0 and older
2903 { "stepping", "4" },
2904 { "spec-ctrl", "on" },
2906 "Intel Core Processor (Haswell, IBRS)" },
2907 { /* end of list */ }
2912 .alias
= "Haswell-noTSX-IBRS",
2913 .props
= (PropValue
[]) {
2916 /* spec-ctrl was already enabled by -v3 above */
2917 { "stepping", "1" },
2919 "Intel Core Processor (Haswell, no TSX, IBRS)" },
2920 { /* end of list */ }
2923 { /* end of list */ }
2927 .name
= "Broadwell",
2929 .vendor
= CPUID_VENDOR_INTEL
,
2933 .features
[FEAT_1_EDX
] =
2934 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
2935 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
2936 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
2937 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
2938 CPUID_DE
| CPUID_FP87
,
2939 .features
[FEAT_1_ECX
] =
2940 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
2941 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
2942 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
2943 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
2944 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
2945 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
2946 .features
[FEAT_8000_0001_EDX
] =
2947 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
2949 .features
[FEAT_8000_0001_ECX
] =
2950 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
2951 .features
[FEAT_7_0_EBX
] =
2952 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
2953 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
2954 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
2955 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
2957 .features
[FEAT_XSAVE
] =
2958 CPUID_XSAVE_XSAVEOPT
,
2959 .features
[FEAT_6_EAX
] =
2961 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
2962 MSR_VMX_BASIC_TRUE_CTLS
,
2963 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
2964 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
2965 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
2966 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
2967 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
2968 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
2969 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
2970 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
2971 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
2972 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
2973 .features
[FEAT_VMX_EXIT_CTLS
] =
2974 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
2975 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2976 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
2977 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
2978 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
2979 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
2980 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
2981 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
2982 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
2983 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
2984 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
2985 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
2986 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
2987 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
2988 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
2989 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
2990 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
2991 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
2992 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
2993 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
2994 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
2995 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
2996 .features
[FEAT_VMX_SECONDARY_CTLS
] =
2997 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2998 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
2999 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3000 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3001 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3002 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3003 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3004 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3005 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3006 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3007 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3008 .xlevel
= 0x80000008,
3009 .model_id
= "Intel Core Processor (Broadwell)",
3010 .versions
= (X86CPUVersionDefinition
[]) {
3014 .alias
= "Broadwell-noTSX",
3015 .props
= (PropValue
[]) {
3018 { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
3019 { /* end of list */ }
3024 .alias
= "Broadwell-IBRS",
3025 .props
= (PropValue
[]) {
3026 /* Restore TSX features removed by -v2 above */
3029 { "spec-ctrl", "on" },
3031 "Intel Core Processor (Broadwell, IBRS)" },
3032 { /* end of list */ }
3037 .alias
= "Broadwell-noTSX-IBRS",
3038 .props
= (PropValue
[]) {
3041 /* spec-ctrl was already enabled by -v3 above */
3043 "Intel Core Processor (Broadwell, no TSX, IBRS)" },
3044 { /* end of list */ }
3047 { /* end of list */ }
3051 .name
= "Skylake-Client",
3053 .vendor
= CPUID_VENDOR_INTEL
,
3057 .features
[FEAT_1_EDX
] =
3058 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3059 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3060 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3061 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3062 CPUID_DE
| CPUID_FP87
,
3063 .features
[FEAT_1_ECX
] =
3064 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3065 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3066 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3067 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3068 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3069 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3070 .features
[FEAT_8000_0001_EDX
] =
3071 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_NX
|
3073 .features
[FEAT_8000_0001_ECX
] =
3074 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3075 .features
[FEAT_7_0_EBX
] =
3076 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3077 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3078 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3079 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3081 /* XSAVES is added in version 4 */
3082 .features
[FEAT_XSAVE
] =
3083 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3084 CPUID_XSAVE_XGETBV1
,
3085 .features
[FEAT_6_EAX
] =
3087 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3088 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3089 MSR_VMX_BASIC_TRUE_CTLS
,
3090 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3091 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3092 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3093 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3094 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3095 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3096 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3097 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3098 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3099 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3100 .features
[FEAT_VMX_EXIT_CTLS
] =
3101 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3102 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3103 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3104 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3105 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3106 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3107 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3108 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3109 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3110 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
,
3111 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3112 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3113 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3114 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3115 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3116 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3117 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3118 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3119 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3120 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3121 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3122 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3123 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3124 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3125 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3126 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3127 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3128 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3129 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3130 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3131 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3132 .xlevel
= 0x80000008,
3133 .model_id
= "Intel Core Processor (Skylake)",
3134 .versions
= (X86CPUVersionDefinition
[]) {
3138 .alias
= "Skylake-Client-IBRS",
3139 .props
= (PropValue
[]) {
3140 { "spec-ctrl", "on" },
3142 "Intel Core Processor (Skylake, IBRS)" },
3143 { /* end of list */ }
3148 .alias
= "Skylake-Client-noTSX-IBRS",
3149 .props
= (PropValue
[]) {
3153 "Intel Core Processor (Skylake, IBRS, no TSX)" },
3154 { /* end of list */ }
3159 .note
= "IBRS, XSAVES, no TSX",
3160 .props
= (PropValue
[]) {
3162 { "vmx-xsaves", "on" },
3163 { /* end of list */ }
3166 { /* end of list */ }
3170 .name
= "Skylake-Server",
3172 .vendor
= CPUID_VENDOR_INTEL
,
3176 .features
[FEAT_1_EDX
] =
3177 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3178 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3179 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3180 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3181 CPUID_DE
| CPUID_FP87
,
3182 .features
[FEAT_1_ECX
] =
3183 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3184 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3185 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3186 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3187 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3188 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3189 .features
[FEAT_8000_0001_EDX
] =
3190 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3191 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3192 .features
[FEAT_8000_0001_ECX
] =
3193 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3194 .features
[FEAT_7_0_EBX
] =
3195 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3196 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3197 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3198 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3199 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3200 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3201 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3202 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3203 .features
[FEAT_7_0_ECX
] =
3205 /* XSAVES is added in version 5 */
3206 .features
[FEAT_XSAVE
] =
3207 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3208 CPUID_XSAVE_XGETBV1
,
3209 .features
[FEAT_6_EAX
] =
3211 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3212 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3213 MSR_VMX_BASIC_TRUE_CTLS
,
3214 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3215 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3216 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3217 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3218 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3219 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3220 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3221 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3222 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3223 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3224 .features
[FEAT_VMX_EXIT_CTLS
] =
3225 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3226 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3227 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3228 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3229 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3230 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3231 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3232 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3233 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3234 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3235 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3236 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3237 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3238 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3239 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3240 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3241 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3242 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3243 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3244 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3245 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3246 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3247 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3248 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3249 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3250 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3251 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3252 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3253 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3254 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3255 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3256 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3257 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3258 .xlevel
= 0x80000008,
3259 .model_id
= "Intel Xeon Processor (Skylake)",
3260 .versions
= (X86CPUVersionDefinition
[]) {
3264 .alias
= "Skylake-Server-IBRS",
3265 .props
= (PropValue
[]) {
3266 /* clflushopt was not added to Skylake-Server-IBRS */
3267 /* TODO: add -v3 including clflushopt */
3268 { "clflushopt", "off" },
3269 { "spec-ctrl", "on" },
3271 "Intel Xeon Processor (Skylake, IBRS)" },
3272 { /* end of list */ }
3277 .alias
= "Skylake-Server-noTSX-IBRS",
3278 .props
= (PropValue
[]) {
3282 "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3283 { /* end of list */ }
3288 .props
= (PropValue
[]) {
3289 { "vmx-eptp-switching", "on" },
3290 { /* end of list */ }
3295 .note
= "IBRS, XSAVES, EPT switching, no TSX",
3296 .props
= (PropValue
[]) {
3298 { "vmx-xsaves", "on" },
3299 { /* end of list */ }
3302 { /* end of list */ }
3306 .name
= "Cascadelake-Server",
3308 .vendor
= CPUID_VENDOR_INTEL
,
3312 .features
[FEAT_1_EDX
] =
3313 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3314 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3315 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3316 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3317 CPUID_DE
| CPUID_FP87
,
3318 .features
[FEAT_1_ECX
] =
3319 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3320 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3321 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3322 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3323 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3324 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3325 .features
[FEAT_8000_0001_EDX
] =
3326 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3327 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3328 .features
[FEAT_8000_0001_ECX
] =
3329 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3330 .features
[FEAT_7_0_EBX
] =
3331 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3332 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3333 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3334 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3335 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3336 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3337 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3338 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3339 .features
[FEAT_7_0_ECX
] =
3341 CPUID_7_0_ECX_AVX512VNNI
,
3342 .features
[FEAT_7_0_EDX
] =
3343 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3344 /* XSAVES is added in version 5 */
3345 .features
[FEAT_XSAVE
] =
3346 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3347 CPUID_XSAVE_XGETBV1
,
3348 .features
[FEAT_6_EAX
] =
3350 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3351 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3352 MSR_VMX_BASIC_TRUE_CTLS
,
3353 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3354 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3355 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3356 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3357 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3358 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3359 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3360 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3361 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3362 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3363 .features
[FEAT_VMX_EXIT_CTLS
] =
3364 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3365 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3366 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3367 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3368 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3369 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3370 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3371 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3372 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3373 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3374 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3375 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3376 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3377 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3378 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3379 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3380 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3381 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3382 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3383 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3384 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3385 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3386 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3387 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3388 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3389 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3390 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3391 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3392 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3393 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3394 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3395 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3396 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3397 .xlevel
= 0x80000008,
3398 .model_id
= "Intel Xeon Processor (Cascadelake)",
3399 .versions
= (X86CPUVersionDefinition
[]) {
3402 .note
= "ARCH_CAPABILITIES",
3403 .props
= (PropValue
[]) {
3404 { "arch-capabilities", "on" },
3405 { "rdctl-no", "on" },
3406 { "ibrs-all", "on" },
3407 { "skip-l1dfl-vmentry", "on" },
3409 { /* end of list */ }
3413 .alias
= "Cascadelake-Server-noTSX",
3414 .note
= "ARCH_CAPABILITIES, no TSX",
3415 .props
= (PropValue
[]) {
3418 { /* end of list */ }
3422 .note
= "ARCH_CAPABILITIES, no TSX",
3423 .props
= (PropValue
[]) {
3424 { "vmx-eptp-switching", "on" },
3425 { /* end of list */ }
3429 .note
= "ARCH_CAPABILITIES, EPT switching, XSAVES, no TSX",
3430 .props
= (PropValue
[]) {
3432 { "vmx-xsaves", "on" },
3433 { /* end of list */ }
3436 { /* end of list */ }
3440 .name
= "Cooperlake",
3442 .vendor
= CPUID_VENDOR_INTEL
,
3446 .features
[FEAT_1_EDX
] =
3447 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3448 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3449 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3450 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3451 CPUID_DE
| CPUID_FP87
,
3452 .features
[FEAT_1_ECX
] =
3453 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3454 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3455 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3456 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3457 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3458 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3459 .features
[FEAT_8000_0001_EDX
] =
3460 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3461 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3462 .features
[FEAT_8000_0001_ECX
] =
3463 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3464 .features
[FEAT_7_0_EBX
] =
3465 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3466 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3467 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3468 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3469 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3470 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3471 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3472 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3473 .features
[FEAT_7_0_ECX
] =
3475 CPUID_7_0_ECX_AVX512VNNI
,
3476 .features
[FEAT_7_0_EDX
] =
3477 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_STIBP
|
3478 CPUID_7_0_EDX_SPEC_CTRL_SSBD
| CPUID_7_0_EDX_ARCH_CAPABILITIES
,
3479 .features
[FEAT_ARCH_CAPABILITIES
] =
3480 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_IBRS_ALL
|
3481 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
| MSR_ARCH_CAP_MDS_NO
|
3482 MSR_ARCH_CAP_PSCHANGE_MC_NO
| MSR_ARCH_CAP_TAA_NO
,
3483 .features
[FEAT_7_1_EAX
] =
3484 CPUID_7_1_EAX_AVX512_BF16
,
3485 /* XSAVES is added in version 2 */
3486 .features
[FEAT_XSAVE
] =
3487 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3488 CPUID_XSAVE_XGETBV1
,
3489 .features
[FEAT_6_EAX
] =
3491 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3492 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3493 MSR_VMX_BASIC_TRUE_CTLS
,
3494 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3495 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3496 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3497 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3498 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3499 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3500 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3501 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3502 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3503 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3504 .features
[FEAT_VMX_EXIT_CTLS
] =
3505 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3506 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3507 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3508 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3509 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3510 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3511 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3512 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3513 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3514 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3515 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3516 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3517 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3518 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3519 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3520 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3521 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3522 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3523 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3524 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3525 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3526 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3527 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3528 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3529 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3530 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3531 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3532 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3533 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3534 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3535 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3536 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3537 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3538 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3539 .xlevel
= 0x80000008,
3540 .model_id
= "Intel Xeon Processor (Cooperlake)",
3541 .versions
= (X86CPUVersionDefinition
[]) {
3545 .props
= (PropValue
[]) {
3547 { "vmx-xsaves", "on" },
3548 { /* end of list */ }
3551 { /* end of list */ }
3555 .name
= "Icelake-Server",
3557 .vendor
= CPUID_VENDOR_INTEL
,
3561 .features
[FEAT_1_EDX
] =
3562 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
3563 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
3564 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
3565 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
3566 CPUID_DE
| CPUID_FP87
,
3567 .features
[FEAT_1_ECX
] =
3568 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
3569 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
3570 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
3571 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
3572 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
3573 CPUID_EXT_PCID
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3574 .features
[FEAT_8000_0001_EDX
] =
3575 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3576 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
3577 .features
[FEAT_8000_0001_ECX
] =
3578 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3579 .features
[FEAT_8000_0008_EBX
] =
3580 CPUID_8000_0008_EBX_WBNOINVD
,
3581 .features
[FEAT_7_0_EBX
] =
3582 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
|
3583 CPUID_7_0_EBX_HLE
| CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
|
3584 CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
|
3585 CPUID_7_0_EBX_RTM
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
3586 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLWB
|
3587 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3588 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512CD
|
3589 CPUID_7_0_EBX_AVX512VL
| CPUID_7_0_EBX_CLFLUSHOPT
,
3590 .features
[FEAT_7_0_ECX
] =
3591 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
3592 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
3593 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
3594 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
3595 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
,
3596 .features
[FEAT_7_0_EDX
] =
3597 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3598 /* XSAVES is added in version 5 */
3599 .features
[FEAT_XSAVE
] =
3600 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3601 CPUID_XSAVE_XGETBV1
,
3602 .features
[FEAT_6_EAX
] =
3604 /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3605 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3606 MSR_VMX_BASIC_TRUE_CTLS
,
3607 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3608 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3609 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3610 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3611 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3612 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3613 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3614 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3615 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3616 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3617 .features
[FEAT_VMX_EXIT_CTLS
] =
3618 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3619 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3620 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3621 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3622 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3623 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3624 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3625 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3626 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3627 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3628 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3629 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3630 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3631 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3632 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3633 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3634 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3635 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3636 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3637 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3638 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3639 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3640 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3641 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3642 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3643 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3644 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3645 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3646 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3647 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3648 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3649 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
,
3650 .xlevel
= 0x80000008,
3651 .model_id
= "Intel Xeon Processor (Icelake)",
3652 .versions
= (X86CPUVersionDefinition
[]) {
3657 .alias
= "Icelake-Server-noTSX",
3658 .props
= (PropValue
[]) {
3661 { /* end of list */ }
3666 .props
= (PropValue
[]) {
3667 { "arch-capabilities", "on" },
3668 { "rdctl-no", "on" },
3669 { "ibrs-all", "on" },
3670 { "skip-l1dfl-vmentry", "on" },
3672 { "pschange-mc-no", "on" },
3674 { /* end of list */ }
3679 .props
= (PropValue
[]) {
3681 { "avx512ifma", "on" },
3684 { "vmx-rdseed-exit", "on" },
3685 { "vmx-pml", "on" },
3686 { "vmx-eptp-switching", "on" },
3688 { /* end of list */ }
3694 .props
= (PropValue
[]) {
3696 { "vmx-xsaves", "on" },
3697 { /* end of list */ }
3702 .note
= "5-level EPT",
3703 .props
= (PropValue
[]) {
3704 { "vmx-page-walk-5", "on" },
3705 { /* end of list */ }
3708 { /* end of list */ }
3712 .name
= "SapphireRapids",
3714 .vendor
= CPUID_VENDOR_INTEL
,
3719 * please keep the ascending order so that we can have a clear view of
3720 * bit position of each feature.
3722 .features
[FEAT_1_EDX
] =
3723 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
| CPUID_TSC
|
3724 CPUID_MSR
| CPUID_PAE
| CPUID_MCE
| CPUID_CX8
| CPUID_APIC
|
3725 CPUID_SEP
| CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3726 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
| CPUID_MMX
| CPUID_FXSR
|
3727 CPUID_SSE
| CPUID_SSE2
,
3728 .features
[FEAT_1_ECX
] =
3729 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSSE3
|
3730 CPUID_EXT_FMA
| CPUID_EXT_CX16
| CPUID_EXT_PCID
| CPUID_EXT_SSE41
|
3731 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3732 CPUID_EXT_POPCNT
| CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_AES
|
3733 CPUID_EXT_XSAVE
| CPUID_EXT_AVX
| CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
3734 .features
[FEAT_8000_0001_EDX
] =
3735 CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
| CPUID_EXT2_PDPE1GB
|
3736 CPUID_EXT2_RDTSCP
| CPUID_EXT2_LM
,
3737 .features
[FEAT_8000_0001_ECX
] =
3738 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_ABM
| CPUID_EXT3_3DNOWPREFETCH
,
3739 .features
[FEAT_8000_0008_EBX
] =
3740 CPUID_8000_0008_EBX_WBNOINVD
,
3741 .features
[FEAT_7_0_EBX
] =
3742 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_HLE
|
3743 CPUID_7_0_EBX_AVX2
| CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
|
3744 CPUID_7_0_EBX_ERMS
| CPUID_7_0_EBX_INVPCID
| CPUID_7_0_EBX_RTM
|
3745 CPUID_7_0_EBX_AVX512F
| CPUID_7_0_EBX_AVX512DQ
|
3746 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
|
3747 CPUID_7_0_EBX_AVX512IFMA
| CPUID_7_0_EBX_CLFLUSHOPT
|
3748 CPUID_7_0_EBX_CLWB
| CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_SHA_NI
|
3749 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512VL
,
3750 .features
[FEAT_7_0_ECX
] =
3751 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
3752 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
3753 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
3754 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
3755 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
|
3756 CPUID_7_0_ECX_RDPID
| CPUID_7_0_ECX_BUS_LOCK_DETECT
,
3757 .features
[FEAT_7_0_EDX
] =
3758 CPUID_7_0_EDX_FSRM
| CPUID_7_0_EDX_SERIALIZE
|
3759 CPUID_7_0_EDX_TSX_LDTRK
| CPUID_7_0_EDX_AMX_BF16
|
3760 CPUID_7_0_EDX_AVX512_FP16
| CPUID_7_0_EDX_AMX_TILE
|
3761 CPUID_7_0_EDX_AMX_INT8
| CPUID_7_0_EDX_SPEC_CTRL
|
3762 CPUID_7_0_EDX_ARCH_CAPABILITIES
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3763 .features
[FEAT_ARCH_CAPABILITIES
] =
3764 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_IBRS_ALL
|
3765 MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
| MSR_ARCH_CAP_MDS_NO
|
3766 MSR_ARCH_CAP_PSCHANGE_MC_NO
| MSR_ARCH_CAP_TAA_NO
,
3767 .features
[FEAT_XSAVE
] =
3768 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
3769 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
| CPUID_D_1_EAX_XFD
,
3770 .features
[FEAT_6_EAX
] =
3772 .features
[FEAT_7_1_EAX
] =
3773 CPUID_7_1_EAX_AVX_VNNI
| CPUID_7_1_EAX_AVX512_BF16
|
3774 CPUID_7_1_EAX_FZRM
| CPUID_7_1_EAX_FSRS
| CPUID_7_1_EAX_FSRC
,
3775 .features
[FEAT_VMX_BASIC
] =
3776 MSR_VMX_BASIC_INS_OUTS
| MSR_VMX_BASIC_TRUE_CTLS
,
3777 .features
[FEAT_VMX_ENTRY_CTLS
] =
3778 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_IA32E_MODE
|
3779 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
|
3780 VMX_VM_ENTRY_LOAD_IA32_PAT
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3781 .features
[FEAT_VMX_EPT_VPID_CAPS
] =
3782 MSR_VMX_EPT_EXECONLY
|
3783 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_PAGE_WALK_LENGTH_5
|
3784 MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
| MSR_VMX_EPT_1GB
|
3785 MSR_VMX_EPT_INVEPT
| MSR_VMX_EPT_AD_BITS
|
3786 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3787 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3788 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
|
3789 MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3790 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
,
3791 .features
[FEAT_VMX_EXIT_CTLS
] =
3792 VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3793 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3794 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_IA32_PAT
|
3795 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3796 VMX_VM_EXIT_LOAD_IA32_EFER
| VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3797 .features
[FEAT_VMX_MISC
] =
3798 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_ACTIVITY_HLT
|
3799 MSR_VMX_MISC_VMWRITE_VMEXIT
,
3800 .features
[FEAT_VMX_PINBASED_CTLS
] =
3801 VMX_PIN_BASED_EXT_INTR_MASK
| VMX_PIN_BASED_NMI_EXITING
|
3802 VMX_PIN_BASED_VIRTUAL_NMIS
| VMX_PIN_BASED_VMX_PREEMPTION_TIMER
|
3803 VMX_PIN_BASED_POSTED_INTR
,
3804 .features
[FEAT_VMX_PROCBASED_CTLS
] =
3805 VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3806 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3807 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3808 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3809 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3810 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3811 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_VIRTUAL_NMI_PENDING
|
3812 VMX_CPU_BASED_MOV_DR_EXITING
| VMX_CPU_BASED_UNCOND_IO_EXITING
|
3813 VMX_CPU_BASED_USE_IO_BITMAPS
| VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3814 VMX_CPU_BASED_USE_MSR_BITMAPS
| VMX_CPU_BASED_MONITOR_EXITING
|
3815 VMX_CPU_BASED_PAUSE_EXITING
|
3816 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3817 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3818 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3819 VMX_SECONDARY_EXEC_ENABLE_EPT
| VMX_SECONDARY_EXEC_DESC
|
3820 VMX_SECONDARY_EXEC_RDTSCP
|
3821 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3822 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_WBINVD_EXITING
|
3823 VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3824 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3825 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3826 VMX_SECONDARY_EXEC_RDRAND_EXITING
|
3827 VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3828 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3829 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
|
3830 VMX_SECONDARY_EXEC_XSAVES
,
3831 .features
[FEAT_VMX_VMFUNC
] =
3832 MSR_VMX_VMFUNC_EPT_SWITCHING
,
3833 .xlevel
= 0x80000008,
3834 .model_id
= "Intel Xeon Processor (SapphireRapids)",
3835 .versions
= (X86CPUVersionDefinition
[]) {
3837 { /* end of list */ },
3841 .name
= "Denverton",
3843 .vendor
= CPUID_VENDOR_INTEL
,
3847 .features
[FEAT_1_EDX
] =
3848 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
| CPUID_TSC
|
3849 CPUID_MSR
| CPUID_PAE
| CPUID_MCE
| CPUID_CX8
| CPUID_APIC
|
3850 CPUID_SEP
| CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3851 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
| CPUID_MMX
| CPUID_FXSR
|
3852 CPUID_SSE
| CPUID_SSE2
,
3853 .features
[FEAT_1_ECX
] =
3854 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_MONITOR
|
3855 CPUID_EXT_SSSE3
| CPUID_EXT_CX16
| CPUID_EXT_SSE41
|
3856 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3857 CPUID_EXT_POPCNT
| CPUID_EXT_TSC_DEADLINE_TIMER
|
3858 CPUID_EXT_AES
| CPUID_EXT_XSAVE
| CPUID_EXT_RDRAND
,
3859 .features
[FEAT_8000_0001_EDX
] =
3860 CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
| CPUID_EXT2_PDPE1GB
|
3861 CPUID_EXT2_RDTSCP
| CPUID_EXT2_LM
,
3862 .features
[FEAT_8000_0001_ECX
] =
3863 CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
3864 .features
[FEAT_7_0_EBX
] =
3865 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_ERMS
|
3866 CPUID_7_0_EBX_MPX
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_SMAP
|
3867 CPUID_7_0_EBX_CLFLUSHOPT
| CPUID_7_0_EBX_SHA_NI
,
3868 .features
[FEAT_7_0_EDX
] =
3869 CPUID_7_0_EDX_SPEC_CTRL
| CPUID_7_0_EDX_ARCH_CAPABILITIES
|
3870 CPUID_7_0_EDX_SPEC_CTRL_SSBD
,
3871 /* XSAVES is added in version 3 */
3872 .features
[FEAT_XSAVE
] =
3873 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
| CPUID_XSAVE_XGETBV1
,
3874 .features
[FEAT_6_EAX
] =
3876 .features
[FEAT_ARCH_CAPABILITIES
] =
3877 MSR_ARCH_CAP_RDCL_NO
| MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY
,
3878 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
3879 MSR_VMX_BASIC_TRUE_CTLS
,
3880 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
3881 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
3882 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
3883 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
3884 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
3885 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
3886 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
3887 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
3888 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
3889 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
3890 .features
[FEAT_VMX_EXIT_CTLS
] =
3891 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
3892 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
3893 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
3894 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
3895 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
3896 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
3897 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
3898 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
3899 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
3900 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
3901 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
3902 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
3903 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
3904 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
3905 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
3906 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
3907 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
3908 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
3909 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
3910 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
3911 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
3912 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
3913 .features
[FEAT_VMX_SECONDARY_CTLS
] =
3914 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3915 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
3916 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
3917 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3918 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3919 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3920 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3921 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
3922 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
3923 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
3924 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
3925 .xlevel
= 0x80000008,
3926 .model_id
= "Intel Atom Processor (Denverton)",
3927 .versions
= (X86CPUVersionDefinition
[]) {
3931 .note
= "no MPX, no MONITOR",
3932 .props
= (PropValue
[]) {
3933 { "monitor", "off" },
3935 { /* end of list */ },
3940 .note
= "XSAVES, no MPX, no MONITOR",
3941 .props
= (PropValue
[]) {
3943 { "vmx-xsaves", "on" },
3944 { /* end of list */ },
3947 { /* end of list */ },
3951 .name
= "Snowridge",
3953 .vendor
= CPUID_VENDOR_INTEL
,
3957 .features
[FEAT_1_EDX
] =
3958 /* missing: CPUID_PN CPUID_IA64 */
3959 /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3960 CPUID_FP87
| CPUID_VME
| CPUID_DE
| CPUID_PSE
|
3961 CPUID_TSC
| CPUID_MSR
| CPUID_PAE
| CPUID_MCE
|
3962 CPUID_CX8
| CPUID_APIC
| CPUID_SEP
|
3963 CPUID_MTRR
| CPUID_PGE
| CPUID_MCA
| CPUID_CMOV
|
3964 CPUID_PAT
| CPUID_PSE36
| CPUID_CLFLUSH
|
3966 CPUID_FXSR
| CPUID_SSE
| CPUID_SSE2
,
3967 .features
[FEAT_1_ECX
] =
3968 CPUID_EXT_SSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_MONITOR
|
3972 CPUID_EXT_SSE42
| CPUID_EXT_X2APIC
| CPUID_EXT_MOVBE
|
3974 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_AES
| CPUID_EXT_XSAVE
|
3976 .features
[FEAT_8000_0001_EDX
] =
3977 CPUID_EXT2_SYSCALL
|
3979 CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
3981 .features
[FEAT_8000_0001_ECX
] =
3982 CPUID_EXT3_LAHF_LM
|
3983 CPUID_EXT3_3DNOWPREFETCH
,
3984 .features
[FEAT_7_0_EBX
] =
3985 CPUID_7_0_EBX_FSGSBASE
|
3986 CPUID_7_0_EBX_SMEP
|
3987 CPUID_7_0_EBX_ERMS
|
3988 CPUID_7_0_EBX_MPX
| /* missing bits 13, 15 */
3989 CPUID_7_0_EBX_RDSEED
|
3990 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
3991 CPUID_7_0_EBX_CLWB
|
3992 CPUID_7_0_EBX_SHA_NI
,
3993 .features
[FEAT_7_0_ECX
] =
3994 CPUID_7_0_ECX_UMIP
|
3996 CPUID_7_0_ECX_GFNI
|
3997 CPUID_7_0_ECX_MOVDIRI
| CPUID_7_0_ECX_CLDEMOTE
|
3998 CPUID_7_0_ECX_MOVDIR64B
,
3999 .features
[FEAT_7_0_EDX
] =
4000 CPUID_7_0_EDX_SPEC_CTRL
|
4001 CPUID_7_0_EDX_ARCH_CAPABILITIES
| CPUID_7_0_EDX_SPEC_CTRL_SSBD
|
4002 CPUID_7_0_EDX_CORE_CAPABILITY
,
4003 .features
[FEAT_CORE_CAPABILITY
] =
4004 MSR_CORE_CAP_SPLIT_LOCK_DETECT
,
4005 /* XSAVES is added in version 3 */
4006 .features
[FEAT_XSAVE
] =
4007 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4008 CPUID_XSAVE_XGETBV1
,
4009 .features
[FEAT_6_EAX
] =
4011 .features
[FEAT_VMX_BASIC
] = MSR_VMX_BASIC_INS_OUTS
|
4012 MSR_VMX_BASIC_TRUE_CTLS
,
4013 .features
[FEAT_VMX_ENTRY_CTLS
] = VMX_VM_ENTRY_IA32E_MODE
|
4014 VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VMX_VM_ENTRY_LOAD_IA32_PAT
|
4015 VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS
| VMX_VM_ENTRY_LOAD_IA32_EFER
,
4016 .features
[FEAT_VMX_EPT_VPID_CAPS
] = MSR_VMX_EPT_EXECONLY
|
4017 MSR_VMX_EPT_PAGE_WALK_LENGTH_4
| MSR_VMX_EPT_WB
| MSR_VMX_EPT_2MB
|
4018 MSR_VMX_EPT_1GB
| MSR_VMX_EPT_INVEPT
|
4019 MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT
| MSR_VMX_EPT_INVEPT_ALL_CONTEXT
|
4020 MSR_VMX_EPT_INVVPID
| MSR_VMX_EPT_INVVPID_SINGLE_ADDR
|
4021 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT
| MSR_VMX_EPT_INVVPID_ALL_CONTEXT
|
4022 MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS
| MSR_VMX_EPT_AD_BITS
,
4023 .features
[FEAT_VMX_EXIT_CTLS
] =
4024 VMX_VM_EXIT_ACK_INTR_ON_EXIT
| VMX_VM_EXIT_SAVE_DEBUG_CONTROLS
|
4025 VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
4026 VMX_VM_EXIT_LOAD_IA32_PAT
| VMX_VM_EXIT_LOAD_IA32_EFER
|
4027 VMX_VM_EXIT_SAVE_IA32_PAT
| VMX_VM_EXIT_SAVE_IA32_EFER
|
4028 VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
,
4029 .features
[FEAT_VMX_MISC
] = MSR_VMX_MISC_ACTIVITY_HLT
|
4030 MSR_VMX_MISC_STORE_LMA
| MSR_VMX_MISC_VMWRITE_VMEXIT
,
4031 .features
[FEAT_VMX_PINBASED_CTLS
] = VMX_PIN_BASED_EXT_INTR_MASK
|
4032 VMX_PIN_BASED_NMI_EXITING
| VMX_PIN_BASED_VIRTUAL_NMIS
|
4033 VMX_PIN_BASED_VMX_PREEMPTION_TIMER
| VMX_PIN_BASED_POSTED_INTR
,
4034 .features
[FEAT_VMX_PROCBASED_CTLS
] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING
|
4035 VMX_CPU_BASED_USE_TSC_OFFSETING
| VMX_CPU_BASED_HLT_EXITING
|
4036 VMX_CPU_BASED_INVLPG_EXITING
| VMX_CPU_BASED_MWAIT_EXITING
|
4037 VMX_CPU_BASED_RDPMC_EXITING
| VMX_CPU_BASED_RDTSC_EXITING
|
4038 VMX_CPU_BASED_CR8_LOAD_EXITING
| VMX_CPU_BASED_CR8_STORE_EXITING
|
4039 VMX_CPU_BASED_TPR_SHADOW
| VMX_CPU_BASED_MOV_DR_EXITING
|
4040 VMX_CPU_BASED_UNCOND_IO_EXITING
| VMX_CPU_BASED_USE_IO_BITMAPS
|
4041 VMX_CPU_BASED_MONITOR_EXITING
| VMX_CPU_BASED_PAUSE_EXITING
|
4042 VMX_CPU_BASED_VIRTUAL_NMI_PENDING
| VMX_CPU_BASED_USE_MSR_BITMAPS
|
4043 VMX_CPU_BASED_CR3_LOAD_EXITING
| VMX_CPU_BASED_CR3_STORE_EXITING
|
4044 VMX_CPU_BASED_MONITOR_TRAP_FLAG
|
4045 VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
,
4046 .features
[FEAT_VMX_SECONDARY_CTLS
] =
4047 VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
4048 VMX_SECONDARY_EXEC_WBINVD_EXITING
| VMX_SECONDARY_EXEC_ENABLE_EPT
|
4049 VMX_SECONDARY_EXEC_DESC
| VMX_SECONDARY_EXEC_RDTSCP
|
4050 VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
4051 VMX_SECONDARY_EXEC_ENABLE_VPID
| VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST
|
4052 VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4053 VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
4054 VMX_SECONDARY_EXEC_RDRAND_EXITING
| VMX_SECONDARY_EXEC_ENABLE_INVPCID
|
4055 VMX_SECONDARY_EXEC_ENABLE_VMFUNC
| VMX_SECONDARY_EXEC_SHADOW_VMCS
|
4056 VMX_SECONDARY_EXEC_RDSEED_EXITING
| VMX_SECONDARY_EXEC_ENABLE_PML
,
4057 .features
[FEAT_VMX_VMFUNC
] = MSR_VMX_VMFUNC_EPT_SWITCHING
,
4058 .xlevel
= 0x80000008,
4059 .model_id
= "Intel Atom Processor (SnowRidge)",
4060 .versions
= (X86CPUVersionDefinition
[]) {
4064 .props
= (PropValue
[]) {
4066 { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
4067 { /* end of list */ },
4072 .note
= "XSAVES, no MPX",
4073 .props
= (PropValue
[]) {
4075 { "vmx-xsaves", "on" },
4076 { /* end of list */ },
4081 .note
= "no split lock detect, no core-capability",
4082 .props
= (PropValue
[]) {
4083 { "split-lock-detect", "off" },
4084 { "core-capability", "off" },
4085 { /* end of list */ },
4088 { /* end of list */ },
4092 .name
= "KnightsMill",
4094 .vendor
= CPUID_VENDOR_INTEL
,
4098 .features
[FEAT_1_EDX
] =
4099 CPUID_VME
| CPUID_SS
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
|
4100 CPUID_MMX
| CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
|
4101 CPUID_MCA
| CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
|
4102 CPUID_CX8
| CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
|
4103 CPUID_PSE
| CPUID_DE
| CPUID_FP87
,
4104 .features
[FEAT_1_ECX
] =
4105 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
4106 CPUID_EXT_POPCNT
| CPUID_EXT_X2APIC
| CPUID_EXT_SSE42
|
4107 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_SSSE3
|
4108 CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
4109 CPUID_EXT_TSC_DEADLINE_TIMER
| CPUID_EXT_FMA
| CPUID_EXT_MOVBE
|
4110 CPUID_EXT_F16C
| CPUID_EXT_RDRAND
,
4111 .features
[FEAT_8000_0001_EDX
] =
4112 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
|
4113 CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
4114 .features
[FEAT_8000_0001_ECX
] =
4115 CPUID_EXT3_ABM
| CPUID_EXT3_LAHF_LM
| CPUID_EXT3_3DNOWPREFETCH
,
4116 .features
[FEAT_7_0_EBX
] =
4117 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4118 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
|
4119 CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_AVX512F
|
4120 CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_AVX512PF
|
4121 CPUID_7_0_EBX_AVX512ER
,
4122 .features
[FEAT_7_0_ECX
] =
4123 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
,
4124 .features
[FEAT_7_0_EDX
] =
4125 CPUID_7_0_EDX_AVX512_4VNNIW
| CPUID_7_0_EDX_AVX512_4FMAPS
,
4126 .features
[FEAT_XSAVE
] =
4127 CPUID_XSAVE_XSAVEOPT
,
4128 .features
[FEAT_6_EAX
] =
4130 .xlevel
= 0x80000008,
4131 .model_id
= "Intel Xeon Phi Processor (Knights Mill)",
4134 .name
= "Opteron_G1",
4136 .vendor
= CPUID_VENDOR_AMD
,
4140 .features
[FEAT_1_EDX
] =
4141 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4142 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4143 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4144 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4145 CPUID_DE
| CPUID_FP87
,
4146 .features
[FEAT_1_ECX
] =
4148 .features
[FEAT_8000_0001_EDX
] =
4149 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
4150 .xlevel
= 0x80000008,
4151 .model_id
= "AMD Opteron 240 (Gen 1 Class Opteron)",
4154 .name
= "Opteron_G2",
4156 .vendor
= CPUID_VENDOR_AMD
,
4160 .features
[FEAT_1_EDX
] =
4161 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4162 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4163 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4164 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4165 CPUID_DE
| CPUID_FP87
,
4166 .features
[FEAT_1_ECX
] =
4167 CPUID_EXT_CX16
| CPUID_EXT_SSE3
,
4168 .features
[FEAT_8000_0001_EDX
] =
4169 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
,
4170 .features
[FEAT_8000_0001_ECX
] =
4171 CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
4172 .xlevel
= 0x80000008,
4173 .model_id
= "AMD Opteron 22xx (Gen 2 Class Opteron)",
4176 .name
= "Opteron_G3",
4178 .vendor
= CPUID_VENDOR_AMD
,
4182 .features
[FEAT_1_EDX
] =
4183 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4184 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4185 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4186 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4187 CPUID_DE
| CPUID_FP87
,
4188 .features
[FEAT_1_ECX
] =
4189 CPUID_EXT_POPCNT
| CPUID_EXT_CX16
| CPUID_EXT_MONITOR
|
4191 .features
[FEAT_8000_0001_EDX
] =
4192 CPUID_EXT2_LM
| CPUID_EXT2_NX
| CPUID_EXT2_SYSCALL
|
4194 .features
[FEAT_8000_0001_ECX
] =
4195 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
|
4196 CPUID_EXT3_ABM
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
,
4197 .xlevel
= 0x80000008,
4198 .model_id
= "AMD Opteron 23xx (Gen 3 Class Opteron)",
4201 .name
= "Opteron_G4",
4203 .vendor
= CPUID_VENDOR_AMD
,
4207 .features
[FEAT_1_EDX
] =
4208 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4209 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4210 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4211 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4212 CPUID_DE
| CPUID_FP87
,
4213 .features
[FEAT_1_ECX
] =
4214 CPUID_EXT_AVX
| CPUID_EXT_XSAVE
| CPUID_EXT_AES
|
4215 CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4216 CPUID_EXT_CX16
| CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
|
4218 .features
[FEAT_8000_0001_EDX
] =
4219 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
4220 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
4221 .features
[FEAT_8000_0001_ECX
] =
4222 CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
4223 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
4224 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
4226 .features
[FEAT_SVM
] =
4227 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4229 .xlevel
= 0x8000001A,
4230 .model_id
= "AMD Opteron 62xx class CPU",
4233 .name
= "Opteron_G5",
4235 .vendor
= CPUID_VENDOR_AMD
,
4239 .features
[FEAT_1_EDX
] =
4240 CPUID_VME
| CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
|
4241 CPUID_CLFLUSH
| CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
|
4242 CPUID_PGE
| CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
|
4243 CPUID_MCE
| CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
|
4244 CPUID_DE
| CPUID_FP87
,
4245 .features
[FEAT_1_ECX
] =
4246 CPUID_EXT_F16C
| CPUID_EXT_AVX
| CPUID_EXT_XSAVE
|
4247 CPUID_EXT_AES
| CPUID_EXT_POPCNT
| CPUID_EXT_SSE42
|
4248 CPUID_EXT_SSE41
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
4249 CPUID_EXT_SSSE3
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
4250 .features
[FEAT_8000_0001_EDX
] =
4251 CPUID_EXT2_LM
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_NX
|
4252 CPUID_EXT2_SYSCALL
| CPUID_EXT2_RDTSCP
,
4253 .features
[FEAT_8000_0001_ECX
] =
4254 CPUID_EXT3_TBM
| CPUID_EXT3_FMA4
| CPUID_EXT3_XOP
|
4255 CPUID_EXT3_3DNOWPREFETCH
| CPUID_EXT3_MISALIGNSSE
|
4256 CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
| CPUID_EXT3_SVM
|
4258 .features
[FEAT_SVM
] =
4259 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4261 .xlevel
= 0x8000001A,
4262 .model_id
= "AMD Opteron 63xx class CPU",
4267 .vendor
= CPUID_VENDOR_AMD
,
4271 .features
[FEAT_1_EDX
] =
4272 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4273 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4274 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4275 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4276 CPUID_VME
| CPUID_FP87
,
4277 .features
[FEAT_1_ECX
] =
4278 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4279 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4280 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4281 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4282 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
4283 .features
[FEAT_8000_0001_EDX
] =
4284 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4285 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4287 .features
[FEAT_8000_0001_ECX
] =
4288 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4289 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4290 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4292 .features
[FEAT_7_0_EBX
] =
4293 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4294 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4295 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4296 CPUID_7_0_EBX_SHA_NI
,
4297 .features
[FEAT_XSAVE
] =
4298 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4299 CPUID_XSAVE_XGETBV1
,
4300 .features
[FEAT_6_EAX
] =
4302 .features
[FEAT_SVM
] =
4303 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4304 .xlevel
= 0x8000001E,
4305 .model_id
= "AMD EPYC Processor",
4306 .cache_info
= &epyc_cache_info
,
4307 .versions
= (X86CPUVersionDefinition
[]) {
4311 .alias
= "EPYC-IBPB",
4312 .props
= (PropValue
[]) {
4315 "AMD EPYC Processor (with IBPB)" },
4316 { /* end of list */ }
4321 .props
= (PropValue
[]) {
4323 { "perfctr-core", "on" },
4325 { "xsaveerptr", "on" },
4328 "AMD EPYC Processor" },
4329 { /* end of list */ }
4334 .props
= (PropValue
[]) {
4336 "AMD EPYC-v4 Processor" },
4337 { /* end of list */ }
4339 .cache_info
= &epyc_v4_cache_info
4341 { /* end of list */ }
4347 .vendor
= CPUID_VENDOR_HYGON
,
4351 .features
[FEAT_1_EDX
] =
4352 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4353 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4354 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4355 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4356 CPUID_VME
| CPUID_FP87
,
4357 .features
[FEAT_1_ECX
] =
4358 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4359 CPUID_EXT_XSAVE
| CPUID_EXT_POPCNT
|
4360 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4361 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4362 CPUID_EXT_MONITOR
| CPUID_EXT_SSE3
,
4363 .features
[FEAT_8000_0001_EDX
] =
4364 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4365 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4367 .features
[FEAT_8000_0001_ECX
] =
4368 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4369 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4370 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4372 .features
[FEAT_8000_0008_EBX
] =
4373 CPUID_8000_0008_EBX_IBPB
,
4374 .features
[FEAT_7_0_EBX
] =
4375 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4376 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4377 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
,
4378 /* XSAVES is added in version 2 */
4379 .features
[FEAT_XSAVE
] =
4380 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4381 CPUID_XSAVE_XGETBV1
,
4382 .features
[FEAT_6_EAX
] =
4384 .features
[FEAT_SVM
] =
4385 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4386 .xlevel
= 0x8000001E,
4387 .model_id
= "Hygon Dhyana Processor",
4388 .cache_info
= &epyc_cache_info
,
4389 .versions
= (X86CPUVersionDefinition
[]) {
4393 .props
= (PropValue
[]) {
4395 { /* end of list */ }
4398 { /* end of list */ }
4402 .name
= "EPYC-Rome",
4404 .vendor
= CPUID_VENDOR_AMD
,
4408 .features
[FEAT_1_EDX
] =
4409 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4410 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4411 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4412 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4413 CPUID_VME
| CPUID_FP87
,
4414 .features
[FEAT_1_ECX
] =
4415 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4416 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4417 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4418 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4419 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
,
4420 .features
[FEAT_8000_0001_EDX
] =
4421 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4422 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4424 .features
[FEAT_8000_0001_ECX
] =
4425 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4426 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4427 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4428 CPUID_EXT3_TOPOEXT
| CPUID_EXT3_PERFCORE
,
4429 .features
[FEAT_8000_0008_EBX
] =
4430 CPUID_8000_0008_EBX_CLZERO
| CPUID_8000_0008_EBX_XSAVEERPTR
|
4431 CPUID_8000_0008_EBX_WBNOINVD
| CPUID_8000_0008_EBX_IBPB
|
4432 CPUID_8000_0008_EBX_STIBP
,
4433 .features
[FEAT_7_0_EBX
] =
4434 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4435 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4436 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4437 CPUID_7_0_EBX_SHA_NI
| CPUID_7_0_EBX_CLWB
,
4438 .features
[FEAT_7_0_ECX
] =
4439 CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_RDPID
,
4440 .features
[FEAT_XSAVE
] =
4441 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4442 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
,
4443 .features
[FEAT_6_EAX
] =
4445 .features
[FEAT_SVM
] =
4446 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
,
4447 .xlevel
= 0x8000001E,
4448 .model_id
= "AMD EPYC-Rome Processor",
4449 .cache_info
= &epyc_rome_cache_info
,
4450 .versions
= (X86CPUVersionDefinition
[]) {
4454 .props
= (PropValue
[]) {
4456 { "amd-ssbd", "on" },
4457 { /* end of list */ }
4462 .props
= (PropValue
[]) {
4464 "AMD EPYC-Rome-v3 Processor" },
4465 { /* end of list */ }
4467 .cache_info
= &epyc_rome_v3_cache_info
4469 { /* end of list */ }
4473 .name
= "EPYC-Milan",
4475 .vendor
= CPUID_VENDOR_AMD
,
4479 .features
[FEAT_1_EDX
] =
4480 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4481 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4482 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4483 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4484 CPUID_VME
| CPUID_FP87
,
4485 .features
[FEAT_1_ECX
] =
4486 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4487 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4488 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4489 CPUID_EXT_CX16
| CPUID_EXT_FMA
| CPUID_EXT_SSSE3
|
4490 CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
| CPUID_EXT_SSE3
|
4492 .features
[FEAT_8000_0001_EDX
] =
4493 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4494 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4496 .features
[FEAT_8000_0001_ECX
] =
4497 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4498 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4499 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4500 CPUID_EXT3_TOPOEXT
| CPUID_EXT3_PERFCORE
,
4501 .features
[FEAT_8000_0008_EBX
] =
4502 CPUID_8000_0008_EBX_CLZERO
| CPUID_8000_0008_EBX_XSAVEERPTR
|
4503 CPUID_8000_0008_EBX_WBNOINVD
| CPUID_8000_0008_EBX_IBPB
|
4504 CPUID_8000_0008_EBX_IBRS
| CPUID_8000_0008_EBX_STIBP
|
4505 CPUID_8000_0008_EBX_AMD_SSBD
,
4506 .features
[FEAT_7_0_EBX
] =
4507 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4508 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_RDSEED
|
4509 CPUID_7_0_EBX_ADX
| CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_CLFLUSHOPT
|
4510 CPUID_7_0_EBX_SHA_NI
| CPUID_7_0_EBX_CLWB
| CPUID_7_0_EBX_ERMS
|
4511 CPUID_7_0_EBX_INVPCID
,
4512 .features
[FEAT_7_0_ECX
] =
4513 CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_RDPID
| CPUID_7_0_ECX_PKU
,
4514 .features
[FEAT_7_0_EDX
] =
4516 .features
[FEAT_XSAVE
] =
4517 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4518 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
,
4519 .features
[FEAT_6_EAX
] =
4521 .features
[FEAT_SVM
] =
4522 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
| CPUID_SVM_SVME_ADDR_CHK
,
4523 .xlevel
= 0x8000001E,
4524 .model_id
= "AMD EPYC-Milan Processor",
4525 .cache_info
= &epyc_milan_cache_info
,
4526 .versions
= (X86CPUVersionDefinition
[]) {
4530 .props
= (PropValue
[]) {
4532 "AMD EPYC-Milan-v2 Processor" },
4534 { "vpclmulqdq", "on" },
4535 { "stibp-always-on", "on" },
4536 { "amd-psfd", "on" },
4537 { "no-nested-data-bp", "on" },
4538 { "lfence-always-serializing", "on" },
4539 { "null-sel-clr-base", "on" },
4540 { /* end of list */ }
4542 .cache_info
= &epyc_milan_v2_cache_info
4544 { /* end of list */ }
4548 .name
= "EPYC-Genoa",
4550 .vendor
= CPUID_VENDOR_AMD
,
4554 .features
[FEAT_1_EDX
] =
4555 CPUID_SSE2
| CPUID_SSE
| CPUID_FXSR
| CPUID_MMX
| CPUID_CLFLUSH
|
4556 CPUID_PSE36
| CPUID_PAT
| CPUID_CMOV
| CPUID_MCA
| CPUID_PGE
|
4557 CPUID_MTRR
| CPUID_SEP
| CPUID_APIC
| CPUID_CX8
| CPUID_MCE
|
4558 CPUID_PAE
| CPUID_MSR
| CPUID_TSC
| CPUID_PSE
| CPUID_DE
|
4559 CPUID_VME
| CPUID_FP87
,
4560 .features
[FEAT_1_ECX
] =
4561 CPUID_EXT_RDRAND
| CPUID_EXT_F16C
| CPUID_EXT_AVX
|
4562 CPUID_EXT_XSAVE
| CPUID_EXT_AES
| CPUID_EXT_POPCNT
|
4563 CPUID_EXT_MOVBE
| CPUID_EXT_SSE42
| CPUID_EXT_SSE41
|
4564 CPUID_EXT_PCID
| CPUID_EXT_CX16
| CPUID_EXT_FMA
|
4565 CPUID_EXT_SSSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_PCLMULQDQ
|
4567 .features
[FEAT_8000_0001_EDX
] =
4568 CPUID_EXT2_LM
| CPUID_EXT2_RDTSCP
| CPUID_EXT2_PDPE1GB
|
4569 CPUID_EXT2_FFXSR
| CPUID_EXT2_MMXEXT
| CPUID_EXT2_NX
|
4571 .features
[FEAT_8000_0001_ECX
] =
4572 CPUID_EXT3_OSVW
| CPUID_EXT3_3DNOWPREFETCH
|
4573 CPUID_EXT3_MISALIGNSSE
| CPUID_EXT3_SSE4A
| CPUID_EXT3_ABM
|
4574 CPUID_EXT3_CR8LEG
| CPUID_EXT3_SVM
| CPUID_EXT3_LAHF_LM
|
4575 CPUID_EXT3_TOPOEXT
| CPUID_EXT3_PERFCORE
,
4576 .features
[FEAT_8000_0008_EBX
] =
4577 CPUID_8000_0008_EBX_CLZERO
| CPUID_8000_0008_EBX_XSAVEERPTR
|
4578 CPUID_8000_0008_EBX_WBNOINVD
| CPUID_8000_0008_EBX_IBPB
|
4579 CPUID_8000_0008_EBX_IBRS
| CPUID_8000_0008_EBX_STIBP
|
4580 CPUID_8000_0008_EBX_STIBP_ALWAYS_ON
|
4581 CPUID_8000_0008_EBX_AMD_SSBD
| CPUID_8000_0008_EBX_AMD_PSFD
,
4582 .features
[FEAT_8000_0021_EAX
] =
4583 CPUID_8000_0021_EAX_No_NESTED_DATA_BP
|
4584 CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING
|
4585 CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE
|
4586 CPUID_8000_0021_EAX_AUTO_IBRS
,
4587 .features
[FEAT_7_0_EBX
] =
4588 CPUID_7_0_EBX_FSGSBASE
| CPUID_7_0_EBX_BMI1
| CPUID_7_0_EBX_AVX2
|
4589 CPUID_7_0_EBX_SMEP
| CPUID_7_0_EBX_BMI2
| CPUID_7_0_EBX_ERMS
|
4590 CPUID_7_0_EBX_INVPCID
| CPUID_7_0_EBX_AVX512F
|
4591 CPUID_7_0_EBX_AVX512DQ
| CPUID_7_0_EBX_RDSEED
| CPUID_7_0_EBX_ADX
|
4592 CPUID_7_0_EBX_SMAP
| CPUID_7_0_EBX_AVX512IFMA
|
4593 CPUID_7_0_EBX_CLFLUSHOPT
| CPUID_7_0_EBX_CLWB
|
4594 CPUID_7_0_EBX_AVX512CD
| CPUID_7_0_EBX_SHA_NI
|
4595 CPUID_7_0_EBX_AVX512BW
| CPUID_7_0_EBX_AVX512VL
,
4596 .features
[FEAT_7_0_ECX
] =
4597 CPUID_7_0_ECX_AVX512_VBMI
| CPUID_7_0_ECX_UMIP
| CPUID_7_0_ECX_PKU
|
4598 CPUID_7_0_ECX_AVX512_VBMI2
| CPUID_7_0_ECX_GFNI
|
4599 CPUID_7_0_ECX_VAES
| CPUID_7_0_ECX_VPCLMULQDQ
|
4600 CPUID_7_0_ECX_AVX512VNNI
| CPUID_7_0_ECX_AVX512BITALG
|
4601 CPUID_7_0_ECX_AVX512_VPOPCNTDQ
| CPUID_7_0_ECX_LA57
|
4602 CPUID_7_0_ECX_RDPID
,
4603 .features
[FEAT_7_0_EDX
] =
4605 .features
[FEAT_7_1_EAX
] =
4606 CPUID_7_1_EAX_AVX512_BF16
,
4607 .features
[FEAT_XSAVE
] =
4608 CPUID_XSAVE_XSAVEOPT
| CPUID_XSAVE_XSAVEC
|
4609 CPUID_XSAVE_XGETBV1
| CPUID_XSAVE_XSAVES
,
4610 .features
[FEAT_6_EAX
] =
4612 .features
[FEAT_SVM
] =
4613 CPUID_SVM_NPT
| CPUID_SVM_NRIPSAVE
| CPUID_SVM_VNMI
|
4614 CPUID_SVM_SVME_ADDR_CHK
,
4615 .xlevel
= 0x80000022,
4616 .model_id
= "AMD EPYC-Genoa Processor",
4617 .cache_info
= &epyc_genoa_cache_info
,
4622 * We resolve CPU model aliases using -v1 when using "-machine
4623 * none", but this is just for compatibility while libvirt isn't
4624 * adapted to resolve CPU model versions before creating VMs.
4625 * See "Runnability guarantee of CPU models" at
4626 * docs/about/deprecated.rst.
4628 X86CPUVersion default_cpu_version
= 1;
4630 void x86_cpu_set_default_version(X86CPUVersion version
)
4632 /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4633 assert(version
!= CPU_VERSION_AUTO
);
4634 default_cpu_version
= version
;
4637 static X86CPUVersion
x86_cpu_model_last_version(const X86CPUModel
*model
)
4640 const X86CPUVersionDefinition
*vdef
=
4641 x86_cpu_def_get_versions(model
->cpudef
);
4642 while (vdef
->version
) {
4649 /* Return the actual version being used for a specific CPU model */
4650 static X86CPUVersion
x86_cpu_model_resolve_version(const X86CPUModel
*model
)
4652 X86CPUVersion v
= model
->version
;
4653 if (v
== CPU_VERSION_AUTO
) {
4654 v
= default_cpu_version
;
4656 if (v
== CPU_VERSION_LATEST
) {
4657 return x86_cpu_model_last_version(model
);
4662 static Property max_x86_cpu_properties
[] = {
4663 DEFINE_PROP_BOOL("migratable", X86CPU
, migratable
, true),
4664 DEFINE_PROP_BOOL("host-cache-info", X86CPU
, cache_info_passthrough
, false),
4665 DEFINE_PROP_END_OF_LIST()
4668 static void max_x86_cpu_realize(DeviceState
*dev
, Error
**errp
)
4670 Object
*obj
= OBJECT(dev
);
4672 if (!object_property_get_int(obj
, "family", &error_abort
)) {
4673 if (X86_CPU(obj
)->env
.features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
4674 object_property_set_int(obj
, "family", 15, &error_abort
);
4675 object_property_set_int(obj
, "model", 107, &error_abort
);
4676 object_property_set_int(obj
, "stepping", 1, &error_abort
);
4678 object_property_set_int(obj
, "family", 6, &error_abort
);
4679 object_property_set_int(obj
, "model", 6, &error_abort
);
4680 object_property_set_int(obj
, "stepping", 3, &error_abort
);
4684 x86_cpu_realizefn(dev
, errp
);
4687 static void max_x86_cpu_class_init(ObjectClass
*oc
, void *data
)
4689 DeviceClass
*dc
= DEVICE_CLASS(oc
);
4690 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
4694 xcc
->model_description
=
4695 "Enables all features supported by the accelerator in the current host";
4697 device_class_set_props(dc
, max_x86_cpu_properties
);
4698 dc
->realize
= max_x86_cpu_realize
;
4701 static void max_x86_cpu_initfn(Object
*obj
)
4703 X86CPU
*cpu
= X86_CPU(obj
);
4705 /* We can't fill the features array here because we don't know yet if
4706 * "migratable" is true or false.
4708 cpu
->max_features
= true;
4709 object_property_set_bool(OBJECT(cpu
), "pmu", true, &error_abort
);
4712 * these defaults are used for TCG and all other accelerators
4713 * besides KVM and HVF, which overwrite these values
4715 object_property_set_str(OBJECT(cpu
), "vendor", CPUID_VENDOR_AMD
,
4717 object_property_set_str(OBJECT(cpu
), "model-id",
4718 "QEMU TCG CPU version " QEMU_HW_VERSION
,
4722 static const TypeInfo max_x86_cpu_type_info
= {
4723 .name
= X86_CPU_TYPE_NAME("max"),
4724 .parent
= TYPE_X86_CPU
,
4725 .instance_init
= max_x86_cpu_initfn
,
4726 .class_init
= max_x86_cpu_class_init
,
4729 static char *feature_word_description(FeatureWordInfo
*f
, uint32_t bit
)
4731 assert(f
->type
== CPUID_FEATURE_WORD
|| f
->type
== MSR_FEATURE_WORD
);
4734 case CPUID_FEATURE_WORD
:
4736 const char *reg
= get_register_name_32(f
->cpuid
.reg
);
4738 return g_strdup_printf("CPUID.%02XH:%s",
4741 case MSR_FEATURE_WORD
:
4742 return g_strdup_printf("MSR(%02XH)",
4749 static bool x86_cpu_have_filtered_features(X86CPU
*cpu
)
4753 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
4754 if (cpu
->filtered_features
[w
]) {
4762 static void mark_unavailable_features(X86CPU
*cpu
, FeatureWord w
, uint64_t mask
,
4763 const char *verbose_prefix
)
4765 CPUX86State
*env
= &cpu
->env
;
4766 FeatureWordInfo
*f
= &feature_word_info
[w
];
4769 if (!cpu
->force_features
) {
4770 env
->features
[w
] &= ~mask
;
4772 cpu
->filtered_features
[w
] |= mask
;
4774 if (!verbose_prefix
) {
4778 for (i
= 0; i
< 64; ++i
) {
4779 if ((1ULL << i
) & mask
) {
4780 g_autofree
char *feat_word_str
= feature_word_description(f
, i
);
4781 warn_report("%s: %s%s%s [bit %d]",
4784 f
->feat_names
[i
] ? "." : "",
4785 f
->feat_names
[i
] ? f
->feat_names
[i
] : "", i
);
4790 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
,
4791 const char *name
, void *opaque
,
4794 X86CPU
*cpu
= X86_CPU(obj
);
4795 CPUX86State
*env
= &cpu
->env
;
4798 value
= (env
->cpuid_version
>> 8) & 0xf;
4800 value
+= (env
->cpuid_version
>> 20) & 0xff;
4802 visit_type_int(v
, name
, &value
, errp
);
4805 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
,
4806 const char *name
, void *opaque
,
4809 X86CPU
*cpu
= X86_CPU(obj
);
4810 CPUX86State
*env
= &cpu
->env
;
4811 const int64_t min
= 0;
4812 const int64_t max
= 0xff + 0xf;
4815 if (!visit_type_int(v
, name
, &value
, errp
)) {
4818 if (value
< min
|| value
> max
) {
4819 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4820 name
? name
: "null", value
, min
, max
);
4824 env
->cpuid_version
&= ~0xff00f00;
4826 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
4828 env
->cpuid_version
|= value
<< 8;
4832 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
,
4833 const char *name
, void *opaque
,
4836 X86CPU
*cpu
= X86_CPU(obj
);
4837 CPUX86State
*env
= &cpu
->env
;
4840 value
= (env
->cpuid_version
>> 4) & 0xf;
4841 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
4842 visit_type_int(v
, name
, &value
, errp
);
4845 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
,
4846 const char *name
, void *opaque
,
4849 X86CPU
*cpu
= X86_CPU(obj
);
4850 CPUX86State
*env
= &cpu
->env
;
4851 const int64_t min
= 0;
4852 const int64_t max
= 0xff;
4855 if (!visit_type_int(v
, name
, &value
, errp
)) {
4858 if (value
< min
|| value
> max
) {
4859 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4860 name
? name
: "null", value
, min
, max
);
4864 env
->cpuid_version
&= ~0xf00f0;
4865 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
4868 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
4869 const char *name
, void *opaque
,
4872 X86CPU
*cpu
= X86_CPU(obj
);
4873 CPUX86State
*env
= &cpu
->env
;
4876 value
= env
->cpuid_version
& 0xf;
4877 visit_type_int(v
, name
, &value
, errp
);
4880 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
4881 const char *name
, void *opaque
,
4884 X86CPU
*cpu
= X86_CPU(obj
);
4885 CPUX86State
*env
= &cpu
->env
;
4886 const int64_t min
= 0;
4887 const int64_t max
= 0xf;
4890 if (!visit_type_int(v
, name
, &value
, errp
)) {
4893 if (value
< min
|| value
> max
) {
4894 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4895 name
? name
: "null", value
, min
, max
);
4899 env
->cpuid_version
&= ~0xf;
4900 env
->cpuid_version
|= value
& 0xf;
4903 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
4905 X86CPU
*cpu
= X86_CPU(obj
);
4906 CPUX86State
*env
= &cpu
->env
;
4909 value
= g_malloc(CPUID_VENDOR_SZ
+ 1);
4910 x86_cpu_vendor_words2str(value
, env
->cpuid_vendor1
, env
->cpuid_vendor2
,
4911 env
->cpuid_vendor3
);
4915 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
4918 X86CPU
*cpu
= X86_CPU(obj
);
4919 CPUX86State
*env
= &cpu
->env
;
4922 if (strlen(value
) != CPUID_VENDOR_SZ
) {
4923 error_setg(errp
, QERR_PROPERTY_VALUE_BAD
, "", "vendor", value
);
4927 env
->cpuid_vendor1
= 0;
4928 env
->cpuid_vendor2
= 0;
4929 env
->cpuid_vendor3
= 0;
4930 for (i
= 0; i
< 4; i
++) {
4931 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
4932 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
4933 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
4937 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
4939 X86CPU
*cpu
= X86_CPU(obj
);
4940 CPUX86State
*env
= &cpu
->env
;
4944 value
= g_malloc(48 + 1);
4945 for (i
= 0; i
< 48; i
++) {
4946 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
4952 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
4955 X86CPU
*cpu
= X86_CPU(obj
);
4956 CPUX86State
*env
= &cpu
->env
;
4959 if (model_id
== NULL
) {
4962 len
= strlen(model_id
);
4963 memset(env
->cpuid_model
, 0, 48);
4964 for (i
= 0; i
< 48; i
++) {
4968 c
= (uint8_t)model_id
[i
];
4970 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
4974 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
4975 void *opaque
, Error
**errp
)
4977 X86CPU
*cpu
= X86_CPU(obj
);
4980 value
= cpu
->env
.tsc_khz
* 1000;
4981 visit_type_int(v
, name
, &value
, errp
);
4984 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, const char *name
,
4985 void *opaque
, Error
**errp
)
4987 X86CPU
*cpu
= X86_CPU(obj
);
4988 const int64_t min
= 0;
4989 const int64_t max
= INT64_MAX
;
4992 if (!visit_type_int(v
, name
, &value
, errp
)) {
4995 if (value
< min
|| value
> max
) {
4996 error_setg(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
4997 name
? name
: "null", value
, min
, max
);
5001 cpu
->env
.tsc_khz
= cpu
->env
.user_tsc_khz
= value
/ 1000;
5004 /* Generic getter for "feature-words" and "filtered-features" properties */
5005 static void x86_cpu_get_feature_words(Object
*obj
, Visitor
*v
,
5006 const char *name
, void *opaque
,
5009 uint64_t *array
= (uint64_t *)opaque
;
5011 X86CPUFeatureWordInfo word_infos
[FEATURE_WORDS
] = { };
5012 X86CPUFeatureWordInfoList list_entries
[FEATURE_WORDS
] = { };
5013 X86CPUFeatureWordInfoList
*list
= NULL
;
5015 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5016 FeatureWordInfo
*wi
= &feature_word_info
[w
];
5018 * We didn't have MSR features when "feature-words" was
5019 * introduced. Therefore skipped other type entries.
5021 if (wi
->type
!= CPUID_FEATURE_WORD
) {
5024 X86CPUFeatureWordInfo
*qwi
= &word_infos
[w
];
5025 qwi
->cpuid_input_eax
= wi
->cpuid
.eax
;
5026 qwi
->has_cpuid_input_ecx
= wi
->cpuid
.needs_ecx
;
5027 qwi
->cpuid_input_ecx
= wi
->cpuid
.ecx
;
5028 qwi
->cpuid_register
= x86_reg_info_32
[wi
->cpuid
.reg
].qapi_enum
;
5029 qwi
->features
= array
[w
];
5031 /* List will be in reverse order, but order shouldn't matter */
5032 list_entries
[w
].next
= list
;
5033 list_entries
[w
].value
= &word_infos
[w
];
5034 list
= &list_entries
[w
];
5037 visit_type_X86CPUFeatureWordInfoList(v
, "feature-words", &list
, errp
);
5040 /* Convert all '_' in a feature string option name to '-', to make feature
5041 * name conform to QOM property naming rule, which uses '-' instead of '_'.
5043 static inline void feat2prop(char *s
)
5045 while ((s
= strchr(s
, '_'))) {
5050 /* Return the feature property name for a feature flag bit */
5051 static const char *x86_cpu_feature_name(FeatureWord w
, int bitnr
)
5054 /* XSAVE components are automatically enabled by other features,
5055 * so return the original feature name instead
5057 if (w
== FEAT_XSAVE_XCR0_LO
|| w
== FEAT_XSAVE_XCR0_HI
) {
5058 int comp
= (w
== FEAT_XSAVE_XCR0_HI
) ? bitnr
+ 32 : bitnr
;
5060 if (comp
< ARRAY_SIZE(x86_ext_save_areas
) &&
5061 x86_ext_save_areas
[comp
].bits
) {
5062 w
= x86_ext_save_areas
[comp
].feature
;
5063 bitnr
= ctz32(x86_ext_save_areas
[comp
].bits
);
5068 assert(w
< FEATURE_WORDS
);
5069 name
= feature_word_info
[w
].feat_names
[bitnr
];
5070 assert(bitnr
< 32 || !(name
&& feature_word_info
[w
].type
== CPUID_FEATURE_WORD
));
5074 /* Compatibily hack to maintain legacy +-feat semantic,
5075 * where +-feat overwrites any feature set by
5076 * feat=on|feat even if the later is parsed after +-feat
5077 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
5079 static GList
*plus_features
, *minus_features
;
5081 static gint
compare_string(gconstpointer a
, gconstpointer b
)
5083 return g_strcmp0(a
, b
);
5086 /* Parse "+feature,-feature,feature=foo" CPU feature string
5088 static void x86_cpu_parse_featurestr(const char *typename
, char *features
,
5091 char *featurestr
; /* Single 'key=value" string being parsed */
5092 static bool cpu_globals_initialized
;
5093 bool ambiguous
= false;
5095 if (cpu_globals_initialized
) {
5098 cpu_globals_initialized
= true;
5104 for (featurestr
= strtok(features
, ",");
5106 featurestr
= strtok(NULL
, ",")) {
5108 const char *val
= NULL
;
5111 GlobalProperty
*prop
;
5113 /* Compatibility syntax: */
5114 if (featurestr
[0] == '+') {
5115 plus_features
= g_list_append(plus_features
,
5116 g_strdup(featurestr
+ 1));
5118 } else if (featurestr
[0] == '-') {
5119 minus_features
= g_list_append(minus_features
,
5120 g_strdup(featurestr
+ 1));
5124 eq
= strchr(featurestr
, '=');
5132 feat2prop(featurestr
);
5135 if (g_list_find_custom(plus_features
, name
, compare_string
)) {
5136 warn_report("Ambiguous CPU model string. "
5137 "Don't mix both \"+%s\" and \"%s=%s\"",
5141 if (g_list_find_custom(minus_features
, name
, compare_string
)) {
5142 warn_report("Ambiguous CPU model string. "
5143 "Don't mix both \"-%s\" and \"%s=%s\"",
5149 if (!strcmp(name
, "tsc-freq")) {
5153 ret
= qemu_strtosz_metric(val
, NULL
, &tsc_freq
);
5154 if (ret
< 0 || tsc_freq
> INT64_MAX
) {
5155 error_setg(errp
, "bad numerical value %s", val
);
5158 snprintf(num
, sizeof(num
), "%" PRId64
, tsc_freq
);
5160 name
= "tsc-frequency";
5163 prop
= g_new0(typeof(*prop
), 1);
5164 prop
->driver
= typename
;
5165 prop
->property
= g_strdup(name
);
5166 prop
->value
= g_strdup(val
);
5167 qdev_prop_register_global(prop
);
5171 warn_report("Compatibility of ambiguous CPU model "
5172 "strings won't be kept on future QEMU versions");
5176 static void x86_cpu_filter_features(X86CPU
*cpu
, bool verbose
);
5178 /* Build a list with the name of all features on a feature word array */
5179 static void x86_cpu_list_feature_names(FeatureWordArray features
,
5182 strList
**tail
= list
;
5185 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5186 uint64_t filtered
= features
[w
];
5188 for (i
= 0; i
< 64; i
++) {
5189 if (filtered
& (1ULL << i
)) {
5190 QAPI_LIST_APPEND(tail
, g_strdup(x86_cpu_feature_name(w
, i
)));
5196 static void x86_cpu_get_unavailable_features(Object
*obj
, Visitor
*v
,
5197 const char *name
, void *opaque
,
5200 X86CPU
*xc
= X86_CPU(obj
);
5201 strList
*result
= NULL
;
5203 x86_cpu_list_feature_names(xc
->filtered_features
, &result
);
5204 visit_type_strList(v
, "unavailable-features", &result
, errp
);
5207 /* Print all cpuid feature names in featureset
5209 static void listflags(GList
*features
)
5214 for (tmp
= features
; tmp
; tmp
= tmp
->next
) {
5215 const char *name
= tmp
->data
;
5216 if ((len
+ strlen(name
) + 1) >= 75) {
5220 qemu_printf("%s%s", len
== 0 ? " " : " ", name
);
5221 len
+= strlen(name
) + 1;
5226 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
5227 static gint
x86_cpu_list_compare(gconstpointer a
, gconstpointer b
)
5229 ObjectClass
*class_a
= (ObjectClass
*)a
;
5230 ObjectClass
*class_b
= (ObjectClass
*)b
;
5231 X86CPUClass
*cc_a
= X86_CPU_CLASS(class_a
);
5232 X86CPUClass
*cc_b
= X86_CPU_CLASS(class_b
);
5235 if (cc_a
->ordering
!= cc_b
->ordering
) {
5236 ret
= cc_a
->ordering
- cc_b
->ordering
;
5238 g_autofree
char *name_a
= x86_cpu_class_get_model_name(cc_a
);
5239 g_autofree
char *name_b
= x86_cpu_class_get_model_name(cc_b
);
5240 ret
= strcmp(name_a
, name_b
);
5245 static GSList
*get_sorted_cpu_model_list(void)
5247 GSList
*list
= object_class_get_list(TYPE_X86_CPU
, false);
5248 list
= g_slist_sort(list
, x86_cpu_list_compare
);
5252 static char *x86_cpu_class_get_model_id(X86CPUClass
*xc
)
5254 Object
*obj
= object_new_with_class(OBJECT_CLASS(xc
));
5255 char *r
= object_property_get_str(obj
, "model-id", &error_abort
);
5260 static char *x86_cpu_class_get_alias_of(X86CPUClass
*cc
)
5262 X86CPUVersion version
;
5264 if (!cc
->model
|| !cc
->model
->is_alias
) {
5267 version
= x86_cpu_model_resolve_version(cc
->model
);
5271 return x86_cpu_versioned_model_name(cc
->model
->cpudef
, version
);
5274 static void x86_cpu_list_entry(gpointer data
, gpointer user_data
)
5276 ObjectClass
*oc
= data
;
5277 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
5278 g_autofree
char *name
= x86_cpu_class_get_model_name(cc
);
5279 g_autofree
char *desc
= g_strdup(cc
->model_description
);
5280 g_autofree
char *alias_of
= x86_cpu_class_get_alias_of(cc
);
5281 g_autofree
char *model_id
= x86_cpu_class_get_model_id(cc
);
5283 if (!desc
&& alias_of
) {
5284 if (cc
->model
&& cc
->model
->version
== CPU_VERSION_AUTO
) {
5285 desc
= g_strdup("(alias configured by machine type)");
5287 desc
= g_strdup_printf("(alias of %s)", alias_of
);
5290 if (!desc
&& cc
->model
&& cc
->model
->note
) {
5291 desc
= g_strdup_printf("%s [%s]", model_id
, cc
->model
->note
);
5294 desc
= g_strdup_printf("%s", model_id
);
5297 if (cc
->model
&& cc
->model
->cpudef
->deprecation_note
) {
5298 g_autofree
char *olddesc
= desc
;
5299 desc
= g_strdup_printf("%s (deprecated)", olddesc
);
5302 qemu_printf("x86 %-20s %s\n", name
, desc
);
5305 /* list available CPU models and flags */
5306 void x86_cpu_list(void)
5310 GList
*names
= NULL
;
5312 qemu_printf("Available CPUs:\n");
5313 list
= get_sorted_cpu_model_list();
5314 g_slist_foreach(list
, x86_cpu_list_entry
, NULL
);
5318 for (i
= 0; i
< ARRAY_SIZE(feature_word_info
); i
++) {
5319 FeatureWordInfo
*fw
= &feature_word_info
[i
];
5320 for (j
= 0; j
< 64; j
++) {
5321 if (fw
->feat_names
[j
]) {
5322 names
= g_list_append(names
, (gpointer
)fw
->feat_names
[j
]);
5327 names
= g_list_sort(names
, (GCompareFunc
)strcmp
);
5329 qemu_printf("\nRecognized CPUID flags:\n");
5335 #ifndef CONFIG_USER_ONLY
5337 /* Check for missing features that may prevent the CPU class from
5338 * running using the current machine and accelerator.
5340 static void x86_cpu_class_check_missing_features(X86CPUClass
*xcc
,
5343 strList
**tail
= list
;
5347 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
5348 QAPI_LIST_APPEND(tail
, g_strdup("kvm"));
5352 xc
= X86_CPU(object_new_with_class(OBJECT_CLASS(xcc
)));
5354 x86_cpu_expand_features(xc
, &err
);
5356 /* Errors at x86_cpu_expand_features should never happen,
5357 * but in case it does, just report the model as not
5358 * runnable at all using the "type" property.
5360 QAPI_LIST_APPEND(tail
, g_strdup("type"));
5364 x86_cpu_filter_features(xc
, false);
5366 x86_cpu_list_feature_names(xc
->filtered_features
, tail
);
5368 object_unref(OBJECT(xc
));
5371 static void x86_cpu_definition_entry(gpointer data
, gpointer user_data
)
5373 ObjectClass
*oc
= data
;
5374 X86CPUClass
*cc
= X86_CPU_CLASS(oc
);
5375 CpuDefinitionInfoList
**cpu_list
= user_data
;
5376 CpuDefinitionInfo
*info
;
5378 info
= g_malloc0(sizeof(*info
));
5379 info
->name
= x86_cpu_class_get_model_name(cc
);
5380 x86_cpu_class_check_missing_features(cc
, &info
->unavailable_features
);
5381 info
->has_unavailable_features
= true;
5382 info
->q_typename
= g_strdup(object_class_get_name(oc
));
5383 info
->migration_safe
= cc
->migration_safe
;
5384 info
->has_migration_safe
= true;
5385 info
->q_static
= cc
->static_model
;
5386 if (cc
->model
&& cc
->model
->cpudef
->deprecation_note
) {
5387 info
->deprecated
= true;
5389 info
->deprecated
= false;
5392 * Old machine types won't report aliases, so that alias translation
5393 * doesn't break compatibility with previous QEMU versions.
5395 if (default_cpu_version
!= CPU_VERSION_LEGACY
) {
5396 info
->alias_of
= x86_cpu_class_get_alias_of(cc
);
5399 QAPI_LIST_PREPEND(*cpu_list
, info
);
5402 CpuDefinitionInfoList
*qmp_query_cpu_definitions(Error
**errp
)
5404 CpuDefinitionInfoList
*cpu_list
= NULL
;
5405 GSList
*list
= get_sorted_cpu_model_list();
5406 g_slist_foreach(list
, x86_cpu_definition_entry
, &cpu_list
);
5411 #endif /* !CONFIG_USER_ONLY */
5413 uint64_t x86_cpu_get_supported_feature_word(FeatureWord w
,
5414 bool migratable_only
)
5416 FeatureWordInfo
*wi
= &feature_word_info
[w
];
5419 if (kvm_enabled()) {
5421 case CPUID_FEATURE_WORD
:
5422 r
= kvm_arch_get_supported_cpuid(kvm_state
, wi
->cpuid
.eax
,
5426 case MSR_FEATURE_WORD
:
5427 r
= kvm_arch_get_supported_msr_feature(kvm_state
,
5431 } else if (hvf_enabled()) {
5432 if (wi
->type
!= CPUID_FEATURE_WORD
) {
5435 r
= hvf_get_supported_cpuid(wi
->cpuid
.eax
,
5438 } else if (tcg_enabled()) {
5439 r
= wi
->tcg_features
;
5443 #ifndef TARGET_X86_64
5444 if (w
== FEAT_8000_0001_EDX
) {
5445 r
&= ~CPUID_EXT2_LM
;
5448 if (migratable_only
) {
5449 r
&= x86_cpu_get_migratable_flags(w
);
5454 static void x86_cpu_get_supported_cpuid(uint32_t func
, uint32_t index
,
5455 uint32_t *eax
, uint32_t *ebx
,
5456 uint32_t *ecx
, uint32_t *edx
)
5458 if (kvm_enabled()) {
5459 *eax
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_EAX
);
5460 *ebx
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_EBX
);
5461 *ecx
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_ECX
);
5462 *edx
= kvm_arch_get_supported_cpuid(kvm_state
, func
, index
, R_EDX
);
5463 } else if (hvf_enabled()) {
5464 *eax
= hvf_get_supported_cpuid(func
, index
, R_EAX
);
5465 *ebx
= hvf_get_supported_cpuid(func
, index
, R_EBX
);
5466 *ecx
= hvf_get_supported_cpuid(func
, index
, R_ECX
);
5467 *edx
= hvf_get_supported_cpuid(func
, index
, R_EDX
);
5476 static void x86_cpu_get_cache_cpuid(uint32_t func
, uint32_t index
,
5477 uint32_t *eax
, uint32_t *ebx
,
5478 uint32_t *ecx
, uint32_t *edx
)
5480 uint32_t level
, unused
;
5482 /* Only return valid host leaves. */
5486 host_cpuid(0, 0, &level
, &unused
, &unused
, &unused
);
5491 host_cpuid(0x80000000, 0, &level
, &unused
, &unused
, &unused
);
5503 host_cpuid(func
, index
, eax
, ebx
, ecx
, edx
);
5508 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5510 void x86_cpu_apply_props(X86CPU
*cpu
, PropValue
*props
)
5513 for (pv
= props
; pv
->prop
; pv
++) {
5517 object_property_parse(OBJECT(cpu
), pv
->prop
, pv
->value
,
5523 * Apply properties for the CPU model version specified in model.
5524 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5527 static void x86_cpu_apply_version_props(X86CPU
*cpu
, X86CPUModel
*model
)
5529 const X86CPUVersionDefinition
*vdef
;
5530 X86CPUVersion version
= x86_cpu_model_resolve_version(model
);
5532 if (version
== CPU_VERSION_LEGACY
) {
5536 for (vdef
= x86_cpu_def_get_versions(model
->cpudef
); vdef
->version
; vdef
++) {
5539 for (p
= vdef
->props
; p
&& p
->prop
; p
++) {
5540 object_property_parse(OBJECT(cpu
), p
->prop
, p
->value
,
5544 if (vdef
->version
== version
) {
5550 * If we reached the end of the list, version number was invalid
5552 assert(vdef
->version
== version
);
5555 static const CPUCaches
*x86_cpu_get_versioned_cache_info(X86CPU
*cpu
,
5558 const X86CPUVersionDefinition
*vdef
;
5559 X86CPUVersion version
= x86_cpu_model_resolve_version(model
);
5560 const CPUCaches
*cache_info
= model
->cpudef
->cache_info
;
5562 if (version
== CPU_VERSION_LEGACY
) {
5566 for (vdef
= x86_cpu_def_get_versions(model
->cpudef
); vdef
->version
; vdef
++) {
5567 if (vdef
->cache_info
) {
5568 cache_info
= vdef
->cache_info
;
5571 if (vdef
->version
== version
) {
5576 assert(vdef
->version
== version
);
5581 * Load data from X86CPUDefinition into a X86CPU object.
5582 * Only for builtin_x86_defs models initialized with x86_register_cpudef_types.
5584 static void x86_cpu_load_model(X86CPU
*cpu
, X86CPUModel
*model
)
5586 const X86CPUDefinition
*def
= model
->cpudef
;
5587 CPUX86State
*env
= &cpu
->env
;
5590 /*NOTE: any property set by this function should be returned by
5591 * x86_cpu_static_props(), so static expansion of
5592 * query-cpu-model-expansion is always complete.
5595 /* CPU models only set _minimum_ values for level/xlevel: */
5596 object_property_set_uint(OBJECT(cpu
), "min-level", def
->level
,
5598 object_property_set_uint(OBJECT(cpu
), "min-xlevel", def
->xlevel
,
5601 object_property_set_int(OBJECT(cpu
), "family", def
->family
, &error_abort
);
5602 object_property_set_int(OBJECT(cpu
), "model", def
->model
, &error_abort
);
5603 object_property_set_int(OBJECT(cpu
), "stepping", def
->stepping
,
5605 object_property_set_str(OBJECT(cpu
), "model-id", def
->model_id
,
5607 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
5608 env
->features
[w
] = def
->features
[w
];
5611 /* legacy-cache defaults to 'off' if CPU model provides cache info */
5612 cpu
->legacy_cache
= !x86_cpu_get_versioned_cache_info(cpu
, model
);
5614 env
->features
[FEAT_1_ECX
] |= CPUID_EXT_HYPERVISOR
;
5616 /* sysenter isn't supported in compatibility mode on AMD,
5617 * syscall isn't supported in compatibility mode on Intel.
5618 * Normally we advertise the actual CPU vendor, but you can
5619 * override this using the 'vendor' property if you want to use
5620 * KVM's sysenter/syscall emulation in compatibility mode and
5621 * when doing cross vendor migration
5625 * vendor property is set here but then overloaded with the
5626 * host cpu vendor for KVM and HVF.
5628 object_property_set_str(OBJECT(cpu
), "vendor", def
->vendor
, &error_abort
);
5630 x86_cpu_apply_version_props(cpu
, model
);
5633 * Properties in versioned CPU model are not user specified features.
5634 * We can simply clear env->user_features here since it will be filled later
5635 * in x86_cpu_expand_features() based on plus_features and minus_features.
5637 memset(&env
->user_features
, 0, sizeof(env
->user_features
));
5640 static gchar
*x86_gdb_arch_name(CPUState
*cs
)
5642 #ifdef TARGET_X86_64
5643 return g_strdup("i386:x86-64");
5645 return g_strdup("i386");
5649 static void x86_cpu_cpudef_class_init(ObjectClass
*oc
, void *data
)
5651 X86CPUModel
*model
= data
;
5652 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
5653 CPUClass
*cc
= CPU_CLASS(oc
);
5656 xcc
->migration_safe
= true;
5657 cc
->deprecation_note
= model
->cpudef
->deprecation_note
;
5660 static void x86_register_cpu_model_type(const char *name
, X86CPUModel
*model
)
5662 g_autofree
char *typename
= x86_cpu_type_name(name
);
5665 .parent
= TYPE_X86_CPU
,
5666 .class_init
= x86_cpu_cpudef_class_init
,
5667 .class_data
= model
,
5675 * register builtin_x86_defs;
5676 * "max", "base" and subclasses ("host") are not registered here.
5677 * See x86_cpu_register_types for all model registrations.
5679 static void x86_register_cpudef_types(const X86CPUDefinition
*def
)
5682 const X86CPUVersionDefinition
*vdef
;
5684 /* AMD aliases are handled at runtime based on CPUID vendor, so
5685 * they shouldn't be set on the CPU model table.
5687 assert(!(def
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_AMD_ALIASES
));
5688 /* catch mistakes instead of silently truncating model_id when too long */
5689 assert(def
->model_id
&& strlen(def
->model_id
) <= 48);
5691 /* Unversioned model: */
5692 m
= g_new0(X86CPUModel
, 1);
5694 m
->version
= CPU_VERSION_AUTO
;
5696 x86_register_cpu_model_type(def
->name
, m
);
5698 /* Versioned models: */
5700 for (vdef
= x86_cpu_def_get_versions(def
); vdef
->version
; vdef
++) {
5701 X86CPUModel
*m
= g_new0(X86CPUModel
, 1);
5702 g_autofree
char *name
=
5703 x86_cpu_versioned_model_name(def
, vdef
->version
);
5705 m
->version
= vdef
->version
;
5706 m
->note
= vdef
->note
;
5707 x86_register_cpu_model_type(name
, m
);
5710 X86CPUModel
*am
= g_new0(X86CPUModel
, 1);
5712 am
->version
= vdef
->version
;
5713 am
->is_alias
= true;
5714 x86_register_cpu_model_type(vdef
->alias
, am
);
5720 uint32_t cpu_x86_virtual_addr_width(CPUX86State
*env
)
5722 if (env
->features
[FEAT_7_0_ECX
] & CPUID_7_0_ECX_LA57
) {
5723 return 57; /* 57 bits virtual */
5725 return 48; /* 48 bits virtual */
5729 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
5730 uint32_t *eax
, uint32_t *ebx
,
5731 uint32_t *ecx
, uint32_t *edx
)
5733 X86CPU
*cpu
= env_archcpu(env
);
5734 CPUState
*cs
= env_cpu(env
);
5735 uint32_t die_offset
;
5737 uint32_t signature
[3];
5738 X86CPUTopoInfo topo_info
;
5740 topo_info
.dies_per_pkg
= env
->nr_dies
;
5741 topo_info
.cores_per_die
= cs
->nr_cores
;
5742 topo_info
.threads_per_core
= cs
->nr_threads
;
5744 /* Calculate & apply limits for different index ranges */
5745 if (index
>= 0xC0000000) {
5746 limit
= env
->cpuid_xlevel2
;
5747 } else if (index
>= 0x80000000) {
5748 limit
= env
->cpuid_xlevel
;
5749 } else if (index
>= 0x40000000) {
5752 limit
= env
->cpuid_level
;
5755 if (index
> limit
) {
5756 /* Intel documentation states that invalid EAX input will
5757 * return the same information as EAX=cpuid_level
5758 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5760 index
= env
->cpuid_level
;
5765 *eax
= env
->cpuid_level
;
5766 *ebx
= env
->cpuid_vendor1
;
5767 *edx
= env
->cpuid_vendor2
;
5768 *ecx
= env
->cpuid_vendor3
;
5771 *eax
= env
->cpuid_version
;
5772 *ebx
= (cpu
->apic_id
<< 24) |
5773 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5774 *ecx
= env
->features
[FEAT_1_ECX
];
5775 if ((*ecx
& CPUID_EXT_XSAVE
) && (env
->cr
[4] & CR4_OSXSAVE_MASK
)) {
5776 *ecx
|= CPUID_EXT_OSXSAVE
;
5778 *edx
= env
->features
[FEAT_1_EDX
];
5779 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
5780 *ebx
|= (cs
->nr_cores
* cs
->nr_threads
) << 16;
5783 if (!cpu
->enable_pmu
) {
5784 *ecx
&= ~CPUID_EXT_PDCM
;
5788 /* cache info: needed for Pentium Pro compatibility */
5789 if (cpu
->cache_info_passthrough
) {
5790 x86_cpu_get_cache_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
5792 } else if (cpu
->vendor_cpuid_only
&& IS_AMD_CPU(env
)) {
5793 *eax
= *ebx
= *ecx
= *edx
= 0;
5796 *eax
= 1; /* Number of CPUID[EAX=2] calls required */
5798 if (!cpu
->enable_l3_cache
) {
5801 *ecx
= cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l3_cache
);
5803 *edx
= (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1d_cache
) << 16) |
5804 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l1i_cache
) << 8) |
5805 (cpuid2_cache_descriptor(env
->cache_info_cpuid2
.l2_cache
));
5808 /* cache info: needed for Core compatibility */
5809 if (cpu
->cache_info_passthrough
) {
5810 x86_cpu_get_cache_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
5812 * QEMU has its own number of cores/logical cpus,
5813 * set 24..14, 31..26 bit to configured values
5816 int host_vcpus_per_cache
= 1 + ((*eax
& 0x3FFC000) >> 14);
5817 int vcpus_per_socket
= env
->nr_dies
* cs
->nr_cores
*
5819 if (cs
->nr_cores
> 1) {
5820 *eax
&= ~0xFC000000;
5821 *eax
|= (pow2ceil(cs
->nr_cores
) - 1) << 26;
5823 if (host_vcpus_per_cache
> vcpus_per_socket
) {
5825 *eax
|= (pow2ceil(vcpus_per_socket
) - 1) << 14;
5828 } else if (cpu
->vendor_cpuid_only
&& IS_AMD_CPU(env
)) {
5829 *eax
= *ebx
= *ecx
= *edx
= 0;
5833 case 0: /* L1 dcache info */
5834 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1d_cache
,
5836 eax
, ebx
, ecx
, edx
);
5838 case 1: /* L1 icache info */
5839 encode_cache_cpuid4(env
->cache_info_cpuid4
.l1i_cache
,
5841 eax
, ebx
, ecx
, edx
);
5843 case 2: /* L2 cache info */
5844 encode_cache_cpuid4(env
->cache_info_cpuid4
.l2_cache
,
5845 cs
->nr_threads
, cs
->nr_cores
,
5846 eax
, ebx
, ecx
, edx
);
5848 case 3: /* L3 cache info */
5849 die_offset
= apicid_die_offset(&topo_info
);
5850 if (cpu
->enable_l3_cache
) {
5851 encode_cache_cpuid4(env
->cache_info_cpuid4
.l3_cache
,
5852 (1 << die_offset
), cs
->nr_cores
,
5853 eax
, ebx
, ecx
, edx
);
5857 default: /* end of info */
5858 *eax
= *ebx
= *ecx
= *edx
= 0;
5864 /* MONITOR/MWAIT Leaf */
5865 *eax
= cpu
->mwait
.eax
; /* Smallest monitor-line size in bytes */
5866 *ebx
= cpu
->mwait
.ebx
; /* Largest monitor-line size in bytes */
5867 *ecx
= cpu
->mwait
.ecx
; /* flags */
5868 *edx
= cpu
->mwait
.edx
; /* mwait substates */
5871 /* Thermal and Power Leaf */
5872 *eax
= env
->features
[FEAT_6_EAX
];
5878 /* Structured Extended Feature Flags Enumeration Leaf */
5880 /* Maximum ECX value for sub-leaves */
5881 *eax
= env
->cpuid_level_func7
;
5882 *ebx
= env
->features
[FEAT_7_0_EBX
]; /* Feature flags */
5883 *ecx
= env
->features
[FEAT_7_0_ECX
]; /* Feature flags */
5884 if ((*ecx
& CPUID_7_0_ECX_PKU
) && env
->cr
[4] & CR4_PKE_MASK
) {
5885 *ecx
|= CPUID_7_0_ECX_OSPKE
;
5887 *edx
= env
->features
[FEAT_7_0_EDX
]; /* Feature flags */
5890 * SGX cannot be emulated in software. If hardware does not
5891 * support enabling SGX and/or SGX flexible launch control,
5892 * then we need to update the VM's CPUID values accordingly.
5894 if ((*ebx
& CPUID_7_0_EBX_SGX
) &&
5896 !(kvm_arch_get_supported_cpuid(cs
->kvm_state
, 0x7, 0, R_EBX
) &
5897 CPUID_7_0_EBX_SGX
))) {
5898 *ebx
&= ~CPUID_7_0_EBX_SGX
;
5901 if ((*ecx
& CPUID_7_0_ECX_SGX_LC
) &&
5902 (!(*ebx
& CPUID_7_0_EBX_SGX
) || !kvm_enabled() ||
5903 !(kvm_arch_get_supported_cpuid(cs
->kvm_state
, 0x7, 0, R_ECX
) &
5904 CPUID_7_0_ECX_SGX_LC
))) {
5905 *ecx
&= ~CPUID_7_0_ECX_SGX_LC
;
5907 } else if (count
== 1) {
5908 *eax
= env
->features
[FEAT_7_1_EAX
];
5909 *edx
= env
->features
[FEAT_7_1_EDX
];
5920 /* Direct Cache Access Information Leaf */
5921 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
5927 /* Architectural Performance Monitoring Leaf */
5928 if (accel_uses_host_cpuid() && cpu
->enable_pmu
) {
5929 x86_cpu_get_supported_cpuid(0xA, count
, eax
, ebx
, ecx
, edx
);
5938 /* Extended Topology Enumeration Leaf */
5939 if (!cpu
->enable_cpuid_0xb
) {
5940 *eax
= *ebx
= *ecx
= *edx
= 0;
5944 *ecx
= count
& 0xff;
5945 *edx
= cpu
->apic_id
;
5949 *eax
= apicid_core_offset(&topo_info
);
5950 *ebx
= cs
->nr_threads
;
5951 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
5954 *eax
= apicid_pkg_offset(&topo_info
);
5955 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
5956 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
5961 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
5964 assert(!(*eax
& ~0x1f));
5965 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
5968 if (accel_uses_host_cpuid() && cpu
->enable_pmu
&&
5969 (env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_ARCH_LBR
)) {
5970 x86_cpu_get_supported_cpuid(0x1C, 0, eax
, ebx
, ecx
, edx
);
5975 /* V2 Extended Topology Enumeration Leaf */
5976 if (env
->nr_dies
< 2) {
5977 *eax
= *ebx
= *ecx
= *edx
= 0;
5981 *ecx
= count
& 0xff;
5982 *edx
= cpu
->apic_id
;
5985 *eax
= apicid_core_offset(&topo_info
);
5986 *ebx
= cs
->nr_threads
;
5987 *ecx
|= CPUID_TOPOLOGY_LEVEL_SMT
;
5990 *eax
= apicid_die_offset(&topo_info
);
5991 *ebx
= cs
->nr_cores
* cs
->nr_threads
;
5992 *ecx
|= CPUID_TOPOLOGY_LEVEL_CORE
;
5995 *eax
= apicid_pkg_offset(&topo_info
);
5996 *ebx
= env
->nr_dies
* cs
->nr_cores
* cs
->nr_threads
;
5997 *ecx
|= CPUID_TOPOLOGY_LEVEL_DIE
;
6002 *ecx
|= CPUID_TOPOLOGY_LEVEL_INVALID
;
6004 assert(!(*eax
& ~0x1f));
6005 *ebx
&= 0xffff; /* The count doesn't need to be reliable. */
6008 /* Processor Extended State */
6013 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
6018 *ecx
= xsave_area_size(x86_cpu_xsave_xcr0_components(cpu
), false);
6019 *eax
= env
->features
[FEAT_XSAVE_XCR0_LO
];
6020 *edx
= env
->features
[FEAT_XSAVE_XCR0_HI
];
6022 * The initial value of xcr0 and ebx == 0, On host without kvm
6023 * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
6024 * even through guest update xcr0, this will crash some legacy guest
6025 * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
6027 *ebx
= kvm_enabled() ? *ecx
: xsave_area_size(env
->xcr0
, false);
6028 } else if (count
== 1) {
6029 uint64_t xstate
= x86_cpu_xsave_xcr0_components(cpu
) |
6030 x86_cpu_xsave_xss_components(cpu
);
6032 *eax
= env
->features
[FEAT_XSAVE
];
6033 *ebx
= xsave_area_size(xstate
, true);
6034 *ecx
= env
->features
[FEAT_XSAVE_XSS_LO
];
6035 *edx
= env
->features
[FEAT_XSAVE_XSS_HI
];
6036 if (kvm_enabled() && cpu
->enable_pmu
&&
6037 (env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_ARCH_LBR
) &&
6038 (*eax
& CPUID_XSAVE_XSAVES
)) {
6039 *ecx
|= XSTATE_ARCH_LBR_MASK
;
6041 *ecx
&= ~XSTATE_ARCH_LBR_MASK
;
6043 } else if (count
== 0xf &&
6044 accel_uses_host_cpuid() && cpu
->enable_pmu
&&
6045 (env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_ARCH_LBR
)) {
6046 x86_cpu_get_supported_cpuid(0xD, count
, eax
, ebx
, ecx
, edx
);
6047 } else if (count
< ARRAY_SIZE(x86_ext_save_areas
)) {
6048 const ExtSaveArea
*esa
= &x86_ext_save_areas
[count
];
6050 if (x86_cpu_xsave_xcr0_components(cpu
) & (1ULL << count
)) {
6054 (ESA_FEATURE_ALIGN64_MASK
| ESA_FEATURE_XFD_MASK
);
6055 } else if (x86_cpu_xsave_xss_components(cpu
) & (1ULL << count
)) {
6064 #ifndef CONFIG_USER_ONLY
6065 if (!kvm_enabled() ||
6066 !(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SGX
)) {
6067 *eax
= *ebx
= *ecx
= *edx
= 0;
6072 * SGX sub-leafs CPUID.0x12.{0x2..N} enumerate EPC sections. Retrieve
6073 * the EPC properties, e.g. confidentiality and integrity, from the
6074 * host's first EPC section, i.e. assume there is one EPC section or
6075 * that all EPC sections have the same security properties.
6078 uint64_t epc_addr
, epc_size
;
6080 if (sgx_epc_get_section(count
- 2, &epc_addr
, &epc_size
)) {
6081 *eax
= *ebx
= *ecx
= *edx
= 0;
6084 host_cpuid(index
, 2, eax
, ebx
, ecx
, edx
);
6085 *eax
= (uint32_t)(epc_addr
& 0xfffff000) | 0x1;
6086 *ebx
= (uint32_t)(epc_addr
>> 32);
6087 *ecx
= (uint32_t)(epc_size
& 0xfffff000) | (*ecx
& 0xf);
6088 *edx
= (uint32_t)(epc_size
>> 32);
6093 * SGX sub-leafs CPUID.0x12.{0x0,0x1} are heavily dependent on hardware
6094 * and KVM, i.e. QEMU cannot emulate features to override what KVM
6095 * supports. Features can be further restricted by userspace, but not
6096 * made more permissive.
6098 x86_cpu_get_supported_cpuid(0x12, count
, eax
, ebx
, ecx
, edx
);
6101 *eax
&= env
->features
[FEAT_SGX_12_0_EAX
];
6102 *ebx
&= env
->features
[FEAT_SGX_12_0_EBX
];
6104 *eax
&= env
->features
[FEAT_SGX_12_1_EAX
];
6105 *ebx
&= 0; /* ebx reserve */
6106 *ecx
&= env
->features
[FEAT_XSAVE_XCR0_LO
];
6107 *edx
&= env
->features
[FEAT_XSAVE_XCR0_HI
];
6109 /* FP and SSE are always allowed regardless of XSAVE/XCR0. */
6110 *ecx
|= XSTATE_FP_MASK
| XSTATE_SSE_MASK
;
6112 /* Access to PROVISIONKEY requires additional credentials. */
6113 if ((*eax
& (1U << 4)) &&
6114 !kvm_enable_sgx_provisioning(cs
->kvm_state
)) {
6121 /* Intel Processor Trace Enumeration */
6126 if (!(env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) ||
6132 *eax
= INTEL_PT_MAX_SUBLEAF
;
6133 *ebx
= INTEL_PT_MINIMAL_EBX
;
6134 *ecx
= INTEL_PT_MINIMAL_ECX
;
6135 if (env
->features
[FEAT_14_0_ECX
] & CPUID_14_0_ECX_LIP
) {
6136 *ecx
|= CPUID_14_0_ECX_LIP
;
6138 } else if (count
== 1) {
6139 *eax
= INTEL_PT_MTC_BITMAP
| INTEL_PT_ADDR_RANGES_NUM
;
6140 *ebx
= INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
;
6145 /* AMX TILE, for now hardcoded for Sapphire Rapids*/
6150 if (!(env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_AMX_TILE
)) {
6155 /* Highest numbered palette subleaf */
6156 *eax
= INTEL_AMX_TILE_MAX_SUBLEAF
;
6157 } else if (count
== 1) {
6158 *eax
= INTEL_AMX_TOTAL_TILE_BYTES
|
6159 (INTEL_AMX_BYTES_PER_TILE
<< 16);
6160 *ebx
= INTEL_AMX_BYTES_PER_ROW
| (INTEL_AMX_TILE_MAX_NAMES
<< 16);
6161 *ecx
= INTEL_AMX_TILE_MAX_ROWS
;
6166 /* AMX TMUL, for now hardcoded for Sapphire Rapids */
6171 if (!(env
->features
[FEAT_7_0_EDX
] & CPUID_7_0_EDX_AMX_TILE
)) {
6176 /* Highest numbered palette subleaf */
6177 *ebx
= INTEL_AMX_TMUL_MAX_K
| (INTEL_AMX_TMUL_MAX_N
<< 8);
6183 * CPUID code in kvm_arch_init_vcpu() ignores stuff
6184 * set here, but we restrict to TCG none the less.
6186 if (tcg_enabled() && cpu
->expose_tcg
) {
6187 memcpy(signature
, "TCGTCGTCGTCG", 12);
6189 *ebx
= signature
[0];
6190 *ecx
= signature
[1];
6191 *edx
= signature
[2];
6206 *eax
= env
->cpuid_xlevel
;
6207 *ebx
= env
->cpuid_vendor1
;
6208 *edx
= env
->cpuid_vendor2
;
6209 *ecx
= env
->cpuid_vendor3
;
6212 *eax
= env
->cpuid_version
;
6214 *ecx
= env
->features
[FEAT_8000_0001_ECX
];
6215 *edx
= env
->features
[FEAT_8000_0001_EDX
];
6217 /* The Linux kernel checks for the CMPLegacy bit and
6218 * discards multiple thread information if it is set.
6219 * So don't set it here for Intel to make Linux guests happy.
6221 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
6222 if (env
->cpuid_vendor1
!= CPUID_VENDOR_INTEL_1
||
6223 env
->cpuid_vendor2
!= CPUID_VENDOR_INTEL_2
||
6224 env
->cpuid_vendor3
!= CPUID_VENDOR_INTEL_3
) {
6225 *ecx
|= 1 << 1; /* CmpLegacy bit */
6232 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
6233 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
6234 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
6235 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
6238 /* cache info (L1 cache) */
6239 if (cpu
->cache_info_passthrough
) {
6240 x86_cpu_get_cache_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
6243 *eax
= (L1_DTLB_2M_ASSOC
<< 24) | (L1_DTLB_2M_ENTRIES
<< 16) |
6244 (L1_ITLB_2M_ASSOC
<< 8) | (L1_ITLB_2M_ENTRIES
);
6245 *ebx
= (L1_DTLB_4K_ASSOC
<< 24) | (L1_DTLB_4K_ENTRIES
<< 16) |
6246 (L1_ITLB_4K_ASSOC
<< 8) | (L1_ITLB_4K_ENTRIES
);
6247 *ecx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1d_cache
);
6248 *edx
= encode_cache_cpuid80000005(env
->cache_info_amd
.l1i_cache
);
6251 /* cache info (L2 cache) */
6252 if (cpu
->cache_info_passthrough
) {
6253 x86_cpu_get_cache_cpuid(index
, 0, eax
, ebx
, ecx
, edx
);
6256 *eax
= (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC
) << 28) |
6257 (L2_DTLB_2M_ENTRIES
<< 16) |
6258 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC
) << 12) |
6259 (L2_ITLB_2M_ENTRIES
);
6260 *ebx
= (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC
) << 28) |
6261 (L2_DTLB_4K_ENTRIES
<< 16) |
6262 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC
) << 12) |
6263 (L2_ITLB_4K_ENTRIES
);
6264 encode_cache_cpuid80000006(env
->cache_info_amd
.l2_cache
,
6265 cpu
->enable_l3_cache
?
6266 env
->cache_info_amd
.l3_cache
: NULL
,
6273 *edx
= env
->features
[FEAT_8000_0007_EDX
];
6276 /* virtual & phys address size in low 2 bytes. */
6277 *eax
= cpu
->phys_bits
;
6278 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
6279 /* 64 bit processor */
6280 *eax
|= (cpu_x86_virtual_addr_width(env
) << 8);
6282 *ebx
= env
->features
[FEAT_8000_0008_EBX
];
6283 if (cs
->nr_cores
* cs
->nr_threads
> 1) {
6285 * Bits 15:12 is "The number of bits in the initial
6286 * Core::X86::Apic::ApicId[ApicId] value that indicate
6287 * thread ID within a package".
6288 * Bits 7:0 is "The number of threads in the package is NC+1"
6290 *ecx
= (apicid_pkg_offset(&topo_info
) << 12) |
6291 ((cs
->nr_cores
* cs
->nr_threads
) - 1);
6298 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
6299 *eax
= 0x00000001; /* SVM Revision */
6300 *ebx
= 0x00000010; /* nr of ASIDs */
6302 *edx
= env
->features
[FEAT_SVM
]; /* optional features */
6312 if (cpu
->cache_info_passthrough
) {
6313 x86_cpu_get_cache_cpuid(index
, count
, eax
, ebx
, ecx
, edx
);
6317 case 0: /* L1 dcache info */
6318 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1d_cache
,
6319 &topo_info
, eax
, ebx
, ecx
, edx
);
6321 case 1: /* L1 icache info */
6322 encode_cache_cpuid8000001d(env
->cache_info_amd
.l1i_cache
,
6323 &topo_info
, eax
, ebx
, ecx
, edx
);
6325 case 2: /* L2 cache info */
6326 encode_cache_cpuid8000001d(env
->cache_info_amd
.l2_cache
,
6327 &topo_info
, eax
, ebx
, ecx
, edx
);
6329 case 3: /* L3 cache info */
6330 encode_cache_cpuid8000001d(env
->cache_info_amd
.l3_cache
,
6331 &topo_info
, eax
, ebx
, ecx
, edx
);
6333 default: /* end of info */
6334 *eax
= *ebx
= *ecx
= *edx
= 0;
6339 if (cpu
->core_id
<= 255) {
6340 encode_topo_cpuid8000001e(cpu
, &topo_info
, eax
, ebx
, ecx
, edx
);
6349 *eax
= env
->cpuid_xlevel2
;
6355 /* Support for VIA CPU's CPUID instruction */
6356 *eax
= env
->cpuid_version
;
6359 *edx
= env
->features
[FEAT_C000_0001_EDX
];
6364 /* Reserved for the future, and now filled with zero */
6371 *eax
= *ebx
= *ecx
= *edx
= 0;
6372 if (sev_enabled()) {
6374 *eax
|= sev_es_enabled() ? 0x8 : 0;
6375 *ebx
= sev_get_cbit_position() & 0x3f; /* EBX[5:0] */
6376 *ebx
|= (sev_get_reduced_phys_bits() & 0x3f) << 6; /* EBX[11:6] */
6380 *eax
= env
->features
[FEAT_8000_0021_EAX
];
6381 *ebx
= *ecx
= *edx
= 0;
6384 /* reserved values: zero */
6393 static void x86_cpu_set_sgxlepubkeyhash(CPUX86State
*env
)
6395 #ifndef CONFIG_USER_ONLY
6396 /* Those default values are defined in Skylake HW */
6397 env
->msr_ia32_sgxlepubkeyhash
[0] = 0xa6053e051270b7acULL
;
6398 env
->msr_ia32_sgxlepubkeyhash
[1] = 0x6cfbe8ba8b3b413dULL
;
6399 env
->msr_ia32_sgxlepubkeyhash
[2] = 0xc4916d99f2b3735dULL
;
6400 env
->msr_ia32_sgxlepubkeyhash
[3] = 0xd4f8c05909f9bb3bULL
;
6404 static void x86_cpu_reset_hold(Object
*obj
)
6406 CPUState
*s
= CPU(obj
);
6407 X86CPU
*cpu
= X86_CPU(s
);
6408 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
6409 CPUX86State
*env
= &cpu
->env
;
6414 if (xcc
->parent_phases
.hold
) {
6415 xcc
->parent_phases
.hold(obj
);
6418 memset(env
, 0, offsetof(CPUX86State
, end_reset_fields
));
6420 env
->old_exception
= -1;
6422 /* init to reset state */
6424 env
->hflags2
|= HF2_GIF_MASK
;
6425 env
->hflags2
|= HF2_VGIF_MASK
;
6426 env
->hflags
&= ~HF_GUEST_MASK
;
6428 cpu_x86_update_cr0(env
, 0x60000010);
6429 env
->a20_mask
= ~0x0;
6430 env
->smbase
= 0x30000;
6431 env
->msr_smi_count
= 0;
6433 env
->idt
.limit
= 0xffff;
6434 env
->gdt
.limit
= 0xffff;
6435 env
->ldt
.limit
= 0xffff;
6436 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
6437 env
->tr
.limit
= 0xffff;
6438 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
6440 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
6441 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
6442 DESC_R_MASK
| DESC_A_MASK
);
6443 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
6444 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6446 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
6447 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6449 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
6450 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6452 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
6453 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6455 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
6456 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
6460 env
->regs
[R_EDX
] = env
->cpuid_version
;
6465 for (i
= 0; i
< 8; i
++) {
6468 cpu_set_fpuc(env
, 0x37f);
6470 env
->mxcsr
= 0x1f80;
6471 /* All units are in INIT state. */
6474 env
->pat
= 0x0007040600070406ULL
;
6476 if (kvm_enabled()) {
6478 * KVM handles TSC = 0 specially and thinks we are hot-plugging
6479 * a new CPU, use 1 instead to force a reset.
6481 if (env
->tsc
!= 0) {
6488 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
6489 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_MONITOR
) {
6490 env
->msr_ia32_misc_enable
|= MSR_IA32_MISC_ENABLE_MWAIT
;
6493 memset(env
->dr
, 0, sizeof(env
->dr
));
6494 env
->dr
[6] = DR6_FIXED_1
;
6495 env
->dr
[7] = DR7_FIXED_1
;
6496 cpu_breakpoint_remove_all(s
, BP_CPU
);
6497 cpu_watchpoint_remove_all(s
, BP_CPU
);
6500 xcr0
= XSTATE_FP_MASK
;
6502 #ifdef CONFIG_USER_ONLY
6503 /* Enable all the features for user-mode. */
6504 if (env
->features
[FEAT_1_EDX
] & CPUID_SSE
) {
6505 xcr0
|= XSTATE_SSE_MASK
;
6507 for (i
= 2; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
6508 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
6509 if (!((1 << i
) & CPUID_XSTATE_XCR0_MASK
)) {
6512 if (env
->features
[esa
->feature
] & esa
->bits
) {
6517 if (env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
) {
6518 cr4
|= CR4_OSFXSR_MASK
| CR4_OSXSAVE_MASK
;
6520 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_FSGSBASE
) {
6521 cr4
|= CR4_FSGSBASE_MASK
;
6526 cpu_x86_update_cr4(env
, cr4
);
6529 * SDM 11.11.5 requires:
6530 * - IA32_MTRR_DEF_TYPE MSR.E = 0
6531 * - IA32_MTRR_PHYSMASKn.V = 0
6532 * All other bits are undefined. For simplification, zero it all.
6534 env
->mtrr_deftype
= 0;
6535 memset(env
->mtrr_var
, 0, sizeof(env
->mtrr_var
));
6536 memset(env
->mtrr_fixed
, 0, sizeof(env
->mtrr_fixed
));
6538 env
->interrupt_injected
= -1;
6539 env
->exception_nr
= -1;
6540 env
->exception_pending
= 0;
6541 env
->exception_injected
= 0;
6542 env
->exception_has_payload
= false;
6543 env
->exception_payload
= 0;
6544 env
->nmi_injected
= false;
6545 env
->triple_fault_pending
= false;
6546 #if !defined(CONFIG_USER_ONLY)
6547 /* We hard-wire the BSP to the first CPU. */
6548 apic_designate_bsp(cpu
->apic_state
, s
->cpu_index
== 0);
6550 s
->halted
= !cpu_is_bsp(cpu
);
6552 if (kvm_enabled()) {
6553 kvm_arch_reset_vcpu(cpu
);
6556 x86_cpu_set_sgxlepubkeyhash(env
);
6558 env
->amd_tsc_scale_msr
= MSR_AMD64_TSC_RATIO_DEFAULT
;
6563 void x86_cpu_after_reset(X86CPU
*cpu
)
6565 #ifndef CONFIG_USER_ONLY
6566 if (kvm_enabled()) {
6567 kvm_arch_after_reset_vcpu(cpu
);
6570 if (cpu
->apic_state
) {
6571 device_cold_reset(cpu
->apic_state
);
6576 static void mce_init(X86CPU
*cpu
)
6578 CPUX86State
*cenv
= &cpu
->env
;
6581 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
6582 && (cenv
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
6583 (CPUID_MCE
| CPUID_MCA
)) {
6584 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
|
6585 (cpu
->enable_lmce
? MCG_LMCE_P
: 0);
6586 cenv
->mcg_ctl
= ~(uint64_t)0;
6587 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
6588 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
6593 static void x86_cpu_adjust_level(X86CPU
*cpu
, uint32_t *min
, uint32_t value
)
6600 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6601 static void x86_cpu_adjust_feat_level(X86CPU
*cpu
, FeatureWord w
)
6603 CPUX86State
*env
= &cpu
->env
;
6604 FeatureWordInfo
*fi
= &feature_word_info
[w
];
6605 uint32_t eax
= fi
->cpuid
.eax
;
6606 uint32_t region
= eax
& 0xF0000000;
6608 assert(feature_word_info
[w
].type
== CPUID_FEATURE_WORD
);
6609 if (!env
->features
[w
]) {
6615 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, eax
);
6618 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, eax
);
6621 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel2
, eax
);
6626 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level_func7
,
6631 /* Calculate XSAVE components based on the configured CPU feature flags */
6632 static void x86_cpu_enable_xsave_components(X86CPU
*cpu
)
6634 CPUX86State
*env
= &cpu
->env
;
6637 static bool request_perm
;
6639 if (!(env
->features
[FEAT_1_ECX
] & CPUID_EXT_XSAVE
)) {
6640 env
->features
[FEAT_XSAVE_XCR0_LO
] = 0;
6641 env
->features
[FEAT_XSAVE_XCR0_HI
] = 0;
6646 for (i
= 0; i
< ARRAY_SIZE(x86_ext_save_areas
); i
++) {
6647 const ExtSaveArea
*esa
= &x86_ext_save_areas
[i
];
6648 if (env
->features
[esa
->feature
] & esa
->bits
) {
6649 mask
|= (1ULL << i
);
6653 /* Only request permission for first vcpu */
6654 if (kvm_enabled() && !request_perm
) {
6655 kvm_request_xsave_components(cpu
, mask
);
6656 request_perm
= true;
6659 env
->features
[FEAT_XSAVE_XCR0_LO
] = mask
& CPUID_XSTATE_XCR0_MASK
;
6660 env
->features
[FEAT_XSAVE_XCR0_HI
] = mask
>> 32;
6661 env
->features
[FEAT_XSAVE_XSS_LO
] = mask
& CPUID_XSTATE_XSS_MASK
;
6662 env
->features
[FEAT_XSAVE_XSS_HI
] = mask
>> 32;
6665 /***** Steps involved on loading and filtering CPUID data
6667 * When initializing and realizing a CPU object, the steps
6668 * involved in setting up CPUID data are:
6670 * 1) Loading CPU model definition (X86CPUDefinition). This is
6671 * implemented by x86_cpu_load_model() and should be completely
6672 * transparent, as it is done automatically by instance_init.
6673 * No code should need to look at X86CPUDefinition structs
6674 * outside instance_init.
6676 * 2) CPU expansion. This is done by realize before CPUID
6677 * filtering, and will make sure host/accelerator data is
6678 * loaded for CPU models that depend on host capabilities
6679 * (e.g. "host"). Done by x86_cpu_expand_features().
6681 * 3) CPUID filtering. This initializes extra data related to
6682 * CPUID, and checks if the host supports all capabilities
6683 * required by the CPU. Runnability of a CPU model is
6684 * determined at this step. Done by x86_cpu_filter_features().
6686 * Some operations don't require all steps to be performed.
6689 * - CPU instance creation (instance_init) will run only CPU
6690 * model loading. CPU expansion can't run at instance_init-time
6691 * because host/accelerator data may be not available yet.
6692 * - CPU realization will perform both CPU model expansion and CPUID
6693 * filtering, and return an error in case one of them fails.
6694 * - query-cpu-definitions needs to run all 3 steps. It needs
6695 * to run CPUID filtering, as the 'unavailable-features'
6696 * field is set based on the filtering results.
6697 * - The query-cpu-model-expansion QMP command only needs to run
6698 * CPU model loading and CPU expansion. It should not filter
6699 * any CPUID data based on host capabilities.
6702 /* Expand CPU configuration data, based on configured features
6703 * and host/accelerator capabilities when appropriate.
6705 void x86_cpu_expand_features(X86CPU
*cpu
, Error
**errp
)
6707 CPUX86State
*env
= &cpu
->env
;
6712 for (l
= plus_features
; l
; l
= l
->next
) {
6713 const char *prop
= l
->data
;
6714 if (!object_property_set_bool(OBJECT(cpu
), prop
, true, errp
)) {
6719 for (l
= minus_features
; l
; l
= l
->next
) {
6720 const char *prop
= l
->data
;
6721 if (!object_property_set_bool(OBJECT(cpu
), prop
, false, errp
)) {
6726 /*TODO: Now cpu->max_features doesn't overwrite features
6727 * set using QOM properties, and we can convert
6728 * plus_features & minus_features to global properties
6729 * inside x86_cpu_parse_featurestr() too.
6731 if (cpu
->max_features
) {
6732 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
6733 /* Override only features that weren't set explicitly
6737 x86_cpu_get_supported_feature_word(w
, cpu
->migratable
) &
6738 ~env
->user_features
[w
] &
6739 ~feature_word_info
[w
].no_autoenable_flags
;
6743 for (i
= 0; i
< ARRAY_SIZE(feature_dependencies
); i
++) {
6744 FeatureDep
*d
= &feature_dependencies
[i
];
6745 if (!(env
->features
[d
->from
.index
] & d
->from
.mask
)) {
6746 uint64_t unavailable_features
= env
->features
[d
->to
.index
] & d
->to
.mask
;
6748 /* Not an error unless the dependent feature was added explicitly. */
6749 mark_unavailable_features(cpu
, d
->to
.index
,
6750 unavailable_features
& env
->user_features
[d
->to
.index
],
6751 "This feature depends on other features that were not requested");
6753 env
->features
[d
->to
.index
] &= ~unavailable_features
;
6757 if (!kvm_enabled() || !cpu
->expose_kvm
) {
6758 env
->features
[FEAT_KVM
] = 0;
6761 x86_cpu_enable_xsave_components(cpu
);
6763 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6764 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_EBX
);
6765 if (cpu
->full_cpuid_auto_level
) {
6766 x86_cpu_adjust_feat_level(cpu
, FEAT_1_EDX
);
6767 x86_cpu_adjust_feat_level(cpu
, FEAT_1_ECX
);
6768 x86_cpu_adjust_feat_level(cpu
, FEAT_6_EAX
);
6769 x86_cpu_adjust_feat_level(cpu
, FEAT_7_0_ECX
);
6770 x86_cpu_adjust_feat_level(cpu
, FEAT_7_1_EAX
);
6771 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_EDX
);
6772 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0001_ECX
);
6773 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0007_EDX
);
6774 x86_cpu_adjust_feat_level(cpu
, FEAT_8000_0008_EBX
);
6775 x86_cpu_adjust_feat_level(cpu
, FEAT_C000_0001_EDX
);
6776 x86_cpu_adjust_feat_level(cpu
, FEAT_SVM
);
6777 x86_cpu_adjust_feat_level(cpu
, FEAT_XSAVE
);
6779 /* Intel Processor Trace requires CPUID[0x14] */
6780 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
)) {
6781 if (cpu
->intel_pt_auto_level
) {
6782 x86_cpu_adjust_level(cpu
, &cpu
->env
.cpuid_min_level
, 0x14);
6783 } else if (cpu
->env
.cpuid_min_level
< 0x14) {
6784 mark_unavailable_features(cpu
, FEAT_7_0_EBX
,
6785 CPUID_7_0_EBX_INTEL_PT
,
6786 "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
6791 * Intel CPU topology with multi-dies support requires CPUID[0x1F].
6792 * For AMD Rome/Milan, cpuid level is 0x10, and guest OS should detect
6793 * extended toplogy by leaf 0xB. Only adjust it for Intel CPU, unless
6794 * cpu->vendor_cpuid_only has been unset for compatibility with older
6797 if ((env
->nr_dies
> 1) &&
6798 (IS_INTEL_CPU(env
) || !cpu
->vendor_cpuid_only
)) {
6799 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, 0x1F);
6802 /* SVM requires CPUID[0x8000000A] */
6803 if (env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_SVM
) {
6804 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000000A);
6807 /* SEV requires CPUID[0x8000001F] */
6808 if (sev_enabled()) {
6809 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x8000001F);
6812 if (env
->features
[FEAT_8000_0021_EAX
]) {
6813 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_xlevel
, 0x80000021);
6816 /* SGX requires CPUID[0x12] for EPC enumeration */
6817 if (env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_SGX
) {
6818 x86_cpu_adjust_level(cpu
, &env
->cpuid_min_level
, 0x12);
6822 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6823 if (env
->cpuid_level_func7
== UINT32_MAX
) {
6824 env
->cpuid_level_func7
= env
->cpuid_min_level_func7
;
6826 if (env
->cpuid_level
== UINT32_MAX
) {
6827 env
->cpuid_level
= env
->cpuid_min_level
;
6829 if (env
->cpuid_xlevel
== UINT32_MAX
) {
6830 env
->cpuid_xlevel
= env
->cpuid_min_xlevel
;
6832 if (env
->cpuid_xlevel2
== UINT32_MAX
) {
6833 env
->cpuid_xlevel2
= env
->cpuid_min_xlevel2
;
6836 if (kvm_enabled()) {
6837 kvm_hyperv_expand_features(cpu
, errp
);
6842 * Finishes initialization of CPUID data, filters CPU feature
6843 * words based on host availability of each feature.
6845 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6847 static void x86_cpu_filter_features(X86CPU
*cpu
, bool verbose
)
6849 CPUX86State
*env
= &cpu
->env
;
6851 const char *prefix
= NULL
;
6854 prefix
= accel_uses_host_cpuid()
6855 ? "host doesn't support requested feature"
6856 : "TCG doesn't support requested feature";
6859 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
6860 uint64_t host_feat
=
6861 x86_cpu_get_supported_feature_word(w
, false);
6862 uint64_t requested_features
= env
->features
[w
];
6863 uint64_t unavailable_features
= requested_features
& ~host_feat
;
6864 mark_unavailable_features(cpu
, w
, unavailable_features
, prefix
);
6867 if ((env
->features
[FEAT_7_0_EBX
] & CPUID_7_0_EBX_INTEL_PT
) &&
6869 KVMState
*s
= CPU(cpu
)->kvm_state
;
6870 uint32_t eax_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EAX
);
6871 uint32_t ebx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_EBX
);
6872 uint32_t ecx_0
= kvm_arch_get_supported_cpuid(s
, 0x14, 0, R_ECX
);
6873 uint32_t eax_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EAX
);
6874 uint32_t ebx_1
= kvm_arch_get_supported_cpuid(s
, 0x14, 1, R_EBX
);
6877 ((ebx_0
& INTEL_PT_MINIMAL_EBX
) != INTEL_PT_MINIMAL_EBX
) ||
6878 ((ecx_0
& INTEL_PT_MINIMAL_ECX
) != INTEL_PT_MINIMAL_ECX
) ||
6879 ((eax_1
& INTEL_PT_MTC_BITMAP
) != INTEL_PT_MTC_BITMAP
) ||
6880 ((eax_1
& INTEL_PT_ADDR_RANGES_NUM_MASK
) <
6881 INTEL_PT_ADDR_RANGES_NUM
) ||
6882 ((ebx_1
& (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) !=
6883 (INTEL_PT_PSB_BITMAP
| INTEL_PT_CYCLE_BITMAP
)) ||
6884 ((ecx_0
& CPUID_14_0_ECX_LIP
) !=
6885 (env
->features
[FEAT_14_0_ECX
] & CPUID_14_0_ECX_LIP
))) {
6887 * Processor Trace capabilities aren't configurable, so if the
6888 * host can't emulate the capabilities we report on
6889 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6891 mark_unavailable_features(cpu
, FEAT_7_0_EBX
, CPUID_7_0_EBX_INTEL_PT
, prefix
);
6896 static void x86_cpu_hyperv_realize(X86CPU
*cpu
)
6900 /* Hyper-V vendor id */
6901 if (!cpu
->hyperv_vendor
) {
6902 object_property_set_str(OBJECT(cpu
), "hv-vendor-id", "Microsoft Hv",
6905 len
= strlen(cpu
->hyperv_vendor
);
6907 warn_report("hv-vendor-id truncated to 12 characters");
6910 memset(cpu
->hyperv_vendor_id
, 0, 12);
6911 memcpy(cpu
->hyperv_vendor_id
, cpu
->hyperv_vendor
, len
);
6913 /* 'Hv#1' interface identification*/
6914 cpu
->hyperv_interface_id
[0] = 0x31237648;
6915 cpu
->hyperv_interface_id
[1] = 0;
6916 cpu
->hyperv_interface_id
[2] = 0;
6917 cpu
->hyperv_interface_id
[3] = 0;
6919 /* Hypervisor implementation limits */
6920 cpu
->hyperv_limits
[0] = 64;
6921 cpu
->hyperv_limits
[1] = 0;
6922 cpu
->hyperv_limits
[2] = 0;
6925 static void x86_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
6927 CPUState
*cs
= CPU(dev
);
6928 X86CPU
*cpu
= X86_CPU(dev
);
6929 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
6930 CPUX86State
*env
= &cpu
->env
;
6931 Error
*local_err
= NULL
;
6932 static bool ht_warned
;
6933 unsigned requested_lbr_fmt
;
6935 /* Use pc-relative instructions in system-mode */
6936 #ifndef CONFIG_USER_ONLY
6937 cs
->tcg_cflags
|= CF_PCREL
;
6940 if (cpu
->apic_id
== UNASSIGNED_APIC_ID
) {
6941 error_setg(errp
, "apic-id property was not initialized properly");
6946 * Process Hyper-V enlightenments.
6947 * Note: this currently has to happen before the expansion of CPU features.
6949 x86_cpu_hyperv_realize(cpu
);
6951 x86_cpu_expand_features(cpu
, &local_err
);
6957 * Override env->features[FEAT_PERF_CAPABILITIES].LBR_FMT
6958 * with user-provided setting.
6960 if (cpu
->lbr_fmt
!= ~PERF_CAP_LBR_FMT
) {
6961 if ((cpu
->lbr_fmt
& PERF_CAP_LBR_FMT
) != cpu
->lbr_fmt
) {
6962 error_setg(errp
, "invalid lbr-fmt");
6965 env
->features
[FEAT_PERF_CAPABILITIES
] &= ~PERF_CAP_LBR_FMT
;
6966 env
->features
[FEAT_PERF_CAPABILITIES
] |= cpu
->lbr_fmt
;
6970 * vPMU LBR is supported when 1) KVM is enabled 2) Option pmu=on and
6971 * 3)vPMU LBR format matches that of host setting.
6974 env
->features
[FEAT_PERF_CAPABILITIES
] & PERF_CAP_LBR_FMT
;
6975 if (requested_lbr_fmt
&& kvm_enabled()) {
6976 uint64_t host_perf_cap
=
6977 x86_cpu_get_supported_feature_word(FEAT_PERF_CAPABILITIES
, false);
6978 unsigned host_lbr_fmt
= host_perf_cap
& PERF_CAP_LBR_FMT
;
6980 if (!cpu
->enable_pmu
) {
6981 error_setg(errp
, "vPMU: LBR is unsupported without pmu=on");
6984 if (requested_lbr_fmt
!= host_lbr_fmt
) {
6985 error_setg(errp
, "vPMU: the lbr-fmt value (0x%x) does not match "
6986 "the host value (0x%x).",
6987 requested_lbr_fmt
, host_lbr_fmt
);
6992 x86_cpu_filter_features(cpu
, cpu
->check_cpuid
|| cpu
->enforce_cpuid
);
6994 if (cpu
->enforce_cpuid
&& x86_cpu_have_filtered_features(cpu
)) {
6995 error_setg(&local_err
,
6996 accel_uses_host_cpuid() ?
6997 "Host doesn't support requested features" :
6998 "TCG doesn't support requested features");
7002 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
7005 if (IS_AMD_CPU(env
)) {
7006 env
->features
[FEAT_8000_0001_EDX
] &= ~CPUID_EXT2_AMD_ALIASES
;
7007 env
->features
[FEAT_8000_0001_EDX
] |= (env
->features
[FEAT_1_EDX
]
7008 & CPUID_EXT2_AMD_ALIASES
);
7011 x86_cpu_set_sgxlepubkeyhash(env
);
7014 * note: the call to the framework needs to happen after feature expansion,
7015 * but before the checks/modifications to ucode_rev, mwait, phys_bits.
7016 * These may be set by the accel-specific code,
7017 * and the results are subsequently checked / assumed in this function.
7019 cpu_exec_realizefn(cs
, &local_err
);
7020 if (local_err
!= NULL
) {
7021 error_propagate(errp
, local_err
);
7025 if (xcc
->host_cpuid_required
&& !accel_uses_host_cpuid()) {
7026 g_autofree
char *name
= x86_cpu_class_get_model_name(xcc
);
7027 error_setg(&local_err
, "CPU model '%s' requires KVM or HVF", name
);
7031 if (cpu
->ucode_rev
== 0) {
7033 * The default is the same as KVM's. Note that this check
7034 * needs to happen after the evenual setting of ucode_rev in
7035 * accel-specific code in cpu_exec_realizefn.
7037 if (IS_AMD_CPU(env
)) {
7038 cpu
->ucode_rev
= 0x01000065;
7040 cpu
->ucode_rev
= 0x100000000ULL
;
7045 * mwait extended info: needed for Core compatibility
7046 * We always wake on interrupt even if host does not have the capability.
7048 * requires the accel-specific code in cpu_exec_realizefn to
7049 * have already acquired the CPUID data into cpu->mwait.
7051 cpu
->mwait
.ecx
|= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
7053 /* For 64bit systems think about the number of physical bits to present.
7054 * ideally this should be the same as the host; anything other than matching
7055 * the host can cause incorrect guest behaviour.
7056 * QEMU used to pick the magic value of 40 bits that corresponds to
7057 * consumer AMD devices but nothing else.
7059 * Note that this code assumes features expansion has already been done
7060 * (as it checks for CPUID_EXT2_LM), and also assumes that potential
7061 * phys_bits adjustments to match the host have been already done in
7062 * accel-specific code in cpu_exec_realizefn.
7064 if (env
->features
[FEAT_8000_0001_EDX
] & CPUID_EXT2_LM
) {
7065 if (cpu
->phys_bits
&&
7066 (cpu
->phys_bits
> TARGET_PHYS_ADDR_SPACE_BITS
||
7067 cpu
->phys_bits
< 32)) {
7068 error_setg(errp
, "phys-bits should be between 32 and %u "
7070 TARGET_PHYS_ADDR_SPACE_BITS
, cpu
->phys_bits
);
7074 * 0 means it was not explicitly set by the user (or by machine
7075 * compat_props or by the host code in host-cpu.c).
7076 * In this case, the default is the value used by TCG (40).
7078 if (cpu
->phys_bits
== 0) {
7079 cpu
->phys_bits
= TCG_PHYS_ADDR_BITS
;
7082 /* For 32 bit systems don't use the user set value, but keep
7083 * phys_bits consistent with what we tell the guest.
7085 if (cpu
->phys_bits
!= 0) {
7086 error_setg(errp
, "phys-bits is not user-configurable in 32 bit");
7090 if (env
->features
[FEAT_1_EDX
] & CPUID_PSE36
) {
7091 cpu
->phys_bits
= 36;
7093 cpu
->phys_bits
= 32;
7097 /* Cache information initialization */
7098 if (!cpu
->legacy_cache
) {
7099 const CPUCaches
*cache_info
=
7100 x86_cpu_get_versioned_cache_info(cpu
, xcc
->model
);
7102 if (!xcc
->model
|| !cache_info
) {
7103 g_autofree
char *name
= x86_cpu_class_get_model_name(xcc
);
7105 "CPU model '%s' doesn't support legacy-cache=off", name
);
7108 env
->cache_info_cpuid2
= env
->cache_info_cpuid4
= env
->cache_info_amd
=
7111 /* Build legacy cache information */
7112 env
->cache_info_cpuid2
.l1d_cache
= &legacy_l1d_cache
;
7113 env
->cache_info_cpuid2
.l1i_cache
= &legacy_l1i_cache
;
7114 env
->cache_info_cpuid2
.l2_cache
= &legacy_l2_cache_cpuid2
;
7115 env
->cache_info_cpuid2
.l3_cache
= &legacy_l3_cache
;
7117 env
->cache_info_cpuid4
.l1d_cache
= &legacy_l1d_cache
;
7118 env
->cache_info_cpuid4
.l1i_cache
= &legacy_l1i_cache
;
7119 env
->cache_info_cpuid4
.l2_cache
= &legacy_l2_cache
;
7120 env
->cache_info_cpuid4
.l3_cache
= &legacy_l3_cache
;
7122 env
->cache_info_amd
.l1d_cache
= &legacy_l1d_cache_amd
;
7123 env
->cache_info_amd
.l1i_cache
= &legacy_l1i_cache_amd
;
7124 env
->cache_info_amd
.l2_cache
= &legacy_l2_cache_amd
;
7125 env
->cache_info_amd
.l3_cache
= &legacy_l3_cache
;
7128 #ifndef CONFIG_USER_ONLY
7129 MachineState
*ms
= MACHINE(qdev_get_machine());
7130 qemu_register_reset(x86_cpu_machine_reset_cb
, cpu
);
7132 if (cpu
->env
.features
[FEAT_1_EDX
] & CPUID_APIC
|| ms
->smp
.cpus
> 1) {
7133 x86_cpu_apic_create(cpu
, &local_err
);
7134 if (local_err
!= NULL
) {
7145 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
7146 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
7147 * based on inputs (sockets,cores,threads), it is still better to give
7150 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
7151 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
7153 if (IS_AMD_CPU(env
) &&
7154 !(env
->features
[FEAT_8000_0001_ECX
] & CPUID_EXT3_TOPOEXT
) &&
7155 cs
->nr_threads
> 1 && !ht_warned
) {
7156 warn_report("This family of AMD CPU doesn't support "
7157 "hyperthreading(%d)",
7159 error_printf("Please configure -smp options properly"
7160 " or try enabling topoext feature.\n");
7164 #ifndef CONFIG_USER_ONLY
7165 x86_cpu_apic_realize(cpu
, &local_err
);
7166 if (local_err
!= NULL
) {
7169 #endif /* !CONFIG_USER_ONLY */
7172 xcc
->parent_realize(dev
, &local_err
);
7175 if (local_err
!= NULL
) {
7176 error_propagate(errp
, local_err
);
7181 static void x86_cpu_unrealizefn(DeviceState
*dev
)
7183 X86CPU
*cpu
= X86_CPU(dev
);
7184 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(dev
);
7186 #ifndef CONFIG_USER_ONLY
7187 cpu_remove_sync(CPU(dev
));
7188 qemu_unregister_reset(x86_cpu_machine_reset_cb
, dev
);
7191 if (cpu
->apic_state
) {
7192 object_unparent(OBJECT(cpu
->apic_state
));
7193 cpu
->apic_state
= NULL
;
7196 xcc
->parent_unrealize(dev
);
7199 typedef struct BitProperty
{
7204 static void x86_cpu_get_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
7205 void *opaque
, Error
**errp
)
7207 X86CPU
*cpu
= X86_CPU(obj
);
7208 BitProperty
*fp
= opaque
;
7209 uint64_t f
= cpu
->env
.features
[fp
->w
];
7210 bool value
= (f
& fp
->mask
) == fp
->mask
;
7211 visit_type_bool(v
, name
, &value
, errp
);
7214 static void x86_cpu_set_bit_prop(Object
*obj
, Visitor
*v
, const char *name
,
7215 void *opaque
, Error
**errp
)
7217 DeviceState
*dev
= DEVICE(obj
);
7218 X86CPU
*cpu
= X86_CPU(obj
);
7219 BitProperty
*fp
= opaque
;
7222 if (dev
->realized
) {
7223 qdev_prop_set_after_realize(dev
, name
, errp
);
7227 if (!visit_type_bool(v
, name
, &value
, errp
)) {
7232 cpu
->env
.features
[fp
->w
] |= fp
->mask
;
7234 cpu
->env
.features
[fp
->w
] &= ~fp
->mask
;
7236 cpu
->env
.user_features
[fp
->w
] |= fp
->mask
;
7239 /* Register a boolean property to get/set a single bit in a uint32_t field.
7241 * The same property name can be registered multiple times to make it affect
7242 * multiple bits in the same FeatureWord. In that case, the getter will return
7243 * true only if all bits are set.
7245 static void x86_cpu_register_bit_prop(X86CPUClass
*xcc
,
7246 const char *prop_name
,
7250 ObjectClass
*oc
= OBJECT_CLASS(xcc
);
7253 uint64_t mask
= (1ULL << bitnr
);
7255 op
= object_class_property_find(oc
, prop_name
);
7261 fp
= g_new0(BitProperty
, 1);
7264 object_class_property_add(oc
, prop_name
, "bool",
7265 x86_cpu_get_bit_prop
,
7266 x86_cpu_set_bit_prop
,
7271 static void x86_cpu_register_feature_bit_props(X86CPUClass
*xcc
,
7275 FeatureWordInfo
*fi
= &feature_word_info
[w
];
7276 const char *name
= fi
->feat_names
[bitnr
];
7282 /* Property names should use "-" instead of "_".
7283 * Old names containing underscores are registered as aliases
7284 * using object_property_add_alias()
7286 assert(!strchr(name
, '_'));
7287 /* aliases don't use "|" delimiters anymore, they are registered
7288 * manually using object_property_add_alias() */
7289 assert(!strchr(name
, '|'));
7290 x86_cpu_register_bit_prop(xcc
, name
, w
, bitnr
);
7293 static void x86_cpu_post_initfn(Object
*obj
)
7295 accel_cpu_instance_init(CPU(obj
));
7298 static void x86_cpu_initfn(Object
*obj
)
7300 X86CPU
*cpu
= X86_CPU(obj
);
7301 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(obj
);
7302 CPUX86State
*env
= &cpu
->env
;
7305 cpu_set_cpustate_pointers(cpu
);
7307 object_property_add(obj
, "feature-words", "X86CPUFeatureWordInfo",
7308 x86_cpu_get_feature_words
,
7309 NULL
, NULL
, (void *)env
->features
);
7310 object_property_add(obj
, "filtered-features", "X86CPUFeatureWordInfo",
7311 x86_cpu_get_feature_words
,
7312 NULL
, NULL
, (void *)cpu
->filtered_features
);
7314 object_property_add_alias(obj
, "sse3", obj
, "pni");
7315 object_property_add_alias(obj
, "pclmuldq", obj
, "pclmulqdq");
7316 object_property_add_alias(obj
, "sse4-1", obj
, "sse4.1");
7317 object_property_add_alias(obj
, "sse4-2", obj
, "sse4.2");
7318 object_property_add_alias(obj
, "xd", obj
, "nx");
7319 object_property_add_alias(obj
, "ffxsr", obj
, "fxsr-opt");
7320 object_property_add_alias(obj
, "i64", obj
, "lm");
7322 object_property_add_alias(obj
, "ds_cpl", obj
, "ds-cpl");
7323 object_property_add_alias(obj
, "tsc_adjust", obj
, "tsc-adjust");
7324 object_property_add_alias(obj
, "fxsr_opt", obj
, "fxsr-opt");
7325 object_property_add_alias(obj
, "lahf_lm", obj
, "lahf-lm");
7326 object_property_add_alias(obj
, "cmp_legacy", obj
, "cmp-legacy");
7327 object_property_add_alias(obj
, "nodeid_msr", obj
, "nodeid-msr");
7328 object_property_add_alias(obj
, "perfctr_core", obj
, "perfctr-core");
7329 object_property_add_alias(obj
, "perfctr_nb", obj
, "perfctr-nb");
7330 object_property_add_alias(obj
, "kvm_nopiodelay", obj
, "kvm-nopiodelay");
7331 object_property_add_alias(obj
, "kvm_mmu", obj
, "kvm-mmu");
7332 object_property_add_alias(obj
, "kvm_asyncpf", obj
, "kvm-asyncpf");
7333 object_property_add_alias(obj
, "kvm_asyncpf_int", obj
, "kvm-asyncpf-int");
7334 object_property_add_alias(obj
, "kvm_steal_time", obj
, "kvm-steal-time");
7335 object_property_add_alias(obj
, "kvm_pv_eoi", obj
, "kvm-pv-eoi");
7336 object_property_add_alias(obj
, "kvm_pv_unhalt", obj
, "kvm-pv-unhalt");
7337 object_property_add_alias(obj
, "kvm_poll_control", obj
, "kvm-poll-control");
7338 object_property_add_alias(obj
, "svm_lock", obj
, "svm-lock");
7339 object_property_add_alias(obj
, "nrip_save", obj
, "nrip-save");
7340 object_property_add_alias(obj
, "tsc_scale", obj
, "tsc-scale");
7341 object_property_add_alias(obj
, "vmcb_clean", obj
, "vmcb-clean");
7342 object_property_add_alias(obj
, "pause_filter", obj
, "pause-filter");
7343 object_property_add_alias(obj
, "sse4_1", obj
, "sse4.1");
7344 object_property_add_alias(obj
, "sse4_2", obj
, "sse4.2");
7346 object_property_add_alias(obj
, "hv-apicv", obj
, "hv-avic");
7347 cpu
->lbr_fmt
= ~PERF_CAP_LBR_FMT
;
7348 object_property_add_alias(obj
, "lbr_fmt", obj
, "lbr-fmt");
7351 x86_cpu_load_model(cpu
, xcc
->model
);
7355 static int64_t x86_cpu_get_arch_id(CPUState
*cs
)
7357 X86CPU
*cpu
= X86_CPU(cs
);
7359 return cpu
->apic_id
;
7362 #if !defined(CONFIG_USER_ONLY)
7363 static bool x86_cpu_get_paging_enabled(const CPUState
*cs
)
7365 X86CPU
*cpu
= X86_CPU(cs
);
7367 return cpu
->env
.cr
[0] & CR0_PG_MASK
;
7369 #endif /* !CONFIG_USER_ONLY */
7371 static void x86_cpu_set_pc(CPUState
*cs
, vaddr value
)
7373 X86CPU
*cpu
= X86_CPU(cs
);
7375 cpu
->env
.eip
= value
;
7378 static vaddr
x86_cpu_get_pc(CPUState
*cs
)
7380 X86CPU
*cpu
= X86_CPU(cs
);
7382 /* Match cpu_get_tb_cpu_state. */
7383 return cpu
->env
.eip
+ cpu
->env
.segs
[R_CS
].base
;
7386 int x86_cpu_pending_interrupt(CPUState
*cs
, int interrupt_request
)
7388 X86CPU
*cpu
= X86_CPU(cs
);
7389 CPUX86State
*env
= &cpu
->env
;
7391 #if !defined(CONFIG_USER_ONLY)
7392 if (interrupt_request
& CPU_INTERRUPT_POLL
) {
7393 return CPU_INTERRUPT_POLL
;
7396 if (interrupt_request
& CPU_INTERRUPT_SIPI
) {
7397 return CPU_INTERRUPT_SIPI
;
7400 if (env
->hflags2
& HF2_GIF_MASK
) {
7401 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
7402 !(env
->hflags
& HF_SMM_MASK
)) {
7403 return CPU_INTERRUPT_SMI
;
7404 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
7405 !(env
->hflags2
& HF2_NMI_MASK
)) {
7406 return CPU_INTERRUPT_NMI
;
7407 } else if (interrupt_request
& CPU_INTERRUPT_MCE
) {
7408 return CPU_INTERRUPT_MCE
;
7409 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
7410 (((env
->hflags2
& HF2_VINTR_MASK
) &&
7411 (env
->hflags2
& HF2_HIF_MASK
)) ||
7412 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
7413 (env
->eflags
& IF_MASK
&&
7414 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
7415 return CPU_INTERRUPT_HARD
;
7416 #if !defined(CONFIG_USER_ONLY)
7417 } else if (env
->hflags2
& HF2_VGIF_MASK
) {
7418 if((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
7419 (env
->eflags
& IF_MASK
) &&
7420 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
7421 return CPU_INTERRUPT_VIRQ
;
7430 static bool x86_cpu_has_work(CPUState
*cs
)
7432 return x86_cpu_pending_interrupt(cs
, cs
->interrupt_request
) != 0;
7435 static void x86_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
7437 X86CPU
*cpu
= X86_CPU(cs
);
7438 CPUX86State
*env
= &cpu
->env
;
7440 info
->mach
= (env
->hflags
& HF_CS64_MASK
? bfd_mach_x86_64
7441 : env
->hflags
& HF_CS32_MASK
? bfd_mach_i386_i386
7442 : bfd_mach_i386_i8086
);
7444 info
->cap_arch
= CS_ARCH_X86
;
7445 info
->cap_mode
= (env
->hflags
& HF_CS64_MASK
? CS_MODE_64
7446 : env
->hflags
& HF_CS32_MASK
? CS_MODE_32
7448 info
->cap_insn_unit
= 1;
7449 info
->cap_insn_split
= 8;
7452 void x86_update_hflags(CPUX86State
*env
)
7455 #define HFLAG_COPY_MASK \
7456 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7457 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7458 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7459 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7461 hflags
= env
->hflags
& HFLAG_COPY_MASK
;
7462 hflags
|= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
7463 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
7464 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
7465 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
7466 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
7468 if (env
->cr
[4] & CR4_OSFXSR_MASK
) {
7469 hflags
|= HF_OSFXSR_MASK
;
7472 if (env
->efer
& MSR_EFER_LMA
) {
7473 hflags
|= HF_LMA_MASK
;
7476 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
7477 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
7479 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
7480 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
7481 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
7482 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
7483 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
7484 !(hflags
& HF_CS32_MASK
)) {
7485 hflags
|= HF_ADDSEG_MASK
;
7487 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
7488 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
7491 env
->hflags
= hflags
;
7494 static Property x86_cpu_properties
[] = {
7495 #ifdef CONFIG_USER_ONLY
7496 /* apic_id = 0 by default for *-user, see commit 9886e834 */
7497 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, 0),
7498 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, 0),
7499 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, 0),
7500 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, 0),
7501 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, 0),
7503 DEFINE_PROP_UINT32("apic-id", X86CPU
, apic_id
, UNASSIGNED_APIC_ID
),
7504 DEFINE_PROP_INT32("thread-id", X86CPU
, thread_id
, -1),
7505 DEFINE_PROP_INT32("core-id", X86CPU
, core_id
, -1),
7506 DEFINE_PROP_INT32("die-id", X86CPU
, die_id
, -1),
7507 DEFINE_PROP_INT32("socket-id", X86CPU
, socket_id
, -1),
7509 DEFINE_PROP_INT32("node-id", X86CPU
, node_id
, CPU_UNSET_NUMA_NODE_ID
),
7510 DEFINE_PROP_BOOL("pmu", X86CPU
, enable_pmu
, false),
7511 DEFINE_PROP_UINT64_CHECKMASK("lbr-fmt", X86CPU
, lbr_fmt
, PERF_CAP_LBR_FMT
),
7513 DEFINE_PROP_UINT32("hv-spinlocks", X86CPU
, hyperv_spinlock_attempts
,
7514 HYPERV_SPINLOCK_NEVER_NOTIFY
),
7515 DEFINE_PROP_BIT64("hv-relaxed", X86CPU
, hyperv_features
,
7516 HYPERV_FEAT_RELAXED
, 0),
7517 DEFINE_PROP_BIT64("hv-vapic", X86CPU
, hyperv_features
,
7518 HYPERV_FEAT_VAPIC
, 0),
7519 DEFINE_PROP_BIT64("hv-time", X86CPU
, hyperv_features
,
7520 HYPERV_FEAT_TIME
, 0),
7521 DEFINE_PROP_BIT64("hv-crash", X86CPU
, hyperv_features
,
7522 HYPERV_FEAT_CRASH
, 0),
7523 DEFINE_PROP_BIT64("hv-reset", X86CPU
, hyperv_features
,
7524 HYPERV_FEAT_RESET
, 0),
7525 DEFINE_PROP_BIT64("hv-vpindex", X86CPU
, hyperv_features
,
7526 HYPERV_FEAT_VPINDEX
, 0),
7527 DEFINE_PROP_BIT64("hv-runtime", X86CPU
, hyperv_features
,
7528 HYPERV_FEAT_RUNTIME
, 0),
7529 DEFINE_PROP_BIT64("hv-synic", X86CPU
, hyperv_features
,
7530 HYPERV_FEAT_SYNIC
, 0),
7531 DEFINE_PROP_BIT64("hv-stimer", X86CPU
, hyperv_features
,
7532 HYPERV_FEAT_STIMER
, 0),
7533 DEFINE_PROP_BIT64("hv-frequencies", X86CPU
, hyperv_features
,
7534 HYPERV_FEAT_FREQUENCIES
, 0),
7535 DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU
, hyperv_features
,
7536 HYPERV_FEAT_REENLIGHTENMENT
, 0),
7537 DEFINE_PROP_BIT64("hv-tlbflush", X86CPU
, hyperv_features
,
7538 HYPERV_FEAT_TLBFLUSH
, 0),
7539 DEFINE_PROP_BIT64("hv-evmcs", X86CPU
, hyperv_features
,
7540 HYPERV_FEAT_EVMCS
, 0),
7541 DEFINE_PROP_BIT64("hv-ipi", X86CPU
, hyperv_features
,
7542 HYPERV_FEAT_IPI
, 0),
7543 DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU
, hyperv_features
,
7544 HYPERV_FEAT_STIMER_DIRECT
, 0),
7545 DEFINE_PROP_BIT64("hv-avic", X86CPU
, hyperv_features
,
7546 HYPERV_FEAT_AVIC
, 0),
7547 DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU
, hyperv_features
,
7548 HYPERV_FEAT_MSR_BITMAP
, 0),
7549 DEFINE_PROP_BIT64("hv-xmm-input", X86CPU
, hyperv_features
,
7550 HYPERV_FEAT_XMM_INPUT
, 0),
7551 DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU
, hyperv_features
,
7552 HYPERV_FEAT_TLBFLUSH_EXT
, 0),
7553 DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU
, hyperv_features
,
7554 HYPERV_FEAT_TLBFLUSH_DIRECT
, 0),
7555 DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU
,
7556 hyperv_no_nonarch_cs
, ON_OFF_AUTO_OFF
),
7557 DEFINE_PROP_BIT64("hv-syndbg", X86CPU
, hyperv_features
,
7558 HYPERV_FEAT_SYNDBG
, 0),
7559 DEFINE_PROP_BOOL("hv-passthrough", X86CPU
, hyperv_passthrough
, false),
7560 DEFINE_PROP_BOOL("hv-enforce-cpuid", X86CPU
, hyperv_enforce_cpuid
, false),
7562 /* WS2008R2 identify by default */
7563 DEFINE_PROP_UINT32("hv-version-id-build", X86CPU
, hyperv_ver_id_build
,
7565 DEFINE_PROP_UINT16("hv-version-id-major", X86CPU
, hyperv_ver_id_major
,
7567 DEFINE_PROP_UINT16("hv-version-id-minor", X86CPU
, hyperv_ver_id_minor
,
7569 DEFINE_PROP_UINT32("hv-version-id-spack", X86CPU
, hyperv_ver_id_sp
, 0),
7570 DEFINE_PROP_UINT8("hv-version-id-sbranch", X86CPU
, hyperv_ver_id_sb
, 0),
7571 DEFINE_PROP_UINT32("hv-version-id-snumber", X86CPU
, hyperv_ver_id_sn
, 0),
7573 DEFINE_PROP_BOOL("check", X86CPU
, check_cpuid
, true),
7574 DEFINE_PROP_BOOL("enforce", X86CPU
, enforce_cpuid
, false),
7575 DEFINE_PROP_BOOL("x-force-features", X86CPU
, force_features
, false),
7576 DEFINE_PROP_BOOL("kvm", X86CPU
, expose_kvm
, true),
7577 DEFINE_PROP_UINT32("phys-bits", X86CPU
, phys_bits
, 0),
7578 DEFINE_PROP_BOOL("host-phys-bits", X86CPU
, host_phys_bits
, false),
7579 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU
, host_phys_bits_limit
, 0),
7580 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU
, fill_mtrr_mask
, true),
7581 DEFINE_PROP_UINT32("level-func7", X86CPU
, env
.cpuid_level_func7
,
7583 DEFINE_PROP_UINT32("level", X86CPU
, env
.cpuid_level
, UINT32_MAX
),
7584 DEFINE_PROP_UINT32("xlevel", X86CPU
, env
.cpuid_xlevel
, UINT32_MAX
),
7585 DEFINE_PROP_UINT32("xlevel2", X86CPU
, env
.cpuid_xlevel2
, UINT32_MAX
),
7586 DEFINE_PROP_UINT32("min-level", X86CPU
, env
.cpuid_min_level
, 0),
7587 DEFINE_PROP_UINT32("min-xlevel", X86CPU
, env
.cpuid_min_xlevel
, 0),
7588 DEFINE_PROP_UINT32("min-xlevel2", X86CPU
, env
.cpuid_min_xlevel2
, 0),
7589 DEFINE_PROP_UINT64("ucode-rev", X86CPU
, ucode_rev
, 0),
7590 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU
, full_cpuid_auto_level
, true),
7591 DEFINE_PROP_STRING("hv-vendor-id", X86CPU
, hyperv_vendor
),
7592 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU
, enable_cpuid_0xb
, true),
7593 DEFINE_PROP_BOOL("x-vendor-cpuid-only", X86CPU
, vendor_cpuid_only
, true),
7594 DEFINE_PROP_BOOL("lmce", X86CPU
, enable_lmce
, false),
7595 DEFINE_PROP_BOOL("l3-cache", X86CPU
, enable_l3_cache
, true),
7596 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU
, kvm_no_smi_migration
,
7598 DEFINE_PROP_BOOL("kvm-pv-enforce-cpuid", X86CPU
, kvm_pv_enforce_cpuid
,
7600 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU
, vmware_cpuid_freq
, true),
7601 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU
, expose_tcg
, true),
7602 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU
, migrate_smi_count
,
7605 * lecacy_cache defaults to true unless the CPU model provides its
7606 * own cache information (see x86_cpu_load_def()).
7608 DEFINE_PROP_BOOL("legacy-cache", X86CPU
, legacy_cache
, true),
7609 DEFINE_PROP_BOOL("xen-vapic", X86CPU
, xen_vapic
, false),
7612 * From "Requirements for Implementing the Microsoft
7613 * Hypervisor Interface":
7614 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7616 * "Starting with Windows Server 2012 and Windows 8, if
7617 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7618 * the hypervisor imposes no specific limit to the number of VPs.
7619 * In this case, Windows Server 2012 guest VMs may use more than
7620 * 64 VPs, up to the maximum supported number of processors applicable
7621 * to the specific Windows version being used."
7623 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU
, hv_max_vps
, -1),
7624 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU
, hyperv_synic_kvm_only
,
7626 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU
, intel_pt_auto_level
,
7628 DEFINE_PROP_END_OF_LIST()
7631 #ifndef CONFIG_USER_ONLY
7632 #include "hw/core/sysemu-cpu-ops.h"
7634 static const struct SysemuCPUOps i386_sysemu_ops
= {
7635 .get_memory_mapping
= x86_cpu_get_memory_mapping
,
7636 .get_paging_enabled
= x86_cpu_get_paging_enabled
,
7637 .get_phys_page_attrs_debug
= x86_cpu_get_phys_page_attrs_debug
,
7638 .asidx_from_attrs
= x86_asidx_from_attrs
,
7639 .get_crash_info
= x86_cpu_get_crash_info
,
7640 .write_elf32_note
= x86_cpu_write_elf32_note
,
7641 .write_elf64_note
= x86_cpu_write_elf64_note
,
7642 .write_elf32_qemunote
= x86_cpu_write_elf32_qemunote
,
7643 .write_elf64_qemunote
= x86_cpu_write_elf64_qemunote
,
7644 .legacy_vmsd
= &vmstate_x86_cpu
,
7648 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
7650 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
7651 CPUClass
*cc
= CPU_CLASS(oc
);
7652 DeviceClass
*dc
= DEVICE_CLASS(oc
);
7653 ResettableClass
*rc
= RESETTABLE_CLASS(oc
);
7656 device_class_set_parent_realize(dc
, x86_cpu_realizefn
,
7657 &xcc
->parent_realize
);
7658 device_class_set_parent_unrealize(dc
, x86_cpu_unrealizefn
,
7659 &xcc
->parent_unrealize
);
7660 device_class_set_props(dc
, x86_cpu_properties
);
7662 resettable_class_set_parent_phases(rc
, NULL
, x86_cpu_reset_hold
, NULL
,
7663 &xcc
->parent_phases
);
7664 cc
->reset_dump_flags
= CPU_DUMP_FPU
| CPU_DUMP_CCOP
;
7666 cc
->class_by_name
= x86_cpu_class_by_name
;
7667 cc
->parse_features
= x86_cpu_parse_featurestr
;
7668 cc
->has_work
= x86_cpu_has_work
;
7669 cc
->dump_state
= x86_cpu_dump_state
;
7670 cc
->set_pc
= x86_cpu_set_pc
;
7671 cc
->get_pc
= x86_cpu_get_pc
;
7672 cc
->gdb_read_register
= x86_cpu_gdb_read_register
;
7673 cc
->gdb_write_register
= x86_cpu_gdb_write_register
;
7674 cc
->get_arch_id
= x86_cpu_get_arch_id
;
7676 #ifndef CONFIG_USER_ONLY
7677 cc
->sysemu_ops
= &i386_sysemu_ops
;
7678 #endif /* !CONFIG_USER_ONLY */
7680 cc
->gdb_arch_name
= x86_gdb_arch_name
;
7681 #ifdef TARGET_X86_64
7682 cc
->gdb_core_xml_file
= "i386-64bit.xml";
7683 cc
->gdb_num_core_regs
= 66;
7685 cc
->gdb_core_xml_file
= "i386-32bit.xml";
7686 cc
->gdb_num_core_regs
= 50;
7688 cc
->disas_set_info
= x86_disas_set_info
;
7690 dc
->user_creatable
= true;
7692 object_class_property_add(oc
, "family", "int",
7693 x86_cpuid_version_get_family
,
7694 x86_cpuid_version_set_family
, NULL
, NULL
);
7695 object_class_property_add(oc
, "model", "int",
7696 x86_cpuid_version_get_model
,
7697 x86_cpuid_version_set_model
, NULL
, NULL
);
7698 object_class_property_add(oc
, "stepping", "int",
7699 x86_cpuid_version_get_stepping
,
7700 x86_cpuid_version_set_stepping
, NULL
, NULL
);
7701 object_class_property_add_str(oc
, "vendor",
7702 x86_cpuid_get_vendor
,
7703 x86_cpuid_set_vendor
);
7704 object_class_property_add_str(oc
, "model-id",
7705 x86_cpuid_get_model_id
,
7706 x86_cpuid_set_model_id
);
7707 object_class_property_add(oc
, "tsc-frequency", "int",
7708 x86_cpuid_get_tsc_freq
,
7709 x86_cpuid_set_tsc_freq
, NULL
, NULL
);
7711 * The "unavailable-features" property has the same semantics as
7712 * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
7713 * QMP command: they list the features that would have prevented the
7714 * CPU from running if the "enforce" flag was set.
7716 object_class_property_add(oc
, "unavailable-features", "strList",
7717 x86_cpu_get_unavailable_features
,
7720 #if !defined(CONFIG_USER_ONLY)
7721 object_class_property_add(oc
, "crash-information", "GuestPanicInformation",
7722 x86_cpu_get_crash_info_qom
, NULL
, NULL
, NULL
);
7725 for (w
= 0; w
< FEATURE_WORDS
; w
++) {
7727 for (bitnr
= 0; bitnr
< 64; bitnr
++) {
7728 x86_cpu_register_feature_bit_props(xcc
, w
, bitnr
);
7733 static const TypeInfo x86_cpu_type_info
= {
7734 .name
= TYPE_X86_CPU
,
7736 .instance_size
= sizeof(X86CPU
),
7737 .instance_init
= x86_cpu_initfn
,
7738 .instance_post_init
= x86_cpu_post_initfn
,
7741 .class_size
= sizeof(X86CPUClass
),
7742 .class_init
= x86_cpu_common_class_init
,
7745 /* "base" CPU model, used by query-cpu-model-expansion */
7746 static void x86_cpu_base_class_init(ObjectClass
*oc
, void *data
)
7748 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
7750 xcc
->static_model
= true;
7751 xcc
->migration_safe
= true;
7752 xcc
->model_description
= "base CPU model type with no features enabled";
7756 static const TypeInfo x86_base_cpu_type_info
= {
7757 .name
= X86_CPU_TYPE_NAME("base"),
7758 .parent
= TYPE_X86_CPU
,
7759 .class_init
= x86_cpu_base_class_init
,
7762 static void x86_cpu_register_types(void)
7766 type_register_static(&x86_cpu_type_info
);
7767 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); i
++) {
7768 x86_register_cpudef_types(&builtin_x86_defs
[i
]);
7770 type_register_static(&max_x86_cpu_type_info
);
7771 type_register_static(&x86_base_cpu_type_info
);
7774 type_init(x86_cpu_register_types
)